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authorOlof Johansson <olof@lixom.net>2012-10-17 20:09:37 -0400
committerOlof Johansson <olof@lixom.net>2012-10-17 20:09:37 -0400
commit327f81c4558dac2138a6339069988d3baa5a152d (patch)
treea7f0a5e461c3299aacf7b04d4a8358e6e20ec189 /arch/arm
parentb5beb20d03c89a1ea7cb208c445546f2c62225e4 (diff)
parenta458926e16a37ef41a4fbf45957cb9faaeb6a6ef (diff)
Merge tag 'mvebu_dove_late_fixes_for_v3.7' of git://git.infradead.org/users/jcooper/linux into fixes
From Jason Cooper: Misc. fixes for latest changes to mach-dove/ Fixes build breakage for mach-dove * tag 'mvebu_dove_late_fixes_for_v3.7' of git://git.infradead.org/users/jcooper/linux: ARM: dove: Add crypto engine to DT ARM: dove: Remove watchdog from DT ARM: dove: Restructure SoC device tree descriptor ARM: dove: Fix clock names of sata and gbe ARM: dove: Fix tauros2 device tree init ARM: dove: Add pcie clock support
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/dove.dtsi49
-rw-r--r--arch/arm/mach-dove/common.c8
-rw-r--r--arch/arm/mach-dove/pcie.c5
3 files changed, 41 insertions, 21 deletions
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 96fb824b5e6e..5a00022383e7 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -4,21 +4,32 @@
4 compatible = "marvell,dove"; 4 compatible = "marvell,dove";
5 model = "Marvell Armada 88AP510 SoC"; 5 model = "Marvell Armada 88AP510 SoC";
6 6
7 interrupt-parent = <&intc>; 7 soc@f1000000 {
8
9 intc: interrupt-controller {
10 compatible = "marvell,orion-intc";
11 interrupt-controller;
12 #interrupt-cells = <1>;
13 reg = <0xf1020204 0x04>,
14 <0xf1020214 0x04>;
15 };
16
17 mbus@f1000000 {
18 compatible = "simple-bus"; 8 compatible = "simple-bus";
19 ranges = <0 0xf1000000 0x4000000>;
20 #address-cells = <1>; 9 #address-cells = <1>;
21 #size-cells = <1>; 10 #size-cells = <1>;
11 interrupt-parent = <&intc>;
12
13 ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
14 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
15 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
16 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
17 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
18 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
19 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
20 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
21
22 l2: l2-cache {
23 compatible = "marvell,tauros2-cache";
24 marvell,tauros2-cache-features = <0>;
25 };
26
27 intc: interrupt-controller {
28 compatible = "marvell,orion-intc";
29 interrupt-controller;
30 #interrupt-cells = <1>;
31 reg = <0x20204 0x04>, <0x20214 0x04>;
32 };
22 33
23 uart0: serial@12000 { 34 uart0: serial@12000 {
24 compatible = "ns16550a"; 35 compatible = "ns16550a";
@@ -56,11 +67,6 @@
56 status = "disabled"; 67 status = "disabled";
57 }; 68 };
58 69
59 wdt: wdt@20300 {
60 compatible = "marvell,orion-wdt";
61 reg = <0x20300 0x28>;
62 };
63
64 gpio0: gpio@d0400 { 70 gpio0: gpio@d0400 {
65 compatible = "marvell,orion-gpio"; 71 compatible = "marvell,orion-gpio";
66 #gpio-cells = <2>; 72 #gpio-cells = <2>;
@@ -139,5 +145,14 @@
139 nr-ports = <1>; 145 nr-ports = <1>;
140 status = "disabled"; 146 status = "disabled";
141 }; 147 };
148
149 crypto: crypto@30000 {
150 compatible = "marvell,orion-crypto";
151 reg = <0x30000 0x10000>,
152 <0xc8000000 0x800>;
153 reg-names = "regs", "sram";
154 interrupts = <31>;
155 status = "okay";
156 };
142 }; 157 };
143}; 158};
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index b37bef1d5ffa..f723fe13d0f0 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -32,6 +32,7 @@
32#include <linux/irq.h> 32#include <linux/irq.h>
33#include <plat/time.h> 33#include <plat/time.h>
34#include <linux/platform_data/usb-ehci-orion.h> 34#include <linux/platform_data/usb-ehci-orion.h>
35#include <plat/irq.h>
35#include <plat/common.h> 36#include <plat/common.h>
36#include <plat/addr-map.h> 37#include <plat/addr-map.h>
37#include "common.h" 38#include "common.h"
@@ -109,8 +110,8 @@ static void __init dove_clk_init(void)
109 110
110 orion_clkdev_add(NULL, "orion-ehci.0", usb0); 111 orion_clkdev_add(NULL, "orion-ehci.0", usb0);
111 orion_clkdev_add(NULL, "orion-ehci.1", usb1); 112 orion_clkdev_add(NULL, "orion-ehci.1", usb1);
112 orion_clkdev_add(NULL, "mv643xx_eth.0", ge); 113 orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
113 orion_clkdev_add("0", "sata_mv.0", sata); 114 orion_clkdev_add(NULL, "sata_mv.0", sata);
114 orion_clkdev_add("0", "pcie", pex0); 115 orion_clkdev_add("0", "pcie", pex0);
115 orion_clkdev_add("1", "pcie", pex1); 116 orion_clkdev_add("1", "pcie", pex1);
116 orion_clkdev_add(NULL, "sdhci-dove.0", sdio0); 117 orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
@@ -399,7 +400,7 @@ static void __init dove_dt_init(void)
399 (dove_tclk + 499999) / 1000000); 400 (dove_tclk + 499999) / 1000000);
400 401
401#ifdef CONFIG_CACHE_TAUROS2 402#ifdef CONFIG_CACHE_TAUROS2
402 tauros2_init(); 403 tauros2_init(0);
403#endif 404#endif
404 dove_setup_cpu_mbus(); 405 dove_setup_cpu_mbus();
405 406
@@ -415,7 +416,6 @@ static void __init dove_dt_init(void)
415 dove_ehci0_init(); 416 dove_ehci0_init();
416 dove_ehci1_init(); 417 dove_ehci1_init();
417 dove_pcie_init(1, 1); 418 dove_pcie_init(1, 1);
418 dove_crypto_init();
419 419
420 of_platform_populate(NULL, of_default_bus_match_table, 420 of_platform_populate(NULL, of_default_bus_match_table,
421 dove_auxdata_lookup, NULL); 421 dove_auxdata_lookup, NULL);
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index bb15b26041cb..0ef4435b1657 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -10,6 +10,7 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/clk.h>
13#include <video/vga.h> 14#include <video/vga.h>
14#include <asm/mach/pci.h> 15#include <asm/mach/pci.h>
15#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
@@ -188,6 +189,10 @@ static void __init add_pcie_port(int index, void __iomem *base)
188 189
189 if (orion_pcie_link_up(base)) { 190 if (orion_pcie_link_up(base)) {
190 struct pcie_port *pp = &pcie_port[num_pcie_ports++]; 191 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
192 struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));
193
194 if (!IS_ERR(clk))
195 clk_prepare_enable(clk);
191 196
192 printk(KERN_INFO "link up\n"); 197 printk(KERN_INFO "link up\n");
193 198