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authorKrzysztof Helt <krzysztof.h1@wp.pl>2007-10-16 04:28:58 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-16 12:43:16 -0400
commitf28ef573ad09596b771b67c276bbc5f49281fa9d (patch)
tree5061be2ae82f513a8c23e220b8a97f30b08ec34a /arch/arm
parent9939a481cd66a109e4ad09328df1bd0540e0aa84 (diff)
s3c2410fb: remove lcdcon3 register from s3c2410fb_display
This patch removes unused lcdcon3 register from the s3c2410fb_display structure. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-s3c2410/mach-amlm5900.c11
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c99
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c36
-rw-r--r--arch/arm/mach-s3c2410/mach-qt2410.c111
-rw-r--r--arch/arm/mach-s3c2440/mach-rx3715.c36
-rw-r--r--arch/arm/mach-s3c2440/mach-smdk2440.c34
6 files changed, 129 insertions, 198 deletions
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index e96b413a114d..74801ce022c1 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -180,13 +180,10 @@ static struct s3c2410fb_display __initdata amlm5900_lcd_info = {
180 .left_margin = 1 << (4 + 3), 180 .left_margin = 1 << (4 + 3),
181 .right_margin = 8 << 3, 181 .right_margin = 8 << 3,
182 182
183 .regs = { 183 .lcdcon1 = 0x00008225,
184 .lcdcon1 = 0x00008225, 184 .lcdcon2 = 0x0027c000,
185 .lcdcon2 = 0x0027c000, 185 .lcdcon4 = 0x00000002,
186 .lcdcon3 = 0x00182708, 186 .lcdcon5 = 0x00000001,
187 .lcdcon4 = 0x00000002,
188 .lcdcon5 = 0x00000001,
189 }
190}; 187};
191 188
192static struct s3c2410fb_mach_info __initdata amlm5900_fb_info = { 189static struct s3c2410fb_mach_info __initdata amlm5900_fb_info = {
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 1b4f9f922c8a..6e46c20b648c 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -479,13 +479,10 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
479 479
480 .bpp = 4, 480 .bpp = 4,
481 481
482 .regs = { 482 .lcdcon1 = 0x00000176,
483 .lcdcon1 = 0x00000176, 483 .lcdcon2 = 0x1d77c7c2,
484 .lcdcon2 = 0x1d77c7c2, 484 .lcdcon4 = 0x00000057,
485 .lcdcon3 = 0x013a7f13, 485 .lcdcon5 = 0x00014b02,
486 .lcdcon4 = 0x00000057,
487 .lcdcon5 = 0x00014b02,
488 }
489 }, 486 },
490 { 487 {
491 .type = S3C2410_LCDCON1_TFT, 488 .type = S3C2410_LCDCON1_TFT,
@@ -498,13 +495,10 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
498 .left_margin = 40, 495 .left_margin = 40,
499 .right_margin = 20, 496 .right_margin = 20,
500 497
501 .regs = { 498 .lcdcon1 = 0x00000176,
502 .lcdcon1 = 0x00000176, 499 .lcdcon2 = 0x1d77c7c2,
503 .lcdcon2 = 0x1d77c7c2, 500 .lcdcon4 = 0x00000057,
504 .lcdcon3 = 0x013a7f13, 501 .lcdcon5 = 0x00014b02,
505 .lcdcon4 = 0x00000057,
506 .lcdcon5 = 0x00014b02,
507 }
508 }, 502 },
509 { 503 {
510 .type = S3C2410_LCDCON1_TFT, 504 .type = S3C2410_LCDCON1_TFT,
@@ -517,13 +511,10 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
517 .left_margin = 40, 511 .left_margin = 40,
518 .right_margin = 20, 512 .right_margin = 20,
519 513
520 .regs = { 514 .lcdcon1 = 0x00000176,
521 .lcdcon1 = 0x00000176, 515 .lcdcon2 = 0x1d77c7c2,
522 .lcdcon2 = 0x1d77c7c2, 516 .lcdcon4 = 0x00000057,
523 .lcdcon3 = 0x013a7f13, 517 .lcdcon5 = 0x00014b02,
524 .lcdcon4 = 0x00000057,
525 .lcdcon5 = 0x00014b02,
526 }
527 }, 518 },
528 { 519 {
529 .type = S3C2410_LCDCON1_TFT, 520 .type = S3C2410_LCDCON1_TFT,
@@ -536,13 +527,10 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
536 .left_margin = 40, 527 .left_margin = 40,
537 .right_margin = 20, 528 .right_margin = 20,
538 529
539 .regs = { 530 .lcdcon1 = 0x00000176,
540 .lcdcon1 = 0x00000176, 531 .lcdcon2 = 0x1d77c7c2,
541 .lcdcon2 = 0x1d77c7c2, 532 .lcdcon4 = 0x00000057,
542 .lcdcon3 = 0x013a7f13, 533 .lcdcon5 = 0x00014b02,
543 .lcdcon4 = 0x00000057,
544 .lcdcon5 = 0x00014b02,
545 }
546 }, 534 },
547 { 535 {
548 .type = S3C2410_LCDCON1_TFT, 536 .type = S3C2410_LCDCON1_TFT,
@@ -555,13 +543,10 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
555 .left_margin = 40, 543 .left_margin = 40,
556 .right_margin = 20, 544 .right_margin = 20,
557 545
558 .regs = { 546 .lcdcon1 = 0x00000176,
559 .lcdcon1 = 0x00000176, 547 .lcdcon2 = 0x1d77c7c2,
560 .lcdcon2 = 0x1d77c7c2, 548 .lcdcon4 = 0x00000057,
561 .lcdcon3 = 0x013a7f13, 549 .lcdcon5 = 0x00014b02,
562 .lcdcon4 = 0x00000057,
563 .lcdcon5 = 0x00014b02,
564 }
565 }, 550 },
566 { 551 {
567 .type = S3C2410_LCDCON1_TFT, 552 .type = S3C2410_LCDCON1_TFT,
@@ -574,13 +559,10 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
574 .left_margin = 40, 559 .left_margin = 40,
575 .right_margin = 20, 560 .right_margin = 20,
576 561
577 .regs = { 562 .lcdcon1 = 0x00000176,
578 .lcdcon1 = 0x00000176, 563 .lcdcon2 = 0x1d77c7c2,
579 .lcdcon2 = 0x1d77c7c2, 564 .lcdcon4 = 0x00000057,
580 .lcdcon3 = 0x013a7f13, 565 .lcdcon5 = 0x00014b02,
581 .lcdcon4 = 0x00000057,
582 .lcdcon5 = 0x00014b02,
583 }
584 }, 566 },
585 { 567 {
586 .type = S3C2410_LCDCON1_TFT, 568 .type = S3C2410_LCDCON1_TFT,
@@ -593,13 +575,10 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
593 .left_margin = 40, 575 .left_margin = 40,
594 .right_margin = 20, 576 .right_margin = 20,
595 577
596 .regs = { 578 .lcdcon1 = 0x00000176,
597 .lcdcon1 = 0x00000176, 579 .lcdcon2 = 0x1d77c7c2,
598 .lcdcon2 = 0x1d77c7c2, 580 .lcdcon4 = 0x00000057,
599 .lcdcon3 = 0x013a7f13, 581 .lcdcon5 = 0x00014b02,
600 .lcdcon4 = 0x00000057,
601 .lcdcon5 = 0x00014b02,
602 }
603 }, 582 },
604 { 583 {
605 .type = S3C2410_LCDCON1_TFT, 584 .type = S3C2410_LCDCON1_TFT,
@@ -612,13 +591,10 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
612 .left_margin = 40, 591 .left_margin = 40,
613 .right_margin = 20, 592 .right_margin = 20,
614 593
615 .regs = { 594 .lcdcon1 = 0x00000176,
616 .lcdcon1 = 0x00000176, 595 .lcdcon2 = 0x1d77c7c2,
617 .lcdcon2 = 0x1d77c7c2, 596 .lcdcon4 = 0x00000057,
618 .lcdcon3 = 0x013a7f13, 597 .lcdcon5 = 0x00014b02,
619 .lcdcon4 = 0x00000057,
620 .lcdcon5 = 0x00014b02,
621 }
622 }, 598 },
623 { 599 {
624 .type = S3C2410_LCDCON1_TFT, 600 .type = S3C2410_LCDCON1_TFT,
@@ -631,13 +607,10 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
631 .left_margin = 40, 607 .left_margin = 40,
632 .right_margin = 20, 608 .right_margin = 20,
633 609
634 .regs = { 610 .lcdcon1 = 0x00000176,
635 .lcdcon1 = 0x00000176, 611 .lcdcon2 = 0x1d77c7c2,
636 .lcdcon2 = 0x1d77c7c2, 612 .lcdcon4 = 0x00000057,
637 .lcdcon3 = 0x013a7f13, 613 .lcdcon5 = 0x00014b02,
638 .lcdcon4 = 0x00000057,
639 .lcdcon5 = 0x00014b02,
640 }
641 }, 614 },
642}; 615};
643 616
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 372caa289f2b..52d7685180c4 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -134,27 +134,21 @@ static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = {
134 * Set lcd on or off 134 * Set lcd on or off
135 **/ 135 **/
136static struct s3c2410fb_display h1940_lcd __initdata = { 136static struct s3c2410fb_display h1940_lcd __initdata = {
137 .regs={ 137 .lcdcon1= S3C2410_LCDCON1_TFT16BPP | \
138 .lcdcon1= S3C2410_LCDCON1_TFT16BPP | \ 138 S3C2410_LCDCON1_TFT | \
139 S3C2410_LCDCON1_TFT | \ 139 S3C2410_LCDCON1_CLKVAL(0x0C),
140 S3C2410_LCDCON1_CLKVAL(0x0C), 140
141 141 .lcdcon2= S3C2410_LCDCON2_VBPD(7) | \
142 .lcdcon2= S3C2410_LCDCON2_VBPD(7) | \ 142 S3C2410_LCDCON2_LINEVAL(319) | \
143 S3C2410_LCDCON2_LINEVAL(319) | \ 143 S3C2410_LCDCON2_VFPD(6) | \
144 S3C2410_LCDCON2_VFPD(6) | \ 144 S3C2410_LCDCON2_VSPW(0),
145 S3C2410_LCDCON2_VSPW(0), 145
146 146 .lcdcon4= S3C2410_LCDCON4_MVAL(0) | \
147 .lcdcon3= S3C2410_LCDCON3_HBPD(19) | \ 147 S3C2410_LCDCON4_HSPW(3),
148 S3C2410_LCDCON3_HOZVAL(239) | \ 148
149 S3C2410_LCDCON3_HFPD(7), 149 .lcdcon5= S3C2410_LCDCON5_FRM565 | \
150 150 S3C2410_LCDCON5_INVVLINE | \
151 .lcdcon4= S3C2410_LCDCON4_MVAL(0) | \ 151 S3C2410_LCDCON5_HWSWP,
152 S3C2410_LCDCON4_HSPW(3),
153
154 .lcdcon5= S3C2410_LCDCON5_FRM565 | \
155 S3C2410_LCDCON5_INVVLINE | \
156 S3C2410_LCDCON5_HWSWP,
157 },
158 152
159 .type = S3C2410_LCDCON1_TFT, 153 .type = S3C2410_LCDCON1_TFT,
160 .width = 240, 154 .width = 240,
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 0c1ff0a41a99..0a746f7f639f 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -98,30 +98,23 @@ static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
98static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = { 98static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
99 { 99 {
100 /* Configuration for 640x480 SHARP LQ080V3DG01 */ 100 /* Configuration for 640x480 SHARP LQ080V3DG01 */
101 .regs = { 101 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
102 S3C2410_LCDCON1_TFT |
103 S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
102 104
103 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | 105 .lcdcon2 = S3C2410_LCDCON2_VBPD(18) | /* 19 */
104 S3C2410_LCDCON1_TFT | 106 S3C2410_LCDCON2_LINEVAL(479) |
105 S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */ 107 S3C2410_LCDCON2_VFPD(10) | /* 11 */
108 S3C2410_LCDCON2_VSPW(14), /* 15 */
106 109
107 .lcdcon2 = S3C2410_LCDCON2_VBPD(18) | /* 19 */ 110 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
108 S3C2410_LCDCON2_LINEVAL(479) | 111 S3C2410_LCDCON4_HSPW(95), /* 96 */
109 S3C2410_LCDCON2_VFPD(10) | /* 11 */
110 S3C2410_LCDCON2_VSPW(14), /* 15 */
111 112
112 .lcdcon3 = S3C2410_LCDCON3_HBPD(43) | /* 44 */ 113 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
113 S3C2410_LCDCON3_HOZVAL(639) | /* 640 */ 114 S3C2410_LCDCON5_INVVLINE |
114 S3C2410_LCDCON3_HFPD(115), /* 116 */ 115 S3C2410_LCDCON5_INVVFRAME |
115 116 S3C2410_LCDCON5_PWREN |
116 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | 117 S3C2410_LCDCON5_HWSWP,
117 S3C2410_LCDCON4_HSPW(95), /* 96 */
118
119 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
120 S3C2410_LCDCON5_INVVLINE |
121 S3C2410_LCDCON5_INVVFRAME |
122 S3C2410_LCDCON5_PWREN |
123 S3C2410_LCDCON5_HWSWP,
124 },
125 118
126 .type = S3C2410_LCDCON1_TFT, 119 .type = S3C2410_LCDCON1_TFT,
127 .width = 640, 120 .width = 640,
@@ -135,30 +128,23 @@ static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
135 }, 128 },
136 { 129 {
137 /* Configuration for 480x640 toppoly TD028TTEC1 */ 130 /* Configuration for 480x640 toppoly TD028TTEC1 */
138 .regs = { 131 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
139 132 S3C2410_LCDCON1_TFT |
140 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | 133 S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
141 S3C2410_LCDCON1_TFT |
142 S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
143
144 .lcdcon2 = S3C2410_LCDCON2_VBPD(1) | /* 2 */
145 S3C2410_LCDCON2_LINEVAL(639) |/* 640 */
146 S3C2410_LCDCON2_VFPD(3) | /* 4 */
147 S3C2410_LCDCON2_VSPW(1), /* 2 */
148 134
149 .lcdcon3 = S3C2410_LCDCON3_HBPD(7) | /* 8 */ 135 .lcdcon2 = S3C2410_LCDCON2_VBPD(1) | /* 2 */
150 S3C2410_LCDCON3_HOZVAL(479) | /* 479 */ 136 S3C2410_LCDCON2_LINEVAL(639) |/* 640 */
151 S3C2410_LCDCON3_HFPD(23), /* 24 */ 137 S3C2410_LCDCON2_VFPD(3) | /* 4 */
138 S3C2410_LCDCON2_VSPW(1), /* 2 */
152 139
153 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | 140 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
154 S3C2410_LCDCON4_HSPW(7), /* 8 */ 141 S3C2410_LCDCON4_HSPW(7), /* 8 */
155 142
156 .lcdcon5 = S3C2410_LCDCON5_FRM565 | 143 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
157 S3C2410_LCDCON5_INVVLINE | 144 S3C2410_LCDCON5_INVVLINE |
158 S3C2410_LCDCON5_INVVFRAME | 145 S3C2410_LCDCON5_INVVFRAME |
159 S3C2410_LCDCON5_PWREN | 146 S3C2410_LCDCON5_PWREN |
160 S3C2410_LCDCON5_HWSWP, 147 S3C2410_LCDCON5_HWSWP,
161 },
162 148
163 .type = S3C2410_LCDCON1_TFT, 149 .type = S3C2410_LCDCON1_TFT,
164 .width = 480, 150 .width = 480,
@@ -171,30 +157,23 @@ static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
171 }, 157 },
172 { 158 {
173 /* Config for 240x320 LCD */ 159 /* Config for 240x320 LCD */
174 .regs = { 160 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
175 161 S3C2410_LCDCON1_TFT |
176 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | 162 S3C2410_LCDCON1_CLKVAL(0x04),
177 S3C2410_LCDCON1_TFT | 163
178 S3C2410_LCDCON1_CLKVAL(0x04), 164 .lcdcon2 = S3C2410_LCDCON2_VBPD(1) |
179 165 S3C2410_LCDCON2_LINEVAL(319) |
180 .lcdcon2 = S3C2410_LCDCON2_VBPD(1) | 166 S3C2410_LCDCON2_VFPD(6) |
181 S3C2410_LCDCON2_LINEVAL(319) | 167 S3C2410_LCDCON2_VSPW(3),
182 S3C2410_LCDCON2_VFPD(6) | 168
183 S3C2410_LCDCON2_VSPW(3), 169 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
184 170 S3C2410_LCDCON4_HSPW(3),
185 .lcdcon3 = S3C2410_LCDCON3_HBPD(12) | 171
186 S3C2410_LCDCON3_HOZVAL(239) | 172 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
187 S3C2410_LCDCON3_HFPD(7), 173 S3C2410_LCDCON5_INVVLINE |
188 174 S3C2410_LCDCON5_INVVFRAME |
189 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | 175 S3C2410_LCDCON5_PWREN |
190 S3C2410_LCDCON4_HSPW(3), 176 S3C2410_LCDCON5_HWSWP,
191
192 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
193 S3C2410_LCDCON5_INVVLINE |
194 S3C2410_LCDCON5_INVVFRAME |
195 S3C2410_LCDCON5_PWREN |
196 S3C2410_LCDCON5_HWSWP,
197 },
198 177
199 .type = S3C2410_LCDCON1_TFT, 178 .type = S3C2410_LCDCON1_TFT,
200 .width = 240, 179 .width = 240,
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index dab8e7b474d8..305827242bec 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -111,27 +111,21 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
111/* framebuffer lcd controller information */ 111/* framebuffer lcd controller information */
112 112
113static struct s3c2410fb_display rx3715_lcdcfg __initdata = { 113static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
114 .regs = { 114 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | \
115 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | \ 115 S3C2410_LCDCON1_TFT | \
116 S3C2410_LCDCON1_TFT | \ 116 S3C2410_LCDCON1_CLKVAL(0x0C),
117 S3C2410_LCDCON1_CLKVAL(0x0C), 117
118 118 .lcdcon2 = S3C2410_LCDCON2_VBPD(5) | \
119 .lcdcon2 = S3C2410_LCDCON2_VBPD(5) | \ 119 S3C2410_LCDCON2_LINEVAL(319) | \
120 S3C2410_LCDCON2_LINEVAL(319) | \ 120 S3C2410_LCDCON2_VFPD(6) | \
121 S3C2410_LCDCON2_VFPD(6) | \ 121 S3C2410_LCDCON2_VSPW(2),
122 S3C2410_LCDCON2_VSPW(2), 122
123 123 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | \
124 .lcdcon3 = S3C2410_LCDCON3_HBPD(35) | \ 124 S3C2410_LCDCON4_HSPW(7),
125 S3C2410_LCDCON3_HOZVAL(239) | \ 125
126 S3C2410_LCDCON3_HFPD(35), 126 .lcdcon5 = S3C2410_LCDCON5_INVVLINE |
127 127 S3C2410_LCDCON5_FRM565 |
128 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | \ 128 S3C2410_LCDCON5_HWSWP,
129 S3C2410_LCDCON4_HSPW(7),
130
131 .lcdcon5 = S3C2410_LCDCON5_INVVLINE |
132 S3C2410_LCDCON5_FRM565 |
133 S3C2410_LCDCON5_HWSWP,
134 },
135 129
136 .type = S3C2410_LCDCON1_TFT, 130 .type = S3C2410_LCDCON1_TFT,
137 .width = 240, 131 .width = 240,
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index 5930f1708027..33b364476c18 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -104,30 +104,24 @@ static struct s3c2410_uartcfg smdk2440_uartcfgs[] __initdata = {
104/* LCD driver info */ 104/* LCD driver info */
105 105
106static struct s3c2410fb_display smdk2440_lcd_cfg __initdata = { 106static struct s3c2410fb_display smdk2440_lcd_cfg __initdata = {
107 .regs = {
108 107
109 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | 108 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
110 S3C2410_LCDCON1_TFT | 109 S3C2410_LCDCON1_TFT |
111 S3C2410_LCDCON1_CLKVAL(0x04), 110 S3C2410_LCDCON1_CLKVAL(0x04),
112 111
113 .lcdcon2 = S3C2410_LCDCON2_VBPD(7) | 112 .lcdcon2 = S3C2410_LCDCON2_VBPD(7) |
114 S3C2410_LCDCON2_LINEVAL(319) | 113 S3C2410_LCDCON2_LINEVAL(319) |
115 S3C2410_LCDCON2_VFPD(6) | 114 S3C2410_LCDCON2_VFPD(6) |
116 S3C2410_LCDCON2_VSPW(3), 115 S3C2410_LCDCON2_VSPW(3),
117 116
118 .lcdcon3 = S3C2410_LCDCON3_HBPD(19) | 117 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
119 S3C2410_LCDCON3_HOZVAL(239) | 118 S3C2410_LCDCON4_HSPW(3),
120 S3C2410_LCDCON3_HFPD(7),
121 119
122 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | 120 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
123 S3C2410_LCDCON4_HSPW(3), 121 S3C2410_LCDCON5_INVVLINE |
124 122 S3C2410_LCDCON5_INVVFRAME |
125 .lcdcon5 = S3C2410_LCDCON5_FRM565 | 123 S3C2410_LCDCON5_PWREN |
126 S3C2410_LCDCON5_INVVLINE | 124 S3C2410_LCDCON5_HWSWP,
127 S3C2410_LCDCON5_INVVFRAME |
128 S3C2410_LCDCON5_PWREN |
129 S3C2410_LCDCON5_HWSWP,
130 },
131 125
132 .type = S3C2410_LCDCON1_TFT16BPP, 126 .type = S3C2410_LCDCON1_TFT16BPP,
133 127
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 16:11:24 -0500