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authorAndrew Lunn <andrew@lunn.ch>2011-05-15 07:32:48 -0400
committerNicolas Pitre <nico@fluxnic.net>2011-05-16 15:10:50 -0400
commitee9627234dae8d1b8059b2ac39c961ee0932b803 (patch)
tree1a2dfea66908b45439d322729cb6e34a59330682 /arch/arm
parent5e00d3783dd362a34c9816bb582103c9833e4643 (diff)
ARM: orion: Consolidate the XOR platform setup code.
Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-dove/common.c197
-rw-r--r--arch/arm/mach-kirkwood/common.c195
-rw-r--r--arch/arm/mach-orion5x/common.c102
-rw-r--r--arch/arm/plat-orion/common.c215
-rw-r--r--arch/arm/plat-orion/include/plat/common.h11
5 files changed, 242 insertions, 478 deletions
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e3e043c0004c..6703bf3120b6 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -30,7 +30,6 @@
30#include <mach/bridge-regs.h> 30#include <mach/bridge-regs.h>
31#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
32#include <linux/irq.h> 32#include <linux/irq.h>
33#include <plat/mv_xor.h>
34#include <plat/ehci-orion.h> 33#include <plat/ehci-orion.h>
35#include <plat/time.h> 34#include <plat/time.h>
36#include <plat/common.h> 35#include <plat/common.h>
@@ -278,208 +277,22 @@ struct sys_timer dove_timer = {
278}; 277};
279 278
280/***************************************************************************** 279/*****************************************************************************
281 * XOR
282 ****************************************************************************/
283static struct mv_xor_platform_shared_data dove_xor_shared_data = {
284 .dram = &dove_mbus_dram_info,
285};
286
287/*****************************************************************************
288 * XOR 0 280 * XOR 0
289 ****************************************************************************/ 281 ****************************************************************************/
290static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
291
292static struct resource dove_xor0_shared_resources[] = {
293 {
294 .name = "xor 0 low",
295 .start = DOVE_XOR0_PHYS_BASE,
296 .end = DOVE_XOR0_PHYS_BASE + 0xff,
297 .flags = IORESOURCE_MEM,
298 }, {
299 .name = "xor 0 high",
300 .start = DOVE_XOR0_HIGH_PHYS_BASE,
301 .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
302 .flags = IORESOURCE_MEM,
303 },
304};
305
306static struct platform_device dove_xor0_shared = {
307 .name = MV_XOR_SHARED_NAME,
308 .id = 0,
309 .dev = {
310 .platform_data = &dove_xor_shared_data,
311 },
312 .num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
313 .resource = dove_xor0_shared_resources,
314};
315
316static struct resource dove_xor00_resources[] = {
317 [0] = {
318 .start = IRQ_DOVE_XOR_00,
319 .end = IRQ_DOVE_XOR_00,
320 .flags = IORESOURCE_IRQ,
321 },
322};
323
324static struct mv_xor_platform_data dove_xor00_data = {
325 .shared = &dove_xor0_shared,
326 .hw_id = 0,
327 .pool_size = PAGE_SIZE,
328};
329
330static struct platform_device dove_xor00_channel = {
331 .name = MV_XOR_NAME,
332 .id = 0,
333 .num_resources = ARRAY_SIZE(dove_xor00_resources),
334 .resource = dove_xor00_resources,
335 .dev = {
336 .dma_mask = &dove_xor0_dmamask,
337 .coherent_dma_mask = DMA_BIT_MASK(64),
338 .platform_data = &dove_xor00_data,
339 },
340};
341
342static struct resource dove_xor01_resources[] = {
343 [0] = {
344 .start = IRQ_DOVE_XOR_01,
345 .end = IRQ_DOVE_XOR_01,
346 .flags = IORESOURCE_IRQ,
347 },
348};
349
350static struct mv_xor_platform_data dove_xor01_data = {
351 .shared = &dove_xor0_shared,
352 .hw_id = 1,
353 .pool_size = PAGE_SIZE,
354};
355
356static struct platform_device dove_xor01_channel = {
357 .name = MV_XOR_NAME,
358 .id = 1,
359 .num_resources = ARRAY_SIZE(dove_xor01_resources),
360 .resource = dove_xor01_resources,
361 .dev = {
362 .dma_mask = &dove_xor0_dmamask,
363 .coherent_dma_mask = DMA_BIT_MASK(64),
364 .platform_data = &dove_xor01_data,
365 },
366};
367
368void __init dove_xor0_init(void) 282void __init dove_xor0_init(void)
369{ 283{
370 platform_device_register(&dove_xor0_shared); 284 orion_xor0_init(&dove_mbus_dram_info,
371 285 DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
372 /* 286 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
373 * two engines can't do memset simultaneously, this limitation
374 * satisfied by removing memset support from one of the engines.
375 */
376 dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
377 dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
378 platform_device_register(&dove_xor00_channel);
379
380 dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
381 dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
382 dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
383 platform_device_register(&dove_xor01_channel);
384} 287}
385 288
386/***************************************************************************** 289/*****************************************************************************
387 * XOR 1 290 * XOR 1
388 ****************************************************************************/ 291 ****************************************************************************/
389static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
390
391static struct resource dove_xor1_shared_resources[] = {
392 {
393 .name = "xor 0 low",
394 .start = DOVE_XOR1_PHYS_BASE,
395 .end = DOVE_XOR1_PHYS_BASE + 0xff,
396 .flags = IORESOURCE_MEM,
397 }, {
398 .name = "xor 0 high",
399 .start = DOVE_XOR1_HIGH_PHYS_BASE,
400 .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
401 .flags = IORESOURCE_MEM,
402 },
403};
404
405static struct platform_device dove_xor1_shared = {
406 .name = MV_XOR_SHARED_NAME,
407 .id = 1,
408 .dev = {
409 .platform_data = &dove_xor_shared_data,
410 },
411 .num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
412 .resource = dove_xor1_shared_resources,
413};
414
415static struct resource dove_xor10_resources[] = {
416 [0] = {
417 .start = IRQ_DOVE_XOR_10,
418 .end = IRQ_DOVE_XOR_10,
419 .flags = IORESOURCE_IRQ,
420 },
421};
422
423static struct mv_xor_platform_data dove_xor10_data = {
424 .shared = &dove_xor1_shared,
425 .hw_id = 0,
426 .pool_size = PAGE_SIZE,
427};
428
429static struct platform_device dove_xor10_channel = {
430 .name = MV_XOR_NAME,
431 .id = 2,
432 .num_resources = ARRAY_SIZE(dove_xor10_resources),
433 .resource = dove_xor10_resources,
434 .dev = {
435 .dma_mask = &dove_xor1_dmamask,
436 .coherent_dma_mask = DMA_BIT_MASK(64),
437 .platform_data = &dove_xor10_data,
438 },
439};
440
441static struct resource dove_xor11_resources[] = {
442 [0] = {
443 .start = IRQ_DOVE_XOR_11,
444 .end = IRQ_DOVE_XOR_11,
445 .flags = IORESOURCE_IRQ,
446 },
447};
448
449static struct mv_xor_platform_data dove_xor11_data = {
450 .shared = &dove_xor1_shared,
451 .hw_id = 1,
452 .pool_size = PAGE_SIZE,
453};
454
455static struct platform_device dove_xor11_channel = {
456 .name = MV_XOR_NAME,
457 .id = 3,
458 .num_resources = ARRAY_SIZE(dove_xor11_resources),
459 .resource = dove_xor11_resources,
460 .dev = {
461 .dma_mask = &dove_xor1_dmamask,
462 .coherent_dma_mask = DMA_BIT_MASK(64),
463 .platform_data = &dove_xor11_data,
464 },
465};
466
467void __init dove_xor1_init(void) 292void __init dove_xor1_init(void)
468{ 293{
469 platform_device_register(&dove_xor1_shared); 294 orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
470 295 IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
471 /*
472 * two engines can't do memset simultaneously, this limitation
473 * satisfied by removing memset support from one of the engines.
474 */
475 dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
476 dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
477 platform_device_register(&dove_xor10_channel);
478
479 dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
480 dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
481 dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
482 platform_device_register(&dove_xor11_channel);
483} 296}
484 297
485/***************************************************************************** 298/*****************************************************************************
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 08847a6f7d10..7c2b5df4aa1c 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -15,6 +15,7 @@
15#include <linux/mbus.h> 15#include <linux/mbus.h>
16#include <linux/ata_platform.h> 16#include <linux/ata_platform.h>
17#include <linux/mtd/nand.h> 17#include <linux/mtd/nand.h>
18#include <linux/dma-mapping.h>
18#include <net/dsa.h> 19#include <net/dsa.h>
19#include <asm/page.h> 20#include <asm/page.h>
20#include <asm/timex.h> 21#include <asm/timex.h>
@@ -27,7 +28,6 @@
27#include <plat/cache-feroceon-l2.h> 28#include <plat/cache-feroceon-l2.h>
28#include <plat/ehci-orion.h> 29#include <plat/ehci-orion.h>
29#include <plat/mvsdio.h> 30#include <plat/mvsdio.h>
30#include <plat/mv_xor.h>
31#include <plat/orion_nand.h> 31#include <plat/orion_nand.h>
32#include <plat/common.h> 32#include <plat/common.h>
33#include <plat/time.h> 33#include <plat/time.h>
@@ -364,210 +364,27 @@ void __init kirkwood_crypto_init(void)
364 364
365 365
366/***************************************************************************** 366/*****************************************************************************
367 * XOR
368 ****************************************************************************/
369static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
370 .dram = &kirkwood_mbus_dram_info,
371};
372
373
374/*****************************************************************************
375 * XOR0 367 * XOR0
376 ****************************************************************************/ 368 ****************************************************************************/
377static struct resource kirkwood_xor0_shared_resources[] = {
378 {
379 .name = "xor 0 low",
380 .start = XOR0_PHYS_BASE,
381 .end = XOR0_PHYS_BASE + 0xff,
382 .flags = IORESOURCE_MEM,
383 }, {
384 .name = "xor 0 high",
385 .start = XOR0_HIGH_PHYS_BASE,
386 .end = XOR0_HIGH_PHYS_BASE + 0xff,
387 .flags = IORESOURCE_MEM,
388 },
389};
390
391static struct platform_device kirkwood_xor0_shared = {
392 .name = MV_XOR_SHARED_NAME,
393 .id = 0,
394 .dev = {
395 .platform_data = &kirkwood_xor_shared_data,
396 },
397 .num_resources = ARRAY_SIZE(kirkwood_xor0_shared_resources),
398 .resource = kirkwood_xor0_shared_resources,
399};
400
401static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32);
402
403static struct resource kirkwood_xor00_resources[] = {
404 [0] = {
405 .start = IRQ_KIRKWOOD_XOR_00,
406 .end = IRQ_KIRKWOOD_XOR_00,
407 .flags = IORESOURCE_IRQ,
408 },
409};
410
411static struct mv_xor_platform_data kirkwood_xor00_data = {
412 .shared = &kirkwood_xor0_shared,
413 .hw_id = 0,
414 .pool_size = PAGE_SIZE,
415};
416
417static struct platform_device kirkwood_xor00_channel = {
418 .name = MV_XOR_NAME,
419 .id = 0,
420 .num_resources = ARRAY_SIZE(kirkwood_xor00_resources),
421 .resource = kirkwood_xor00_resources,
422 .dev = {
423 .dma_mask = &kirkwood_xor_dmamask,
424 .coherent_dma_mask = DMA_BIT_MASK(64),
425 .platform_data = &kirkwood_xor00_data,
426 },
427};
428
429static struct resource kirkwood_xor01_resources[] = {
430 [0] = {
431 .start = IRQ_KIRKWOOD_XOR_01,
432 .end = IRQ_KIRKWOOD_XOR_01,
433 .flags = IORESOURCE_IRQ,
434 },
435};
436
437static struct mv_xor_platform_data kirkwood_xor01_data = {
438 .shared = &kirkwood_xor0_shared,
439 .hw_id = 1,
440 .pool_size = PAGE_SIZE,
441};
442
443static struct platform_device kirkwood_xor01_channel = {
444 .name = MV_XOR_NAME,
445 .id = 1,
446 .num_resources = ARRAY_SIZE(kirkwood_xor01_resources),
447 .resource = kirkwood_xor01_resources,
448 .dev = {
449 .dma_mask = &kirkwood_xor_dmamask,
450 .coherent_dma_mask = DMA_BIT_MASK(64),
451 .platform_data = &kirkwood_xor01_data,
452 },
453};
454
455static void __init kirkwood_xor0_init(void) 369static void __init kirkwood_xor0_init(void)
456{ 370{
457 kirkwood_clk_ctrl |= CGC_XOR0; 371 kirkwood_clk_ctrl |= CGC_XOR0;
458 platform_device_register(&kirkwood_xor0_shared);
459 372
460 /* 373 orion_xor0_init(&kirkwood_mbus_dram_info,
461 * two engines can't do memset simultaneously, this limitation 374 XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
462 * satisfied by removing memset support from one of the engines. 375 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
463 */
464 dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
465 dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
466 platform_device_register(&kirkwood_xor00_channel);
467
468 dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
469 dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
470 dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
471 platform_device_register(&kirkwood_xor01_channel);
472} 376}
473 377
474 378
475/***************************************************************************** 379/*****************************************************************************
476 * XOR1 380 * XOR1
477 ****************************************************************************/ 381 ****************************************************************************/
478static struct resource kirkwood_xor1_shared_resources[] = {
479 {
480 .name = "xor 1 low",
481 .start = XOR1_PHYS_BASE,
482 .end = XOR1_PHYS_BASE + 0xff,
483 .flags = IORESOURCE_MEM,
484 }, {
485 .name = "xor 1 high",
486 .start = XOR1_HIGH_PHYS_BASE,
487 .end = XOR1_HIGH_PHYS_BASE + 0xff,
488 .flags = IORESOURCE_MEM,
489 },
490};
491
492static struct platform_device kirkwood_xor1_shared = {
493 .name = MV_XOR_SHARED_NAME,
494 .id = 1,
495 .dev = {
496 .platform_data = &kirkwood_xor_shared_data,
497 },
498 .num_resources = ARRAY_SIZE(kirkwood_xor1_shared_resources),
499 .resource = kirkwood_xor1_shared_resources,
500};
501
502static struct resource kirkwood_xor10_resources[] = {
503 [0] = {
504 .start = IRQ_KIRKWOOD_XOR_10,
505 .end = IRQ_KIRKWOOD_XOR_10,
506 .flags = IORESOURCE_IRQ,
507 },
508};
509
510static struct mv_xor_platform_data kirkwood_xor10_data = {
511 .shared = &kirkwood_xor1_shared,
512 .hw_id = 0,
513 .pool_size = PAGE_SIZE,
514};
515
516static struct platform_device kirkwood_xor10_channel = {
517 .name = MV_XOR_NAME,
518 .id = 2,
519 .num_resources = ARRAY_SIZE(kirkwood_xor10_resources),
520 .resource = kirkwood_xor10_resources,
521 .dev = {
522 .dma_mask = &kirkwood_xor_dmamask,
523 .coherent_dma_mask = DMA_BIT_MASK(64),
524 .platform_data = &kirkwood_xor10_data,
525 },
526};
527
528static struct resource kirkwood_xor11_resources[] = {
529 [0] = {
530 .start = IRQ_KIRKWOOD_XOR_11,
531 .end = IRQ_KIRKWOOD_XOR_11,
532 .flags = IORESOURCE_IRQ,
533 },
534};
535
536static struct mv_xor_platform_data kirkwood_xor11_data = {
537 .shared = &kirkwood_xor1_shared,
538 .hw_id = 1,
539 .pool_size = PAGE_SIZE,
540};
541
542static struct platform_device kirkwood_xor11_channel = {
543 .name = MV_XOR_NAME,
544 .id = 3,
545 .num_resources = ARRAY_SIZE(kirkwood_xor11_resources),
546 .resource = kirkwood_xor11_resources,
547 .dev = {
548 .dma_mask = &kirkwood_xor_dmamask,
549 .coherent_dma_mask = DMA_BIT_MASK(64),
550 .platform_data = &kirkwood_xor11_data,
551 },
552};
553
554static void __init kirkwood_xor1_init(void) 382static void __init kirkwood_xor1_init(void)
555{ 383{
556 kirkwood_clk_ctrl |= CGC_XOR1; 384 kirkwood_clk_ctrl |= CGC_XOR1;
557 platform_device_register(&kirkwood_xor1_shared);
558 385
559 /* 386 orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
560 * two engines can't do memset simultaneously, this limitation 387 IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
561 * satisfied by removing memset support from one of the engines.
562 */
563 dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
564 dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
565 platform_device_register(&kirkwood_xor10_channel);
566
567 dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
568 dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
569 dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
570 platform_device_register(&kirkwood_xor11_channel);
571} 388}
572 389
573 390
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index c26e6dbe489b..5c7e39164c5e 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -13,6 +13,7 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
16#include <linux/serial_8250.h> 17#include <linux/serial_8250.h>
17#include <linux/mbus.h> 18#include <linux/mbus.h>
18#include <linux/mv643xx_i2c.h> 19#include <linux/mv643xx_i2c.h>
@@ -28,7 +29,6 @@
28#include <mach/hardware.h> 29#include <mach/hardware.h>
29#include <mach/orion5x.h> 30#include <mach/orion5x.h>
30#include <plat/ehci-orion.h> 31#include <plat/ehci-orion.h>
31#include <plat/mv_xor.h>
32#include <plat/orion_nand.h> 32#include <plat/orion_nand.h>
33#include <plat/time.h> 33#include <plat/time.h>
34#include <plat/common.h> 34#include <plat/common.h>
@@ -239,104 +239,12 @@ void __init orion5x_uart1_init(void)
239/***************************************************************************** 239/*****************************************************************************
240 * XOR engine 240 * XOR engine
241 ****************************************************************************/ 241 ****************************************************************************/
242struct mv_xor_platform_shared_data orion5x_xor_shared_data = {
243 .dram = &orion5x_mbus_dram_info,
244};
245
246static struct resource orion5x_xor_shared_resources[] = {
247 {
248 .name = "xor low",
249 .start = ORION5X_XOR_PHYS_BASE,
250 .end = ORION5X_XOR_PHYS_BASE + 0xff,
251 .flags = IORESOURCE_MEM,
252 }, {
253 .name = "xor high",
254 .start = ORION5X_XOR_PHYS_BASE + 0x200,
255 .end = ORION5X_XOR_PHYS_BASE + 0x2ff,
256 .flags = IORESOURCE_MEM,
257 },
258};
259
260static struct platform_device orion5x_xor_shared = {
261 .name = MV_XOR_SHARED_NAME,
262 .id = 0,
263 .dev = {
264 .platform_data = &orion5x_xor_shared_data,
265 },
266 .num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
267 .resource = orion5x_xor_shared_resources,
268};
269
270static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32);
271
272static struct resource orion5x_xor0_resources[] = {
273 [0] = {
274 .start = IRQ_ORION5X_XOR0,
275 .end = IRQ_ORION5X_XOR0,
276 .flags = IORESOURCE_IRQ,
277 },
278};
279
280static struct mv_xor_platform_data orion5x_xor0_data = {
281 .shared = &orion5x_xor_shared,
282 .hw_id = 0,
283 .pool_size = PAGE_SIZE,
284};
285
286static struct platform_device orion5x_xor0_channel = {
287 .name = MV_XOR_NAME,
288 .id = 0,
289 .num_resources = ARRAY_SIZE(orion5x_xor0_resources),
290 .resource = orion5x_xor0_resources,
291 .dev = {
292 .dma_mask = &orion5x_xor_dmamask,
293 .coherent_dma_mask = DMA_BIT_MASK(64),
294 .platform_data = &orion5x_xor0_data,
295 },
296};
297
298static struct resource orion5x_xor1_resources[] = {
299 [0] = {
300 .start = IRQ_ORION5X_XOR1,
301 .end = IRQ_ORION5X_XOR1,
302 .flags = IORESOURCE_IRQ,
303 },
304};
305
306static struct mv_xor_platform_data orion5x_xor1_data = {
307 .shared = &orion5x_xor_shared,
308 .hw_id = 1,
309 .pool_size = PAGE_SIZE,
310};
311
312static struct platform_device orion5x_xor1_channel = {
313 .name = MV_XOR_NAME,
314 .id = 1,
315 .num_resources = ARRAY_SIZE(orion5x_xor1_resources),
316 .resource = orion5x_xor1_resources,
317 .dev = {
318 .dma_mask = &orion5x_xor_dmamask,
319 .coherent_dma_mask = DMA_BIT_MASK(64),
320 .platform_data = &orion5x_xor1_data,
321 },
322};
323
324void __init orion5x_xor_init(void) 242void __init orion5x_xor_init(void)
325{ 243{
326 platform_device_register(&orion5x_xor_shared); 244 orion_xor0_init(&orion5x_mbus_dram_info,
327 245 ORION5X_XOR_PHYS_BASE,
328 /* 246 ORION5X_XOR_PHYS_BASE + 0x200,
329 * two engines can't do memset simultaneously, this limitation 247 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
330 * satisfied by removing memset support from one of the engines.
331 */
332 dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
333 dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
334 platform_device_register(&orion5x_xor0_channel);
335
336 dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
337 dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
338 dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
339 platform_device_register(&orion5x_xor1_channel);
340} 248}
341 249
342static struct resource orion5x_crypto_res[] = { 250static struct resource orion5x_crypto_res[] = {
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 65022094747a..0a2face7109e 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -19,6 +19,7 @@
19#include <net/dsa.h> 19#include <net/dsa.h>
20#include <linux/spi/orion_spi.h> 20#include <linux/spi/orion_spi.h>
21#include <plat/orion_wdt.h> 21#include <plat/orion_wdt.h>
22#include <plat/mv_xor.h>
22 23
23/* Fill in the resources structure and link it into the platform 24/* Fill in the resources structure and link it into the platform
24 device structure. There is always a memory region, and nearly 25 device structure. There is always a memory region, and nearly
@@ -585,3 +586,217 @@ void __init orion_wdt_init(unsigned long tclk)
585 orion_wdt_data.tclk = tclk; 586 orion_wdt_data.tclk = tclk;
586 platform_device_register(&orion_wdt_device); 587 platform_device_register(&orion_wdt_device);
587} 588}
589
590/*****************************************************************************
591 * XOR
592 ****************************************************************************/
593static struct mv_xor_platform_shared_data orion_xor_shared_data;
594
595static u64 orion_xor_dmamask = DMA_BIT_MASK(32);
596
597void __init orion_xor_init_channels(
598 struct mv_xor_platform_data *orion_xor0_data,
599 struct platform_device *orion_xor0_channel,
600 struct mv_xor_platform_data *orion_xor1_data,
601 struct platform_device *orion_xor1_channel)
602{
603 /*
604 * two engines can't do memset simultaneously, this limitation
605 * satisfied by removing memset support from one of the engines.
606 */
607 dma_cap_set(DMA_MEMCPY, orion_xor0_data->cap_mask);
608 dma_cap_set(DMA_XOR, orion_xor0_data->cap_mask);
609 platform_device_register(orion_xor0_channel);
610
611 dma_cap_set(DMA_MEMCPY, orion_xor1_data->cap_mask);
612 dma_cap_set(DMA_MEMSET, orion_xor1_data->cap_mask);
613 dma_cap_set(DMA_XOR, orion_xor1_data->cap_mask);
614 platform_device_register(orion_xor1_channel);
615}
616
617/*****************************************************************************
618 * XOR0
619 ****************************************************************************/
620static struct resource orion_xor0_shared_resources[] = {
621 {
622 .name = "xor 0 low",
623 .flags = IORESOURCE_MEM,
624 }, {
625 .name = "xor 0 high",
626 .flags = IORESOURCE_MEM,
627 },
628};
629
630static struct platform_device orion_xor0_shared = {
631 .name = MV_XOR_SHARED_NAME,
632 .id = 0,
633 .dev = {
634 .platform_data = &orion_xor_shared_data,
635 },
636 .num_resources = ARRAY_SIZE(orion_xor0_shared_resources),
637 .resource = orion_xor0_shared_resources,
638};
639
640static struct resource orion_xor00_resources[] = {
641 [0] = {
642 .flags = IORESOURCE_IRQ,
643 },
644};
645
646static struct mv_xor_platform_data orion_xor00_data = {
647 .shared = &orion_xor0_shared,
648 .hw_id = 0,
649 .pool_size = PAGE_SIZE,
650};
651
652static struct platform_device orion_xor00_channel = {
653 .name = MV_XOR_NAME,
654 .id = 0,
655 .num_resources = ARRAY_SIZE(orion_xor00_resources),
656 .resource = orion_xor00_resources,
657 .dev = {
658 .dma_mask = &orion_xor_dmamask,
659 .coherent_dma_mask = DMA_BIT_MASK(64),
660 .platform_data = &orion_xor00_data,
661 },
662};
663
664static struct resource orion_xor01_resources[] = {
665 [0] = {
666 .flags = IORESOURCE_IRQ,
667 },
668};
669
670static struct mv_xor_platform_data orion_xor01_data = {
671 .shared = &orion_xor0_shared,
672 .hw_id = 1,
673 .pool_size = PAGE_SIZE,
674};
675
676static struct platform_device orion_xor01_channel = {
677 .name = MV_XOR_NAME,
678 .id = 1,
679 .num_resources = ARRAY_SIZE(orion_xor01_resources),
680 .resource = orion_xor01_resources,
681 .dev = {
682 .dma_mask = &orion_xor_dmamask,
683 .coherent_dma_mask = DMA_BIT_MASK(64),
684 .platform_data = &orion_xor01_data,
685 },
686};
687
688void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
689 unsigned long mapbase_low,
690 unsigned long mapbase_high,
691 unsigned long irq_0,
692 unsigned long irq_1)
693{
694 orion_xor_shared_data.dram = mbus_dram_info;
695
696 orion_xor0_shared_resources[0].start = mapbase_low;
697 orion_xor0_shared_resources[0].end = mapbase_low + 0xff;
698 orion_xor0_shared_resources[1].start = mapbase_high;
699 orion_xor0_shared_resources[1].end = mapbase_high + 0xff;
700
701 orion_xor00_resources[0].start = irq_0;
702 orion_xor00_resources[0].end = irq_0;
703 orion_xor01_resources[0].start = irq_1;
704 orion_xor01_resources[0].end = irq_1;
705
706 platform_device_register(&orion_xor0_shared);
707
708 orion_xor_init_channels(&orion_xor00_data, &orion_xor00_channel,
709 &orion_xor01_data, &orion_xor01_channel);
710}
711
712/*****************************************************************************
713 * XOR1
714 ****************************************************************************/
715static struct resource orion_xor1_shared_resources[] = {
716 {
717 .name = "xor 1 low",
718 .flags = IORESOURCE_MEM,
719 }, {
720 .name = "xor 1 high",
721 .flags = IORESOURCE_MEM,
722 },
723};
724
725static struct platform_device orion_xor1_shared = {
726 .name = MV_XOR_SHARED_NAME,
727 .id = 1,
728 .dev = {
729 .platform_data = &orion_xor_shared_data,
730 },
731 .num_resources = ARRAY_SIZE(orion_xor1_shared_resources),
732 .resource = orion_xor1_shared_resources,
733};
734
735static struct resource orion_xor10_resources[] = {
736 [0] = {
737 .flags = IORESOURCE_IRQ,
738 },
739};
740
741static struct mv_xor_platform_data orion_xor10_data = {
742 .shared = &orion_xor1_shared,
743 .hw_id = 0,
744 .pool_size = PAGE_SIZE,
745};
746
747static struct platform_device orion_xor10_channel = {
748 .name = MV_XOR_NAME,
749 .id = 2,
750 .num_resources = ARRAY_SIZE(orion_xor10_resources),
751 .resource = orion_xor10_resources,
752 .dev = {
753 .dma_mask = &orion_xor_dmamask,
754 .coherent_dma_mask = DMA_BIT_MASK(64),
755 .platform_data = &orion_xor10_data,
756 },
757};
758
759static struct resource orion_xor11_resources[] = {
760 [0] = {
761 .flags = IORESOURCE_IRQ,
762 },
763};
764
765static struct mv_xor_platform_data orion_xor11_data = {
766 .shared = &orion_xor1_shared,
767 .hw_id = 1,
768 .pool_size = PAGE_SIZE,
769};
770
771static struct platform_device orion_xor11_channel = {
772 .name = MV_XOR_NAME,
773 .id = 3,
774 .num_resources = ARRAY_SIZE(orion_xor11_resources),
775 .resource = orion_xor11_resources,
776 .dev = {
777 .dma_mask = &orion_xor_dmamask,
778 .coherent_dma_mask = DMA_BIT_MASK(64),
779 .platform_data = &orion_xor11_data,
780 },
781};
782
783void __init orion_xor1_init(unsigned long mapbase_low,
784 unsigned long mapbase_high,
785 unsigned long irq_0,
786 unsigned long irq_1)
787{
788 orion_xor1_shared_resources[0].start = mapbase_low;
789 orion_xor1_shared_resources[0].end = mapbase_low + 0xff;
790 orion_xor1_shared_resources[1].start = mapbase_high;
791 orion_xor1_shared_resources[1].end = mapbase_high + 0xff;
792
793 orion_xor10_resources[0].start = irq_0;
794 orion_xor10_resources[0].end = irq_0;
795 orion_xor11_resources[0].start = irq_1;
796 orion_xor11_resources[0].end = irq_1;
797
798 platform_device_register(&orion_xor1_shared);
799
800 orion_xor_init_channels(&orion_xor10_data, &orion_xor10_channel,
801 &orion_xor11_data, &orion_xor11_channel);
802}
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index 38ae4bfd22a4..0e11ca5acd02 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -81,4 +81,15 @@ void __init orion_spi_1_init(unsigned long mapbase,
81 unsigned long tclk); 81 unsigned long tclk);
82 82
83void __init orion_wdt_init(unsigned long tclk); 83void __init orion_wdt_init(unsigned long tclk);
84
85void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
86 unsigned long mapbase_low,
87 unsigned long mapbase_high,
88 unsigned long irq_0,
89 unsigned long irq_1);
90
91void __init orion_xor1_init(unsigned long mapbase_low,
92 unsigned long mapbase_high,
93 unsigned long irq_0,
94 unsigned long irq_1);
84#endif 95#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-31 22:25:41 -0400