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authorLinus Torvalds <torvalds@linux-foundation.org>2012-02-18 18:40:00 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-02-18 18:40:00 -0500
commitbe2874cb4e625716fa9758ad122084da7764cad0 (patch)
tree68966366c698bac9e4fd5dc5d12aa4bc3aad98fc /arch/arm
parent584216b79ca684431ac6f961ae5cf0bb1d31024f (diff)
parenta5368e770c9ec58b9d18378844c149df8513e7b8 (diff)
Merge tag 'fixes-3.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
These are the bug fixes that have accumulated since 3.3-rc3 in arm-soc. The majority of them are regression fixes for stuff that broke during the merge 3.3 window. The notable ones are: * The at91 ata drivers both broke because of an earlier cleanup patch that some other patches were based on. Jean-Christophe decided to remove the legacy at91_ide driver and fix the new-style at91-pata driver while keeping the cleanup patch. I almost rejected the patches for being too late and too big but in the end decided to accept them because they fix a regression. * A patch fixing build breakage from the sysdev-to-device conversion colliding with other changes touches a number of mach-s3c files. * b0654037 "ARM: orion: Fix Orion5x GPIO regression from MPP cleanup" is a mechanical change that unfortunately touches a lot of lines that should up in the diffstat. * tag 'fixes-3.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits) ARM: at91: drop ide driver in favor of the pata one pata/at91: use newly introduced SMC accessors ARM: at91: add accessor to manage SMC ARM: at91:rtc/rtc-at91sam9: ioremap register bank ARM: at91: USB AT91 gadget registration for module ep93xx: fix build of vision_ep93xx.c ARM: OMAP2xxx: PM: fix OMAP2xxx-specific UART idle bug in v3.3 ARM: orion: Fix USB phy for orion5x. ARM: orion: Fix Orion5x GPIO regression from MPP cleanup ARM: EXYNOS: Add cpu-offset property in gic device tree node ARM: EXYNOS: Bring exynos4-dt up to date ARM: OMAP3: cm-t35: fix section mismatch warning ARM: OMAP2: Fix the OMAP2 only build break seen with 2011+ ARM tool-chains ARM: tegra: paz00: fix wrong UART port on mini-pcie plug ARM: tegra: paz00: fix wrong SD1 power gpio i2c: tegra: Add devexit_p() for remove ARM: EXYNOS: Correct M-5MOLS sensor clock frequency on Universal C210 board ARM: EXYNOS: Correct framebuffer window size on Nuri board ARM: SAMSUNG: Fix missing api-change from subsys_interface change ARM: EXYNOS: Fix "warning: initialization from incompatible pointer type" ...
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi1
-rw-r--r--arch/arm/boot/dts/tegra-paz00.dts6
-rw-r--r--arch/arm/mach-at91/at91rm9200_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c9
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c8
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_smc.h29
-rw-r--r--arch/arm/mach-at91/sam9_smc.c76
-rw-r--r--arch/arm/mach-at91/sam9_smc.h23
-rw-r--r--arch/arm/mach-dove/common.c3
-rw-r--r--arch/arm/mach-ep93xx/vision_ep9307.c4
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c2
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c2
-rw-r--r--arch/arm/mach-exynos/clock.c2
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c8
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c8
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c2
-rw-r--r--arch/arm/mach-exynos/pm.c4
-rw-r--r--arch/arm/mach-kirkwood/common.c3
-rw-r--r--arch/arm/mach-kirkwood/mpp.h320
-rw-r--r--arch/arm/mach-mv78xx0/common.c3
-rw-r--r--arch/arm/mach-mv78xx0/mpp.h226
-rw-r--r--arch/arm/mach-omap2/Makefile4
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c2
-rw-r--r--arch/arm/mach-omap2/board-generic.c4
-rw-r--r--arch/arm/mach-omap2/pm24xx.c8
-rw-r--r--arch/arm/mach-orion5x/common.c4
-rw-r--r--arch/arm/mach-s3c2410/cpu-freq.c8
-rw-r--r--arch/arm/mach-s3c2410/dma.c5
-rw-r--r--arch/arm/mach-s3c2410/pll.c2
-rw-r--r--arch/arm/mach-s3c2410/pm.c2
-rw-r--r--arch/arm/mach-s3c2412/cpu-freq.c3
-rw-r--r--arch/arm/mach-s3c2412/dma.c3
-rw-r--r--arch/arm/mach-s3c2412/irq.c2
-rw-r--r--arch/arm/mach-s3c2412/pm.c2
-rw-r--r--arch/arm/mach-s3c2416/irq.c3
-rw-r--r--arch/arm/mach-s3c2416/pm.c2
-rw-r--r--arch/arm/mach-s3c2440/clock.c2
-rw-r--r--arch/arm/mach-s3c2440/dma.c3
-rw-r--r--arch/arm/mach-s3c2440/irq.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c2440-cpufreq.c3
-rw-r--r--arch/arm/mach-s3c2440/s3c2440-pll-12000000.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c2440-pll-16934400.c3
-rw-r--r--arch/arm/mach-s3c2440/s3c2442.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c244x-clock.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c244x-irq.c2
-rw-r--r--arch/arm/mach-s3c2443/dma.c3
-rw-r--r--arch/arm/mach-s3c2443/irq.c3
-rw-r--r--arch/arm/mach-s3c64xx/clock.c5
-rw-r--r--arch/arm/mach-s3c64xx/common.c2
-rw-r--r--arch/arm/mach-s5p64x0/pm.c2
-rw-r--r--arch/arm/mach-s5pv210/clock.c4
-rw-r--r--arch/arm/mach-s5pv210/pm.c2
-rw-r--r--arch/arm/mach-tegra/board-paz00.c8
-rw-r--r--arch/arm/mach-tegra/board-paz00.h2
-rw-r--r--arch/arm/mach-tegra/include/mach/dma.h10
-rw-r--r--arch/arm/plat-omap/include/plat/omap-secure.h2
-rw-r--r--arch/arm/plat-orion/common.c9
-rw-r--r--arch/arm/plat-orion/include/plat/common.h3
-rw-r--r--arch/arm/plat-orion/mpp.c3
-rw-r--r--arch/arm/plat-samsung/devs.c4
61 files changed, 492 insertions, 388 deletions
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 63d7578856c1..a1dd2ee83753 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -29,6 +29,7 @@
29 compatible = "arm,cortex-a9-gic"; 29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>; 30 #interrupt-cells = <3>;
31 interrupt-controller; 31 interrupt-controller;
32 cpu-offset = <0x8000>;
32 reg = <0x10490000 0x1000>, <0x10480000 0x100>; 33 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
33 }; 34 };
34 35
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 1a1d7023b69b..825d2957da0b 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -46,11 +46,11 @@
46 }; 46 };
47 47
48 serial@70006200 { 48 serial@70006200 {
49 status = "disable"; 49 clock-frequency = <216000000>;
50 }; 50 };
51 51
52 serial@70006300 { 52 serial@70006300 {
53 clock-frequency = <216000000>; 53 status = "disable";
54 }; 54 };
55 55
56 serial@70006400 { 56 serial@70006400 {
@@ -60,7 +60,7 @@
60 sdhci@c8000000 { 60 sdhci@c8000000 {
61 cd-gpios = <&gpio 173 0>; /* gpio PV5 */ 61 cd-gpios = <&gpio 173 0>; /* gpio PV5 */
62 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 62 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
63 power-gpios = <&gpio 155 0>; /* gpio PT3 */ 63 power-gpios = <&gpio 169 0>; /* gpio PV1 */
64 }; 64 };
65 65
66 sdhci@c8000200 { 66 sdhci@c8000200 {
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 18bacec2b094..97676bdae998 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -83,7 +83,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
83 * USB Device (Gadget) 83 * USB Device (Gadget)
84 * -------------------------------------------------------------------- */ 84 * -------------------------------------------------------------------- */
85 85
86#ifdef CONFIG_USB_AT91 86#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
87static struct at91_udc_data udc_data; 87static struct at91_udc_data udc_data;
88 88
89static struct resource udc_resources[] = { 89static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 642ccb6d26b2..5a24f0b4554d 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -84,7 +84,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
84 * USB Device (Gadget) 84 * USB Device (Gadget)
85 * -------------------------------------------------------------------- */ 85 * -------------------------------------------------------------------- */
86 86
87#ifdef CONFIG_USB_AT91 87#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
88static struct at91_udc_data udc_data; 88static struct at91_udc_data udc_data;
89 89
90static struct resource udc_resources[] = { 90static struct resource udc_resources[] = {
@@ -1215,8 +1215,7 @@ void __init at91_add_device_serial(void) {}
1215 * CF/IDE 1215 * CF/IDE
1216 * -------------------------------------------------------------------- */ 1216 * -------------------------------------------------------------------- */
1217 1217
1218#if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) || \ 1218#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
1219 defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
1220 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) 1219 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
1221 1220
1222static struct at91_cf_data cf0_data; 1221static struct at91_cf_data cf0_data;
@@ -1313,10 +1312,8 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
1313 if (data->flags & AT91_CF_TRUE_IDE) 1312 if (data->flags & AT91_CF_TRUE_IDE)
1314#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) 1313#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE)
1315 pdev->name = "pata_at91"; 1314 pdev->name = "pata_at91";
1316#elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
1317 pdev->name = "at91_ide";
1318#else 1315#else
1319#warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91" 1316#warning "board requires AT91_CF_TRUE_IDE: enable pata_at91"
1320#endif 1317#endif
1321 else 1318 else
1322 pdev->name = "at91_cf"; 1319 pdev->name = "at91_cf";
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index fc59cbdb0e3c..1e28bed8f425 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -87,7 +87,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
87 * USB Device (Gadget) 87 * USB Device (Gadget)
88 * -------------------------------------------------------------------- */ 88 * -------------------------------------------------------------------- */
89 89
90#ifdef CONFIG_USB_AT91 90#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
91static struct at91_udc_data udc_data; 91static struct at91_udc_data udc_data;
92 92
93static struct resource udc_resources[] = { 93static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 7b46b2787022..366a7765635b 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -92,7 +92,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
92 * USB Device (Gadget) 92 * USB Device (Gadget)
93 * -------------------------------------------------------------------- */ 93 * -------------------------------------------------------------------- */
94 94
95#ifdef CONFIG_USB_AT91 95#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
96static struct at91_udc_data udc_data; 96static struct at91_udc_data udc_data;
97 97
98static struct resource udc_resources[] = { 98static struct resource udc_resources[] = {
@@ -355,8 +355,8 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
355 * Compact Flash (PCMCIA or IDE) 355 * Compact Flash (PCMCIA or IDE)
356 * -------------------------------------------------------------------- */ 356 * -------------------------------------------------------------------- */
357 357
358#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \ 358#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
359 defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) 359 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
360 360
361static struct at91_cf_data cf0_data; 361static struct at91_cf_data cf0_data;
362 362
@@ -450,7 +450,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
450 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */ 450 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
451 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */ 451 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
452 452
453 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf"; 453 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf";
454 platform_device_register(pdev); 454 platform_device_register(pdev);
455} 455}
456#else 456#else
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index eb18a70fa647..175e1fdd9fe8 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -18,6 +18,35 @@
18 18
19#include <mach/cpu.h> 19#include <mach/cpu.h>
20 20
21#ifndef __ASSEMBLY__
22struct sam9_smc_config {
23 /* Setup register */
24 u8 ncs_read_setup;
25 u8 nrd_setup;
26 u8 ncs_write_setup;
27 u8 nwe_setup;
28
29 /* Pulse register */
30 u8 ncs_read_pulse;
31 u8 nrd_pulse;
32 u8 ncs_write_pulse;
33 u8 nwe_pulse;
34
35 /* Cycle register */
36 u16 read_cycle;
37 u16 write_cycle;
38
39 /* Mode register */
40 u32 mode;
41 u8 tdf_cycles:4;
42};
43
44extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
45extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
46extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
47extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
48#endif
49
21#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ 50#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
22#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ 51#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
23#define AT91_SMC_NWESETUP_(x) ((x) << 0) 52#define AT91_SMC_NWESETUP_(x) ((x) << 0)
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index 8294783b679d..99a0a1d2b7dc 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -2,6 +2,7 @@
2 * linux/arch/arm/mach-at91/sam9_smc.c 2 * linux/arch/arm/mach-at91/sam9_smc.c
3 * 3 *
4 * Copyright (C) 2008 Andrew Victor 4 * Copyright (C) 2008 Andrew Victor
5 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -22,7 +23,22 @@
22 23
23static void __iomem *smc_base_addr[2]; 24static void __iomem *smc_base_addr[2];
24 25
25static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config) 26static void sam9_smc_cs_write_mode(void __iomem *base,
27 struct sam9_smc_config *config)
28{
29 __raw_writel(config->mode
30 | AT91_SMC_TDF_(config->tdf_cycles),
31 base + AT91_SMC_MODE);
32}
33
34void sam9_smc_write_mode(int id, int cs,
35 struct sam9_smc_config *config)
36{
37 sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
38}
39
40static void sam9_smc_cs_configure(void __iomem *base,
41 struct sam9_smc_config *config)
26{ 42{
27 43
28 /* Setup register */ 44 /* Setup register */
@@ -45,16 +61,66 @@ static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_con
45 base + AT91_SMC_CYCLE); 61 base + AT91_SMC_CYCLE);
46 62
47 /* Mode register */ 63 /* Mode register */
48 __raw_writel(config->mode 64 sam9_smc_cs_write_mode(base, config);
49 | AT91_SMC_TDF_(config->tdf_cycles),
50 base + AT91_SMC_MODE);
51} 65}
52 66
53void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config) 67void sam9_smc_configure(int id, int cs,
68 struct sam9_smc_config *config)
54{ 69{
55 sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); 70 sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
56} 71}
57 72
73static void sam9_smc_cs_read_mode(void __iomem *base,
74 struct sam9_smc_config *config)
75{
76 u32 val = __raw_readl(base + AT91_SMC_MODE);
77
78 config->mode = (val & ~AT91_SMC_NWECYCLE);
79 config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
80}
81
82void sam9_smc_read_mode(int id, int cs,
83 struct sam9_smc_config *config)
84{
85 sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
86}
87
88static void sam9_smc_cs_read(void __iomem *base,
89 struct sam9_smc_config *config)
90{
91 u32 val;
92
93 /* Setup register */
94 val = __raw_readl(base + AT91_SMC_SETUP);
95
96 config->nwe_setup = val & AT91_SMC_NWESETUP;
97 config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
98 config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16;
99 config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
100
101 /* Pulse register */
102 val = __raw_readl(base + AT91_SMC_PULSE);
103
104 config->nwe_setup = val & AT91_SMC_NWEPULSE;
105 config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
106 config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
107 config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
108
109 /* Cycle register */
110 val = __raw_readl(base + AT91_SMC_CYCLE);
111
112 config->write_cycle = val & AT91_SMC_NWECYCLE;
113 config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
114
115 /* Mode register */
116 sam9_smc_cs_read_mode(base, config);
117}
118
119void sam9_smc_read(int id, int cs, struct sam9_smc_config *config)
120{
121 sam9_smc_cs_read(AT91_SMC_CS(id, cs), config);
122}
123
58void __init at91sam9_ioremap_smc(int id, u32 addr) 124void __init at91sam9_ioremap_smc(int id, u32 addr)
59{ 125{
60 if (id > 1) { 126 if (id > 1) {
diff --git a/arch/arm/mach-at91/sam9_smc.h b/arch/arm/mach-at91/sam9_smc.h
index 039c5ce17aec..3e52dcd4a59f 100644
--- a/arch/arm/mach-at91/sam9_smc.h
+++ b/arch/arm/mach-at91/sam9_smc.h
@@ -8,27 +8,4 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11struct sam9_smc_config {
12 /* Setup register */
13 u8 ncs_read_setup;
14 u8 nrd_setup;
15 u8 ncs_write_setup;
16 u8 nwe_setup;
17
18 /* Pulse register */
19 u8 ncs_read_pulse;
20 u8 nrd_pulse;
21 u8 ncs_write_pulse;
22 u8 nwe_pulse;
23
24 /* Cycle register */
25 u16 read_cycle;
26 u16 write_cycle;
27
28 /* Mode register */
29 u32 mode;
30 u8 tdf_cycles:4;
31};
32
33extern void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config);
34extern void __init at91sam9_ioremap_smc(int id, u32 addr); 11extern void __init at91sam9_ioremap_smc(int id, u32 addr);
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index dd1429ae6405..bda7aca04ca0 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -28,6 +28,7 @@
28#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
29#include <linux/irq.h> 29#include <linux/irq.h>
30#include <plat/time.h> 30#include <plat/time.h>
31#include <plat/ehci-orion.h>
31#include <plat/common.h> 32#include <plat/common.h>
32#include <plat/addr-map.h> 33#include <plat/addr-map.h>
33#include "common.h" 34#include "common.h"
@@ -71,7 +72,7 @@ void __init dove_map_io(void)
71 ****************************************************************************/ 72 ****************************************************************************/
72void __init dove_ehci0_init(void) 73void __init dove_ehci0_init(void)
73{ 74{
74 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); 75 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
75} 76}
76 77
77/***************************************************************************** 78/*****************************************************************************
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index 03dd4012043e..d5fb44f16d31 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -32,6 +32,7 @@
32#include <mach/hardware.h> 32#include <mach/hardware.h>
33#include <mach/fb.h> 33#include <mach/fb.h>
34#include <mach/ep93xx_spi.h> 34#include <mach/ep93xx_spi.h>
35#include <mach/gpio-ep93xx.h>
35 36
36#include <asm/mach-types.h> 37#include <asm/mach-types.h>
37#include <asm/mach/map.h> 38#include <asm/mach/map.h>
@@ -153,7 +154,6 @@ static struct i2c_board_info vision_i2c_info[] __initdata = {
153 }, { 154 }, {
154 I2C_BOARD_INFO("pca9539", 0x74), 155 I2C_BOARD_INFO("pca9539", 0x74),
155 .platform_data = &pca953x_74_gpio_data, 156 .platform_data = &pca953x_74_gpio_data,
156 .irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7)),
157 }, { 157 }, {
158 I2C_BOARD_INFO("pca9539", 0x75), 158 I2C_BOARD_INFO("pca9539", 0x75),
159 .platform_data = &pca953x_75_gpio_data, 159 .platform_data = &pca953x_75_gpio_data,
@@ -348,6 +348,8 @@ static void __init vision_init_machine(void)
348 "pca9539:74")) 348 "pca9539:74"))
349 pr_warn("cannot request interrupt gpio for pca9539:74\n"); 349 pr_warn("cannot request interrupt gpio for pca9539:74\n");
350 350
351 vision_i2c_info[1].irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7));
352
351 ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info, 353 ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info,
352 ARRAY_SIZE(vision_i2c_info)); 354 ARRAY_SIZE(vision_i2c_info));
353 ep93xx_register_spi(&vision_spi_master, vision_spi_board_info, 355 ep93xx_register_spi(&vision_spi_master, vision_spi_board_info,
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index a5823a7f249e..13312ccb2d93 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -32,6 +32,7 @@
32 32
33#include "common.h" 33#include "common.h"
34 34
35#ifdef CONFIG_PM_SLEEP
35static struct sleep_save exynos4210_clock_save[] = { 36static struct sleep_save exynos4210_clock_save[] = {
36 SAVE_ITEM(S5P_CLKSRC_IMAGE), 37 SAVE_ITEM(S5P_CLKSRC_IMAGE),
37 SAVE_ITEM(S5P_CLKSRC_LCD1), 38 SAVE_ITEM(S5P_CLKSRC_LCD1),
@@ -42,6 +43,7 @@ static struct sleep_save exynos4210_clock_save[] = {
42 SAVE_ITEM(S5P_CLKGATE_IP_LCD1), 43 SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
43 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210), 44 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
44}; 45};
46#endif
45 47
46static struct clksrc_clk *sysclks[] = { 48static struct clksrc_clk *sysclks[] = {
47 /* nothing here yet */ 49 /* nothing here yet */
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 26a668b0d101..48af28566fa1 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -32,12 +32,14 @@
32 32
33#include "common.h" 33#include "common.h"
34 34
35#ifdef CONFIG_PM_SLEEP
35static struct sleep_save exynos4212_clock_save[] = { 36static struct sleep_save exynos4212_clock_save[] = {
36 SAVE_ITEM(S5P_CLKSRC_IMAGE), 37 SAVE_ITEM(S5P_CLKSRC_IMAGE),
37 SAVE_ITEM(S5P_CLKDIV_IMAGE), 38 SAVE_ITEM(S5P_CLKDIV_IMAGE),
38 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212), 39 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
39 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212), 40 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
40}; 41};
42#endif
41 43
42static struct clk *clk_src_mpll_user_list[] = { 44static struct clk *clk_src_mpll_user_list[] = {
43 [0] = &clk_fin_mpll, 45 [0] = &clk_fin_mpll,
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 5a8c42e90005..187287aa57ab 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -30,6 +30,7 @@
30 30
31#include "common.h" 31#include "common.h"
32 32
33#ifdef CONFIG_PM_SLEEP
33static struct sleep_save exynos4_clock_save[] = { 34static struct sleep_save exynos4_clock_save[] = {
34 SAVE_ITEM(S5P_CLKDIV_LEFTBUS), 35 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
35 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), 36 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
@@ -93,6 +94,7 @@ static struct sleep_save exynos4_clock_save[] = {
93 SAVE_ITEM(S5P_CLKGATE_SCLKCPU), 94 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
94 SAVE_ITEM(S5P_CLKGATE_IP_CPU), 95 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
95}; 96};
97#endif
96 98
97struct clk clk_sclk_hdmi27m = { 99struct clk clk_sclk_hdmi27m = {
98 .name = "sclk_hdmi27m", 100 .name = "sclk_hdmi27m",
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 85fa02767d67..e6b02fdf1b09 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -15,11 +15,13 @@
15#include <linux/serial_core.h> 15#include <linux/serial_core.h>
16 16
17#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
18#include <asm/hardware/gic.h>
18#include <mach/map.h> 19#include <mach/map.h>
19 20
20#include <plat/cpu.h> 21#include <plat/cpu.h>
21#include <plat/regs-serial.h> 22#include <plat/regs-serial.h>
22#include <plat/exynos4.h> 23
24#include "common.h"
23 25
24/* 26/*
25 * The following lookup table is used to override device names when devices 27 * The following lookup table is used to override device names when devices
@@ -60,7 +62,7 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
60 62
61static void __init exynos4210_dt_map_io(void) 63static void __init exynos4210_dt_map_io(void)
62{ 64{
63 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 65 exynos_init_io(NULL, 0);
64 s3c24xx_init_clocks(24000000); 66 s3c24xx_init_clocks(24000000);
65} 67}
66 68
@@ -79,7 +81,9 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
79 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ 81 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
80 .init_irq = exynos4_init_irq, 82 .init_irq = exynos4_init_irq,
81 .map_io = exynos4210_dt_map_io, 83 .map_io = exynos4210_dt_map_io,
84 .handle_irq = gic_handle_irq,
82 .init_machine = exynos4210_dt_machine_init, 85 .init_machine = exynos4210_dt_machine_init,
83 .timer = &exynos4_timer, 86 .timer = &exynos4_timer,
84 .dt_compat = exynos4210_dt_compat, 87 .dt_compat = exynos4210_dt_compat,
88 .restart = exynos4_restart,
85MACHINE_END 89MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index b895ec031105..435261f83f46 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -220,14 +220,14 @@ static struct s3c_fb_pd_win nuri_fb_win0 = {
220 .lower_margin = 1, 220 .lower_margin = 1,
221 .hsync_len = 48, 221 .hsync_len = 48,
222 .vsync_len = 3, 222 .vsync_len = 3,
223 .xres = 1280, 223 .xres = 1024,
224 .yres = 800, 224 .yres = 600,
225 .refresh = 60, 225 .refresh = 60,
226 }, 226 },
227 .max_bpp = 24, 227 .max_bpp = 24,
228 .default_bpp = 16, 228 .default_bpp = 16,
229 .virtual_x = 1280, 229 .virtual_x = 1024,
230 .virtual_y = 800, 230 .virtual_y = 2 * 600,
231}; 231};
232 232
233static struct s3c_fb_platdata nuri_fb_pdata __initdata = { 233static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 37ac93e8d6d9..0fc65ffde8ff 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -910,7 +910,7 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = {
910 .bus_type = FIMC_MIPI_CSI2, 910 .bus_type = FIMC_MIPI_CSI2,
911 .board_info = &m5mols_board_info, 911 .board_info = &m5mols_board_info,
912 .i2c_bus_num = 0, 912 .i2c_bus_num = 0,
913 .clk_frequency = 21600000UL, 913 .clk_frequency = 24000000UL,
914 .csi_data_align = 32, 914 .csi_data_align = 32,
915 }, 915 },
916}; 916};
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index a4f61a43c7ba..e19013051772 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -206,7 +206,7 @@ static void exynos4_pm_prepare(void)
206 206
207} 207}
208 208
209static int exynos4_pm_add(struct device *dev) 209static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif)
210{ 210{
211 pm_cpu_prep = exynos4_pm_prepare; 211 pm_cpu_prep = exynos4_pm_prepare;
212 pm_cpu_sleep = exynos4_cpu_suspend; 212 pm_cpu_sleep = exynos4_cpu_suspend;
@@ -384,7 +384,9 @@ static void exynos4_pm_resume(void)
384 384
385 exynos4_restore_pll(); 385 exynos4_restore_pll();
386 386
387#ifdef CONFIG_SMP
387 scu_enable(S5P_VA_SCU); 388 scu_enable(S5P_VA_SCU);
389#endif
388 390
389#ifdef CONFIG_CACHE_L2X0 391#ifdef CONFIG_CACHE_L2X0
390 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); 392 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index cc15426787b1..77d4852e19f2 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -27,6 +27,7 @@
27#include <plat/cache-feroceon-l2.h> 27#include <plat/cache-feroceon-l2.h>
28#include <plat/mvsdio.h> 28#include <plat/mvsdio.h>
29#include <plat/orion_nand.h> 29#include <plat/orion_nand.h>
30#include <plat/ehci-orion.h>
30#include <plat/common.h> 31#include <plat/common.h>
31#include <plat/time.h> 32#include <plat/time.h>
32#include <plat/addr-map.h> 33#include <plat/addr-map.h>
@@ -73,7 +74,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
73void __init kirkwood_ehci_init(void) 74void __init kirkwood_ehci_init(void)
74{ 75{
75 kirkwood_clk_ctrl |= CGC_USB0; 76 kirkwood_clk_ctrl |= CGC_USB0;
76 orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB); 77 orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
77} 78}
78 79
79 80
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index e8fda45c0736..d5a0d1da2e0e 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -31,314 +31,314 @@
31#define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 ) 31#define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 )
32 32
33#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 33#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 )
34#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 34#define MPP0_NF_IO2 MPP( 0, 0x1, 0, 0, 1, 1, 1, 1, 1 )
35#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 35#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 0, 1, 1, 1, 1, 1 )
36 36
37#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 37#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 )
38#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 38#define MPP1_NF_IO3 MPP( 1, 0x1, 0, 0, 1, 1, 1, 1, 1 )
39#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 39#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 0, 1, 1, 1, 1, 1 )
40 40
41#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 41#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 )
42#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 42#define MPP2_NF_IO4 MPP( 2, 0x1, 0, 0, 1, 1, 1, 1, 1 )
43#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 43#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 0, 1, 1, 1, 1, 1 )
44 44
45#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 45#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 )
46#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 46#define MPP3_NF_IO5 MPP( 3, 0x1, 0, 0, 1, 1, 1, 1, 1 )
47#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 47#define MPP3_SPI_MISO MPP( 3, 0x2, 0, 0, 1, 1, 1, 1, 1 )
48 48
49#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 49#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 )
50#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 50#define MPP4_NF_IO6 MPP( 4, 0x1, 0, 0, 1, 1, 1, 1, 1 )
51#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 51#define MPP4_UART0_RXD MPP( 4, 0x2, 0, 0, 1, 1, 1, 1, 1 )
52#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 52#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 0, 0, 0, 1, 1, 1 )
53#define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 53#define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 )
54#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 ) 54#define MPP4_PTP_CLK MPP( 4, 0xd, 0, 0, 1, 1, 1, 1, 0 )
55 55
56#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 56#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 )
57#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 57#define MPP5_NF_IO7 MPP( 5, 0x1, 0, 0, 1, 1, 1, 1, 1 )
58#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 58#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 0, 1, 1, 1, 1, 1 )
59#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 ) 59#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 0, 1, 1, 1, 1, 0 )
60#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 60#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 0, 0, 1, 1, 1, 1 )
61#define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 61#define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 )
62 62
63#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 ) 63#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 0, 1, 1, 1, 1, 1 )
64#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 64#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 0, 1, 1, 1, 1, 1 )
65#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 ) 65#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 0, 1, 1, 1, 1, 0 )
66 66
67#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 67#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 )
68#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 ) 68#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 0, 1, 1, 1, 1, 0 )
69#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 69#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 0, 1, 1, 1, 1, 1 )
70#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 ) 70#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 0, 1, 1, 1, 1, 0 )
71#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 71#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 0, 0, 0, 0, 0, 1 )
72 72
73#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 73#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 )
74#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 74#define MPP8_TW0_SDA MPP( 8, 0x1, 0, 0, 1, 1, 1, 1, 1 )
75#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 75#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 0, 1, 1, 1, 1, 1 )
76#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 ) 76#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 0, 1, 1, 1, 1, 1 )
77#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 ) 77#define MPP8_MII0_RXERR MPP( 8, 0x4, 0, 0, 0, 1, 1, 1, 1 )
78#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 78#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 0, 0, 0, 1, 1, 1 )
79#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 ) 79#define MPP8_PTP_CLK MPP( 8, 0xc, 0, 0, 1, 1, 1, 1, 0 )
80#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 80#define MPP8_MII0_COL MPP( 8, 0xd, 0, 0, 1, 1, 1, 1, 1 )
81 81
82#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 82#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 )
83#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 83#define MPP9_TW0_SCK MPP( 9, 0x1, 0, 0, 1, 1, 1, 1, 1 )
84#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 84#define MPP9_UART0_CTS MPP( 9, 0x2, 0, 0, 1, 1, 1, 1, 1 )
85#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 85#define MPP9_UART1_CTS MPP( 9, 0x3, 0, 0, 1, 1, 1, 1, 1 )
86#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 86#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 0, 0, 1, 1, 1, 1 )
87#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 ) 87#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 0, 0, 1, 1, 1, 1, 0 )
88#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 88#define MPP9_MII0_CRS MPP( 9, 0xd, 0, 0, 1, 1, 1, 1, 1 )
89 89
90#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 90#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 )
91#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 91#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 0, 1, 1, 1, 1, 1 )
92#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 ) 92#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 0, 1, 1, 1, 1, 1 )
93#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 93#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 0, 0, 0, 1, 1, 1 )
94#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 ) 94#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 0, 1, 1, 1, 1, 0 )
95 95
96#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 96#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 )
97#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 97#define MPP11_SPI_MISO MPP( 11, 0x2, 0, 0, 1, 1, 1, 1, 1 )
98#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 98#define MPP11_UART0_RXD MPP( 11, 0x3, 0, 0, 1, 1, 1, 1, 1 )
99#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 ) 99#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 0, 0, 1, 1, 1, 1, 0 )
100#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 ) 100#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 0, 1, 1, 1, 1, 0 )
101#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 ) 101#define MPP11_PTP_CLK MPP( 11, 0xd, 0, 0, 1, 1, 1, 1, 0 )
102#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 102#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 0, 0, 1, 1, 1, 1 )
103 103
104#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 104#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 )
105#define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 ) 105#define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 )
106#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) 106#define MPP12_SD_CLK MPP( 12, 0x1, 0, 0, 1, 1, 1, 1, 1 )
107#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 107#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 0, 0, 0, 0, 0, 1 )
108#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 108#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 0, 0, 0, 0, 0, 1 )
109#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 ) 109#define MPP12_TW1_SDA MPP( 12, 0xd, 0, 0, 0, 0, 0, 0, 1 )
110 110
111#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 111#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 )
112#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 112#define MPP13_SD_CMD MPP( 13, 0x1, 0, 0, 1, 1, 1, 1, 1 )
113#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 ) 113#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 0, 1, 1, 1, 1, 1 )
114#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 114#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 0, 0, 0, 0, 0, 1 )
115#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 115#define MPP13_LCDPWM MPP( 13, 0xb, 0, 0, 0, 0, 0, 0, 1 )
116 116
117#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 117#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 )
118#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 118#define MPP14_SD_D0 MPP( 14, 0x1, 0, 0, 1, 1, 1, 1, 1 )
119#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 119#define MPP14_UART1_RXD MPP( 14, 0x3, 0, 0, 1, 1, 1, 1, 1 )
120#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 120#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 0, 0, 0, 1, 1, 1 )
121#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 ) 121#define MPP14_AU_SPDIFI MPP( 14, 0xa, 0, 0, 0, 0, 0, 0, 1 )
122#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 ) 122#define MPP14_AU_I2SDI MPP( 14, 0xb, 0, 0, 0, 0, 0, 0, 1 )
123#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 123#define MPP14_MII0_COL MPP( 14, 0xd, 0, 0, 1, 1, 1, 1, 1 )
124 124
125#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 125#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 )
126#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 126#define MPP15_SD_D1 MPP( 15, 0x1, 0, 0, 1, 1, 1, 1, 1 )
127#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 127#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 0, 1, 1, 1, 1, 1 )
128#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 ) 128#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 0, 1, 1, 1, 1, 1 )
129#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 ) 129#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 0, 0, 1, 1, 1, 1 )
130#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 130#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 0, 0, 0, 0, 0, 1 )
131 131
132#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 132#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 )
133#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 133#define MPP16_SD_D2 MPP( 16, 0x1, 0, 0, 1, 1, 1, 1, 1 )
134#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 134#define MPP16_UART0_CTS MPP( 16, 0x2, 0, 0, 1, 1, 1, 1, 1 )
135#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 135#define MPP16_UART1_RXD MPP( 16, 0x3, 0, 0, 1, 1, 1, 1, 1 )
136#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 136#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 0, 0, 0, 1, 1, 1 )
137#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 ) 137#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 0, 0, 0, 0, 0, 0, 1 )
138#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 138#define MPP16_MII0_CRS MPP( 16, 0xd, 0, 0, 1, 1, 1, 1, 1 )
139 139
140#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 140#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 )
141#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 141#define MPP17_SD_D3 MPP( 17, 0x1, 0, 0, 1, 1, 1, 1, 1 )
142#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 ) 142#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 0, 0, 1, 1, 1, 1 )
143#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 143#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 0, 0, 0, 0, 0, 1 )
144#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 ) 144#define MPP17_TW1_SCK MPP( 17, 0xd, 0, 0, 0, 0, 0, 0, 1 )
145 145
146#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 146#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 )
147#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 147#define MPP18_NF_IO0 MPP( 18, 0x1, 0, 0, 1, 1, 1, 1, 1 )
148#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 ) 148#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 0, 0, 0, 0, 0, 1 )
149 149
150#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 150#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 )
151#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 151#define MPP19_NF_IO1 MPP( 19, 0x1, 0, 0, 1, 1, 1, 1, 1 )
152 152
153#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 153#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 )
154#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 154#define MPP20_TSMP0 MPP( 20, 0x1, 0, 0, 0, 0, 1, 1, 1 )
155#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 155#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 0, 0, 0, 1, 1, 1 )
156#define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 156#define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 )
157#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 ) 157#define MPP20_AU_SPDIFI MPP( 20, 0x4, 0, 0, 0, 0, 1, 1, 1 )
158#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 158#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 0, 0, 0, 1, 1, 1 )
159#define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 159#define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 )
160 160
161#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 161#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 )
162#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 162#define MPP21_TSMP1 MPP( 21, 0x1, 0, 0, 0, 0, 1, 1, 1 )
163#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 163#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 0, 0, 0, 1, 1, 1 )
164#define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 164#define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 )
165#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 165#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 0, 0, 0, 1, 1, 1 )
166#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 166#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 0, 0, 1, 1, 1, 1 )
167#define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 167#define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 )
168 168
169#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 169#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 )
170#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 170#define MPP22_TSMP2 MPP( 22, 0x1, 0, 0, 0, 0, 1, 1, 1 )
171#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 171#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 0, 0, 0, 1, 1, 1 )
172#define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 172#define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 )
173#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 173#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 0, 0, 0, 1, 1, 1 )
174#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 174#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 0, 0, 0, 1, 1, 1 )
175#define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 175#define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
176 176
177#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 177#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 )
178#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 178#define MPP23_TSMP3 MPP( 23, 0x1, 0, 0, 0, 0, 1, 1, 1 )
179#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 ) 179#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 0, 0, 0, 0, 1, 1, 1 )
180#define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 180#define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 )
181#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 181#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 0, 0, 0, 1, 1, 1 )
182#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 182#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 0, 0, 1, 1, 1, 1 )
183#define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 183#define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 )
184 184
185#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 185#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 )
186#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 186#define MPP24_TSMP4 MPP( 24, 0x1, 0, 0, 0, 0, 1, 1, 1 )
187#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 187#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 0, 0, 0, 1, 1, 1 )
188#define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 188#define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 )
189#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 189#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 0, 0, 0, 1, 1, 1 )
190#define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 190#define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 )
191 191
192#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 192#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 )
193#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 193#define MPP25_TSMP5 MPP( 25, 0x1, 0, 0, 0, 0, 1, 1, 1 )
194#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 194#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 0, 0, 0, 1, 1, 1 )
195#define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 195#define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 )
196#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 196#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 0, 0, 0, 1, 1, 1 )
197#define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 197#define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 )
198 198
199#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 199#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 )
200#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 200#define MPP26_TSMP6 MPP( 26, 0x1, 0, 0, 0, 0, 1, 1, 1 )
201#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 ) 201#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 0, 0, 0, 0, 1, 1, 1 )
202#define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 202#define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 )
203#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 203#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 0, 0, 0, 1, 1, 1 )
204#define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 204#define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 )
205 205
206#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 206#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 )
207#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 207#define MPP27_TSMP7 MPP( 27, 0x1, 0, 0, 0, 0, 1, 1, 1 )
208#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 208#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 0, 0, 0, 1, 1, 1 )
209#define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 209#define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 )
210#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 ) 210#define MPP27_AU_I2SDI MPP( 27, 0x4, 0, 0, 0, 0, 1, 1, 1 )
211#define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 211#define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 )
212 212
213#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 213#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 )
214#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 214#define MPP28_TSMP8 MPP( 28, 0x1, 0, 0, 0, 0, 1, 1, 1 )
215#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 215#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 )
216#define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 216#define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 )
217#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 ) 217#define MPP28_AU_EXTCLK MPP( 28, 0x4, 0, 0, 0, 0, 1, 1, 1 )
218#define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 218#define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 )
219 219
220#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 220#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 )
221#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 221#define MPP29_TSMP9 MPP( 29, 0x1, 0, 0, 0, 0, 1, 1, 1 )
222#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 222#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 )
223#define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 223#define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 )
224#define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 224#define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 )
225 225
226#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 226#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 )
227#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 227#define MPP30_TSMP10 MPP( 30, 0x1, 0, 0, 0, 0, 1, 1, 1 )
228#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 ) 228#define MPP30_TDM_PCLK MPP( 30, 0x2, 0, 0, 0, 0, 1, 1, 1 )
229#define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 229#define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 )
230#define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 230#define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 )
231 231
232#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 232#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 )
233#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 233#define MPP31_TSMP11 MPP( 31, 0x1, 0, 0, 0, 0, 1, 1, 1 )
234#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 ) 234#define MPP31_TDM_FS MPP( 31, 0x2, 0, 0, 0, 0, 1, 1, 1 )
235#define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 235#define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 )
236#define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 236#define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 )
237 237
238#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 238#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 )
239#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 239#define MPP32_TSMP12 MPP( 32, 0x1, 0, 0, 0, 0, 1, 1, 1 )
240#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 ) 240#define MPP32_TDM_DRX MPP( 32, 0x2, 0, 0, 0, 0, 1, 1, 1 )
241#define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 241#define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 )
242#define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 242#define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 )
243 243
244#define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 ) 244#define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 )
245#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 245#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 0, 0, 0, 1, 1, 1 )
246#define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 246#define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 )
247#define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 247#define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 )
248 248
249#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 249#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 )
250#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 250#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 0, 0, 0, 1, 1, 1 )
251#define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 251#define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 )
252#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 ) 252#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 0, 0, 0, 0, 1, 1 )
253#define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 253#define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 )
254 254
255#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 255#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 )
256#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 256#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 0, 0, 0, 1, 1, 1 )
257#define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 257#define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 )
258#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 258#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 0, 0, 1, 1, 1, 1 )
259#define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 259#define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
260#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 ) 260#define MPP35_MII0_RXERR MPP( 35, 0xc, 0, 0, 1, 1, 1, 1, 1 )
261 261
262#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 262#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 )
263#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 263#define MPP36_TSMP0 MPP( 36, 0x1, 0, 0, 0, 0, 0, 1, 1 )
264#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 264#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 0, 0, 0, 0, 1, 1 )
265#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 ) 265#define MPP36_AU_SPDIFI MPP( 36, 0x4, 0, 0, 1, 0, 0, 1, 1 )
266#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 ) 266#define MPP36_TW1_SDA MPP( 36, 0xb, 0, 0, 0, 0, 0, 0, 1 )
267 267
268#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 268#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 )
269#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 269#define MPP37_TSMP1 MPP( 37, 0x1, 0, 0, 0, 0, 0, 1, 1 )
270#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 270#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 0, 0, 0, 0, 1, 1 )
271#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 271#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 0, 1, 0, 0, 1, 1 )
272#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 ) 272#define MPP37_TW1_SCK MPP( 37, 0xb, 0, 0, 0, 0, 0, 0, 1 )
273 273
274#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 274#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 )
275#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 275#define MPP38_TSMP2 MPP( 38, 0x1, 0, 0, 0, 0, 0, 1, 1 )
276#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 276#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 0, 0, 0, 0, 1, 1 )
277#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 277#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 0, 1, 0, 0, 1, 1 )
278#define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 278#define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 )
279 279
280#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 280#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 )
281#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 281#define MPP39_TSMP3 MPP( 39, 0x1, 0, 0, 0, 0, 0, 1, 1 )
282#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 282#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 0, 0, 0, 0, 1, 1 )
283#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 283#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 0, 1, 0, 0, 1, 1 )
284#define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 284#define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 )
285 285
286#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 286#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 )
287#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 287#define MPP40_TSMP4 MPP( 40, 0x1, 0, 0, 0, 0, 0, 1, 1 )
288#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 288#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 0, 0, 0, 0, 1, 1 )
289#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 289#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 0, 1, 0, 0, 1, 1 )
290#define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 290#define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 )
291 291
292#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 292#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 )
293#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 293#define MPP41_TSMP5 MPP( 41, 0x1, 0, 0, 0, 0, 0, 1, 1 )
294#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 ) 294#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 0, 0, 0, 0, 0, 1, 1 )
295#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 295#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 0, 1, 0, 0, 1, 1 )
296#define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 296#define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 )
297 297
298#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 298#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 )
299#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 299#define MPP42_TSMP6 MPP( 42, 0x1, 0, 0, 0, 0, 0, 1, 1 )
300#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 300#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 0, 0, 0, 0, 1, 1 )
301#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 301#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 0, 1, 0, 0, 1, 1 )
302#define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 302#define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 )
303 303
304#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 304#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 )
305#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 305#define MPP43_TSMP7 MPP( 43, 0x1, 0, 0, 0, 0, 0, 1, 1 )
306#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 306#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 )
307#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 ) 307#define MPP43_AU_I2SDI MPP( 43, 0x4, 0, 0, 1, 0, 0, 1, 1 )
308#define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 308#define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
309 309
310#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 310#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 )
311#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 311#define MPP44_TSMP8 MPP( 44, 0x1, 0, 0, 0, 0, 0, 1, 1 )
312#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 312#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 )
313#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 ) 313#define MPP44_AU_EXTCLK MPP( 44, 0x4, 0, 0, 1, 0, 0, 1, 1 )
314#define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 314#define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 )
315 315
316#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 316#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 )
317#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 317#define MPP45_TSMP9 MPP( 45, 0x1, 0, 0, 0, 0, 0, 1, 1 )
318#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 ) 318#define MPP45_TDM_PCLK MPP( 45, 0x2, 0, 0, 0, 0, 0, 1, 1 )
319#define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 319#define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 )
320 320
321#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 321#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 )
322#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 322#define MPP46_TSMP10 MPP( 46, 0x1, 0, 0, 0, 0, 0, 1, 1 )
323#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 ) 323#define MPP46_TDM_FS MPP( 46, 0x2, 0, 0, 0, 0, 0, 1, 1 )
324#define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 324#define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 )
325 325
326#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 326#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 )
327#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 327#define MPP47_TSMP11 MPP( 47, 0x1, 0, 0, 0, 0, 0, 1, 1 )
328#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 ) 328#define MPP47_TDM_DRX MPP( 47, 0x2, 0, 0, 0, 0, 0, 1, 1 )
329#define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 329#define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 )
330 330
331#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 331#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 )
332#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 332#define MPP48_TSMP12 MPP( 48, 0x1, 0, 0, 0, 0, 0, 1, 1 )
333#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 333#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 0, 0, 0, 0, 1, 1 )
334#define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 334#define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
335 335
336#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 ) 336#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 )
337#define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 ) 337#define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 )
338#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 ) 338#define MPP49_TSMP9 MPP( 49, 0x1, 0, 0, 0, 0, 0, 1, 0 )
339#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 339#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 0, 0, 0, 0, 1, 1 )
340#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 ) 340#define MPP49_PTP_CLK MPP( 49, 0x5, 0, 0, 0, 0, 0, 1, 0 )
341#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 341#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 0, 0, 0, 0, 0, 1 )
342#define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 342#define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 )
343 343
344#define MPP_MAX 49 344#define MPP_MAX 49
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 0cdd41004ad0..a5dcf766a3f9 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -19,6 +19,7 @@
19#include <mach/mv78xx0.h> 19#include <mach/mv78xx0.h>
20#include <mach/bridge-regs.h> 20#include <mach/bridge-regs.h>
21#include <plat/cache-feroceon-l2.h> 21#include <plat/cache-feroceon-l2.h>
22#include <plat/ehci-orion.h>
22#include <plat/orion_nand.h> 23#include <plat/orion_nand.h>
23#include <plat/time.h> 24#include <plat/time.h>
24#include <plat/common.h> 25#include <plat/common.h>
@@ -169,7 +170,7 @@ void __init mv78xx0_map_io(void)
169 ****************************************************************************/ 170 ****************************************************************************/
170void __init mv78xx0_ehci0_init(void) 171void __init mv78xx0_ehci0_init(void)
171{ 172{
172 orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); 173 orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
173} 174}
174 175
175 176
diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h
index b61b50927123..3752302ae2ee 100644
--- a/arch/arm/mach-mv78xx0/mpp.h
+++ b/arch/arm/mach-mv78xx0/mpp.h
@@ -24,296 +24,296 @@
24#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) 24#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
25 25
26#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) 26#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)
27#define MPP0_GE0_COL MPP(0, 0x1, 1, 0, 1) 27#define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1)
28#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 1, 1) 28#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1)
29#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1) 29#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1)
30 30
31#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1) 31#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1)
32#define MPP1_GE0_RXERR MPP(1, 0x1, 1, 0, 1) 32#define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1)
33#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 1, 1) 33#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1)
34#define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1) 34#define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1)
35 35
36#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1) 36#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1)
37#define MPP2_GE0_CRS MPP(2, 0x1, 1, 0, 1) 37#define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1)
38#define MPP2_GE1_RXCTL MPP(2, 0x2, 1, 0, 1) 38#define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1)
39#define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1) 39#define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1)
40 40
41#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1) 41#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1)
42#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 1, 1) 42#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1)
43#define MPP3_GE1_RXCLK MPP(3, 0x2, 1, 0, 1) 43#define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1)
44#define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1) 44#define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1)
45 45
46#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1) 46#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1)
47#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 1, 1) 47#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1)
48#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 1, 1) 48#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1)
49#define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1) 49#define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1)
50 50
51#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1) 51#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1)
52#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 1, 1) 52#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1)
53#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 1, 1) 53#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1)
54#define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1) 54#define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1)
55 55
56#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1) 56#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1)
57#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 1, 1) 57#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1)
58#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 1, 1) 58#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1)
59#define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1) 59#define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1)
60 60
61#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1) 61#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1)
62#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 1, 1) 62#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1)
63#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 1, 1) 63#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1)
64#define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1) 64#define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1)
65 65
66#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1) 66#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1)
67#define MPP8_GE0_RXD4 MPP(8, 0x1, 1, 0, 1) 67#define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1)
68#define MPP8_GE1_RXD0 MPP(8, 0x2, 1, 0, 1) 68#define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1)
69#define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1) 69#define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1)
70 70
71#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1) 71#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1)
72#define MPP9_GE0_RXD5 MPP(9, 0x1, 1, 0, 1) 72#define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1)
73#define MPP9_GE1_RXD1 MPP(9, 0x2, 1, 0, 1) 73#define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1)
74#define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1) 74#define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1)
75 75
76#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1) 76#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1)
77#define MPP10_GE0_RXD6 MPP(10, 0x1, 1, 0, 1) 77#define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1)
78#define MPP10_GE1_RXD2 MPP(10, 0x2, 1, 0, 1) 78#define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1)
79#define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1) 79#define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1)
80 80
81#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1) 81#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1)
82#define MPP11_GE0_RXD7 MPP(11, 0x1, 1, 0, 1) 82#define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1)
83#define MPP11_GE1_RXD3 MPP(11, 0x2, 1, 0, 1) 83#define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1)
84#define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1) 84#define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1)
85 85
86#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1) 86#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1)
87#define MPP12_M_BB MPP(12, 0x3, 1, 0, 1) 87#define MPP12_M_BB MPP(12, 0x3, 0, 0, 1)
88#define MPP12_UA0_CTSn MPP(12, 0x4, 1, 0, 1) 88#define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1)
89#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 1, 1) 89#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1)
90#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 1, 1) 90#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1)
91#define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1) 91#define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1)
92 92
93#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1) 93#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1)
94#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 1, 1) 94#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1)
95#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 1, 1) 95#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1)
96#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 1, 1) 96#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1)
97#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 1, 1) 97#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1)
98#define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1) 98#define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1)
99 99
100#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1) 100#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1)
101#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 1, 1) 101#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1)
102#define MPP14_UA1_CTSn MPP(14, 0x4, 1, 0, 1) 102#define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1)
103#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 1, 1) 103#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1)
104#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 1, 1) 104#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1)
105#define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1) 105#define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1)
106 106
107#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1) 107#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1)
108#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 1, 1) 108#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1)
109#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 1, 1) 109#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1)
110#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 1, 1) 110#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1)
111#define MPP15_TDM_SMISO MPP(15, 0x6, 1, 0, 1) 111#define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1)
112#define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1) 112#define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1)
113 113
114#define MPP16_GPIO MPP(16, 0x0, 1, 1, 1) 114#define MPP16_GPIO MPP(16, 0x0, 1, 1, 1)
115#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 1, 1) 115#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1)
116#define MPP16_UA2_TXD MPP(16, 0x4, 0, 1, 1) 116#define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1)
117#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 1, 1) 117#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1)
118#define MPP16_TDM_INTn MPP(16, 0x6, 1, 0, 1) 118#define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1)
119#define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1) 119#define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1)
120 120
121 121
122#define MPP17_GPIO MPP(17, 0x0, 1, 1, 1) 122#define MPP17_GPIO MPP(17, 0x0, 1, 1, 1)
123#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 1, 1) 123#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1)
124#define MPP17_UA2_RXD MPP(17, 0x4, 1, 0, 1) 124#define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1)
125#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 1, 1) 125#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1)
126#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 1, 1) 126#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1)
127#define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1) 127#define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1)
128 128
129 129
130#define MPP18_GPIO MPP(18, 0x0, 1, 1, 1) 130#define MPP18_GPIO MPP(18, 0x0, 1, 1, 1)
131#define MPP18_UA0_CTSn MPP(18, 0x4, 1, 0, 1) 131#define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1)
132#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 1, 1) 132#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1)
133#define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1) 133#define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1)
134 134
135 135
136 136
137#define MPP19_GPIO MPP(19, 0x0, 1, 1, 1) 137#define MPP19_GPIO MPP(19, 0x0, 1, 1, 1)
138#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 1, 1) 138#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1)
139#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 1, 1) 139#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1)
140#define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1) 140#define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1)
141 141
142 142
143#define MPP20_GPIO MPP(20, 0x0, 1, 1, 1) 143#define MPP20_GPIO MPP(20, 0x0, 1, 1, 1)
144#define MPP20_UA1_CTSs MPP(20, 0x4, 1, 0, 1) 144#define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1)
145#define MPP20_TDM_PCLK MPP(20, 0x6, 1, 1, 0) 145#define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0)
146#define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1) 146#define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1)
147 147
148 148
149 149
150#define MPP21_GPIO MPP(21, 0x0, 1, 1, 1) 150#define MPP21_GPIO MPP(21, 0x0, 1, 1, 1)
151#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 1, 1) 151#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1)
152#define MPP21_TDM_FSYNC MPP(21, 0x6, 1, 1, 0) 152#define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0)
153#define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1) 153#define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1)
154 154
155 155
156 156
157#define MPP22_GPIO MPP(22, 0x0, 1, 1, 1) 157#define MPP22_GPIO MPP(22, 0x0, 1, 1, 1)
158#define MPP22_UA3_TDX MPP(22, 0x4, 0, 1, 1) 158#define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1)
159#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 1, 1) 159#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1)
160#define MPP22_TDM_DRX MPP(22, 0x6, 1, 0, 1) 160#define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1)
161#define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1) 161#define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1)
162 162
163 163
164 164
165#define MPP23_GPIO MPP(23, 0x0, 1, 1, 1) 165#define MPP23_GPIO MPP(23, 0x0, 1, 1, 1)
166#define MPP23_UA3_RDX MPP(23, 0x4, 1, 0, 1) 166#define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1)
167#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 1, 1) 167#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1)
168#define MPP23_TDM_DTX MPP(23, 0x6, 0, 1, 1) 168#define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1)
169#define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1) 169#define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1)
170 170
171 171
172#define MPP24_GPIO MPP(24, 0x0, 1, 1, 1) 172#define MPP24_GPIO MPP(24, 0x0, 1, 1, 1)
173#define MPP24_UA2_TXD MPP(24, 0x4, 0, 1, 1) 173#define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1)
174#define MPP24_TDM_INTn MPP(24, 0x6, 1, 0, 1) 174#define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1)
175#define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1) 175#define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1)
176 176
177 177
178#define MPP25_GPIO MPP(25, 0x0, 1, 1, 1) 178#define MPP25_GPIO MPP(25, 0x0, 1, 1, 1)
179#define MPP25_UA2_RXD MPP(25, 0x4, 1, 0, 1) 179#define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1)
180#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 1, 1) 180#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1)
181#define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1) 181#define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1)
182 182
183 183
184#define MPP26_GPIO MPP(26, 0x0, 1, 1, 1) 184#define MPP26_GPIO MPP(26, 0x0, 1, 1, 1)
185#define MPP26_UA2_CTSn MPP(26, 0x4, 1, 0, 1) 185#define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1)
186#define MPP26_TDM_PCLK MPP(26, 0x6, 1, 1, 1) 186#define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1)
187#define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1) 187#define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1)
188 188
189 189
190#define MPP27_GPIO MPP(27, 0x0, 1, 1, 1) 190#define MPP27_GPIO MPP(27, 0x0, 1, 1, 1)
191#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 1, 1) 191#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1)
192#define MPP27_TDM_FSYNC MPP(27, 0x6, 1, 1, 1) 192#define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1)
193#define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1) 193#define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1)
194 194
195 195
196#define MPP28_GPIO MPP(28, 0x0, 1, 1, 1) 196#define MPP28_GPIO MPP(28, 0x0, 1, 1, 1)
197#define MPP28_UA3_TXD MPP(28, 0x4, 0, 1, 1) 197#define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1)
198#define MPP28_TDM_DRX MPP(28, 0x6, 1, 0, 1) 198#define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1)
199#define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1) 199#define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1)
200 200
201#define MPP29_GPIO MPP(29, 0x0, 1, 1, 1) 201#define MPP29_GPIO MPP(29, 0x0, 1, 1, 1)
202#define MPP29_UA3_RXD MPP(29, 0x4, 1, 0, 1) 202#define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1)
203#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 1, 1) 203#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1)
204#define MPP29_TDM_DTX MPP(29, 0x6, 0, 1, 1) 204#define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1)
205#define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1) 205#define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1)
206 206
207#define MPP30_GPIO MPP(30, 0x0, 1, 1, 1) 207#define MPP30_GPIO MPP(30, 0x0, 1, 1, 1)
208#define MPP30_UA3_CTSn MPP(30, 0x4, 1, 0, 1) 208#define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1)
209#define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1) 209#define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1)
210 210
211#define MPP31_GPIO MPP(31, 0x0, 1, 1, 1) 211#define MPP31_GPIO MPP(31, 0x0, 1, 1, 1)
212#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 1, 1) 212#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1)
213#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 1, 1) 213#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1)
214#define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1) 214#define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1)
215 215
216 216
217#define MPP32_GPIO MPP(32, 0x1, 1, 1, 1) 217#define MPP32_GPIO MPP(32, 0x1, 1, 1, 1)
218#define MPP32_UA3_TDX MPP(32, 0x4, 0, 1, 1) 218#define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1)
219#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 1, 1) 219#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1)
220#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 1, 1) 220#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1)
221#define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1) 221#define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1)
222 222
223 223
224#define MPP33_GPIO MPP(33, 0x1, 1, 1, 1) 224#define MPP33_GPIO MPP(33, 0x1, 1, 1, 1)
225#define MPP33_UA3_RDX MPP(33, 0x4, 1, 0, 1) 225#define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1)
226#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 1, 1) 226#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1)
227#define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1) 227#define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1)
228 228
229 229
230 230
231#define MPP34_GPIO MPP(34, 0x1, 1, 1, 1) 231#define MPP34_GPIO MPP(34, 0x1, 1, 1, 1)
232#define MPP34_UA2_TDX MPP(34, 0x4, 0, 1, 1) 232#define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1)
233#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 1, 1) 233#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1)
234#define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1) 234#define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1)
235 235
236 236
237 237
238#define MPP35_GPIO MPP(35, 0x1, 1, 1, 1) 238#define MPP35_GPIO MPP(35, 0x1, 1, 1, 1)
239#define MPP35_UA2_RDX MPP(35, 0x4, 1, 0, 1) 239#define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1)
240#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 1, 1) 240#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1)
241#define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1) 241#define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1)
242 242
243#define MPP36_GPIO MPP(36, 0x1, 1, 1, 1) 243#define MPP36_GPIO MPP(36, 0x1, 1, 1, 1)
244#define MPP36_UA0_CTSn MPP(36, 0x2, 1, 0, 1) 244#define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1)
245#define MPP36_UA2_TDX MPP(36, 0x4, 0, 1, 1) 245#define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1)
246#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 1, 1) 246#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1)
247#define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1) 247#define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1)
248 248
249 249
250#define MPP37_GPIO MPP(37, 0x1, 1, 1, 1) 250#define MPP37_GPIO MPP(37, 0x1, 1, 1, 1)
251#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 1, 1) 251#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1)
252#define MPP37_UA2_RXD MPP(37, 0x4, 1, 0, 1) 252#define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1)
253#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 1, 1) 253#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1)
254#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 1, 1) 254#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1)
255#define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1) 255#define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1)
256 256
257 257
258 258
259 259
260#define MPP38_GPIO MPP(38, 0x1, 1, 1, 1) 260#define MPP38_GPIO MPP(38, 0x1, 1, 1, 1)
261#define MPP38_UA1_CTSn MPP(38, 0x2, 1, 0, 1) 261#define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1)
262#define MPP38_UA3_TXD MPP(38, 0x4, 0, 1, 1) 262#define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1)
263#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 1, 1) 263#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1)
264#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 1, 1) 264#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1)
265#define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1) 265#define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1)
266 266
267 267
268 268
269 269
270#define MPP39_GPIO MPP(39, 0x1, 1, 1, 1) 270#define MPP39_GPIO MPP(39, 0x1, 1, 1, 1)
271#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 1, 1) 271#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1)
272#define MPP39_UA3_RXD MPP(39, 0x4, 1, 0, 1) 272#define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1)
273#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 1, 1) 273#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1)
274#define MPP39_TDM_SMISO MPP(39, 0x6, 1, 0, 1) 274#define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1)
275#define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1) 275#define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1)
276 276
277 277
278 278
279#define MPP40_GPIO MPP(40, 0x1, 1, 1, 1) 279#define MPP40_GPIO MPP(40, 0x1, 1, 1, 1)
280#define MPP40_TDM_INTn MPP(40, 0x6, 1, 0, 1) 280#define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1)
281#define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1) 281#define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1)
282 282
283 283
284 284
285#define MPP41_GPIO MPP(41, 0x1, 1, 1, 1) 285#define MPP41_GPIO MPP(41, 0x1, 1, 1, 1)
286#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 1, 1) 286#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1)
287#define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1) 287#define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1)
288 288
289 289
290 290
291#define MPP42_GPIO MPP(42, 0x1, 1, 1, 1) 291#define MPP42_GPIO MPP(42, 0x1, 1, 1, 1)
292#define MPP42_TDM_PCLK MPP(42, 0x6, 1, 1, 1) 292#define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1)
293#define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1) 293#define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1)
294 294
295 295
296 296
297#define MPP43_GPIO MPP(43, 0x1, 1, 1, 1) 297#define MPP43_GPIO MPP(43, 0x1, 1, 1, 1)
298#define MPP43_TDM_FSYNC MPP(43, 0x6, 1, 1, 1) 298#define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1)
299#define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1) 299#define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1)
300 300
301 301
302 302
303#define MPP44_GPIO MPP(44, 0x1, 1, 1, 1) 303#define MPP44_GPIO MPP(44, 0x1, 1, 1, 1)
304#define MPP44_TDM_DRX MPP(44, 0x6, 1, 0, 1) 304#define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1)
305#define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1) 305#define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1)
306 306
307 307
308 308
309#define MPP45_GPIO MPP(45, 0x1, 1, 1, 1) 309#define MPP45_GPIO MPP(45, 0x1, 1, 1, 1)
310#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 1, 1) 310#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1)
311#define MPP45_TDM_DRX MPP(45, 0x6, 0, 1, 1) 311#define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1)
312#define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1) 312#define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1)
313 313
314 314
315#define MPP46_GPIO MPP(46, 0x1, 1, 1, 1) 315#define MPP46_GPIO MPP(46, 0x1, 1, 1, 1)
316#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 1, 1) 316#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1)
317#define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1) 317#define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1)
318 318
319 319
@@ -323,14 +323,14 @@
323 323
324 324
325#define MPP48_GPIO MPP(48, 0x1, 1, 1, 1) 325#define MPP48_GPIO MPP(48, 0x1, 1, 1, 1)
326#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 1, 1) 326#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1)
327#define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1) 327#define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1)
328 328
329 329
330 330
331#define MPP49_GPIO MPP(49, 0x1, 1, 1, 1) 331#define MPP49_GPIO MPP(49, 0x1, 1, 1, 1)
332#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 1, 1) 332#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1)
333#define MPP49_M_BB MPP(49, 0x4, 1, 0, 1) 333#define MPP49_M_BB MPP(49, 0x4, 0, 0, 1)
334#define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1) 334#define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1)
335 335
336 336
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fc9b238cbc19..bd76394ccaf8 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -11,9 +11,9 @@ hwmod-common = omap_hwmod.o \
11 omap_hwmod_common_data.o 11 omap_hwmod_common_data.o
12clock-common = clock.o clock_common_data.o \ 12clock-common = clock.o clock_common_data.o \
13 clkt_dpll.o clkt_clksel.o 13 clkt_dpll.o clkt_clksel.o
14secure-common = omap-smc.o omap-secure.o 14secure-common = omap-smc.o omap-secure.o
15 15
16obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common) 16obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
17obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) 17obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
18obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) 18obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
19 19
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index e921e3be24a4..d73316ed4207 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -437,7 +437,7 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
437 .reset_gpio_port[2] = -EINVAL 437 .reset_gpio_port[2] = -EINVAL
438}; 438};
439 439
440static void cm_t35_init_usbh(void) 440static void __init cm_t35_init_usbh(void)
441{ 441{
442 int err; 442 int err;
443 443
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index d58756060483..ad497620539b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -17,6 +17,7 @@
17#include <linux/i2c/twl.h> 17#include <linux/i2c/twl.h>
18 18
19#include <mach/hardware.h> 19#include <mach/hardware.h>
20#include <asm/hardware/gic.h>
20#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
21 22
22#include <plat/board.h> 23#include <plat/board.h>
@@ -102,6 +103,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
102 .map_io = omap242x_map_io, 103 .map_io = omap242x_map_io,
103 .init_early = omap2420_init_early, 104 .init_early = omap2420_init_early,
104 .init_irq = omap2_init_irq, 105 .init_irq = omap2_init_irq,
106 .handle_irq = omap2_intc_handle_irq,
105 .init_machine = omap_generic_init, 107 .init_machine = omap_generic_init,
106 .timer = &omap2_timer, 108 .timer = &omap2_timer,
107 .dt_compat = omap242x_boards_compat, 109 .dt_compat = omap242x_boards_compat,
@@ -141,6 +143,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
141 .map_io = omap3_map_io, 143 .map_io = omap3_map_io,
142 .init_early = omap3430_init_early, 144 .init_early = omap3430_init_early,
143 .init_irq = omap3_init_irq, 145 .init_irq = omap3_init_irq,
146 .handle_irq = omap3_intc_handle_irq,
144 .init_machine = omap3_init, 147 .init_machine = omap3_init,
145 .timer = &omap3_timer, 148 .timer = &omap3_timer,
146 .dt_compat = omap3_boards_compat, 149 .dt_compat = omap3_boards_compat,
@@ -160,6 +163,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
160 .map_io = omap4_map_io, 163 .map_io = omap4_map_io,
161 .init_early = omap4430_init_early, 164 .init_early = omap4430_init_early,
162 .init_irq = gic_init_irq, 165 .init_irq = gic_init_irq,
166 .handle_irq = gic_handle_irq,
163 .init_machine = omap4_init, 167 .init_machine = omap4_init,
164 .timer = &omap4_timer, 168 .timer = &omap4_timer,
165 .dt_compat = omap4_boards_compat, 169 .dt_compat = omap4_boards_compat,
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index b8822f8b2891..23de98d03841 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -82,13 +82,7 @@ static int omap2_fclks_active(void)
82 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 82 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
83 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); 83 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
84 84
85 /* Ignore UART clocks. These are handled by UART core (serial.c) */ 85 return (f1 | f2) ? 1 : 0;
86 f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
87 f2 &= ~OMAP24XX_EN_UART3_MASK;
88
89 if (f1 | f2)
90 return 1;
91 return 0;
92} 86}
93 87
94static void omap2_enter_full_retention(void) 88static void omap2_enter_full_retention(void)
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 0e28bae20bd4..5dad38ec00ea 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -29,6 +29,7 @@
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <mach/orion5x.h> 30#include <mach/orion5x.h>
31#include <plat/orion_nand.h> 31#include <plat/orion_nand.h>
32#include <plat/ehci-orion.h>
32#include <plat/time.h> 33#include <plat/time.h>
33#include <plat/common.h> 34#include <plat/common.h>
34#include <plat/addr-map.h> 35#include <plat/addr-map.h>
@@ -72,7 +73,8 @@ void __init orion5x_map_io(void)
72 ****************************************************************************/ 73 ****************************************************************************/
73void __init orion5x_ehci0_init(void) 74void __init orion5x_ehci0_init(void)
74{ 75{
75 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); 76 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
77 EHCI_PHY_ORION);
76} 78}
77 79
78 80
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c
index 7dc6c46b5e2b..5404535da1a5 100644
--- a/arch/arm/mach-s3c2410/cpu-freq.c
+++ b/arch/arm/mach-s3c2410/cpu-freq.c
@@ -115,7 +115,8 @@ static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
115 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), 115 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
116}; 116};
117 117
118static int s3c2410_cpufreq_add(struct device *dev) 118static int s3c2410_cpufreq_add(struct device *dev,
119 struct subsys_interface *sif)
119{ 120{
120 return s3c_cpufreq_register(&s3c2410_cpufreq_info); 121 return s3c_cpufreq_register(&s3c2410_cpufreq_info);
121} 122}
@@ -133,7 +134,8 @@ static int __init s3c2410_cpufreq_init(void)
133 134
134arch_initcall(s3c2410_cpufreq_init); 135arch_initcall(s3c2410_cpufreq_init);
135 136
136static int s3c2410a_cpufreq_add(struct device *dev) 137static int s3c2410a_cpufreq_add(struct device *dev,
138 struct subsys_interface *sif)
137{ 139{
138 /* alter the maximum freq settings for S3C2410A. If a board knows 140 /* alter the maximum freq settings for S3C2410A. If a board knows
139 * it only has a maximum of 200, then it should register its own 141 * it only has a maximum of 200, then it should register its own
@@ -144,7 +146,7 @@ static int s3c2410a_cpufreq_add(struct device *dev)
144 s3c2410_cpufreq_info.max.pclk = 66500000; 146 s3c2410_cpufreq_info.max.pclk = 66500000;
145 s3c2410_cpufreq_info.name = "s3c2410a"; 147 s3c2410_cpufreq_info.name = "s3c2410a";
146 148
147 return s3c2410_cpufreq_add(dev); 149 return s3c2410_cpufreq_add(dev, sif);
148} 150}
149 151
150static struct subsys_interface s3c2410a_cpufreq_interface = { 152static struct subsys_interface s3c2410a_cpufreq_interface = {
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 2afd00014a77..4803338cf56e 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -132,7 +132,8 @@ static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
132 }, 132 },
133}; 133};
134 134
135static int __init s3c2410_dma_add(struct device *dev) 135static int __init s3c2410_dma_add(struct device *dev,
136 struct subsys_interface *sif)
136{ 137{
137 s3c2410_dma_init(); 138 s3c2410_dma_init();
138 s3c24xx_dma_order_set(&s3c2410_dma_order); 139 s3c24xx_dma_order_set(&s3c2410_dma_order);
@@ -148,7 +149,7 @@ static struct subsys_interface s3c2410_dma_interface = {
148 149
149static int __init s3c2410_dma_drvinit(void) 150static int __init s3c2410_dma_drvinit(void)
150{ 151{
151 return subsys_interface_register(&s3c2410_interface); 152 return subsys_interface_register(&s3c2410_dma_interface);
152} 153}
153 154
154arch_initcall(s3c2410_dma_drvinit); 155arch_initcall(s3c2410_dma_drvinit);
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c
index c07438bfc99f..e0b3b347da82 100644
--- a/arch/arm/mach-s3c2410/pll.c
+++ b/arch/arm/mach-s3c2410/pll.c
@@ -66,7 +66,7 @@ static struct cpufreq_frequency_table pll_vals_12MHz[] = {
66 { .frequency = 270000000, .index = PLLVAL(127, 1, 1), }, 66 { .frequency = 270000000, .index = PLLVAL(127, 1, 1), },
67}; 67};
68 68
69static int s3c2410_plls_add(struct device *dev) 69static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
70{ 70{
71 return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz)); 71 return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
72} 72}
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index fda5385deff6..03f706dd6009 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -111,7 +111,7 @@ struct syscore_ops s3c2410_pm_syscore_ops = {
111 .resume = s3c2410_pm_resume, 111 .resume = s3c2410_pm_resume,
112}; 112};
113 113
114static int s3c2410_pm_add(struct device *dev) 114static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif)
115{ 115{
116 pm_cpu_prep = s3c2410_pm_prepare; 116 pm_cpu_prep = s3c2410_pm_prepare;
117 pm_cpu_sleep = s3c2410_cpu_suspend; 117 pm_cpu_sleep = s3c2410_cpu_suspend;
diff --git a/arch/arm/mach-s3c2412/cpu-freq.c b/arch/arm/mach-s3c2412/cpu-freq.c
index d8664b7652ce..125be7d5fa60 100644
--- a/arch/arm/mach-s3c2412/cpu-freq.c
+++ b/arch/arm/mach-s3c2412/cpu-freq.c
@@ -194,7 +194,8 @@ static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
194 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs), 194 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
195}; 195};
196 196
197static int s3c2412_cpufreq_add(struct device *dev) 197static int s3c2412_cpufreq_add(struct device *dev,
198 struct subsys_interface *sif)
198{ 199{
199 unsigned long fclk_rate; 200 unsigned long fclk_rate;
200 201
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 142acd3b5e15..38472ac920ff 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -159,7 +159,8 @@ static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
159 .map_size = ARRAY_SIZE(s3c2412_dma_mappings), 159 .map_size = ARRAY_SIZE(s3c2412_dma_mappings),
160}; 160};
161 161
162static int __init s3c2412_dma_add(struct device *dev) 162static int __init s3c2412_dma_add(struct device *dev,
163 struct subsys_interface *sif)
163{ 164{
164 s3c2410_dma_init(); 165 s3c2410_dma_init();
165 return s3c24xx_dma_init_map(&s3c2412_dma_sel); 166 return s3c24xx_dma_init_map(&s3c2412_dma_sel);
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
index a8a46c1644f4..e65619ddbccc 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -170,7 +170,7 @@ static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
170 170
171static struct irq_chip s3c2412_irq_rtc_chip; 171static struct irq_chip s3c2412_irq_rtc_chip;
172 172
173static int s3c2412_irq_add(struct device *dev) 173static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
174{ 174{
175 unsigned int irqno; 175 unsigned int irqno;
176 176
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index d1adfa65f66d..d04588506ec4 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -56,7 +56,7 @@ static void s3c2412_pm_prepare(void)
56{ 56{
57} 57}
58 58
59static int s3c2412_pm_add(struct device *dev) 59static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif)
60{ 60{
61 pm_cpu_prep = s3c2412_pm_prepare; 61 pm_cpu_prep = s3c2412_pm_prepare;
62 pm_cpu_sleep = s3c2412_cpu_suspend; 62 pm_cpu_sleep = s3c2412_cpu_suspend;
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
index 36df761061de..fd49f35e448e 100644
--- a/arch/arm/mach-s3c2416/irq.c
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -213,7 +213,8 @@ static int __init s3c2416_add_sub(unsigned int base,
213 return 0; 213 return 0;
214} 214}
215 215
216static int __init s3c2416_irq_add(struct device *dev) 216static int __init s3c2416_irq_add(struct device *dev,
217 struct subsys_interface *sif)
217{ 218{
218 printk(KERN_INFO "S3C2416: IRQ Support\n"); 219 printk(KERN_INFO "S3C2416: IRQ Support\n");
219 220
diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c
index 3bdb15a0d419..1bd4817b8eb8 100644
--- a/arch/arm/mach-s3c2416/pm.c
+++ b/arch/arm/mach-s3c2416/pm.c
@@ -48,7 +48,7 @@ static void s3c2416_pm_prepare(void)
48 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); 48 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
49} 49}
50 50
51static int s3c2416_pm_add(struct device *dev) 51static int s3c2416_pm_add(struct device *dev, struct subsys_interface *sif)
52{ 52{
53 pm_cpu_prep = s3c2416_pm_prepare; 53 pm_cpu_prep = s3c2416_pm_prepare;
54 pm_cpu_sleep = s3c2416_cpu_suspend; 54 pm_cpu_sleep = s3c2416_cpu_suspend;
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index bedbc87a3426..414364eb426c 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -149,7 +149,7 @@ static struct clk_lookup s3c2440_clk_lookup[] = {
149 CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n), 149 CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
150}; 150};
151 151
152static int s3c2440_clk_add(struct device *dev) 152static int s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
153{ 153{
154 struct clk *clock_upll; 154 struct clk *clock_upll;
155 struct clk *clock_h; 155 struct clk *clock_h;
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 15b1ddf8f626..5f0a0c8ef84f 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -174,7 +174,8 @@ static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
174 }, 174 },
175}; 175};
176 176
177static int __init s3c2440_dma_add(struct device *dev) 177static int __init s3c2440_dma_add(struct device *dev,
178 struct subsys_interface *sif)
178{ 179{
179 s3c2410_dma_init(); 180 s3c2410_dma_init();
180 s3c24xx_dma_order_set(&s3c2440_dma_order); 181 s3c24xx_dma_order_set(&s3c2440_dma_order);
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index 4fee9bc6bcb5..4a18cde439cc 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -92,7 +92,7 @@ static struct irq_chip s3c_irq_wdtac97 = {
92 .irq_ack = s3c_irq_wdtac97_ack, 92 .irq_ack = s3c_irq_wdtac97_ack,
93}; 93};
94 94
95static int s3c2440_irq_add(struct device *dev) 95static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif)
96{ 96{
97 unsigned int irqno; 97 unsigned int irqno;
98 98
diff --git a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c b/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
index cf7596694efe..61776764d9f4 100644
--- a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
+++ b/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
@@ -270,7 +270,8 @@ struct s3c_cpufreq_info s3c2440_cpufreq_info = {
270 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), 270 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
271}; 271};
272 272
273static int s3c2440_cpufreq_add(struct device *dev) 273static int s3c2440_cpufreq_add(struct device *dev,
274 struct subsys_interface *sif)
274{ 275{
275 xtal = s3c_cpufreq_clk_get(NULL, "xtal"); 276 xtal = s3c_cpufreq_clk_get(NULL, "xtal");
276 hclk = s3c_cpufreq_clk_get(NULL, "hclk"); 277 hclk = s3c_cpufreq_clk_get(NULL, "hclk");
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
index b5368ae8d7fe..551fb433be87 100644
--- a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
+++ b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
@@ -51,7 +51,7 @@ static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
51 { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ 51 { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */
52}; 52};
53 53
54static int s3c2440_plls12_add(struct device *dev) 54static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
55{ 55{
56 struct clk *xtal_clk; 56 struct clk *xtal_clk;
57 unsigned long xtal; 57 unsigned long xtal;
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
index 42f2b5cd2399..3f15bcf64290 100644
--- a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
+++ b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
@@ -79,7 +79,8 @@ static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
79 { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ 79 { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */
80}; 80};
81 81
82static int s3c2440_plls169344_add(struct device *dev) 82static int s3c2440_plls169344_add(struct device *dev,
83 struct subsys_interface *sif)
83{ 84{
84 struct clk *xtal_clk; 85 struct clk *xtal_clk;
85 unsigned long xtal; 86 unsigned long xtal;
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c
index 8004e0497bf4..22cb7c94a8c8 100644
--- a/arch/arm/mach-s3c2440/s3c2442.c
+++ b/arch/arm/mach-s3c2440/s3c2442.c
@@ -122,7 +122,7 @@ static struct clk s3c2442_clk_cam_upll = {
122 }, 122 },
123}; 123};
124 124
125static int s3c2442_clk_add(struct device *dev) 125static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif)
126{ 126{
127 struct clk *clock_upll; 127 struct clk *clock_upll;
128 struct clk *clock_h; 128 struct clk *clock_h;
diff --git a/arch/arm/mach-s3c2440/s3c244x-clock.c b/arch/arm/mach-s3c2440/s3c244x-clock.c
index b3fdbdda3d5f..6d9b688c442b 100644
--- a/arch/arm/mach-s3c2440/s3c244x-clock.c
+++ b/arch/arm/mach-s3c2440/s3c244x-clock.c
@@ -72,7 +72,7 @@ static struct clk clk_arm = {
72 }, 72 },
73}; 73};
74 74
75static int s3c244x_clk_add(struct device *dev) 75static int s3c244x_clk_add(struct device *dev, struct subsys_interface *sif)
76{ 76{
77 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); 77 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
78 unsigned long clkdivn; 78 unsigned long clkdivn;
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c
index 74d3dcf46a48..5fe8e58d3afd 100644
--- a/arch/arm/mach-s3c2440/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2440/s3c244x-irq.c
@@ -91,7 +91,7 @@ static struct irq_chip s3c_irq_cam = {
91 .irq_ack = s3c_irq_cam_ack, 91 .irq_ack = s3c_irq_cam_ack,
92}; 92};
93 93
94static int s3c244x_irq_add(struct device *dev) 94static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif)
95{ 95{
96 unsigned int irqno; 96 unsigned int irqno;
97 97
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index de6b4a23c9ed..14224517e621 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -135,7 +135,8 @@ static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
135 .map_size = ARRAY_SIZE(s3c2443_dma_mappings), 135 .map_size = ARRAY_SIZE(s3c2443_dma_mappings),
136}; 136};
137 137
138static int __init s3c2443_dma_add(struct device *dev) 138static int __init s3c2443_dma_add(struct device *dev,
139 struct subsys_interface *sif)
139{ 140{
140 s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100); 141 s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
141 return s3c24xx_dma_init_map(&s3c2443_dma_sel); 142 return s3c24xx_dma_init_map(&s3c2443_dma_sel);
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
index 35e4ff24fb43..ac2829f56d12 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c2443/irq.c
@@ -241,7 +241,8 @@ static int __init s3c2443_add_sub(unsigned int base,
241 return 0; 241 return 0;
242} 242}
243 243
244static int __init s3c2443_irq_add(struct device *dev) 244static int __init s3c2443_irq_add(struct device *dev,
245 struct subsys_interface *sif)
245{ 246{
246 printk("S3C2443: IRQ Support\n"); 247 printk("S3C2443: IRQ Support\n");
247 248
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 31bb27dc4aeb..aebbcc291b4e 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -138,6 +138,11 @@ static struct clk init_clocks_off[] = {
138 .ctrlbit = S3C_CLKCON_PCLK_TSADC, 138 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
139 }, { 139 }, {
140 .name = "i2c", 140 .name = "i2c",
141#ifdef CONFIG_S3C_DEV_I2C1
142 .devname = "s3c2440-i2c.0",
143#else
144 .devname = "s3c2440-i2c",
145#endif
141 .parent = &clk_p, 146 .parent = &clk_p,
142 .enable = s3c64xx_pclk_ctrl, 147 .enable = s3c64xx_pclk_ctrl,
143 .ctrlbit = S3C_CLKCON_PCLK_IIC, 148 .ctrlbit = S3C_CLKCON_PCLK_IIC,
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 4a7394d4bd9e..bee7dcd4df7c 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -49,7 +49,7 @@
49 49
50/* uart registration process */ 50/* uart registration process */
51 51
52void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) 52static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
53{ 53{
54 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); 54 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
55} 55}
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
index 23f9b22439c9..9cba18bfe47b 100644
--- a/arch/arm/mach-s5p64x0/pm.c
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -160,7 +160,7 @@ static void s5p64x0_pm_prepare(void)
160 160
161} 161}
162 162
163static int s5p64x0_pm_add(struct device *dev) 163static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif)
164{ 164{
165 pm_cpu_prep = s5p64x0_pm_prepare; 165 pm_cpu_prep = s5p64x0_pm_prepare;
166 pm_cpu_sleep = s5p64x0_cpu_suspend; 166 pm_cpu_sleep = s5p64x0_cpu_suspend;
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index c78dfddd77fd..b9ec0c35379f 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -175,7 +175,7 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
175 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); 175 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
176} 176}
177 177
178static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) 178static int s5pv210_clk_hdmiphy_ctrl(struct clk *clk, int enable)
179{ 179{
180 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); 180 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
181} 181}
@@ -372,7 +372,7 @@ static struct clk init_clocks_off[] = {
372 }, { 372 }, {
373 .name = "hdmiphy", 373 .name = "hdmiphy",
374 .devname = "s5pv210-hdmi", 374 .devname = "s5pv210-hdmi",
375 .enable = exynos4_clk_hdmiphy_ctrl, 375 .enable = s5pv210_clk_hdmiphy_ctrl,
376 .ctrlbit = (1 << 0), 376 .ctrlbit = (1 << 0),
377 }, { 377 }, {
378 .name = "dacphy", 378 .name = "dacphy",
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 677c71c41e50..736bfb103cbc 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -133,7 +133,7 @@ static void s5pv210_pm_prepare(void)
133 s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); 133 s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
134} 134}
135 135
136static int s5pv210_pm_add(struct device *dev) 136static int s5pv210_pm_add(struct device *dev, struct subsys_interface *sif)
137{ 137{
138 pm_cpu_prep = s5pv210_pm_prepare; 138 pm_cpu_prep = s5pv210_pm_prepare;
139 pm_cpu_sleep = s5pv210_cpu_suspend; 139 pm_cpu_sleep = s5pv210_cpu_suspend;
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index fcf4f377b1dc..330afdfa2475 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -60,9 +60,9 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
60 .uartclk = 216000000, 60 .uartclk = 216000000,
61 }, { 61 }, {
62 /* serial port on mini-pcie */ 62 /* serial port on mini-pcie */
63 .membase = IO_ADDRESS(TEGRA_UARTD_BASE), 63 .membase = IO_ADDRESS(TEGRA_UARTC_BASE),
64 .mapbase = TEGRA_UARTD_BASE, 64 .mapbase = TEGRA_UARTC_BASE,
65 .irq = INT_UARTD, 65 .irq = INT_UARTC,
66 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, 66 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
67 .type = PORT_TEGRA, 67 .type = PORT_TEGRA,
68 .iotype = UPIO_MEM, 68 .iotype = UPIO_MEM,
@@ -174,7 +174,7 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
174static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { 174static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
175 /* name parent rate enabled */ 175 /* name parent rate enabled */
176 { "uarta", "pll_p", 216000000, true }, 176 { "uarta", "pll_p", 216000000, true },
177 { "uartd", "pll_p", 216000000, true }, 177 { "uartc", "pll_p", 216000000, true },
178 178
179 { "pll_p_out4", "pll_p", 24000000, true }, 179 { "pll_p_out4", "pll_p", 24000000, true },
180 { "usbd", "clk_m", 12000000, false }, 180 { "usbd", "clk_m", 12000000, false },
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index ffa83f580db6..3c9f8da37ea3 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -22,7 +22,7 @@
22/* SDCARD */ 22/* SDCARD */
23#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 23#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5
24#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 24#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1
25#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3 25#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PV1
26 26
27/* ULPI */ 27/* ULPI */
28#define TEGRA_ULPI_RST TEGRA_GPIO_PV0 28#define TEGRA_ULPI_RST TEGRA_GPIO_PV0
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index d0132e8031a1..3c9339058bec 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -23,11 +23,6 @@
23 23
24#include <linux/list.h> 24#include <linux/list.h>
25 25
26#if defined(CONFIG_TEGRA_SYSTEM_DMA)
27
28struct tegra_dma_req;
29struct tegra_dma_channel;
30
31#define TEGRA_DMA_REQ_SEL_CNTR 0 26#define TEGRA_DMA_REQ_SEL_CNTR 0
32#define TEGRA_DMA_REQ_SEL_I2S_2 1 27#define TEGRA_DMA_REQ_SEL_I2S_2 1
33#define TEGRA_DMA_REQ_SEL_I2S_1 2 28#define TEGRA_DMA_REQ_SEL_I2S_1 2
@@ -56,6 +51,11 @@ struct tegra_dma_channel;
56#define TEGRA_DMA_REQ_SEL_OWR 25 51#define TEGRA_DMA_REQ_SEL_OWR 25
57#define TEGRA_DMA_REQ_SEL_INVALID 31 52#define TEGRA_DMA_REQ_SEL_INVALID 31
58 53
54#if defined(CONFIG_TEGRA_SYSTEM_DMA)
55
56struct tegra_dma_req;
57struct tegra_dma_channel;
58
59enum tegra_dma_mode { 59enum tegra_dma_mode {
60 TEGRA_DMA_SHARED = 1, 60 TEGRA_DMA_SHARED = 1,
61 TEGRA_DMA_MODE_CONTINOUS = 2, 61 TEGRA_DMA_MODE_CONTINOUS = 2,
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
index 64f9d1c7f1bb..3047ff923a63 100644
--- a/arch/arm/plat-omap/include/plat/omap-secure.h
+++ b/arch/arm/plat-omap/include/plat/omap-secure.h
@@ -3,7 +3,7 @@
3 3
4#include <linux/types.h> 4#include <linux/types.h>
5 5
6#ifdef CONFIG_ARCH_OMAP2PLUS 6#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
7extern int omap_secure_ram_reserve_memblock(void); 7extern int omap_secure_ram_reserve_memblock(void);
8#else 8#else
9static inline void omap_secure_ram_reserve_memblock(void) 9static inline void omap_secure_ram_reserve_memblock(void)
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index e5a2fde29b19..089899a7db72 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -789,10 +789,7 @@ void __init orion_xor1_init(unsigned long mapbase_low,
789/***************************************************************************** 789/*****************************************************************************
790 * EHCI 790 * EHCI
791 ****************************************************************************/ 791 ****************************************************************************/
792static struct orion_ehci_data orion_ehci_data = { 792static struct orion_ehci_data orion_ehci_data;
793 .phy_version = EHCI_PHY_NA,
794};
795
796static u64 ehci_dmamask = DMA_BIT_MASK(32); 793static u64 ehci_dmamask = DMA_BIT_MASK(32);
797 794
798 795
@@ -812,8 +809,10 @@ static struct platform_device orion_ehci = {
812}; 809};
813 810
814void __init orion_ehci_init(unsigned long mapbase, 811void __init orion_ehci_init(unsigned long mapbase,
815 unsigned long irq) 812 unsigned long irq,
813 enum orion_ehci_phy_ver phy_version)
816{ 814{
815 orion_ehci_data.phy_version = phy_version;
817 fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, 816 fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
818 irq); 817 irq);
819 818
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index 0fe08d77e835..a7fa005a5a0e 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -89,7 +89,8 @@ void __init orion_xor1_init(unsigned long mapbase_low,
89 unsigned long irq_1); 89 unsigned long irq_1);
90 90
91void __init orion_ehci_init(unsigned long mapbase, 91void __init orion_ehci_init(unsigned long mapbase,
92 unsigned long irq); 92 unsigned long irq,
93 enum orion_ehci_phy_ver phy_version);
93 94
94void __init orion_ehci_1_init(unsigned long mapbase, 95void __init orion_ehci_1_init(unsigned long mapbase,
95 unsigned long irq); 96 unsigned long irq);
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
index 91553432711d..3b1e17bd3d17 100644
--- a/arch/arm/plat-orion/mpp.c
+++ b/arch/arm/plat-orion/mpp.c
@@ -64,8 +64,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
64 gpio_mode |= GPIO_INPUT_OK; 64 gpio_mode |= GPIO_INPUT_OK;
65 if (*mpp_list & MPP_OUTPUT_MASK) 65 if (*mpp_list & MPP_OUTPUT_MASK)
66 gpio_mode |= GPIO_OUTPUT_OK; 66 gpio_mode |= GPIO_OUTPUT_OK;
67 if (sel != 0) 67
68 gpio_mode = 0;
69 orion_gpio_set_valid(num, gpio_mode); 68 orion_gpio_set_valid(num, gpio_mode);
70 } 69 }
71 70
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 32a6e394db24..f10768e988d4 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -468,8 +468,10 @@ void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
468{ 468{
469 struct s3c2410_platform_i2c *npd; 469 struct s3c2410_platform_i2c *npd;
470 470
471 if (!pd) 471 if (!pd) {
472 pd = &default_i2c_data; 472 pd = &default_i2c_data;
473 pd->bus_num = 0;
474 }
473 475
474 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), 476 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
475 &s3c_device_i2c0); 477 &s3c_device_i2c0);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 02:52:23 -0500