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authorTony Lindgren <tony@atomide.com>2011-11-23 17:57:37 -0500
committerTony Lindgren <tony@atomide.com>2011-11-23 17:57:37 -0500
commitb079d671f88322733010082a590f59885eafd62e (patch)
tree6e824cdc1f62da9516ebc2f851229b6535a33028 /arch/arm
parentcfcfc9eca2bcbd26a8e206baeb005b055dbf8e37 (diff)
parentb923d40dd4211c4ef7d4efa2bd81b7ca1d8744c1 (diff)
Merge branch 'hwmod_dss_fixes_3.2rc' of git://git.pwsan.com/linux-2.6 into fixes-dss
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/Makefile5
-rw-r--r--arch/arm/mach-omap2/display.c159
-rw-r--r--arch/arm/mach-omap2/display.h29
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c17
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c17
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c5
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c37
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c24
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.c4
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h4
-rw-r--r--arch/arm/plat-omap/include/plat/common.h3
11 files changed, 276 insertions, 28 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 69ab1c069134..b009f17dee56 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
4 4
5# Common support 5# Common support
6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \ 6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
7 common.o gpio.o dma.o wd_timer.o 7 common.o gpio.o dma.o wd_timer.o display.o
8 8
9omap-2-3-common = irq.o sdrc.o 9omap-2-3-common = irq.o sdrc.o
10hwmod-common = omap_hwmod.o \ 10hwmod-common = omap_hwmod.o \
@@ -264,7 +264,4 @@ smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
264obj-y += $(smsc911x-m) $(smsc911x-y) 264obj-y += $(smsc911x-m) $(smsc911x-y)
265obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o 265obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
266 266
267disp-$(CONFIG_OMAP2_DSS) := display.o
268obj-y += $(disp-m) $(disp-y)
269
270obj-y += common-board-devices.o twl-common.o 267obj-y += common-board-devices.o twl-common.o
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index adb2756e242f..dce9905d64bb 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -27,8 +27,35 @@
27#include <plat/omap_hwmod.h> 27#include <plat/omap_hwmod.h>
28#include <plat/omap_device.h> 28#include <plat/omap_device.h>
29#include <plat/omap-pm.h> 29#include <plat/omap-pm.h>
30#include <plat/common.h>
30 31
31#include "control.h" 32#include "control.h"
33#include "display.h"
34
35#define DISPC_CONTROL 0x0040
36#define DISPC_CONTROL2 0x0238
37#define DISPC_IRQSTATUS 0x0018
38
39#define DSS_SYSCONFIG 0x10
40#define DSS_SYSSTATUS 0x14
41#define DSS_CONTROL 0x40
42#define DSS_SDI_CONTROL 0x44
43#define DSS_PLL_CONTROL 0x48
44
45#define LCD_EN_MASK (0x1 << 0)
46#define DIGIT_EN_MASK (0x1 << 1)
47
48#define FRAMEDONE_IRQ_SHIFT 0
49#define EVSYNC_EVEN_IRQ_SHIFT 2
50#define EVSYNC_ODD_IRQ_SHIFT 3
51#define FRAMEDONE2_IRQ_SHIFT 22
52#define FRAMEDONETV_IRQ_SHIFT 24
53
54/*
55 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
56 * reset before deciding that something has gone wrong
57 */
58#define FRAMEDONE_IRQ_TIMEOUT 100
32 59
33static struct platform_device omap_display_device = { 60static struct platform_device omap_display_device = {
34 .name = "omapdss", 61 .name = "omapdss",
@@ -172,3 +199,135 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
172 199
173 return r; 200 return r;
174} 201}
202
203static void dispc_disable_outputs(void)
204{
205 u32 v, irq_mask = 0;
206 bool lcd_en, digit_en, lcd2_en = false;
207 int i;
208 struct omap_dss_dispc_dev_attr *da;
209 struct omap_hwmod *oh;
210
211 oh = omap_hwmod_lookup("dss_dispc");
212 if (!oh) {
213 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
214 return;
215 }
216
217 if (!oh->dev_attr) {
218 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
219 return;
220 }
221
222 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
223
224 /* store value of LCDENABLE and DIGITENABLE bits */
225 v = omap_hwmod_read(oh, DISPC_CONTROL);
226 lcd_en = v & LCD_EN_MASK;
227 digit_en = v & DIGIT_EN_MASK;
228
229 /* store value of LCDENABLE for LCD2 */
230 if (da->manager_count > 2) {
231 v = omap_hwmod_read(oh, DISPC_CONTROL2);
232 lcd2_en = v & LCD_EN_MASK;
233 }
234
235 if (!(lcd_en | digit_en | lcd2_en))
236 return; /* no managers currently enabled */
237
238 /*
239 * If any manager was enabled, we need to disable it before
240 * DSS clocks are disabled or DISPC module is reset
241 */
242 if (lcd_en)
243 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
244
245 if (digit_en) {
246 if (da->has_framedonetv_irq) {
247 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
248 } else {
249 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
250 1 << EVSYNC_ODD_IRQ_SHIFT;
251 }
252 }
253
254 if (lcd2_en)
255 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
256
257 /*
258 * clear any previous FRAMEDONE, FRAMEDONETV,
259 * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
260 */
261 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
262
263 /* disable LCD and TV managers */
264 v = omap_hwmod_read(oh, DISPC_CONTROL);
265 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
266 omap_hwmod_write(v, oh, DISPC_CONTROL);
267
268 /* disable LCD2 manager */
269 if (da->manager_count > 2) {
270 v = omap_hwmod_read(oh, DISPC_CONTROL2);
271 v &= ~LCD_EN_MASK;
272 omap_hwmod_write(v, oh, DISPC_CONTROL2);
273 }
274
275 i = 0;
276 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
277 irq_mask) {
278 i++;
279 if (i > FRAMEDONE_IRQ_TIMEOUT) {
280 pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
281 break;
282 }
283 mdelay(1);
284 }
285}
286
287#define MAX_MODULE_SOFTRESET_WAIT 10000
288int omap_dss_reset(struct omap_hwmod *oh)
289{
290 struct omap_hwmod_opt_clk *oc;
291 int c = 0;
292 int i, r;
293
294 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
295 pr_err("dss_core: hwmod data doesn't contain reset data\n");
296 return -EINVAL;
297 }
298
299 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
300 if (oc->_clk)
301 clk_enable(oc->_clk);
302
303 dispc_disable_outputs();
304
305 /* clear SDI registers */
306 if (cpu_is_omap3430()) {
307 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
308 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
309 }
310
311 /*
312 * clear DSS_CONTROL register to switch DSS clock sources to
313 * PRCM clock, if any
314 */
315 omap_hwmod_write(0x0, oh, DSS_CONTROL);
316
317 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
318 & SYSS_RESETDONE_MASK),
319 MAX_MODULE_SOFTRESET_WAIT, c);
320
321 if (c == MAX_MODULE_SOFTRESET_WAIT)
322 pr_warning("dss_core: waiting for reset to finish failed\n");
323 else
324 pr_debug("dss_core: softreset done\n");
325
326 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
327 if (oc->_clk)
328 clk_disable(oc->_clk);
329
330 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
331
332 return r;
333}
diff --git a/arch/arm/mach-omap2/display.h b/arch/arm/mach-omap2/display.h
new file mode 100644
index 000000000000..b871b017b352
--- /dev/null
+++ b/arch/arm/mach-omap2/display.h
@@ -0,0 +1,29 @@
1/*
2 * display.h - OMAP2+ integration-specific DSS header
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifndef __ARCH_ARM_MACH_OMAP2_DISPLAY_H
20#define __ARCH_ARM_MACH_OMAP2_DISPLAY_H
21
22#include <linux/kernel.h>
23
24struct omap_dss_dispc_dev_attr {
25 u8 manager_count;
26 bool has_framedonetv_irq;
27};
28
29#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 6d7206213525..a5409ce3f323 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -875,6 +875,10 @@ static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
875}; 875};
876 876
877static struct omap_hwmod_opt_clk dss_opt_clks[] = { 877static struct omap_hwmod_opt_clk dss_opt_clks[] = {
878 /*
879 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
880 * driver does not use these clocks.
881 */
878 { .role = "tv_clk", .clk = "dss_54m_fck" }, 882 { .role = "tv_clk", .clk = "dss_54m_fck" },
879 { .role = "sys_clk", .clk = "dss2_fck" }, 883 { .role = "sys_clk", .clk = "dss2_fck" },
880}; 884};
@@ -899,7 +903,7 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
899 .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), 903 .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
900 .masters = omap2420_dss_masters, 904 .masters = omap2420_dss_masters,
901 .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), 905 .masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
902 .flags = HWMOD_NO_IDLEST, 906 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
903}; 907};
904 908
905/* l4_core -> dss_dispc */ 909/* l4_core -> dss_dispc */
@@ -939,6 +943,7 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
939 .slaves = omap2420_dss_dispc_slaves, 943 .slaves = omap2420_dss_dispc_slaves,
940 .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), 944 .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
941 .flags = HWMOD_NO_IDLEST, 945 .flags = HWMOD_NO_IDLEST,
946 .dev_attr = &omap2_3_dss_dispc_dev_attr
942}; 947};
943 948
944/* l4_core -> dss_rfbi */ 949/* l4_core -> dss_rfbi */
@@ -961,6 +966,10 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
961 &omap2420_l4_core__dss_rfbi, 966 &omap2420_l4_core__dss_rfbi,
962}; 967};
963 968
969static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
970 { .role = "ick", .clk = "dss_ick" },
971};
972
964static struct omap_hwmod omap2420_dss_rfbi_hwmod = { 973static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
965 .name = "dss_rfbi", 974 .name = "dss_rfbi",
966 .class = &omap2_rfbi_hwmod_class, 975 .class = &omap2_rfbi_hwmod_class,
@@ -972,6 +981,8 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
972 .module_offs = CORE_MOD, 981 .module_offs = CORE_MOD,
973 }, 982 },
974 }, 983 },
984 .opt_clks = dss_rfbi_opt_clks,
985 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
975 .slaves = omap2420_dss_rfbi_slaves, 986 .slaves = omap2420_dss_rfbi_slaves,
976 .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), 987 .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
977 .flags = HWMOD_NO_IDLEST, 988 .flags = HWMOD_NO_IDLEST,
@@ -981,7 +992,7 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
981static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { 992static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
982 .master = &omap2420_l4_core_hwmod, 993 .master = &omap2420_l4_core_hwmod,
983 .slave = &omap2420_dss_venc_hwmod, 994 .slave = &omap2420_dss_venc_hwmod,
984 .clk = "dss_54m_fck", 995 .clk = "dss_ick",
985 .addr = omap2_dss_venc_addrs, 996 .addr = omap2_dss_venc_addrs,
986 .fw = { 997 .fw = {
987 .omap2 = { 998 .omap2 = {
@@ -1001,7 +1012,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1001static struct omap_hwmod omap2420_dss_venc_hwmod = { 1012static struct omap_hwmod omap2420_dss_venc_hwmod = {
1002 .name = "dss_venc", 1013 .name = "dss_venc",
1003 .class = &omap2_venc_hwmod_class, 1014 .class = &omap2_venc_hwmod_class,
1004 .main_clk = "dss1_fck", 1015 .main_clk = "dss_54m_fck",
1005 .prcm = { 1016 .prcm = {
1006 .omap2 = { 1017 .omap2 = {
1007 .prcm_reg_id = 1, 1018 .prcm_reg_id = 1,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index a2580d01c3ff..c4f56cb60d7d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -942,6 +942,10 @@ static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
942}; 942};
943 943
944static struct omap_hwmod_opt_clk dss_opt_clks[] = { 944static struct omap_hwmod_opt_clk dss_opt_clks[] = {
945 /*
946 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
947 * driver does not use these clocks.
948 */
945 { .role = "tv_clk", .clk = "dss_54m_fck" }, 949 { .role = "tv_clk", .clk = "dss_54m_fck" },
946 { .role = "sys_clk", .clk = "dss2_fck" }, 950 { .role = "sys_clk", .clk = "dss2_fck" },
947}; 951};
@@ -966,7 +970,7 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
966 .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), 970 .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
967 .masters = omap2430_dss_masters, 971 .masters = omap2430_dss_masters,
968 .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), 972 .masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
969 .flags = HWMOD_NO_IDLEST, 973 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
970}; 974};
971 975
972/* l4_core -> dss_dispc */ 976/* l4_core -> dss_dispc */
@@ -1000,6 +1004,7 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1000 .slaves = omap2430_dss_dispc_slaves, 1004 .slaves = omap2430_dss_dispc_slaves,
1001 .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), 1005 .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1002 .flags = HWMOD_NO_IDLEST, 1006 .flags = HWMOD_NO_IDLEST,
1007 .dev_attr = &omap2_3_dss_dispc_dev_attr
1003}; 1008};
1004 1009
1005/* l4_core -> dss_rfbi */ 1010/* l4_core -> dss_rfbi */
@@ -1016,6 +1021,10 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1016 &omap2430_l4_core__dss_rfbi, 1021 &omap2430_l4_core__dss_rfbi,
1017}; 1022};
1018 1023
1024static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1025 { .role = "ick", .clk = "dss_ick" },
1026};
1027
1019static struct omap_hwmod omap2430_dss_rfbi_hwmod = { 1028static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1020 .name = "dss_rfbi", 1029 .name = "dss_rfbi",
1021 .class = &omap2_rfbi_hwmod_class, 1030 .class = &omap2_rfbi_hwmod_class,
@@ -1027,6 +1036,8 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1027 .module_offs = CORE_MOD, 1036 .module_offs = CORE_MOD,
1028 }, 1037 },
1029 }, 1038 },
1039 .opt_clks = dss_rfbi_opt_clks,
1040 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1030 .slaves = omap2430_dss_rfbi_slaves, 1041 .slaves = omap2430_dss_rfbi_slaves,
1031 .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), 1042 .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1032 .flags = HWMOD_NO_IDLEST, 1043 .flags = HWMOD_NO_IDLEST,
@@ -1036,7 +1047,7 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1036static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { 1047static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1037 .master = &omap2430_l4_core_hwmod, 1048 .master = &omap2430_l4_core_hwmod,
1038 .slave = &omap2430_dss_venc_hwmod, 1049 .slave = &omap2430_dss_venc_hwmod,
1039 .clk = "dss_54m_fck", 1050 .clk = "dss_ick",
1040 .addr = omap2_dss_venc_addrs, 1051 .addr = omap2_dss_venc_addrs,
1041 .flags = OCPIF_SWSUP_IDLE, 1052 .flags = OCPIF_SWSUP_IDLE,
1042 .user = OCP_USER_MPU | OCP_USER_SDMA, 1053 .user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1050,7 +1061,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1050static struct omap_hwmod omap2430_dss_venc_hwmod = { 1061static struct omap_hwmod omap2430_dss_venc_hwmod = {
1051 .name = "dss_venc", 1062 .name = "dss_venc",
1052 .class = &omap2_venc_hwmod_class, 1063 .class = &omap2_venc_hwmod_class,
1053 .main_clk = "dss1_fck", 1064 .main_clk = "dss_54m_fck",
1054 .prcm = { 1065 .prcm = {
1055 .omap2 = { 1066 .omap2 = {
1056 .prcm_reg_id = 1, 1067 .prcm_reg_id = 1,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index c451729d289a..c11273da5dcc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -11,6 +11,7 @@
11#include <plat/omap_hwmod.h> 11#include <plat/omap_hwmod.h>
12#include <plat/serial.h> 12#include <plat/serial.h>
13#include <plat/dma.h> 13#include <plat/dma.h>
14#include <plat/common.h>
14 15
15#include <mach/irqs.h> 16#include <mach/irqs.h>
16 17
@@ -43,13 +44,15 @@ static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
43 .rev_offs = 0x0000, 44 .rev_offs = 0x0000,
44 .sysc_offs = 0x0010, 45 .sysc_offs = 0x0010,
45 .syss_offs = 0x0014, 46 .syss_offs = 0x0014,
46 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 47 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
48 SYSS_HAS_RESET_STATUS),
47 .sysc_fields = &omap_hwmod_sysc_type1, 49 .sysc_fields = &omap_hwmod_sysc_type1,
48}; 50};
49 51
50struct omap_hwmod_class omap2_dss_hwmod_class = { 52struct omap_hwmod_class omap2_dss_hwmod_class = {
51 .name = "dss", 53 .name = "dss",
52 .sysc = &omap2_dss_sysc, 54 .sysc = &omap2_dss_sysc,
55 .reset = omap_dss_reset,
53}; 56};
54 57
55/* 58/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index bc9035ec87fc..7f8915ad5099 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1369,9 +1369,14 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1369}; 1369};
1370 1370
1371static struct omap_hwmod_opt_clk dss_opt_clks[] = { 1371static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1372 { .role = "tv_clk", .clk = "dss_tv_fck" }, 1372 /*
1373 { .role = "video_clk", .clk = "dss_96m_fck" }, 1373 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1374 * driver does not use these clocks.
1375 */
1374 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 1376 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1377 { .role = "tv_clk", .clk = "dss_tv_fck" },
1378 /* required only on OMAP3430 */
1379 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1375}; 1380};
1376 1381
1377static struct omap_hwmod omap3430es1_dss_core_hwmod = { 1382static struct omap_hwmod omap3430es1_dss_core_hwmod = {
@@ -1394,11 +1399,12 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1394 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), 1399 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1395 .masters = omap3xxx_dss_masters, 1400 .masters = omap3xxx_dss_masters,
1396 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), 1401 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1397 .flags = HWMOD_NO_IDLEST, 1402 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1398}; 1403};
1399 1404
1400static struct omap_hwmod omap3xxx_dss_core_hwmod = { 1405static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1401 .name = "dss_core", 1406 .name = "dss_core",
1407 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1402 .class = &omap2_dss_hwmod_class, 1408 .class = &omap2_dss_hwmod_class,
1403 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 1409 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1404 .sdma_reqs = omap3xxx_dss_sdma_chs, 1410 .sdma_reqs = omap3xxx_dss_sdma_chs,
@@ -1456,6 +1462,7 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1456 .slaves = omap3xxx_dss_dispc_slaves, 1462 .slaves = omap3xxx_dss_dispc_slaves,
1457 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), 1463 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1458 .flags = HWMOD_NO_IDLEST, 1464 .flags = HWMOD_NO_IDLEST,
1465 .dev_attr = &omap2_3_dss_dispc_dev_attr
1459}; 1466};
1460 1467
1461/* 1468/*
@@ -1486,6 +1493,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1486static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { 1493static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1487 .master = &omap3xxx_l4_core_hwmod, 1494 .master = &omap3xxx_l4_core_hwmod,
1488 .slave = &omap3xxx_dss_dsi1_hwmod, 1495 .slave = &omap3xxx_dss_dsi1_hwmod,
1496 .clk = "dss_ick",
1489 .addr = omap3xxx_dss_dsi1_addrs, 1497 .addr = omap3xxx_dss_dsi1_addrs,
1490 .fw = { 1498 .fw = {
1491 .omap2 = { 1499 .omap2 = {
@@ -1502,6 +1510,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1502 &omap3xxx_l4_core__dss_dsi1, 1510 &omap3xxx_l4_core__dss_dsi1,
1503}; 1511};
1504 1512
1513static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1514 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1515};
1516
1505static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { 1517static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1506 .name = "dss_dsi1", 1518 .name = "dss_dsi1",
1507 .class = &omap3xxx_dsi_hwmod_class, 1519 .class = &omap3xxx_dsi_hwmod_class,
@@ -1514,6 +1526,8 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1514 .module_offs = OMAP3430_DSS_MOD, 1526 .module_offs = OMAP3430_DSS_MOD,
1515 }, 1527 },
1516 }, 1528 },
1529 .opt_clks = dss_dsi1_opt_clks,
1530 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1517 .slaves = omap3xxx_dss_dsi1_slaves, 1531 .slaves = omap3xxx_dss_dsi1_slaves,
1518 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), 1532 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1519 .flags = HWMOD_NO_IDLEST, 1533 .flags = HWMOD_NO_IDLEST,
@@ -1540,6 +1554,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1540 &omap3xxx_l4_core__dss_rfbi, 1554 &omap3xxx_l4_core__dss_rfbi,
1541}; 1555};
1542 1556
1557static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1558 { .role = "ick", .clk = "dss_ick" },
1559};
1560
1543static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { 1561static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1544 .name = "dss_rfbi", 1562 .name = "dss_rfbi",
1545 .class = &omap2_rfbi_hwmod_class, 1563 .class = &omap2_rfbi_hwmod_class,
@@ -1551,6 +1569,8 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1551 .module_offs = OMAP3430_DSS_MOD, 1569 .module_offs = OMAP3430_DSS_MOD,
1552 }, 1570 },
1553 }, 1571 },
1572 .opt_clks = dss_rfbi_opt_clks,
1573 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1554 .slaves = omap3xxx_dss_rfbi_slaves, 1574 .slaves = omap3xxx_dss_rfbi_slaves,
1555 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), 1575 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1556 .flags = HWMOD_NO_IDLEST, 1576 .flags = HWMOD_NO_IDLEST,
@@ -1560,7 +1580,7 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1560static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { 1580static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1561 .master = &omap3xxx_l4_core_hwmod, 1581 .master = &omap3xxx_l4_core_hwmod,
1562 .slave = &omap3xxx_dss_venc_hwmod, 1582 .slave = &omap3xxx_dss_venc_hwmod,
1563 .clk = "dss_tv_fck", 1583 .clk = "dss_ick",
1564 .addr = omap2_dss_venc_addrs, 1584 .addr = omap2_dss_venc_addrs,
1565 .fw = { 1585 .fw = {
1566 .omap2 = { 1586 .omap2 = {
@@ -1578,10 +1598,15 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1578 &omap3xxx_l4_core__dss_venc, 1598 &omap3xxx_l4_core__dss_venc,
1579}; 1599};
1580 1600
1601static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1602 /* required only on OMAP3430 */
1603 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1604};
1605
1581static struct omap_hwmod omap3xxx_dss_venc_hwmod = { 1606static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1582 .name = "dss_venc", 1607 .name = "dss_venc",
1583 .class = &omap2_venc_hwmod_class, 1608 .class = &omap2_venc_hwmod_class,
1584 .main_clk = "dss1_alwon_fck", 1609 .main_clk = "dss_tv_fck",
1585 .prcm = { 1610 .prcm = {
1586 .omap2 = { 1611 .omap2 = {
1587 .prcm_reg_id = 1, 1612 .prcm_reg_id = 1,
@@ -1589,6 +1614,8 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1589 .module_offs = OMAP3430_DSS_MOD, 1614 .module_offs = OMAP3430_DSS_MOD,
1590 }, 1615 },
1591 }, 1616 },
1617 .opt_clks = dss_venc_opt_clks,
1618 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
1592 .slaves = omap3xxx_dss_venc_slaves, 1619 .slaves = omap3xxx_dss_venc_slaves,
1593 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), 1620 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1594 .flags = HWMOD_NO_IDLEST, 1621 .flags = HWMOD_NO_IDLEST,
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7695e5d43316..daaf165af696 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -30,6 +30,7 @@
30#include <plat/mmc.h> 30#include <plat/mmc.h>
31#include <plat/i2c.h> 31#include <plat/i2c.h>
32#include <plat/dmtimer.h> 32#include <plat/dmtimer.h>
33#include <plat/common.h>
33 34
34#include "omap_hwmod_common_data.h" 35#include "omap_hwmod_common_data.h"
35 36
@@ -1187,6 +1188,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1187static struct omap_hwmod_class omap44xx_dss_hwmod_class = { 1188static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1188 .name = "dss", 1189 .name = "dss",
1189 .sysc = &omap44xx_dss_sysc, 1190 .sysc = &omap44xx_dss_sysc,
1191 .reset = omap_dss_reset,
1190}; 1192};
1191 1193
1192/* dss */ 1194/* dss */
@@ -1240,12 +1242,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1240static struct omap_hwmod_opt_clk dss_opt_clks[] = { 1242static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1241 { .role = "sys_clk", .clk = "dss_sys_clk" }, 1243 { .role = "sys_clk", .clk = "dss_sys_clk" },
1242 { .role = "tv_clk", .clk = "dss_tv_clk" }, 1244 { .role = "tv_clk", .clk = "dss_tv_clk" },
1243 { .role = "dss_clk", .clk = "dss_dss_clk" }, 1245 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1244 { .role = "video_clk", .clk = "dss_48mhz_clk" },
1245}; 1246};
1246 1247
1247static struct omap_hwmod omap44xx_dss_hwmod = { 1248static struct omap_hwmod omap44xx_dss_hwmod = {
1248 .name = "dss_core", 1249 .name = "dss_core",
1250 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1249 .class = &omap44xx_dss_hwmod_class, 1251 .class = &omap44xx_dss_hwmod_class,
1250 .clkdm_name = "l3_dss_clkdm", 1252 .clkdm_name = "l3_dss_clkdm",
1251 .main_clk = "dss_dss_clk", 1253 .main_clk = "dss_dss_clk",
@@ -1325,6 +1327,11 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1325 { } 1327 { }
1326}; 1328};
1327 1329
1330static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1331 .manager_count = 3,
1332 .has_framedonetv_irq = 1
1333};
1334
1328/* l4_per -> dss_dispc */ 1335/* l4_per -> dss_dispc */
1329static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { 1336static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1330 .master = &omap44xx_l4_per_hwmod, 1337 .master = &omap44xx_l4_per_hwmod,
@@ -1340,12 +1347,6 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1340 &omap44xx_l4_per__dss_dispc, 1347 &omap44xx_l4_per__dss_dispc,
1341}; 1348};
1342 1349
1343static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1344 { .role = "sys_clk", .clk = "dss_sys_clk" },
1345 { .role = "tv_clk", .clk = "dss_tv_clk" },
1346 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1347};
1348
1349static struct omap_hwmod omap44xx_dss_dispc_hwmod = { 1350static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1350 .name = "dss_dispc", 1351 .name = "dss_dispc",
1351 .class = &omap44xx_dispc_hwmod_class, 1352 .class = &omap44xx_dispc_hwmod_class,
@@ -1359,10 +1360,9 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1359 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1360 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1360 }, 1361 },
1361 }, 1362 },
1362 .opt_clks = dss_dispc_opt_clks,
1363 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
1364 .slaves = omap44xx_dss_dispc_slaves, 1363 .slaves = omap44xx_dss_dispc_slaves,
1365 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), 1364 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1365 .dev_attr = &omap44xx_dss_dispc_dev_attr
1366}; 1366};
1367 1367
1368/* 1368/*
@@ -1624,7 +1624,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1624 .clkdm_name = "l3_dss_clkdm", 1624 .clkdm_name = "l3_dss_clkdm",
1625 .mpu_irqs = omap44xx_dss_hdmi_irqs, 1625 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1626 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, 1626 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1627 .main_clk = "dss_dss_clk", 1627 .main_clk = "dss_48mhz_clk",
1628 .prcm = { 1628 .prcm = {
1629 .omap4 = { 1629 .omap4 = {
1630 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1630 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -1785,7 +1785,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1785 .name = "dss_venc", 1785 .name = "dss_venc",
1786 .class = &omap44xx_venc_hwmod_class, 1786 .class = &omap44xx_venc_hwmod_class,
1787 .clkdm_name = "l3_dss_clkdm", 1787 .clkdm_name = "l3_dss_clkdm",
1788 .main_clk = "dss_dss_clk", 1788 .main_clk = "dss_tv_clk",
1789 .prcm = { 1789 .prcm = {
1790 .omap4 = { 1790 .omap4 = {
1791 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1791 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
index de832ebc93a9..51e5418899fb 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -49,3 +49,7 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
49 .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT, 49 .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
50}; 50};
51 51
52struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
53 .manager_count = 2,
54 .has_framedonetv_irq = 0
55};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 39a7c37f4587..ad5d8f04c0b8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -16,6 +16,8 @@
16 16
17#include <plat/omap_hwmod.h> 17#include <plat/omap_hwmod.h>
18 18
19#include "display.h"
20
19/* Common address space across OMAP2xxx */ 21/* Common address space across OMAP2xxx */
20extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[]; 22extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
21extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[]; 23extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
@@ -111,4 +113,6 @@ extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
111extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class; 113extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
112extern struct omap_hwmod_class omap2xxx_mcspi_class; 114extern struct omap_hwmod_class omap2xxx_mcspi_class;
113 115
116extern struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr;
117
114#endif 118#endif
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index c50df4814f6f..3ff3e36580f2 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -30,6 +30,7 @@
30#include <linux/delay.h> 30#include <linux/delay.h>
31 31
32#include <plat/i2c.h> 32#include <plat/i2c.h>
33#include <plat/omap_hwmod.h>
33 34
34struct sys_timer; 35struct sys_timer;
35 36
@@ -55,6 +56,8 @@ void am35xx_init_early(void);
55void ti816x_init_early(void); 56void ti816x_init_early(void);
56void omap4430_init_early(void); 57void omap4430_init_early(void);
57 58
59extern int omap_dss_reset(struct omap_hwmod *);
60
58void omap_sram_init(void); 61void omap_sram_init(void);
59 62
60/* 63/*