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authorDmitriy Taychenachev <dimichxp@gmail.com>2009-07-31 07:29:23 -0400
committerSascha Hauer <s.hauer@pengutronix.de>2009-08-14 06:40:47 -0400
commit94da274b4982f5b36b55bde0c76d3ef8233bceda (patch)
treec1684cf7f755642517c2ec4fb52ce958a7e454d6 /arch/arm
parentfd6ac7bb9d671d36fd7536c68fde977d197756ab (diff)
MXC: add iomux pins configuration support for MXC91231
Signed-off-by: Dmitriy Taychenachev <dimichxp@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-mxc91231/Makefile2
-rw-r--r--arch/arm/mach-mxc91231/iomux.c177
-rw-r--r--arch/arm/mach-mxc91231/magx-zn5.c4
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mxc91231.h287
4 files changed, 469 insertions, 1 deletions
diff --git a/arch/arm/mach-mxc91231/Makefile b/arch/arm/mach-mxc91231/Makefile
index eb70b669c556..011d5e197125 100644
--- a/arch/arm/mach-mxc91231/Makefile
+++ b/arch/arm/mach-mxc91231/Makefile
@@ -1,2 +1,2 @@
1obj-y := mm.o clock.o devices.o system.o 1obj-y := mm.o clock.o devices.o system.o iomux.o
2obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o 2obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o
diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c
new file mode 100644
index 000000000000..405d9b19d891
--- /dev/null
+++ b/arch/arm/mach-mxc91231/iomux.c
@@ -0,0 +1,177 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <linux/module.h>
22#include <linux/spinlock.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <mach/hardware.h>
26#include <mach/gpio.h>
27#include <mach/iomux-mxc91231.h>
28
29/*
30 * IOMUX register (base) addresses
31 */
32#define IOMUX_AP_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_AP_BASE_ADDR)
33#define IOMUX_COM_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_COM_BASE_ADDR)
34#define IOMUXSW_AP_MUX_CTL (IOMUX_AP_BASE + 0x000)
35#define IOMUXSW_SP_MUX_CTL (IOMUX_COM_BASE + 0x000)
36#define IOMUXSW_PAD_CTL (IOMUX_COM_BASE + 0x200)
37
38#define IOMUXINT_OBS1 (IOMUX_AP_BASE + 0x600)
39#define IOMUXINT_OBS2 (IOMUX_AP_BASE + 0x004)
40
41static DEFINE_SPINLOCK(gpio_mux_lock);
42
43#define NB_PORTS ((PIN_MAX + 32) / 32)
44#define PIN_GLOBAL_NUM(pin) \
45 (((pin & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT)*PIN_AP_MAX + \
46 ((pin & MUX_REG_MASK) >> MUX_REG_SHIFT)*4 + \
47 ((pin & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT))
48
49unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
50/*
51 * set the mode for a IOMUX pin.
52 */
53int mxc_iomux_mode(const unsigned int pin_mode)
54{
55 u32 side, field, l, mode, ret = 0;
56 void __iomem *reg;
57
58 side = (pin_mode & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT;
59 switch (side) {
60 case MUX_SIDE_AP:
61 reg = IOMUXSW_AP_MUX_CTL;
62 break;
63 case MUX_SIDE_SP:
64 reg = IOMUXSW_SP_MUX_CTL;
65 break;
66 default:
67 return -EINVAL;
68 }
69 reg += ((pin_mode & MUX_REG_MASK) >> MUX_REG_SHIFT) * 4;
70 field = (pin_mode & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT;
71 mode = (pin_mode & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
72
73 spin_lock(&gpio_mux_lock);
74
75 l = __raw_readl(reg);
76 l &= ~(0xff << (field * 8));
77 l |= mode << (field * 8);
78 __raw_writel(l, reg);
79
80 spin_unlock(&gpio_mux_lock);
81
82 return ret;
83}
84EXPORT_SYMBOL(mxc_iomux_mode);
85
86/*
87 * This function configures the pad value for a IOMUX pin.
88 */
89void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
90{
91 u32 padgrp, field, l;
92 void __iomem *reg;
93
94 padgrp = (pin & MUX_PADGRP_MASK) >> MUX_PADGRP_SHIFT;
95 reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
96 field = (pin + 2) % 3;
97
98 pr_debug("%s: reg offset = 0x%x, field = %d\n",
99 __func__, (pin + 2) / 3, field);
100
101 spin_lock(&gpio_mux_lock);
102
103 l = __raw_readl(reg);
104 l &= ~(0x1ff << (field * 10));
105 l |= config << (field * 10);
106 __raw_writel(l, reg);
107
108 spin_unlock(&gpio_mux_lock);
109}
110EXPORT_SYMBOL(mxc_iomux_set_pad);
111
112/*
113 * allocs a single pin:
114 * - reserves the pin so that it is not claimed by another driver
115 * - setups the iomux according to the configuration
116 */
117int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label)
118{
119 unsigned pad = PIN_GLOBAL_NUM(pin_mode);
120 if (pad >= (PIN_MAX + 1)) {
121 printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
122 pad, label ? label : "?");
123 return -EINVAL;
124 }
125
126 if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
127 printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
128 pad, label ? label : "?");
129 return -EBUSY;
130 }
131 mxc_iomux_mode(pin_mode);
132
133 return 0;
134}
135EXPORT_SYMBOL(mxc_iomux_alloc_pin);
136
137int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
138 const char *label)
139{
140 unsigned int *p = pin_list;
141 int i;
142 int ret = -EINVAL;
143
144 for (i = 0; i < count; i++) {
145 ret = mxc_iomux_alloc_pin(*p, label);
146 if (ret)
147 goto setup_error;
148 p++;
149 }
150 return 0;
151
152setup_error:
153 mxc_iomux_release_multiple_pins(pin_list, i);
154 return ret;
155}
156EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
157
158void mxc_iomux_release_pin(const unsigned int pin_mode)
159{
160 unsigned pad = PIN_GLOBAL_NUM(pin_mode);
161
162 if (pad < (PIN_MAX + 1))
163 clear_bit(pad, mxc_pin_alloc_map);
164}
165EXPORT_SYMBOL(mxc_iomux_release_pin);
166
167void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
168{
169 unsigned int *p = pin_list;
170 int i;
171
172 for (i = 0; i < count; i++) {
173 mxc_iomux_release_pin(*p);
174 p++;
175 }
176}
177EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
index 8757573b0a8a..7dbe4ca12efd 100644
--- a/arch/arm/mach-mxc91231/magx-zn5.c
+++ b/arch/arm/mach-mxc91231/magx-zn5.c
@@ -14,6 +14,7 @@
14 14
15#include <mach/common.h> 15#include <mach/common.h>
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17#include <mach/iomux-mxc91231.h>
17#include <mach/mmc.h> 18#include <mach/mmc.h>
18#include <mach/imx-uart.h> 19#include <mach/imx-uart.h>
19 20
@@ -29,6 +30,9 @@ static void __init zn5_init(void)
29{ 30{
30 pm_power_off = mxc91231_power_off; 31 pm_power_off = mxc91231_power_off;
31 32
33 mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_DAT_VP__RXD2, "uart2-rx");
34 mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_SE0_VM__TXD2, "uart2-tx");
35
32 mxc_register_device(&mxc_uart_device1, &uart_pdata); 36 mxc_register_device(&mxc_uart_device1, &uart_pdata);
33 mxc_register_device(&mxc_uart_device0, &uart_pdata); 37 mxc_register_device(&mxc_uart_device0, &uart_pdata);
34 38
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
new file mode 100644
index 000000000000..9f13061192c8
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -0,0 +1,287 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Dmitriy Taychenachev <dimichxp@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __MACH_IOMUX_MXC91231_H__
22#define __MACH_IOMUX_MXC91231_H__
23
24/*
25 * various IOMUX output functions
26 */
27
28#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */
29#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */
30#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */
31#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */
32#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */
33#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
34#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
35#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
36#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
37#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
38#define IOMUX_ICONFIG_FUNC 2 /* used as function */
39#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
40#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */
41
42#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
43#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
44#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
45#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
46
47/*
48 * setups a single pin:
49 * - reserves the pin so that it is not claimed by another driver
50 * - setups the iomux according to the configuration
51 * - if the pin is configured as a GPIO, we claim it throug kernel gpiolib
52 */
53int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label);
54/*
55 * setups mutliple pins
56 * convenient way to call the above function with tables
57 */
58int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
59 const char *label);
60
61/*
62 * releases a single pin:
63 * - make it available for a future use by another driver
64 * - frees the GPIO if the pin was configured as GPIO
65 * - DOES NOT reconfigure the IOMUX in its reset state
66 */
67void mxc_iomux_release_pin(const unsigned int pin_mode);
68/*
69 * releases multiple pins
70 * convenvient way to call the above function with tables
71 */
72void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count);
73
74#define MUX_SIDE_AP (0)
75#define MUX_SIDE_SP (1)
76
77#define MUX_SIDE_SHIFT (26)
78#define MUX_SIDE_MASK (0x1 << MUX_SIDE_SHIFT)
79
80#define MUX_GPIO_PORT_SHIFT (23)
81#define MUX_GPIO_PORT_MASK (0x7 << MUX_GPIO_PORT_SHIFT)
82
83#define MUX_GPIO_PIN_SHIFT (20)
84#define MUX_GPIO_PIN_MASK (0x1f << MUX_GPIO_PIN_SHIFT)
85
86#define MUX_REG_SHIFT (15)
87#define MUX_REG_MASK (0x1f << MUX_REG_SHIFT)
88
89#define MUX_FIELD_SHIFT (13)
90#define MUX_FIELD_MASK (0x3 << MUX_FIELD_SHIFT)
91
92#define MUX_PADGRP_SHIFT (8)
93#define MUX_PADGRP_MASK (0x1f << MUX_PADGRP_SHIFT)
94
95#define MUX_PIN_MASK (0xffffff << 8)
96
97#define GPIO_PORT_MAX (3)
98
99#define IOMUX_PIN(side, gport, gpin, ctlreg, ctlfield, padgrp) \
100 (((side) << MUX_SIDE_SHIFT) | \
101 (gport << MUX_GPIO_PORT_SHIFT) | \
102 ((gpin) << MUX_GPIO_PIN_SHIFT) | \
103 ((ctlreg) << MUX_REG_SHIFT) | \
104 ((ctlfield) << MUX_FIELD_SHIFT) | \
105 ((padgrp) << MUX_PADGRP_SHIFT))
106
107#define MUX_MODE_OUT_SHIFT (4)
108#define MUX_MODE_IN_SHIFT (0)
109#define MUX_MODE_SHIFT (0)
110#define MUX_MODE_MASK (0xff << MUX_MODE_SHIFT)
111
112#define IOMUX_MODE(pin, mode) \
113 (pin | (mode << MUX_MODE_SHIFT))
114
115enum iomux_pins {
116 /* AP Side pins */
117 MXC91231_PIN_AP_CLE = IOMUX_PIN(0, 0, 0, 0, 0, 24),
118 MXC91231_PIN_AP_ALE = IOMUX_PIN(0, 0, 1, 0, 1, 24),
119 MXC91231_PIN_AP_CE_B = IOMUX_PIN(0, 0, 2, 0, 2, 24),
120 MXC91231_PIN_AP_RE_B = IOMUX_PIN(0, 0, 3, 0, 3, 24),
121 MXC91231_PIN_AP_WE_B = IOMUX_PIN(0, 0, 4, 1, 0, 24),
122 MXC91231_PIN_AP_WP_B = IOMUX_PIN(0, 0, 5, 1, 1, 24),
123 MXC91231_PIN_AP_BSY_B = IOMUX_PIN(0, 0, 6, 1, 2, 24),
124 MXC91231_PIN_AP_U1_TXD = IOMUX_PIN(0, 0, 7, 1, 3, 28),
125 MXC91231_PIN_AP_U1_RXD = IOMUX_PIN(0, 0, 8, 2, 0, 28),
126 MXC91231_PIN_AP_U1_RTS_B = IOMUX_PIN(0, 0, 9, 2, 1, 28),
127 MXC91231_PIN_AP_U1_CTS_B = IOMUX_PIN(0, 0, 10, 2, 2, 28),
128 MXC91231_PIN_AP_AD1_TXD = IOMUX_PIN(0, 0, 11, 2, 3, 9),
129 MXC91231_PIN_AP_AD1_RXD = IOMUX_PIN(0, 0, 12, 3, 0, 9),
130 MXC91231_PIN_AP_AD1_TXC = IOMUX_PIN(0, 0, 13, 3, 1, 9),
131 MXC91231_PIN_AP_AD1_TXFS = IOMUX_PIN(0, 0, 14, 3, 2, 9),
132 MXC91231_PIN_AP_AD2_TXD = IOMUX_PIN(0, 0, 15, 3, 3, 9),
133 MXC91231_PIN_AP_AD2_RXD = IOMUX_PIN(0, 0, 16, 4, 0, 9),
134 MXC91231_PIN_AP_AD2_TXC = IOMUX_PIN(0, 0, 17, 4, 1, 9),
135 MXC91231_PIN_AP_AD2_TXFS = IOMUX_PIN(0, 0, 18, 4, 2, 9),
136 MXC91231_PIN_AP_OWDAT = IOMUX_PIN(0, 0, 19, 4, 3, 28),
137 MXC91231_PIN_AP_IPU_LD17 = IOMUX_PIN(0, 0, 20, 5, 0, 28),
138 MXC91231_PIN_AP_IPU_D3_VSYNC = IOMUX_PIN(0, 0, 21, 5, 1, 28),
139 MXC91231_PIN_AP_IPU_D3_HSYNC = IOMUX_PIN(0, 0, 22, 5, 2, 28),
140 MXC91231_PIN_AP_IPU_D3_CLK = IOMUX_PIN(0, 0, 23, 5, 3, 28),
141 MXC91231_PIN_AP_IPU_D3_DRDY = IOMUX_PIN(0, 0, 24, 6, 0, 28),
142 MXC91231_PIN_AP_IPU_D3_CONTR = IOMUX_PIN(0, 0, 25, 6, 1, 28),
143 MXC91231_PIN_AP_IPU_D0_CS = IOMUX_PIN(0, 0, 26, 6, 2, 28),
144 MXC91231_PIN_AP_IPU_LD16 = IOMUX_PIN(0, 0, 27, 6, 3, 28),
145 MXC91231_PIN_AP_IPU_D2_CS = IOMUX_PIN(0, 0, 28, 7, 0, 28),
146 MXC91231_PIN_AP_IPU_PAR_RS = IOMUX_PIN(0, 0, 29, 7, 1, 28),
147 MXC91231_PIN_AP_IPU_D3_PS = IOMUX_PIN(0, 0, 30, 7, 2, 28),
148 MXC91231_PIN_AP_IPU_D3_CLS = IOMUX_PIN(0, 0, 31, 7, 3, 28),
149 MXC91231_PIN_AP_IPU_RD = IOMUX_PIN(0, 1, 0, 8, 0, 28),
150 MXC91231_PIN_AP_IPU_WR = IOMUX_PIN(0, 1, 1, 8, 1, 28),
151 MXC91231_PIN_AP_IPU_LD0 = IOMUX_PIN(0, 7, 0, 8, 2, 28),
152 MXC91231_PIN_AP_IPU_LD1 = IOMUX_PIN(0, 7, 0, 8, 3, 28),
153 MXC91231_PIN_AP_IPU_LD2 = IOMUX_PIN(0, 7, 0, 9, 0, 28),
154 MXC91231_PIN_AP_IPU_LD3 = IOMUX_PIN(0, 1, 2, 9, 1, 28),
155 MXC91231_PIN_AP_IPU_LD4 = IOMUX_PIN(0, 1, 3, 9, 2, 28),
156 MXC91231_PIN_AP_IPU_LD5 = IOMUX_PIN(0, 1, 4, 9, 3, 28),
157 MXC91231_PIN_AP_IPU_LD6 = IOMUX_PIN(0, 1, 5, 10, 0, 28),
158 MXC91231_PIN_AP_IPU_LD7 = IOMUX_PIN(0, 1, 6, 10, 1, 28),
159 MXC91231_PIN_AP_IPU_LD8 = IOMUX_PIN(0, 1, 7, 10, 2, 28),
160 MXC91231_PIN_AP_IPU_LD9 = IOMUX_PIN(0, 1, 8, 10, 3, 28),
161 MXC91231_PIN_AP_IPU_LD10 = IOMUX_PIN(0, 1, 9, 11, 0, 28),
162 MXC91231_PIN_AP_IPU_LD11 = IOMUX_PIN(0, 1, 10, 11, 1, 28),
163 MXC91231_PIN_AP_IPU_LD12 = IOMUX_PIN(0, 1, 11, 11, 2, 28),
164 MXC91231_PIN_AP_IPU_LD13 = IOMUX_PIN(0, 1, 12, 11, 3, 28),
165 MXC91231_PIN_AP_IPU_LD14 = IOMUX_PIN(0, 1, 13, 12, 0, 28),
166 MXC91231_PIN_AP_IPU_LD15 = IOMUX_PIN(0, 1, 14, 12, 1, 28),
167 MXC91231_PIN_AP_KPROW4 = IOMUX_PIN(0, 7, 0, 12, 2, 10),
168 MXC91231_PIN_AP_KPROW5 = IOMUX_PIN(0, 1, 16, 12, 3, 10),
169 MXC91231_PIN_AP_GPIO_AP_B17 = IOMUX_PIN(0, 1, 17, 13, 0, 10),
170 MXC91231_PIN_AP_GPIO_AP_B18 = IOMUX_PIN(0, 1, 18, 13, 1, 10),
171 MXC91231_PIN_AP_KPCOL3 = IOMUX_PIN(0, 1, 19, 13, 2, 11),
172 MXC91231_PIN_AP_KPCOL4 = IOMUX_PIN(0, 1, 20, 13, 3, 11),
173 MXC91231_PIN_AP_KPCOL5 = IOMUX_PIN(0, 1, 21, 14, 0, 11),
174 MXC91231_PIN_AP_GPIO_AP_B22 = IOMUX_PIN(0, 1, 22, 14, 1, 11),
175 MXC91231_PIN_AP_GPIO_AP_B23 = IOMUX_PIN(0, 1, 23, 14, 2, 11),
176 MXC91231_PIN_AP_CSI_D0 = IOMUX_PIN(0, 1, 24, 14, 3, 21),
177 MXC91231_PIN_AP_CSI_D1 = IOMUX_PIN(0, 1, 25, 15, 0, 21),
178 MXC91231_PIN_AP_CSI_D2 = IOMUX_PIN(0, 1, 26, 15, 1, 21),
179 MXC91231_PIN_AP_CSI_D3 = IOMUX_PIN(0, 1, 27, 15, 2, 21),
180 MXC91231_PIN_AP_CSI_D4 = IOMUX_PIN(0, 1, 28, 15, 3, 21),
181 MXC91231_PIN_AP_CSI_D5 = IOMUX_PIN(0, 1, 29, 16, 0, 21),
182 MXC91231_PIN_AP_CSI_D6 = IOMUX_PIN(0, 1, 30, 16, 1, 21),
183 MXC91231_PIN_AP_CSI_D7 = IOMUX_PIN(0, 1, 31, 16, 2, 21),
184 MXC91231_PIN_AP_CSI_D8 = IOMUX_PIN(0, 2, 0, 16, 3, 21),
185 MXC91231_PIN_AP_CSI_D9 = IOMUX_PIN(0, 2, 1, 17, 0, 21),
186 MXC91231_PIN_AP_CSI_MCLK = IOMUX_PIN(0, 2, 2, 17, 1, 21),
187 MXC91231_PIN_AP_CSI_VSYNC = IOMUX_PIN(0, 2, 3, 17, 2, 21),
188 MXC91231_PIN_AP_CSI_HSYNC = IOMUX_PIN(0, 2, 4, 17, 3, 21),
189 MXC91231_PIN_AP_CSI_PIXCLK = IOMUX_PIN(0, 2, 5, 18, 0, 21),
190 MXC91231_PIN_AP_I2CLK = IOMUX_PIN(0, 2, 6, 18, 1, 12),
191 MXC91231_PIN_AP_I2DAT = IOMUX_PIN(0, 2, 7, 18, 2, 12),
192 MXC91231_PIN_AP_GPIO_AP_C8 = IOMUX_PIN(0, 2, 8, 18, 3, 9),
193 MXC91231_PIN_AP_GPIO_AP_C9 = IOMUX_PIN(0, 2, 9, 19, 0, 9),
194 MXC91231_PIN_AP_GPIO_AP_C10 = IOMUX_PIN(0, 2, 10, 19, 1, 9),
195 MXC91231_PIN_AP_GPIO_AP_C11 = IOMUX_PIN(0, 2, 11, 19, 2, 9),
196 MXC91231_PIN_AP_GPIO_AP_C12 = IOMUX_PIN(0, 2, 12, 19, 3, 9),
197 MXC91231_PIN_AP_GPIO_AP_C13 = IOMUX_PIN(0, 2, 13, 20, 0, 28),
198 MXC91231_PIN_AP_GPIO_AP_C14 = IOMUX_PIN(0, 2, 14, 20, 1, 28),
199 MXC91231_PIN_AP_GPIO_AP_C15 = IOMUX_PIN(0, 2, 15, 20, 2, 9),
200 MXC91231_PIN_AP_GPIO_AP_C16 = IOMUX_PIN(0, 2, 16, 20, 3, 9),
201 MXC91231_PIN_AP_GPIO_AP_C17 = IOMUX_PIN(0, 2, 17, 21, 0, 9),
202 MXC91231_PIN_AP_ED_INT0 = IOMUX_PIN(0, 2, 18, 21, 1, 22),
203 MXC91231_PIN_AP_ED_INT1 = IOMUX_PIN(0, 2, 19, 21, 2, 22),
204 MXC91231_PIN_AP_ED_INT2 = IOMUX_PIN(0, 2, 20, 21, 3, 22),
205 MXC91231_PIN_AP_ED_INT3 = IOMUX_PIN(0, 2, 21, 22, 0, 22),
206 MXC91231_PIN_AP_ED_INT4 = IOMUX_PIN(0, 2, 22, 22, 1, 23),
207 MXC91231_PIN_AP_ED_INT5 = IOMUX_PIN(0, 2, 23, 22, 2, 23),
208 MXC91231_PIN_AP_ED_INT6 = IOMUX_PIN(0, 2, 24, 22, 3, 23),
209 MXC91231_PIN_AP_ED_INT7 = IOMUX_PIN(0, 2, 25, 23, 0, 23),
210 MXC91231_PIN_AP_U2_DSR_B = IOMUX_PIN(0, 2, 26, 23, 1, 28),
211 MXC91231_PIN_AP_U2_RI_B = IOMUX_PIN(0, 2, 27, 23, 2, 28),
212 MXC91231_PIN_AP_U2_CTS_B = IOMUX_PIN(0, 2, 28, 23, 3, 28),
213 MXC91231_PIN_AP_U2_DTR_B = IOMUX_PIN(0, 2, 29, 24, 0, 28),
214 MXC91231_PIN_AP_KPROW0 = IOMUX_PIN(0, 7, 0, 24, 1, 10),
215 MXC91231_PIN_AP_KPROW1 = IOMUX_PIN(0, 1, 15, 24, 2, 10),
216 MXC91231_PIN_AP_KPROW2 = IOMUX_PIN(0, 7, 0, 24, 3, 10),
217 MXC91231_PIN_AP_KPROW3 = IOMUX_PIN(0, 7, 0, 25, 0, 10),
218 MXC91231_PIN_AP_KPCOL0 = IOMUX_PIN(0, 7, 0, 25, 1, 11),
219 MXC91231_PIN_AP_KPCOL1 = IOMUX_PIN(0, 7, 0, 25, 2, 11),
220 MXC91231_PIN_AP_KPCOL2 = IOMUX_PIN(0, 7, 0, 25, 3, 11),
221
222 /* Shared pins */
223 MXC91231_PIN_SP_U3_TXD = IOMUX_PIN(1, 3, 0, 0, 0, 28),
224 MXC91231_PIN_SP_U3_RXD = IOMUX_PIN(1, 3, 1, 0, 1, 28),
225 MXC91231_PIN_SP_U3_RTS_B = IOMUX_PIN(1, 3, 2, 0, 2, 28),
226 MXC91231_PIN_SP_U3_CTS_B = IOMUX_PIN(1, 3, 3, 0, 3, 28),
227 MXC91231_PIN_SP_USB_TXOE_B = IOMUX_PIN(1, 3, 4, 1, 0, 28),
228 MXC91231_PIN_SP_USB_DAT_VP = IOMUX_PIN(1, 3, 5, 1, 1, 28),
229 MXC91231_PIN_SP_USB_SE0_VM = IOMUX_PIN(1, 3, 6, 1, 2, 28),
230 MXC91231_PIN_SP_USB_RXD = IOMUX_PIN(1, 3, 7, 1, 3, 28),
231 MXC91231_PIN_SP_UH2_TXOE_B = IOMUX_PIN(1, 3, 8, 2, 0, 28),
232 MXC91231_PIN_SP_UH2_SPEED = IOMUX_PIN(1, 3, 9, 2, 1, 28),
233 MXC91231_PIN_SP_UH2_SUSPEN = IOMUX_PIN(1, 3, 10, 2, 2, 28),
234 MXC91231_PIN_SP_UH2_TXDP = IOMUX_PIN(1, 3, 11, 2, 3, 28),
235 MXC91231_PIN_SP_UH2_RXDP = IOMUX_PIN(1, 3, 12, 3, 0, 28),
236 MXC91231_PIN_SP_UH2_RXDM = IOMUX_PIN(1, 3, 13, 3, 1, 28),
237 MXC91231_PIN_SP_UH2_OVR = IOMUX_PIN(1, 3, 14, 3, 2, 28),
238 MXC91231_PIN_SP_UH2_PWR = IOMUX_PIN(1, 3, 15, 3, 3, 28),
239 MXC91231_PIN_SP_SD1_DAT0 = IOMUX_PIN(1, 3, 16, 4, 0, 25),
240 MXC91231_PIN_SP_SD1_DAT1 = IOMUX_PIN(1, 3, 17, 4, 1, 25),
241 MXC91231_PIN_SP_SD1_DAT2 = IOMUX_PIN(1, 3, 18, 4, 2, 25),
242 MXC91231_PIN_SP_SD1_DAT3 = IOMUX_PIN(1, 3, 19, 4, 3, 25),
243 MXC91231_PIN_SP_SD1_CMD = IOMUX_PIN(1, 3, 20, 5, 0, 25),
244 MXC91231_PIN_SP_SD1_CLK = IOMUX_PIN(1, 3, 21, 5, 1, 25),
245 MXC91231_PIN_SP_SD2_DAT0 = IOMUX_PIN(1, 3, 22, 5, 2, 26),
246 MXC91231_PIN_SP_SD2_DAT1 = IOMUX_PIN(1, 3, 23, 5, 3, 26),
247 MXC91231_PIN_SP_SD2_DAT2 = IOMUX_PIN(1, 3, 24, 6, 0, 26),
248 MXC91231_PIN_SP_SD2_DAT3 = IOMUX_PIN(1, 3, 25, 6, 1, 26),
249 MXC91231_PIN_SP_GPIO_SP_A26 = IOMUX_PIN(1, 3, 26, 6, 2, 28),
250 MXC91231_PIN_SP_SPI1_CLK = IOMUX_PIN(1, 3, 27, 6, 3, 13),
251 MXC91231_PIN_SP_SPI1_MOSI = IOMUX_PIN(1, 3, 28, 7, 0, 13),
252 MXC91231_PIN_SP_SPI1_MISO = IOMUX_PIN(1, 3, 29, 7, 1, 13),
253 MXC91231_PIN_SP_SPI1_SS0 = IOMUX_PIN(1, 3, 30, 7, 2, 13),
254 MXC91231_PIN_SP_SPI1_SS1 = IOMUX_PIN(1, 3, 31, 7, 3, 13),
255 MXC91231_PIN_SP_SD2_CMD = IOMUX_PIN(1, 7, 0, 8, 0, 26),
256 MXC91231_PIN_SP_SD2_CLK = IOMUX_PIN(1, 7, 0, 8, 1, 26),
257 MXC91231_PIN_SP_SIM1_RST_B = IOMUX_PIN(1, 2, 30, 8, 2, 28),
258 MXC91231_PIN_SP_SIM1_SVEN = IOMUX_PIN(1, 7, 0, 8, 3, 28),
259 MXC91231_PIN_SP_SIM1_CLK = IOMUX_PIN(1, 7, 0, 9, 0, 28),
260 MXC91231_PIN_SP_SIM1_TRXD = IOMUX_PIN(1, 7, 0, 9, 1, 28),
261 MXC91231_PIN_SP_SIM1_PD = IOMUX_PIN(1, 2, 31, 9, 2, 28),
262 MXC91231_PIN_SP_UH2_TXDM = IOMUX_PIN(1, 7, 0, 9, 3, 28),
263 MXC91231_PIN_SP_UH2_RXD = IOMUX_PIN(1, 7, 0, 10, 0, 28),
264};
265
266#define PIN_AP_MAX (104)
267#define PIN_SP_MAX (41)
268
269#define PIN_MAX (PIN_AP_MAX + PIN_SP_MAX)
270
271/*
272 * Convenience values for use with mxc_iomux_mode()
273 *
274 * Format here is MXC91231_PIN_(pin name)__(function)
275 */
276
277#define MXC91231_PIN_SP_USB_DAT_VP__USB_DAT_VP \
278 IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_FUNC)
279#define MXC91231_PIN_SP_USB_SE0_VM__USB_SE0_VM \
280 IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_FUNC)
281#define MXC91231_PIN_SP_USB_DAT_VP__RXD2 \
282 IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_ALT1)
283#define MXC91231_PIN_SP_USB_SE0_VM__TXD2 \
284 IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_ALT1)
285
286
287#endif /* __MACH_IOMUX_MXC91231_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 22:03:14 -0500