Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm

A few more things this time around.  The only thing warranting some
commentry is the modpost change, which allows folk building a Thumb2
enabled kernel to see section mismatch warnings.  This is why many
weren't noticed with OMAP.

* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
  ARM/audit: include audit header and fix audit arch
  ARM: OMAP: fix voltage domain build errors with PM_OPP disabled
  ARM/PCI: Remove ARM's duplicate definition of 'pcibios_max_latency'
  ARM: 7336/1: smp_twd: Don't register CPUFREQ notifiers if local timers are not initialised
  ARM: 7327/1: need to include asm/system.h in asm/processor.h
  ARM: 7326/2: PL330: fix null pointer dereference in pl330_chan_ctrl()
  ARM: 7164/3: PL330: Fix the size of the dst_cache_ctrl field
  ARM: 7325/1: fix v7 boot with lockdep enabled
  ARM: 7324/1: modpost: Fix section warnings for ARM for many compilers
  ARM: 7323/1: Do not allow ARM_LPAE on pre-ARMv7 architectures

11 files changed, 25 insertions, 13 deletions

diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index d1bcd7b13ebc..fb1f1cfce60c 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -320,13 +320,6 @@ err0:
         return -EBUSY;
 }
 
-/*
- * If we set up a device for bus mastering, we need to check the latency
- * timer as we don't have even crappy BIOSes to set it properly.
- * The implementation is from arch/i386/pci/i386.c
- */
-unsigned int pcibios_max_latency = 255;
-
 /* ITE bridge requires setting latency timer to avoid early bus access
    termination by PCI bus master devices
 */
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c
index d8e44a43047c..ff3ad2244824 100644
--- a/arch/arm/common/pl330.c
+++ b/arch/arm/common/pl330.c
@@ -1502,12 +1502,13 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
         struct pl330_thread *thrd = ch_id;
         struct pl330_dmac *pl330;
         unsigned long flags;
-        int ret = 0, active = thrd->req_running;
+        int ret = 0, active;
 
         if (!thrd || thrd->free || thrd->dmac->state == DYING)
                 return -EINVAL;
 
         pl330 = thrd->dmac;
+        active = thrd->req_running;
 
         spin_lock_irqsave(&pl330->lock, flags);
 
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 62f8095d46de..23371b17b23e 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -137,6 +137,11 @@
         disable_irq
         .endm
 
+        .macro  save_and_disable_irqs_notrace, oldcpsr
+        mrs     \oldcpsr, cpsr
+        disable_irq_notrace
+        .endm
+
 /*
  * Restore interrupt state previously stored in a register.  We don't
  * guarantee that this will preserve the flags.
diff --git a/arch/arm/include/asm/hardware/pl330.h b/arch/arm/include/asm/hardware/pl330.h
index 575fa8186ca0..c1821385abfa 100644
--- a/arch/arm/include/asm/hardware/pl330.h
+++ b/arch/arm/include/asm/hardware/pl330.h
@@ -41,7 +41,7 @@ enum pl330_dstcachectrl {
         DCCTRL1, /* Bufferable only */
         DCCTRL2, /* Cacheable, but do not allocate */
         DCCTRL3, /* Cacheable and bufferable, but do not allocate */
-        DINVALID1 = 8,
+        DINVALID1,              /* AWCACHE = 0x1000 */
         DINVALID2,
         DCCTRL6, /* Cacheable write-through, allocate on writes only */
         DCCTRL7, /* Cacheable write-back, allocate on writes only */
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index ce280b8d613c..cb8d638924fd 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -22,6 +22,7 @@
 #include <asm/hw_breakpoint.h>
 #include <asm/ptrace.h>
 #include <asm/types.h>
+#include <asm/system.h>
 
 #ifdef __KERNEL__
 #define STACK_TOP       ((current->personality & ADDR_LIMIT_32BIT) ? \
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index e33870ff0ac0..ede6443c34d9 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -23,6 +23,7 @@
 #include <linux/perf_event.h>
 #include <linux/hw_breakpoint.h>
 #include <linux/regset.h>
+#include <linux/audit.h>
 
 #include <asm/pgtable.h>
 #include <asm/system.h>
@@ -904,6 +905,12 @@ long arch_ptrace(struct task_struct *child, long request,
         return ret;
 }
 
+#ifdef __ARMEB__
+#define AUDIT_ARCH_NR AUDIT_ARCH_ARMEB
+#else
+#define AUDIT_ARCH_NR AUDIT_ARCH_ARM
+#endif
+
 asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
 {
         unsigned long ip;
@@ -918,7 +925,7 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
         if (!ip)
                 audit_syscall_exit(regs);
         else
-                audit_syscall_entry(AUDIT_ARCH_ARMEB, scno, regs->ARM_r0,
+                audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0,
                                     regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
 
         if (!test_thread_flag(TIF_SYSCALL_TRACE))
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 4285daa077b0..7a79b24597b2 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -129,7 +129,7 @@ static struct notifier_block twd_cpufreq_nb = {
 
 static int twd_cpufreq_init(void)
 {
-        if (!IS_ERR(twd_clk))
+        if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
                 return cpufreq_register_notifier(&twd_cpufreq_nb,
                         CPUFREQ_TRANSITION_NOTIFIER);
 
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
index c005e2f5e383..57db2038b23c 100644
--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -108,6 +108,7 @@ void __init omap3xxx_voltagedomains_init(void)
          * XXX Will depend on the process, validation, and binning
          * for the currently-running IC
          */
+#ifdef CONFIG_PM_OPP
         if (cpu_is_omap3630()) {
                 omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data;
                 omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data;
@@ -115,6 +116,7 @@ void __init omap3xxx_voltagedomains_init(void)
                 omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data;
                 omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data;
         }
+#endif
 
         if (cpu_is_omap3517() || cpu_is_omap3505())
                 voltdms = voltagedomains_am35xx;
diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
index 4e11d022595d..c3115f6853d4 100644
--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
@@ -100,9 +100,11 @@ void __init omap44xx_voltagedomains_init(void)
          * XXX Will depend on the process, validation, and binning
          * for the currently-running IC
          */
+#ifdef CONFIG_PM_OPP
         omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data;
         omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data;
         omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data;
+#endif
 
         for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++)
                 voltdm->sys_clk.name = sys_clk_name;
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 1a3ca2488164..7edef9121632 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -631,7 +631,8 @@ comment "Processor Features"
 
 config ARM_LPAE
         bool "Support for the Large Physical Address Extension"
-        depends on MMU && CPU_V7
+        depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
+                !CPU_32v4 && !CPU_32v3
         help
           Say Y if you have an ARMv7 processor supporting the LPAE page
           table format and you would like to access memory beyond the
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 7a24d39661f0..a655d3da386d 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -55,7 +55,7 @@ loop1:
         cmp     r1, #2                          @ see what cache we have at this level
         blt     skip                            @ skip if no cache, or just i-cache
 #ifdef CONFIG_PREEMPT
-        save_and_disable_irqs r9                @ make cssr&csidr read atomic
+        save_and_disable_irqs_notrace r9        @ make cssr&csidr read atomic
 #endif
         mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
         isb                                     @ isb to sych the new cssr&csidr