Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

Conflicts:
	drivers/mtd/mtdcore.c

Merged in order that I can apply the Nomadik nand/onenand support patches.

641 files changed, 65807 insertions, 3915 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index aef63c8e3d2d..d778a699f577 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -46,10 +46,6 @@ config GENERIC_CLOCKEVENTS_BROADCAST
         depends on GENERIC_CLOCKEVENTS
         default y if SMP && !LOCAL_TIMERS
 
-config MMU
-        bool
-        default y
-
 config NO_IOPORT
         bool
 
@@ -126,6 +122,13 @@ config ARCH_HAS_ILOG2_U32
 config ARCH_HAS_ILOG2_U64
         bool
 
+config ARCH_HAS_CPUFREQ
+        bool
+        help
+          Internal node to signify that the ARCH has CPUFREQ support
+          and that the relevant menu configurations are displayed for
+          it.
+
 config GENERIC_HWEIGHT
         bool
         default y
@@ -188,6 +191,13 @@ source "kernel/Kconfig.freezer"
 
 menu "System Type"
 
+config MMU
+        bool "MMU-based Paged Memory Management Support"
+        default y
+        help
+          Select if you want MMU-based virtualised addressing space
+          support by paged memory management. If unsure, say 'Y'.
+
 choice
         prompt "ARM system type"
         default ARCH_VERSATILE
@@ -203,6 +213,7 @@ config ARCH_AAEC2000
 config ARCH_INTEGRATOR
         bool "ARM Ltd. Integrator family"
         select ARM_AMBA
+        select ARCH_HAS_CPUFREQ
         select HAVE_CLK
         select COMMON_CLKDEV
         select ICST525
@@ -217,6 +228,7 @@ config ARCH_REALVIEW
         select ICST307
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         help
           This enables support for ARM Ltd RealView boards.
 
@@ -229,6 +241,7 @@ config ARCH_VERSATILE
         select ICST307
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         help
           This enables support for ARM Ltd Versatile board.
 
@@ -327,6 +340,20 @@ config ARCH_H720X
         help
           This enables support for systems based on the Hynix HMS720x
 
+config ARCH_NOMADIK
+        bool "STMicroelectronics Nomadik"
+        select ARM_AMBA
+        select ARM_VIC
+        select CPU_ARM926T
+        select HAVE_CLK
+        select COMMON_CLKDEV
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        help
+          Support for the Nomadik platform by ST-Ericsson
+
 config ARCH_IOP13XX
         bool "IOP13xx-based"
         depends on MMU
@@ -493,10 +520,18 @@ config ARCH_W90X900
         select CPU_ARM926T
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_GPIO
+        select HAVE_CLK
         select COMMON_CLKDEV
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
         help
-                Support for Nuvoton (Winbond logic dept.) ARM9 processor,You
-                can login www.mcuos.com or www.nuvoton.com to know more.
+          Support for Nuvoton (Winbond logic dept.) ARM9 processor,
+          At present, the w90x900 has been renamed nuc900, regarding
+          the ARM series product line, you can login the following
+          link address to know more.
+
+          <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
+                ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 
 config ARCH_PNX4008
         bool "Philips Nexperia PNX4008 Mobile"
@@ -509,6 +544,7 @@ config ARCH_PXA
         bool "PXA2xx/PXA3xx-based"
         depends on MMU
         select ARCH_MTD_XIP
+        select ARCH_HAS_CPUFREQ
         select GENERIC_GPIO
         select HAVE_CLK
         select COMMON_CLKDEV
@@ -551,6 +587,7 @@ config ARCH_SA1100
         select ISA
         select ARCH_SPARSEMEM_ENABLE
         select ARCH_MTD_XIP
+        select ARCH_HAS_CPUFREQ
         select GENERIC_GPIO
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
@@ -563,6 +600,7 @@ config ARCH_SA1100
 config ARCH_S3C2410
         bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
         select GENERIC_GPIO
+        select ARCH_HAS_CPUFREQ
         select HAVE_CLK
         help
           Samsung S3C2410X CPU based systems, such as the Simtec Electronics
@@ -573,9 +611,18 @@ config ARCH_S3C64XX
         bool "Samsung S3C64XX"
         select GENERIC_GPIO
         select HAVE_CLK
+        select ARCH_HAS_CPUFREQ
         help
           Samsung S3C64XX series based systems
 
+config ARCH_S5PC1XX
+        bool "Samsung S5PC1XX"
+        select GENERIC_GPIO
+        select HAVE_CLK
+        select CPU_V7
+        help
+          Samsung S5PC1XX series based systems
+
 config ARCH_SHARK
         bool "Shark"
         select CPU_SA110
@@ -632,11 +679,24 @@ config ARCH_OMAP
         select GENERIC_GPIO
         select HAVE_CLK
         select ARCH_REQUIRE_GPIOLIB
+        select ARCH_HAS_CPUFREQ
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         help
           Support for TI's OMAP platform (OMAP1 and OMAP2).
 
+config ARCH_BCMRING
+        bool "Broadcom BCMRING"
+        depends on MMU
+        select CPU_V6
+        select ARM_AMBA
+        select COMMON_CLKDEV
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        help
+          Support for Broadcom's BCMRing platform.
+
 endchoice
 
 source "arch/arm/mach-clps711x/Kconfig"
@@ -685,6 +745,7 @@ source "arch/arm/mach-kirkwood/Kconfig"
 source "arch/arm/plat-s3c24xx/Kconfig"
 source "arch/arm/plat-s3c64xx/Kconfig"
 source "arch/arm/plat-s3c/Kconfig"
+source "arch/arm/plat-s5pc1xx/Kconfig"
 
 if ARCH_S3C2410
 source "arch/arm/mach-s3c2400/Kconfig"
@@ -702,6 +763,10 @@ endif
 
 source "arch/arm/plat-stmp3xxx/Kconfig"
 
+if ARCH_S5PC1XX
+source "arch/arm/mach-s5pc100/Kconfig"
+endif
+
 source "arch/arm/mach-lh7a40x/Kconfig"
 
 source "arch/arm/mach-h720x/Kconfig"
@@ -716,6 +781,8 @@ source "arch/arm/mach-at91/Kconfig"
 
 source "arch/arm/plat-mxc/Kconfig"
 
+source "arch/arm/mach-nomadik/Kconfig"
+
 source "arch/arm/mach-netx/Kconfig"
 
 source "arch/arm/mach-ns9xxx/Kconfig"
@@ -730,6 +797,8 @@ source "arch/arm/mach-u300/Kconfig"
 
 source "arch/arm/mach-w90x900/Kconfig"
 
+source "arch/arm/mach-bcmring/Kconfig"
+
 # Definitions to make life easier
 config ARCH_ACORN
         bool
@@ -962,18 +1031,7 @@ config LOCAL_TIMERS
           accounting to be spread across the timer interval, preventing a
           "thundering herd" at every timer tick.
 
-config PREEMPT
-        bool "Preemptible Kernel (EXPERIMENTAL)"
-        depends on EXPERIMENTAL
-        help
-          This option reduces the latency of the kernel when reacting to
-          real-time or interactive events by allowing a low priority process to
-          be preempted even if it is in kernel mode executing a system call.
-          This allows applications to run more reliably even when the system is
-          under load.
-
-          Say Y here if you are building a kernel for a desktop, embedded
-          or real-time system.  Say N if you are unsure.
+source kernel/Kconfig.preempt
 
 config HZ
         int
@@ -983,6 +1041,21 @@ config HZ
         default AT91_TIMER_HZ if ARCH_AT91
         default 100
 
+config THUMB2_KERNEL
+        bool "Compile the kernel in Thumb-2 mode"
+        depends on CPU_V7 && EXPERIMENTAL
+        select AEABI
+        select ARM_ASM_UNIFIED
+        help
+          By enabling this option, the kernel will be compiled in
+          Thumb-2 mode. A compiler/assembler that understand the unified
+          ARM-Thumb syntax is needed.
+
+          If unsure, say N.
+
+config ARM_ASM_UNIFIED
+        bool
+
 config AEABI
         bool "Use the ARM EABI to compile the kernel"
         help
@@ -1054,6 +1127,11 @@ config HIGHMEM
 
           If unsure, say n.
 
+config HIGHPTE
+        bool "Allocate 2nd-level pagetables from highmem"
+        depends on HIGHMEM
+        depends on !OUTER_CACHE
+
 source "mm/Kconfig"
 
 config LEDS
@@ -1241,7 +1319,7 @@ endmenu
 
 menu "CPU Power Management"
 
-if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA || ARCH_S3C64XX)
+if ARCH_HAS_CPUFREQ
 
 source "drivers/cpufreq/Kconfig"
 
@@ -1276,6 +1354,52 @@ config CPU_FREQ_S3C64XX
         bool "CPUfreq support for Samsung S3C64XX CPUs"
         depends on CPU_FREQ && CPU_S3C6410
 
+config CPU_FREQ_S3C
+        bool
+        help
+          Internal configuration node for common cpufreq on Samsung SoC
+
+config CPU_FREQ_S3C24XX
+        bool "CPUfreq driver for Samsung S3C24XX series CPUs"
+        depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
+        select CPU_FREQ_S3C
+        help
+          This enables the CPUfreq driver for the Samsung S3C24XX family
+          of CPUs.
+
+          For details, take a look at <file:Documentation/cpu-freq>.
+
+          If in doubt, say N.
+
+config CPU_FREQ_S3C24XX_PLL
+        bool "Support CPUfreq changing of PLL frequency"
+        depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
+        help
+          Compile in support for changing the PLL frequency from the
+          S3C24XX series CPUfreq driver. The PLL takes time to settle
+          after a frequency change, so by default it is not enabled.
+
+          This also means that the PLL tables for the selected CPU(s) will
+          be built which may increase the size of the kernel image.
+
+config CPU_FREQ_S3C24XX_DEBUG
+        bool "Debug CPUfreq Samsung driver core"
+        depends on CPU_FREQ_S3C24XX
+        help
+          Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
+
+config CPU_FREQ_S3C24XX_IODEBUG
+        bool "Debug CPUfreq Samsung driver IO timing"
+        depends on CPU_FREQ_S3C24XX
+        help
+          Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
+
+config CPU_FREQ_S3C24XX_DEBUGFS
+        bool "Export debugfs for CPUFreq"
+        depends on CPU_FREQ_S3C24XX && DEBUG_FS
+        help
+          Export status information via debugfs.
+
 endif
 
 source "drivers/cpuidle/Kconfig"
@@ -1377,107 +1501,7 @@ endmenu
 
 source "net/Kconfig"
 
-menu "Device Drivers"
-
-source "drivers/base/Kconfig"
-
-source "drivers/connector/Kconfig"
-
-if ALIGNMENT_TRAP || !CPU_CP15_MMU
-source "drivers/mtd/Kconfig"
-endif
-
-source "drivers/parport/Kconfig"
-
-source "drivers/pnp/Kconfig"
-
-source "drivers/block/Kconfig"
-
-# misc before ide - BLK_DEV_SGIIOC4 depends on SGI_IOC4
-
-source "drivers/misc/Kconfig"
-
-source "drivers/ide/Kconfig"
-
-source "drivers/scsi/Kconfig"
-
-source "drivers/ata/Kconfig"
-
-source "drivers/md/Kconfig"
-
-source "drivers/message/fusion/Kconfig"
-
-source "drivers/ieee1394/Kconfig"
-
-source "drivers/message/i2o/Kconfig"
-
-source "drivers/net/Kconfig"
-
-source "drivers/isdn/Kconfig"
-
-# input before char - char/joystick depends on it. As does USB.
-
-source "drivers/input/Kconfig"
-
-source "drivers/char/Kconfig"
-
-source "drivers/i2c/Kconfig"
-
-source "drivers/spi/Kconfig"
-
-source "drivers/gpio/Kconfig"
-
-source "drivers/w1/Kconfig"
-
-source "drivers/power/Kconfig"
-
-source "drivers/hwmon/Kconfig"
-
-source "drivers/thermal/Kconfig"
-
-source "drivers/watchdog/Kconfig"
-
-source "drivers/ssb/Kconfig"
-
-#source "drivers/l3/Kconfig"
-
-source "drivers/mfd/Kconfig"
-
-source "drivers/media/Kconfig"
-
-source "drivers/video/Kconfig"
-
-source "sound/Kconfig"
-
-source "drivers/hid/Kconfig"
-
-source "drivers/usb/Kconfig"
-
-source "drivers/uwb/Kconfig"
-
-source "drivers/mmc/Kconfig"
-
-source "drivers/memstick/Kconfig"
-
-source "drivers/accessibility/Kconfig"
-
-source "drivers/leds/Kconfig"
-
-source "drivers/rtc/Kconfig"
-
-source "drivers/dma/Kconfig"
-
-source "drivers/dca/Kconfig"
-
-source "drivers/auxdisplay/Kconfig"
-
-source "drivers/regulator/Kconfig"
-
-source "drivers/uio/Kconfig"
-
-source "drivers/staging/Kconfig"
-
-endmenu
+source "drivers/Kconfig"
 
 source "fs/Kconfig"
 
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index a89e4734b8f0..1a6f70e52921 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -8,6 +8,7 @@ source "lib/Kconfig.debug"
 # n, but then RMK will have to kill you ;).
 config FRAME_POINTER
         bool
+        depends on !THUMB2_KERNEL
         default y if !ARM_UNWIND
         help
           If you say N here, the resulting kernel will be slightly smaller and
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c877d6df23d1..7350557a81e0 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -93,9 +93,16 @@ ifeq ($(CONFIG_ARM_UNWIND),y)
 CFLAGS_ABI      +=-funwind-tables
 endif
 
+ifeq ($(CONFIG_THUMB2_KERNEL),y)
+AFLAGS_AUTOIT   :=$(call as-option,-Wa$(comma)-mimplicit-it=thumb,-Wa$(comma)-mauto-it)
+AFLAGS_NOWARN   :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)
+CFLAGS_THUMB2   :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)
+AFLAGS_THUMB2   :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb
+endif
+
 # Need -Uarm for gcc < 3.x
-KBUILD_CFLAGS   +=$(CFLAGS_ABI) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm
-KBUILD_AFLAGS   +=$(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float
+KBUILD_CFLAGS   +=$(CFLAGS_ABI) $(CFLAGS_THUMB2) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm
+KBUILD_AFLAGS   +=$(CFLAGS_ABI) $(AFLAGS_THUMB2) $(arch-y) $(tune-y) -include asm/unified.h -msoft-float
 
 CHECKFLAGS      += -D__arm__
 
@@ -112,6 +119,7 @@ endif
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AAEC2000)         := aaec2000
 machine-$(CONFIG_ARCH_AT91)             := at91
+machine-$(CONFIG_ARCH_BCMRING)          := bcmring
 machine-$(CONFIG_ARCH_CLPS711X)         := clps711x
 machine-$(CONFIG_ARCH_DAVINCI)          := davinci
 machine-$(CONFIG_ARCH_EBSA110)          := ebsa110
@@ -135,8 +143,10 @@ machine-$(CONFIG_ARCH_MSM)		:= msm
 machine-$(CONFIG_ARCH_MV78XX0)          := mv78xx0
 machine-$(CONFIG_ARCH_MX1)              := mx1
 machine-$(CONFIG_ARCH_MX2)              := mx2
+machine-$(CONFIG_ARCH_MX25)             := mx25
 machine-$(CONFIG_ARCH_MX3)              := mx3
 machine-$(CONFIG_ARCH_NETX)             := netx
+machine-$(CONFIG_ARCH_NOMADIK)          := nomadik
 machine-$(CONFIG_ARCH_NS9XXX)           := ns9xxx
 machine-$(CONFIG_ARCH_OMAP1)            := omap1
 machine-$(CONFIG_ARCH_OMAP2)            := omap2
@@ -150,6 +160,7 @@ machine-$(CONFIG_ARCH_RPC)		:= rpc
 machine-$(CONFIG_ARCH_S3C2410)          := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
 machine-$(CONFIG_ARCH_S3C24A0)          := s3c24a0
 machine-$(CONFIG_ARCH_S3C64XX)          := s3c6400 s3c6410
+machine-$(CONFIG_ARCH_S5PC1XX)          := s5pc100
 machine-$(CONFIG_ARCH_SA1100)           := sa1100
 machine-$(CONFIG_ARCH_SHARK)            := shark
 machine-$(CONFIG_ARCH_STMP378X)         := stmp378x
@@ -158,6 +169,7 @@ machine-$(CONFIG_ARCH_U300)		:= u300
 machine-$(CONFIG_ARCH_VERSATILE)        := versatile
 machine-$(CONFIG_ARCH_W90X900)          := w90x900
 machine-$(CONFIG_FOOTBRIDGE)            := footbridge
+machine-$(CONFIG_ARCH_MXC91231)         := mxc91231
 
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
@@ -168,6 +180,7 @@ plat-$(CONFIG_PLAT_ORION)	:= orion
 plat-$(CONFIG_PLAT_PXA)         := pxa
 plat-$(CONFIG_PLAT_S3C24XX)     := s3c24xx s3c
 plat-$(CONFIG_PLAT_S3C64XX)     := s3c64xx s3c
+plat-$(CONFIG_PLAT_S5PC1XX)     := s5pc1xx s3c
 plat-$(CONFIG_ARCH_STMP3XXX)    := stmp3xxx
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index da226abce2d0..4a590f4113e2 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -61,7 +61,7 @@ endif
 
 quiet_cmd_uimage = UIMAGE  $@
       cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
-                   -C none -a $(LOADADDR) -e $(LOADADDR) \
+                   -C none -a $(LOADADDR) -e $(STARTADDR) \
                    -n 'Linux-$(KERNELRELEASE)' -d $< $@
 
 ifeq ($(CONFIG_ZBOOT_ROM),y)
@@ -70,6 +70,13 @@ else
 $(obj)/uImage: LOADADDR=$(ZRELADDR)
 endif
 
+ifeq ($(CONFIG_THUMB2_KERNEL),y)
+# Set bit 0 to 1 so that "mov pc, rx" switches to Thumb-2 mode
+$(obj)/uImage: STARTADDR=$(shell echo $(LOADADDR) | sed -e "s/.$$/1/")
+else
+$(obj)/uImage: STARTADDR=$(LOADADDR)
+endif
+
 $(obj)/uImage:  $(obj)/zImage FORCE
         $(call if_changed,uimage)
         @echo '  Image $@ is ready'
diff --git a/arch/arm/boot/compressed/head-sa1100.S b/arch/arm/boot/compressed/head-sa1100.S
index 4c8c0e46027d..6179d94dd5c6 100644
--- a/arch/arm/boot/compressed/head-sa1100.S
+++ b/arch/arm/boot/compressed/head-sa1100.S
@@ -1,7 +1,7 @@
 /* 
  * linux/arch/arm/boot/compressed/head-sa1100.S
  * 
- * Copyright (C) 1999 Nicolas Pitre <nico@cam.org>
+ * Copyright (C) 1999 Nicolas Pitre <nico@fluxnic.net>
  * 
  * SA1100 specific tweaks.  This is merged into head.S by the linker.
  *
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 4515728c5345..fa6fbf45cf3b 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -140,7 +140,8 @@ start:
                 tst     r2, #3                  @ not user?
                 bne     not_angel
                 mov     r0, #0x17               @ angel_SWIreason_EnterSVC
-                swi     0x123456                @ angel_SWI_ARM
+ ARM(           swi     0x123456        )       @ angel_SWI_ARM
+ THUMB(         svc     0xab            )       @ angel_SWI_THUMB
 not_angel:
                 mrs     r2, cpsr                @ turn off interrupts to
                 orr     r2, r2, #0xc0           @ prevent angel from running
@@ -161,7 +162,9 @@ not_angel:
 
                 .text
                 adr     r0, LC0
-                ldmia   r0, {r1, r2, r3, r4, r5, r6, ip, sp}
+ ARM(           ldmia   r0, {r1, r2, r3, r4, r5, r6, ip, sp}    )
+ THUMB(         ldmia   r0, {r1, r2, r3, r4, r5, r6, ip}        )
+ THUMB(         ldr     sp, [r0, #28]                           )
                 subs    r0, r0, r1              @ calculate the delta offset
 
                                                 @ if delta is zero, we are
@@ -263,22 +266,25 @@ not_relocated:	mov	r0, #0
  * r6     = processor ID
  * r7     = architecture ID
  * r8     = atags pointer
- * r9-r14 = corrupted
+ * r9-r12,r14 = corrupted
  */
                 add     r1, r5, r0              @ end of decompressed kernel
                 adr     r2, reloc_start
                 ldr     r3, LC1
                 add     r3, r2, r3
-1:              ldmia   r2!, {r9 - r14}         @ copy relocation code
-                stmia   r1!, {r9 - r14}
-                ldmia   r2!, {r9 - r14}
-                stmia   r1!, {r9 - r14}
+1:              ldmia   r2!, {r9 - r12, r14}    @ copy relocation code
+                stmia   r1!, {r9 - r12, r14}
+                ldmia   r2!, {r9 - r12, r14}
+                stmia   r1!, {r9 - r12, r14}
                 cmp     r2, r3
                 blo     1b
-                add     sp, r1, #128            @ relocate the stack
+                mov     sp, r1
+                add     sp, sp, #128            @ relocate the stack
 
                 bl      cache_clean_flush
-                add     pc, r5, r0              @ call relocation code
+ ARM(           add     pc, r5, r0              ) @ call relocation code
+ THUMB(         add     r12, r5, r0             )
+ THUMB(         mov     pc, r12                 ) @ call relocation code
 
 /*
  * We're not in danger of overwriting ourselves.  Do this the simple way.
@@ -291,6 +297,7 @@ wont_overwrite:	mov	r0, r4
                 bl      decompress_kernel
                 b       call_kernel
 
+                .align  2
                 .type   LC0, #object
 LC0:            .word   LC0                     @ r1
                 .word   __bss_start             @ r2
@@ -431,6 +438,7 @@ ENDPROC(__setup_mmu)
 
 __armv4_mmu_cache_on:
                 mov     r12, lr
+#ifdef CONFIG_MMU
                 bl      __setup_mmu
                 mov     r0, #0
                 mcr     p15, 0, r0, c7, c10, 4  @ drain write buffer
@@ -444,10 +452,12 @@ __armv4_mmu_cache_on:
                 bl      __common_mmu_cache_on
                 mov     r0, #0
                 mcr     p15, 0, r0, c8, c7, 0   @ flush I,D TLBs
+#endif
                 mov     pc, r12
 
 __armv7_mmu_cache_on:
                 mov     r12, lr
+#ifdef CONFIG_MMU
                 mrc     p15, 0, r11, c0, c1, 4  @ read ID_MMFR0
                 tst     r11, #0xf               @ VMSA
                 blne    __setup_mmu
@@ -455,9 +465,11 @@ __armv7_mmu_cache_on:
                 mcr     p15, 0, r0, c7, c10, 4  @ drain write buffer
                 tst     r11, #0xf               @ VMSA
                 mcrne   p15, 0, r0, c8, c7, 0   @ flush I,D TLBs
+#endif
                 mrc     p15, 0, r0, c1, c0, 0   @ read control reg
                 orr     r0, r0, #0x5000         @ I-cache enable, RR cache replacement
                 orr     r0, r0, #0x003c         @ write buffer
+#ifdef CONFIG_MMU
 #ifdef CONFIG_CPU_ENDIAN_BE8
                 orr     r0, r0, #1 << 25        @ big-endian page tables
 #endif
@@ -465,6 +477,7 @@ __armv7_mmu_cache_on:
                 movne   r1, #-1
                 mcrne   p15, 0, r3, c2, c0, 0   @ load page table pointer
                 mcrne   p15, 0, r1, c3, c0, 0   @ load domain access control
+#endif
                 mcr     p15, 0, r0, c1, c0, 0   @ load control register
                 mrc     p15, 0, r0, c1, c0, 0   @ and read it back
                 mov     r0, #0
@@ -498,6 +511,7 @@ __arm6_mmu_cache_on:
                 mov     pc, r12
 
 __common_mmu_cache_on:
+#ifndef CONFIG_THUMB2_KERNEL
 #ifndef DEBUG
                 orr     r0, r0, #0x000d         @ Write buffer, mmu
 #endif
@@ -509,6 +523,7 @@ __common_mmu_cache_on:
 1:              mcr     p15, 0, r0, c1, c0, 0   @ load control register
                 mrc     p15, 0, r0, c1, c0, 0   @ and read it back to
                 sub     pc, lr, r0, lsr #32     @ properly flush pipeline
+#endif
 
 /*
  * All code following this line is relocatable.  It is relocated by
@@ -522,7 +537,7 @@ __common_mmu_cache_on:
  * r6     = processor ID
  * r7     = architecture ID
  * r8     = atags pointer
- * r9-r14 = corrupted
+ * r9-r12,r14 = corrupted
  */
                 .align  5
 reloc_start:    add     r9, r5, r0
@@ -531,13 +546,14 @@ reloc_start:	add	r9, r5, r0
                 mov     r1, r4
 1:
                 .rept   4
-                ldmia   r5!, {r0, r2, r3, r10 - r14}    @ relocate kernel
-                stmia   r1!, {r0, r2, r3, r10 - r14}
+                ldmia   r5!, {r0, r2, r3, r10 - r12, r14}       @ relocate kernel
+                stmia   r1!, {r0, r2, r3, r10 - r12, r14}
                 .endr
 
                 cmp     r5, r9
                 blo     1b
-                add     sp, r1, #128            @ relocate the stack
+                mov     sp, r1
+                add     sp, sp, #128            @ relocate the stack
                 debug_reloc_end
 
 call_kernel:    bl      cache_clean_flush
@@ -571,7 +587,9 @@ call_cache_fn:	adr	r12, proc_types
                 ldr     r2, [r12, #4]           @ get mask
                 eor     r1, r1, r6              @ (real ^ match)
                 tst     r1, r2                  @       & mask
-                addeq   pc, r12, r3             @ call cache function
+ ARM(           addeq   pc, r12, r3             ) @ call cache function
+ THUMB(         addeq   r12, r3                 )
+ THUMB(         moveq   pc, r12                 ) @ call cache function
                 add     r12, r12, #4*5
                 b       1b
 
@@ -589,13 +607,15 @@ call_cache_fn:	adr	r12, proc_types
  * methods.  Writeback caches _must_ have the flush method
  * defined.
  */
+                .align  2
                 .type   proc_types,#object
 proc_types:
                 .word   0x41560600              @ ARM6/610
                 .word   0xffffffe0
-                b       __arm6_mmu_cache_off    @ works, but slow
-                b       __arm6_mmu_cache_off
+                W(b)    __arm6_mmu_cache_off    @ works, but slow
+                W(b)    __arm6_mmu_cache_off
                 mov     pc, lr
+ THUMB(         nop                             )
 @               b       __arm6_mmu_cache_on             @ untested
 @               b       __arm6_mmu_cache_off
 @               b       __armv3_mmu_cache_flush
@@ -603,76 +623,84 @@ proc_types:
                 .word   0x00000000              @ old ARM ID
                 .word   0x0000f000
                 mov     pc, lr
+ THUMB(         nop                             )
                 mov     pc, lr
+ THUMB(         nop                             )
                 mov     pc, lr
+ THUMB(         nop                             )
 
                 .word   0x41007000              @ ARM7/710
                 .word   0xfff8fe00
-                b       __arm7_mmu_cache_off
-                b       __arm7_mmu_cache_off
+                W(b)    __arm7_mmu_cache_off
+                W(b)    __arm7_mmu_cache_off
                 mov     pc, lr
+ THUMB(         nop                             )
 
                 .word   0x41807200              @ ARM720T (writethrough)
                 .word   0xffffff00
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
                 mov     pc, lr
+ THUMB(         nop                             )
 
                 .word   0x41007400              @ ARM74x
                 .word   0xff00ff00
-                b       __armv3_mpu_cache_on
-                b       __armv3_mpu_cache_off
-                b       __armv3_mpu_cache_flush
+                W(b)    __armv3_mpu_cache_on
+                W(b)    __armv3_mpu_cache_off
+                W(b)    __armv3_mpu_cache_flush
                 
                 .word   0x41009400              @ ARM94x
                 .word   0xff00ff00
-                b       __armv4_mpu_cache_on
-                b       __armv4_mpu_cache_off
-                b       __armv4_mpu_cache_flush
+                W(b)    __armv4_mpu_cache_on
+                W(b)    __armv4_mpu_cache_off
+                W(b)    __armv4_mpu_cache_flush
 
                 .word   0x00007000              @ ARM7 IDs
                 .word   0x0000f000
                 mov     pc, lr
+ THUMB(         nop                             )
                 mov     pc, lr
+ THUMB(         nop                             )
                 mov     pc, lr
+ THUMB(         nop                             )
 
                 @ Everything from here on will be the new ID system.
 
                 .word   0x4401a100              @ sa110 / sa1100
                 .word   0xffffffe0
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_flush
 
                 .word   0x6901b110              @ sa1110
                 .word   0xfffffff0
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_flush
 
                 .word   0x56056930
                 .word   0xff0ffff0              @ PXA935
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_flush
 
                 .word   0x56158000              @ PXA168
                 .word   0xfffff000
-                b __armv4_mmu_cache_on
-                b __armv4_mmu_cache_off
-                b __armv5tej_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv5tej_mmu_cache_flush
 
                 .word   0x56056930
                 .word   0xff0ffff0              @ PXA935
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_flush
 
                 .word   0x56050000              @ Feroceon
                 .word   0xff0f0000
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv5tej_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv5tej_mmu_cache_flush
 
 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
                 /* this conflicts with the standard ARMv5TE entry */
@@ -685,47 +713,50 @@ proc_types:
 
                 .word   0x66015261              @ FA526
                 .word   0xff01fff1
-                b       __fa526_cache_on
-                b       __armv4_mmu_cache_off
-                b       __fa526_cache_flush
+                W(b)    __fa526_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __fa526_cache_flush
 
                 @ These match on the architecture ID
 
                 .word   0x00020000              @ ARMv4T
                 .word   0x000f0000
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_flush
 
                 .word   0x00050000              @ ARMv5TE
                 .word   0x000f0000
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_flush
 
                 .word   0x00060000              @ ARMv5TEJ
                 .word   0x000f0000
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv5tej_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_flush
 
                 .word   0x0007b000              @ ARMv6
                 .word   0x000ff000
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv6_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv6_mmu_cache_flush
 
                 .word   0x000f0000              @ new CPU Id
                 .word   0x000f0000
-                b       __armv7_mmu_cache_on
-                b       __armv7_mmu_cache_off
-                b       __armv7_mmu_cache_flush
+                W(b)    __armv7_mmu_cache_on
+                W(b)    __armv7_mmu_cache_off
+                W(b)    __armv7_mmu_cache_flush
 
                 .word   0                       @ unrecognised type
                 .word   0
                 mov     pc, lr
+ THUMB(         nop                             )
                 mov     pc, lr
+ THUMB(         nop                             )
                 mov     pc, lr
+ THUMB(         nop                             )
 
                 .size   proc_types, . - proc_types
 
@@ -760,22 +791,30 @@ __armv3_mpu_cache_off:
                 mov     pc, lr
 
 __armv4_mmu_cache_off:
+#ifdef CONFIG_MMU
                 mrc     p15, 0, r0, c1, c0
                 bic     r0, r0, #0x000d
                 mcr     p15, 0, r0, c1, c0      @ turn MMU and cache off
                 mov     r0, #0
                 mcr     p15, 0, r0, c7, c7      @ invalidate whole cache v4
                 mcr     p15, 0, r0, c8, c7      @ invalidate whole TLB v4
+#endif
                 mov     pc, lr
 
 __armv7_mmu_cache_off:
                 mrc     p15, 0, r0, c1, c0
+#ifdef CONFIG_MMU
                 bic     r0, r0, #0x000d
+#else
+                bic     r0, r0, #0x000c
+#endif
                 mcr     p15, 0, r0, c1, c0      @ turn MMU and cache off
                 mov     r12, lr
                 bl      __armv7_mmu_cache_flush
                 mov     r0, #0
+#ifdef CONFIG_MMU
                 mcr     p15, 0, r0, c8, c7, 0   @ invalidate whole TLB
+#endif
                 mcr     p15, 0, r0, c7, c5, 6   @ invalidate BTC
                 mcr     p15, 0, r0, c7, c10, 4  @ DSB
                 mcr     p15, 0, r0, c7, c5, 4   @ ISB
@@ -852,7 +891,7 @@ __armv7_mmu_cache_flush:
                 b       iflush
 hierarchical:
                 mcr     p15, 0, r10, c7, c10, 5 @ DMB
-                stmfd   sp!, {r0-r5, r7, r9, r11}
+                stmfd   sp!, {r0-r7, r9-r11}
                 mrc     p15, 1, r0, c0, c0, 1   @ read clidr
                 ands    r3, r0, #0x7000000      @ extract loc from clidr
                 mov     r3, r3, lsr #23         @ left align loc bit field
@@ -877,8 +916,12 @@ loop1:
 loop2:
                 mov     r9, r4                  @ create working copy of max way size
 loop3:
-                orr     r11, r10, r9, lsl r5    @ factor way and cache number into r11
-                orr     r11, r11, r7, lsl r2    @ factor index number into r11
+ ARM(           orr     r11, r10, r9, lsl r5    ) @ factor way and cache number into r11
+ ARM(           orr     r11, r11, r7, lsl r2    ) @ factor index number into r11
+ THUMB(         lsl     r6, r9, r5              )
+ THUMB(         orr     r11, r10, r6            ) @ factor way and cache number into r11
+ THUMB(         lsl     r6, r7, r2              )
+ THUMB(         orr     r11, r11, r6            ) @ factor index number into r11
                 mcr     p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
                 subs    r9, r9, #1              @ decrement the way
                 bge     loop3
@@ -889,7 +932,7 @@ skip:
                 cmp     r3, r10
                 bgt     loop1
 finished:
-                ldmfd   sp!, {r0-r5, r7, r9, r11}
+                ldmfd   sp!, {r0-r7, r9-r11}
                 mov     r10, #0                 @ swith back to cache level 0
                 mcr     p15, 2, r10, c0, c0, 0  @ select current cache level in cssr
 iflush:
@@ -923,9 +966,13 @@ __armv4_mmu_cache_flush:
                 mov     r11, #8
                 mov     r11, r11, lsl r3        @ cache line size in bytes
 no_cache_id:
-                bic     r1, pc, #63             @ align to longest cache line
+                mov     r1, pc
+                bic     r1, r1, #63             @ align to longest cache line
                 add     r2, r1, r2
-1:              ldr     r3, [r1], r11           @ s/w flush D cache
+1:
+ ARM(           ldr     r3, [r1], r11           ) @ s/w flush D cache
+ THUMB(         ldr     r3, [r1]                ) @ s/w flush D cache
+ THUMB(         add     r1, r1, r11             )
                 teq     r1, r2
                 bne     1b
 
@@ -945,6 +992,7 @@ __armv3_mpu_cache_flush:
  * memory, which again must be relocatable.
  */
 #ifdef DEBUG
+                .align  2
                 .type   phexbuf,#object
 phexbuf:        .space  12
                 .size   phexbuf, . - phexbuf
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 6ed89836e908..920ced0b73c5 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -22,10 +22,20 @@
 #include <linux/list.h>
 #include <linux/io.h>
 #include <linux/sysdev.h>
+#include <linux/amba/bus.h>
 
 #include <asm/mach/irq.h>
 #include <asm/hardware/vic.h>
 
+static void vic_ack_irq(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        irq &= 31;
+        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
+        /* moreover, clear the soft-triggered, in case it was the reason */
+        writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
+}
+
 static void vic_mask_irq(unsigned int irq)
 {
         void __iomem *base = get_irq_chip_data(irq);
@@ -253,12 +263,16 @@ static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg
 
 static struct irq_chip vic_chip = {
         .name   = "VIC",
-        .ack    = vic_mask_irq,
+        .ack    = vic_ack_irq,
         .mask   = vic_mask_irq,
         .unmask = vic_unmask_irq,
         .set_wake = vic_set_wake,
 };
 
+/* The PL190 cell from ARM has been modified by ST, so handle both here */
+static void vik_init_st(void __iomem *base, unsigned int irq_start,
+                         u32 vic_sources);
+
 /**
  * vic_init - initialise a vectored interrupt controller
  * @base: iomem base address
@@ -270,6 +284,28 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
                      u32 vic_sources, u32 resume_sources)
 {
         unsigned int i;
+        u32 cellid = 0;
+        enum amba_vendor vendor;
+
+        /* Identify which VIC cell this one is, by reading the ID */
+        for (i = 0; i < 4; i++) {
+                u32 addr = ((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
+                cellid |= (readl(addr) & 0xff) << (8 * i);
+        }
+        vendor = (cellid >> 12) & 0xff;
+        printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
+               base, cellid, vendor);
+
+        switch(vendor) {
+        case AMBA_VENDOR_ST:
+                vik_init_st(base, irq_start, vic_sources);
+                return;
+        default:
+                printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
+                /* fall through */
+        case AMBA_VENDOR_ARM:
+                break;
+        }
 
         /* Disable all interrupts initially. */
 
@@ -306,3 +342,60 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
 
         vic_pm_register(base, irq_start, resume_sources);
 }
+
+/*
+ * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
+ * The original cell has 32 interrupts, while the modified one has 64,
+ * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
+ * the probe function is called twice, with base set to offset 000
+ *  and 020 within the page. We call this "second block".
+ */
+static void __init vik_init_st(void __iomem *base, unsigned int irq_start,
+                                u32 vic_sources)
+{
+        unsigned int i;
+        int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
+
+        /* Disable all interrupts initially. */
+
+        writel(0, base + VIC_INT_SELECT);
+        writel(0, base + VIC_INT_ENABLE);
+        writel(~0, base + VIC_INT_ENABLE_CLEAR);
+        writel(0, base + VIC_IRQ_STATUS);
+        writel(0, base + VIC_ITCR);
+        writel(~0, base + VIC_INT_SOFT_CLEAR);
+
+        /*
+         * Make sure we clear all existing interrupts. The vector registers
+         * in this cell are after the second block of general registers,
+         * so we can address them using standard offsets, but only from
+         * the second base address, which is 0x20 in the page
+         */
+        if (vic_2nd_block) {
+                writel(0, base + VIC_PL190_VECT_ADDR);
+                for (i = 0; i < 19; i++) {
+                        unsigned int value;
+
+                        value = readl(base + VIC_PL190_VECT_ADDR);
+                        writel(value, base + VIC_PL190_VECT_ADDR);
+                }
+                /* ST has 16 vectors as well, but we don't enable them by now */
+                for (i = 0; i < 16; i++) {
+                        void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
+                        writel(0, reg);
+                }
+
+                writel(32, base + VIC_PL190_DEF_VECT_ADDR);
+        }
+
+        for (i = 0; i < 32; i++) {
+                if (vic_sources & (1 << i)) {
+                        unsigned int irq = irq_start + i;
+
+                        set_irq_chip(irq, &vic_chip);
+                        set_irq_chip_data(irq, base);
+                        set_irq_handler(irq, handle_level_irq);
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                }
+        }
+}
diff --git a/arch/arm/configs/bcmring_defconfig b/arch/arm/configs/bcmring_defconfig
new file mode 100644
index 000000000000..bcc0bac551a5
--- /dev/null
+++ b/arch/arm/configs/bcmring_defconfig
@@ -0,0 +1,725 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc3
+# Fri Jul 17 12:07:28 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+# CONFIG_EPOLL is not set
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+CONFIG_SHMEM=y
+# CONFIG_AIO is not set
+
+#
+# Performance Counters
+#
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+CONFIG_ARCH_BCMRING=y
+# CONFIG_ARCH_FPGA11107 is not set
+CONFIG_ARCH_BCM11107=y
+
+#
+# BCMRING Options
+#
+CONFIG_BCM_ZRELADDR=0x8000
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_ARM_ERRATA_411920 is not set
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0e000000
+CONFIG_ZBOOT_ROM_BSS=0x0ea00000
+CONFIG_ZBOOT_ROM=y
+CONFIG_CMDLINE=""
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_UNIX is not set
+# CONFIG_NET_KEY is not set
+# CONFIG_INET is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_BCM_UMI=y
+CONFIG_MTD_NAND_BCM_UMI_HWCS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=64
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_FSNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+# CONFIG_JFFS2_FS_SECURITY is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+CONFIG_HEADERS_CHECK=y
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_BUILD_DOCSRC is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_ARM_UNWIND is not set
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/cpu9260_defconfig b/arch/arm/configs/cpu9260_defconfig
new file mode 100644
index 000000000000..601e7f3d5e97
--- /dev/null
+++ b/arch/arm/configs/cpu9260_defconfig
@@ -0,0 +1,1338 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc3
+# Tue Jul 14 14:57:55 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+CONFIG_ARCH_AT91SAM9260=y
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91SAM9G20 is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
+
+#
+# AT91SAM9260 / AT91SAM9XE Board Type
+#
+# CONFIG_MACH_AT91SAM9260EK is not set
+# CONFIG_MACH_CAM60 is not set
+# CONFIG_MACH_SAM9_L9260 is not set
+# CONFIG_MACH_AFEB9260 is not set
+# CONFIG_MACH_USB_A9260 is not set
+# CONFIG_MACH_QIL_A9260 is not set
+CONFIG_MACH_CPU9260=y
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_ATMEL_ECC_HW=y
+# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=y
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=32
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9X_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_AT91=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_BD2802 is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AT91SAM9 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/cpu9g20_defconfig b/arch/arm/configs/cpu9g20_defconfig
new file mode 100644
index 000000000000..b5b9cbbc6977
--- /dev/null
+++ b/arch/arm/configs/cpu9g20_defconfig
@@ -0,0 +1,1328 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc3
+# Tue Jul 14 15:03:43 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+CONFIG_ARCH_AT91SAM9G20=y
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9G20 Board Type
+#
+# CONFIG_MACH_AT91SAM9G20EK is not set
+CONFIG_MACH_CPU9G20=y
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_ATMEL=y
+# CONFIG_MTD_NAND_ATMEL_ECC_HW is not set
+CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=y
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=32
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9X_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_AT91=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_BD2802 is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AT91SAM9 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/cpuat91_defconfig b/arch/arm/configs/cpuat91_defconfig
new file mode 100644
index 000000000000..4901827253fb
--- /dev/null
+++ b/arch/arm/configs/cpuat91_defconfig
@@ -0,0 +1,1316 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc3
+# Tue Jul 14 14:45:01 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Atmel AT91 System-on-Chip
+#
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91SAM9G20 is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91RM9200 Board Type
+#
+# CONFIG_MACH_ONEARM is not set
+# CONFIG_ARCH_AT91RM9200DK is not set
+# CONFIG_MACH_AT91RM9200EK is not set
+# CONFIG_MACH_CSB337 is not set
+# CONFIG_MACH_CSB637 is not set
+# CONFIG_MACH_CARMEVA is not set
+# CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_PICOTUX2XX is not set
+# CONFIG_MACH_KAFA is not set
+# CONFIG_MACH_ECBAT91 is not set
+# CONFIG_MACH_YL9200 is not set
+CONFIG_MACH_CPUAT91=y
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=y
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_ARM_AT91_ETHER=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=32
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91RM9200_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_AT91=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_BD2802 is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+CONFIG_RTC_DRV_PCF8563=y
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AT91RM9200 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/da830_omapl137_defconfig b/arch/arm/configs/da830_omapl137_defconfig
new file mode 100644
index 000000000000..7c8e38f5c5ab
--- /dev/null
+++ b/arch/arm/configs/da830_omapl137_defconfig
@@ -0,0 +1,1254 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30-rc2-davinci1
+# Wed May 13 15:33:29 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+CONFIG_ARCH_DAVINCI=y
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+CONFIG_CP_INTC=y
+
+#
+# TI DaVinci Implementations
+#
+
+#
+# DaVinci Core Type
+#
+# CONFIG_ARCH_DAVINCI_DM644x is not set
+# CONFIG_ARCH_DAVINCI_DM646x is not set
+# CONFIG_ARCH_DAVINCI_DM355 is not set
+CONFIG_ARCH_DAVINCI_DA830=y
+
+#
+# DaVinci Board Type
+#
+CONFIG_MACH_DAVINCI_DA830_EVM=y
+CONFIG_DAVINCI_MUX=y
+# CONFIG_DAVINCI_MUX_DEBUG is not set
+# CONFIG_DAVINCI_MUX_WARNINGS is not set
+CONFIG_DAVINCI_RESET_CLOCKS=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+CONFIG_CPU_DCACHE_WRITETHROUGH=y
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_LEDS=y
+# CONFIG_LEDS_CPU is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+CONFIG_LXT_PHY=y
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+CONFIG_LSI_ET1011C_PHY=y
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+CONFIG_TI_DAVINCI_EMAC=y
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+CONFIG_NETCONSOLE=y
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=m
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_EVBUG=m
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=m
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_XTKBD=m
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+# CONFIG_VT_CONSOLE is not set
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_DAVINCI=y
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+CONFIG_GPIO_PCF857X=m
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_DAVINCI_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_SOUND=m
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SOC=m
+CONFIG_SND_DAVINCI_SOC=m
+CONFIG_SND_SOC_I2C_AND_SPI=m
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=m
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_DEBUG_PREEMPT=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_PI_LIST=y
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=m
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/da850_omapl138_defconfig b/arch/arm/configs/da850_omapl138_defconfig
new file mode 100644
index 000000000000..842a70b079bf
--- /dev/null
+++ b/arch/arm/configs/da850_omapl138_defconfig
@@ -0,0 +1,1229 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30-davinci1
+# Mon Jun 29 07:54:15 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+CONFIG_ARCH_DAVINCI=y
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+CONFIG_CP_INTC=y
+
+#
+# TI DaVinci Implementations
+#
+
+#
+# DaVinci Core Type
+#
+# CONFIG_ARCH_DAVINCI_DM644x is not set
+# CONFIG_ARCH_DAVINCI_DM355 is not set
+# CONFIG_ARCH_DAVINCI_DM646x is not set
+# CONFIG_ARCH_DAVINCI_DA830 is not set
+CONFIG_ARCH_DAVINCI_DA850=y
+CONFIG_ARCH_DAVINCI_DA8XX=y
+# CONFIG_ARCH_DAVINCI_DM365 is not set
+
+#
+# DaVinci Board Type
+#
+CONFIG_MACH_DAVINCI_DA850_EVM=y
+CONFIG_DAVINCI_MUX=y
+# CONFIG_DAVINCI_MUX_DEBUG is not set
+# CONFIG_DAVINCI_MUX_WARNINGS is not set
+CONFIG_DAVINCI_RESET_CLOCKS=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_LEDS=y
+# CONFIG_LEDS_CPU is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+CONFIG_LXT_PHY=y
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+CONFIG_LSI_ET1011C_PHY=y
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_TI_DAVINCI_EMAC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+CONFIG_NETCONSOLE=y
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=m
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_EVBUG=m
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=m
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_XTKBD=m
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+# CONFIG_VT_CONSOLE is not set
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_DAVINCI=y
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+CONFIG_GPIO_PCF857X=m
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_DAVINCI_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_SOUND=m
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SOC=m
+CONFIG_SND_DAVINCI_SOC=m
+CONFIG_SND_SOC_I2C_AND_SPI=m
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=m
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_DEBUG_PREEMPT=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_PI_LIST=y
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=m
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index ac18662f38cc..ddffe39d9f87 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc7
-# Tue May 26 07:24:28 2009
+# Linux kernel version: 2.6.31-rc3-davinci1
+# Fri Jul 17 08:26:52 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -9,7 +9,6 @@ CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -18,14 +17,13 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_ZONE_DMA=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -62,8 +60,7 @@ CONFIG_FAIR_GROUP_SCHED=y
 CONFIG_USER_SCHED=y
 # CONFIG_CGROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
@@ -80,7 +77,6 @@ CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
@@ -93,8 +89,13 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+
+#
+# Performance Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
@@ -106,6 +107,11 @@ CONFIG_HAVE_OPROFILE=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
 # CONFIG_SLOW_WORK is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
@@ -118,7 +124,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -145,13 +151,14 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
 # CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -160,26 +167,27 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_LOKI is not set
 # CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_MSM is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
 CONFIG_ARCH_DAVINCI=y
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_W90X900 is not set
 CONFIG_AINTC=y
+CONFIG_ARCH_DAVINCI_DMx=y
 
 #
 # TI DaVinci Implementations
@@ -191,6 +199,9 @@ CONFIG_AINTC=y
 CONFIG_ARCH_DAVINCI_DM644x=y
 CONFIG_ARCH_DAVINCI_DM355=y
 CONFIG_ARCH_DAVINCI_DM646x=y
+# CONFIG_ARCH_DAVINCI_DA830 is not set
+# CONFIG_ARCH_DAVINCI_DA850 is not set
+CONFIG_ARCH_DAVINCI_DM365=y
 
 #
 # DaVinci Board Type
@@ -200,6 +211,7 @@ CONFIG_MACH_SFFSDR=y
 CONFIG_MACH_DAVINCI_DM355_EVM=y
 CONFIG_MACH_DM355_LEOPARD=y
 CONFIG_MACH_DAVINCI_DM6467_EVM=y
+CONFIG_MACH_DAVINCI_DM365_EVM=y
 CONFIG_DAVINCI_MUX=y
 CONFIG_DAVINCI_MUX_DEBUG=y
 CONFIG_DAVINCI_MUX_WARNINGS=y
@@ -227,7 +239,6 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 # CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-# CONFIG_OUTER_CACHE is not set
 CONFIG_COMMON_CLKDEV=y
 
 #
@@ -252,7 +263,6 @@ CONFIG_PREEMPT=y
 CONFIG_HZ=100
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 # CONFIG_HIGHMEM is not set
@@ -268,12 +278,13 @@ CONFIG_SPLIT_PTLOCK_CPUS=4096
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
 CONFIG_HAVE_MLOCK=y
 CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_LEDS=y
 # CONFIG_LEDS_CPU is not set
 CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
 
 #
 # Boot options
@@ -415,6 +426,7 @@ CONFIG_NETFILTER_ADVANCED=y
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 
@@ -553,6 +565,7 @@ CONFIG_BLK_DEV_RAM_SIZE=32768
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_ICS932S401 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -564,6 +577,7 @@ CONFIG_MISC_DEVICES=y
 #
 CONFIG_EEPROM_AT24=y
 # CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
 # CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 CONFIG_IDE=m
@@ -609,10 +623,6 @@ CONFIG_BLK_DEV_SD=m
 # CONFIG_BLK_DEV_SR is not set
 # CONFIG_CHR_DEV_SG is not set
 # CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
 # CONFIG_SCSI_MULTI_LUN is not set
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
@@ -637,7 +647,6 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -684,6 +693,7 @@ CONFIG_DM9000_DEBUGLEVEL=4
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 
@@ -748,18 +758,21 @@ CONFIG_INPUT_EVBUG=m
 #
 CONFIG_INPUT_KEYBOARD=y
 CONFIG_KEYBOARD_ATKBD=m
-# CONFIG_KEYBOARD_SUNKBD is not set
 # CONFIG_KEYBOARD_LKKBD is not set
-CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+CONFIG_KEYBOARD_XTKBD=m
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_AD7879_I2C is not set
 # CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
@@ -773,6 +786,7 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
 # CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -832,6 +846,7 @@ CONFIG_I2C_HELPER_AUTO=y
 # I2C system bus drivers (mostly embedded / system-on-chip)
 #
 CONFIG_I2C_DAVINCI=y
+# CONFIG_I2C_DESIGNWARE is not set
 # CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_SIMTEC is not set
@@ -854,7 +869,6 @@ CONFIG_I2C_DAVINCI=y
 #
 # CONFIG_DS1682 is not set
 # CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -935,6 +949,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_ADS7828 is not set
 # CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83781D is not set
 # CONFIG_SENSORS_W83791D is not set
@@ -986,52 +1001,8 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_PCF50633 is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=y
-CONFIG_VIDEO_ALLOW_V4L1=y
-CONFIG_VIDEO_V4L1_COMPAT=y
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=y
-
-#
-# Multimedia drivers
-#
-# CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_MEDIA_TUNER_SIMPLE=y
-CONFIG_MEDIA_TUNER_TDA8290=y
-CONFIG_MEDIA_TUNER_TDA9887=y
-CONFIG_MEDIA_TUNER_TEA5761=y
-CONFIG_MEDIA_TUNER_TEA5767=y
-CONFIG_MEDIA_TUNER_MT20XX=y
-CONFIG_MEDIA_TUNER_XC2028=y
-CONFIG_MEDIA_TUNER_XC5000=y
-CONFIG_MEDIA_TUNER_MC44S803=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_V4L1=y
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_CPIA is not set
-# CONFIG_VIDEO_CPIA2 is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-# CONFIG_SOC_CAMERA is not set
-# CONFIG_V4L_USB_DRIVERS is not set
-# CONFIG_RADIO_ADAPTERS is not set
-CONFIG_DAB=y
-# CONFIG_USB_DABUSB is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -1102,6 +1073,11 @@ CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
 CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_MTPAV is not set
@@ -1112,9 +1088,16 @@ CONFIG_SND_USB=y
 # CONFIG_SND_USB_AUDIO is not set
 # CONFIG_SND_USB_CAIAQ is not set
 CONFIG_SND_SOC=m
-# CONFIG_SND_DAVINCI_SOC is not set
+CONFIG_SND_DAVINCI_SOC=m
+CONFIG_SND_DAVINCI_SOC_I2S=m
+CONFIG_SND_DAVINCI_SOC_MCASP=m
+CONFIG_SND_DAVINCI_SOC_EVM=m
+CONFIG_SND_DM6467_SOC_EVM=m
+# CONFIG_SND_DAVINCI_SOC_SFFSDR is not set
 CONFIG_SND_SOC_I2C_AND_SPI=m
 # CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_SPDIF=m
+CONFIG_SND_SOC_TLV320AIC3X=m
 # CONFIG_SOUND_PRIME is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=m
@@ -1143,7 +1126,7 @@ CONFIG_HID_BELKIN=m
 CONFIG_HID_CHERRY=m
 CONFIG_HID_CHICONY=m
 CONFIG_HID_CYPRESS=m
-# CONFIG_DRAGONRISE_FF is not set
+# CONFIG_HID_DRAGONRISE is not set
 CONFIG_HID_EZKEY=m
 # CONFIG_HID_KYE is not set
 CONFIG_HID_GYRATION=m
@@ -1160,10 +1143,11 @@ CONFIG_HID_PETALYNX=m
 CONFIG_HID_SAMSUNG=m
 CONFIG_HID_SONY=m
 CONFIG_HID_SUNPLUS=m
-# CONFIG_GREENASIA_FF is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
 # CONFIG_HID_TOPSEED is not set
-# CONFIG_THRUSTMASTER_FF is not set
-# CONFIG_ZEROPLUS_FF is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
@@ -1266,6 +1250,7 @@ CONFIG_USB_STORAGE=m
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
@@ -1285,17 +1270,20 @@ CONFIG_USB_GADGET_SELECTED=y
 # CONFIG_USB_GADGET_OMAP is not set
 # CONFIG_USB_GADGET_PXA25X is not set
 # CONFIG_USB_GADGET_PXA27X is not set
-# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
 # CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
 # CONFIG_USB_GADGET_M66592 is not set
 # CONFIG_USB_GADGET_AMD5536UDC is not set
 # CONFIG_USB_GADGET_FSL_QE is not set
 # CONFIG_USB_GADGET_CI13XXX is not set
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
 CONFIG_USB_GADGET_DUALSPEED=y
 CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
 CONFIG_USB_ETH=m
 CONFIG_USB_ETH_RNDIS=y
 CONFIG_USB_GADGETFS=m
@@ -1311,7 +1299,7 @@ CONFIG_USB_CDC_COMPOSITE=m
 #
 CONFIG_USB_OTG_UTILS=y
 # CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_NOP_USB_XCEIV=m
 CONFIG_MMC=m
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
@@ -1328,7 +1316,6 @@ CONFIG_MMC_BLOCK=m
 # MMC/SD/SDIO Host Controller Drivers
 #
 # CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_DAVINCI is not set
 # CONFIG_MEMSTICK is not set
 # CONFIG_ACCESSIBILITY is not set
 CONFIG_NEW_LEDS=y
@@ -1340,7 +1327,7 @@ CONFIG_LEDS_CLASS=m
 # CONFIG_LEDS_PCA9532 is not set
 CONFIG_LEDS_GPIO=m
 CONFIG_LEDS_GPIO_PLATFORM=y
-# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP3944 is not set
 # CONFIG_LEDS_PCA955X is not set
 # CONFIG_LEDS_BD2802 is not set
 
@@ -1386,6 +1373,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
 # CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 
 #
 # SPI RTC drivers
@@ -1433,14 +1421,16 @@ CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 CONFIG_XFS_FS=m
 # CONFIG_XFS_QUOTA is not set
 # CONFIG_XFS_POSIX_ACL is not set
 # CONFIG_XFS_RT is not set
 # CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -1623,6 +1613,7 @@ CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_SLUB_DEBUG_ON is not set
 # CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
 CONFIG_DEBUG_PREEMPT=y
 CONFIG_DEBUG_RT_MUTEXES=y
 CONFIG_DEBUG_PI_LIST=y
@@ -1654,18 +1645,16 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_PAGE_POISONING is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_TRACING_SUPPORT=y
-
-#
-# Tracers
-#
+CONFIG_FTRACE=y
 # CONFIG_FUNCTION_TRACER is not set
 # CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_PREEMPT_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_EVENT_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
 # CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
 # CONFIG_STACK_TRACER is not set
 # CONFIG_KMEMTRACE is not set
 # CONFIG_WORKQUEUE_TRACER is not set
diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig
index f3074e49f2fa..df9bfbea8612 100644
--- a/arch/arm/configs/jornada720_defconfig
+++ b/arch/arm/configs/jornada720_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc6
-# Tue Sep 16 18:56:58 2008
+# Linux kernel version: 2.6.31-rc6
+# Fri Aug 21 15:41:39 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -9,7 +9,6 @@ CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -18,16 +17,14 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_ZONE_DMA=y
 CONFIG_ARCH_MTD_XIP=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -44,10 +41,19 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
@@ -56,9 +62,11 @@ CONFIG_NAMESPACES=y
 # CONFIG_IPC_NS is not set
 # CONFIG_USER_NS is not set
 # CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 # CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
@@ -69,17 +77,22 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Performance Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
@@ -87,30 +100,25 @@ CONFIG_SLUB=y
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
-# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-# CONFIG_HAVE_IOREMAP_PROT is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
-# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-# CONFIG_HAVE_DMA_ATTRS is not set
-# CONFIG_USE_GENERIC_SMP_HELPERS is not set
 CONFIG_HAVE_CLK=y
-CONFIG_PROC_PAGE_MONITOR=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
 # CONFIG_MODULE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -126,7 +134,7 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
 
 #
 # System Type
@@ -136,14 +144,15 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -152,23 +161,25 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_LOKI is not set
 # CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
 # CONFIG_ARCH_RPC is not set
 CONFIG_ARCH_SA1100=y
 # CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM7X00A is not set
-CONFIG_DMABOUNCE=y
 
 #
 # SA11x0 Implementations
@@ -189,14 +200,6 @@ CONFIG_SA1100_JORNADA720_SSP=y
 CONFIG_SA1100_SSP=y
 
 #
-# Boot options
-#
-
-#
-# Power management
-#
-
-#
 # Processor Type
 #
 CONFIG_CPU_32=y
@@ -215,8 +218,8 @@ CONFIG_CPU_CP15_MMU=y
 #
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
 CONFIG_SA1111=y
+CONFIG_DMABOUNCE=y
 CONFIG_FORCE_MAX_ZONEORDER=9
 
 #
@@ -246,30 +249,36 @@ CONFIG_TICK_ONESHOT=y
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
 # CONFIG_PREEMPT is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
 CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_NODES_SHIFT=2
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 # CONFIG_FLATMEM_MANUAL is not set
-CONFIG_DISCONTIGMEM_MANUAL=y
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_DISCONTIGMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_NEED_MULTIPLE_NODES=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_EXTREME=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
 
 #
 # Boot options
@@ -281,9 +290,10 @@ CONFIG_CMDLINE=""
 # CONFIG_KEXEC is not set
 
 #
-# CPU Frequency scaling
+# CPU Power Management
 #
 # CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
 
 #
 # Floating point emulation
@@ -294,12 +304,14 @@ CONFIG_CMDLINE=""
 #
 CONFIG_FPE_NWFPE=y
 # CONFIG_FPE_NWFPE_XP is not set
-CONFIG_FPE_FASTFPE=y
+# CONFIG_FPE_FASTFPE is not set
 
 #
 # Userspace binary formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
 CONFIG_BINFMT_AOUT=y
 # CONFIG_BINFMT_MISC is not set
 # CONFIG_ARTHUR is not set
@@ -353,7 +365,6 @@ CONFIG_INET_TCP_DIAG=y
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-# CONFIG_IP_VS is not set
 # CONFIG_IPV6 is not set
 # CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
@@ -367,10 +378,12 @@ CONFIG_NETFILTER_ADVANCED=y
 # CONFIG_NETFILTER_NETLINK_LOG is not set
 # CONFIG_NF_CONNTRACK is not set
 # CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
 
 #
 # IP: Netfilter Configuration
 #
+# CONFIG_NF_DEFRAG_IPV4 is not set
 # CONFIG_IP_NF_QUEUE is not set
 # CONFIG_IP_NF_IPTABLES is not set
 # CONFIG_IP_NF_ARPTABLES is not set
@@ -379,6 +392,7 @@ CONFIG_NETFILTER_ADVANCED=y
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -388,7 +402,10 @@ CONFIG_NETFILTER_ADVANCED=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
@@ -431,14 +448,17 @@ CONFIG_IRCOMM=m
 CONFIG_SA1100_FIR=m
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
 
 #
-# Wireless
+# CFG80211 needs to be enabled for MAC80211
 #
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+CONFIG_MAC80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -464,29 +484,34 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_PNP is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
-CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_NBD=y
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
 CONFIG_MISC_DEVICES=y
-# CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
-CONFIG_BLK_DEV_IDE=y
 
 #
 # Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
 # CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
 CONFIG_BLK_DEV_IDECS=y
 # CONFIG_BLK_DEV_IDECD is not set
 # CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
 # CONFIG_IDE_TASK_IOCTL is not set
 CONFIG_IDE_PROC_FS=y
 
@@ -513,8 +538,34 @@ CONFIG_DUMMY=y
 # CONFIG_TUN is not set
 # CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
-# CONFIG_NET_ETHERNET is not set
-CONFIG_MII=m
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_DNET is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_KS8842 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
@@ -523,17 +574,27 @@ CONFIG_MII=m
 # Wireless LAN
 #
 # CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_HERMES is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
 CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_3C589=m
-CONFIG_PCMCIA_3C574=m
-CONFIG_PCMCIA_FMVJ18X=m
-CONFIG_PCMCIA_PCNET=m
-CONFIG_PCMCIA_NMCLAN=m
-CONFIG_PCMCIA_SMC91C92=m
-CONFIG_PCMCIA_XIRC2PS=m
-CONFIG_PCMCIA_AXNET=m
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+# CONFIG_PCMCIA_PCNET is not set
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_PCMCIA_AXNET is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -565,20 +626,23 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
 #
 CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
 # CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+CONFIG_KEYBOARD_HP7XX=y
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_KEYBOARD_HP7XX=y
-# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_AD7879 is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
 # CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
@@ -587,8 +651,8 @@ CONFIG_TOUCHSCREEN_HP7XX=y
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_UCB1400 is not set
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -624,11 +688,12 @@ CONFIG_SERIAL_SA1100_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=32
 # CONFIG_IPMI_HANDLER is not set
 CONFIG_HW_RANDOM=m
-# CONFIG_NVRAM is not set
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 
@@ -650,6 +715,10 @@ CONFIG_GPIOLIB=y
 # CONFIG_GPIO_SYSFS is not set
 
 #
+# Memory mapped GPIO expanders:
+#
+
+#
 # I2C GPIO expanders:
 #
 
@@ -663,12 +732,14 @@ CONFIG_GPIOLIB=y
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB is not set
 
 #
@@ -676,6 +747,7 @@ CONFIG_SSB_POSSIBLE=y
 #
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_MFD_TMIO is not set
@@ -687,22 +759,7 @@ CONFIG_SSB_POSSIBLE=y
 # Multimedia Capabilities Port drivers
 #
 # CONFIG_MCP_SA11X0 is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -712,6 +769,7 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
@@ -733,7 +791,17 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_SA1100 is not set
 CONFIG_FB_S1D13XXX=y
 # CONFIG_FB_VIRTUAL is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_LCD_HP700=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_HP700=y
 
 #
 # Display device support
@@ -757,6 +825,8 @@ CONFIG_FONT_8x16=y
 # CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_NEW_LEDS is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -781,12 +851,15 @@ CONFIG_RTC_INTF_DEV=y
 # Platform RTC drivers
 #
 # CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
 # CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
@@ -794,15 +867,10 @@ CONFIG_RTC_INTF_DEV=y
 #
 CONFIG_RTC_DRV_SA1100=y
 # CONFIG_DMADEVICES is not set
-
-#
-# Voltage and Current regulators
-#
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_REGULATOR is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
@@ -811,12 +879,16 @@ CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -826,6 +898,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -846,14 +923,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -862,6 +937,7 @@ CONFIG_SYSFS=y
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@@ -870,6 +946,7 @@ CONFIG_SYSFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 # CONFIG_NETWORK_FILESYSTEMS is not set
 
 #
@@ -935,12 +1012,16 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_SLUB_DEBUG_ON is not set
 # CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
@@ -958,19 +1039,20 @@ CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 # CONFIG_SYSCTL_SYSCALL_CHECK is not set
-CONFIG_HAVE_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
 # CONFIG_FTRACE is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
@@ -985,13 +1067,16 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
 
 #
 # Crypto core or helper
 #
+# CONFIG_CRYPTO_FIPS is not set
 # CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
 # CONFIG_CRYPTO_CRYPTD is not set
@@ -1062,15 +1147,21 @@ CONFIG_CRYPTO=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
@@ -1078,7 +1169,7 @@ CONFIG_CRC_CCITT=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/n8x0_defconfig b/arch/arm/configs/n8x0_defconfig
new file mode 100644
index 000000000000..8da75dede52e
--- /dev/null
+++ b/arch/arm/configs/n8x0_defconfig
@@ -0,0 +1,1104 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc5
+# Thu Aug  6 22:17:23 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+# CONFIG_CLASSIC_RCU is not set
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+CONFIG_ARCH_OMAP2=y
+# CONFIG_ARCH_OMAP3 is not set
+# CONFIG_ARCH_OMAP4 is not set
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+# CONFIG_OMAP_MUX is not set
+# CONFIG_OMAP_MCBSP is not set
+CONFIG_OMAP_MBOX_FWK=y
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+# CONFIG_MACH_OMAP_GENERIC is not set
+
+#
+# OMAP Core Type
+#
+CONFIG_ARCH_OMAP24XX=y
+CONFIG_ARCH_OMAP2420=y
+# CONFIG_ARCH_OMAP2430 is not set
+
+#
+# OMAP Board Type
+#
+CONFIG_MACH_OMAP2_TUSB6010=y
+# CONFIG_MACH_OMAP_H4 is not set
+# CONFIG_MACH_OMAP_APOLLON is not set
+# CONFIG_MACH_OMAP_2430SDP is not set
+CONFIG_MACH_NOKIA_N8X0=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_ARM_ERRATA_411920 is not set
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_LEDS=y
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x10C08000
+CONFIG_ZBOOT_ROM_BSS=0x10200000
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_CMDLINE="root=1f03 rootfstype=jffs2 console=ttyS0,115200n8"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+CONFIG_MAC80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+CONFIG_HAVE_MTD_OTP=y
+# CONFIG_MTD_BLKDEVS is not set
+# CONFIG_MTD_BLOCK is not set
+# CONFIG_MTD_BLOCK_RO is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+CONFIG_MTD_ONENAND=y
+# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
+# CONFIG_MTD_ONENAND_GENERIC is not set
+CONFIG_MTD_ONENAND_OMAP2=y
+CONFIG_MTD_ONENAND_OTP=y
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_OMAP24XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_TUSB6010=y
+# CONFIG_USB_MUSB_HOST is not set
+CONFIG_USB_MUSB_PERIPHERAL=y
+# CONFIG_USB_MUSB_OTG is not set
+CONFIG_USB_GADGET_MUSB_HDRC=y
+# CONFIG_MUSB_PIO_ONLY is not set
+# CONFIG_USB_INVENTRA_DMA is not set
+# CONFIG_USB_TI_CPPI_DMA is not set
+CONFIG_USB_TUSB_OMAP_DMA=y
+CONFIG_USB_MUSB_DEBUG=y
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DEBUG=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=y
+# CONFIG_USB_ETH_RNDIS is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+CONFIG_NOP_USB_XCEIV=y
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
new file mode 100644
index 000000000000..9bb45b932f04
--- /dev/null
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -0,0 +1,1316 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30
+# Tue Jun 23 22:57:16 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+CONFIG_ARCH_NOMADIK=y
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Nomadik boards
+#
+CONFIG_MACH_NOMADIK_8815NHK=y
+CONFIG_NOMADIK_8815=y
+CONFIG_I2C_BITBANG_8815NHK=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_L2X0=y
+CONFIG_ARM_VIC=y
+CONFIG_ARM_VIC_NR=2
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+# CONFIG_IP_PIMSM_V1 is not set
+# CONFIG_IP_PIMSM_V2 is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+# CONFIG_BT_HCIUART_LL is not set
+CONFIG_BT_HCIVHCI=m
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+CONFIG_MAC80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_TESTS=m
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_NOMADIK=y
+CONFIG_MTD_ONENAND=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+CONFIG_MTD_ONENAND_GENERIC=y
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+CONFIG_NETCONSOLE=m
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_DEBUG_GPIO=y
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_PL061 is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_WACOM is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_PL030 is not set
+# CONFIG_RTC_DRV_PL031 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+CONFIG_CIFS_WEAK_PW_HASH=y
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=y
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/omap3_beagle_defconfig b/arch/arm/configs/omap3_beagle_defconfig
index 4c6fb7e959df..51c0fa8897cd 100644
--- a/arch/arm/configs/omap3_beagle_defconfig
+++ b/arch/arm/configs/omap3_beagle_defconfig
@@ -128,6 +128,7 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
 CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
 
 #
 # System Type
@@ -236,6 +237,7 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_HAS_TLS_REG=y
 # CONFIG_OUTER_CACHE is not set
+CONFIG_COMMON_CLKDEV=y
 
 #
 # Bus support
@@ -317,7 +319,12 @@ CONFIG_BINFMT_MISC=y
 #
 # Power management options
 #
-# CONFIG_PM is not set
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_NET=y
 
@@ -713,6 +720,7 @@ CONFIG_GPIOLIB=y
 # CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
 
 #
 # PCI GPIO expanders:
@@ -741,6 +749,7 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
+CONFIG_TWL4030_CORE=y
 # CONFIG_UCB1400_CORE is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_MFD_T7L66XB is not set
@@ -787,7 +796,7 @@ CONFIG_DUMMY_CONSOLE=y
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB_ARCH_HAS_EHCI=y
 CONFIG_USB=y
 # CONFIG_USB_DEBUG is not set
 # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
@@ -798,7 +807,8 @@ CONFIG_USB=y
 CONFIG_USB_DEVICEFS=y
 CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_OTG is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
 CONFIG_USB_MON=y
@@ -806,6 +816,8 @@ CONFIG_USB_MON=y
 #
 # USB Host Controller Drivers
 #
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
 # CONFIG_USB_C67X00_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
@@ -818,10 +830,10 @@ CONFIG_USB_MUSB_SOC=y
 #
 # OMAP 343x high speed USB support
 #
-CONFIG_USB_MUSB_HOST=y
+# CONFIG_USB_MUSB_HOST is not set
 # CONFIG_USB_MUSB_PERIPHERAL is not set
-# CONFIG_USB_MUSB_OTG is not set
-# CONFIG_USB_GADGET_MUSB_HDRC is not set
+CONFIG_USB_MUSB_OTG=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
 CONFIG_USB_MUSB_HDRC_HCD=y
 # CONFIG_MUSB_PIO_ONLY is not set
 CONFIG_USB_INVENTRA_DMA=y
@@ -887,8 +899,8 @@ CONFIG_USB_GADGET_SELECTED=y
 # CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_PXA25X is not set
-CONFIG_USB_GADGET_M66592=y
-CONFIG_USB_M66592=y
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_M66592 is not set
 # CONFIG_USB_GADGET_PXA27X is not set
 # CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
@@ -906,6 +918,15 @@ CONFIG_USB_ETH_RNDIS=y
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_G_PRINTER is not set
 # CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TWL4030_USB=y
+# CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
@@ -923,6 +944,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 #
 # CONFIG_MMC_SDHCI is not set
 # CONFIG_MMC_OMAP is not set
+CONFIG_MMC_OMAP_HS=y
 # CONFIG_MEMSTICK is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_NEW_LEDS is not set
@@ -981,10 +1003,11 @@ CONFIG_RTC_INTF_DEV=y
 #
 # Voltage and Current regulators
 #
-# CONFIG_REGULATOR is not set
+CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_FIXED_VOLTAGE is not set
 # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
 # CONFIG_REGULATOR_BQ24022 is not set
+CONFIG_REGULATOR_TWL4030=y
 # CONFIG_UIO is not set
 
 #
diff --git a/arch/arm/configs/omap_3430sdp_defconfig b/arch/arm/configs/omap_3430sdp_defconfig
index 8fb918d9ba65..9a510eab75a6 100644
--- a/arch/arm/configs/omap_3430sdp_defconfig
+++ b/arch/arm/configs/omap_3430sdp_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc8
-# Fri Mar 13 14:17:01 2009
+# Linux kernel version: 2.6.30-omap1
+# Tue Jun 23 10:36:45 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -197,9 +197,9 @@ CONFIG_OMAP_MCBSP=y
 CONFIG_OMAP_32K_TIMER=y
 CONFIG_OMAP_32K_TIMER_HZ=128
 CONFIG_OMAP_DM_TIMER=y
-# CONFIG_OMAP_LL_DEBUG_UART1 is not set
+CONFIG_OMAP_LL_DEBUG_UART1=y
 # CONFIG_OMAP_LL_DEBUG_UART2 is not set
-CONFIG_OMAP_LL_DEBUG_UART3=y
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
 CONFIG_OMAP_SERIAL_WAKE=y
 CONFIG_ARCH_OMAP34XX=y
 CONFIG_ARCH_OMAP3430=y
@@ -207,10 +207,10 @@ CONFIG_ARCH_OMAP3430=y
 #
 # OMAP Board Type
 #
-CONFIG_MACH_OMAP3_BEAGLE=y
-CONFIG_MACH_OMAP_LDP=y
-CONFIG_MACH_OVERO=y
-CONFIG_MACH_OMAP3_PANDORA=y
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OVERO is not set
+# CONFIG_MACH_OMAP3_PANDORA is not set
 CONFIG_MACH_OMAP_3430SDP=y
 
 #
@@ -950,7 +950,7 @@ CONFIG_SPI_OMAP24XX=y
 # CONFIG_SPI_TLE62X0 is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
-CONFIG_DEBUG_GPIO=y
+# CONFIG_DEBUG_GPIO is not set
 CONFIG_GPIO_SYSFS=y
 
 #
@@ -1370,7 +1370,7 @@ CONFIG_SND_OMAP_SOC=y
 CONFIG_SND_OMAP_SOC_MCBSP=y
 # CONFIG_SND_OMAP_SOC_OVERO is not set
 CONFIG_SND_OMAP_SOC_SDP3430=y
-CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y
+# CONFIG_SND_OMAP_SOC_OMAP3_PANDORA is not set
 CONFIG_SND_SOC_I2C_AND_SPI=y
 # CONFIG_SND_SOC_ALL_CODECS is not set
 CONFIG_SND_SOC_TWL4030=y
diff --git a/arch/arm/configs/omap_zoom2_defconfig b/arch/arm/configs/omap_zoom2_defconfig
index 213fe9c5eaae..f1739fae7ed4 100644
--- a/arch/arm/configs/omap_zoom2_defconfig
+++ b/arch/arm/configs/omap_zoom2_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc5
-# Fri Oct 10 11:49:41 2008
+# Linux kernel version: 2.6.30-omap1
+# Fri Jun 12 17:25:46 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -22,8 +22,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_SUPPORTS_AOUT=y
-CONFIG_ZONE_DMA=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -39,44 +37,61 @@ CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 CONFIG_GROUP_SCHED=y
 CONFIG_FAIR_GROUP_SCHED=y
 # CONFIG_RT_GROUP_SCHED is not set
 CONFIG_USER_SCHED=y
 # CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 CONFIG_KALLSYMS_EXTRA_PASS=y
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
@@ -84,19 +99,13 @@ CONFIG_SLAB=y
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
-# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-# CONFIG_HAVE_IOREMAP_PROT is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
-# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-# CONFIG_HAVE_DMA_ATTRS is not set
-# CONFIG_USE_GENERIC_SMP_HELPERS is not set
 CONFIG_HAVE_CLK=y
-CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_SLOW_WORK is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@@ -104,11 +113,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -124,7 +130,7 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
 
 #
 # System Type
@@ -134,10 +140,10 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
@@ -158,14 +164,17 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_ORION5X is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MMP is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_DAVINCI is not set
 CONFIG_ARCH_OMAP=y
-# CONFIG_ARCH_MSM7X00A is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
 
 #
 # TI OMAP Implementations
@@ -174,6 +183,7 @@ CONFIG_ARCH_OMAP_OTG=y
 # CONFIG_ARCH_OMAP1 is not set
 # CONFIG_ARCH_OMAP2 is not set
 CONFIG_ARCH_OMAP3=y
+# CONFIG_ARCH_OMAP4 is not set
 
 #
 # OMAP Feature Selections
@@ -185,6 +195,7 @@ CONFIG_OMAP_MUX=y
 CONFIG_OMAP_MUX_DEBUG=y
 CONFIG_OMAP_MUX_WARNINGS=y
 CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MBOX_FWK is not set
 # CONFIG_OMAP_MPU_TIMER is not set
 CONFIG_OMAP_32K_TIMER=y
 CONFIG_OMAP_32K_TIMER_HZ=128
@@ -192,25 +203,20 @@ CONFIG_OMAP_DM_TIMER=y
 # CONFIG_OMAP_LL_DEBUG_UART1 is not set
 # CONFIG_OMAP_LL_DEBUG_UART2 is not set
 CONFIG_OMAP_LL_DEBUG_UART3=y
-CONFIG_OMAP_SERIAL_WAKE=y
 CONFIG_ARCH_OMAP34XX=y
 CONFIG_ARCH_OMAP3430=y
 
 #
 # OMAP Board Type
 #
-# CONFIG_MACH_OMAP3_BEAGLE is not set
+# CONFIG_MACH_NOKIA_RX51 is not set
 # CONFIG_MACH_OMAP_LDP is not set
-CONFIG_MACH_OMAP_ZOOM2=y
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_OMAP3EVM is not set
+# CONFIG_MACH_OMAP3_BEAGLE is not set
 # CONFIG_MACH_OVERO is not set
-
-#
-# Boot options
-#
-
-#
-# Power management
-#
+# CONFIG_MACH_OMAP3_PANDORA is not set
+CONFIG_MACH_OMAP_ZOOM2=y
 
 #
 # Processor Type
@@ -239,6 +245,10 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_HAS_TLS_REG=y
 # CONFIG_OUTER_CACHE is not set
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_COMMON_CLKDEV=y
 
 #
 # Bus support
@@ -254,26 +264,32 @@ CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
 # CONFIG_PREEMPT is not set
 CONFIG_HZ=128
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -287,9 +303,10 @@ CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.16
 # CONFIG_KEXEC is not set
 
 #
-# CPU Frequency scaling
+# CPU Power Management
 #
 # CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
 
 #
 # Floating point emulation
@@ -309,13 +326,23 @@ CONFIG_VFPv3=y
 # Userspace binary formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
 # CONFIG_BINFMT_AOUT is not set
 CONFIG_BINFMT_MISC=y
 
 #
 # Power management options
 #
-# CONFIG_PM is not set
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_VERBOSE=y
+CONFIG_CAN_PM_TRACE=y
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_NET=y
 
@@ -378,7 +405,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
@@ -389,8 +418,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
 # CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
 
@@ -416,14 +445,28 @@ CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=16384
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
 CONFIG_MISC_DEVICES=y
-# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_OMAP_STI is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
@@ -461,14 +504,20 @@ CONFIG_SCSI_WAIT_SCAN=m
 #
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
 # CONFIG_SCSI_SRP_ATTRS is not set
 CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -501,8 +550,10 @@ CONFIG_MII=y
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
 # CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
 # CONFIG_SMC911X is not set
 CONFIG_SMSC911X=y
+# CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -519,7 +570,10 @@ CONFIG_NETDEV_10000=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
 
 #
 # USB Network Adapters
@@ -561,17 +615,25 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
 # CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC210X is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -607,13 +669,15 @@ CONFIG_SERIAL_8250_RSA=y
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
 CONFIG_HW_RANDOM=y
-# CONFIG_NVRAM is not set
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
@@ -639,6 +703,7 @@ CONFIG_I2C_OMAP=y
 #
 # CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
 
 #
 # Other I2C/SMBus bus drivers
@@ -650,14 +715,11 @@ CONFIG_I2C_OMAP=y
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_ISP1301_OMAP is not set
-# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_MADC is not set
+# CONFIG_TWL4030_POWEROFF is not set
 # CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
@@ -672,12 +734,12 @@ CONFIG_SPI_MASTER=y
 # SPI Master Controller Drivers
 #
 # CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
 CONFIG_SPI_OMAP24XX=y
 
 #
 # SPI Protocol Masters
 #
-# CONFIG_EEPROM_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
@@ -686,11 +748,16 @@ CONFIG_GPIOLIB=y
 # CONFIG_GPIO_SYSFS is not set
 
 #
+# Memory mapped GPIO expanders:
+#
+
+#
 # I2C GPIO expanders:
 #
 # CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
 
 #
 # PCI GPIO expanders:
@@ -702,26 +769,34 @@ CONFIG_GPIOLIB=y
 # CONFIG_GPIO_MAX7301 is not set
 # CONFIG_GPIO_MCP23S08 is not set
 CONFIG_W1=y
+CONFIG_W1_CON=y
 
 #
 # 1-wire Bus Masters
 #
+# CONFIG_W1_MASTER_DS2490 is not set
 # CONFIG_W1_MASTER_DS2482 is not set
 # CONFIG_W1_MASTER_DS1WM is not set
 # CONFIG_W1_MASTER_GPIO is not set
+# CONFIG_HDQ_MASTER_OMAP is not set
 
 #
 # 1-wire Slaves
 #
 # CONFIG_W1_SLAVE_THERM is not set
 # CONFIG_W1_SLAVE_SMEM is not set
+# CONFIG_W1_SLAVE_DS2431 is not set
 # CONFIG_W1_SLAVE_DS2433 is not set
 # CONFIG_W1_SLAVE_DS2760 is not set
+# CONFIG_W1_SLAVE_BQ27000 is not set
 CONFIG_POWER_SUPPLY=y
 # CONFIG_POWER_SUPPLY_DEBUG is not set
 # CONFIG_PDA_POWER is not set
 # CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
 # CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
 
@@ -729,11 +804,17 @@ CONFIG_WATCHDOG_NOWAYOUT=y
 # Watchdog Device Drivers
 #
 # CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_OMAP_WATCHDOG is not set
 
 #
-# Sonics Silicon Backplane
+# USB-based Watchdog Cards
 #
+# CONFIG_USBPCWATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
 # CONFIG_SSB is not set
 
 #
@@ -741,12 +822,19 @@ CONFIG_SSB_POSSIBLE=y
 #
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_CORE=y
 # CONFIG_MFD_TMIO is not set
 # CONFIG_MFD_T7L66XB is not set
 # CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
 
 #
 # Multimedia devices
@@ -756,12 +844,14 @@ CONFIG_SSB_POSSIBLE=y
 # Multimedia core support
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
 # CONFIG_VIDEO_MEDIA is not set
 
 #
 # Multimedia drivers
 #
 CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
 
 #
 # Graphics support
@@ -782,10 +872,12 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
 CONFIG_SND=y
 # CONFIG_SND_SEQUENCER is not set
 # CONFIG_SND_MIXER_OSS is not set
 # CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
 # CONFIG_SND_DYNAMIC_MINORS is not set
 CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
@@ -798,19 +890,197 @@ CONFIG_SND_DRIVERS=y
 # CONFIG_SND_MPU401 is not set
 CONFIG_SND_ARM=y
 CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
 # CONFIG_SND_SOC is not set
 # CONFIG_SOUND_PRIME is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
-# CONFIG_USB_SUPPORT is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_DRAGONRISE_FF is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_GREENASIA_FF is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+CONFIG_USB_MUSB_OTG=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+CONFIG_USB_MUSB_DEBUG=y
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DEBUG=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=y
+# CONFIG_USB_ZERO_HNPTEST is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TWL4030_USB=y
+# CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card Drivers
+# MMC/SD/SDIO Card Drivers
 #
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_BOUNCE=y
@@ -818,11 +1088,13 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 # CONFIG_MMC_TEST is not set
 
 #
-# MMC/SD Host Controller Drivers
+# MMC/SD/SDIO Host Controller Drivers
 #
 # CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_OMAP is not set
+CONFIG_MMC_OMAP_HS=y
 # CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_NEW_LEDS is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -852,43 +1124,55 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_TWL4030 is not set
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
 
 #
 # SPI RTC drivers
 #
 # CONFIG_RTC_DRV_M41T94 is not set
 # CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
 # CONFIG_RTC_DRV_R9701 is not set
 # CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
 
 #
 # Platform RTC drivers
 #
 # CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
 # CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
 # CONFIG_DMADEVICES is not set
-
-#
-# Voltage and Current regulators
-#
-# CONFIG_REGULATOR is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
 # CONFIG_REGULATOR_FIXED_VOLTAGE is not set
 # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
 # CONFIG_REGULATOR_BQ24022 is not set
+CONFIG_REGULATOR_TWL4030=y
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
 
 #
 # File systems
@@ -897,18 +1181,24 @@ CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 CONFIG_JBD=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
 CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_QUOTA_TREE=y
 # CONFIG_QFMT_V1 is not set
 CONFIG_QFMT_V2=y
 CONFIG_QUOTACTL=y
@@ -917,6 +1207,11 @@ CONFIG_QUOTACTL=y
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -937,15 +1232,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -954,6 +1247,7 @@ CONFIG_TMPFS=y
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@@ -962,6 +1256,7 @@ CONFIG_TMPFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -975,7 +1270,6 @@ CONFIG_NFS_ACL_SUPPORT=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1045,6 +1339,7 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
@@ -1062,6 +1357,9 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@@ -1084,21 +1382,36 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
-CONFIG_FRAME_POINTER=y
+# CONFIG_DEBUG_NOTIFIERS is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
-CONFIG_HAVE_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-# CONFIG_FTRACE is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
 # CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
 # CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
 # CONFIG_DEBUG_USER is not set
 # CONFIG_DEBUG_ERRORS is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
@@ -1110,17 +1423,28 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
 
 #
 # Crypto core or helper
 #
+# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
 CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
 CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
 # CONFIG_CRYPTO_CRYPTD is not set
 # CONFIG_CRYPTO_AUTHENC is not set
 # CONFIG_CRYPTO_TEST is not set
@@ -1152,7 +1476,7 @@ CONFIG_CRYPTO_PCBC=m
 #
 # Digest
 #
-# CONFIG_CRYPTO_CRC32C is not set
+CONFIG_CRYPTO_CRC32C=y
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
@@ -1189,15 +1513,21 @@ CONFIG_CRYPTO_DES=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_GENERIC_FIND_LAST_BIT=y
 CONFIG_CRC_CCITT=y
 # CONFIG_CRC16 is not set
 CONFIG_CRC_T10DIF=y
@@ -1205,7 +1535,9 @@ CONFIG_CRC_T10DIF=y
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
 CONFIG_LIBCRC32C=y
-CONFIG_PLIST=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig
index f238df66efd4..e7e31332c62a 100644
--- a/arch/arm/configs/rx51_defconfig
+++ b/arch/arm/configs/rx51_defconfig
@@ -1006,6 +1006,7 @@ CONFIG_WATCHDOG=y
 #
 # CONFIG_SOFT_WATCHDOG is not set
 CONFIG_OMAP_WATCHDOG=m
+CONFIG_TWL4030_WATCHDOG=m
 
 #
 # USB-based Watchdog Cards
diff --git a/arch/arm/configs/s5pc100_defconfig b/arch/arm/configs/s5pc100_defconfig
new file mode 100644
index 000000000000..b0d7d3d3a5e3
--- /dev/null
+++ b/arch/arm/configs/s5pc100_defconfig
@@ -0,0 +1,892 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30
+# Wed Jul  1 15:53:07 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_MMU=y
+CONFIG_NO_IOPORT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+# CONFIG_SYSVIPC is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+CONFIG_ARCH_S5PC1XX=y
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+CONFIG_PLAT_S3C=y
+
+#
+# Boot options
+#
+# CONFIG_S3C_BOOT_ERROR_RESET is not set
+CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
+
+#
+# Power management
+#
+CONFIG_S3C_LOWLEVEL_UART_PORT=0
+CONFIG_S3C_GPIO_SPACE=0
+CONFIG_S3C_GPIO_TRACK=y
+CONFIG_S3C_GPIO_PULL_UPDOWN=y
+CONFIG_PLAT_S5PC1XX=y
+CONFIG_CPU_S5PC100_INIT=y
+CONFIG_CPU_S5PC100_CLOCK=y
+CONFIG_S5PC100_SETUP_I2C0=y
+CONFIG_CPU_S5PC100=y
+CONFIG_MACH_SMDKC100=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_ARM_VIC=y
+CONFIG_ARM_VIC_NR=2
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC2,115200 mem=128M"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_CONSOLE is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_UARTS=3
+# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_PLTFM is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+CONFIG_ROMFS_ON_BLOCK=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_PI_LIST=y
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+CONFIG_DEBUG_S3C_PORT=y
+CONFIG_DEBUG_S3C_UART=0
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 15f8a092b700..00f46d9ce299 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -74,23 +74,56 @@
  * Enable and disable interrupts
  */
 #if __LINUX_ARM_ARCH__ >= 6
-        .macro  disable_irq
+        .macro  disable_irq_notrace
         cpsid   i
         .endm
 
-        .macro  enable_irq
+        .macro  enable_irq_notrace
         cpsie   i
         .endm
 #else
-        .macro  disable_irq
+        .macro  disable_irq_notrace
         msr     cpsr_c, #PSR_I_BIT | SVC_MODE
         .endm
 
-        .macro  enable_irq
+        .macro  enable_irq_notrace
         msr     cpsr_c, #SVC_MODE
         .endm
 #endif
 
+        .macro asm_trace_hardirqs_off
+#if defined(CONFIG_TRACE_IRQFLAGS)
+        stmdb   sp!, {r0-r3, ip, lr}
+        bl      trace_hardirqs_off
+        ldmia   sp!, {r0-r3, ip, lr}
+#endif
+        .endm
+
+        .macro asm_trace_hardirqs_on_cond, cond
+#if defined(CONFIG_TRACE_IRQFLAGS)
+        /*
+         * actually the registers should be pushed and pop'd conditionally, but
+         * after bl the flags are certainly clobbered
+         */
+        stmdb   sp!, {r0-r3, ip, lr}
+        bl\cond trace_hardirqs_on
+        ldmia   sp!, {r0-r3, ip, lr}
+#endif
+        .endm
+
+        .macro asm_trace_hardirqs_on
+        asm_trace_hardirqs_on_cond al
+        .endm
+
+        .macro disable_irq
+        disable_irq_notrace
+        asm_trace_hardirqs_off
+        .endm
+
+        .macro enable_irq
+        asm_trace_hardirqs_on
+        enable_irq_notrace
+        .endm
 /*
  * Save the current IRQ state and disable IRQs.  Note that this macro
  * assumes FIQs are enabled, and that the processor is in SVC mode.
@@ -104,10 +137,16 @@
  * Restore interrupt state previously stored in a register.  We don't
  * guarantee that this will preserve the flags.
  */
-        .macro  restore_irqs, oldcpsr
+        .macro  restore_irqs_notrace, oldcpsr
         msr     cpsr_c, \oldcpsr
         .endm
 
+        .macro restore_irqs, oldcpsr
+        tst     \oldcpsr, #PSR_I_BIT
+        asm_trace_hardirqs_on_cond eq
+        restore_irqs_notrace \oldcpsr
+        .endm
+
 #define USER(x...)                              \
 9999:   x;                                      \
         .section __ex_table,"a";                \
@@ -127,3 +166,87 @@
 #endif
 #endif
         .endm
+
+#ifdef CONFIG_THUMB2_KERNEL
+        .macro  setmode, mode, reg
+        mov     \reg, #\mode
+        msr     cpsr_c, \reg
+        .endm
+#else
+        .macro  setmode, mode, reg
+        msr     cpsr_c, #\mode
+        .endm
+#endif
+
+/*
+ * STRT/LDRT access macros with ARM and Thumb-2 variants
+ */
+#ifdef CONFIG_THUMB2_KERNEL
+
+        .macro  usraccoff, instr, reg, ptr, inc, off, cond, abort
+9999:
+        .if     \inc == 1
+        \instr\cond\()bt \reg, [\ptr, #\off]
+        .elseif \inc == 4
+        \instr\cond\()t \reg, [\ptr, #\off]
+        .else
+        .error  "Unsupported inc macro argument"
+        .endif
+
+        .section __ex_table,"a"
+        .align  3
+        .long   9999b, \abort
+        .previous
+        .endm
+
+        .macro  usracc, instr, reg, ptr, inc, cond, rept, abort
+        @ explicit IT instruction needed because of the label
+        @ introduced by the USER macro
+        .ifnc   \cond,al
+        .if     \rept == 1
+        itt     \cond
+        .elseif \rept == 2
+        ittt    \cond
+        .else
+        .error  "Unsupported rept macro argument"
+        .endif
+        .endif
+
+        @ Slightly optimised to avoid incrementing the pointer twice
+        usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
+        .if     \rept == 2
+        usraccoff \instr, \reg, \ptr, \inc, 4, \cond, \abort
+        .endif
+
+        add\cond \ptr, #\rept * \inc
+        .endm
+
+#else   /* !CONFIG_THUMB2_KERNEL */
+
+        .macro  usracc, instr, reg, ptr, inc, cond, rept, abort
+        .rept   \rept
+9999:
+        .if     \inc == 1
+        \instr\cond\()bt \reg, [\ptr], #\inc
+        .elseif \inc == 4
+        \instr\cond\()t \reg, [\ptr], #\inc
+        .else
+        .error  "Unsupported inc macro argument"
+        .endif
+
+        .section __ex_table,"a"
+        .align  3
+        .long   9999b, \abort
+        .previous
+        .endr
+        .endm
+
+#endif  /* CONFIG_THUMB2_KERNEL */
+
+        .macro  strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
+        usracc  str, \reg, \ptr, \inc, \cond, \rept, \abort
+        .endm
+
+        .macro  ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
+        usracc  ldr, \reg, \ptr, \inc, \cond, \rept, \abort
+        .endm
diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h
index c61642b40603..9f390ce335cb 100644
--- a/arch/arm/include/asm/device.h
+++ b/arch/arm/include/asm/device.h
@@ -12,4 +12,7 @@ struct dev_archdata {
 #endif
 };
 
+struct pdev_archdata {
+};
+
 #endif
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index c207504de84d..c3b911ee9151 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -55,6 +55,9 @@ typedef struct user_fp elf_fpregset_t;
 #define R_ARM_MOVW_ABS_NC       43
 #define R_ARM_MOVT_ABS          44
 
+#define R_ARM_THM_CALL          10
+#define R_ARM_THM_JUMP24        30
+
 /*
  * These are used to set parameters in the core dumps.
  */
diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h
index 39c8bc1a006a..103f7ee97313 100644
--- a/arch/arm/include/asm/ftrace.h
+++ b/arch/arm/include/asm/ftrace.h
@@ -7,8 +7,43 @@
 
 #ifndef __ASSEMBLY__
 extern void mcount(void);
+extern void __gnu_mcount_nc(void);
 #endif
 
 #endif
 
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND)
+/*
+ * return_address uses walk_stackframe to do it's work.  If both
+ * CONFIG_FRAME_POINTER=y and CONFIG_ARM_UNWIND=y walk_stackframe uses unwind
+ * information.  For this to work in the function tracer many functions would
+ * have to be marked with __notrace.  So for now just depend on
+ * !CONFIG_ARM_UNWIND.
+ */
+
+void *return_address(unsigned int);
+
+#else
+
+extern inline void *return_address(unsigned int level)
+{
+        return NULL;
+}
+
+#endif
+
+#define HAVE_ARCH_CALLER_ADDR
+
+#define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0))
+#define CALLER_ADDR1 ((unsigned long)return_address(1))
+#define CALLER_ADDR2 ((unsigned long)return_address(2))
+#define CALLER_ADDR3 ((unsigned long)return_address(3))
+#define CALLER_ADDR4 ((unsigned long)return_address(4))
+#define CALLER_ADDR5 ((unsigned long)return_address(5))
+#define CALLER_ADDR6 ((unsigned long)return_address(6))
+
+#endif /* ifndef __ASSEMBLY__ */
+
 #endif /* _ASM_ARM_FTRACE */
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 9ee743b95de8..bfcc15929a7f 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -99,6 +99,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
         __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
         "1:     ldrt    %0, [%3]\n"
         "       teq     %0, %1\n"
+        "       it      eq      @ explicit IT needed for the 2b label\n"
         "2:     streqt  %2, [%3]\n"
         "3:\n"
         "       .section __ex_table,\"a\"\n"
diff --git a/arch/arm/include/asm/mach/mmc.h b/arch/arm/include/asm/mach/mmc.h
index 4da332b03144..b490ecc79def 100644
--- a/arch/arm/include/asm/mach/mmc.h
+++ b/arch/arm/include/asm/mach/mmc.h
@@ -10,6 +10,8 @@ struct mmc_platform_data {
         unsigned int ocr_mask;                  /* available voltages */
         u32 (*translate_vdd)(struct device *, unsigned int);
         unsigned int (*status)(struct device *);
+        int     gpio_wp;
+        int     gpio_cd;
 };
 
 #endif
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 85763db87449..cefedf062138 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -44,7 +44,13 @@
  * The module space lives between the addresses given by TASK_SIZE
  * and PAGE_OFFSET - it must be within 32MB of the kernel text.
  */
+#ifndef CONFIG_THUMB2_KERNEL
 #define MODULES_VADDR           (PAGE_OFFSET - 16*1024*1024)
+#else
+/* smaller range for Thumb-2 symbols relocation (2^24)*/
+#define MODULES_VADDR           (PAGE_OFFSET - 8*1024*1024)
+#endif
+
 #if TASK_SIZE > MODULES_VADDR
 #error Top of user space clashes with start of module space
 #endif
@@ -212,7 +218,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
  *
  *  page_to_pfn(page)   convert a struct page * to a PFN number
  *  pfn_to_page(pfn)    convert a _valid_ PFN number to struct page *
- *  pfn_valid(pfn)      indicates whether a PFN number is valid
  *
  *  virt_to_page(k)     convert a _valid_ virtual address to struct page *
  *  virt_addr_valid(k)  indicates whether a virtual address is valid
@@ -221,10 +226,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 
 #define ARCH_PFN_OFFSET         PHYS_PFN_OFFSET
 
-#ifndef CONFIG_SPARSEMEM
-#define pfn_valid(pfn)          ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
-#endif
-
 #define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 #define virt_addr_valid(kaddr)  ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
 
@@ -241,18 +242,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 #define arch_pfn_to_nid(pfn)    PFN_TO_NID(pfn)
 #define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT)
 
-#define pfn_valid(pfn)                                          \
-        ({                                                      \
-                unsigned int nid = PFN_TO_NID(pfn);             \
-                int valid = nid < MAX_NUMNODES;                 \
-                if (valid) {                                    \
-                        pg_data_t *node = NODE_DATA(nid);       \
-                        valid = (pfn - node->node_start_pfn) <  \
-                                node->node_spanned_pages;       \
-                }                                               \
-                valid;                                          \
-        })
-
 #define virt_to_page(kaddr)                                     \
         (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
 
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index 263fed05ea33..bcdb9291ef0c 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -62,8 +62,10 @@ static inline void check_context(struct mm_struct *mm)
 
 static inline void check_context(struct mm_struct *mm)
 {
+#ifdef CONFIG_MMU
         if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
                 __check_kvm_seq(mm);
+#endif
 }
 
 #define init_new_context(tsk,mm)        0
diff --git a/arch/arm/include/asm/page-nommu.h b/arch/arm/include/asm/page-nommu.h
index 3574c0deb37f..d1b162a18dcb 100644
--- a/arch/arm/include/asm/page-nommu.h
+++ b/arch/arm/include/asm/page-nommu.h
@@ -43,7 +43,4 @@ typedef unsigned long pgprot_t;
 #define __pmd(x)        (x)
 #define __pgprot(x)     (x)
 
-extern unsigned long memory_start;
-extern unsigned long memory_end;
-
 #endif
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 9c746af1bf6e..3a32af4cce30 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -194,6 +194,10 @@ typedef unsigned long pgprot_t;
 
 typedef struct page *pgtable_t;
 
+#ifndef CONFIG_SPARSEMEM
+extern int pfn_valid(unsigned long);
+#endif
+
 #include <asm/memory.h>
 
 #endif /* !__ASSEMBLY__ */
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 0abf386ba3d3..226cddd2fb65 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -6,8 +6,6 @@
 
 #include <mach/hardware.h> /* for PCIBIOS_MIN_* */
 
-#define pcibios_scan_all_fns(a, b)      0
-
 #ifdef CONFIG_PCI_HOST_ITE8152
 /* ITE bridge requires setting latency timer to avoid early bus access
    termination by PIC bus mater devices
diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h
index 3dcd64bf1824..b12cc98bbe04 100644
--- a/arch/arm/include/asm/pgalloc.h
+++ b/arch/arm/include/asm/pgalloc.h
@@ -36,6 +36,8 @@ extern void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd);
 #define pgd_alloc(mm)                   get_pgd_slow(mm)
 #define pgd_free(mm, pgd)               free_pgd_slow(mm, pgd)
 
+#define PGALLOC_GFP     (GFP_KERNEL | __GFP_NOTRACK | __GFP_REPEAT | __GFP_ZERO)
+
 /*
  * Allocate one PTE table.
  *
@@ -57,7 +59,7 @@ pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr)
 {
         pte_t *pte;
 
-        pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
+        pte = (pte_t *)__get_free_page(PGALLOC_GFP);
         if (pte) {
                 clean_dcache_area(pte, sizeof(pte_t) * PTRS_PER_PTE);
                 pte += PTRS_PER_PTE;
@@ -71,10 +73,16 @@ pte_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
         struct page *pte;
 
-        pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0);
+#ifdef CONFIG_HIGHPTE
+        pte = alloc_pages(PGALLOC_GFP | __GFP_HIGHMEM, 0);
+#else
+        pte = alloc_pages(PGALLOC_GFP, 0);
+#endif
         if (pte) {
-                void *page = page_address(pte);
-                clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE);
+                if (!PageHighMem(pte)) {
+                        void *page = page_address(pte);
+                        clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE);
+                }
                 pgtable_page_ctor(pte);
         }
 
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index c433c6c73112..201ccaa11f61 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -162,10 +162,8 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
  * entries are stored 1024 bytes below.
  */
 #define L_PTE_PRESENT           (1 << 0)
-#define L_PTE_FILE              (1 << 1)        /* only when !PRESENT */
 #define L_PTE_YOUNG             (1 << 1)
-#define L_PTE_BUFFERABLE        (1 << 2)        /* obsolete, matches PTE */
-#define L_PTE_CACHEABLE         (1 << 3)        /* obsolete, matches PTE */
+#define L_PTE_FILE              (1 << 2)        /* only when !PRESENT */
 #define L_PTE_DIRTY             (1 << 6)
 #define L_PTE_WRITE             (1 << 7)
 #define L_PTE_USER              (1 << 8)
@@ -264,10 +262,19 @@ extern struct page *empty_zero_page;
 #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
 #define pte_page(pte)           (pfn_to_page(pte_pfn(pte)))
 #define pte_offset_kernel(dir,addr)     (pmd_page_vaddr(*(dir)) + __pte_index(addr))
-#define pte_offset_map(dir,addr)        (pmd_page_vaddr(*(dir)) + __pte_index(addr))
-#define pte_offset_map_nested(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr))
-#define pte_unmap(pte)          do { } while (0)
-#define pte_unmap_nested(pte)   do { } while (0)
+
+#define pte_offset_map(dir,addr)        (__pte_map(dir, KM_PTE0) + __pte_index(addr))
+#define pte_offset_map_nested(dir,addr) (__pte_map(dir, KM_PTE1) + __pte_index(addr))
+#define pte_unmap(pte)                  __pte_unmap(pte, KM_PTE0)
+#define pte_unmap_nested(pte)           __pte_unmap(pte, KM_PTE1)
+
+#ifndef CONFIG_HIGHPTE
+#define __pte_map(dir,km)       pmd_page_vaddr(*(dir))
+#define __pte_unmap(pte,km)     do { } while (0)
+#else
+#define __pte_map(dir,km)       ((pte_t *)kmap_atomic(pmd_page(*(dir)), km) + PTRS_PER_PTE)
+#define __pte_unmap(pte,km)     kunmap_atomic((pte - PTRS_PER_PTE), km)
+#endif
 
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
 
@@ -381,13 +388,13 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
  *
  *   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
  *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- *   <--------------- offset --------------------> <--- type --> 0 0
+ *   <--------------- offset --------------------> <- type --> 0 0 0
  *
- * This gives us up to 127 swap files and 32GB per swap file.  Note that
+ * This gives us up to 63 swap files and 32GB per swap file.  Note that
  * the offset field is always non-zero.
  */
-#define __SWP_TYPE_SHIFT        2
-#define __SWP_TYPE_BITS         7
+#define __SWP_TYPE_SHIFT        3
+#define __SWP_TYPE_BITS         6
 #define __SWP_TYPE_MASK         ((1 << __SWP_TYPE_BITS) - 1)
 #define __SWP_OFFSET_SHIFT      (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
 
@@ -411,13 +418,13 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
  *
  *   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
  *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- *   <------------------------ offset -------------------------> 1 0
+ *   <----------------------- offset ------------------------> 1 0 0
  */
 #define pte_file(pte)           (pte_val(pte) & L_PTE_FILE)
-#define pte_to_pgoff(x)         (pte_val(x) >> 2)
-#define pgoff_to_pte(x)         __pte(((x) << 2) | L_PTE_FILE)
+#define pte_to_pgoff(x)         (pte_val(x) >> 3)
+#define pgoff_to_pte(x)         __pte(((x) << 3) | L_PTE_FILE)
 
-#define PTE_FILE_MAX_BITS       30
+#define PTE_FILE_MAX_BITS       29
 
 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 /* FIXME: this is not correct */
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 67b833c9b6b9..bbecccda76d0 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -82,6 +82,14 @@
 #define PSR_ENDSTATE    0
 #endif
 
+/* 
+ * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
+ * process is located in memory.
+ */
+#define PT_TEXT_ADDR            0x10000
+#define PT_DATA_ADDR            0x10004
+#define PT_TEXT_END_ADDR        0x10008
+
 #ifndef __ASSEMBLY__
 
 /*
diff --git a/arch/arm/include/asm/socket.h b/arch/arm/include/asm/socket.h
index 537de4e0ef50..92ac61d294fd 100644
--- a/arch/arm/include/asm/socket.h
+++ b/arch/arm/include/asm/socket.h
@@ -57,4 +57,7 @@
 #define SO_TIMESTAMPING         37
 #define SCM_TIMESTAMPING        SO_TIMESTAMPING
 
+#define SO_PROTOCOL             38
+#define SO_DOMAIN               39
+
 #endif /* _ASM_SOCKET_H */
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 73394e50cbca..2dfb7d7a66e9 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -130,23 +130,28 @@ extern void vfp_sync_state(struct thread_info *thread);
  *  TIF_SYSCALL_TRACE   - syscall trace active
  *  TIF_SIGPENDING      - signal pending
  *  TIF_NEED_RESCHED    - rescheduling necessary
+ *  TIF_NOTIFY_RESUME   - callback before returning to user
  *  TIF_USEDFPU         - FPU was used by this task this quantum (SMP)
  *  TIF_POLLING_NRFLAG  - true if poll_idle() is polling TIF_NEED_RESCHED
  */
 #define TIF_SIGPENDING          0
 #define TIF_NEED_RESCHED        1
+#define TIF_NOTIFY_RESUME       2       /* callback before returning to user */
 #define TIF_SYSCALL_TRACE       8
 #define TIF_POLLING_NRFLAG      16
 #define TIF_USING_IWMMXT        17
 #define TIF_MEMDIE              18
 #define TIF_FREEZE              19
+#define TIF_RESTORE_SIGMASK     20
 
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
+#define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
 #define _TIF_POLLING_NRFLAG     (1 << TIF_POLLING_NRFLAG)
 #define _TIF_USING_IWMMXT       (1 << TIF_USING_IWMMXT)
 #define _TIF_FREEZE             (1 << TIF_FREEZE)
+#define _TIF_RESTORE_SIGMASK    (1 << TIF_RESTORE_SIGMASK)
 
 /*
  * Change these and you break ASM code in entry-common.S
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 0da9bc9b3b1d..1d6bd40a4322 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -17,6 +17,7 @@
 #include <asm/memory.h>
 #include <asm/domain.h>
 #include <asm/system.h>
+#include <asm/unified.h>
 
 #define VERIFY_READ 0
 #define VERIFY_WRITE 1
@@ -365,8 +366,10 @@ do {									\
 
 #define __put_user_asm_dword(x,__pu_addr,err)                   \
         __asm__ __volatile__(                                   \
-        "1:     strt    " __reg_oper1 ", [%1], #4\n"            \
-        "2:     strt    " __reg_oper0 ", [%1]\n"                \
+ ARM(   "1:     strt    " __reg_oper1 ", [%1], #4\n"    )       \
+ ARM(   "2:     strt    " __reg_oper0 ", [%1]\n"        )       \
+ THUMB( "1:     strt    " __reg_oper1 ", [%1]\n"        )       \
+ THUMB( "2:     strt    " __reg_oper0 ", [%1, #4]\n"    )       \
         "3:\n"                                                  \
         "       .section .fixup,\"ax\"\n"                       \
         "       .align  2\n"                                    \
diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h
new file mode 100644
index 000000000000..073e85b9b961
--- /dev/null
+++ b/arch/arm/include/asm/unified.h
@@ -0,0 +1,126 @@
+/*
+ * include/asm-arm/unified.h - Unified Assembler Syntax helper macros
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_UNIFIED_H
+#define __ASM_UNIFIED_H
+
+#if defined(__ASSEMBLY__) && defined(CONFIG_ARM_ASM_UNIFIED)
+        .syntax unified
+#endif
+
+#ifdef CONFIG_THUMB2_KERNEL
+
+#if __GNUC__ < 4
+#error Thumb-2 kernel requires gcc >= 4
+#endif
+
+/* The CPSR bit describing the instruction set (Thumb) */
+#define PSR_ISETSTATE   PSR_T_BIT
+
+#define ARM(x...)
+#define THUMB(x...)     x
+#define W(instr)        instr.w
+#define BSYM(sym)       sym + 1
+
+#else   /* !CONFIG_THUMB2_KERNEL */
+
+/* The CPSR bit describing the instruction set (ARM) */
+#define PSR_ISETSTATE   0
+
+#define ARM(x...)       x
+#define THUMB(x...)
+#define W(instr)        instr
+#define BSYM(sym)       sym
+
+#endif  /* CONFIG_THUMB2_KERNEL */
+
+#ifndef CONFIG_ARM_ASM_UNIFIED
+
+/*
+ * If the unified assembly syntax isn't used (in ARM mode), these
+ * macros expand to an empty string
+ */
+#ifdef __ASSEMBLY__
+        .macro  it, cond
+        .endm
+        .macro  itt, cond
+        .endm
+        .macro  ite, cond
+        .endm
+        .macro  ittt, cond
+        .endm
+        .macro  itte, cond
+        .endm
+        .macro  itet, cond
+        .endm
+        .macro  itee, cond
+        .endm
+        .macro  itttt, cond
+        .endm
+        .macro  ittte, cond
+        .endm
+        .macro  ittet, cond
+        .endm
+        .macro  ittee, cond
+        .endm
+        .macro  itett, cond
+        .endm
+        .macro  itete, cond
+        .endm
+        .macro  iteet, cond
+        .endm
+        .macro  iteee, cond
+        .endm
+#else   /* !__ASSEMBLY__ */
+__asm__(
+"       .macro  it, cond\n"
+"       .endm\n"
+"       .macro  itt, cond\n"
+"       .endm\n"
+"       .macro  ite, cond\n"
+"       .endm\n"
+"       .macro  ittt, cond\n"
+"       .endm\n"
+"       .macro  itte, cond\n"
+"       .endm\n"
+"       .macro  itet, cond\n"
+"       .endm\n"
+"       .macro  itee, cond\n"
+"       .endm\n"
+"       .macro  itttt, cond\n"
+"       .endm\n"
+"       .macro  ittte, cond\n"
+"       .endm\n"
+"       .macro  ittet, cond\n"
+"       .endm\n"
+"       .macro  ittee, cond\n"
+"       .endm\n"
+"       .macro  itett, cond\n"
+"       .endm\n"
+"       .macro  itete, cond\n"
+"       .endm\n"
+"       .macro  iteet, cond\n"
+"       .endm\n"
+"       .macro  iteee, cond\n"
+"       .endm\n");
+#endif  /* __ASSEMBLY__ */
+
+#endif  /* CONFIG_ARM_ASM_UNIFIED */
+
+#endif  /* !__ASM_UNIFIED_H */
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 0e97b8cb77d5..9122c9ee18fb 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -360,8 +360,8 @@
 #define __NR_readlinkat                 (__NR_SYSCALL_BASE+332)
 #define __NR_fchmodat                   (__NR_SYSCALL_BASE+333)
 #define __NR_faccessat                  (__NR_SYSCALL_BASE+334)
-                                        /* 335 for pselect6 */
-                                        /* 336 for ppoll */
+#define __NR_pselect6                   (__NR_SYSCALL_BASE+335)
+#define __NR_ppoll                      (__NR_SYSCALL_BASE+336)
 #define __NR_unshare                    (__NR_SYSCALL_BASE+337)
 #define __NR_set_robust_list            (__NR_SYSCALL_BASE+338)
 #define __NR_get_robust_list            (__NR_SYSCALL_BASE+339)
@@ -372,7 +372,7 @@
 #define __NR_vmsplice                   (__NR_SYSCALL_BASE+343)
 #define __NR_move_pages                 (__NR_SYSCALL_BASE+344)
 #define __NR_getcpu                     (__NR_SYSCALL_BASE+345)
-                                        /* 346 for epoll_pwait */
+#define __NR_epoll_pwait                (__NR_SYSCALL_BASE+346)
 #define __NR_kexec_load                 (__NR_SYSCALL_BASE+347)
 #define __NR_utimensat                  (__NR_SYSCALL_BASE+348)
 #define __NR_signalfd                   (__NR_SYSCALL_BASE+349)
@@ -432,6 +432,7 @@
 #define __ARCH_WANT_SYS_SIGPENDING
 #define __ARCH_WANT_SYS_SIGPROCMASK
 #define __ARCH_WANT_SYS_RT_SIGACTION
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
 
 #if !defined(CONFIG_AEABI) || defined(CONFIG_OABI_COMPAT)
 #define __ARCH_WANT_SYS_TIME
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index ff89d0b3abc5..3213c9382b17 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -8,10 +8,12 @@ ifdef CONFIG_DYNAMIC_FTRACE
 CFLAGS_REMOVE_ftrace.o = -pg
 endif
 
+CFLAGS_REMOVE_return_address.o = -pg
+
 # Object file lists.
 
 obj-y           := compat.o elf.o entry-armv.o entry-common.o irq.o \
-                   process.o ptrace.o setup.o signal.o \
+                   process.o ptrace.o return_address.o setup.o signal.o \
                    sys_arm.o stacktrace.o time.o traps.o
 
 obj-$(CONFIG_ISA_DMA_API)       += dma.o
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 531e1860e546..0e627705f746 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -186,4 +186,5 @@ EXPORT_SYMBOL(_find_next_bit_be);
 
 #ifdef CONFIG_FUNCTION_TRACER
 EXPORT_SYMBOL(mcount);
+EXPORT_SYMBOL(__gnu_mcount_nc);
 #endif
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index f776e72a4cb8..ecfa98954d1d 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -81,7 +81,7 @@
                 CALL(sys_ni_syscall)            /* was sys_ssetmask */
 /* 70 */        CALL(sys_setreuid16)
                 CALL(sys_setregid16)
-                CALL(sys_sigsuspend_wrapper)
+                CALL(sys_sigsuspend)
                 CALL(sys_sigpending)
                 CALL(sys_sethostname)
 /* 75 */        CALL(sys_setrlimit)
@@ -188,7 +188,7 @@
                 CALL(sys_rt_sigpending)
                 CALL(sys_rt_sigtimedwait)
                 CALL(sys_rt_sigqueueinfo)
-                CALL(sys_rt_sigsuspend_wrapper)
+                CALL(sys_rt_sigsuspend)
 /* 180 */       CALL(ABI(sys_pread64, sys_oabi_pread64))
                 CALL(ABI(sys_pwrite64, sys_oabi_pwrite64))
                 CALL(sys_chown16)
@@ -344,8 +344,8 @@
                 CALL(sys_readlinkat)
                 CALL(sys_fchmodat)
                 CALL(sys_faccessat)
-/* 335 */       CALL(sys_ni_syscall)            /* eventually pselect6 */
-                CALL(sys_ni_syscall)            /* eventually ppoll */
+/* 335 */       CALL(sys_pselect6)
+                CALL(sys_ppoll)
                 CALL(sys_unshare)
                 CALL(sys_set_robust_list)
                 CALL(sys_get_robust_list)
@@ -355,7 +355,7 @@
                 CALL(sys_vmsplice)
                 CALL(sys_move_pages)
 /* 345 */       CALL(sys_getcpu)
-                CALL(sys_ni_syscall)            /* eventually epoll_pwait */
+                CALL(sys_epoll_pwait)
                 CALL(sys_kexec_load)
                 CALL(sys_utimensat)
                 CALL(sys_signalfd)
diff --git a/arch/arm/kernel/crunch.c b/arch/arm/kernel/crunch.c
index 99995c2b2312..769abe15cf91 100644
--- a/arch/arm/kernel/crunch.c
+++ b/arch/arm/kernel/crunch.c
@@ -31,7 +31,7 @@ void crunch_task_release(struct thread_info *thread)
 
 static int crunch_enabled(u32 devcfg)
 {
-        return !!(devcfg & EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE);
+        return !!(devcfg & EP93XX_SYSCON_DEVCFG_CPENA);
 }
 
 static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t)
@@ -56,11 +56,16 @@ static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t)
                 break;
 
         case THREAD_NOTIFY_SWITCH:
-                devcfg = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
+                devcfg = __raw_readl(EP93XX_SYSCON_DEVCFG);
                 if (crunch_enabled(devcfg) || crunch_owner == crunch_state) {
-                        devcfg ^= EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
+                        /*
+                         * We don't use ep93xx_syscon_swlocked_write() here
+                         * because we are on the context switch path and
+                         * preemption is already disabled.
+                         */
+                        devcfg ^= EP93XX_SYSCON_DEVCFG_CPENA;
                         __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-                        __raw_writel(devcfg, EP93XX_SYSCON_DEVICE_CONFIG);
+                        __raw_writel(devcfg, EP93XX_SYSCON_DEVCFG);
                 }
                 break;
         }
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index fc8af43c5000..3d727a8a23bc 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -34,7 +34,7 @@
         @
         @ routine called with r0 = irq number, r1 = struct pt_regs *
         @
-        adrne   lr, 1b
+        adrne   lr, BSYM(1b)
         bne     asm_do_IRQ
 
 #ifdef CONFIG_SMP
@@ -46,13 +46,13 @@
          */
         test_for_ipi r0, r6, r5, lr
         movne   r0, sp
-        adrne   lr, 1b
+        adrne   lr, BSYM(1b)
         bne     do_IPI
 
 #ifdef CONFIG_LOCAL_TIMERS
         test_for_ltirq r0, r6, r5, lr
         movne   r0, sp
-        adrne   lr, 1b
+        adrne   lr, BSYM(1b)
         bne     do_local_timer
 #endif
 #endif
@@ -70,7 +70,10 @@
  */
         .macro  inv_entry, reason
         sub     sp, sp, #S_FRAME_SIZE
-        stmib   sp, {r1 - lr}
+ ARM(   stmib   sp, {r1 - lr}           )
+ THUMB( stmia   sp, {r0 - r12}          )
+ THUMB( str     sp, [sp, #S_SP]         )
+ THUMB( str     lr, [sp, #S_LR]         )
         mov     r1, #\reason
         .endm
 
@@ -126,17 +129,24 @@ ENDPROC(__und_invalid)
         .macro  svc_entry, stack_hole=0
  UNWIND(.fnstart                )
  UNWIND(.save {r0 - pc}         )
-        sub     sp, sp, #(S_FRAME_SIZE + \stack_hole)
+        sub     sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
+#ifdef CONFIG_THUMB2_KERNEL
+ SPFIX( str     r0, [sp]        )       @ temporarily saved
+ SPFIX( mov     r0, sp          )
+ SPFIX( tst     r0, #4          )       @ test original stack alignment
+ SPFIX( ldr     r0, [sp]        )       @ restored
+#else
  SPFIX( tst     sp, #4          )
- SPFIX( bicne   sp, sp, #4      )
-        stmib   sp, {r1 - r12}
+#endif
+ SPFIX( subeq   sp, sp, #4      )
+        stmia   sp, {r1 - r12}
 
         ldmia   r0, {r1 - r3}
-        add     r5, sp, #S_SP           @ here for interlock avoidance
+        add     r5, sp, #S_SP - 4       @ here for interlock avoidance
         mov     r4, #-1                 @  ""  ""      ""       ""
-        add     r0, sp, #(S_FRAME_SIZE + \stack_hole)
- SPFIX( addne   r0, r0, #4      )
-        str     r1, [sp]                @ save the "real" r0 copied
+        add     r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
+ SPFIX( addeq   r0, r0, #4      )
+        str     r1, [sp, #-4]!          @ save the "real" r0 copied
                                         @ from the exception stack
 
         mov     r1, lr
@@ -151,6 +161,8 @@ ENDPROC(__und_invalid)
         @  r4 - orig_r0 (see pt_regs definition in ptrace.h)
         @
         stmia   r5, {r0 - r4}
+
+        asm_trace_hardirqs_off
         .endm
 
         .align  5
@@ -196,9 +208,8 @@ __dabt_svc:
         @
         @ restore SPSR and restart the instruction
         @
-        ldr     r0, [sp, #S_PSR]
-        msr     spsr_cxsf, r0
-        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+        ldr     r2, [sp, #S_PSR]
+        svc_exit r2                             @ return from exception
  UNWIND(.fnend          )
 ENDPROC(__dabt_svc)
 
@@ -206,9 +217,6 @@ ENDPROC(__dabt_svc)
 __irq_svc:
         svc_entry
 
-#ifdef CONFIG_TRACE_IRQFLAGS
-        bl      trace_hardirqs_off
-#endif
 #ifdef CONFIG_PREEMPT
         get_thread_info tsk
         ldr     r8, [tsk, #TI_PREEMPT]          @ get preempt count
@@ -225,13 +233,12 @@ __irq_svc:
         tst     r0, #_TIF_NEED_RESCHED
         blne    svc_preempt
 #endif
-        ldr     r0, [sp, #S_PSR]                @ irqs are already disabled
-        msr     spsr_cxsf, r0
+        ldr     r4, [sp, #S_PSR]                @ irqs are already disabled
 #ifdef CONFIG_TRACE_IRQFLAGS
-        tst     r0, #PSR_I_BIT
+        tst     r4, #PSR_I_BIT
         bleq    trace_hardirqs_on
 #endif
-        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+        svc_exit r4                             @ return from exception
  UNWIND(.fnend          )
 ENDPROC(__irq_svc)
 
@@ -266,7 +273,7 @@ __und_svc:
         @  r0 - instruction
         @
         ldr     r0, [r2, #-4]
-        adr     r9, 1f
+        adr     r9, BSYM(1f)
         bl      call_fpe
 
         mov     r0, sp                          @ struct pt_regs *regs
@@ -280,9 +287,8 @@ __und_svc:
         @
         @ restore SPSR and restart the instruction
         @
-        ldr     lr, [sp, #S_PSR]                @ Get SVC cpsr
-        msr     spsr_cxsf, lr
-        ldmia   sp, {r0 - pc}^                  @ Restore SVC registers
+        ldr     r2, [sp, #S_PSR]                @ Get SVC cpsr
+        svc_exit r2                             @ return from exception
  UNWIND(.fnend          )
 ENDPROC(__und_svc)
 
@@ -323,9 +329,8 @@ __pabt_svc:
         @
         @ restore SPSR and restart the instruction
         @
-        ldr     r0, [sp, #S_PSR]
-        msr     spsr_cxsf, r0
-        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+        ldr     r2, [sp, #S_PSR]
+        svc_exit r2                             @ return from exception
  UNWIND(.fnend          )
 ENDPROC(__pabt_svc)
 
@@ -353,7 +358,8 @@ ENDPROC(__pabt_svc)
  UNWIND(.fnstart        )
  UNWIND(.cantunwind     )       @ don't unwind the user space
         sub     sp, sp, #S_FRAME_SIZE
-        stmib   sp, {r1 - r12}
+ ARM(   stmib   sp, {r1 - r12}  )
+ THUMB( stmia   sp, {r0 - r12}  )
 
         ldmia   r0, {r1 - r3}
         add     r0, sp, #S_PC           @ here for interlock avoidance
@@ -372,7 +378,8 @@ ENDPROC(__pabt_svc)
         @ Also, separately save sp_usr and lr_usr
         @
         stmia   r0, {r2 - r4}
-        stmdb   r0, {sp, lr}^
+ ARM(   stmdb   r0, {sp, lr}^                   )
+ THUMB( store_user_sp_lr r0, r1, S_SP - S_PC    )
 
         @
         @ Enable the alignment trap while in kernel mode
@@ -383,6 +390,8 @@ ENDPROC(__pabt_svc)
         @ Clear FP to mark the first stack frame
         @
         zero_fp
+
+        asm_trace_hardirqs_off
         .endm
 
         .macro  kuser_cmpxchg_check
@@ -427,7 +436,7 @@ __dabt_usr:
         @
         enable_irq
         mov     r2, sp
-        adr     lr, ret_from_exception
+        adr     lr, BSYM(ret_from_exception)
         b       do_DataAbort
  UNWIND(.fnend          )
 ENDPROC(__dabt_usr)
@@ -437,9 +446,6 @@ __irq_usr:
         usr_entry
         kuser_cmpxchg_check
 
-#ifdef CONFIG_TRACE_IRQFLAGS
-        bl      trace_hardirqs_off
-#endif
         get_thread_info tsk
 #ifdef CONFIG_PREEMPT
         ldr     r8, [tsk, #TI_PREEMPT]          @ get preempt count
@@ -452,7 +458,9 @@ __irq_usr:
         ldr     r0, [tsk, #TI_PREEMPT]
         str     r8, [tsk, #TI_PREEMPT]
         teq     r0, r7
-        strne   r0, [r0, -r0]
+ ARM(   strne   r0, [r0, -r0]   )
+ THUMB( movne   r0, #0          )
+ THUMB( strne   r0, [r0]        )
 #endif
 #ifdef CONFIG_TRACE_IRQFLAGS
         bl      trace_hardirqs_on
@@ -476,9 +484,10 @@ __und_usr:
         @
         @  r0 - instruction
         @
-        adr     r9, ret_from_exception
-        adr     lr, __und_usr_unknown
+        adr     r9, BSYM(ret_from_exception)
+        adr     lr, BSYM(__und_usr_unknown)
         tst     r3, #PSR_T_BIT                  @ Thumb mode?
+        itet    eq                              @ explicit IT needed for the 1f label
         subeq   r4, r2, #4                      @ ARM instr at LR - 4
         subne   r4, r2, #2                      @ Thumb instr at LR - 2
 1:      ldreqt  r0, [r4]
@@ -488,7 +497,10 @@ __und_usr:
         beq     call_fpe
         @ Thumb instruction
 #if __LINUX_ARM_ARCH__ >= 7
-2:      ldrht   r5, [r4], #2
+2:
+ ARM(   ldrht   r5, [r4], #2    )
+ THUMB( ldrht   r5, [r4]        )
+ THUMB( add     r4, r4, #2      )
         and     r0, r5, #0xf800                 @ mask bits 111x x... .... ....
         cmp     r0, #0xe800                     @ 32bit instruction if xx != 0
         blo     __und_usr_unknown
@@ -577,9 +589,11 @@ call_fpe:
         moveq   pc, lr
         get_thread_info r10                     @ get current thread
         and     r8, r0, #0x00000f00             @ mask out CP number
+ THUMB( lsr     r8, r8, #8              )
         mov     r7, #1
         add     r6, r10, #TI_USED_CP
-        strb    r7, [r6, r8, lsr #8]            @ set appropriate used_cp[]
+ ARM(   strb    r7, [r6, r8, lsr #8]    )       @ set appropriate used_cp[]
+ THUMB( strb    r7, [r6, r8]            )       @ set appropriate used_cp[]
 #ifdef CONFIG_IWMMXT
         @ Test if we need to give access to iWMMXt coprocessors
         ldr     r5, [r10, #TI_FLAGS]
@@ -587,36 +601,38 @@ call_fpe:
         movcss  r7, r5, lsr #(TIF_USING_IWMMXT + 1)
         bcs     iwmmxt_task_enable
 #endif
-        add     pc, pc, r8, lsr #6
-        mov     r0, r0
-
-        mov     pc, lr                          @ CP#0
-        b       do_fpe                          @ CP#1 (FPE)
-        b       do_fpe                          @ CP#2 (FPE)
-        mov     pc, lr                          @ CP#3
+ ARM(   add     pc, pc, r8, lsr #6      )
+ THUMB( lsl     r8, r8, #2              )
+ THUMB( add     pc, r8                  )
+        nop
+
+        W(mov)  pc, lr                          @ CP#0
+        W(b)    do_fpe                          @ CP#1 (FPE)
+        W(b)    do_fpe                          @ CP#2 (FPE)
+        W(mov)  pc, lr                          @ CP#3
 #ifdef CONFIG_CRUNCH
         b       crunch_task_enable              @ CP#4 (MaverickCrunch)
         b       crunch_task_enable              @ CP#5 (MaverickCrunch)
         b       crunch_task_enable              @ CP#6 (MaverickCrunch)
 #else
-        mov     pc, lr                          @ CP#4
-        mov     pc, lr                          @ CP#5
-        mov     pc, lr                          @ CP#6
+        W(mov)  pc, lr                          @ CP#4
+        W(mov)  pc, lr                          @ CP#5
+        W(mov)  pc, lr                          @ CP#6
 #endif
-        mov     pc, lr                          @ CP#7
-        mov     pc, lr                          @ CP#8
-        mov     pc, lr                          @ CP#9
+        W(mov)  pc, lr                          @ CP#7
+        W(mov)  pc, lr                          @ CP#8
+        W(mov)  pc, lr                          @ CP#9
 #ifdef CONFIG_VFP
-        b       do_vfp                          @ CP#10 (VFP)
-        b       do_vfp                          @ CP#11 (VFP)
+        W(b)    do_vfp                          @ CP#10 (VFP)
+        W(b)    do_vfp                          @ CP#11 (VFP)
 #else
-        mov     pc, lr                          @ CP#10 (VFP)
-        mov     pc, lr                          @ CP#11 (VFP)
+        W(mov)  pc, lr                          @ CP#10 (VFP)
+        W(mov)  pc, lr                          @ CP#11 (VFP)
 #endif
-        mov     pc, lr                          @ CP#12
-        mov     pc, lr                          @ CP#13
-        mov     pc, lr                          @ CP#14 (Debug)
-        mov     pc, lr                          @ CP#15 (Control)
+        W(mov)  pc, lr                          @ CP#12
+        W(mov)  pc, lr                          @ CP#13
+        W(mov)  pc, lr                          @ CP#14 (Debug)
+        W(mov)  pc, lr                          @ CP#15 (Control)
 
 #ifdef CONFIG_NEON
         .align  6
@@ -667,7 +683,7 @@ no_fp:	mov	pc, lr
 __und_usr_unknown:
         enable_irq
         mov     r0, sp
-        adr     lr, ret_from_exception
+        adr     lr, BSYM(ret_from_exception)
         b       do_undefinstr
 ENDPROC(__und_usr_unknown)
 
@@ -711,7 +727,10 @@ ENTRY(__switch_to)
  UNWIND(.cantunwind     )
         add     ip, r1, #TI_CPU_SAVE
         ldr     r3, [r2, #TI_TP_VALUE]
-        stmia   ip!, {r4 - sl, fp, sp, lr}      @ Store most regs on stack
+ ARM(   stmia   ip!, {r4 - sl, fp, sp, lr} )    @ Store most regs on stack
+ THUMB( stmia   ip!, {r4 - sl, fp}         )    @ Store most regs on stack
+ THUMB( str     sp, [ip], #4               )
+ THUMB( str     lr, [ip], #4               )
 #ifdef CONFIG_MMU
         ldr     r6, [r2, #TI_CPU_DOMAIN]
 #endif
@@ -736,8 +755,12 @@ ENTRY(__switch_to)
         ldr     r0, =thread_notify_head
         mov     r1, #THREAD_NOTIFY_SWITCH
         bl      atomic_notifier_call_chain
+ THUMB( mov     ip, r4                     )
         mov     r0, r5
-        ldmia   r4, {r4 - sl, fp, sp, pc}       @ Load all regs saved previously
+ ARM(   ldmia   r4, {r4 - sl, fp, sp, pc}  )    @ Load all regs saved previously
+ THUMB( ldmia   ip!, {r4 - sl, fp}         )    @ Load all regs saved previously
+ THUMB( ldr     sp, [ip], #4               )
+ THUMB( ldr     pc, [ip]                   )
  UNWIND(.fnend          )
 ENDPROC(__switch_to)
 
@@ -772,6 +795,7 @@ ENDPROC(__switch_to)
  * if your compiled code is not going to use the new instructions for other
  * purpose.
  */
+ THUMB( .arm    )
 
         .macro  usr_ret, reg
 #ifdef CONFIG_ARM_THUMB
@@ -1020,6 +1044,7 @@ __kuser_helper_version:				@ 0xffff0ffc
         .globl  __kuser_helper_end
 __kuser_helper_end:
 
+ THUMB( .thumb  )
 
 /*
  * Vector stubs.
@@ -1054,17 +1079,23 @@ vector_\name:
         @ Prepare for SVC32 mode.  IRQs remain disabled.
         @
         mrs     r0, cpsr
-        eor     r0, r0, #(\mode ^ SVC_MODE)
+        eor     r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
         msr     spsr_cxsf, r0
 
         @
         @ the branch table must immediately follow this code
         @
         and     lr, lr, #0x0f
+ THUMB( adr     r0, 1f                  )
+ THUMB( ldr     lr, [r0, lr, lsl #2]    )
         mov     r0, sp
-        ldr     lr, [pc, lr, lsl #2]
+ ARM(   ldr     lr, [pc, lr, lsl #2]    )
         movs    pc, lr                  @ branch to handler in SVC mode
 ENDPROC(vector_\name)
+
+        .align  2
+        @ handler addresses follow this label
+1:
         .endm
 
         .globl  __stubs_start
@@ -1202,14 +1233,16 @@ __stubs_end:
 
         .globl  __vectors_start
 __vectors_start:
-        swi     SYS_ERROR0
-        b       vector_und + stubs_offset
-        ldr     pc, .LCvswi + stubs_offset
-        b       vector_pabt + stubs_offset
-        b       vector_dabt + stubs_offset
-        b       vector_addrexcptn + stubs_offset
-        b       vector_irq + stubs_offset
-        b       vector_fiq + stubs_offset
+ ARM(   swi     SYS_ERROR0      )
+ THUMB( svc     #0              )
+ THUMB( nop                     )
+        W(b)    vector_und + stubs_offset
+        W(ldr)  pc, .LCvswi + stubs_offset
+        W(b)    vector_pabt + stubs_offset
+        W(b)    vector_dabt + stubs_offset
+        W(b)    vector_addrexcptn + stubs_offset
+        W(b)    vector_irq + stubs_offset
+        W(b)    vector_fiq + stubs_offset
 
         .globl  __vectors_end
 __vectors_end:
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 8c3de1a350b5..807cfebb0f44 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -33,14 +33,7 @@ ret_fast_syscall:
         /* perform architecture specific actions before user return */
         arch_ret_to_user r1, lr
 
-        @ fast_restore_user_regs
-        ldr     r1, [sp, #S_OFF + S_PSR]        @ get calling cpsr
-        ldr     lr, [sp, #S_OFF + S_PC]!        @ get pc
-        msr     spsr_cxsf, r1                   @ save in spsr_svc
-        ldmdb   sp, {r1 - lr}^                  @ get calling r1 - lr
-        mov     r0, r0
-        add     sp, sp, #S_FRAME_SIZE - S_PC
-        movs    pc, lr                          @ return & move spsr_svc into cpsr
+        restore_user_regs fast = 1, offset = S_OFF
  UNWIND(.fnend          )
 
 /*
@@ -51,7 +44,7 @@ fast_work_pending:
 work_pending:
         tst     r1, #_TIF_NEED_RESCHED
         bne     work_resched
-        tst     r1, #_TIF_SIGPENDING
+        tst     r1, #_TIF_SIGPENDING|_TIF_NOTIFY_RESUME
         beq     no_work_pending
         mov     r0, sp                          @ 'regs'
         mov     r2, why                         @ 'syscall'
@@ -73,14 +66,7 @@ no_work_pending:
         /* perform architecture specific actions before user return */
         arch_ret_to_user r1, lr
 
-        @ slow_restore_user_regs
-        ldr     r1, [sp, #S_PSR]                @ get calling cpsr
-        ldr     lr, [sp, #S_PC]!                @ get pc
-        msr     spsr_cxsf, r1                   @ save in spsr_svc
-        ldmdb   sp, {r0 - lr}^                  @ get calling r0 - lr
-        mov     r0, r0
-        add     sp, sp, #S_FRAME_SIZE - S_PC
-        movs    pc, lr                          @ return & move spsr_svc into cpsr
+        restore_user_regs fast = 0, offset = 0
 ENDPROC(ret_to_user)
 
 /*
@@ -132,6 +118,25 @@ ftrace_call:
 
 #else
 
+ENTRY(__gnu_mcount_nc)
+        stmdb sp!, {r0-r3, lr}
+        ldr r0, =ftrace_trace_function
+        ldr r2, [r0]
+        adr r0, ftrace_stub
+        cmp r0, r2
+        bne gnu_trace
+        ldmia sp!, {r0-r3, ip, lr}
+        bx ip
+
+gnu_trace:
+        ldr r1, [sp, #20]                       @ lr of instrumented routine
+        mov r0, lr
+        sub r0, r0, #MCOUNT_INSN_SIZE
+        mov lr, pc
+        mov pc, r2
+        ldmia sp!, {r0-r3, ip, lr}
+        bx ip
+
 ENTRY(mcount)
         stmdb sp!, {r0-r3, lr}
         ldr r0, =ftrace_trace_function
@@ -182,8 +187,10 @@ ftrace_stub:
 ENTRY(vector_swi)
         sub     sp, sp, #S_FRAME_SIZE
         stmia   sp, {r0 - r12}                  @ Calling r0 - r12
-        add     r8, sp, #S_PC
-        stmdb   r8, {sp, lr}^                   @ Calling sp, lr
+ ARM(   add     r8, sp, #S_PC           )
+ ARM(   stmdb   r8, {sp, lr}^           )       @ Calling sp, lr
+ THUMB( mov     r8, sp                  )
+ THUMB( store_user_sp_lr r8, r10, S_SP  )       @ calling sp, lr
         mrs     r8, spsr                        @ called from non-FIQ mode, so ok.
         str     lr, [sp, #S_PC]                 @ Save calling PC
         str     r8, [sp, #S_PSR]                @ Save CPSR
@@ -272,7 +279,7 @@ ENTRY(vector_swi)
         bne     __sys_trace
 
         cmp     scno, #NR_syscalls              @ check upper syscall limit
-        adr     lr, ret_fast_syscall            @ return address
+        adr     lr, BSYM(ret_fast_syscall)      @ return address
         ldrcc   pc, [tbl, scno, lsl #2]         @ call sys_* routine
 
         add     r1, sp, #S_OFF
@@ -293,7 +300,7 @@ __sys_trace:
         mov     r0, #0                          @ trace entry [IP = 0]
         bl      syscall_trace
 
-        adr     lr, __sys_trace_return          @ return address
+        adr     lr, BSYM(__sys_trace_return)    @ return address
         mov     scno, r0                        @ syscall number (possibly new)
         add     r1, sp, #S_R0 + S_OFF           @ pointer to regs
         cmp     scno, #NR_syscalls              @ check upper syscall limit
@@ -373,16 +380,6 @@ sys_clone_wrapper:
                 b       sys_clone
 ENDPROC(sys_clone_wrapper)
 
-sys_sigsuspend_wrapper:
-                add     r3, sp, #S_OFF
-                b       sys_sigsuspend
-ENDPROC(sys_sigsuspend_wrapper)
-
-sys_rt_sigsuspend_wrapper:
-                add     r2, sp, #S_OFF
-                b       sys_rt_sigsuspend
-ENDPROC(sys_rt_sigsuspend_wrapper)
-
 sys_sigreturn_wrapper:
                 add     r0, sp, #S_OFF
                 b       sys_sigreturn
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 87ab4e157997..a4eaf4f920c5 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -36,11 +36,6 @@
 #endif
         .endm
 
-        .macro  get_thread_info, rd
-        mov     \rd, sp, lsr #13
-        mov     \rd, \rd, lsl #13
-        .endm
-
         .macro  alignment_trap, rtemp
 #ifdef CONFIG_ALIGNMENT_TRAP
         ldr     \rtemp, .LCcralign
@@ -49,6 +44,93 @@
 #endif
         .endm
 
+        @
+        @ Store/load the USER SP and LR registers by switching to the SYS
+        @ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
+        @ available. Should only be called from SVC mode
+        @
+        .macro  store_user_sp_lr, rd, rtemp, offset = 0
+        mrs     \rtemp, cpsr
+        eor     \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
+        msr     cpsr_c, \rtemp                  @ switch to the SYS mode
+
+        str     sp, [\rd, #\offset]             @ save sp_usr
+        str     lr, [\rd, #\offset + 4]         @ save lr_usr
+
+        eor     \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
+        msr     cpsr_c, \rtemp                  @ switch back to the SVC mode
+        .endm
+
+        .macro  load_user_sp_lr, rd, rtemp, offset = 0
+        mrs     \rtemp, cpsr
+        eor     \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
+        msr     cpsr_c, \rtemp                  @ switch to the SYS mode
+
+        ldr     sp, [\rd, #\offset]             @ load sp_usr
+        ldr     lr, [\rd, #\offset + 4]         @ load lr_usr
+
+        eor     \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
+        msr     cpsr_c, \rtemp                  @ switch back to the SVC mode
+        .endm
+
+#ifndef CONFIG_THUMB2_KERNEL
+        .macro  svc_exit, rpsr
+        msr     spsr_cxsf, \rpsr
+        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+        .endm
+
+        .macro  restore_user_regs, fast = 0, offset = 0
+        ldr     r1, [sp, #\offset + S_PSR]      @ get calling cpsr
+        ldr     lr, [sp, #\offset + S_PC]!      @ get pc
+        msr     spsr_cxsf, r1                   @ save in spsr_svc
+        .if     \fast
+        ldmdb   sp, {r1 - lr}^                  @ get calling r1 - lr
+        .else
+        ldmdb   sp, {r0 - lr}^                  @ get calling r0 - lr
+        .endif
+        add     sp, sp, #S_FRAME_SIZE - S_PC
+        movs    pc, lr                          @ return & move spsr_svc into cpsr
+        .endm
+
+        .macro  get_thread_info, rd
+        mov     \rd, sp, lsr #13
+        mov     \rd, \rd, lsl #13
+        .endm
+#else   /* CONFIG_THUMB2_KERNEL */
+        .macro  svc_exit, rpsr
+        ldr     r0, [sp, #S_SP]                 @ top of the stack
+        ldr     r1, [sp, #S_PC]                 @ return address
+        tst     r0, #4                          @ orig stack 8-byte aligned?
+        stmdb   r0, {r1, \rpsr}                 @ rfe context
+        ldmia   sp, {r0 - r12}
+        ldr     lr, [sp, #S_LR]
+        addeq   sp, sp, #S_FRAME_SIZE - 8       @ aligned
+        addne   sp, sp, #S_FRAME_SIZE - 4       @ not aligned
+        rfeia   sp!
+        .endm
+
+        .macro  restore_user_regs, fast = 0, offset = 0
+        mov     r2, sp
+        load_user_sp_lr r2, r3, \offset + S_SP  @ calling sp, lr
+        ldr     r1, [sp, #\offset + S_PSR]      @ get calling cpsr
+        ldr     lr, [sp, #\offset + S_PC]       @ get pc
+        add     sp, sp, #\offset + S_SP
+        msr     spsr_cxsf, r1                   @ save in spsr_svc
+        .if     \fast
+        ldmdb   sp, {r1 - r12}                  @ get calling r1 - r12
+        .else
+        ldmdb   sp, {r0 - r12}                  @ get calling r0 - r12
+        .endif
+        add     sp, sp, #S_FRAME_SIZE - S_SP
+        movs    pc, lr                          @ return & move spsr_svc into cpsr
+        .endm
+
+        .macro  get_thread_info, rd
+        mov     \rd, sp
+        lsr     \rd, \rd, #13
+        mov     \rd, \rd, lsl #13
+        .endm
+#endif  /* !CONFIG_THUMB2_KERNEL */
 
 /*
  * These are the registers used in the syscall handler, and allow us to
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 991952c644d1..93ad576b2d74 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -14,6 +14,7 @@
 #define ATAG_CORE 0x54410001
 #define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2)
 
+        .align  2
         .type   __switch_data, %object
 __switch_data:
         .long   __mmap_switched
@@ -51,7 +52,9 @@ __mmap_switched:
         strcc   fp, [r6],#4
         bcc     1b
 
-        ldmia   r3, {r4, r5, r6, r7, sp}
+ ARM(   ldmia   r3, {r4, r5, r6, r7, sp})
+ THUMB( ldmia   r3, {r4, r5, r6, r7}    )
+ THUMB( ldr     sp, [r3, #16]           )
         str     r9, [r4]                        @ Save processor ID
         str     r1, [r5]                        @ Save machine type
         str     r2, [r6]                        @ Save atags pointer
@@ -155,7 +158,8 @@ ENDPROC(__error)
  */
 __lookup_processor_type:
         adr     r3, 3f
-        ldmda   r3, {r5 - r7}
+        ldmia   r3, {r5 - r7}
+        add     r3, r3, #8
         sub     r3, r3, r7                      @ get offset between virt&phys
         add     r5, r5, r3                      @ convert virt addresses to
         add     r6, r6, r3                      @ physical address space
@@ -185,9 +189,10 @@ ENDPROC(lookup_processor_type)
  * Look in <asm/procinfo.h> and arch/arm/kernel/arch.[ch] for
  * more information about the __proc_info and __arch_info structures.
  */
-        .long   __proc_info_begin
+        .align  2
+3:      .long   __proc_info_begin
         .long   __proc_info_end
-3:      .long   .
+4:      .long   .
         .long   __arch_info_begin
         .long   __arch_info_end
 
@@ -203,7 +208,7 @@ ENDPROC(lookup_processor_type)
  *  r5 = mach_info pointer in physical address space
  */
 __lookup_machine_type:
-        adr     r3, 3b
+        adr     r3, 4b
         ldmia   r3, {r4, r5, r6}
         sub     r3, r3, r4                      @ get offset between virt&phys
         add     r5, r5, r3                      @ convert virt addresses to
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index cc87e1765ed2..e5dfc2895e24 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -34,7 +34,7 @@
  */
         .section ".text.head", "ax"
 ENTRY(stext)
-        msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                 @ and irqs disabled
 #ifndef CONFIG_CPU_CP15
         ldr     r9, =CONFIG_PROCESSOR_ID
@@ -50,8 +50,10 @@ ENTRY(stext)
 
         ldr     r13, __switch_data              @ address to jump to after
                                                 @ the initialization is done
-        adr     lr, __after_proc_init           @ return (PIC) address
-        add     pc, r10, #PROCINFO_INITFUNC
+        adr     lr, BSYM(__after_proc_init)     @ return (PIC) address
+ ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
+ THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
+ THUMB( mov     pc, r12                         )
 ENDPROC(stext)
 
 /*
@@ -59,7 +61,10 @@ ENDPROC(stext)
  */
 __after_proc_init:
 #ifdef CONFIG_CPU_CP15
-        mrc     p15, 0, r0, c1, c0, 0           @ read control reg
+        /*
+         * CP15 system control register value returned in r0 from
+         * the CPU init function.
+         */
 #ifdef CONFIG_ALIGNMENT_TRAP
         orr     r0, r0, #CR_A
 #else
@@ -82,7 +87,8 @@ __after_proc_init:
         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 #endif /* CONFIG_CPU_CP15 */
 
-        mov     pc, r13                         @ clear the BSS and jump
+        mov     r3, r13
+        mov     pc, r3                          @ clear the BSS and jump
                                                 @ to start_kernel
 ENDPROC(__after_proc_init)
         .ltorg
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 21e17dc94cb5..38ccbe1d3b2c 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -76,7 +76,7 @@
  */
         .section ".text.head", "ax"
 ENTRY(stext)
-        msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                 @ and irqs disabled
         mrc     p15, 0, r9, c0, c0              @ get processor id
         bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
@@ -97,8 +97,10 @@ ENTRY(stext)
          */
         ldr     r13, __switch_data              @ address to jump to after
                                                 @ mmu has been enabled
-        adr     lr, __enable_mmu                @ return (PIC) address
-        add     pc, r10, #PROCINFO_INITFUNC
+        adr     lr, BSYM(__enable_mmu)          @ return (PIC) address
+ ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
+ THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
+ THUMB( mov     pc, r12                         )
 ENDPROC(stext)
 
 #if defined(CONFIG_SMP)
@@ -110,7 +112,7 @@ ENTRY(secondary_startup)
          * the processor type - there is no need to check the machine type
          * as it has already been validated by the primary processor.
          */
-        msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
         mrc     p15, 0, r9, c0, c0              @ get processor id
         bl      __lookup_processor_type
         movs    r10, r5                         @ invalid processor?
@@ -121,12 +123,15 @@ ENTRY(secondary_startup)
          * Use the page tables supplied from  __cpu_up.
          */
         adr     r4, __secondary_data
-        ldmia   r4, {r5, r7, r13}               @ address to jump to after
+        ldmia   r4, {r5, r7, r12}               @ address to jump to after
         sub     r4, r4, r5                      @ mmu has been enabled
         ldr     r4, [r7, r4]                    @ get secondary_data.pgdir
-        adr     lr, __enable_mmu                @ return address
-        add     pc, r10, #PROCINFO_INITFUNC     @ initialise processor
-                                                @ (return control reg)
+        adr     lr, BSYM(__enable_mmu)          @ return address
+        mov     r13, r12                        @ __secondary_switched address
+ ARM(   add     pc, r10, #PROCINFO_INITFUNC     ) @ initialise processor
+                                                  @ (return control reg)
+ THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
+ THUMB( mov     pc, r12                         )
 ENDPROC(secondary_startup)
 
         /*
@@ -193,8 +198,8 @@ __turn_mmu_on:
         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
         mrc     p15, 0, r3, c0, c0, 0           @ read id reg
         mov     r3, r3
-        mov     r3, r3
-        mov     pc, r13
+        mov     r3, r13
+        mov     pc, r3
 ENDPROC(__turn_mmu_on)
 
 
@@ -235,7 +240,8 @@ __create_page_tables:
          * will be removed by paging_init().  We use our current program
          * counter to determine corresponding section base address.
          */
-        mov     r6, pc, lsr #20                 @ start of kernel section
+        mov     r6, pc
+        mov     r6, r6, lsr #20                 @ start of kernel section
         orr     r3, r7, r6, lsl #20             @ flags + kernel base
         str     r3, [r4, r6, lsl #2]            @ identity mapping
 
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index b7c3490eaa24..c9a8619f3856 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -86,7 +86,7 @@ int show_interrupts(struct seq_file *p, void *v)
 unlock:
                 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
         } else if (i == NR_IRQS) {
-#ifdef CONFIG_ARCH_ACORN
+#ifdef CONFIG_FIQ
                 show_fiq_list(p, v);
 #endif
 #ifdef CONFIG_SMP
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index bac03c81489d..f28c5e9c51ea 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -102,6 +102,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
                 unsigned long loc;
                 Elf32_Sym *sym;
                 s32 offset;
+                u32 upper, lower, sign, j1, j2;
 
                 offset = ELF32_R_SYM(rel->r_info);
                 if (offset < 0 || offset > (symsec->sh_size / sizeof(Elf32_Sym))) {
@@ -184,6 +185,58 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
                                         (offset & 0x0fff);
                         break;
 
+                case R_ARM_THM_CALL:
+                case R_ARM_THM_JUMP24:
+                        upper = *(u16 *)loc;
+                        lower = *(u16 *)(loc + 2);
+
+                        /*
+                         * 25 bit signed address range (Thumb-2 BL and B.W
+                         * instructions):
+                         *   S:I1:I2:imm10:imm11:0
+                         * where:
+                         *   S     = upper[10]   = offset[24]
+                         *   I1    = ~(J1 ^ S)   = offset[23]
+                         *   I2    = ~(J2 ^ S)   = offset[22]
+                         *   imm10 = upper[9:0]  = offset[21:12]
+                         *   imm11 = lower[10:0] = offset[11:1]
+                         *   J1    = lower[13]
+                         *   J2    = lower[11]
+                         */
+                        sign = (upper >> 10) & 1;
+                        j1 = (lower >> 13) & 1;
+                        j2 = (lower >> 11) & 1;
+                        offset = (sign << 24) | ((~(j1 ^ sign) & 1) << 23) |
+                                ((~(j2 ^ sign) & 1) << 22) |
+                                ((upper & 0x03ff) << 12) |
+                                ((lower & 0x07ff) << 1);
+                        if (offset & 0x01000000)
+                                offset -= 0x02000000;
+                        offset += sym->st_value - loc;
+
+                        /* only Thumb addresses allowed (no interworking) */
+                        if (!(offset & 1) ||
+                            offset <= (s32)0xff000000 ||
+                            offset >= (s32)0x01000000) {
+                                printk(KERN_ERR
+                                       "%s: relocation out of range, section "
+                                       "%d reloc %d sym '%s'\n", module->name,
+                                       relindex, i, strtab + sym->st_name);
+                                return -ENOEXEC;
+                        }
+
+                        sign = (offset >> 24) & 1;
+                        j1 = sign ^ (~(offset >> 23) & 1);
+                        j2 = sign ^ (~(offset >> 22) & 1);
+                        *(u16 *)loc = (u16)((upper & 0xf800) | (sign << 10) |
+                                            ((offset >> 12) & 0x03ff));
+                        *(u16 *)(loc + 2) = (u16)((lower & 0xd000) |
+                                                  (j1 << 13) | (j2 << 11) |
+                                                  ((offset >> 1) & 0x07ff));
+                        upper = *(u16 *)loc;
+                        lower = *(u16 *)(loc + 2);
+                        break;
+
                 default:
                         printk(KERN_ERR "%s: unknown relocation: %u\n",
                                module->name, ELF32_R_TYPE(rel->r_info));
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 39196dff478c..790fbee92ec5 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -388,7 +388,7 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
         regs.ARM_r2 = (unsigned long)fn;
         regs.ARM_r3 = (unsigned long)kernel_thread_exit;
         regs.ARM_pc = (unsigned long)kernel_thread_helper;
-        regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE;
+        regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE | PSR_ISETSTATE;
 
         return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
 }
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 89882a1d0187..a2ea3854cb3c 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -521,7 +521,13 @@ static int ptrace_read_user(struct task_struct *tsk, unsigned long off,
                 return -EIO;
 
         tmp = 0;
-        if (off < sizeof(struct pt_regs))
+        if (off == PT_TEXT_ADDR)
+                tmp = tsk->mm->start_code;
+        else if (off == PT_DATA_ADDR)
+                tmp = tsk->mm->start_data;
+        else if (off == PT_TEXT_END_ADDR)
+                tmp = tsk->mm->end_code;
+        else if (off < sizeof(struct pt_regs))
                 tmp = get_user_reg(tsk, off >> 2);
 
         return put_user(tmp, ret);
diff --git a/arch/arm/kernel/return_address.c b/arch/arm/kernel/return_address.c
new file mode 100644
index 000000000000..df246da4ceca
--- /dev/null
+++ b/arch/arm/kernel/return_address.c
@@ -0,0 +1,71 @@
+/*
+ * arch/arm/kernel/return_address.c
+ *
+ * Copyright (C) 2009 Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ * for Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/module.h>
+
+#if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND)
+#include <linux/sched.h>
+
+#include <asm/stacktrace.h>
+
+struct return_address_data {
+        unsigned int level;
+        void *addr;
+};
+
+static int save_return_addr(struct stackframe *frame, void *d)
+{
+        struct return_address_data *data = d;
+
+        if (!data->level) {
+                data->addr = (void *)frame->lr;
+
+                return 1;
+        } else {
+                --data->level;
+                return 0;
+        }
+}
+
+void *return_address(unsigned int level)
+{
+        struct return_address_data data;
+        struct stackframe frame;
+        register unsigned long current_sp asm ("sp");
+
+        data.level = level + 1;
+
+        frame.fp = (unsigned long)__builtin_frame_address(0);
+        frame.sp = current_sp;
+        frame.lr = (unsigned long)__builtin_return_address(0);
+        frame.pc = (unsigned long)return_address;
+
+        walk_stackframe(&frame, save_return_addr, &data);
+
+        if (!data.level)
+                return data.addr;
+        else
+                return NULL;
+}
+
+#else /* if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) */
+
+#if defined(CONFIG_ARM_UNWIND)
+#warning "TODO: return_address should use unwind tables"
+#endif
+
+void *return_address(unsigned int level)
+{
+        return NULL;
+}
+
+#endif /* if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) / else */
+
+EXPORT_SYMBOL_GPL(return_address);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index bc5e4128f9f3..d4d4f77c91b2 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -25,6 +25,7 @@
 #include <linux/smp.h>
 #include <linux/fs.h>
 
+#include <asm/unified.h>
 #include <asm/cpu.h>
 #include <asm/cputype.h>
 #include <asm/elf.h>
@@ -327,25 +328,38 @@ void cpu_init(void)
         }
 
         /*
+         * Define the placement constraint for the inline asm directive below.
+         * In Thumb-2, msr with an immediate value is not allowed.
+         */
+#ifdef CONFIG_THUMB2_KERNEL
+#define PLC     "r"
+#else
+#define PLC     "I"
+#endif
+
+        /*
          * setup stacks for re-entrant exception handlers
          */
         __asm__ (
         "msr    cpsr_c, %1\n\t"
-        "add    sp, %0, %2\n\t"
+        "add    r14, %0, %2\n\t"
+        "mov    sp, r14\n\t"
         "msr    cpsr_c, %3\n\t"
-        "add    sp, %0, %4\n\t"
+        "add    r14, %0, %4\n\t"
+        "mov    sp, r14\n\t"
         "msr    cpsr_c, %5\n\t"
-        "add    sp, %0, %6\n\t"
+        "add    r14, %0, %6\n\t"
+        "mov    sp, r14\n\t"
         "msr    cpsr_c, %7"
             :
             : "r" (stk),
-              "I" (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
+              PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
               "I" (offsetof(struct stack, irq[0])),
-              "I" (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
+              PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
               "I" (offsetof(struct stack, abt[0])),
-              "I" (PSR_F_BIT | PSR_I_BIT | UND_MODE),
+              PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
               "I" (offsetof(struct stack, und[0])),
-              "I" (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
+              PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
             : "r14");
 }
 
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index f6bc5d442782..1423a3419789 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -12,6 +12,7 @@
 #include <linux/personality.h>
 #include <linux/freezer.h>
 #include <linux/uaccess.h>
+#include <linux/tracehook.h>
 
 #include <asm/elf.h>
 #include <asm/cacheflush.h>
@@ -47,57 +48,22 @@ const unsigned long sigreturn_codes[7] = {
         MOV_R7_NR_RT_SIGRETURN, SWI_SYS_RT_SIGRETURN, SWI_THUMB_RT_SIGRETURN,
 };
 
-static int do_signal(sigset_t *oldset, struct pt_regs * regs, int syscall);
-
 /*
  * atomically swap in the new signal mask, and wait for a signal.
  */
-asmlinkage int sys_sigsuspend(int restart, unsigned long oldmask, old_sigset_t mask, struct pt_regs *regs)
+asmlinkage int sys_sigsuspend(int restart, unsigned long oldmask, old_sigset_t mask)
 {
-        sigset_t saveset;
-
         mask &= _BLOCKABLE;
         spin_lock_irq(&current->sighand->siglock);
-        saveset = current->blocked;
+        current->saved_sigmask = current->blocked;
         siginitset(&current->blocked, mask);
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
-        regs->ARM_r0 = -EINTR;
 
-        while (1) {
-                current->state = TASK_INTERRUPTIBLE;
-                schedule();
-                if (do_signal(&saveset, regs, 0))
-                        return regs->ARM_r0;
-        }
-}
-
-asmlinkage int
-sys_rt_sigsuspend(sigset_t __user *unewset, size_t sigsetsize, struct pt_regs *regs)
-{
-        sigset_t saveset, newset;
-
-        /* XXX: Don't preclude handling different sized sigset_t's. */
-        if (sigsetsize != sizeof(sigset_t))
-                return -EINVAL;
-
-        if (copy_from_user(&newset, unewset, sizeof(newset)))
-                return -EFAULT;
-        sigdelsetmask(&newset, ~_BLOCKABLE);
-
-        spin_lock_irq(&current->sighand->siglock);
-        saveset = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-        regs->ARM_r0 = -EINTR;
-
-        while (1) {
-                current->state = TASK_INTERRUPTIBLE;
-                schedule();
-                if (do_signal(&saveset, regs, 0))
-                        return regs->ARM_r0;
-        }
+        current->state = TASK_INTERRUPTIBLE;
+        schedule();
+        set_restore_sigmask();
+        return -ERESTARTNOHAND;
 }
 
 asmlinkage int 
@@ -545,7 +511,7 @@ static inline void setup_syscall_restart(struct pt_regs *regs)
 /*
  * OK, we're invoking a handler
  */     
-static void
+static int
 handle_signal(unsigned long sig, struct k_sigaction *ka,
               siginfo_t *info, sigset_t *oldset,
               struct pt_regs * regs, int syscall)
@@ -596,7 +562,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
 
         if (ret != 0) {
                 force_sigsegv(sig, tsk);
-                return;
+                return ret;
         }
 
         /*
@@ -610,6 +576,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
         recalc_sigpending();
         spin_unlock_irq(&tsk->sighand->siglock);
 
+        return 0;
 }
 
 /*
@@ -621,7 +588,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
  * the kernel can handle, and then we build all the user-level signal handling
  * stack-frames in one go after that.
  */
-static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
+static void do_signal(struct pt_regs *regs, int syscall)
 {
         struct k_sigaction ka;
         siginfo_t info;
@@ -634,7 +601,7 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
          * if so.
          */
         if (!user_mode(regs))
-                return 0;
+                return;
 
         if (try_to_freeze())
                 goto no_signal;
@@ -643,9 +610,24 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
 
         signr = get_signal_to_deliver(&info, &ka, regs, NULL);
         if (signr > 0) {
-                handle_signal(signr, &ka, &info, oldset, regs, syscall);
+                sigset_t *oldset;
+
+                if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                        oldset = &current->saved_sigmask;
+                else
+                        oldset = &current->blocked;
+                if (handle_signal(signr, &ka, &info, oldset, regs, syscall) == 0) {
+                        /*
+                         * A signal was successfully delivered; the saved
+                         * sigmask will have been stored in the signal frame,
+                         * and will be restored by sigreturn, so we can simply
+                         * clear the TIF_RESTORE_SIGMASK flag.
+                         */
+                        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                }
                 single_step_set(current);
-                return 1;
+                return;
         }
 
  no_signal:
@@ -697,14 +679,28 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
                     regs->ARM_r0 == -ERESTARTNOINTR) {
                         setup_syscall_restart(regs);
                 }
+
+                /* If there's no signal to deliver, we just put the saved sigmask
+                 * back.
+                 */
+                if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
+                        clear_thread_flag(TIF_RESTORE_SIGMASK);
+                        sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
+                }
         }
         single_step_set(current);
-        return 0;
 }
 
 asmlinkage void
 do_notify_resume(struct pt_regs *regs, unsigned int thread_flags, int syscall)
 {
         if (thread_flags & _TIF_SIGPENDING)
-                do_signal(&current->blocked, regs, syscall);
+                do_signal(regs, syscall);
+
+        if (thread_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
+        }
 }
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
index 9f444e5cc165..20b7411e47fd 100644
--- a/arch/arm/kernel/stacktrace.c
+++ b/arch/arm/kernel/stacktrace.c
@@ -21,7 +21,7 @@
  * Note that with framepointer enabled, even the leaf functions have the same
  * prologue and epilogue, therefore we can ignore the LR value in this case.
  */
-int unwind_frame(struct stackframe *frame)
+int notrace unwind_frame(struct stackframe *frame)
 {
         unsigned long high, low;
         unsigned long fp = frame->fp;
@@ -43,7 +43,7 @@ int unwind_frame(struct stackframe *frame)
 }
 #endif
 
-void walk_stackframe(struct stackframe *frame,
+void notrace walk_stackframe(struct stackframe *frame,
                      int (*fn)(struct stackframe *, void *), void *data)
 {
         while (1) {
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index dd56e11f339a..39baf1128bfa 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -62,7 +62,11 @@ struct unwind_ctrl_block {
 };
 
 enum regs {
+#ifdef CONFIG_THUMB2_KERNEL
+        FP = 7,
+#else
         FP = 11,
+#endif
         SP = 13,
         LR = 14,
         PC = 15
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 69371028a202..5cc4812c9763 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -83,6 +83,7 @@ SECTIONS
                 EXIT_TEXT
                 EXIT_DATA
                 *(.exitcall.exit)
+                *(.discard)
                 *(.ARM.exidx.exit.text)
                 *(.ARM.extab.exit.text)
 #ifndef CONFIG_HOTPLUG_CPU
diff --git a/arch/arm/lib/ashldi3.S b/arch/arm/lib/ashldi3.S
index 1154d924080b..638deb13da1c 100644
--- a/arch/arm/lib/ashldi3.S
+++ b/arch/arm/lib/ashldi3.S
@@ -43,7 +43,9 @@ ENTRY(__aeabi_llsl)
         rsb     ip, r2, #32
         movmi   ah, ah, lsl r2
         movpl   ah, al, lsl r3
-        orrmi   ah, ah, al, lsr ip
+ ARM(   orrmi   ah, ah, al, lsr ip      )
+ THUMB( lsrmi   r3, al, ip              )
+ THUMB( orrmi   ah, ah, r3              )
         mov     al, al, lsl r2
         mov     pc, lr
 
diff --git a/arch/arm/lib/ashrdi3.S b/arch/arm/lib/ashrdi3.S
index 9f8b35572f8c..015e8aa5a1d1 100644
--- a/arch/arm/lib/ashrdi3.S
+++ b/arch/arm/lib/ashrdi3.S
@@ -43,7 +43,9 @@ ENTRY(__aeabi_lasr)
         rsb     ip, r2, #32
         movmi   al, al, lsr r2
         movpl   al, ah, asr r3
-        orrmi   al, al, ah, lsl ip
+ ARM(   orrmi   al, al, ah, lsl ip      )
+ THUMB( lslmi   r3, ah, ip              )
+ THUMB( orrmi   al, al, r3              )
         mov     ah, ah, asr r2
         mov     pc, lr
 
diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S
index b0951d0e8b2c..aaf7220d9e30 100644
--- a/arch/arm/lib/backtrace.S
+++ b/arch/arm/lib/backtrace.S
@@ -38,7 +38,9 @@ ENDPROC(c_backtrace)
                 beq     no_frame                @ we have no stack frames
 
                 tst     r1, #0x10               @ 26 or 32-bit mode?
-                moveq   mask, #0xfc000003       @ mask for 26-bit
+ ARM(           moveq   mask, #0xfc000003       )
+ THUMB(         moveq   mask, #0xfc000000       )
+ THUMB(         orreq   mask, #0x03             )
                 movne   mask, #0                @ mask for 32-bit
 
 1:              stmfd   sp!, {pc}               @ calculate offset of PC stored
@@ -126,7 +128,9 @@ ENDPROC(c_backtrace)
                 mov     reg, #10
                 mov     r7, #0
 1:              mov     r3, #1
-                tst     instr, r3, lsl reg
+ ARM(           tst     instr, r3, lsl reg      )
+ THUMB(         lsl     r3, reg                 )
+ THUMB(         tst     instr, r3               )
                 beq     2f
                 add     r7, r7, #1
                 teq     r7, #6
diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
index c7f2627385e7..d42252918bfb 100644
--- a/arch/arm/lib/bitops.h
+++ b/arch/arm/lib/bitops.h
@@ -60,8 +60,8 @@
         tst     r2, r0, lsl r3
         \instr  r2, r2, r0, lsl r3
         \store  r2, [r1]
-        restore_irqs ip
         moveq   r0, #0
+        restore_irqs ip
         mov     pc, lr
         .endm
 #endif
diff --git a/arch/arm/lib/clear_user.S b/arch/arm/lib/clear_user.S
index 844f56785ebc..1279abd8b886 100644
--- a/arch/arm/lib/clear_user.S
+++ b/arch/arm/lib/clear_user.S
@@ -27,21 +27,20 @@ WEAK(__clear_user)
                 ands    ip, r0, #3
                 beq     1f
                 cmp     ip, #2
-USER(           strbt   r2, [r0], #1)
-USER(           strlebt r2, [r0], #1)
-USER(           strltbt r2, [r0], #1)
+                strusr  r2, r0, 1
+                strusr  r2, r0, 1, le
+                strusr  r2, r0, 1, lt
                 rsb     ip, ip, #4
                 sub     r1, r1, ip              @  7  6  5  4  3  2  1
 1:              subs    r1, r1, #8              @ -1 -2 -3 -4 -5 -6 -7
-USER(           strplt  r2, [r0], #4)
-USER(           strplt  r2, [r0], #4)
+                strusr  r2, r0, 4, pl, rept=2
                 bpl     1b
                 adds    r1, r1, #4              @  3  2  1  0 -1 -2 -3
-USER(           strplt  r2, [r0], #4)
+                strusr  r2, r0, 4, pl
 2:              tst     r1, #2                  @ 1x 1x 0x 0x 1x 1x 0x
-USER(           strnebt r2, [r0], #1)
-USER(           strnebt r2, [r0], #1)
+                strusr  r2, r0, 1, ne, rept=2
                 tst     r1, #1                  @ x1 x0 x1 x0 x1 x0 x1
+                it      ne                      @ explicit IT needed for the label
 USER(           strnebt r2, [r0])
                 mov     r0, #0
                 ldmfd   sp!, {r1, pc}
diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S
index 56799a165cc4..e4fe124acedc 100644
--- a/arch/arm/lib/copy_from_user.S
+++ b/arch/arm/lib/copy_from_user.S
@@ -33,11 +33,15 @@
  *      Number of bytes NOT copied.
  */
 
+#ifndef CONFIG_THUMB2_KERNEL
+#define LDR1W_SHIFT     0
+#else
+#define LDR1W_SHIFT     1
+#endif
+#define STR1W_SHIFT     0
+
         .macro ldr1w ptr reg abort
-100:    ldrt \reg, [\ptr], #4
-        .section __ex_table, "a"
-        .long 100b, \abort
-        .previous
+        ldrusr  \reg, \ptr, 4, abort=\abort
         .endm
 
         .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
@@ -53,14 +57,11 @@
         .endm
 
         .macro ldr1b ptr reg cond=al abort
-100:    ldr\cond\()bt \reg, [\ptr], #1
-        .section __ex_table, "a"
-        .long 100b, \abort
-        .previous
+        ldrusr  \reg, \ptr, 1, \cond, abort=\abort
         .endm
 
         .macro str1w ptr reg abort
-        str \reg, [\ptr], #4
+        W(str) \reg, [\ptr], #4
         .endm
 
         .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index 139cce646055..805e3f8fb007 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -57,6 +57,13 @@
  *
  *      Restore registers with the values previously saved with the
  *      'preserv' macro. Called upon code termination.
+ *
+ * LDR1W_SHIFT
+ * STR1W_SHIFT
+ *
+ *      Correction to be applied to the "ip" register when branching into
+ *      the ldr1w or str1w instructions (some of these macros may expand to
+ *      than one 32bit instruction in Thumb-2)
  */
 
 
@@ -99,9 +106,15 @@
 
 5:              ands    ip, r2, #28
                 rsb     ip, ip, #32
+#if LDR1W_SHIFT > 0
+                lsl     ip, ip, #LDR1W_SHIFT
+#endif
                 addne   pc, pc, ip              @ C is always clear here
                 b       7f
-6:              nop
+6:
+                .rept   (1 << LDR1W_SHIFT)
+                W(nop)
+                .endr
                 ldr1w   r1, r3, abort=20f
                 ldr1w   r1, r4, abort=20f
                 ldr1w   r1, r5, abort=20f
@@ -110,9 +123,16 @@
                 ldr1w   r1, r8, abort=20f
                 ldr1w   r1, lr, abort=20f
 
+#if LDR1W_SHIFT < STR1W_SHIFT
+                lsl     ip, ip, #STR1W_SHIFT - LDR1W_SHIFT
+#elif LDR1W_SHIFT > STR1W_SHIFT
+                lsr     ip, ip, #LDR1W_SHIFT - STR1W_SHIFT
+#endif
                 add     pc, pc, ip
                 nop
-                nop
+                .rept   (1 << STR1W_SHIFT)
+                W(nop)
+                .endr
                 str1w   r0, r3, abort=20f
                 str1w   r0, r4, abort=20f
                 str1w   r0, r5, abort=20f
diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
index 878820f0a320..1a71e1584442 100644
--- a/arch/arm/lib/copy_to_user.S
+++ b/arch/arm/lib/copy_to_user.S
@@ -33,8 +33,15 @@
  *      Number of bytes NOT copied.
  */
 
+#define LDR1W_SHIFT     0
+#ifndef CONFIG_THUMB2_KERNEL
+#define STR1W_SHIFT     0
+#else
+#define STR1W_SHIFT     1
+#endif
+
         .macro ldr1w ptr reg abort
-        ldr \reg, [\ptr], #4
+        W(ldr) \reg, [\ptr], #4
         .endm
 
         .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
@@ -50,10 +57,7 @@
         .endm
 
         .macro str1w ptr reg abort
-100:    strt \reg, [\ptr], #4
-        .section __ex_table, "a"
-        .long 100b, \abort
-        .previous
+        strusr  \reg, \ptr, 4, abort=\abort
         .endm
 
         .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
@@ -68,10 +72,7 @@
         .endm
 
         .macro str1b ptr reg cond=al abort
-100:    str\cond\()bt \reg, [\ptr], #1
-        .section __ex_table, "a"
-        .long 100b, \abort
-        .previous
+        strusr  \reg, \ptr, 1, \cond, abort=\abort
         .endm
 
         .macro enter reg1 reg2
diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S
index 14677fb4b0c4..fd0e9dcd9fdc 100644
--- a/arch/arm/lib/csumpartialcopyuser.S
+++ b/arch/arm/lib/csumpartialcopyuser.S
@@ -26,50 +26,28 @@
                 .endm
 
                 .macro  load1b, reg1
-9999:           ldrbt   \reg1, [r0], $1
-                .section __ex_table, "a"
-                .align  3
-                .long   9999b, 6001f
-                .previous
+                ldrusr  \reg1, r0, 1
                 .endm
 
                 .macro  load2b, reg1, reg2
-9999:           ldrbt   \reg1, [r0], $1
-9998:           ldrbt   \reg2, [r0], $1
-                .section __ex_table, "a"
-                .long   9999b, 6001f
-                .long   9998b, 6001f
-                .previous
+                ldrusr  \reg1, r0, 1
+                ldrusr  \reg2, r0, 1
                 .endm
 
                 .macro  load1l, reg1
-9999:           ldrt    \reg1, [r0], $4
-                .section __ex_table, "a"
-                .align  3
-                .long   9999b, 6001f
-                .previous
+                ldrusr  \reg1, r0, 4
                 .endm
 
                 .macro  load2l, reg1, reg2
-9999:           ldrt    \reg1, [r0], $4
-9998:           ldrt    \reg2, [r0], $4
-                .section __ex_table, "a"
-                .long   9999b, 6001f
-                .long   9998b, 6001f
-                .previous
+                ldrusr  \reg1, r0, 4
+                ldrusr  \reg2, r0, 4
                 .endm
 
                 .macro  load4l, reg1, reg2, reg3, reg4
-9999:           ldrt    \reg1, [r0], $4
-9998:           ldrt    \reg2, [r0], $4
-9997:           ldrt    \reg3, [r0], $4
-9996:           ldrt    \reg4, [r0], $4
-                .section __ex_table, "a"
-                .long   9999b, 6001f
-                .long   9998b, 6001f
-                .long   9997b, 6001f
-                .long   9996b, 6001f
-                .previous
+                ldrusr  \reg1, r0, 4
+                ldrusr  \reg2, r0, 4
+                ldrusr  \reg3, r0, 4
+                ldrusr  \reg4, r0, 4
                 .endm
 
 /*
@@ -92,14 +70,14 @@
  */
                 .section .fixup,"ax"
                 .align  4
-6001:           mov     r4, #-EFAULT
+9001:           mov     r4, #-EFAULT
                 ldr     r5, [fp, #4]            @ *err_ptr
                 str     r4, [r5]
                 ldmia   sp, {r1, r2}            @ retrieve dst, len
                 add     r2, r2, r1
                 mov     r0, #0                  @ zero the buffer
-6002:           teq     r2, r1
+9002:           teq     r2, r1
                 strneb  r0, [r1], #1
-                bne     6002b
+                bne     9002b
                 load_regs
                 .previous
diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
index 1425e789ba86..faa7748142da 100644
--- a/arch/arm/lib/div64.S
+++ b/arch/arm/lib/div64.S
@@ -177,7 +177,9 @@ ENTRY(__do_div64)
         mov     yh, xh, lsr ip
         mov     yl, xl, lsr ip
         rsb     ip, ip, #32
-        orr     yl, yl, xh, lsl ip
+ ARM(   orr     yl, yl, xh, lsl ip      )
+ THUMB( lsl     xh, xh, ip              )
+ THUMB( orr     yl, yl, xh              )
         mov     xh, xl, lsl ip
         mov     xh, xh, lsr ip
         mov     pc, lr
diff --git a/arch/arm/lib/findbit.S b/arch/arm/lib/findbit.S
index 8c4defc4f3c4..1e4cbd4e7be9 100644
--- a/arch/arm/lib/findbit.S
+++ b/arch/arm/lib/findbit.S
@@ -25,7 +25,10 @@ ENTRY(_find_first_zero_bit_le)
                 teq     r1, #0  
                 beq     3f
                 mov     r2, #0
-1:              ldrb    r3, [r0, r2, lsr #3]
+1:
+ ARM(           ldrb    r3, [r0, r2, lsr #3]    )
+ THUMB(         lsr     r3, r2, #3              )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 eors    r3, r3, #0xff           @ invert bits
                 bne     .L_found                @ any now set - found zero bit
                 add     r2, r2, #8              @ next bit pointer
@@ -44,7 +47,9 @@ ENTRY(_find_next_zero_bit_le)
                 beq     3b
                 ands    ip, r2, #7
                 beq     1b                      @ If new byte, goto old routine
-                ldrb    r3, [r0, r2, lsr #3]
+ ARM(           ldrb    r3, [r0, r2, lsr #3]    )
+ THUMB(         lsr     r3, r2, #3              )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 eor     r3, r3, #0xff           @ now looking for a 1 bit
                 movs    r3, r3, lsr ip          @ shift off unused bits
                 bne     .L_found
@@ -61,7 +66,10 @@ ENTRY(_find_first_bit_le)
                 teq     r1, #0  
                 beq     3f
                 mov     r2, #0
-1:              ldrb    r3, [r0, r2, lsr #3]
+1:
+ ARM(           ldrb    r3, [r0, r2, lsr #3]    )
+ THUMB(         lsr     r3, r2, #3              )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 movs    r3, r3
                 bne     .L_found                @ any now set - found zero bit
                 add     r2, r2, #8              @ next bit pointer
@@ -80,7 +88,9 @@ ENTRY(_find_next_bit_le)
                 beq     3b
                 ands    ip, r2, #7
                 beq     1b                      @ If new byte, goto old routine
-                ldrb    r3, [r0, r2, lsr #3]
+ ARM(           ldrb    r3, [r0, r2, lsr #3]    )
+ THUMB(         lsr     r3, r2, #3              )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 movs    r3, r3, lsr ip          @ shift off unused bits
                 bne     .L_found
                 orr     r2, r2, #7              @ if zero, then no bits here
@@ -95,7 +105,9 @@ ENTRY(_find_first_zero_bit_be)
                 beq     3f
                 mov     r2, #0
 1:              eor     r3, r2, #0x18           @ big endian byte ordering
-                ldrb    r3, [r0, r3, lsr #3]
+ ARM(           ldrb    r3, [r0, r3, lsr #3]    )
+ THUMB(         lsr     r3, #3                  )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 eors    r3, r3, #0xff           @ invert bits
                 bne     .L_found                @ any now set - found zero bit
                 add     r2, r2, #8              @ next bit pointer
@@ -111,7 +123,9 @@ ENTRY(_find_next_zero_bit_be)
                 ands    ip, r2, #7
                 beq     1b                      @ If new byte, goto old routine
                 eor     r3, r2, #0x18           @ big endian byte ordering
-                ldrb    r3, [r0, r3, lsr #3]
+ ARM(           ldrb    r3, [r0, r3, lsr #3]    )
+ THUMB(         lsr     r3, #3                  )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 eor     r3, r3, #0xff           @ now looking for a 1 bit
                 movs    r3, r3, lsr ip          @ shift off unused bits
                 bne     .L_found
@@ -125,7 +139,9 @@ ENTRY(_find_first_bit_be)
                 beq     3f
                 mov     r2, #0
 1:              eor     r3, r2, #0x18           @ big endian byte ordering
-                ldrb    r3, [r0, r3, lsr #3]
+ ARM(           ldrb    r3, [r0, r3, lsr #3]    )
+ THUMB(         lsr     r3, #3                  )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 movs    r3, r3
                 bne     .L_found                @ any now set - found zero bit
                 add     r2, r2, #8              @ next bit pointer
@@ -141,7 +157,9 @@ ENTRY(_find_next_bit_be)
                 ands    ip, r2, #7
                 beq     1b                      @ If new byte, goto old routine
                 eor     r3, r2, #0x18           @ big endian byte ordering
-                ldrb    r3, [r0, r3, lsr #3]
+ ARM(           ldrb    r3, [r0, r3, lsr #3]    )
+ THUMB(         lsr     r3, #3                  )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 movs    r3, r3, lsr ip          @ shift off unused bits
                 bne     .L_found
                 orr     r2, r2, #7              @ if zero, then no bits here
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index 6763088b7607..a1814d927122 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -36,8 +36,13 @@ ENTRY(__get_user_1)
 ENDPROC(__get_user_1)
 
 ENTRY(__get_user_2)
+#ifdef CONFIG_THUMB2_KERNEL
+2:      ldrbt   r2, [r0]
+3:      ldrbt   r3, [r0, #1]
+#else
 2:      ldrbt   r2, [r0], #1
 3:      ldrbt   r3, [r0]
+#endif
 #ifndef __ARMEB__
         orr     r2, r2, r3, lsl #8
 #else
diff --git a/arch/arm/lib/io-writesw-armv4.S b/arch/arm/lib/io-writesw-armv4.S
index d6585612c86b..ff4f71b579ee 100644
--- a/arch/arm/lib/io-writesw-armv4.S
+++ b/arch/arm/lib/io-writesw-armv4.S
@@ -75,7 +75,10 @@ ENTRY(__raw_writesw)
 #endif
 
 .Loutsw_noalign:
-                ldr     r3, [r1, -r3]!
+ ARM(           ldr     r3, [r1, -r3]!  )
+ THUMB(         rsb     r3, r3, #0      )
+ THUMB(         ldr     r3, [r1, r3]    )
+ THUMB(         sub     r1, r3          )
                 subcs   r2, r2, #1
                 bcs     2f
                 subs    r2, r2, #2
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index 67964bcfc854..6dc06487f3c3 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -1,7 +1,7 @@
 /*
  * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines
  *
- * Author: Nicolas Pitre <nico@cam.org>
+ * Author: Nicolas Pitre <nico@fluxnic.net>
  *   - contributed to gcc-3.4 on Sep 30, 2003
  *   - adapted for the Linux kernel on Oct 2, 2003
  */
diff --git a/arch/arm/lib/lshrdi3.S b/arch/arm/lib/lshrdi3.S
index 99ea338bf87c..f83d449141f7 100644
--- a/arch/arm/lib/lshrdi3.S
+++ b/arch/arm/lib/lshrdi3.S
@@ -43,7 +43,9 @@ ENTRY(__aeabi_llsr)
         rsb     ip, r2, #32
         movmi   al, al, lsr r2
         movpl   al, ah, lsr r3
-        orrmi   al, al, ah, lsl ip
+ ARM(   orrmi   al, al, ah, lsl ip      )
+ THUMB( lslmi   r3, ah, ip              )
+ THUMB( orrmi   al, al, r3              )
         mov     ah, ah, lsr r2
         mov     pc, lr
 
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index e0d002641d3f..a9b9e2287a09 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -13,8 +13,11 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
+#define LDR1W_SHIFT     0
+#define STR1W_SHIFT     0
+
         .macro ldr1w ptr reg abort
-        ldr \reg, [\ptr], #4
+        W(ldr) \reg, [\ptr], #4
         .endm
 
         .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
@@ -30,7 +33,7 @@
         .endm
 
         .macro str1w ptr reg abort
-        str \reg, [\ptr], #4
+        W(str) \reg, [\ptr], #4
         .endm
 
         .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
index 12549187088c..5025c863713d 100644
--- a/arch/arm/lib/memmove.S
+++ b/arch/arm/lib/memmove.S
@@ -75,24 +75,24 @@ ENTRY(memmove)
                 addne   pc, pc, ip              @ C is always clear here
                 b       7f
 6:              nop
-                ldr     r3, [r1, #-4]!
-                ldr     r4, [r1, #-4]!
-                ldr     r5, [r1, #-4]!
-                ldr     r6, [r1, #-4]!
-                ldr     r7, [r1, #-4]!
-                ldr     r8, [r1, #-4]!
-                ldr     lr, [r1, #-4]!
+                W(ldr)  r3, [r1, #-4]!
+                W(ldr)  r4, [r1, #-4]!
+                W(ldr)  r5, [r1, #-4]!
+                W(ldr)  r6, [r1, #-4]!
+                W(ldr)  r7, [r1, #-4]!
+                W(ldr)  r8, [r1, #-4]!
+                W(ldr)  lr, [r1, #-4]!
 
                 add     pc, pc, ip
                 nop
                 nop
-                str     r3, [r0, #-4]!
-                str     r4, [r0, #-4]!
-                str     r5, [r0, #-4]!
-                str     r6, [r0, #-4]!
-                str     r7, [r0, #-4]!
-                str     r8, [r0, #-4]!
-                str     lr, [r0, #-4]!
+                W(str)  r3, [r0, #-4]!
+                W(str)  r4, [r0, #-4]!
+                W(str)  r5, [r0, #-4]!
+                W(str)  r6, [r0, #-4]!
+                W(str)  r7, [r0, #-4]!
+                W(str)  r8, [r0, #-4]!
+                W(str)  lr, [r0, #-4]!
 
         CALGN(  bcs     2b                      )
 
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S
index 864f3c1c4f18..02fedbf07c0d 100644
--- a/arch/arm/lib/putuser.S
+++ b/arch/arm/lib/putuser.S
@@ -37,6 +37,15 @@ ENDPROC(__put_user_1)
 
 ENTRY(__put_user_2)
         mov     ip, r2, lsr #8
+#ifdef CONFIG_THUMB2_KERNEL
+#ifndef __ARMEB__
+2:      strbt   r2, [r0]
+3:      strbt   ip, [r0, #1]
+#else
+2:      strbt   ip, [r0]
+3:      strbt   r2, [r0, #1]
+#endif
+#else   /* !CONFIG_THUMB2_KERNEL */
 #ifndef __ARMEB__
 2:      strbt   r2, [r0], #1
 3:      strbt   ip, [r0]
@@ -44,6 +53,7 @@ ENTRY(__put_user_2)
 2:      strbt   ip, [r0], #1
 3:      strbt   r2, [r0]
 #endif
+#endif  /* CONFIG_THUMB2_KERNEL */
         mov     r0, #0
         mov     pc, lr
 ENDPROC(__put_user_2)
@@ -55,8 +65,13 @@ ENTRY(__put_user_4)
 ENDPROC(__put_user_4)
 
 ENTRY(__put_user_8)
+#ifdef CONFIG_THUMB2_KERNEL
+5:      strt    r2, [r0]
+6:      strt    r3, [r0, #4]
+#else
 5:      strt    r2, [r0], #4
 6:      strt    r3, [r0]
+#endif
         mov     r0, #0
         mov     pc, lr
 ENDPROC(__put_user_8)
diff --git a/arch/arm/lib/sha1.S b/arch/arm/lib/sha1.S
index a16fb208c841..eb0edb80d7b8 100644
--- a/arch/arm/lib/sha1.S
+++ b/arch/arm/lib/sha1.S
@@ -3,7 +3,7 @@
  *
  *  SHA transform optimized for ARM
  *
- *  Copyright:  (C) 2005 by Nicolas Pitre <nico@cam.org>
+ *  Copyright:  (C) 2005 by Nicolas Pitre <nico@fluxnic.net>
  *  Created:    September 17, 2005
  *
  *  This program is free software; you can redistribute it and/or modify
@@ -187,6 +187,7 @@ ENTRY(sha_transform)
 
 ENDPROC(sha_transform)
 
+        .align  2
 .L_sha_K:
         .word   0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6
 
@@ -195,6 +196,7 @@ ENDPROC(sha_transform)
  * void sha_init(__u32 *buf)
  */
 
+        .align  2
 .L_sha_initial_digest:
         .word   0x67452301, 0xefcdab89, 0x98badcfe, 0x10325476, 0xc3d2e1f0
 
diff --git a/arch/arm/lib/strncpy_from_user.S b/arch/arm/lib/strncpy_from_user.S
index 330373c26dd9..1c9814f346c6 100644
--- a/arch/arm/lib/strncpy_from_user.S
+++ b/arch/arm/lib/strncpy_from_user.S
@@ -23,7 +23,7 @@
 ENTRY(__strncpy_from_user)
         mov     ip, r1
 1:      subs    r2, r2, #1
-USER(   ldrplbt r3, [r1], #1)
+        ldrusr  r3, r1, 1, pl
         bmi     2f
         strb    r3, [r0], #1
         teq     r3, #0
diff --git a/arch/arm/lib/strnlen_user.S b/arch/arm/lib/strnlen_user.S
index 90bb9d020836..7855b2906659 100644
--- a/arch/arm/lib/strnlen_user.S
+++ b/arch/arm/lib/strnlen_user.S
@@ -23,7 +23,7 @@
 ENTRY(__strnlen_user)
         mov     r2, r0
 1:
-USER(   ldrbt   r3, [r0], #1)
+        ldrusr  r3, r0, 1
         teq     r3, #0
         beq     2f
         subs    r1, r1, #1
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 323b47f2b52f..a24d824c428b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -23,6 +23,12 @@ config ARCH_AT91SAM9261
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
 
+config ARCH_AT91SAM9G10
+        bool "AT91SAM9G10"
+        select CPU_ARM926T
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+
 config ARCH_AT91SAM9263
         bool "AT91SAM9263"
         select CPU_ARM926T
@@ -41,6 +47,12 @@ config ARCH_AT91SAM9G20
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
 
+config ARCH_AT91SAM9G45
+        bool "AT91SAM9G45"
+        select CPU_ARM926T
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+
 config ARCH_AT91CAP9
         bool "AT91CAP9"
         select CPU_ARM926T
@@ -144,6 +156,13 @@ config MACH_YL9200
         help
           Select this if you are using the ucDragon YL-9200 board.
 
+config MACH_CPUAT91
+        bool "Eukrea CPUAT91"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using the Eukrea Electromatique's
+          CPUAT91 board <http://www.eukrea.com/>.
+
 endif
 
 # ----------------------------------------------------------
@@ -205,6 +224,13 @@ config MACH_QIL_A9260
           Select this if you are using a Calao Systems QIL-A9260 Board.
           <http://www.calao-systems.com>
 
+config MACH_CPU9260
+        bool "Eukrea CPU9260 board"
+        depends on ARCH_AT91SAM9260
+        help
+          Select this if you are using a Eukrea Electromatique's
+          CPU9260 Board <http://www.eukrea.com/>
+
 endif
 
 # ----------------------------------------------------------
@@ -224,6 +250,21 @@ endif
 
 # ----------------------------------------------------------
 
+if ARCH_AT91SAM9G10
+
+comment "AT91SAM9G10 Board Type"
+
+config MACH_AT91SAM9G10EK
+        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
+        depends on ARCH_AT91SAM9G10
+        help
+          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
+
+endif
+
+# ----------------------------------------------------------
+
 if ARCH_AT91SAM9263
 
 comment "AT91SAM9263 Board Type"
@@ -276,6 +317,29 @@ config MACH_AT91SAM9G20EK
         help
           Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit.
 
+config MACH_CPU9G20
+        bool "Eukrea CPU9G20 board"
+        depends on ARCH_AT91SAM9G20
+        help
+          Select this if you are using a Eukrea Electromatique's
+          CPU9G20 Board <http://www.eukrea.com/>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9G45
+
+comment "AT91SAM9G45 Board Type"
+
+config MACH_AT91SAM9G45EKES
+        bool "Atmel AT91SAM9G45-EKES Evaluation Kit"
+        depends on ARCH_AT91SAM9G45
+        help
+          Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.
+          "ES" at the end of the name means that this board is an
+          Engineering Sample.
+
 endif
 
 # ----------------------------------------------------------
@@ -315,13 +379,13 @@ comment "AT91 Board Options"
 
 config MTD_AT91_DATAFLASH_CARD
         bool "Enable DataFlash Card support"
-        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK || MACH_NEOCORE926)
+        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK || MACH_NEOCORE926)
         help
           Enable support for the DataFlash card.
 
 config MTD_NAND_ATMEL_BUSWIDTH_16
         bool "Enable 16-bit data bus interface to NAND flash"
-        depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91CAP9ADK)
+        depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91SAM9G45EKES || MACH_AT91CAP9ADK)
         help
           On AT91SAM926x boards both types of NAND flash can be present
           (8 and 16 bit data bus width).
@@ -383,7 +447,7 @@ config AT91_EARLY_USART2
 
 config AT91_EARLY_USART3
         bool "USART3"
-        depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
+        depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20 || ARCH_AT91SAM9G45)
 
 config AT91_EARLY_USART4
         bool "USART4"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c69ff237fd14..a6ed015d82ed 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -13,9 +13,11 @@ obj-$(CONFIG_AT91_PMC_UNIT)	+= clock.o
 obj-$(CONFIG_ARCH_AT91RM9200)   += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9260)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9261)  += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9G10)  += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9263)  += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9RL)   += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o  sam9_smc.o
+ obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91CAP9)     += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
 
@@ -32,6 +34,7 @@ obj-$(CONFIG_MACH_KAFA)		+= board-kafa.o
 obj-$(CONFIG_MACH_PICOTUX2XX)   += board-picotux200.o
 obj-$(CONFIG_MACH_ECBAT91)      += board-ecbat91.o
 obj-$(CONFIG_MACH_YL9200)       += board-yl-9200.o
+obj-$(CONFIG_MACH_CPUAT91)      += board-cpuat91.o
 
 # AT91SAM9260 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
@@ -40,9 +43,11 @@ obj-$(CONFIG_MACH_SAM9_L9260)	+= board-sam9-l9260.o
 obj-$(CONFIG_MACH_USB_A9260)    += board-usb-a9260.o
 obj-$(CONFIG_MACH_QIL_A9260)    += board-qil-a9260.o
 obj-$(CONFIG_MACH_AFEB9260)     += board-afeb-9260v1.o
+obj-$(CONFIG_MACH_CPU9260)      += board-cpu9krea.o
 
 # AT91SAM9261 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
+obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
 
 # AT91SAM9263 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
@@ -54,6 +59,10 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK)	+= board-sam9rlek.o
 
 # AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
+obj-$(CONFIG_MACH_CPU9G20)      += board-cpu9krea.o
+
+# AT91SAM9G45 board-specific support
+obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
 
 # AT91CAP9 board-specific support
 obj-$(CONFIG_MACH_AT91CAP9ADK)  += board-cap9adk.o
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 071a2506a69f..3462b815054a 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -7,6 +7,10 @@ ifeq ($(CONFIG_ARCH_AT91CAP9),y)
    zreladdr-y   := 0x70008000
 params_phys-y   := 0x70000100
 initrd_phys-y   := 0x70410000
+else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
+   zreladdr-y   := 0x70008000
+params_phys-y   := 0x70000100
+initrd_phys-y   := 0x70410000
 else
    zreladdr-y   := 0x20008000
 params_phys-y   := 0x20000100
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index d74c9ac007e7..ee4ea0e720cf 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -1113,6 +1113,122 @@ void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
 #endif
 
+/* --------------------------------------------------------------------
+ *  CF/IDE
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) || \
+        defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
+        defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
+
+static struct at91_cf_data cf0_data;
+
+static struct resource cf0_resources[] = {
+        [0] = {
+                .start  = AT91_CHIPSELECT_4,
+                .end    = AT91_CHIPSELECT_4 + SZ_256M - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device cf0_device = {
+        .id             = 0,
+        .dev            = {
+                                .platform_data  = &cf0_data,
+        },
+        .resource       = cf0_resources,
+        .num_resources  = ARRAY_SIZE(cf0_resources),
+};
+
+static struct at91_cf_data cf1_data;
+
+static struct resource cf1_resources[] = {
+        [0] = {
+                .start  = AT91_CHIPSELECT_5,
+                .end    = AT91_CHIPSELECT_5 + SZ_256M - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device cf1_device = {
+        .id             = 1,
+        .dev            = {
+                                .platform_data  = &cf1_data,
+        },
+        .resource       = cf1_resources,
+        .num_resources  = ARRAY_SIZE(cf1_resources),
+};
+
+void __init at91_add_device_cf(struct at91_cf_data *data)
+{
+        struct platform_device *pdev;
+        unsigned long csa;
+
+        if (!data)
+                return;
+
+        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+
+        switch (data->chipselect) {
+        case 4:
+                at91_set_multi_drive(AT91_PIN_PC8, 0);
+                at91_set_A_periph(AT91_PIN_PC8, 0);
+                csa |= AT91_MATRIX_CS4A_SMC_CF1;
+                cf0_data = *data;
+                pdev = &cf0_device;
+                break;
+        case 5:
+                at91_set_multi_drive(AT91_PIN_PC9, 0);
+                at91_set_A_periph(AT91_PIN_PC9, 0);
+                csa |= AT91_MATRIX_CS5A_SMC_CF2;
+                cf1_data = *data;
+                pdev = &cf1_device;
+                break;
+        default:
+                printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
+                       data->chipselect);
+                return;
+        }
+
+        at91_sys_write(AT91_MATRIX_EBICSA, csa);
+
+        if (data->rst_pin) {
+                at91_set_multi_drive(data->rst_pin, 0);
+                at91_set_gpio_output(data->rst_pin, 1);
+        }
+
+        if (data->irq_pin) {
+                at91_set_gpio_input(data->irq_pin, 0);
+                at91_set_deglitch(data->irq_pin, 1);
+        }
+
+        if (data->det_pin) {
+                at91_set_gpio_input(data->det_pin, 0);
+                at91_set_deglitch(data->det_pin, 1);
+        }
+
+        at91_set_B_periph(AT91_PIN_PC6, 0);     /* CFCE1 */
+        at91_set_B_periph(AT91_PIN_PC7, 0);     /* CFCE2 */
+        at91_set_A_periph(AT91_PIN_PC10, 0);    /* CFRNW */
+        at91_set_A_periph(AT91_PIN_PC15, 1);    /* NWAIT */
+
+        if (data->flags & AT91_CF_TRUE_IDE)
+#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE)
+                pdev->name = "pata_at91";
+#elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
+                pdev->name = "at91_ide";
+#else
+#warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91"
+#endif
+        else
+                pdev->name = "at91_cf";
+
+        platform_device_register(pdev);
+}
+
+#else
+void __init at91_add_device_cf(struct at91_cf_data * data) {}
+#endif
 
 /* -------------------------------------------------------------------- */
 /*
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 3acd7d7e6a42..4ecf37996c77 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -16,6 +16,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <mach/cpu.h>
 #include <mach/at91sam9261.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
@@ -30,7 +31,11 @@ static struct map_desc at91sam9261_io_desc[] __initdata = {
                 .pfn            = __phys_to_pfn(AT91_BASE_SYS),
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
-        }, {
+        },
+};
+
+static struct map_desc at91sam9261_sram_desc[] __initdata = {
+        {
                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
                 .pfn            = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
                 .length         = AT91SAM9261_SRAM_SIZE,
@@ -38,6 +43,15 @@ static struct map_desc at91sam9261_io_desc[] __initdata = {
         },
 };
 
+static struct map_desc at91sam9g10_sram_desc[] __initdata = {
+        {
+                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G10_SRAM_SIZE,
+                .pfn            = __phys_to_pfn(AT91SAM9G10_SRAM_BASE),
+                .length         = AT91SAM9G10_SRAM_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
 /* --------------------------------------------------------------------
  *  Clocks
  * -------------------------------------------------------------------- */
@@ -263,6 +277,12 @@ void __init at91sam9261_initialize(unsigned long main_clock)
         /* Map peripherals */
         iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
 
+        if (cpu_is_at91sam9g10())
+                iotable_init(at91sam9g10_sram_desc, ARRAY_SIZE(at91sam9g10_sram_desc));
+        else
+                iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc));
+
+
         at91_arch_reset = at91sam9261_reset;
         pm_power_off = at91sam9261_poweroff;
         at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index b7f233242315..55719a974276 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -707,9 +707,9 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
  *  AC97
  * -------------------------------------------------------------------- */
 
-#if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE)
+#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
 static u64 ac97_dmamask = DMA_BIT_MASK(32);
-static struct atmel_ac97_data ac97_data;
+static struct ac97c_platform_data ac97_data;
 
 static struct resource ac97_resources[] = {
         [0] = {
@@ -725,8 +725,8 @@ static struct resource ac97_resources[] = {
 };
 
 static struct platform_device at91sam9263_ac97_device = {
-        .name           = "ac97c",
-        .id             = 1,
+        .name           = "atmel_ac97c",
+        .id             = 0,
         .dev            = {
                                 .dma_mask               = &ac97_dmamask,
                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
@@ -736,7 +736,7 @@ static struct platform_device at91sam9263_ac97_device = {
         .num_resources  = ARRAY_SIZE(ac97_resources),
 };
 
-void __init at91_add_device_ac97(struct atmel_ac97_data *data)
+void __init at91_add_device_ac97(struct ac97c_platform_data *data)
 {
         if (!data)
                 return;
@@ -750,11 +750,11 @@ void __init at91_add_device_ac97(struct atmel_ac97_data *data)
         if (data->reset_pin)
                 at91_set_gpio_output(data->reset_pin, 0);
 
-        ac97_data = *ek_data;
+        ac97_data = *data;
         platform_device_register(&at91sam9263_ac97_device);
 }
 #else
-void __init at91_add_device_ac97(struct atmel_ac97_data *data) {}
+void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
 #endif
 
 
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
new file mode 100644
index 000000000000..85166b7e69a1
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -0,0 +1,360 @@
+/*
+ *  Chip-specific setup code for the AT91SAM9G45 family
+ *
+ *  Copyright (C) 2009 Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/pm.h>
+
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/at91sam9g45.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_shdwc.h>
+
+#include "generic.h"
+#include "clock.h"
+
+static struct map_desc at91sam9g45_io_desc[] __initdata = {
+        {
+                .virtual        = AT91_VA_BASE_SYS,
+                .pfn            = __phys_to_pfn(AT91_BASE_SYS),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G45_SRAM_SIZE,
+                .pfn            = __phys_to_pfn(AT91SAM9G45_SRAM_BASE),
+                .length         = AT91SAM9G45_SRAM_SIZE,
+                .type           = MT_DEVICE,
+        }
+};
+
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioA_clk = {
+        .name           = "pioA_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_PIOA,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioB_clk = {
+        .name           = "pioB_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_PIOB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioC_clk = {
+        .name           = "pioC_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_PIOC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioDE_clk = {
+        .name           = "pioDE_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_PIODE,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+        .name           = "usart0_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_US0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+        .name           = "usart1_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_US1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+        .name           = "usart2_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_US2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart3_clk = {
+        .name           = "usart3_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_US3,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc0_clk = {
+        .name           = "mci0_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_MCI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi0_clk = {
+        .name           = "twi0_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_TWI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi1_clk = {
+        .name           = "twi1_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_TWI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+        .name           = "spi0_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_SPI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+        .name           = "spi1_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_SPI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc0_clk = {
+        .name           = "ssc0_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_SSC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc1_clk = {
+        .name           = "ssc1_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_SSC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tcb_clk = {
+        .name           = "tcb_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_TCB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pwm_clk = {
+        .name           = "pwm_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_PWMC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tsc_clk = {
+        .name           = "tsc_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_TSC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk dma_clk = {
+        .name           = "dma_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_DMA,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uhphs_clk = {
+        .name           = "uhphs_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_UHPHS,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk lcdc_clk = {
+        .name           = "lcdc_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_LCDC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ac97_clk = {
+        .name           = "ac97_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_AC97C,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk macb_clk = {
+        .name           = "macb_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_EMAC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk isi_clk = {
+        .name           = "isi_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_ISI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udphs_clk = {
+        .name           = "udphs_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_UDPHS,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc1_clk = {
+        .name           = "mci1_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_MCI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+
+/* One additional fake clock for ohci */
+static struct clk ohci_clk = {
+        .name           = "ohci_clk",
+        .pmc_mask       = 0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .parent         = &uhphs_clk,
+};
+
+static struct clk *periph_clocks[] __initdata = {
+        &pioA_clk,
+        &pioB_clk,
+        &pioC_clk,
+        &pioDE_clk,
+        &usart0_clk,
+        &usart1_clk,
+        &usart2_clk,
+        &usart3_clk,
+        &mmc0_clk,
+        &twi0_clk,
+        &twi1_clk,
+        &spi0_clk,
+        &spi1_clk,
+        &ssc0_clk,
+        &ssc1_clk,
+        &tcb_clk,
+        &pwm_clk,
+        &tsc_clk,
+        &dma_clk,
+        &uhphs_clk,
+        &lcdc_clk,
+        &ac97_clk,
+        &macb_clk,
+        &isi_clk,
+        &udphs_clk,
+        &mmc1_clk,
+        // irq0
+        &ohci_clk,
+};
+
+/*
+ * The two programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 0,
+};
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 1,
+};
+
+static void __init at91sam9g45_register_clocks(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+                clk_register(periph_clocks[i]);
+
+        clk_register(&pck0);
+        clk_register(&pck1);
+}
+
+/* --------------------------------------------------------------------
+ *  GPIO
+ * -------------------------------------------------------------------- */
+
+static struct at91_gpio_bank at91sam9g45_gpio[] = {
+        {
+                .id             = AT91SAM9G45_ID_PIOA,
+                .offset         = AT91_PIOA,
+                .clock          = &pioA_clk,
+        }, {
+                .id             = AT91SAM9G45_ID_PIOB,
+                .offset         = AT91_PIOB,
+                .clock          = &pioB_clk,
+        }, {
+                .id             = AT91SAM9G45_ID_PIOC,
+                .offset         = AT91_PIOC,
+                .clock          = &pioC_clk,
+        }, {
+                .id             = AT91SAM9G45_ID_PIODE,
+                .offset         = AT91_PIOD,
+                .clock          = &pioDE_clk,
+        }, {
+                .id             = AT91SAM9G45_ID_PIODE,
+                .offset         = AT91_PIOE,
+                .clock          = &pioDE_clk,
+        }
+};
+
+static void at91sam9g45_reset(void)
+{
+        at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
+}
+
+static void at91sam9g45_poweroff(void)
+{
+        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
+
+/* --------------------------------------------------------------------
+ *  AT91SAM9G45 processor initialization
+ * -------------------------------------------------------------------- */
+
+void __init at91sam9g45_initialize(unsigned long main_clock)
+{
+        /* Map peripherals */
+        iotable_init(at91sam9g45_io_desc, ARRAY_SIZE(at91sam9g45_io_desc));
+
+        at91_arch_reset = at91sam9g45_reset;
+        pm_power_off = at91sam9g45_poweroff;
+        at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
+
+        /* Init clock subsystem */
+        at91_clock_init(main_clock);
+
+        /* Register the processor-specific clocks */
+        at91sam9g45_register_clocks();
+
+        /* Register GPIO subsystem */
+        at91_gpio_init(at91sam9g45_gpio, 5);
+}
+
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
+        7,      /* Advanced Interrupt Controller (FIQ) */
+        7,      /* System Peripherals */
+        1,      /* Parallel IO Controller A */
+        1,      /* Parallel IO Controller B */
+        1,      /* Parallel IO Controller C */
+        1,      /* Parallel IO Controller D and E */
+        0,
+        5,      /* USART 0 */
+        5,      /* USART 1 */
+        5,      /* USART 2 */
+        5,      /* USART 3 */
+        0,      /* Multimedia Card Interface 0 */
+        6,      /* Two-Wire Interface 0 */
+        6,      /* Two-Wire Interface 1 */
+        5,      /* Serial Peripheral Interface 0 */
+        5,      /* Serial Peripheral Interface 1 */
+        4,      /* Serial Synchronous Controller 0 */
+        4,      /* Serial Synchronous Controller 1 */
+        0,      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+        0,      /* Pulse Width Modulation Controller */
+        0,      /* Touch Screen Controller */
+        0,      /* DMA Controller */
+        2,      /* USB Host High Speed port */
+        3,      /* LDC Controller */
+        5,      /* AC97 Controller */
+        3,      /* Ethernet */
+        0,      /* Image Sensor Interface */
+        2,      /* USB Device High speed port */
+        0,
+        0,      /* Multimedia Card Interface 1 */
+        0,
+        0,      /* Advanced Interrupt Controller (IRQ0) */
+};
+
+void __init at91sam9g45_init_interrupts(unsigned int priority[NR_AIC_IRQS])
+{
+        if (!priority)
+                priority = at91sam9g45_default_irq_priority;
+
+        /* Initialize the AIC interrupt controller */
+        at91_aic_init(priority);
+
+        /* Enable GPIO interrupts */
+        at91_gpio_irq_setup();
+}
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
new file mode 100644
index 000000000000..d746e8621bc2
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -0,0 +1,1230 @@
+/*
+ *  On-Chip devices setup code for the AT91SAM9G45 family
+ *
+ *  Copyright (C) 2009 Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/i2c-gpio.h>
+
+#include <linux/fb.h>
+#include <video/atmel_lcdc.h>
+
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9g45.h>
+#include <mach/at91sam9g45_matrix.h>
+#include <mach/at91sam9_smc.h>
+
+#include "generic.h"
+
+
+/* --------------------------------------------------------------------
+ *  USB Host (OHCI)
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static u64 ohci_dmamask = DMA_BIT_MASK(32);
+static struct at91_usbh_data usbh_ohci_data;
+
+static struct resource usbh_ohci_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_OHCI_BASE,
+                .end    = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_UHPHS,
+                .end    = AT91SAM9G45_ID_UHPHS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91_usbh_ohci_device = {
+        .name           = "at91_ohci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &ohci_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &usbh_ohci_data,
+        },
+        .resource       = usbh_ohci_resources,
+        .num_resources  = ARRAY_SIZE(usbh_ohci_resources),
+};
+
+void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
+{
+        int i;
+
+        if (!data)
+                return;
+
+        /* Enable VBus control for UHP ports */
+        for (i = 0; i < data->ports; i++) {
+                if (data->vbus_pin[i])
+                        at91_set_gpio_output(data->vbus_pin[i], 0);
+        }
+
+        usbh_ohci_data = *data;
+        platform_device_register(&at91_usbh_ohci_device);
+}
+#else
+void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  USB HS Device (Gadget)
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
+static struct resource usba_udc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_UDPHS_FIFO,
+                .end    = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_BASE_UDPHS,
+                .end    = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = AT91SAM9G45_ID_UDPHS,
+                .end    = AT91SAM9G45_ID_UDPHS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+#define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
+        [idx] = {                                               \
+                .name           = nam,                          \
+                .index          = idx,                          \
+                .fifo_size      = maxpkt,                       \
+                .nr_banks       = maxbk,                        \
+                .can_dma        = dma,                          \
+                .can_isoc       = isoc,                         \
+        }
+
+static struct usba_ep_data usba_udc_ep[] __initdata = {
+        EP("ep0", 0, 64, 1, 0, 0),
+        EP("ep1", 1, 1024, 2, 1, 1),
+        EP("ep2", 2, 1024, 2, 1, 1),
+        EP("ep3", 3, 1024, 3, 1, 0),
+        EP("ep4", 4, 1024, 3, 1, 0),
+        EP("ep5", 5, 1024, 3, 1, 1),
+        EP("ep6", 6, 1024, 3, 1, 1),
+};
+
+#undef EP
+
+/*
+ * pdata doesn't have room for any endpoints, so we need to
+ * append room for the ones we need right after it.
+ */
+static struct {
+        struct usba_platform_data pdata;
+        struct usba_ep_data ep[7];
+} usba_udc_data;
+
+static struct platform_device at91_usba_udc_device = {
+        .name           = "atmel_usba_udc",
+        .id             = -1,
+        .dev            = {
+                                .platform_data  = &usba_udc_data.pdata,
+        },
+        .resource       = usba_udc_resources,
+        .num_resources  = ARRAY_SIZE(usba_udc_resources),
+};
+
+void __init at91_add_device_usba(struct usba_platform_data *data)
+{
+        usba_udc_data.pdata.vbus_pin = -EINVAL;
+        usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
+        memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
+
+        if (data && data->vbus_pin > 0) {
+                at91_set_gpio_input(data->vbus_pin, 0);
+                at91_set_deglitch(data->vbus_pin, 1);
+                usba_udc_data.pdata.vbus_pin = data->vbus_pin;
+        }
+
+        /* Pullup pin is handled internally by USB device peripheral */
+
+        /* Clocks */
+        at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
+        at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
+
+        platform_device_register(&at91_usba_udc_device);
+}
+#else
+void __init at91_add_device_usba(struct usba_platform_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  Ethernet
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
+static u64 eth_dmamask = DMA_BIT_MASK(32);
+static struct at91_eth_data eth_data;
+
+static struct resource eth_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_EMAC,
+                .end    = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_EMAC,
+                .end    = AT91SAM9G45_ID_EMAC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_eth_device = {
+        .name           = "macb",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &eth_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &eth_data,
+        },
+        .resource       = eth_resources,
+        .num_resources  = ARRAY_SIZE(eth_resources),
+};
+
+void __init at91_add_device_eth(struct at91_eth_data *data)
+{
+        if (!data)
+                return;
+
+        if (data->phy_irq_pin) {
+                at91_set_gpio_input(data->phy_irq_pin, 0);
+                at91_set_deglitch(data->phy_irq_pin, 1);
+        }
+
+        /* Pins used for MII and RMII */
+        at91_set_A_periph(AT91_PIN_PA17, 0);    /* ETXCK_EREFCK */
+        at91_set_A_periph(AT91_PIN_PA15, 0);    /* ERXDV */
+        at91_set_A_periph(AT91_PIN_PA12, 0);    /* ERX0 */
+        at91_set_A_periph(AT91_PIN_PA13, 0);    /* ERX1 */
+        at91_set_A_periph(AT91_PIN_PA16, 0);    /* ERXER */
+        at91_set_A_periph(AT91_PIN_PA14, 0);    /* ETXEN */
+        at91_set_A_periph(AT91_PIN_PA10, 0);    /* ETX0 */
+        at91_set_A_periph(AT91_PIN_PA11, 0);    /* ETX1 */
+        at91_set_A_periph(AT91_PIN_PA19, 0);    /* EMDIO */
+        at91_set_A_periph(AT91_PIN_PA18, 0);    /* EMDC */
+
+        if (!data->is_rmii) {
+                at91_set_B_periph(AT91_PIN_PA29, 0);    /* ECRS */
+                at91_set_B_periph(AT91_PIN_PA30, 0);    /* ECOL */
+                at91_set_B_periph(AT91_PIN_PA8,  0);    /* ERX2 */
+                at91_set_B_periph(AT91_PIN_PA9,  0);    /* ERX3 */
+                at91_set_B_periph(AT91_PIN_PA28, 0);    /* ERXCK */
+                at91_set_B_periph(AT91_PIN_PA6,  0);    /* ETX2 */
+                at91_set_B_periph(AT91_PIN_PA7,  0);    /* ETX3 */
+                at91_set_B_periph(AT91_PIN_PA27, 0);    /* ETXER */
+        }
+
+        eth_data = *data;
+        platform_device_register(&at91sam9g45_eth_device);
+}
+#else
+void __init at91_add_device_eth(struct at91_eth_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  NAND / SmartMedia
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
+static struct atmel_nand_data nand_data;
+
+#define NAND_BASE       AT91_CHIPSELECT_3
+
+static struct resource nand_resources[] = {
+        [0] = {
+                .start  = NAND_BASE,
+                .end    = NAND_BASE + SZ_256M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_BASE_SYS + AT91_ECC,
+                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device at91sam9g45_nand_device = {
+        .name           = "atmel_nand",
+        .id             = -1,
+        .dev            = {
+                                .platform_data  = &nand_data,
+        },
+        .resource       = nand_resources,
+        .num_resources  = ARRAY_SIZE(nand_resources),
+};
+
+void __init at91_add_device_nand(struct atmel_nand_data *data)
+{
+        unsigned long csa;
+
+        if (!data)
+                return;
+
+        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+
+        /* enable pin */
+        if (data->enable_pin)
+                at91_set_gpio_output(data->enable_pin, 1);
+
+        /* ready/busy pin */
+        if (data->rdy_pin)
+                at91_set_gpio_input(data->rdy_pin, 1);
+
+        /* card detect pin */
+        if (data->det_pin)
+                at91_set_gpio_input(data->det_pin, 1);
+
+        nand_data = *data;
+        platform_device_register(&at91sam9g45_nand_device);
+}
+#else
+void __init at91_add_device_nand(struct atmel_nand_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  TWI (i2c)
+ * -------------------------------------------------------------------- */
+
+/*
+ * Prefer the GPIO code since the TWI controller isn't robust
+ * (gets overruns and underruns under load) and can only issue
+ * repeated STARTs in one scenario (the driver doesn't yet handle them).
+ */
+#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+static struct i2c_gpio_platform_data pdata_i2c0 = {
+        .sda_pin                = AT91_PIN_PA20,
+        .sda_is_open_drain      = 1,
+        .scl_pin                = AT91_PIN_PA21,
+        .scl_is_open_drain      = 1,
+        .udelay                 = 2,            /* ~100 kHz */
+};
+
+static struct platform_device at91sam9g45_twi0_device = {
+        .name                   = "i2c-gpio",
+        .id                     = 0,
+        .dev.platform_data      = &pdata_i2c0,
+};
+
+static struct i2c_gpio_platform_data pdata_i2c1 = {
+        .sda_pin                = AT91_PIN_PB10,
+        .sda_is_open_drain      = 1,
+        .scl_pin                = AT91_PIN_PB11,
+        .scl_is_open_drain      = 1,
+        .udelay                 = 2,            /* ~100 kHz */
+};
+
+static struct platform_device at91sam9g45_twi1_device = {
+        .name                   = "i2c-gpio",
+        .id                     = 1,
+        .dev.platform_data      = &pdata_i2c1,
+};
+
+void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
+{
+        i2c_register_board_info(i2c_id, devices, nr_devices);
+
+        if (i2c_id == 0) {
+                at91_set_GPIO_periph(AT91_PIN_PA20, 1);         /* TWD (SDA) */
+                at91_set_multi_drive(AT91_PIN_PA20, 1);
+
+                at91_set_GPIO_periph(AT91_PIN_PA21, 1);         /* TWCK (SCL) */
+                at91_set_multi_drive(AT91_PIN_PA21, 1);
+
+                platform_device_register(&at91sam9g45_twi0_device);
+        } else {
+                at91_set_GPIO_periph(AT91_PIN_PB10, 1);         /* TWD (SDA) */
+                at91_set_multi_drive(AT91_PIN_PB10, 1);
+
+                at91_set_GPIO_periph(AT91_PIN_PB11, 1);         /* TWCK (SCL) */
+                at91_set_multi_drive(AT91_PIN_PB11, 1);
+
+                platform_device_register(&at91sam9g45_twi1_device);
+        }
+}
+
+#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
+static struct resource twi0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_TWI0,
+                .end    = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_TWI0,
+                .end    = AT91SAM9G45_ID_TWI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_twi0_device = {
+        .name           = "at91_i2c",
+        .id             = 0,
+        .resource       = twi0_resources,
+        .num_resources  = ARRAY_SIZE(twi0_resources),
+};
+
+static struct resource twi1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_TWI1,
+                .end    = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_TWI1,
+                .end    = AT91SAM9G45_ID_TWI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_twi1_device = {
+        .name           = "at91_i2c",
+        .id             = 1,
+        .resource       = twi1_resources,
+        .num_resources  = ARRAY_SIZE(twi1_resources),
+};
+
+void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
+{
+        i2c_register_board_info(i2c_id, devices, nr_devices);
+
+        /* pins used for TWI interface */
+        if (i2c_id == 0) {
+                at91_set_A_periph(AT91_PIN_PA20, 0);            /* TWD */
+                at91_set_multi_drive(AT91_PIN_PA20, 1);
+
+                at91_set_A_periph(AT91_PIN_PA21, 0);            /* TWCK */
+                at91_set_multi_drive(AT91_PIN_PA21, 1);
+
+                platform_device_register(&at91sam9g45_twi0_device);
+        } else {
+                at91_set_A_periph(AT91_PIN_PB10, 0);            /* TWD */
+                at91_set_multi_drive(AT91_PIN_PB10, 1);
+
+                at91_set_A_periph(AT91_PIN_PB11, 0);            /* TWCK */
+                at91_set_multi_drive(AT91_PIN_PB11, 1);
+
+                platform_device_register(&at91sam9g45_twi1_device);
+        }
+}
+#else
+void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  SPI
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+static struct resource spi0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_SPI0,
+                .end    = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_SPI0,
+                .end    = AT91SAM9G45_ID_SPI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_spi0_device = {
+        .name           = "atmel_spi",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = spi0_resources,
+        .num_resources  = ARRAY_SIZE(spi0_resources),
+};
+
+static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
+
+static struct resource spi1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_SPI1,
+                .end    = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_SPI1,
+                .end    = AT91SAM9G45_ID_SPI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_spi1_device = {
+        .name           = "atmel_spi",
+        .id             = 1,
+        .dev            = {
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = spi1_resources,
+        .num_resources  = ARRAY_SIZE(spi1_resources),
+};
+
+static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
+
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
+{
+        int i;
+        unsigned long cs_pin;
+        short enable_spi0 = 0;
+        short enable_spi1 = 0;
+
+        /* Choose SPI chip-selects */
+        for (i = 0; i < nr_devices; i++) {
+                if (devices[i].controller_data)
+                        cs_pin = (unsigned long) devices[i].controller_data;
+                else if (devices[i].bus_num == 0)
+                        cs_pin = spi0_standard_cs[devices[i].chip_select];
+                else
+                        cs_pin = spi1_standard_cs[devices[i].chip_select];
+
+                if (devices[i].bus_num == 0)
+                        enable_spi0 = 1;
+                else
+                        enable_spi1 = 1;
+
+                /* enable chip-select pin */
+                at91_set_gpio_output(cs_pin, 1);
+
+                /* pass chip-select pin to driver */
+                devices[i].controller_data = (void *) cs_pin;
+        }
+
+        spi_register_board_info(devices, nr_devices);
+
+        /* Configure SPI bus(es) */
+        if (enable_spi0) {
+                at91_set_A_periph(AT91_PIN_PB0, 0);     /* SPI0_MISO */
+                at91_set_A_periph(AT91_PIN_PB1, 0);     /* SPI0_MOSI */
+                at91_set_A_periph(AT91_PIN_PB2, 0);     /* SPI0_SPCK */
+
+                at91_clock_associate("spi0_clk", &at91sam9g45_spi0_device.dev, "spi_clk");
+                platform_device_register(&at91sam9g45_spi0_device);
+        }
+        if (enable_spi1) {
+                at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_MISO */
+                at91_set_A_periph(AT91_PIN_PB15, 0);    /* SPI1_MOSI */
+                at91_set_A_periph(AT91_PIN_PB16, 0);    /* SPI1_SPCK */
+
+                at91_clock_associate("spi1_clk", &at91sam9g45_spi1_device.dev, "spi_clk");
+                platform_device_register(&at91sam9g45_spi1_device);
+        }
+}
+#else
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  LCD Controller
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
+static u64 lcdc_dmamask = DMA_BIT_MASK(32);
+static struct atmel_lcdfb_info lcdc_data;
+
+static struct resource lcdc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_LCDC_BASE,
+                .end    = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_LCDC,
+                .end    = AT91SAM9G45_ID_LCDC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91_lcdc_device = {
+        .name           = "atmel_lcdfb",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &lcdc_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &lcdc_data,
+        },
+        .resource       = lcdc_resources,
+        .num_resources  = ARRAY_SIZE(lcdc_resources),
+};
+
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
+{
+        if (!data)
+                return;
+
+        at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
+
+        at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
+        at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
+        at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
+        at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
+        at91_set_A_periph(AT91_PIN_PE6, 0);     /* LCDDEN */
+        at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
+        at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
+        at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
+        at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
+        at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
+        at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
+        at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
+        at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
+        at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
+        at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
+        at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
+        at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
+        at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
+        at91_set_A_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
+        at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
+        at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
+        at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
+        at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
+        at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
+        at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
+        at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
+        at91_set_A_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
+        at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
+        at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
+
+        lcdc_data = *data;
+        platform_device_register(&at91_lcdc_device);
+}
+#else
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+static struct resource tcb0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_TCB0,
+                .end    = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_TCB,
+                .end    = AT91SAM9G45_ID_TCB,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_tcb0_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb0_resources,
+        .num_resources  = ARRAY_SIZE(tcb0_resources),
+};
+
+/* TCB1 begins with TC3 */
+static struct resource tcb1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_TCB1,
+                .end    = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_TCB,
+                .end    = AT91SAM9G45_ID_TCB,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_tcb1_device = {
+        .name           = "atmel_tcb",
+        .id             = 1,
+        .resource       = tcb1_resources,
+        .num_resources  = ARRAY_SIZE(tcb1_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has one clock and irq for all six TC channels */
+        at91_clock_associate("tcb_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
+        platform_device_register(&at91sam9g45_tcb0_device);
+        at91_clock_associate("tcb_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
+        platform_device_register(&at91sam9g45_tcb1_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  RTC
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
+static struct platform_device at91sam9g45_rtc_device = {
+        .name           = "at91_rtc",
+        .id             = -1,
+        .num_resources  = 0,
+};
+
+static void __init at91_add_device_rtc(void)
+{
+        platform_device_register(&at91sam9g45_rtc_device);
+}
+#else
+static void __init at91_add_device_rtc(void) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  RTT
+ * -------------------------------------------------------------------- */
+
+static struct resource rtt_resources[] = {
+        {
+                .start  = AT91_BASE_SYS + AT91_RTT,
+                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device at91sam9g45_rtt_device = {
+        .name           = "at91_rtt",
+        .id             = 0,
+        .resource       = rtt_resources,
+        .num_resources  = ARRAY_SIZE(rtt_resources),
+};
+
+static void __init at91_add_device_rtt(void)
+{
+        platform_device_register(&at91sam9g45_rtt_device);
+}
+
+
+/* --------------------------------------------------------------------
+ *  Watchdog
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
+static struct platform_device at91sam9g45_wdt_device = {
+        .name           = "at91_wdt",
+        .id             = -1,
+        .num_resources  = 0,
+};
+
+static void __init at91_add_device_watchdog(void)
+{
+        platform_device_register(&at91sam9g45_wdt_device);
+}
+#else
+static void __init at91_add_device_watchdog(void) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  PWM
+ * --------------------------------------------------------------------*/
+
+#if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
+static u32 pwm_mask;
+
+static struct resource pwm_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_PWMC,
+                .end    = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_PWMC,
+                .end    = AT91SAM9G45_ID_PWMC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_pwm0_device = {
+        .name   = "atmel_pwm",
+        .id     = -1,
+        .dev    = {
+                .platform_data          = &pwm_mask,
+        },
+        .resource       = pwm_resources,
+        .num_resources  = ARRAY_SIZE(pwm_resources),
+};
+
+void __init at91_add_device_pwm(u32 mask)
+{
+        if (mask & (1 << AT91_PWM0))
+                at91_set_B_periph(AT91_PIN_PD24, 1);    /* enable PWM0 */
+
+        if (mask & (1 << AT91_PWM1))
+                at91_set_B_periph(AT91_PIN_PD31, 1);    /* enable PWM1 */
+
+        if (mask & (1 << AT91_PWM2))
+                at91_set_B_periph(AT91_PIN_PD26, 1);    /* enable PWM2 */
+
+        if (mask & (1 << AT91_PWM3))
+                at91_set_B_periph(AT91_PIN_PD0, 1);     /* enable PWM3 */
+
+        pwm_mask = mask;
+
+        platform_device_register(&at91sam9g45_pwm0_device);
+}
+#else
+void __init at91_add_device_pwm(u32 mask) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  SSC -- Synchronous Serial Controller
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
+static u64 ssc0_dmamask = DMA_BIT_MASK(32);
+
+static struct resource ssc0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_SSC0,
+                .end    = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_SSC0,
+                .end    = AT91SAM9G45_ID_SSC0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_ssc0_device = {
+        .name   = "ssc",
+        .id     = 0,
+        .dev    = {
+                .dma_mask               = &ssc0_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = ssc0_resources,
+        .num_resources  = ARRAY_SIZE(ssc0_resources),
+};
+
+static inline void configure_ssc0_pins(unsigned pins)
+{
+        if (pins & ATMEL_SSC_TF)
+                at91_set_A_periph(AT91_PIN_PD1, 1);
+        if (pins & ATMEL_SSC_TK)
+                at91_set_A_periph(AT91_PIN_PD0, 1);
+        if (pins & ATMEL_SSC_TD)
+                at91_set_A_periph(AT91_PIN_PD2, 1);
+        if (pins & ATMEL_SSC_RD)
+                at91_set_A_periph(AT91_PIN_PD3, 1);
+        if (pins & ATMEL_SSC_RK)
+                at91_set_A_periph(AT91_PIN_PD4, 1);
+        if (pins & ATMEL_SSC_RF)
+                at91_set_A_periph(AT91_PIN_PD5, 1);
+}
+
+static u64 ssc1_dmamask = DMA_BIT_MASK(32);
+
+static struct resource ssc1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_SSC1,
+                .end    = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_SSC1,
+                .end    = AT91SAM9G45_ID_SSC1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_ssc1_device = {
+        .name   = "ssc",
+        .id     = 1,
+        .dev    = {
+                .dma_mask               = &ssc1_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = ssc1_resources,
+        .num_resources  = ARRAY_SIZE(ssc1_resources),
+};
+
+static inline void configure_ssc1_pins(unsigned pins)
+{
+        if (pins & ATMEL_SSC_TF)
+                at91_set_A_periph(AT91_PIN_PD14, 1);
+        if (pins & ATMEL_SSC_TK)
+                at91_set_A_periph(AT91_PIN_PD12, 1);
+        if (pins & ATMEL_SSC_TD)
+                at91_set_A_periph(AT91_PIN_PD10, 1);
+        if (pins & ATMEL_SSC_RD)
+                at91_set_A_periph(AT91_PIN_PD11, 1);
+        if (pins & ATMEL_SSC_RK)
+                at91_set_A_periph(AT91_PIN_PD13, 1);
+        if (pins & ATMEL_SSC_RF)
+                at91_set_A_periph(AT91_PIN_PD15, 1);
+}
+
+/*
+ * SSC controllers are accessed through library code, instead of any
+ * kind of all-singing/all-dancing driver.  For example one could be
+ * used by a particular I2S audio codec's driver, while another one
+ * on the same system might be used by a custom data capture driver.
+ */
+void __init at91_add_device_ssc(unsigned id, unsigned pins)
+{
+        struct platform_device *pdev;
+
+        /*
+         * NOTE: caller is responsible for passing information matching
+         * "pins" to whatever will be using each particular controller.
+         */
+        switch (id) {
+        case AT91SAM9G45_ID_SSC0:
+                pdev = &at91sam9g45_ssc0_device;
+                configure_ssc0_pins(pins);
+                at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
+                break;
+        case AT91SAM9G45_ID_SSC1:
+                pdev = &at91sam9g45_ssc1_device;
+                configure_ssc1_pins(pins);
+                at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
+                break;
+        default:
+                return;
+        }
+
+        platform_device_register(pdev);
+}
+
+#else
+void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  UART
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_SERIAL_ATMEL)
+static struct resource dbgu_resources[] = {
+        [0] = {
+                .start  = AT91_VA_BASE_SYS + AT91_DBGU,
+                .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_ID_SYS,
+                .end    = AT91_ID_SYS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data dbgu_data = {
+        .use_dma_tx     = 0,
+        .use_dma_rx     = 0,
+        .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
+};
+
+static u64 dbgu_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at91sam9g45_dbgu_device = {
+        .name           = "atmel_usart",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &dbgu_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &dbgu_data,
+        },
+        .resource       = dbgu_resources,
+        .num_resources  = ARRAY_SIZE(dbgu_resources),
+};
+
+static inline void configure_dbgu_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PB12, 0);            /* DRXD */
+        at91_set_A_periph(AT91_PIN_PB13, 1);            /* DTXD */
+}
+
+static struct resource uart0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_US0,
+                .end    = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_US0,
+                .end    = AT91SAM9G45_ID_US0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart0_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static u64 uart0_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at91sam9g45_uart0_device = {
+        .name           = "atmel_usart",
+        .id             = 1,
+        .dev            = {
+                                .dma_mask               = &uart0_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart0_data,
+        },
+        .resource       = uart0_resources,
+        .num_resources  = ARRAY_SIZE(uart0_resources),
+};
+
+static inline void configure_usart0_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PB19, 1);            /* TXD0 */
+        at91_set_A_periph(AT91_PIN_PB18, 0);            /* RXD0 */
+
+        if (pins & ATMEL_UART_RTS)
+                at91_set_B_periph(AT91_PIN_PB17, 0);    /* RTS0 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_B_periph(AT91_PIN_PB15, 0);    /* CTS0 */
+}
+
+static struct resource uart1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_US1,
+                .end    = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_US1,
+                .end    = AT91SAM9G45_ID_US1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart1_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static u64 uart1_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at91sam9g45_uart1_device = {
+        .name           = "atmel_usart",
+        .id             = 2,
+        .dev            = {
+                                .dma_mask               = &uart1_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart1_data,
+        },
+        .resource       = uart1_resources,
+        .num_resources  = ARRAY_SIZE(uart1_resources),
+};
+
+static inline void configure_usart1_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PB4, 1);             /* TXD1 */
+        at91_set_A_periph(AT91_PIN_PB5, 0);             /* RXD1 */
+
+        if (pins & ATMEL_UART_RTS)
+                at91_set_A_periph(AT91_PIN_PD16, 0);    /* RTS1 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_A_periph(AT91_PIN_PD17, 0);    /* CTS1 */
+}
+
+static struct resource uart2_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_US2,
+                .end    = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_US2,
+                .end    = AT91SAM9G45_ID_US2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart2_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static u64 uart2_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at91sam9g45_uart2_device = {
+        .name           = "atmel_usart",
+        .id             = 3,
+        .dev            = {
+                                .dma_mask               = &uart2_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart2_data,
+        },
+        .resource       = uart2_resources,
+        .num_resources  = ARRAY_SIZE(uart2_resources),
+};
+
+static inline void configure_usart2_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PB6, 1);             /* TXD2 */
+        at91_set_A_periph(AT91_PIN_PB7, 0);             /* RXD2 */
+
+        if (pins & ATMEL_UART_RTS)
+                at91_set_B_periph(AT91_PIN_PC9, 0);     /* RTS2 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_B_periph(AT91_PIN_PC11, 0);    /* CTS2 */
+}
+
+static struct resource uart3_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_US3,
+                .end    = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_US3,
+                .end    = AT91SAM9G45_ID_US3,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart3_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static u64 uart3_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at91sam9g45_uart3_device = {
+        .name           = "atmel_usart",
+        .id             = 4,
+        .dev            = {
+                                .dma_mask               = &uart3_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart3_data,
+        },
+        .resource       = uart3_resources,
+        .num_resources  = ARRAY_SIZE(uart3_resources),
+};
+
+static inline void configure_usart3_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PB8, 1);             /* TXD3 */
+        at91_set_A_periph(AT91_PIN_PB9, 0);             /* RXD3 */
+
+        if (pins & ATMEL_UART_RTS)
+                at91_set_B_periph(AT91_PIN_PA23, 0);    /* RTS3 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_B_periph(AT91_PIN_PA24, 0);    /* CTS3 */
+}
+
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
+struct platform_device *atmel_default_console_device;   /* the serial console device */
+
+void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
+{
+        struct platform_device *pdev;
+
+        switch (id) {
+                case 0:         /* DBGU */
+                        pdev = &at91sam9g45_dbgu_device;
+                        configure_dbgu_pins();
+                        at91_clock_associate("mck", &pdev->dev, "usart");
+                        break;
+                case AT91SAM9G45_ID_US0:
+                        pdev = &at91sam9g45_uart0_device;
+                        configure_usart0_pins(pins);
+                        at91_clock_associate("usart0_clk", &pdev->dev, "usart");
+                        break;
+                case AT91SAM9G45_ID_US1:
+                        pdev = &at91sam9g45_uart1_device;
+                        configure_usart1_pins(pins);
+                        at91_clock_associate("usart1_clk", &pdev->dev, "usart");
+                        break;
+                case AT91SAM9G45_ID_US2:
+                        pdev = &at91sam9g45_uart2_device;
+                        configure_usart2_pins(pins);
+                        at91_clock_associate("usart2_clk", &pdev->dev, "usart");
+                        break;
+                case AT91SAM9G45_ID_US3:
+                        pdev = &at91sam9g45_uart3_device;
+                        configure_usart3_pins(pins);
+                        at91_clock_associate("usart3_clk", &pdev->dev, "usart");
+                        break;
+                default:
+                        return;
+        }
+        pdev->id = portnr;              /* update to mapped ID */
+
+        if (portnr < ATMEL_MAX_UART)
+                at91_uarts[portnr] = pdev;
+}
+
+void __init at91_set_serial_console(unsigned portnr)
+{
+        if (portnr < ATMEL_MAX_UART)
+                atmel_default_console_device = at91_uarts[portnr];
+}
+
+void __init at91_add_device_serial(void)
+{
+        int i;
+
+        for (i = 0; i < ATMEL_MAX_UART; i++) {
+                if (at91_uarts[i])
+                        platform_device_register(at91_uarts[i]);
+        }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
+}
+#else
+void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
+void __init at91_set_serial_console(unsigned portnr) {}
+void __init at91_add_device_serial(void) {}
+#endif
+
+
+/* -------------------------------------------------------------------- */
+/*
+ * These devices are always present and don't need any board-specific
+ * setup.
+ */
+static int __init at91_add_standard_devices(void)
+{
+        at91_add_device_rtc();
+        at91_add_device_rtt();
+        at91_add_device_watchdog();
+        at91_add_device_tc();
+        return 0;
+}
+
+arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 970fd6b6753e..61e52b66bc72 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -174,6 +174,16 @@ static struct i2c_board_info __initdata afeb9260_i2c_devices[] = {
         },
 };
 
+/*
+ * IDE (CF True IDE mode)
+ */
+static struct at91_cf_data afeb9260_cf_data = {
+        .chipselect = 4,
+        .irq_pin    = AT91_PIN_PA6,
+        .rst_pin    = AT91_PIN_PA7,
+        .flags      = AT91_CF_TRUE_IDE,
+};
+
 static void __init afeb9260_board_init(void)
 {
         /* Serial */
@@ -202,6 +212,8 @@ static void __init afeb9260_board_init(void)
                         ARRAY_SIZE(afeb9260_i2c_devices));
         /* Audio */
         at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
+        /* IDE */
+        at91_add_device_cf(&afeb9260_cf_data);
 }
 
 MACHINE_START(AFEB9260, "Custom afeb9260 board")
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
new file mode 100644
index 000000000000..4bc2e9f6ebb5
--- /dev/null
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -0,0 +1,385 @@
+/*
+ * linux/arch/arm/mach-at91/board-cpu9krea.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2006 Atmel
+ *  Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/mtd/physmap.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91sam9260_matrix.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+static void __init cpu9krea_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91sam9260_initialize(18432000);
+
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS |
+                ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
+                ATMEL_UART_DCD | ATMEL_UART_RI);
+
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS |
+                ATMEL_UART_RTS);
+
+        /* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS |
+                ATMEL_UART_RTS);
+
+        /* USART3 on ttyS4. (Rx, Tx) */
+        at91_register_uart(AT91SAM9260_ID_US3, 4, 0);
+
+        /* USART4 on ttyS5. (Rx, Tx) */
+        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
+
+        /* USART5 on ttyS6. (Rx, Tx) */
+        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init cpu9krea_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata cpu9krea_usbh_data = {
+        .ports          = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata cpu9krea_udc_data = {
+        .vbus_pin       = AT91_PIN_PC8,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata cpu9krea_macb_data = {
+        .is_rmii        = 1,
+};
+
+/*
+ * NAND flash
+ */
+static struct atmel_nand_data __initdata cpu9krea_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+        .rdy_pin        = AT91_PIN_PC13,
+        .enable_pin     = AT91_PIN_PC14,
+        .bus_width_16   = 0,
+};
+
+#ifdef CONFIG_MACH_CPU9260
+static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 1,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 1,
+
+        .ncs_read_pulse         = 3,
+        .nrd_pulse              = 3,
+        .ncs_write_pulse        = 3,
+        .nwe_pulse              = 3,
+
+        .read_cycle             = 5,
+        .write_cycle            = 5,
+
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
+                | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
+        .tdf_cycles             = 2,
+};
+#else
+static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 2,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 2,
+
+        .ncs_read_pulse         = 4,
+        .nrd_pulse              = 4,
+        .ncs_write_pulse        = 4,
+        .nwe_pulse              = 4,
+
+        .read_cycle             = 7,
+        .write_cycle            = 7,
+
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
+                | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
+        .tdf_cycles             = 3,
+};
+#endif
+
+static void __init cpu9krea_add_device_nand(void)
+{
+        sam9_smc_configure(3, &cpu9krea_nand_smc_config);
+        at91_add_device_nand(&cpu9krea_nand_data);
+}
+
+/*
+ * NOR flash
+ */
+static struct physmap_flash_data cpuat9260_nor_data = {
+        .width          = 2,
+};
+
+#define NOR_BASE        AT91_CHIPSELECT_0
+#define NOR_SIZE        SZ_64M
+
+static struct resource nor_flash_resources[] = {
+        {
+                .start  = NOR_BASE,
+                .end    = NOR_BASE + NOR_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device cpu9krea_nor_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &cpuat9260_nor_data,
+        },
+        .resource       = nor_flash_resources,
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+};
+
+#ifdef CONFIG_MACH_CPU9260
+static struct sam9_smc_config __initdata cpu9krea_nor_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 1,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 1,
+
+        .ncs_read_pulse         = 10,
+        .nrd_pulse              = 10,
+        .ncs_write_pulse        = 6,
+        .nwe_pulse              = 6,
+
+        .read_cycle             = 12,
+        .write_cycle            = 8,
+
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
+                        | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE
+                        | AT91_SMC_DBW_16,
+        .tdf_cycles             = 2,
+};
+#else
+static struct sam9_smc_config __initdata cpu9krea_nor_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 1,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 1,
+
+        .ncs_read_pulse         = 13,
+        .nrd_pulse              = 13,
+        .ncs_write_pulse        = 8,
+        .nwe_pulse              = 8,
+
+        .read_cycle             = 15,
+        .write_cycle            = 10,
+
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
+                        | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE
+                        | AT91_SMC_DBW_16,
+        .tdf_cycles             = 2,
+};
+#endif
+
+static __init void cpu9krea_add_device_nor(void)
+{
+        unsigned long csa;
+
+        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
+
+        /* configure chip-select 0 (NOR) */
+        sam9_smc_configure(0, &cpu9krea_nor_smc_config);
+
+        platform_device_register(&cpu9krea_nor_flash);
+}
+
+/*
+ * LEDs
+ */
+static struct gpio_led cpu9krea_leds[] = {
+        {       /* LED1 */
+                .name                   = "LED1",
+                .gpio                   = AT91_PIN_PC11,
+                .active_low             = 1,
+                .default_trigger        = "timer",
+        },
+        {       /* LED2 */
+                .name                   = "LED2",
+                .gpio                   = AT91_PIN_PC12,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+        {       /* LED3 */
+                .name                   = "LED3",
+                .gpio                   = AT91_PIN_PC7,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+        {       /* LED4 */
+                .name                   = "LED4",
+                .gpio                   = AT91_PIN_PC9,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        }
+};
+
+static struct i2c_board_info __initdata cpu9krea_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("rtc-ds1307", 0x68),
+                .type   = "ds1339",
+        },
+};
+
+/*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button cpu9krea_buttons[] = {
+        {
+                .gpio           = AT91_PIN_PC3,
+                .code           = BTN_0,
+                .desc           = "BP1",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = AT91_PIN_PB20,
+                .code           = BTN_1,
+                .desc           = "BP2",
+                .active_low     = 1,
+                .wakeup         = 1,
+        }
+};
+
+static struct gpio_keys_platform_data cpu9krea_button_data = {
+        .buttons        = cpu9krea_buttons,
+        .nbuttons       = ARRAY_SIZE(cpu9krea_buttons),
+};
+
+static struct platform_device cpu9krea_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &cpu9krea_button_data,
+        }
+};
+
+static void __init cpu9krea_add_device_buttons(void)
+{
+        at91_set_gpio_input(AT91_PIN_PC3, 1);   /* BP1 */
+        at91_set_deglitch(AT91_PIN_PC3, 1);
+        at91_set_gpio_input(AT91_PIN_PB20, 1);  /* BP2 */
+        at91_set_deglitch(AT91_PIN_PB20, 1);
+
+        platform_device_register(&cpu9krea_button_device);
+}
+#else
+static void __init cpu9krea_add_device_buttons(void)
+{
+}
+#endif
+
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata cpu9krea_mmc_data = {
+        .slot_b         = 0,
+        .wire4          = 1,
+        .det_pin        = AT91_PIN_PA29,
+};
+
+static void __init cpu9krea_board_init(void)
+{
+        /* NOR */
+        cpu9krea_add_device_nor();
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&cpu9krea_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&cpu9krea_udc_data);
+        /* NAND */
+        cpu9krea_add_device_nand();
+        /* Ethernet */
+        at91_add_device_eth(&cpu9krea_macb_data);
+        /* MMC */
+        at91_add_device_mmc(0, &cpu9krea_mmc_data);
+        /* I2C */
+        at91_add_device_i2c(cpu9krea_i2c_devices,
+                ARRAY_SIZE(cpu9krea_i2c_devices));
+        /* LEDs */
+        at91_gpio_leds(cpu9krea_leds, ARRAY_SIZE(cpu9krea_leds));
+        /* Push Buttons */
+        cpu9krea_add_device_buttons();
+}
+
+#ifdef CONFIG_MACH_CPU9260
+MACHINE_START(CPUAT9260, "Eukrea CPU9260")
+#else
+MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
+#endif
+        /* Maintainer: Eric Benard - EUKREA Electromatique */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = cpu9krea_map_io,
+        .init_irq       = cpu9krea_init_irq,
+        .init_machine   = cpu9krea_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
new file mode 100644
index 000000000000..a28d99656190
--- /dev/null
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -0,0 +1,185 @@
+/*
+ * linux/arch/arm/mach-at91/board-cpuat91.c
+ *
+ *  Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/plat-ram.h>
+
+#include <mach/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91rm9200_mc.h>
+
+#include "generic.h"
+
+static struct gpio_led cpuat91_leds[] = {
+        {
+                .name                   = "led1",
+                .default_trigger        = "heartbeat",
+                .active_low             = 1,
+                .gpio                   = AT91_PIN_PC0,
+        },
+};
+
+static void __init cpuat91_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
+
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS |
+                ATMEL_UART_RTS);
+
+        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS |
+                ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
+                ATMEL_UART_DCD | ATMEL_UART_RI);
+
+        /* USART2 on ttyS3 (Rx, Tx) */
+        at91_register_uart(AT91RM9200_ID_US2, 3, 0);
+
+        /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS |
+                ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init cpuat91_init_irq(void)
+{
+        at91rm9200_init_interrupts(NULL);
+}
+
+static struct at91_eth_data __initdata cpuat91_eth_data = {
+        .is_rmii        = 1,
+};
+
+static struct at91_usbh_data __initdata cpuat91_usbh_data = {
+        .ports          = 1,
+};
+
+static struct at91_udc_data __initdata cpuat91_udc_data = {
+        .vbus_pin       = AT91_PIN_PC15,
+        .pullup_pin     = AT91_PIN_PC14,
+};
+
+static struct at91_mmc_data __initdata cpuat91_mmc_data = {
+        .det_pin        = AT91_PIN_PC2,
+        .wire4          = 1,
+};
+
+static struct physmap_flash_data cpuat91_flash_data = {
+        .width          = 2,
+};
+
+static struct resource cpuat91_flash_resource = {
+        .start          = AT91_CHIPSELECT_0,
+        .end            = AT91_CHIPSELECT_0 + SZ_16M - 1,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device cpuat91_norflash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev    = {
+                .platform_data  = &cpuat91_flash_data,
+        },
+        .resource       = &cpuat91_flash_resource,
+        .num_resources  = 1,
+};
+
+#ifdef CONFIG_MTD_PLATRAM
+struct platdata_mtd_ram at91_sram_pdata = {
+        .mapname        = "SRAM",
+        .bankwidth      = 2,
+};
+
+static struct resource at91_sram_resource[] = {
+        [0] = {
+                .start = AT91RM9200_SRAM_BASE,
+                .end   = AT91RM9200_SRAM_BASE + AT91RM9200_SRAM_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device at91_sram = {
+        .name           = "mtd-ram",
+        .id             = 0,
+        .resource       = at91_sram_resource,
+        .num_resources  = ARRAY_SIZE(at91_sram_resource),
+        .dev    = {
+                .platform_data = &at91_sram_pdata,
+        },
+};
+#endif /* MTD_PLATRAM */
+
+static struct platform_device *platform_devices[] __initdata = {
+        &cpuat91_norflash,
+#ifdef CONFIG_MTD_PLATRAM
+        &at91_sram,
+#endif /* CONFIG_MTD_PLATRAM */
+};
+
+static void __init cpuat91_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* LEDs. */
+        at91_gpio_leds(cpuat91_leds, ARRAY_SIZE(cpuat91_leds));
+        /* Ethernet */
+        at91_add_device_eth(&cpuat91_eth_data);
+        /* USB Host */
+        at91_add_device_usbh(&cpuat91_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&cpuat91_udc_data);
+        /* MMC */
+        at91_add_device_mmc(0, &cpuat91_mmc_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* Platform devices */
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+MACHINE_START(CPUAT91, "Eukrea")
+        /* Maintainer: Eric Benard - EUKREA Electromatique */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91rm9200_timer,
+        .map_io         = cpuat91_map_io,
+        .init_irq       = cpuat91_init_irq,
+        .init_machine   = cpuat91_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index d5266da55311..f9b19993a7a9 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -287,7 +287,11 @@ static void __init ek_add_device_ts(void) {}
  */
 static struct at73c213_board_info at73c213_data = {
         .ssc_id         = 1,
+#if defined(CONFIG_MACH_AT91SAM9261EK)
         .shortname      = "AT91SAM9261-EK external DAC",
+#else
+        .shortname      = "AT91SAM9G10-EK external DAC",
+#endif
 };
 
 #if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
@@ -414,6 +418,9 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
         .default_monspecs               = &at91fb_default_stn_monspecs,
         .atmel_lcdfb_power_control      = at91_lcdc_stn_power_control,
         .guard_time                     = 1,
+#if defined(CONFIG_MACH_AT91SAM9G10EK)
+        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB,
+#endif
 };
 
 #else
@@ -467,6 +474,9 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
         .default_monspecs               = &at91fb_default_tft_monspecs,
         .atmel_lcdfb_power_control      = at91_lcdc_tft_power_control,
         .guard_time                     = 1,
+#if defined(CONFIG_MACH_AT91SAM9G10EK)
+        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB,
+#endif
 };
 #endif
 
@@ -600,7 +610,11 @@ static void __init ek_board_init(void)
         at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
 }
 
+#if defined(CONFIG_MACH_AT91SAM9261EK)
 MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
+#else
+MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
+#endif
         /* Maintainer: Atmel */
         .phys_io        = AT91_BASE_SYS,
         .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 57d52528f224..1bf7bd4cbe13 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -364,9 +364,9 @@ static void __init ek_add_device_buttons(void) {}
 
 /*
  * AC97
+ * reset_pin is not connected: NRST
  */
-static struct atmel_ac97_data ek_ac97_data = {
-        .reset_pin      = AT91_PIN_PA13,
+static struct ac97c_platform_data ek_ac97_data = {
 };
 
 
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index a55398ed1211..ca470d504ea0 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -273,6 +273,7 @@ static void __init ek_add_device_buttons(void) {}
 static struct i2c_board_info __initdata ek_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("24c512", 0x50),
+                I2C_BOARD_INFO("wm8731", 0x1b),
         },
 };
 
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
new file mode 100644
index 000000000000..b8558eae5229
--- /dev/null
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -0,0 +1,389 @@
+/*
+ *  Board-specific setup code for the AT91SAM9M10G45 Evaluation Kit family
+ *
+ *  Covers: * AT91SAM9G45-EKES  board
+ *          * AT91SAM9M10G45-EK board
+ *
+ *  Copyright (C) 2009 Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/fb.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/leds.h>
+#include <linux/clk.h>
+
+#include <mach/hardware.h>
+#include <video/atmel_lcdc.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91_shdwc.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+
+static void __init ek_map_io(void)
+{
+        /* Initialize processor: 12.000 MHz crystal */
+        at91sam9g45_initialize(12000000);
+
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 not connected on the -EK board */
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init ek_init_irq(void)
+{
+        at91sam9g45_init_interrupts(NULL);
+}
+
+
+/*
+ * USB HS Host port (common to OHCI & EHCI)
+ */
+static struct at91_usbh_data __initdata ek_usbh_hs_data = {
+        .ports          = 2,
+        .vbus_pin       = {AT91_PIN_PD1, AT91_PIN_PD3},
+};
+
+
+/*
+ * USB HS Device port
+ */
+static struct usba_platform_data __initdata ek_usba_udc_data = {
+        .vbus_pin       = AT91_PIN_PB19,
+};
+
+
+/*
+ * SPI devices.
+ */
+static struct spi_board_info ek_spi_devices[] = {
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata ek_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PD5,
+        .is_rmii        = 1,
+};
+
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+        {
+                .name   = "Partition 1",
+                .offset = 0,
+                .size   = SZ_64M,
+        },
+        {
+                .name   = "Partition 2",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(ek_nand_partition);
+        return ek_nand_partition;
+}
+
+/* det_pin is not connected */
+static struct atmel_nand_data __initdata ek_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+        .rdy_pin        = AT91_PIN_PC8,
+        .enable_pin     = AT91_PIN_PC14,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+static struct sam9_smc_config __initdata ek_nand_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 2,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 2,
+
+        .ncs_read_pulse         = 4,
+        .nrd_pulse              = 4,
+        .ncs_write_pulse        = 4,
+        .nwe_pulse              = 4,
+
+        .read_cycle             = 7,
+        .write_cycle            = 7,
+
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
+        .tdf_cycles             = 3,
+};
+
+static void __init ek_add_device_nand(void)
+{
+        /* setup bus-width (8 or 16) */
+        if (ek_nand_data.bus_width_16)
+                ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
+        else
+                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
+
+        /* configure chip-select 3 (NAND) */
+        sam9_smc_configure(3, &ek_nand_smc_config);
+
+        at91_add_device_nand(&ek_nand_data);
+}
+
+
+/*
+ * LCD Controller
+ */
+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
+static struct fb_videomode at91_tft_vga_modes[] = {
+        {
+                .name           = "LG",
+                .refresh        = 60,
+                .xres           = 480,          .yres           = 272,
+                .pixclock       = KHZ2PICOS(9000),
+
+                .left_margin    = 1,            .right_margin   = 1,
+                .upper_margin   = 40,           .lower_margin   = 1,
+                .hsync_len      = 45,           .vsync_len      = 1,
+
+                .sync           = 0,
+                .vmode          = FB_VMODE_NONINTERLACED,
+        },
+};
+
+static struct fb_monspecs at91fb_default_monspecs = {
+        .manufacturer   = "LG",
+        .monitor        = "LB043WQ1",
+
+        .modedb         = at91_tft_vga_modes,
+        .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
+        .hfmin          = 15000,
+        .hfmax          = 17640,
+        .vfmin          = 57,
+        .vfmax          = 67,
+};
+
+#define AT91SAM9G45_DEFAULT_LCDCON2     (ATMEL_LCDC_MEMOR_LITTLE \
+                                        | ATMEL_LCDC_DISTYPE_TFT \
+                                        | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
+
+/* Driver datas */
+static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
+        .lcdcon_is_backlight            = true,
+        .default_bpp                    = 32,
+        .default_dmacon                 = ATMEL_LCDC_DMAEN,
+        .default_lcdcon2                = AT91SAM9G45_DEFAULT_LCDCON2,
+        .default_monspecs               = &at91fb_default_monspecs,
+        .guard_time                     = 9,
+        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB,
+};
+
+#else
+static struct atmel_lcdfb_info __initdata ek_lcdc_data;
+#endif
+
+
+/*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button ek_buttons[] = {
+        {       /* BP1, "leftclic" */
+                .code           = BTN_LEFT,
+                .gpio           = AT91_PIN_PB6,
+                .active_low     = 1,
+                .desc           = "left_click",
+                .wakeup         = 1,
+        },
+        {       /* BP2, "rightclic" */
+                .code           = BTN_RIGHT,
+                .gpio           = AT91_PIN_PB7,
+                .active_low     = 1,
+                .desc           = "right_click",
+                .wakeup         = 1,
+        },
+                /* BP3, "joystick" */
+        {
+                .code           = KEY_LEFT,
+                .gpio           = AT91_PIN_PB14,
+                .active_low     = 1,
+                .desc           = "Joystick Left",
+        },
+        {
+                .code           = KEY_RIGHT,
+                .gpio           = AT91_PIN_PB15,
+                .active_low     = 1,
+                .desc           = "Joystick Right",
+        },
+        {
+                .code           = KEY_UP,
+                .gpio           = AT91_PIN_PB16,
+                .active_low     = 1,
+                .desc           = "Joystick Up",
+        },
+        {
+                .code           = KEY_DOWN,
+                .gpio           = AT91_PIN_PB17,
+                .active_low     = 1,
+                .desc           = "Joystick Down",
+        },
+        {
+                .code           = KEY_ENTER,
+                .gpio           = AT91_PIN_PB18,
+                .active_low     = 1,
+                .desc           = "Joystick Press",
+        },
+};
+
+static struct gpio_keys_platform_data ek_button_data = {
+        .buttons        = ek_buttons,
+        .nbuttons       = ARRAY_SIZE(ek_buttons),
+};
+
+static struct platform_device ek_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_button_data,
+        }
+};
+
+static void __init ek_add_device_buttons(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(ek_buttons); i++) {
+                at91_set_GPIO_periph(ek_buttons[i].gpio, 1);
+                at91_set_deglitch(ek_buttons[i].gpio, 1);
+        }
+
+        platform_device_register(&ek_button_device);
+}
+#else
+static void __init ek_add_device_buttons(void) {}
+#endif
+
+
+/*
+ * LEDs ... these could all be PWM-driven, for variable brightness
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* "top" led, red, powerled */
+                .name                   = "d8",
+                .gpio                   = AT91_PIN_PD30,
+                .default_trigger        = "heartbeat",
+        },
+        {       /* "left" led, green, userled2, pwm3 */
+                .name                   = "d6",
+                .gpio                   = AT91_PIN_PD0,
+                .active_low             = 1,
+                .default_trigger        = "nand-disk",
+        },
+#if !(defined(CONFIG_LEDS_ATMEL_PWM) || defined(CONFIG_LEDS_ATMEL_PWM_MODULE))
+        {       /* "right" led, green, userled1, pwm1 */
+                .name                   = "d7",
+                .gpio                   = AT91_PIN_PD31,
+                .active_low             = 1,
+                .default_trigger        = "mmc0",
+        },
+#endif
+};
+
+
+/*
+ * PWM Leds
+ */
+static struct gpio_led ek_pwm_led[] = {
+#if defined(CONFIG_LEDS_ATMEL_PWM) || defined(CONFIG_LEDS_ATMEL_PWM_MODULE)
+        {       /* "right" led, green, userled1, pwm1 */
+                .name                   = "d7",
+                .gpio                   = 1,    /* is PWM channel number */
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+#endif
+};
+
+
+
+static void __init ek_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB HS Host */
+        at91_add_device_usbh_ohci(&ek_usbh_hs_data);
+        /* USB HS Device */
+        at91_add_device_usba(&ek_usba_udc_data);
+        /* SPI */
+        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+        /* Ethernet */
+        at91_add_device_eth(&ek_macb_data);
+        /* NAND */
+        ek_add_device_nand();
+        /* I2C */
+        at91_add_device_i2c(0, NULL, 0);
+        /* LCD Controller */
+        at91_add_device_lcdc(&ek_lcdc_data);
+        /* Push Buttons */
+        ek_add_device_buttons();
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
+}
+
+MACHINE_START(AT91SAM9G45EKES, "Atmel AT91SAM9G45-EKES")
+        /* Maintainer: Atmel */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index f6b5672cabd6..9d07679efce7 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -15,6 +15,8 @@
 #include <linux/spi/spi.h>
 #include <linux/fb.h>
 #include <linux/clk.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
 
 #include <video/atmel_lcdc.h>
 
@@ -208,6 +210,79 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data;
 #endif
 
 
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* "bottom" led, green, userled1 to be defined */
+                .name                   = "ds1",
+                .gpio                   = AT91_PIN_PD15,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+        {       /* "bottom" led, green, userled2 to be defined */
+                .name                   = "ds2",
+                .gpio                   = AT91_PIN_PD16,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+        {       /* "power" led, yellow */
+                .name                   = "ds3",
+                .gpio                   = AT91_PIN_PD14,
+                .default_trigger        = "heartbeat",
+        }
+};
+
+
+/*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button ek_buttons[] = {
+        {
+                .gpio           = AT91_PIN_PB0,
+                .code           = BTN_2,
+                .desc           = "Right Click",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = AT91_PIN_PB1,
+                .code           = BTN_1,
+                .desc           = "Left Click",
+                .active_low     = 1,
+                .wakeup         = 1,
+        }
+};
+
+static struct gpio_keys_platform_data ek_button_data = {
+        .buttons        = ek_buttons,
+        .nbuttons       = ARRAY_SIZE(ek_buttons),
+};
+
+static struct platform_device ek_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_button_data,
+        }
+};
+
+static void __init ek_add_device_buttons(void)
+{
+        at91_set_gpio_input(AT91_PIN_PB1, 1);   /* btn1 */
+        at91_set_deglitch(AT91_PIN_PB1, 1);
+        at91_set_gpio_input(AT91_PIN_PB0, 1);   /* btn2 */
+        at91_set_deglitch(AT91_PIN_PB0, 1);
+
+        platform_device_register(&ek_button_device);
+}
+#else
+static void __init ek_add_device_buttons(void) {}
+#endif
+
+
 static void __init ek_board_init(void)
 {
         /* Serial */
@@ -226,6 +301,10 @@ static void __init ek_board_init(void)
         at91_add_device_lcdc(&ek_lcdc_data);
         /* Touch Screen Controller */
         at91_add_device_tsadcc();
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        /* Push Buttons */
+        ek_add_device_buttons();
 }
 
 MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index bac578fe0d3d..c042dcf4725f 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -47,20 +47,25 @@
  * Chips have some kind of clocks : group them by functionality
  */
 #define cpu_has_utmi()          (  cpu_is_at91cap9() \
-                                || cpu_is_at91sam9rl())
+                                || cpu_is_at91sam9rl() \
+                                || cpu_is_at91sam9g45())
 
-#define cpu_has_800M_plla()     (cpu_is_at91sam9g20())
+#define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
+                                || cpu_is_at91sam9g45())
 
-#define cpu_has_pllb()          (!cpu_is_at91sam9rl())
+#define cpu_has_300M_plla()     (cpu_is_at91sam9g10())
 
-#define cpu_has_upll()          (0)
+#define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
+                                || cpu_is_at91sam9g45()))
+
+#define cpu_has_upll()          (cpu_is_at91sam9g45())
 
 /* USB host HS & FS */
 #define cpu_has_uhp()           (!cpu_is_at91sam9rl())
 
 /* USB device FS only */
-#define cpu_has_udpfs()         (!cpu_is_at91sam9rl())
-
+#define cpu_has_udpfs()         (!(cpu_is_at91sam9rl() \
+                                || cpu_is_at91sam9g45()))
 
 static LIST_HEAD(clocks);
 static DEFINE_SPINLOCK(clk_lock);
@@ -133,6 +138,13 @@ static void pmc_uckr_mode(struct clk *clk, int is_on)
 {
         unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
 
+        if (cpu_is_at91sam9g45()) {
+                if (is_on)
+                        uckr |= AT91_PMC_BIASEN;
+                else
+                        uckr &= ~AT91_PMC_BIASEN;
+        }
+
         if (is_on) {
                 is_on = AT91_PMC_LOCKU;
                 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
@@ -310,6 +322,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
         unsigned long   flags;
         unsigned        prescale;
         unsigned long   actual;
+        unsigned long   prev = ULONG_MAX;
 
         if (!clk_is_programmable(clk))
                 return -EINVAL;
@@ -317,8 +330,16 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
 
         actual = clk->parent->rate_hz;
         for (prescale = 0; prescale < 7; prescale++) {
-                if (actual && actual <= rate)
+                if (actual > rate)
+                        prev = actual;
+
+                if (actual && actual <= rate) {
+                        if ((prev - rate) < (rate - actual)) {
+                                actual = prev;
+                                prescale--;
+                        }
                         break;
+                }
                 actual >>= 1;
         }
 
@@ -373,6 +394,10 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
                 return -EBUSY;
         if (!clk_is_primary(parent) || !clk_is_programmable(clk))
                 return -EINVAL;
+
+        if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
+                return -EINVAL;
+
         spin_lock_irqsave(&clk_lock, flags);
 
         clk->rate_hz = parent->rate_hz;
@@ -601,7 +626,9 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
                 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
                 udpck.pmc_mask = AT91RM9200_PMC_UDP;
                 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
-        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
+        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
+                   cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
+                   cpu_is_at91sam9g10()) {
                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
         } else if (cpu_is_at91cap9()) {
@@ -637,6 +664,7 @@ int __init at91_clock_init(unsigned long main_clock)
 {
         unsigned tmp, freq, mckr;
         int i;
+        int pll_overclock = false;
 
         /*
          * When the bootloader initialized the main oscillator correctly,
@@ -654,12 +682,25 @@ int __init at91_clock_init(unsigned long main_clock)
 
         /* report if PLLA is more than mildly overclocked */
         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
-        if ((!cpu_has_800M_plla() && plla.rate_hz > 209000000)
-           || (cpu_has_800M_plla() && plla.rate_hz > 800000000))
+        if (cpu_has_300M_plla()) {
+                if (plla.rate_hz > 300000000)
+                        pll_overclock = true;
+        } else if (cpu_has_800M_plla()) {
+                if (plla.rate_hz > 800000000)
+                        pll_overclock = true;
+        } else {
+                if (plla.rate_hz > 209000000)
+                        pll_overclock = true;
+        }
+        if (pll_overclock)
                 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 
+        if (cpu_is_at91sam9g45()) {
+                mckr = at91_sys_read(AT91_PMC_MCKR);
+                plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));      /* plla divisor by 2 */
+        }
 
-        if (cpu_has_upll() && !cpu_has_pllb()) {
+        if (!cpu_has_pllb() && cpu_has_upll()) {
                 /* setup UTMI clock as the fourth primary clock
                  * (instead of pllb) */
                 utmi_clk.type |= CLK_TYPE_PRIMARY;
@@ -701,6 +742,9 @@ int __init at91_clock_init(unsigned long main_clock)
                         freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
                 if (mckr & AT91_PMC_PDIV)
                         freq /= 2;              /* processor clock division */
+        } else if (cpu_is_at91sam9g45()) {
+                mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
+                        freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
         } else {
                 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
         }
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index b5daf7f5e011..88e413b38480 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -14,6 +14,7 @@ extern void __init at91sam9260_initialize(unsigned long main_clock);
 extern void __init at91sam9261_initialize(unsigned long main_clock);
 extern void __init at91sam9263_initialize(unsigned long main_clock);
 extern void __init at91sam9rl_initialize(unsigned long main_clock);
+extern void __init at91sam9g45_initialize(unsigned long main_clock);
 extern void __init at91x40_initialize(unsigned long main_clock);
 extern void __init at91cap9_initialize(unsigned long main_clock);
 
@@ -23,6 +24,7 @@ extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
 extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
 extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
 extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
+extern void __init at91sam9g45_init_interrupts(unsigned int priority[]);
 extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91cap9_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index f2236f0e101f..ae4772e744ac 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -44,13 +44,11 @@ static int at91_gpiolib_direction_output(struct gpio_chip *chip,
                                          unsigned offset, int val);
 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                                         unsigned offset);
-static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
 
 #define AT91_GPIO_CHIP(name, base_gpio, nr_gpio)                        \
         {                                                               \
                 .chip = {                                               \
                         .label            = name,                       \
-                        .request          = at91_gpiolib_request,       \
                         .direction_input  = at91_gpiolib_direction_input, \
                         .direction_output = at91_gpiolib_direction_output, \
                         .get              = at91_gpiolib_get,           \
@@ -588,19 +586,6 @@ static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
         __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
 }
 
-static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
-{
-        unsigned pin = chip->base + offset;
-        void __iomem *pio = pin_to_controller(pin);
-        unsigned mask = pin_to_mask(pin);
-
-        /* Cannot request GPIOs that are in alternate function mode */
-        if (!(__raw_readl(pio + PIO_PSR) & mask))
-                return -EPERM;
-
-        return 0;
-}
-
 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 {
         int i;
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 3a348ca20773..87de8be17484 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -95,6 +95,9 @@
 #define AT91SAM9261_SRAM_BASE   0x00300000      /* Internal SRAM base address */
 #define AT91SAM9261_SRAM_SIZE   0x00028000      /* Internal SRAM size (160Kb) */
 
+#define AT91SAM9G10_SRAM_BASE   AT91SAM9261_SRAM_BASE   /* Internal SRAM base address */
+#define AT91SAM9G10_SRAM_SIZE   0x00004000      /* Internal SRAM size (16Kb) */
+
 #define AT91SAM9261_ROM_BASE    0x00400000      /* Internal ROM base address */
 #define AT91SAM9261_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
 
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
new file mode 100644
index 000000000000..a526869aee37
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -0,0 +1,155 @@
+/*
+ * Chip-specific header file for the AT91SAM9G45 family
+ *
+ *  Copyright (C) 2008-2009 Atmel Corporation.
+ *
+ * Common definitions.
+ * Based on AT91SAM9G45 preliminary datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9G45_H
+#define AT91SAM9G45_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Controller Interrupt */
+#define AT91SAM9G45_ID_PIOA     2       /* Parallel I/O Controller A */
+#define AT91SAM9G45_ID_PIOB     3       /* Parallel I/O Controller B */
+#define AT91SAM9G45_ID_PIOC     4       /* Parallel I/O Controller C */
+#define AT91SAM9G45_ID_PIODE    5       /* Parallel I/O Controller D and E */
+#define AT91SAM9G45_ID_TRNG     6       /* True Random Number Generator */
+#define AT91SAM9G45_ID_US0      7       /* USART 0 */
+#define AT91SAM9G45_ID_US1      8       /* USART 1 */
+#define AT91SAM9G45_ID_US2      9       /* USART 2 */
+#define AT91SAM9G45_ID_US3      10      /* USART 3 */
+#define AT91SAM9G45_ID_MCI0     11      /* High Speed Multimedia Card Interface 0 */
+#define AT91SAM9G45_ID_TWI0     12      /* Two-Wire Interface 0 */
+#define AT91SAM9G45_ID_TWI1     13      /* Two-Wire Interface 1 */
+#define AT91SAM9G45_ID_SPI0     14      /* Serial Peripheral Interface 0 */
+#define AT91SAM9G45_ID_SPI1     15      /* Serial Peripheral Interface 1 */
+#define AT91SAM9G45_ID_SSC0     16      /* Synchronous Serial Controller 0 */
+#define AT91SAM9G45_ID_SSC1     17      /* Synchronous Serial Controller 1 */
+#define AT91SAM9G45_ID_TCB      18      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define AT91SAM9G45_ID_PWMC     19      /* Pulse Width Modulation Controller */
+#define AT91SAM9G45_ID_TSC      20      /* Touch Screen ADC Controller */
+#define AT91SAM9G45_ID_DMA      21      /* DMA Controller */
+#define AT91SAM9G45_ID_UHPHS    22      /* USB Host High Speed */
+#define AT91SAM9G45_ID_LCDC     23      /* LCD Controller */
+#define AT91SAM9G45_ID_AC97C    24      /* AC97 Controller */
+#define AT91SAM9G45_ID_EMAC     25      /* Ethernet MAC */
+#define AT91SAM9G45_ID_ISI      26      /* Image Sensor Interface */
+#define AT91SAM9G45_ID_UDPHS    27      /* USB Device High Speed */
+#define AT91SAM9G45_ID_AESTDESSHA 28    /* AES + T-DES + SHA */
+#define AT91SAM9G45_ID_MCI1     29      /* High Speed Multimedia Card Interface 1 */
+#define AT91SAM9G45_ID_VDEC     30      /* Video Decoder */
+#define AT91SAM9G45_ID_IRQ0     31      /* Advanced Interrupt Controller */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9G45_BASE_UDPHS          0xfff78000
+#define AT91SAM9G45_BASE_TCB0           0xfff7c000
+#define AT91SAM9G45_BASE_TC0            0xfff7c000
+#define AT91SAM9G45_BASE_TC1            0xfff7c040
+#define AT91SAM9G45_BASE_TC2            0xfff7c080
+#define AT91SAM9G45_BASE_MCI0           0xfff80000
+#define AT91SAM9G45_BASE_TWI0           0xfff84000
+#define AT91SAM9G45_BASE_TWI1           0xfff88000
+#define AT91SAM9G45_BASE_US0            0xfff8c000
+#define AT91SAM9G45_BASE_US1            0xfff90000
+#define AT91SAM9G45_BASE_US2            0xfff94000
+#define AT91SAM9G45_BASE_US3            0xfff98000
+#define AT91SAM9G45_BASE_SSC0           0xfff9c000
+#define AT91SAM9G45_BASE_SSC1           0xfffa0000
+#define AT91SAM9G45_BASE_SPI0           0xfffa4000
+#define AT91SAM9G45_BASE_SPI1           0xfffa8000
+#define AT91SAM9G45_BASE_AC97C          0xfffac000
+#define AT91SAM9G45_BASE_TSC            0xfffb0000
+#define AT91SAM9G45_BASE_ISI            0xfffb4000
+#define AT91SAM9G45_BASE_PWMC           0xfffb8000
+#define AT91SAM9G45_BASE_EMAC           0xfffbc000
+#define AT91SAM9G45_BASE_AES            0xfffc0000
+#define AT91SAM9G45_BASE_TDES           0xfffc4000
+#define AT91SAM9G45_BASE_SHA            0xfffc8000
+#define AT91SAM9G45_BASE_TRNG           0xfffcc000
+#define AT91SAM9G45_BASE_MCI1           0xfffd0000
+#define AT91SAM9G45_BASE_TCB1           0xfffd4000
+#define AT91SAM9G45_BASE_TC3            0xfffd4000
+#define AT91SAM9G45_BASE_TC4            0xfffd4040
+#define AT91SAM9G45_BASE_TC5            0xfffd4080
+#define AT91_BASE_SYS                   0xffffe200
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC        (0xffffe200 - AT91_BASE_SYS)
+#define AT91_DDRSDRC1   (0xffffe400 - AT91_BASE_SYS)
+#define AT91_DDRSDRC0   (0xffffe600 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffe800 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_DMA        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PIOE       (0xfffffa00 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
+#define AT91_RTC        (0xfffffdb0 - AT91_BASE_SYS)
+
+#define AT91_USART0     AT91SAM9G45_BASE_US0
+#define AT91_USART1     AT91SAM9G45_BASE_US1
+#define AT91_USART2     AT91SAM9G45_BASE_US2
+#define AT91_USART3     AT91SAM9G45_BASE_US3
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9G45_SRAM_BASE   0x00300000      /* Internal SRAM base address */
+#define AT91SAM9G45_SRAM_SIZE   SZ_64K          /* Internal SRAM size (64Kb) */
+
+#define AT91SAM9G45_ROM_BASE    0x00400000      /* Internal ROM base address */
+#define AT91SAM9G45_ROM_SIZE    SZ_64K          /* Internal ROM size (64Kb) */
+
+#define AT91SAM9G45_LCDC_BASE   0x00500000      /* LCD Controller */
+#define AT91SAM9G45_UDPHS_FIFO  0x00600000      /* USB Device HS controller */
+#define AT91SAM9G45_OHCI_BASE   0x00700000      /* USB Host controller (OHCI) */
+#define AT91SAM9G45_EHCI_BASE   0x00800000      /* USB Host controller (EHCI) */
+#define AT91SAM9G45_VDEC_BASE   0x00900000      /* Video Decoder Controller */
+
+#define CONFIG_DRAM_BASE        AT91_CHIPSELECT_6
+
+#define CONSISTENT_DMA_SIZE     SZ_4M
+
+/*
+ * DMA peripheral identifiers
+ * for hardware handshaking interface
+ */
+#define AT_DMA_ID_MCI0           0
+#define AT_DMA_ID_SPI0_TX        1
+#define AT_DMA_ID_SPI0_RX        2
+#define AT_DMA_ID_SPI1_TX        3
+#define AT_DMA_ID_SPI1_RX        4
+#define AT_DMA_ID_SSC0_TX        5
+#define AT_DMA_ID_SSC0_RX        6
+#define AT_DMA_ID_SSC1_TX        7
+#define AT_DMA_ID_SSC1_RX        8
+#define AT_DMA_ID_AC97_TX        9
+#define AT_DMA_ID_AC97_RX       10
+#define AT_DMA_ID_MCI1          13
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
new file mode 100644
index 000000000000..c972d60e0aeb
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
@@ -0,0 +1,153 @@
+/*
+ * Matrix-centric header file for the AT91SAM9G45 family
+ *
+ *  Copyright (C) 2008-2009 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9G45 preliminary datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9G45_MATRIX_H
+#define AT91SAM9G45_MATRIX_H
+
+#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG9       (AT91_MATRIX + 0x24)    /* Master Configuration Register 9 */
+#define AT91_MATRIX_MCFG10      (AT91_MATRIX + 0x28)    /* Master Configuration Register 10 */
+#define AT91_MATRIX_MCFG11      (AT91_MATRIX + 0x2C)    /* Master Configuration Register 11 */
+#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
+#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+#define                 AT91_MATRIX_ULBT_THIRTYTWO      (5 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTYFOUR      (6 << 0)
+#define                 AT91_MATRIX_ULBT_128            (7 << 0)
+
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0x1ff << 0)    /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
+
+#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
+#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
+#define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
+#define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
+#define         AT91_MATRIX_M9PR                (3 << 4)        /* Master 9 Priority (in Register B) */
+#define         AT91_MATRIX_M10PR               (3 << 8)        /* Master 10 Priority (in Register B) */
+#define         AT91_MATRIX_M11PR               (3 << 12)       /* Master 11 Priority (in Register B) */
+
+#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define         AT91_MATRIX_RCB2                (1 << 2)
+#define         AT91_MATRIX_RCB3                (1 << 3)
+#define         AT91_MATRIX_RCB4                (1 << 4)
+#define         AT91_MATRIX_RCB5                (1 << 5)
+#define         AT91_MATRIX_RCB6                (1 << 6)
+#define         AT91_MATRIX_RCB7                (1 << 7)
+#define         AT91_MATRIX_RCB8                (1 << 8)
+#define         AT91_MATRIX_RCB9                (1 << 9)
+#define         AT91_MATRIX_RCB10               (1 << 10)
+#define         AT91_MATRIX_RCB11               (1 << 11)
+
+#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x110)   /* TCM Configuration Register */
+#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
+#define                 AT91_MATRIX_ITCM_0              (0 << 0)
+#define                 AT91_MATRIX_ITCM_32             (6 << 0)
+#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
+#define                 AT91_MATRIX_DTCM_0              (0 << 4)
+#define                 AT91_MATRIX_DTCM_32             (6 << 4)
+#define                 AT91_MATRIX_DTCM_64             (7 << 4)
+#define         AT91_MATRIX_TCM_NWS             (0x1 << 11)     /* Wait state TCM register */
+#define                 AT91_MATRIX_TCM_NO_WS           (0x0 << 11)
+#define                 AT91_MATRIX_TCM_ONE_WS          (0x1 << 11)
+
+#define AT91_MATRIX_VIDEO       (AT91_MATRIX + 0x118)   /* Video Mode Configuration Register */
+#define         AT91C_VDEC_SEL                  (0x1 <<  0) /* Video Mode Selection */
+#define                 AT91C_VDEC_SEL_OFF              (0 << 0)
+#define                 AT91C_VDEC_SEL_ON               (1 << 0)
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x128)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
+#define                 AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
+#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
+#define                 AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
+#define         AT91_MATRIX_EBI_CS4A            (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_EBI_CS4A_SMC                (0 << 4)
+#define                 AT91_MATRIX_EBI_CS4A_SMC_CF0            (1 << 4)
+#define         AT91_MATRIX_EBI_CS5A            (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_EBI_CS5A_SMC                (0 << 5)
+#define                 AT91_MATRIX_EBI_CS5A_SMC_CF1            (1 << 5)
+#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
+#define                 AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
+#define                 AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
+#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
+#define         AT91_MATRIX_EBI_EBI_IOSR        (1 << 17)       /* EBI I/O slew rate selection */
+#define                 AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
+#define                 AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
+#define         AT91_MATRIX_EBI_DDR_IOSR        (1 << 18)       /* DDR2 dedicated port I/O slew rate selection */
+#define                 AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
+#define                 AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
+
+#define AT91_MATRIX_WPMR        (AT91_MATRIX + 0x1E4)   /* Write Protect Mode Register */
+#define         AT91_MATRIX_WPMR_WPEN           (1 << 0)        /* Write Protect ENable */
+#define                 AT91_MATRIX_WPMR_WP_WPDIS               (0 << 0)
+#define                 AT91_MATRIX_WPMR_WP_WPEN                (1 << 0)
+#define         AT91_MATRIX_WPMR_WPKEY          (0xFFFFFF << 8) /* Write Protect KEY */
+
+#define AT91_MATRIX_WPSR        (AT91_MATRIX + 0x1E8)   /* Write Protect Status Register */
+#define         AT91_MATRIX_WPSR_WPVS           (1 << 0)        /* Write Protect Violation Status */
+#define                 AT91_MATRIX_WPSR_NO_WPV         (0 << 0)
+#define                 AT91_MATRIX_WPSR_WPV            (1 << 0)
+#define         AT91_MATRIX_WPSR_WPVSRC         (0xFFFF << 8)   /* Write Protect Violation Source */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index e6afff849b85..13f27a4b882d 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -37,6 +37,7 @@
 #include <linux/leds.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/atmel_usba_udc.h>
+#include <sound/atmel-ac97c.h>
 
  /* USB Device */
 struct at91_udc_data {
@@ -80,7 +81,8 @@ struct at91_eth_data {
 };
 extern void __init at91_add_device_eth(struct at91_eth_data *data);
 
-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9)
+#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
+        || defined(CONFIG_ARCH_AT91SAM9G45)
 #define eth_platform_data       at91_eth_data
 #endif
 
@@ -90,6 +92,7 @@ struct at91_usbh_data {
         u8              vbus_pin[2];    /* port power-control pin */
 };
 extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
+extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
 
  /* NAND / SmartMedia */
 struct atmel_nand_data {
@@ -105,7 +108,11 @@ struct atmel_nand_data {
 extern void __init at91_add_device_nand(struct atmel_nand_data *data);
 
  /* I2C*/
+#if defined(CONFIG_ARCH_AT91SAM9G45)
+extern void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices);
+#else
 extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
+#endif
 
  /* SPI */
 extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
@@ -168,10 +175,7 @@ struct atmel_lcdfb_info;
 extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
 
  /* AC97 */
-struct atmel_ac97_data {
-        u8              reset_pin;      /* reset */
-};
-extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
+extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
 
  /* ISI */
 extern void __init at91_add_device_isi(void);
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index c554c3e4d553..34a9502c48bc 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -21,8 +21,10 @@
 #define ARCH_ID_AT91SAM9260     0x019803a0
 #define ARCH_ID_AT91SAM9261     0x019703a0
 #define ARCH_ID_AT91SAM9263     0x019607a0
+#define ARCH_ID_AT91SAM9G10     0x819903a0
 #define ARCH_ID_AT91SAM9G20     0x019905a0
 #define ARCH_ID_AT91SAM9RL64    0x019b03a0
+#define ARCH_ID_AT91SAM9G45     0x819b05a0
 #define ARCH_ID_AT91CAP9        0x039A03A0
 
 #define ARCH_ID_AT91SAM9XE128   0x329973a0
@@ -39,6 +41,15 @@ static inline unsigned long at91_cpu_identify(void)
         return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
 }
 
+#define ARCH_EXID_AT91SAM9M11   0x00000001
+#define ARCH_EXID_AT91SAM9M10   0x00000002
+#define ARCH_EXID_AT91SAM9G45   0x00000004
+
+static inline unsigned long at91_exid_identify(void)
+{
+        return at91_sys_read(AT91_DBGU_EXID);
+}
+
 
 #define ARCH_FAMILY_AT91X92     0x09200000
 #define ARCH_FAMILY_AT91SAM9    0x01900000
@@ -87,6 +98,12 @@ static inline unsigned long at91cap9_rev_identify(void)
 #define cpu_is_at91sam9261()    (0)
 #endif
 
+#ifdef CONFIG_ARCH_AT91SAM9G10
+#define cpu_is_at91sam9g10()    (at91_cpu_identify() == ARCH_ID_AT91SAM9G10)
+#else
+#define cpu_is_at91sam9g10()    (0)
+#endif
+
 #ifdef CONFIG_ARCH_AT91SAM9263
 #define cpu_is_at91sam9263()    (at91_cpu_identify() == ARCH_ID_AT91SAM9263)
 #else
@@ -99,6 +116,12 @@ static inline unsigned long at91cap9_rev_identify(void)
 #define cpu_is_at91sam9rl()     (0)
 #endif
 
+#ifdef CONFIG_ARCH_AT91SAM9G45
+#define cpu_is_at91sam9g45()    (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
+#else
+#define cpu_is_at91sam9g45()    (0)
+#endif
+
 #ifdef CONFIG_ARCH_AT91CAP9
 #define cpu_is_at91cap9()       (at91_cpu_identify() == ARCH_ID_AT91CAP9)
 #define cpu_is_at91cap9_revB()  (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B)
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index da0b681c652c..a0df8b022df2 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -20,12 +20,14 @@
 #include <mach/at91rm9200.h>
 #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
 #include <mach/at91sam9260.h>
-#elif defined(CONFIG_ARCH_AT91SAM9261)
+#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10)
 #include <mach/at91sam9261.h>
 #elif defined(CONFIG_ARCH_AT91SAM9263)
 #include <mach/at91sam9263.h>
 #elif defined(CONFIG_ARCH_AT91SAM9RL)
 #include <mach/at91sam9rl.h>
+#elif defined(CONFIG_ARCH_AT91SAM9G45)
+#include <mach/at91sam9g45.h>
 #elif defined(CONFIG_ARCH_AT91CAP9)
 #include <mach/at91cap9.h>
 #elif defined(CONFIG_ARCH_AT91X40)
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index d84c9948becf..31ac2d97f14c 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -42,6 +42,11 @@
 #define AT91SAM9_MASTER_CLOCK   99300000
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 
+#elif defined(CONFIG_ARCH_AT91SAM9G10)
+
+#define AT91SAM9_MASTER_CLOCK   133000000
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+
 #elif defined(CONFIG_ARCH_AT91SAM9263)
 
 #if defined(CONFIG_MACH_USB_A9263)
@@ -62,6 +67,11 @@
 #define AT91SAM9_MASTER_CLOCK   132096000
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 
+#elif defined(CONFIG_ARCH_AT91SAM9G45)
+
+#define AT91SAM9_MASTER_CLOCK   133333333
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+
 #elif defined(CONFIG_ARCH_AT91CAP9)
 
 #define AT91CAP9_MASTER_CLOCK   100000000
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index e26c4fe61fae..4028724d490d 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -201,7 +201,8 @@ static int at91_pm_verify_clocks(void)
                         pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
                         return 0;
                 }
-        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
+        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()
+                        || cpu_is_at91sam9g20() || cpu_is_at91sam9g10()) {
                 if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) {
                         pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
                         return 0;
diff --git a/arch/arm/mach-bcmring/Kconfig b/arch/arm/mach-bcmring/Kconfig
new file mode 100644
index 000000000000..457b4384913e
--- /dev/null
+++ b/arch/arm/mach-bcmring/Kconfig
@@ -0,0 +1,21 @@
+choice
+        prompt "Processor selection in BCMRING family of devices"
+        depends on ARCH_BCMRING
+        default ARCH_BCM11107
+
+config ARCH_FPGA11107
+        bool "FPGA11107"
+
+config ARCH_BCM11107
+        bool "BCM11107"
+endchoice
+
+menu "BCMRING Options"
+        depends on ARCH_BCMRING
+
+config BCM_ZRELADDR
+        hex "Compressed ZREL ADDR"
+
+endmenu
+
+# source "drivers/char/bcmring/Kconfig"
diff --git a/arch/arm/mach-bcmring/Makefile b/arch/arm/mach-bcmring/Makefile
new file mode 100644
index 000000000000..f8d9fcedf917
--- /dev/null
+++ b/arch/arm/mach-bcmring/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o
+obj-y += csp/
diff --git a/arch/arm/mach-bcmring/Makefile.boot b/arch/arm/mach-bcmring/Makefile.boot
new file mode 100644
index 000000000000..fb53b283bebb
--- /dev/null
+++ b/arch/arm/mach-bcmring/Makefile.boot
@@ -0,0 +1,6 @@
+# Address where decompressor will be written and eventually executed.
+#
+# default to SDRAM
+zreladdr-y      := $(CONFIG_BCM_ZRELADDR)
+params_phys-y   := 0x00000800
+
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
new file mode 100644
index 000000000000..0da693b0f7e1
--- /dev/null
+++ b/arch/arm/mach-bcmring/arch.c
@@ -0,0 +1,157 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/module.h>
+
+#include <linux/proc_fs.h>
+#include <linux/sysctl.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/time.h>
+
+#include <asm/mach/arch.h>
+#include <mach/dma.h>
+#include <mach/hardware.h>
+#include <mach/csp/mm_io.h>
+#include <mach/csp/chipcHw_def.h>
+#include <mach/csp/chipcHw_inline.h>
+
+#include <cfg_global.h>
+
+#include "core.h"
+
+HW_DECLARE_SPINLOCK(arch)
+HW_DECLARE_SPINLOCK(gpio)
+#if defined(CONFIG_DEBUG_SPINLOCK)
+    EXPORT_SYMBOL(bcmring_gpio_reg_lock);
+#endif
+
+/* FIXME: temporary solution */
+#define BCM_SYSCTL_REBOOT_WARM               1
+#define CTL_BCM_REBOOT                 112
+
+/* sysctl */
+int bcmring_arch_warm_reboot;   /* do a warm reboot on hard reset */
+
+static struct ctl_table_header *bcmring_sysctl_header;
+
+static struct ctl_table bcmring_sysctl_warm_reboot[] = {
+        {
+         .ctl_name = BCM_SYSCTL_REBOOT_WARM,
+         .procname = "warm",
+         .data = &bcmring_arch_warm_reboot,
+         .maxlen = sizeof(int),
+         .mode = 0644,
+         .proc_handler = &proc_dointvec},
+        {}
+};
+
+static struct ctl_table bcmring_sysctl_reboot[] = {
+        {
+         .ctl_name = CTL_BCM_REBOOT,
+         .procname = "reboot",
+         .mode = 0555,
+         .child = bcmring_sysctl_warm_reboot},
+        {}
+};
+
+static struct platform_device nand_device = {
+        .name = "bcm-nand",
+        .id = -1,
+};
+
+static struct platform_device *devices[] __initdata = {
+        &nand_device,
+};
+
+/****************************************************************************
+*
+*   Called from the customize_machine function in arch/arm/kernel/setup.c
+*
+*   The customize_machine function is tagged as an arch_initcall
+*   (see include/linux/init.h for the order that the various init sections
+*   are called in.
+*
+*****************************************************************************/
+static void __init bcmring_init_machine(void)
+{
+
+        bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot);
+
+        /* Enable spread spectrum */
+        chipcHw_enableSpreadSpectrum();
+
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+
+        bcmring_amba_init();
+
+        dma_init();
+}
+
+/****************************************************************************
+*
+*   Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags
+*   passed in by the boot loader.
+*
+*****************************************************************************/
+
+static void __init bcmring_fixup(struct machine_desc *desc,
+     struct tag *t, char **cmdline, struct meminfo *mi) {
+#ifdef CONFIG_BLK_DEV_INITRD
+        printk(KERN_NOTICE "bcmring_fixup\n");
+        t->hdr.tag = ATAG_CORE;
+        t->hdr.size = tag_size(tag_core);
+        t->u.core.flags = 0;
+        t->u.core.pagesize = PAGE_SIZE;
+        t->u.core.rootdev = 31 << 8 | 0;
+        t = tag_next(t);
+
+        t->hdr.tag = ATAG_MEM;
+        t->hdr.size = tag_size(tag_mem32);
+        t->u.mem.start = CFG_GLOBAL_RAM_BASE;
+        t->u.mem.size = CFG_GLOBAL_RAM_SIZE;
+
+        t = tag_next(t);
+
+        t->hdr.tag = ATAG_NONE;
+        t->hdr.size = 0;
+#endif
+}
+
+/****************************************************************************
+*
+*   Machine Description
+*
+*****************************************************************************/
+
+MACHINE_START(BCMRING, "BCMRING")
+        /* Maintainer: Broadcom Corporation */
+        .phys_io = MM_IO_START,
+        .io_pg_offst = (MM_IO_BASE >> 18) & 0xfffc,
+        .fixup = bcmring_fixup,
+        .map_io = bcmring_map_io,
+        .init_irq = bcmring_init_irq,
+        .timer = &bcmring_timer,
+        .init_machine = bcmring_init_machine
+MACHINE_END
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
new file mode 100644
index 000000000000..14bafc38f2dc
--- /dev/null
+++ b/arch/arm/mach-bcmring/clock.c
@@ -0,0 +1,224 @@
+/*****************************************************************************
+* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <mach/csp/hw_cfg.h>
+#include <mach/csp/chipcHw_def.h>
+#include <mach/csp/chipcHw_reg.h>
+#include <mach/csp/chipcHw_inline.h>
+
+#include <asm/clkdev.h>
+
+#include "clock.h"
+
+#define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
+#define clk_is_pll1(x)          ((x)->type & CLK_TYPE_PLL1)
+#define clk_is_pll2(x)          ((x)->type & CLK_TYPE_PLL2)
+#define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
+#define clk_is_bypassable(x)    ((x)->type & CLK_TYPE_BYPASSABLE)
+
+#define clk_is_using_xtal(x)    ((x)->mode & CLK_MODE_XTAL)
+
+static DEFINE_SPINLOCK(clk_lock);
+
+static void __clk_enable(struct clk *clk)
+{
+        if (!clk)
+                return;
+
+        /* enable parent clock first */
+        if (clk->parent)
+                __clk_enable(clk->parent);
+
+        if (clk->use_cnt++ == 0) {
+                if (clk_is_pll1(clk)) { /* PLL1 */
+                        chipcHw_pll1Enable(clk->rate_hz, 0);
+                } else if (clk_is_pll2(clk)) {  /* PLL2 */
+                        chipcHw_pll2Enable(clk->rate_hz);
+                } else if (clk_is_using_xtal(clk)) {    /* source is crystal */
+                        if (!clk_is_primary(clk))
+                                chipcHw_bypassClockEnable(clk->csp_id);
+                } else {        /* source is PLL */
+                        chipcHw_setClockEnable(clk->csp_id);
+                }
+        }
+}
+
+int clk_enable(struct clk *clk)
+{
+        unsigned long flags;
+
+        if (!clk)
+                return -EINVAL;
+
+        spin_lock_irqsave(&clk_lock, flags);
+        __clk_enable(clk);
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+static void __clk_disable(struct clk *clk)
+{
+        if (!clk)
+                return;
+
+        BUG_ON(clk->use_cnt == 0);
+
+        if (--clk->use_cnt == 0) {
+                if (clk_is_pll1(clk)) { /* PLL1 */
+                        chipcHw_pll1Disable();
+                } else if (clk_is_pll2(clk)) {  /* PLL2 */
+                        chipcHw_pll2Disable();
+                } else if (clk_is_using_xtal(clk)) {    /* source is crystal */
+                        if (!clk_is_primary(clk))
+                                chipcHw_bypassClockDisable(clk->csp_id);
+                } else {        /* source is PLL */
+                        chipcHw_setClockDisable(clk->csp_id);
+                }
+        }
+
+        if (clk->parent)
+                __clk_disable(clk->parent);
+}
+
+void clk_disable(struct clk *clk)
+{
+        unsigned long flags;
+
+        if (!clk)
+                return;
+
+        spin_lock_irqsave(&clk_lock, flags);
+        __clk_disable(clk);
+        spin_unlock_irqrestore(&clk_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (!clk)
+                return 0;
+
+        return clk->rate_hz;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long flags;
+        unsigned long actual;
+        unsigned long rate_hz;
+
+        if (!clk)
+                return -EINVAL;
+
+        if (!clk_is_programmable(clk))
+                return -EINVAL;
+
+        if (clk->use_cnt)
+                return -EBUSY;
+
+        spin_lock_irqsave(&clk_lock, flags);
+        actual = clk->parent->rate_hz;
+        rate_hz = min(actual, rate);
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return rate_hz;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long flags;
+        unsigned long actual;
+        unsigned long rate_hz;
+
+        if (!clk)
+                return -EINVAL;
+
+        if (!clk_is_programmable(clk))
+                return -EINVAL;
+
+        if (clk->use_cnt)
+                return -EBUSY;
+
+        spin_lock_irqsave(&clk_lock, flags);
+        actual = clk->parent->rate_hz;
+        rate_hz = min(actual, rate);
+        rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
+        clk->rate_hz = rate_hz;
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+        if (!clk)
+                return NULL;
+
+        return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        unsigned long flags;
+        struct clk *old_parent;
+
+        if (!clk || !parent)
+                return -EINVAL;
+
+        if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
+                return -EINVAL;
+
+        /* if more than one user, parent is not allowed */
+        if (clk->use_cnt > 1)
+                return -EBUSY;
+
+        if (clk->parent == parent)
+                return 0;
+
+        spin_lock_irqsave(&clk_lock, flags);
+        old_parent = clk->parent;
+        clk->parent = parent;
+        if (clk_is_using_xtal(parent))
+                clk->mode |= CLK_MODE_XTAL;
+        else
+                clk->mode &= (~CLK_MODE_XTAL);
+
+        /* if clock is active */
+        if (clk->use_cnt != 0) {
+                clk->use_cnt--;
+                /* enable clock with the new parent */
+                __clk_enable(clk);
+                /* disable the old parent */
+                __clk_disable(old_parent);
+        }
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h
new file mode 100644
index 000000000000..5e0b98138973
--- /dev/null
+++ b/arch/arm/mach-bcmring/clock.h
@@ -0,0 +1,33 @@
+/*****************************************************************************
+* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#include <mach/csp/chipcHw_def.h>
+
+#define CLK_TYPE_PRIMARY         1      /* primary clock must NOT have a parent */
+#define CLK_TYPE_PLL1            2      /* PPL1 */
+#define CLK_TYPE_PLL2            4      /* PPL2 */
+#define CLK_TYPE_PROGRAMMABLE    8      /* programmable clock rate */
+#define CLK_TYPE_BYPASSABLE      16     /* parent can be changed */
+
+#define CLK_MODE_XTAL            1      /* clock source is from crystal */
+
+struct clk {
+        const char *name;       /* clock name */
+        unsigned int type;      /* clock type */
+        unsigned int mode;      /* current mode */
+        volatile int use_bypass;        /* indicate if it's in bypass mode */
+        chipcHw_CLOCK_e csp_id; /* clock ID for CSP CHIPC */
+        unsigned long rate_hz;  /* clock rate in Hz */
+        unsigned int use_cnt;   /* usage count */
+        struct clk *parent;     /* parent clock */
+};
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
new file mode 100644
index 000000000000..492c649f451e
--- /dev/null
+++ b/arch/arm/mach-bcmring/core.c
@@ -0,0 +1,367 @@
+/*
+ *  derived from linux/arch/arm/mach-versatile/core.c
+ *  linux/arch/arm/mach-bcmring/core.c
+ *
+ *  Copyright (C) 1999 - 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/* Portions copyright Broadcom 2008 */
+
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/amba/bus.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+
+#include <linux/amba/bus.h>
+#include <mach/csp/mm_addr.h>
+#include <mach/hardware.h>
+#include <asm/clkdev.h>
+#include <linux/io.h>
+#include <asm/irq.h>
+#include <asm/hardware/arm_timer.h>
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/mach/mmc.h>
+
+#include <cfg_global.h>
+
+#include "clock.h"
+
+#include <csp/secHw.h>
+#include <mach/csp/secHw_def.h>
+#include <mach/csp/chipcHw_inline.h>
+#include <mach/csp/tmrHw_reg.h>
+
+#define AMBA_DEVICE(name, initname, base, plat, size)       \
+static struct amba_device name##_device = {     \
+   .dev = {                                     \
+      .coherent_dma_mask = ~0,                  \
+      .init_name = initname,                    \
+      .platform_data = plat                     \
+   },                                           \
+   .res = {                                     \
+      .start = MM_ADDR_IO_##base,               \
+                .end = MM_ADDR_IO_##base + (size) - 1,    \
+      .flags = IORESOURCE_MEM                   \
+   },                                           \
+   .dma_mask = ~0,                              \
+   .irq = {                                     \
+      IRQ_##base                                \
+   }                                            \
+}
+
+
+AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
+AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
+
+static struct clk pll1_clk = {
+        .name = "PLL1",
+        .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
+        .rate_hz = 2000000000,
+        .use_cnt = 7,
+};
+
+static struct clk uart_clk = {
+        .name = "UART",
+        .type = CLK_TYPE_PROGRAMMABLE,
+        .csp_id = chipcHw_CLOCK_UART,
+        .rate_hz = HW_CFG_UART_CLK_HZ,
+        .parent = &pll1_clk,
+};
+
+static struct clk_lookup lookups[] = {
+        {                       /* UART0 */
+         .dev_id = "uarta",
+         .clk = &uart_clk,
+         }, {                   /* UART1 */
+             .dev_id = "uartb",
+             .clk = &uart_clk,
+             }
+};
+
+static struct amba_device *amba_devs[] __initdata = {
+        &uartA_device,
+        &uartB_device,
+};
+
+void __init bcmring_amba_init(void)
+{
+        int i;
+        u32 bus_clock;
+
+/* Linux is run initially in non-secure mode. Secure peripherals */
+/* generate FIQ, and must be handled in secure mode. Until we have */
+/* a linux security monitor implementation, keep everything in */
+/* non-secure mode. */
+        chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
+        secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
+                          secHw_BLK_MASK_KEY_SCAN |
+                          secHw_BLK_MASK_TOUCH_SCREEN |
+                          secHw_BLK_MASK_UART0 |
+                          secHw_BLK_MASK_UART1 |
+                          secHw_BLK_MASK_WATCHDOG |
+                          secHw_BLK_MASK_SPUM |
+                          secHw_BLK_MASK_DDR2 |
+                          secHw_BLK_MASK_SPU |
+                          secHw_BLK_MASK_PKA |
+                          secHw_BLK_MASK_RNG |
+                          secHw_BLK_MASK_RTC |
+                          secHw_BLK_MASK_OTP |
+                          secHw_BLK_MASK_BOOT |
+                          secHw_BLK_MASK_MPU |
+                          secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
+
+        /* Only the devices attached to the AMBA bus are enabled just before the bus is */
+        /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
+        /* driver to access these blocks. The bus is probed, and the drivers are loaded. */
+        /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
+        bus_clock = chipcHw_REG_BUS_CLOCK_GE
+            | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
+
+        chipcHw_busInterfaceClockEnable(bus_clock);
+
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                struct amba_device *d = amba_devs[i];
+                amba_device_register(d, &iomem_resource);
+        }
+}
+
+/*
+ * Where is the timer (VA)?
+ */
+#define TIMER0_VA_BASE           MM_IO_BASE_TMR
+#define TIMER1_VA_BASE          (MM_IO_BASE_TMR + 0x20)
+#define TIMER2_VA_BASE          (MM_IO_BASE_TMR + 0x40)
+#define TIMER3_VA_BASE          (MM_IO_BASE_TMR + 0x60)
+
+/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically  150-166 MHz */
+#if defined(CONFIG_ARCH_FPGA11107)
+/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
+/* slow down Linux's sense of time */
+#define TIMER0_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
+#define TIMER1_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
+#define TIMER3_FREQUENCY_MHZ  (tmrHw_HIGH_FREQUENCY_MHZ * 30)
+#define TIMER3_FREQUENCY_KHZ   (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
+#else
+#define TIMER0_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
+#define TIMER1_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
+#define TIMER3_FREQUENCY_MHZ  tmrHw_HIGH_FREQUENCY_MHZ
+#define TIMER3_FREQUENCY_KHZ  (tmrHw_HIGH_FREQUENCY_HZ / 1000)
+#endif
+
+#define TICKS_PER_uSEC     TIMER0_FREQUENCY_MHZ
+
+/*
+ *  These are useconds NOT ticks.
+ *
+ */
+#define mSEC_1                          1000
+#define mSEC_5                          (mSEC_1 * 5)
+#define mSEC_10                         (mSEC_1 * 10)
+#define mSEC_25                         (mSEC_1 * 25)
+#define SEC_1                           (mSEC_1 * 1000)
+
+/*
+ * How long is the timer interval?
+ */
+#define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
+#if TIMER_INTERVAL >= 0x100000
+#define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
+#define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
+#define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
+#elif TIMER_INTERVAL >= 0x10000
+#define TIMER_RELOAD    (TIMER_INTERVAL >> 4)   /* Divide by 16 */
+#define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
+#define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
+#else
+#define TIMER_RELOAD    (TIMER_INTERVAL)
+#define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
+#define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
+#endif
+
+static void timer_set_mode(enum clock_event_mode mode,
+                           struct clock_event_device *clk)
+{
+        unsigned long ctrl;
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
+
+                ctrl = TIMER_CTRL_PERIODIC;
+                ctrl |=
+                    TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE |
+                    TIMER_CTRL_ENABLE;
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* period set, and timer enabled in 'next_event' hook */
+                ctrl = TIMER_CTRL_ONESHOT;
+                ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE;
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        default:
+                ctrl = 0;
+        }
+
+        writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
+}
+
+static int timer_set_next_event(unsigned long evt,
+                                struct clock_event_device *unused)
+{
+        unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
+
+        writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
+        writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
+
+        return 0;
+}
+
+static struct clock_event_device timer0_clockevent = {
+        .name = "timer0",
+        .shift = 32,
+        .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .set_mode = timer_set_mode,
+        .set_next_event = timer_set_next_event,
+};
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = &timer0_clockevent;
+
+        writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction bcmring_timer_irq = {
+        .name = "bcmring Timer Tick",
+        .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler = bcmring_timer_interrupt,
+};
+
+static cycle_t bcmring_get_cycles_timer1(void)
+{
+        return ~readl(TIMER1_VA_BASE + TIMER_VALUE);
+}
+
+static cycle_t bcmring_get_cycles_timer3(void)
+{
+        return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
+}
+
+static struct clocksource clocksource_bcmring_timer1 = {
+        .name = "timer1",
+        .rating = 200,
+        .read = bcmring_get_cycles_timer1,
+        .mask = CLOCKSOURCE_MASK(32),
+        .shift = 20,
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static struct clocksource clocksource_bcmring_timer3 = {
+        .name = "timer3",
+        .rating = 100,
+        .read = bcmring_get_cycles_timer3,
+        .mask = CLOCKSOURCE_MASK(32),
+        .shift = 20,
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int __init bcmring_clocksource_init(void)
+{
+        /* setup timer1 as free-running clocksource */
+        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
+        writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD);
+        writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE);
+        writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
+               TIMER1_VA_BASE + TIMER_CTRL);
+
+        clocksource_bcmring_timer1.mult =
+            clocksource_khz2mult(TIMER1_FREQUENCY_MHZ * 1000,
+                                 clocksource_bcmring_timer1.shift);
+        clocksource_register(&clocksource_bcmring_timer1);
+
+        /* setup timer3 as free-running clocksource */
+        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
+        writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
+        writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
+        writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
+               TIMER3_VA_BASE + TIMER_CTRL);
+
+        clocksource_bcmring_timer3.mult =
+            clocksource_khz2mult(TIMER3_FREQUENCY_KHZ,
+                                 clocksource_bcmring_timer3.shift);
+        clocksource_register(&clocksource_bcmring_timer3);
+
+        return 0;
+}
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+void __init bcmring_init_timer(void)
+{
+        printk(KERN_INFO "bcmring_init_timer\n");
+        /*
+         * Initialise to a known state (all timers off)
+         */
+        writel(0, TIMER0_VA_BASE + TIMER_CTRL);
+        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
+        writel(0, TIMER2_VA_BASE + TIMER_CTRL);
+        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
+
+        /*
+         * Make irqs happen for the system timer
+         */
+        setup_irq(IRQ_TIMER0, &bcmring_timer_irq);
+
+        bcmring_clocksource_init();
+
+        timer0_clockevent.mult =
+            div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
+        timer0_clockevent.max_delta_ns =
+            clockevent_delta2ns(0xffffffff, &timer0_clockevent);
+        timer0_clockevent.min_delta_ns =
+            clockevent_delta2ns(0xf, &timer0_clockevent);
+
+        timer0_clockevent.cpumask = cpumask_of(0);
+        clockevents_register_device(&timer0_clockevent);
+}
+
+struct sys_timer bcmring_timer = {
+        .init = bcmring_init_timer,
+};
diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h
new file mode 100644
index 000000000000..b197ba48e36e
--- /dev/null
+++ b/arch/arm/mach-bcmring/core.h
@@ -0,0 +1,30 @@
+/*
+ *  linux/arch/arm/mach-versatile/core.h
+ *
+ *  Copyright (C) 2004 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/* Portions copyright Broadcom 2008 */
+#ifndef __ASM_ARCH_BCMRING_H
+#define __ASM_ARCH_BCMRING_H
+
+void __init bcmring_amba_init(void);
+void __init bcmring_map_io(void);
+void __init bcmring_init_irq(void);
+
+extern struct sys_timer bcmring_timer;
+#endif
diff --git a/arch/arm/mach-bcmring/csp/Makefile b/arch/arm/mach-bcmring/csp/Makefile
new file mode 100644
index 000000000000..648c0377530e
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/Makefile
@@ -0,0 +1,3 @@
+obj-y += dmac/
+obj-y += tmr/
+obj-y += chipc/
diff --git a/arch/arm/mach-bcmring/csp/chipc/Makefile b/arch/arm/mach-bcmring/csp/chipc/Makefile
new file mode 100644
index 000000000000..673952768ee5
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/Makefile
@@ -0,0 +1 @@
+obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
new file mode 100644
index 000000000000..b3a61d860c65
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
@@ -0,0 +1,776 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    chipcHw.c
+*
+*  @brief   Low level Various CHIP clock controlling routines
+*
+*  @note
+*
+*   These routines provide basic clock controlling functionality only.
+*/
+/****************************************************************************/
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#include <csp/errno.h>
+#include <csp/stdint.h>
+#include <csp/module.h>
+
+#include <mach/csp/chipcHw_def.h>
+#include <mach/csp/chipcHw_inline.h>
+
+#include <csp/reg.h>
+#include <csp/delay.h>
+
+/* ---- Private Constants and Types --------------------------------------- */
+
+/* VPM alignment algorithm uses this */
+#define MAX_PHASE_ADJUST_COUNT         0xFFFF   /* Max number of times allowed to adjust the phase */
+#define MAX_PHASE_ALIGN_ATTEMPTS       10       /* Max number of attempt to align the phase */
+
+/* Local definition of clock type */
+#define PLL_CLOCK                      1        /* PLL Clock */
+#define NON_PLL_CLOCK                  2        /* Divider clock */
+
+static int chipcHw_divide(int num, int denom)
+    __attribute__ ((section(".aramtext")));
+
+/****************************************************************************/
+/**
+*  @brief   Set clock fequency for miscellaneous configurable clocks
+*
+*  This function sets clock frequency
+*
+*  @return  Configured clock frequency in hertz
+*
+*/
+/****************************************************************************/
+chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock    /*  [ IN ] Configurable clock */
+    ) {
+        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
+        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
+        volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
+        uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
+        uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
+        uint32_t dependentClockType = 0;
+        uint32_t vcoHz = 0;
+
+        /* Get VCO frequencies */
+        if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+                uint64_t adjustFreq = 0;
+
+                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
+                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
+                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
+
+                /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
+                adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
+                        (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
+                        chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
+                vcoFreqPll1Hz += (uint32_t) adjustFreq;
+        } else {
+                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
+                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
+                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
+        }
+        vcoFreqPll2Hz =
+            chipcHw_XTAL_FREQ_Hz *
+                 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
+            ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
+
+        switch (clock) {
+        case chipcHw_CLOCK_DDR:
+                pPLLReg = &pChipcHw->DDRClock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ARM:
+                pPLLReg = &pChipcHw->ARMClock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ESW:
+                pPLLReg = &pChipcHw->ESWClock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_VPM:
+                pPLLReg = &pChipcHw->VPMClock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ESW125:
+                pPLLReg = &pChipcHw->ESW125Clock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_UART:
+                pPLLReg = &pChipcHw->UARTClock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_SDIO0:
+                pPLLReg = &pChipcHw->SDIO0Clock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_SDIO1:
+                pPLLReg = &pChipcHw->SDIO1Clock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_SPI:
+                pPLLReg = &pChipcHw->SPIClock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ETM:
+                pPLLReg = &pChipcHw->ETMClock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_USB:
+                pPLLReg = &pChipcHw->USBClock;
+                vcoHz = vcoFreqPll2Hz;
+                break;
+        case chipcHw_CLOCK_LCD:
+                pPLLReg = &pChipcHw->LCDClock;
+                vcoHz = vcoFreqPll2Hz;
+                break;
+        case chipcHw_CLOCK_APM:
+                pPLLReg = &pChipcHw->APMClock;
+                vcoHz = vcoFreqPll2Hz;
+                break;
+        case chipcHw_CLOCK_BUS:
+                pClockCtrl = &pChipcHw->ACLKClock;
+                pDependentClock = &pChipcHw->ARMClock;
+                vcoHz = vcoFreqPll1Hz;
+                dependentClockType = PLL_CLOCK;
+                break;
+        case chipcHw_CLOCK_OTP:
+                pClockCtrl = &pChipcHw->OTPClock;
+                break;
+        case chipcHw_CLOCK_I2C:
+                pClockCtrl = &pChipcHw->I2CClock;
+                break;
+        case chipcHw_CLOCK_I2S0:
+                pClockCtrl = &pChipcHw->I2S0Clock;
+                break;
+        case chipcHw_CLOCK_RTBUS:
+                pClockCtrl = &pChipcHw->RTBUSClock;
+                pDependentClock = &pChipcHw->ACLKClock;
+                dependentClockType = NON_PLL_CLOCK;
+                break;
+        case chipcHw_CLOCK_APM100:
+                pClockCtrl = &pChipcHw->APM100Clock;
+                pDependentClock = &pChipcHw->APMClock;
+                vcoHz = vcoFreqPll2Hz;
+                dependentClockType = PLL_CLOCK;
+                break;
+        case chipcHw_CLOCK_TSC:
+                pClockCtrl = &pChipcHw->TSCClock;
+                break;
+        case chipcHw_CLOCK_LED:
+                pClockCtrl = &pChipcHw->LEDClock;
+                break;
+        case chipcHw_CLOCK_I2S1:
+                pClockCtrl = &pChipcHw->I2S1Clock;
+                break;
+        }
+
+        if (pPLLReg) {
+                /* Obtain PLL clock frequency */
+                if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
+                        /* Return crystal clock frequency when bypassed */
+                        return chipcHw_XTAL_FREQ_Hz;
+                } else if (clock == chipcHw_CLOCK_DDR) {
+                        /* DDR frequency is configured in PLLDivider register */
+                        return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
+                } else {
+                        /* From chip revision number B0, LCD clock is internally divided by 2 */
+                        if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
+                                vcoHz >>= 1;
+                        }
+                        /* Obtain PLL clock frequency using VCO dividers */
+                        return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
+                }
+        } else if (pClockCtrl) {
+                /* Obtain divider clock frequency */
+                uint32_t div;
+                uint32_t freq = 0;
+
+                if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
+                        /* Return crystal clock frequency when bypassed */
+                        return chipcHw_XTAL_FREQ_Hz;
+                } else if (pDependentClock) {
+                        /* Identify the dependent clock frequency */
+                        switch (dependentClockType) {
+                        case PLL_CLOCK:
+                                if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
+                                        /* Use crystal clock frequency when dependent PLL clock is bypassed */
+                                        freq = chipcHw_XTAL_FREQ_Hz;
+                                } else {
+                                        /* Obtain PLL clock frequency using VCO dividers */
+                                        div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
+                                        freq = div ? chipcHw_divide(vcoHz, div) : 0;
+                                }
+                                break;
+                        case NON_PLL_CLOCK:
+                                if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
+                                        freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
+                                } else {
+                                        if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
+                                                /* Use crystal clock frequency when dependent divider clock is bypassed */
+                                                freq = chipcHw_XTAL_FREQ_Hz;
+                                        } else {
+                                                /* Obtain divider clock frequency using XTAL dividers */
+                                                div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                                                freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
+                                        }
+                                }
+                                break;
+                        }
+                } else {
+                        /* Dependent on crystal clock */
+                        freq = chipcHw_XTAL_FREQ_Hz;
+                }
+
+                div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                return chipcHw_divide(freq, (div ? div : 256));
+        }
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Set clock fequency for miscellaneous configurable clocks
+*
+*  This function sets clock frequency
+*
+*  @return  Configured clock frequency in Hz
+*
+*/
+/****************************************************************************/
+chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,   /*  [ IN ] Configurable clock */
+                                       uint32_t freq    /*  [ IN ] Clock frequency in Hz */
+    ) {
+        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
+        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
+        volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
+        uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
+        uint32_t desVcoFreqPll1Hz = 0;  /* Desired VCO frequency for PLL1 in Hz */
+        uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
+        uint32_t dependentClockType = 0;
+        uint32_t vcoHz = 0;
+        uint32_t desVcoHz = 0;
+
+        /* Get VCO frequencies */
+        if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+                uint64_t adjustFreq = 0;
+
+                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
+                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
+                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
+
+                /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
+                adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
+                        (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
+                        chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
+                vcoFreqPll1Hz += (uint32_t) adjustFreq;
+
+                /* Desired VCO frequency */
+                desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
+                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
+                    (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
+        } else {
+                vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
+                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
+                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
+        }
+        vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
+            ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
+
+        switch (clock) {
+        case chipcHw_CLOCK_DDR:
+                /* Configure the DDR_ctrl:BUS ratio settings */
+                {
+                        REG_LOCAL_IRQ_SAVE;
+                        /* Dvide DDR_phy by two to obtain DDR_ctrl clock */
+                        pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
+                                << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
+                        REG_LOCAL_IRQ_RESTORE;
+                }
+                pPLLReg = &pChipcHw->DDRClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ARM:
+                pPLLReg = &pChipcHw->ARMClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ESW:
+                pPLLReg = &pChipcHw->ESWClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_VPM:
+                /* Configure the VPM:BUS ratio settings */
+                {
+                        REG_LOCAL_IRQ_SAVE;
+                        pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
+                                << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
+                        REG_LOCAL_IRQ_RESTORE;
+                }
+                pPLLReg = &pChipcHw->VPMClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ESW125:
+                pPLLReg = &pChipcHw->ESW125Clock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_UART:
+                pPLLReg = &pChipcHw->UARTClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_SDIO0:
+                pPLLReg = &pChipcHw->SDIO0Clock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_SDIO1:
+                pPLLReg = &pChipcHw->SDIO1Clock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_SPI:
+                pPLLReg = &pChipcHw->SPIClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ETM:
+                pPLLReg = &pChipcHw->ETMClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_USB:
+                pPLLReg = &pChipcHw->USBClock;
+                vcoHz = vcoFreqPll2Hz;
+                desVcoHz = vcoFreqPll2Hz;
+                break;
+        case chipcHw_CLOCK_LCD:
+                pPLLReg = &pChipcHw->LCDClock;
+                vcoHz = vcoFreqPll2Hz;
+                desVcoHz = vcoFreqPll2Hz;
+                break;
+        case chipcHw_CLOCK_APM:
+                pPLLReg = &pChipcHw->APMClock;
+                vcoHz = vcoFreqPll2Hz;
+                desVcoHz = vcoFreqPll2Hz;
+                break;
+        case chipcHw_CLOCK_BUS:
+                pClockCtrl = &pChipcHw->ACLKClock;
+                pDependentClock = &pChipcHw->ARMClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                dependentClockType = PLL_CLOCK;
+                break;
+        case chipcHw_CLOCK_OTP:
+                pClockCtrl = &pChipcHw->OTPClock;
+                break;
+        case chipcHw_CLOCK_I2C:
+                pClockCtrl = &pChipcHw->I2CClock;
+                break;
+        case chipcHw_CLOCK_I2S0:
+                pClockCtrl = &pChipcHw->I2S0Clock;
+                break;
+        case chipcHw_CLOCK_RTBUS:
+                pClockCtrl = &pChipcHw->RTBUSClock;
+                pDependentClock = &pChipcHw->ACLKClock;
+                dependentClockType = NON_PLL_CLOCK;
+                break;
+        case chipcHw_CLOCK_APM100:
+                pClockCtrl = &pChipcHw->APM100Clock;
+                pDependentClock = &pChipcHw->APMClock;
+                vcoHz = vcoFreqPll2Hz;
+                desVcoHz = vcoFreqPll2Hz;
+                dependentClockType = PLL_CLOCK;
+                break;
+        case chipcHw_CLOCK_TSC:
+                pClockCtrl = &pChipcHw->TSCClock;
+                break;
+        case chipcHw_CLOCK_LED:
+                pClockCtrl = &pChipcHw->LEDClock;
+                break;
+        case chipcHw_CLOCK_I2S1:
+                pClockCtrl = &pChipcHw->I2S1Clock;
+                break;
+        }
+
+        if (pPLLReg) {
+                /* Select XTAL as bypass source */
+                reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO);
+                reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
+                /* For DDR settings use only the PLL divider clock */
+                if (pPLLReg == &pChipcHw->DDRClock) {
+                        /* Set M1DIV for PLL1, which controls the DDR clock */
+                        reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
+                        /* Calculate expected frequency */
+                        freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
+                } else {
+                        /* From chip revision number B0, LCD clock is internally divided by 2 */
+                        if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
+                                desVcoHz >>= 1;
+                                vcoHz >>= 1;
+                        }
+                        /* Set MDIV to change the frequency */
+                        reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
+                        reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
+                        /* Calculate expected frequency */
+                        freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
+                }
+                /* Wait for for atleast 200ns as per the protocol to change frequency */
+                udelay(1);
+                /* Do not bypass */
+                reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
+                /* Return the configured frequency */
+                return freq;
+        } else if (pClockCtrl) {
+                uint32_t divider = 0;
+
+                /* Divider clock should not be bypassed  */
+                reg32_modify_and(pClockCtrl,
+                                 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
+
+                /* Identify the clock source */
+                if (pDependentClock) {
+                        switch (dependentClockType) {
+                        case PLL_CLOCK:
+                                divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
+                                break;
+                        case NON_PLL_CLOCK:
+                                {
+                                        uint32_t sourceClock = 0;
+
+                                        if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
+                                                sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
+                                        } else {
+                                                uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                                                sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
+                                        }
+                                        divider = chipcHw_divide(sourceClock, freq);
+                                }
+                                break;
+                        }
+                } else {
+                        divider = chipcHw_divide(chipcHw_XTAL_FREQ_Hz, freq);
+                }
+
+                if (divider) {
+                        REG_LOCAL_IRQ_SAVE;
+                        /* Set the divider to obtain the required frequency */
+                        *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK);
+                        REG_LOCAL_IRQ_RESTORE;
+                        return freq;
+                }
+        }
+
+        return 0;
+}
+
+EXPORT_SYMBOL(chipcHw_setClockFrequency);
+
+/****************************************************************************/
+/**
+*  @brief   Set VPM clock in sync with BUS clock for Chip Rev #A0
+*
+*  This function does the phase adjustment between VPM and BUS clock
+*
+*  @return >= 0 : On success (# of adjustment required)
+*            -1 : On failure
+*
+*/
+/****************************************************************************/
+static int vpmPhaseAlignA0(void)
+{
+        uint32_t phaseControl;
+        uint32_t phaseValue;
+        uint32_t prevPhaseComp;
+        int iter = 0;
+        int adjustCount = 0;
+        int count = 0;
+
+        for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) {
+                phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
+                phaseValue = 0;
+                prevPhaseComp = 0;
+
+                /* Step 1: Look for falling PH_COMP transition */
+
+                /* Read the contents of VPM Clock resgister */
+                phaseValue = pChipcHw->VPMClock;
+                do {
+                        /* Store previous value of phase comparator */
+                        prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
+                        /* Change the value of PH_CTRL. */
+                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        /* Wait atleast 20 ns */
+                        udelay(1);
+                        /* Toggle the LOAD_CH after phase control is written. */
+                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        /* Read the contents of  VPM Clock resgister. */
+                        phaseValue = pChipcHw->VPMClock;
+
+                        if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
+                                phaseControl = (0x3F & (phaseControl - 1));
+                        } else {
+                                /* Increment to the Phase count value for next write, if Phase is not stable. */
+                                phaseControl = (0x3F & (phaseControl + 1));
+                        }
+                        /* Count number of adjustment made */
+                        adjustCount++;
+                } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || /* Look for a transition */
+                          ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) &&  /* Look for a falling edge */
+                         (adjustCount < MAX_PHASE_ADJUST_COUNT) /* Do not exceed the limit while trying */
+                    );
+
+                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
+                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
+                        return -1;
+                }
+
+                /* Step 2: Keep moving forward to make sure falling PH_COMP transition was valid */
+
+                for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
+                        phaseControl = (0x3F & (phaseControl + 1));
+                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        /* Wait atleast 20 ns */
+                        udelay(1);
+                        /* Toggle the LOAD_CH after phase control is written. */
+                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        phaseValue = pChipcHw->VPMClock;
+                        /* Count number of adjustment made */
+                        adjustCount++;
+                }
+
+                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
+                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
+                        return -1;
+                }
+
+                if (count != 5) {
+                        /* Detected false transition */
+                        continue;
+                }
+
+                /* Step 3: Keep moving backward to make sure falling PH_COMP transition was stable */
+
+                for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
+                        phaseControl = (0x3F & (phaseControl - 1));
+                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        /* Wait atleast 20 ns */
+                        udelay(1);
+                        /* Toggle the LOAD_CH after phase control is written. */
+                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        phaseValue = pChipcHw->VPMClock;
+                        /* Count number of adjustment made */
+                        adjustCount++;
+                }
+
+                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
+                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
+                        return -1;
+                }
+
+                if (count != 3) {
+                        /* Detected noisy transition */
+                        continue;
+                }
+
+                /* Step 4: Keep moving backward before the original transition took place. */
+
+                for (count = 0; (count < 5); count++) {
+                        phaseControl = (0x3F & (phaseControl - 1));
+                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        /* Wait atleast 20 ns */
+                        udelay(1);
+                        /* Toggle the LOAD_CH after phase control is written. */
+                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        phaseValue = pChipcHw->VPMClock;
+                        /* Count number of adjustment made */
+                        adjustCount++;
+                }
+
+                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
+                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
+                        return -1;
+                }
+
+                if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0) {
+                        /* Detected false transition */
+                        continue;
+                }
+
+                /* Step 5: Re discover the valid transition */
+
+                do {
+                        /* Store previous value of phase comparator */
+                        prevPhaseComp = phaseValue;
+                        /* Change the value of PH_CTRL. */
+                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        /* Wait atleast 20 ns */
+                        udelay(1);
+                        /* Toggle the LOAD_CH after phase control is written. */
+                        pChipcHw->VPMClock ^=
+                            chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        /* Read the contents of  VPM Clock resgister. */
+                        phaseValue = pChipcHw->VPMClock;
+
+                        if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
+                                phaseControl = (0x3F & (phaseControl - 1));
+                        } else {
+                                /* Increment to the Phase count value for next write, if Phase is not stable. */
+                                phaseControl = (0x3F & (phaseControl + 1));
+                        }
+
+                        /* Count number of adjustment made */
+                        adjustCount++;
+                } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && (adjustCount < MAX_PHASE_ADJUST_COUNT));
+
+                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
+                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries  */
+                        return -1;
+                } else {
+                        /* Valid phase must have detected */
+                        break;
+                }
+        }
+
+        /* For VPM Phase should be perfectly aligned. */
+        phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
+        {
+                REG_LOCAL_IRQ_SAVE;
+
+                pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT);
+                /* Load new phase value */
+                pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+
+                REG_LOCAL_IRQ_RESTORE;
+        }
+        /* Return the status */
+        return (int)adjustCount;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Set VPM clock in sync with BUS clock
+*
+*  This function does the phase adjustment between VPM and BUS clock
+*
+*  @return >= 0 : On success (# of adjustment required)
+*            -1 : On failure
+*
+*/
+/****************************************************************************/
+int chipcHw_vpmPhaseAlign(void)
+{
+
+        if (chipcHw_getChipRevisionNumber() == chipcHw_REV_NUMBER_A0) {
+                return vpmPhaseAlignA0();
+        } else {
+                uint32_t phaseControl = chipcHw_getVpmPhaseControl();
+                uint32_t phaseValue = 0;
+                int adjustCount = 0;
+
+                /* Disable VPM access */
+                pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+                /* Disable HW VPM phase alignment  */
+                chipcHw_vpmHwPhaseAlignDisable();
+                /* Enable SW VPM phase alignment  */
+                chipcHw_vpmSwPhaseAlignEnable();
+                /* Adjust VPM phase */
+                while (adjustCount < MAX_PHASE_ADJUST_COUNT) {
+                        phaseValue = chipcHw_getVpmHwPhaseAlignStatus();
+
+                        /* Adjust phase control value */
+                        if (phaseValue > 0xF) {
+                                /* Increment phase control value */
+                                phaseControl++;
+                        } else if (phaseValue < 0xF) {
+                                /* Decrement phase control value */
+                                phaseControl--;
+                        } else {
+                                /* Enable VPM access */
+                                pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+                                /* Return adjust count */
+                                return adjustCount;
+                        }
+                        /* Change the value of PH_CTRL. */
+                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        /* Wait atleast 20 ns */
+                        udelay(1);
+                        /* Toggle the LOAD_CH after phase control is written. */
+                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        /* Count adjustment */
+                        adjustCount++;
+                }
+        }
+
+        /* Disable VPM access */
+        pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+        return -1;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Local Divide function
+*
+*  This function does the divide
+*
+*  @return divide value
+*
+*/
+/****************************************************************************/
+static int chipcHw_divide(int num, int denom)
+{
+        int r;
+        int t = 1;
+
+        /* Shift denom and t up to the largest value to optimize algorithm */
+        /* t contains the units of each divide */
+        while ((denom & 0x40000000) == 0) {     /* fails if denom=0 */
+                denom = denom << 1;
+                t = t << 1;
+        }
+
+        /* Intialize the result */
+        r = 0;
+
+        do {
+                /* Determine if there exists a positive remainder */
+                if ((num - denom) >= 0) {
+                        /* Accumlate t to the result and calculate a new remainder */
+                        num = num - denom;
+                        r = r + t;
+                }
+                /* Continue to shift denom and shift t down to 0 */
+                denom = denom >> 1;
+                t = t >> 1;
+        } while (t != 0);
+
+        return r;
+}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
new file mode 100644
index 000000000000..367df75d4bb3
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
@@ -0,0 +1,293 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    chipcHw_init.c
+*
+*  @brief   Low level CHIPC PLL configuration functions
+*
+*  @note
+*
+*   These routines provide basic PLL controlling functionality only.
+*/
+/****************************************************************************/
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#include <csp/errno.h>
+#include <csp/stdint.h>
+#include <csp/module.h>
+
+#include <mach/csp/chipcHw_def.h>
+#include <mach/csp/chipcHw_inline.h>
+
+#include <csp/reg.h>
+#include <csp/delay.h>
+/* ---- Private Constants and Types --------------------------------------- */
+
+/*
+    Calculation for NDIV_i to obtain VCO frequency
+    -----------------------------------------------
+
+        Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f)
+        for Freq_vco = VCO_FREQ_MHz
+                Freq_ref = chipcHw_XTAL_FREQ_Hz
+                PLL_P1 = PLL_P2 = 1
+                and
+                PLL_NDIV_f = 0
+
+        We get:
+                PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz
+
+    Calculation for PLL MDIV to obtain frequency Freq_x for channel x
+    -----------------------------------------------------------------
+                Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = VCO_FREQ_MHz / PLL_MDIV_x
+
+                PLL_MDIV_x = VCO_FREQ_MHz / Freq_x
+*/
+
+/* ---- Private Variables ------------------------------------------------- */
+/****************************************************************************/
+/**
+*  @brief  Initializes the PLL2
+*
+*  This function initializes the PLL2
+*
+*/
+/****************************************************************************/
+void chipcHw_pll2Enable(uint32_t vcoFreqHz)
+{
+        uint32_t pllPreDivider2 = 0;
+
+        {
+                REG_LOCAL_IRQ_SAVE;
+                pChipcHw->PLLConfig2 =
+                    chipcHw_REG_PLL_CONFIG_D_RESET |
+                    chipcHw_REG_PLL_CONFIG_A_RESET;
+
+                pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
+                    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
+                    (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
+                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
+                    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
+                     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
+                    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
+                     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
+
+                /* Enable CHIPC registers to control the PLL */
+                pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
+
+                /* Set pre divider to get desired VCO frequency */
+                pChipcHw->PLLPreDivider2 = pllPreDivider2;
+                /* Set NDIV Frac */
+                pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
+
+                /* This has to be removed once the default values are fixed for PLL2. */
+                pChipcHw->PLLControl12 = 0x38000700;
+                pChipcHw->PLLControl22 = 0x00000015;
+
+                /* Reset PLL2 */
+                if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
+                        pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
+                            chipcHw_REG_PLL_CONFIG_A_RESET |
+                            chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
+                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                } else {
+                        pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
+                            chipcHw_REG_PLL_CONFIG_A_RESET |
+                            chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
+                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                }
+                REG_LOCAL_IRQ_RESTORE;
+        }
+
+        /* Insert certain amount of delay before deasserting ARESET. */
+        udelay(1);
+
+        {
+                REG_LOCAL_IRQ_SAVE;
+                /* Remove analog reset and Power on the PLL */
+                pChipcHw->PLLConfig2 &=
+                    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
+                      chipcHw_REG_PLL_CONFIG_POWER_DOWN);
+
+                REG_LOCAL_IRQ_RESTORE;
+
+        }
+
+        /* Wait until PLL is locked */
+        while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
+                ;
+
+        {
+                REG_LOCAL_IRQ_SAVE;
+                /* Remove digital reset */
+                pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
+
+                REG_LOCAL_IRQ_RESTORE;
+        }
+}
+
+EXPORT_SYMBOL(chipcHw_pll2Enable);
+
+/****************************************************************************/
+/**
+*  @brief  Initializes the PLL1
+*
+*  This function initializes the PLL1
+*
+*/
+/****************************************************************************/
+void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
+{
+        uint32_t pllPreDivider = 0;
+
+        {
+                REG_LOCAL_IRQ_SAVE;
+
+                pChipcHw->PLLConfig =
+                    chipcHw_REG_PLL_CONFIG_D_RESET |
+                    chipcHw_REG_PLL_CONFIG_A_RESET;
+                /* Setting VCO frequency */
+                if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
+                        pllPreDivider =
+                            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 |
+                            ((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) -
+                              1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
+                            (chipcHw_REG_PLL_PREDIVIDER_P1 <<
+                             chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
+                            (chipcHw_REG_PLL_PREDIVIDER_P2 <<
+                             chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
+                } else {
+                        pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
+                            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
+                            (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
+                             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
+                            (chipcHw_REG_PLL_PREDIVIDER_P1 <<
+                             chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
+                            (chipcHw_REG_PLL_PREDIVIDER_P2 <<
+                             chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
+                }
+
+                /* Enable CHIPC registers to control the PLL */
+                pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
+
+                /* Set pre divider to get desired VCO frequency */
+                pChipcHw->PLLPreDivider = pllPreDivider;
+                /* Set NDIV Frac */
+                if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
+                        pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
+                            chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
+                } else {
+                        pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
+                            chipcHw_REG_PLL_DIVIDER_NDIV_f;
+                }
+
+                /* Reset PLL1 */
+                if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
+                        pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
+                            chipcHw_REG_PLL_CONFIG_A_RESET |
+                            chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
+                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                } else {
+                        pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
+                            chipcHw_REG_PLL_CONFIG_A_RESET |
+                            chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
+                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                }
+
+                REG_LOCAL_IRQ_RESTORE;
+
+                /* Insert certain amount of delay before deasserting ARESET. */
+                udelay(1);
+
+                {
+                        REG_LOCAL_IRQ_SAVE;
+                        /* Remove analog reset and Power on the PLL */
+                        pChipcHw->PLLConfig &=
+                            ~(chipcHw_REG_PLL_CONFIG_A_RESET |
+                              chipcHw_REG_PLL_CONFIG_POWER_DOWN);
+                        REG_LOCAL_IRQ_RESTORE;
+                }
+
+                /* Wait until PLL is locked */
+                while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
+                       || !(pChipcHw->
+                            PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
+                        ;
+
+                /* Remove digital reset */
+                {
+                        REG_LOCAL_IRQ_SAVE;
+                        pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
+                        REG_LOCAL_IRQ_RESTORE;
+                }
+        }
+}
+
+EXPORT_SYMBOL(chipcHw_pll1Enable);
+
+/****************************************************************************/
+/**
+*  @brief  Initializes the chipc module
+*
+*  This function initializes the PLLs and core system clocks
+*
+*/
+/****************************************************************************/
+
+void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam       /*  [ IN ] Misc chip initialization parameter */
+    ) {
+#if !(defined(__KERNEL__) && !defined(STANDALONE))
+        delay_init();
+#endif
+
+        /* Do not program PLL, when warm reset */
+        if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) {
+                chipcHw_pll1Enable(initParam->pllVcoFreqHz,
+                                   initParam->ssSupport);
+                chipcHw_pll2Enable(initParam->pll2VcoFreqHz);
+        } else {
+                /* Clear sticky bits */
+                chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET);
+        }
+        /* Clear sticky bits */
+        chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
+
+        /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
+        pChipcHw->ACLKClock =
+            (pChipcHw->
+             ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
+                                                                 armBusRatio &
+                                                                 chipcHw_REG_ACLKClock_CLK_DIV_MASK);
+
+        /* Set various core component frequencies. The order in which this is done is important for some. */
+        /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
+        /* frequency to find its ratio with the BUS.  Hence we must set the ARM first, followed by the BUS,  */
+        /* then VPM and RTBUS. */
+
+        chipcHw_setClockFrequency(chipcHw_CLOCK_ARM,
+                                  initParam->busClockFreqHz *
+                                  initParam->armBusRatio);
+        chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz);
+        chipcHw_setClockFrequency(chipcHw_CLOCK_VPM,
+                                  initParam->busClockFreqHz *
+                                  initParam->vpmBusRatio);
+        chipcHw_setClockFrequency(chipcHw_CLOCK_DDR,
+                                  initParam->busClockFreqHz *
+                                  initParam->ddrBusRatio);
+        chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS,
+                                  initParam->busClockFreqHz / 2);
+}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
new file mode 100644
index 000000000000..2671d8896bbb
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
@@ -0,0 +1,124 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/stdint.h>
+#include <mach/csp/chipcHw_def.h>
+#include <mach/csp/chipcHw_inline.h>
+#include <csp/intcHw.h>
+#include <csp/cache.h>
+
+/* ---- Private Constants and Types --------------------------------------- */
+/* ---- Private Variables ------------------------------------------------- */
+void chipcHw_reset_run_from_aram(void);
+
+typedef void (*RUNFUNC) (void);
+
+/****************************************************************************/
+/**
+*  @brief   warmReset
+*
+*  @note warmReset configures the clocks which are not reset back to the state
+*   required to execute on reset.  To do so we need to copy the code into internal
+*   memory to change the ARM clock while we are not executing from DDR.
+*/
+/****************************************************************************/
+void chipcHw_reset(uint32_t mask)
+{
+        int i = 0;
+        RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM;
+
+        /* Disable all interrupts */
+        intcHw_irq_disable(INTCHW_INTC0, 0xffffffff);
+        intcHw_irq_disable(INTCHW_INTC1, 0xffffffff);
+        intcHw_irq_disable(INTCHW_SINTC, 0xffffffff);
+
+        {
+                REG_LOCAL_IRQ_SAVE;
+                if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) {
+                        chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
+                }
+                /* Bypass the PLL clocks before reboot */
+                pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
+                pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
+
+                /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
+                do {
+                        ((uint32_t *) MM_IO_BASE_ARAM)[i] =
+                            ((uint32_t *) &chipcHw_reset_run_from_aram)[i];
+                        i++;
+                } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f);  /* 0xe1a0f00f == asm ("mov r15, r15"); */
+
+                CSP_CACHE_FLUSH_ALL;
+
+                /* run the function from ARAM */
+                runFunc();
+
+                /* Code will never get here, but include it to balance REG_LOCAL_IRQ_SAVE above */
+                REG_LOCAL_IRQ_RESTORE;
+        }
+}
+
+/* This function must run from internal memory */
+void chipcHw_reset_run_from_aram(void)
+{
+/* Make sure, pipeline is filled with instructions coming from ARAM */
+__asm (" nop                                                            \n\t"
+                " nop                                                            \n\t"
+#if defined(__KERNEL__) && !defined(STANDALONE)
+                " MRC      p15,#0x0,r0,c1,c0,#0                                  \n\t"
+                " BIC      r0,r0,#0xd                                            \n\t"
+                " MCR      p15,#0x0,r0,c1,c0,#0                                  \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+#endif
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+/* Bypass the ARM clock and switch to XTAL clock */
+                " MOV      r2,#0x80000000                                        \n\t"
+                " LDR      r3,[r2,#8]                                            \n\t"
+                " ORR      r3,r3,#0x20000                                        \n\t"
+                " STR      r3,[r2,#8]                                            \n\t"
+
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+/* Issue reset */
+                " MOV      r3,#0x2                                               \n\t"
+                " STR      r3,[r2,#0x80]                                         \n\t"
+/* End here */
+                " MOV      pc,pc                                                 \n\t");
+/* 0xe1a0f00f ==  asm ("mov r15, r15"); */
+}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
new file mode 100644
index 000000000000..54ad964fe94c
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
@@ -0,0 +1,64 @@
+/*****************************************************************************
+* Copyright 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    chipcHw_str.c
+*
+*  @brief   Contains strings which are useful to linux and csp
+*
+*  @note
+*/
+/****************************************************************************/
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#include <mach/csp/chipcHw_inline.h>
+
+/* ---- Private Constants and Types --------------------------------------- */
+
+static const char *gMuxStr[] = {
+        "GPIO",                 /* 0 */
+        "KeyPad",               /* 1 */
+        "I2C-Host",             /* 2 */
+        "SPI",                  /* 3 */
+        "Uart",                 /* 4 */
+        "LED-Mtx-P",            /* 5 */
+        "LED-Mtx-S",            /* 6 */
+        "SDIO-0",               /* 7 */
+        "SDIO-1",               /* 8 */
+        "PCM",                  /* 9 */
+        "I2S",                  /* 10 */
+        "ETM",                  /* 11 */
+        "Debug",                /* 12 */
+        "Misc",                 /* 13 */
+        "0xE",                  /* 14 */
+        "0xF",                  /* 15 */
+};
+
+/****************************************************************************/
+/**
+*  @brief   Retrieves a string representation of the mux setting for a pin.
+*
+*  @return  Pointer to a character string.
+*/
+/****************************************************************************/
+
+const char *chipcHw_getGpioPinFunctionStr(int pin)
+{
+        if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) {
+                return "";
+        }
+
+        return gMuxStr[chipcHw_getGpioPinFunction(pin)];
+}
diff --git a/arch/arm/mach-bcmring/csp/dmac/Makefile b/arch/arm/mach-bcmring/csp/dmac/Makefile
new file mode 100644
index 000000000000..fb1104fe56b2
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/dmac/Makefile
@@ -0,0 +1 @@
+obj-y += dmacHw.o dmacHw_extra.o
\ No newline at end of file
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
new file mode 100644
index 000000000000..7b9bac2d79a5
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
@@ -0,0 +1,917 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    dmacHw.c
+*
+*  @brief   Low level DMA controller driver routines
+*
+*  @note
+*
+*   These routines provide basic DMA functionality only.
+*/
+/****************************************************************************/
+
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/stdint.h>
+#include <csp/string.h>
+#include <stddef.h>
+
+#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw_reg.h>
+#include <mach/csp/dmacHw_priv.h>
+#include <mach/csp/chipcHw_inline.h>
+
+/* ---- External Function Prototypes ------------------------------------- */
+
+/* Allocate DMA control blocks */
+dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];
+
+uint32_t dmaChannelCount_0 = dmacHw_MAX_CHANNEL_COUNT / 2;
+uint32_t dmaChannelCount_1 = dmacHw_MAX_CHANNEL_COUNT / 2;
+
+/****************************************************************************/
+/**
+*  @brief   Get maximum FIFO for a DMA channel
+*
+*  @return  Maximum allowable FIFO size
+*
+*
+*/
+/****************************************************************************/
+static uint32_t GetFifoSize(dmacHw_HANDLE_t handle      /*   [ IN ] DMA Channel handle */
+    ) {
+        uint32_t val = 0;
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        dmacHw_MISC_t *pMiscReg =
+            (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
+
+        switch (pCblk->channel) {
+        case 0:
+                val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
+                break;
+        case 1:
+                val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
+                break;
+        case 2:
+                val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
+                break;
+        case 3:
+                val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
+                break;
+        case 4:
+                val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
+                break;
+        case 5:
+                val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
+                break;
+        case 6:
+                val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
+                break;
+        case 7:
+                val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
+                break;
+        }
+
+        if (val <= 0x4) {
+                return 8 << val;
+        } else {
+                dmacHw_ASSERT(0);
+        }
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Program channel register to initiate transfer
+*
+*  @return  void
+*
+*
+*  @note
+*     - Descriptor buffer MUST ALWAYS be flushed before calling this function
+*     - This function should also be called from ISR to program the channel with
+*       pending descriptors
+*/
+/****************************************************************************/
+void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,    /*   [ IN ] DMA Channel handle */
+                             dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
+                             void *pDescriptor  /*   [ IN ] Descriptor buffer */
+    ) {
+        dmacHw_DESC_RING_t *pRing;
+        dmacHw_DESC_t *pProg;
+        dmacHw_CBLK_t *pCblk;
+
+        pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        pRing = dmacHw_GET_DESC_RING(pDescriptor);
+
+        if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
+                /* Not safe yet to program the channel */
+                return;
+        }
+
+        if (pCblk->varDataStarted) {
+                if (pCblk->descUpdated) {
+                        pCblk->descUpdated = 0;
+                        pProg =
+                            (dmacHw_DESC_t *) ((uint32_t)
+                                               dmacHw_REG_LLP(pCblk->module,
+                                                              pCblk->channel) +
+                                               pRing->virt2PhyOffset);
+
+                        /* Load descriptor if not loaded */
+                        if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) {
+                                dmacHw_SET_SAR(pCblk->module, pCblk->channel,
+                                               pProg->sar);
+                                dmacHw_SET_DAR(pCblk->module, pCblk->channel,
+                                               pProg->dar);
+                                dmacHw_REG_CTL_LO(pCblk->module,
+                                                  pCblk->channel) =
+                                    pProg->ctl.lo;
+                                dmacHw_REG_CTL_HI(pCblk->module,
+                                                  pCblk->channel) =
+                                    pProg->ctl.hi;
+                        } else if (pProg == (dmacHw_DESC_t *) pRing->pEnd->llp) {
+                                /* Return as end descriptor is processed */
+                                return;
+                        } else {
+                                dmacHw_ASSERT(0);
+                        }
+                } else {
+                        return;
+                }
+        } else {
+                if (pConfig->transferMode == dmacHw_TRANSFER_MODE_PERIODIC) {
+                        /* Do not make a single chain, rather process one descriptor at a time */
+                        pProg = pRing->pHead;
+                        /* Point to the next descriptor for next iteration */
+                        dmacHw_NEXT_DESC(pRing, pHead);
+                } else {
+                        /* Return if no more pending descriptor */
+                        if (pRing->pEnd == NULL) {
+                                return;
+                        }
+
+                        pProg = pRing->pProg;
+                        if (pConfig->transferMode ==
+                            dmacHw_TRANSFER_MODE_CONTINUOUS) {
+                                /* Make sure a complete ring can be formed */
+                                dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pEnd->
+                                              llp == pRing->pProg);
+                                /* Make sure pProg pointing to the pHead */
+                                dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pProg ==
+                                              pRing->pHead);
+                                /* Make a complete ring */
+                                do {
+                                        pRing->pProg->ctl.lo |=
+                                            (dmacHw_REG_CTL_LLP_DST_EN |
+                                             dmacHw_REG_CTL_LLP_SRC_EN);
+                                        pRing->pProg =
+                                            (dmacHw_DESC_t *) pRing->pProg->llp;
+                                } while (pRing->pProg != pRing->pHead);
+                        } else {
+                                /* Make a single long chain */
+                                while (pRing->pProg != pRing->pEnd) {
+                                        pRing->pProg->ctl.lo |=
+                                            (dmacHw_REG_CTL_LLP_DST_EN |
+                                             dmacHw_REG_CTL_LLP_SRC_EN);
+                                        pRing->pProg =
+                                            (dmacHw_DESC_t *) pRing->pProg->llp;
+                                }
+                        }
+                }
+
+                /* Program the channel registers */
+                dmacHw_SET_SAR(pCblk->module, pCblk->channel, pProg->sar);
+                dmacHw_SET_DAR(pCblk->module, pCblk->channel, pProg->dar);
+                dmacHw_SET_LLP(pCblk->module, pCblk->channel,
+                               (uint32_t) pProg - pRing->virt2PhyOffset);
+                dmacHw_REG_CTL_LO(pCblk->module, pCblk->channel) =
+                    pProg->ctl.lo;
+                dmacHw_REG_CTL_HI(pCblk->module, pCblk->channel) =
+                    pProg->ctl.hi;
+                if (pRing->pEnd) {
+                        /* Remember the descriptor to use next */
+                        pRing->pProg = (dmacHw_DESC_t *) pRing->pEnd->llp;
+                }
+                /* Indicate no more pending descriptor  */
+                pRing->pEnd = (dmacHw_DESC_t *) NULL;
+        }
+        /* Start DMA operation */
+        dmacHw_DMA_START(pCblk->module, pCblk->channel);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Initializes DMA
+*
+*  This function initializes DMA CSP driver
+*
+*  @note
+*     Must be called before using any DMA channel
+*/
+/****************************************************************************/
+void dmacHw_initDma(void)
+{
+
+        uint32_t i = 0;
+
+        dmaChannelCount_0 = dmacHw_GET_NUM_CHANNEL(0);
+        dmaChannelCount_1 = dmacHw_GET_NUM_CHANNEL(1);
+
+        /* Enable access to the DMA block */
+        chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC0);
+        chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC1);
+
+        if ((dmaChannelCount_0 + dmaChannelCount_1) > dmacHw_MAX_CHANNEL_COUNT) {
+                dmacHw_ASSERT(0);
+        }
+
+        memset((void *)dmacHw_gCblk, 0,
+               sizeof(dmacHw_CBLK_t) * (dmaChannelCount_0 + dmaChannelCount_1));
+        for (i = 0; i < dmaChannelCount_0; i++) {
+                dmacHw_gCblk[i].module = 0;
+                dmacHw_gCblk[i].channel = i;
+        }
+        for (i = 0; i < dmaChannelCount_1; i++) {
+                dmacHw_gCblk[i + dmaChannelCount_0].module = 1;
+                dmacHw_gCblk[i + dmaChannelCount_0].channel = i;
+        }
+}
+
+/****************************************************************************/
+/**
+*  @brief   Exit function for  DMA
+*
+*  This function isolates DMA from the system
+*
+*/
+/****************************************************************************/
+void dmacHw_exitDma(void)
+{
+        /* Disable access to the DMA block */
+        chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC0);
+        chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC1);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Gets a handle to a DMA channel
+*
+*  This function returns a handle, representing a control block of a particular DMA channel
+*
+*  @return  -1       - On Failure
+*            handle  - On Success, representing a channel control block
+*
+*  @note
+*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
+*/
+/****************************************************************************/
+dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId   /* [ IN ] DMA Channel Id */
+    ) {
+        int idx;
+
+        switch ((channelId >> 8)) {
+        case 0:
+                dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_0);
+                idx = (channelId & 0xff);
+                break;
+        case 1:
+                dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_1);
+                idx = dmaChannelCount_0 + (channelId & 0xff);
+                break;
+        default:
+                dmacHw_ASSERT(0);
+                return (dmacHw_HANDLE_t) -1;
+        }
+
+        return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[idx]);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Initializes a DMA channel for use
+*
+*  This function initializes and resets a DMA channel for use
+*
+*  @return  -1     - On Failure
+*            0     - On Success
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+int dmacHw_initChannel(dmacHw_HANDLE_t handle   /*   [ IN ] DMA Channel handle */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        int module = pCblk->module;
+        int channel = pCblk->channel;
+
+        /* Reinitialize the control block */
+        memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t));
+        pCblk->module = module;
+        pCblk->channel = channel;
+
+        /* Enable DMA controller */
+        dmacHw_DMA_ENABLE(pCblk->module);
+        /* Reset DMA channel */
+        dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel);
+        dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel);
+        dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel);
+        dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel);
+
+        /* Clear all raw interrupt status */
+        dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
+        dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
+        dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
+
+        /* Mask event specific interrupts */
+        dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
+        dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
+        dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel);
+        dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel);
+        dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
+
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief  Finds amount of memory required to form a descriptor ring
+*
+*
+*  @return   Number of bytes required to form a descriptor ring
+*
+*
+*/
+/****************************************************************************/
+uint32_t dmacHw_descriptorLen(uint32_t descCnt  /* [ IN ] Number of descriptor in the ring */
+    ) {
+        /* Need extra 4 byte to ensure 32 bit alignment  */
+        return (descCnt * sizeof(dmacHw_DESC_t)) + sizeof(dmacHw_DESC_RING_t) +
+                sizeof(uint32_t);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Initializes descriptor ring
+*
+*  This function will initializes the descriptor ring of a DMA channel
+*
+*
+*  @return   -1 - On failure
+*             0 - On success
+*  @note
+*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
+*     - Descriptor buffer MUST be 32 bit aligned and uncached as it is
+*       accessed by ARM and DMA
+*/
+/****************************************************************************/
+int dmacHw_initDescriptor(void *pDescriptorVirt,        /*  [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
+                          uint32_t descriptorPhyAddr,   /*  [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
+                          uint32_t len, /*  [ IN ] Size of the pBuf */
+                          uint32_t num  /*  [ IN ] Number of descriptor in the ring */
+    ) {
+        uint32_t i;
+        dmacHw_DESC_RING_t *pRing;
+        dmacHw_DESC_t *pDesc;
+
+        /* Check the alignment of the descriptor */
+        if ((uint32_t) pDescriptorVirt & 0x00000003) {
+                dmacHw_ASSERT(0);
+                return -1;
+        }
+
+        /* Check if enough space has been allocated for descriptor ring */
+        if (len < dmacHw_descriptorLen(num)) {
+                return -1;
+        }
+
+        pRing = dmacHw_GET_DESC_RING(pDescriptorVirt);
+        pRing->pHead =
+            (dmacHw_DESC_t *) ((uint32_t) pRing + sizeof(dmacHw_DESC_RING_t));
+        pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
+        pRing->pProg = dmacHw_DESC_INIT;
+        /* Initialize link item chain, starting from the head */
+        pDesc = pRing->pHead;
+        /* Find the offset between virtual to physical address */
+        pRing->virt2PhyOffset = (uint32_t) pDescriptorVirt - descriptorPhyAddr;
+
+        /* Form the descriptor ring */
+        for (i = 0; i < num - 1; i++) {
+                /* Clear link list item */
+                memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
+                /* Point to the next item in the physical address */
+                pDesc->llpPhy = (uint32_t) (pDesc + 1) - pRing->virt2PhyOffset;
+                /* Point to the next item in the virtual address */
+                pDesc->llp = (uint32_t) (pDesc + 1);
+                /* Mark descriptor is ready to use */
+                pDesc->ctl.hi = dmacHw_DESC_FREE;
+                /* Look into next link list item */
+                pDesc++;
+        }
+
+        /* Clear last link list item */
+        memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
+        /* Last item pointing to the first item in the
+           physical address to complete the ring */
+        pDesc->llpPhy = (uint32_t) pRing->pHead - pRing->virt2PhyOffset;
+        /* Last item pointing to the first item in the
+           virtual address to complete the ring
+         */
+        pDesc->llp = (uint32_t) pRing->pHead;
+        /* Mark descriptor is ready to use */
+        pDesc->ctl.hi = dmacHw_DESC_FREE;
+        /* Set the number of descriptors in the ring */
+        pRing->num = num;
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Configure DMA channel
+*
+*  @return  0  : On success
+*           -1 : On failure
+*/
+/****************************************************************************/
+int dmacHw_configChannel(dmacHw_HANDLE_t handle,        /*   [ IN ] DMA Channel handle */
+                         dmacHw_CONFIG_t *pConfig       /*   [ IN ] Configuration settings */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        uint32_t cfgHigh = 0;
+        int srcTrSize;
+        int dstTrSize;
+
+        pCblk->varDataStarted = 0;
+        pCblk->userData = NULL;
+
+        /* Configure
+           - Burst transaction when enough data in available in FIFO
+           - AHB Access protection 1
+           - Source and destination peripheral ports
+         */
+        cfgHigh =
+            dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
+            dmacHw_SRC_PERI_INTF(pConfig->
+                                 srcPeripheralPort) |
+            dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
+        /* Set priority */
+        dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
+                                    pConfig->channelPriority);
+
+        if (pConfig->dstStatusRegisterAddress != 0) {
+                /* Destination status update enable */
+                cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
+                /* Configure status registers */
+                dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
+                                   pConfig->dstStatusRegisterAddress);
+        }
+
+        if (pConfig->srcStatusRegisterAddress != 0) {
+                /* Source status update enable */
+                cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
+                /* Source status update enable */
+                dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
+                                   pConfig->srcStatusRegisterAddress);
+        }
+        /* Configure the config high register */
+        dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;
+
+        /* Clear all raw interrupt status */
+        dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
+        dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
+        dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
+
+        /* Configure block interrupt */
+        if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
+                dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
+        } else {
+                dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
+        }
+        /* Configure complete transfer interrupt */
+        if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
+                dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
+        } else {
+                dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
+        }
+        /* Configure error interrupt */
+        if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
+                dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
+        } else {
+                dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
+        }
+        /* Configure gather register */
+        if (pConfig->srcGatherWidth) {
+                srcTrSize =
+                    dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
+                if (!
+                    ((pConfig->srcGatherWidth % srcTrSize)
+                     && (pConfig->srcGatherJump % srcTrSize))) {
+                        dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
+                            ((pConfig->srcGatherWidth /
+                              srcTrSize) << 20) | (pConfig->srcGatherJump /
+                                                   srcTrSize);
+                } else {
+                        return -1;
+                }
+        }
+        /* Configure scatter register */
+        if (pConfig->dstScatterWidth) {
+                dstTrSize =
+                    dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
+                if (!
+                    ((pConfig->dstScatterWidth % dstTrSize)
+                     && (pConfig->dstScatterJump % dstTrSize))) {
+                        dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
+                            ((pConfig->dstScatterWidth /
+                              dstTrSize) << 20) | (pConfig->dstScatterJump /
+                                                   dstTrSize);
+                } else {
+                        return -1;
+                }
+        }
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Indicates whether DMA transfer is in progress or completed
+*
+*  @return   DMA transfer status
+*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
+*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
+*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
+*
+*/
+/****************************************************************************/
+dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle        /*   [ IN ] DMA Channel handle */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+
+        if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
+                return dmacHw_TRANSFER_STATUS_BUSY;
+        } else if (dmacHw_REG_INT_RAW_ERROR(pCblk->module) &
+                   (0x00000001 << pCblk->channel)) {
+                return dmacHw_TRANSFER_STATUS_ERROR;
+        }
+
+        return dmacHw_TRANSFER_STATUS_DONE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Set descriptors for known data length
+*
+*  When DMA has to work as a flow controller, this function prepares the
+*  descriptor chain to transfer data
+*
+*  from:
+*          - Memory to memory
+*          - Peripheral to memory
+*          - Memory to Peripheral
+*          - Peripheral to Peripheral
+*
+*  @return   -1 - On failure
+*             0 - On success
+*
+*/
+/****************************************************************************/
+int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
+                             void *pDescriptor, /*   [ IN ] Descriptor buffer */
+                             void *pSrcAddr,    /*   [ IN ] Source (Peripheral/Memory) address */
+                             void *pDstAddr,    /*   [ IN ] Destination (Peripheral/Memory) address */
+                             size_t dataLen     /*   [ IN ] Data length in bytes */
+    ) {
+        dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
+        dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
+        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
+        dmacHw_DESC_t *pStart;
+        dmacHw_DESC_t *pProg;
+        int srcTs = 0;
+        int blkTs = 0;
+        int oddSize = 0;
+        int descCount = 0;
+        int count = 0;
+        int dstTrSize = 0;
+        int srcTrSize = 0;
+        uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
+
+        dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
+        srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
+
+        /* Skip Tx if buffer is NULL  or length is unknown */
+        if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
+                /* Do not initiate transfer */
+                return -1;
+        }
+
+        /* Ensure scatter and gather are transaction aligned */
+        if ((pConfig->srcGatherWidth % srcTrSize)
+            || (pConfig->dstScatterWidth % dstTrSize)) {
+                return -2;
+        }
+
+        /*
+           Background 1: DMAC can not perform DMA if source and destination addresses are
+           not properly aligned with the channel's transaction width. So, for successful
+           DMA transfer, transaction width must be set according to the alignment of the
+           source and destination address.
+         */
+
+        /* Adjust destination transaction width if destination address is not aligned properly */
+        dstTrWidth = pConfig->dstMaxTransactionWidth;
+        while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
+                dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
+                dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
+        }
+
+        /* Adjust source transaction width if source address is not aligned properly */
+        srcTrWidth = pConfig->srcMaxTransactionWidth;
+        while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
+                srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
+                srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
+        }
+
+        /* Find the maximum transaction per descriptor */
+        if (pConfig->maxDataPerBlock
+            && ((pConfig->maxDataPerBlock / srcTrSize) <
+                dmacHw_MAX_BLOCKSIZE)) {
+                maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
+        }
+
+        /* Find number of source transactions needed to complete the DMA transfer */
+        srcTs = dataLen / srcTrSize;
+        /* Find the odd number of bytes that need to be transferred as single byte transaction width */
+        if (srcTs && (dstTrSize > srcTrSize)) {
+                oddSize = dataLen % dstTrSize;
+                /* Adjust source transaction count due to "oddSize" */
+                srcTs = srcTs - (oddSize / srcTrSize);
+        } else {
+                oddSize = dataLen % srcTrSize;
+        }
+        /* Adjust "descCount" due to "oddSize" */
+        if (oddSize) {
+                descCount++;
+        }
+        /* Find the number of descriptor needed for total "srcTs" */
+        if (srcTs) {
+                descCount += ((srcTs - 1) / maxBlockSize) + 1;
+        }
+
+        /* Check the availability of "descCount" discriptors in the ring */
+        pProg = pRing->pHead;
+        for (count = 0; (descCount <= pRing->num) && (count < descCount);
+             count++) {
+                if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) {
+                        /* Sufficient descriptors are not available */
+                        return -3;
+                }
+                pProg = (dmacHw_DESC_t *) pProg->llp;
+        }
+
+        /* Remember the link list item to program the channel registers */
+        pStart = pProg = pRing->pHead;
+        /* Make a link list with "descCount(=count)" number of descriptors */
+        while (count) {
+                /* Reset channel control information */
+                pProg->ctl.lo = 0;
+                /* Enable source gather if configured */
+                if (pConfig->srcGatherWidth) {
+                        pProg->ctl.lo |= dmacHw_REG_CTL_SG_ENABLE;
+                }
+                /* Enable destination scatter if configured */
+                if (pConfig->dstScatterWidth) {
+                        pProg->ctl.lo |= dmacHw_REG_CTL_DS_ENABLE;
+                }
+                /* Set source and destination address */
+                pProg->sar = (uint32_t) pSrcAddr;
+                pProg->dar = (uint32_t) pDstAddr;
+                /* Use "devCtl" to mark that user memory need to be freed later if needed */
+                if (pProg == pRing->pHead) {
+                        pProg->devCtl = dmacHw_FREE_USER_MEMORY;
+                } else {
+                        pProg->devCtl = 0;
+                }
+
+                blkTs = srcTs;
+
+                /* Special treatmeant for last descriptor */
+                if (count == 1) {
+                        /* Mark the last descriptor */
+                        pProg->ctl.lo &=
+                            ~(dmacHw_REG_CTL_LLP_DST_EN |
+                              dmacHw_REG_CTL_LLP_SRC_EN);
+                        /* Treatment for odd data bytes */
+                        if (oddSize) {
+                                /* Adjust for single byte transaction width */
+                                switch (pConfig->transferType) {
+                                case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
+                                        dstTrWidth =
+                                            dmacHw_DST_TRANSACTION_WIDTH_8;
+                                        blkTs =
+                                            (oddSize / srcTrSize) +
+                                            ((oddSize % srcTrSize) ? 1 : 0);
+                                        break;
+                                case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
+                                        srcTrWidth =
+                                            dmacHw_SRC_TRANSACTION_WIDTH_8;
+                                        blkTs = oddSize;
+                                        break;
+                                case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
+                                        srcTrWidth =
+                                            dmacHw_SRC_TRANSACTION_WIDTH_8;
+                                        dstTrWidth =
+                                            dmacHw_DST_TRANSACTION_WIDTH_8;
+                                        blkTs = oddSize;
+                                        break;
+                                case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
+                                        /* Do not adjust the transaction width  */
+                                        break;
+                                }
+                        } else {
+                                srcTs -= blkTs;
+                        }
+                } else {
+                        if (srcTs / maxBlockSize) {
+                                blkTs = maxBlockSize;
+                        }
+                        /* Remaining source transactions for next iteration */
+                        srcTs -= blkTs;
+                }
+                /* Must have a valid source transactions */
+                dmacHw_ASSERT(blkTs > 0);
+                /* Set control information */
+                if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
+                        pProg->ctl.lo |= pConfig->transferType |
+                            pConfig->srcUpdate |
+                            pConfig->dstUpdate |
+                            srcTrWidth |
+                            dstTrWidth |
+                            pConfig->srcMaxBurstWidth |
+                            pConfig->dstMaxBurstWidth |
+                            pConfig->srcMasterInterface |
+                            pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
+                } else {
+                        uint32_t transferType = 0;
+                        switch (pConfig->transferType) {
+                        case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
+                                transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
+                                break;
+                        case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
+                                transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
+                                break;
+                        default:
+                                dmacHw_ASSERT(0);
+                        }
+                        pProg->ctl.lo |= transferType |
+                            pConfig->srcUpdate |
+                            pConfig->dstUpdate |
+                            srcTrWidth |
+                            dstTrWidth |
+                            pConfig->srcMaxBurstWidth |
+                            pConfig->dstMaxBurstWidth |
+                            pConfig->srcMasterInterface |
+                            pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
+                }
+
+                /* Set block transaction size */
+                pProg->ctl.hi = blkTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
+                /* Look for next descriptor */
+                if (count > 1) {
+                        /* Point to the next descriptor */
+                        pProg = (dmacHw_DESC_t *) pProg->llp;
+
+                        /* Update source and destination address for next iteration */
+                        switch (pConfig->transferType) {
+                        case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
+                                if (pConfig->dstScatterWidth) {
+                                        pDstAddr =
+                                            (char *)pDstAddr +
+                                            blkTs * srcTrSize +
+                                            (((blkTs * srcTrSize) /
+                                              pConfig->dstScatterWidth) *
+                                             pConfig->dstScatterJump);
+                                } else {
+                                        pDstAddr =
+                                            (char *)pDstAddr +
+                                            blkTs * srcTrSize;
+                                }
+                                break;
+                        case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
+                                if (pConfig->srcGatherWidth) {
+                                        pSrcAddr =
+                                            (char *)pDstAddr +
+                                            blkTs * srcTrSize +
+                                            (((blkTs * srcTrSize) /
+                                              pConfig->srcGatherWidth) *
+                                             pConfig->srcGatherJump);
+                                } else {
+                                        pSrcAddr =
+                                            (char *)pSrcAddr +
+                                            blkTs * srcTrSize;
+                                }
+                                break;
+                        case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
+                                if (pConfig->dstScatterWidth) {
+                                        pDstAddr =
+                                            (char *)pDstAddr +
+                                            blkTs * srcTrSize +
+                                            (((blkTs * srcTrSize) /
+                                              pConfig->dstScatterWidth) *
+                                             pConfig->dstScatterJump);
+                                } else {
+                                        pDstAddr =
+                                            (char *)pDstAddr +
+                                            blkTs * srcTrSize;
+                                }
+
+                                if (pConfig->srcGatherWidth) {
+                                        pSrcAddr =
+                                            (char *)pDstAddr +
+                                            blkTs * srcTrSize +
+                                            (((blkTs * srcTrSize) /
+                                              pConfig->srcGatherWidth) *
+                                             pConfig->srcGatherJump);
+                                } else {
+                                        pSrcAddr =
+                                            (char *)pSrcAddr +
+                                            blkTs * srcTrSize;
+                                }
+                                break;
+                        case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
+                                /* Do not adjust the address */
+                                break;
+                        default:
+                                dmacHw_ASSERT(0);
+                        }
+                } else {
+                        /* At the end of transfer "srcTs" must be zero */
+                        dmacHw_ASSERT(srcTs == 0);
+                }
+                count--;
+        }
+
+        /* Remember the descriptor to initialize the registers */
+        if (pRing->pProg == dmacHw_DESC_INIT) {
+                pRing->pProg = pStart;
+        }
+        /* Indicate that the descriptor is updated */
+        pRing->pEnd = pProg;
+        /* Head pointing to the next descriptor */
+        pRing->pHead = (dmacHw_DESC_t *) pProg->llp;
+        /* Update Tail pointer if destination is a peripheral,
+           because no one is going to read from the pTail
+         */
+        if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
+                pRing->pTail = pRing->pHead;
+        }
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Provides DMA controller attributes
+*
+*
+*  @return  DMA controller attributes
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,       /*  [ IN ]  DMA Channel handle */
+                                          dmacHw_CONTROLLER_ATTRIB_e attr       /*  [ IN ]  DMA Controler attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+
+        switch (attr) {
+        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM:
+                return dmacHw_GET_NUM_CHANNEL(pCblk->module);
+        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE:
+                return (1 <<
+                         (dmacHw_GET_MAX_BLOCK_SIZE
+                          (pCblk->module, pCblk->module) + 2)) - 8;
+        case dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM:
+                return dmacHw_GET_NUM_INTERFACE(pCblk->module);
+        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH:
+                return 32 << dmacHw_GET_CHANNEL_DATA_WIDTH(pCblk->module,
+                                                           pCblk->channel);
+        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE:
+                return GetFifoSize(handle);
+        }
+        dmacHw_ASSERT(0);
+        return 0;
+}
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
new file mode 100644
index 000000000000..ff7b436d0935
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
@@ -0,0 +1,1017 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    dmacHw_extra.c
+*
+*  @brief   Extra Low level DMA controller driver routines
+*
+*  @note
+*
+*   These routines provide basic DMA functionality only.
+*/
+/****************************************************************************/
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#include <csp/stdint.h>
+#include <stddef.h>
+
+#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw_reg.h>
+#include <mach/csp/dmacHw_priv.h>
+
+extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];    /* Declared in dmacHw.c */
+
+/* ---- External Function Prototypes ------------------------------------- */
+
+/* ---- Internal Use Function Prototypes --------------------------------- */
+/****************************************************************************/
+/**
+*  @brief   Overwrites data length in the descriptor
+*
+*  This function overwrites data length in the descriptor
+*
+*
+*  @return   void
+*
+*  @note
+*          This is only used for PCM channel
+*/
+/****************************************************************************/
+void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,     /*   [ IN ] Configuration settings */
+                          void *pDescriptor,    /*   [ IN ] Descriptor buffer */
+                          size_t dataLen        /*   [ IN ] Data length in bytes */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Helper function to display DMA registers
+*
+*  @return  void
+*
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+static void DisplayRegisterContents(int module, /*   [ IN ] DMA Controller unit  (0-1) */
+                                    int channel,        /*   [ IN ] DMA Channel          (0-7) / -1(all) */
+                                    int (*fpPrint) (const char *, ...)  /*   [ IN ] Callback to the print function */
+    ) {
+        int chan;
+
+        (*fpPrint) ("Displaying register content \n\n");
+        (*fpPrint) ("Module %d: Interrupt raw transfer              0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_RAW_TRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt raw block                 0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_RAW_BLOCK(module)));
+        (*fpPrint) ("Module %d: Interrupt raw src transfer          0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_RAW_STRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt raw dst transfer          0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_RAW_DTRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt raw error                 0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_RAW_ERROR(module)));
+        (*fpPrint) ("--------------------------------------------------\n");
+        (*fpPrint) ("Module %d: Interrupt stat transfer             0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_STAT_TRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt stat block                0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_STAT_BLOCK(module)));
+        (*fpPrint) ("Module %d: Interrupt stat src transfer         0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_STAT_STRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt stat dst transfer         0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_STAT_DTRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt stat error                0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_STAT_ERROR(module)));
+        (*fpPrint) ("--------------------------------------------------\n");
+        (*fpPrint) ("Module %d: Interrupt mask transfer             0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_MASK_TRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt mask block                0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_MASK_BLOCK(module)));
+        (*fpPrint) ("Module %d: Interrupt mask src transfer         0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_MASK_STRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt mask dst transfer         0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_MASK_DTRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt mask error                0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_MASK_ERROR(module)));
+        (*fpPrint) ("--------------------------------------------------\n");
+        (*fpPrint) ("Module %d: Interrupt clear transfer            0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_TRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt clear block               0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_BLOCK(module)));
+        (*fpPrint) ("Module %d: Interrupt clear src transfer        0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_STRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt clear dst transfer        0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_DTRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt clear error               0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_ERROR(module)));
+        (*fpPrint) ("--------------------------------------------------\n");
+        (*fpPrint) ("Module %d: SW source req                       0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_REQ(module)));
+        (*fpPrint) ("Module %d: SW dest req                         0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_SW_HS_DST_REQ(module)));
+        (*fpPrint) ("Module %d: SW source signal                    0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_SGL_REQ(module)));
+        (*fpPrint) ("Module %d: SW dest signal                      0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_SW_HS_DST_SGL_REQ(module)));
+        (*fpPrint) ("Module %d: SW source last                      0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_LST_REQ(module)));
+        (*fpPrint) ("Module %d: SW dest last                        0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_SW_HS_DST_LST_REQ(module)));
+        (*fpPrint) ("--------------------------------------------------\n");
+        (*fpPrint) ("Module %d: misc config                         0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_MISC_CFG(module)));
+        (*fpPrint) ("Module %d: misc channel enable                 0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_MISC_CH_ENABLE(module)));
+        (*fpPrint) ("Module %d: misc ID                             0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_MISC_ID(module)));
+        (*fpPrint) ("Module %d: misc test                           0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_MISC_TEST(module)));
+
+        if (channel == -1) {
+                for (chan = 0; chan < 8; chan++) {
+                        (*fpPrint)
+                            ("--------------------------------------------------\n");
+                        (*fpPrint)
+                            ("Module %d: Channel %d Source                   0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_SAR(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Destination              0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_DAR(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d LLP                      0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_LLP(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Control (LO)             0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Control (HI)             0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Source Stats             0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Dest Stats               0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Source Stats Addr        0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Config (LO)              0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Config (HI)              0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
+                }
+        } else {
+                chan = channel;
+                (*fpPrint)
+                    ("--------------------------------------------------\n");
+                (*fpPrint)
+                    ("Module %d: Channel %d Source                   0x%X\n",
+                     module, chan, (uint32_t) (dmacHw_REG_SAR(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Destination              0x%X\n",
+                     module, chan, (uint32_t) (dmacHw_REG_DAR(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d LLP                      0x%X\n",
+                     module, chan, (uint32_t) (dmacHw_REG_LLP(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Control (LO)             0x%X\n",
+                     module, chan,
+                     (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Control (HI)             0x%X\n",
+                     module, chan,
+                     (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Source Stats             0x%X\n",
+                     module, chan, (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Dest Stats               0x%X\n",
+                     module, chan, (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Source Stats Addr        0x%X\n",
+                     module, chan,
+                     (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
+                     module, chan,
+                     (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Config (LO)              0x%X\n",
+                     module, chan,
+                     (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Config (HI)              0x%X\n",
+                     module, chan,
+                     (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
+        }
+}
+
+/****************************************************************************/
+/**
+*  @brief   Helper function to display descriptor ring
+*
+*  @return  void
+*
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+static void DisplayDescRing(void *pDescriptor,  /*   [ IN ] Descriptor buffer */
+                            int (*fpPrint) (const char *, ...)  /*   [ IN ] Callback to the print function */
+    ) {
+        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
+        dmacHw_DESC_t *pStart;
+
+        if (pRing->pHead == NULL) {
+                return;
+        }
+
+        pStart = pRing->pHead;
+
+        while ((dmacHw_DESC_t *) pStart->llp != pRing->pHead) {
+                if (pStart == pRing->pHead) {
+                        (*fpPrint) ("Head\n");
+                }
+                if (pStart == pRing->pTail) {
+                        (*fpPrint) ("Tail\n");
+                }
+                if (pStart == pRing->pProg) {
+                        (*fpPrint) ("Prog\n");
+                }
+                if (pStart == pRing->pEnd) {
+                        (*fpPrint) ("End\n");
+                }
+                if (pStart == pRing->pFree) {
+                        (*fpPrint) ("Free\n");
+                }
+                (*fpPrint) ("0x%X:\n", (uint32_t) pStart);
+                (*fpPrint) ("sar    0x%0X\n", pStart->sar);
+                (*fpPrint) ("dar    0x%0X\n", pStart->dar);
+                (*fpPrint) ("llp    0x%0X\n", pStart->llp);
+                (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
+                (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
+                (*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
+                (*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
+                (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
+
+                pStart = (dmacHw_DESC_t *) pStart->llp;
+        }
+        if (pStart == pRing->pHead) {
+                (*fpPrint) ("Head\n");
+        }
+        if (pStart == pRing->pTail) {
+                (*fpPrint) ("Tail\n");
+        }
+        if (pStart == pRing->pProg) {
+                (*fpPrint) ("Prog\n");
+        }
+        if (pStart == pRing->pEnd) {
+                (*fpPrint) ("End\n");
+        }
+        if (pStart == pRing->pFree) {
+                (*fpPrint) ("Free\n");
+        }
+        (*fpPrint) ("0x%X:\n", (uint32_t) pStart);
+        (*fpPrint) ("sar    0x%0X\n", pStart->sar);
+        (*fpPrint) ("dar    0x%0X\n", pStart->dar);
+        (*fpPrint) ("llp    0x%0X\n", pStart->llp);
+        (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
+        (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
+        (*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
+        (*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
+        (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Check if DMA channel is the flow controller
+*
+*  @return  1 : If DMA is a flow controler
+*           0 : Peripheral is the flow controller
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+static inline int DmaIsFlowController(void *pDescriptor /*   [ IN ] Descriptor buffer */
+    ) {
+        uint32_t ttfc =
+            (dmacHw_GET_DESC_RING(pDescriptor))->pTail->ctl.
+            lo & dmacHw_REG_CTL_TTFC_MASK;
+
+        switch (ttfc) {
+        case dmacHw_REG_CTL_TTFC_MM_DMAC:
+        case dmacHw_REG_CTL_TTFC_MP_DMAC:
+        case dmacHw_REG_CTL_TTFC_PM_DMAC:
+        case dmacHw_REG_CTL_TTFC_PP_DMAC:
+                return 1;
+        }
+
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Overwrites data length in the descriptor
+*
+*  This function overwrites data length in the descriptor
+*
+*
+*  @return   void
+*
+*  @note
+*          This is only used for PCM channel
+*/
+/****************************************************************************/
+void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,     /*   [ IN ] Configuration settings */
+                          void *pDescriptor,    /*   [ IN ] Descriptor buffer */
+                          size_t dataLen        /*   [ IN ] Data length in bytes */
+    ) {
+        dmacHw_DESC_t *pProg;
+        dmacHw_DESC_t *pHead;
+        int srcTs = 0;
+        int srcTrSize = 0;
+
+        pHead = (dmacHw_GET_DESC_RING(pDescriptor))->pHead;
+        pProg = pHead;
+
+        srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
+        srcTs = dataLen / srcTrSize;
+        do {
+                pProg->ctl.hi = srcTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
+                pProg = (dmacHw_DESC_t *) pProg->llp;
+        } while (pProg != pHead);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Clears the interrupt
+*
+*  This function clears the DMA channel specific interrupt
+*
+*
+*  @return   void
+*
+*  @note
+*     Must be called under the context of ISR
+*/
+/****************************************************************************/
+void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle       /* [ IN ] DMA Channel handle */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+
+        dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
+        dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
+        dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Returns the cause of channel specific DMA interrupt
+*
+*  This function returns the cause of interrupt
+*
+*  @return  Interrupt status, each bit representing a specific type of interrupt
+*
+*  @note
+*     Should be called under the context of ISR
+*/
+/****************************************************************************/
+dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle      /* [ IN ] DMA Channel handle */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        dmacHw_INTERRUPT_STATUS_e status = dmacHw_INTERRUPT_STATUS_NONE;
+
+        if (dmacHw_REG_INT_STAT_TRAN(pCblk->module) &
+            ((0x00000001 << pCblk->channel))) {
+                status |= dmacHw_INTERRUPT_STATUS_TRANS;
+        }
+        if (dmacHw_REG_INT_STAT_BLOCK(pCblk->module) &
+            ((0x00000001 << pCblk->channel))) {
+                status |= dmacHw_INTERRUPT_STATUS_BLOCK;
+        }
+        if (dmacHw_REG_INT_STAT_ERROR(pCblk->module) &
+            ((0x00000001 << pCblk->channel))) {
+                status |= dmacHw_INTERRUPT_STATUS_ERROR;
+        }
+
+        return status;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Indentifies a DMA channel causing interrupt
+*
+*  This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
+*
+*  @return  NULL   : No channel causing DMA interrupt
+*           ! NULL : Handle to a channel causing DMA interrupt
+*  @note
+*     dmacHw_clearInterrupt() must be called with a valid handle after calling this function
+*/
+/****************************************************************************/
+dmacHw_HANDLE_t dmacHw_getInterruptSource(void)
+{
+        uint32_t i;
+
+        for (i = 0; i < dmaChannelCount_0 + dmaChannelCount_1; i++) {
+                if ((dmacHw_REG_INT_STAT_TRAN(dmacHw_gCblk[i].module) &
+                     ((0x00000001 << dmacHw_gCblk[i].channel)))
+                    || (dmacHw_REG_INT_STAT_BLOCK(dmacHw_gCblk[i].module) &
+                        ((0x00000001 << dmacHw_gCblk[i].channel)))
+                    || (dmacHw_REG_INT_STAT_ERROR(dmacHw_gCblk[i].module) &
+                        ((0x00000001 << dmacHw_gCblk[i].channel)))
+                    ) {
+                        return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[i]);
+                }
+        }
+        return dmacHw_CBLK_TO_HANDLE(NULL);
+}
+
+/****************************************************************************/
+/**
+*  @brief  Estimates number of descriptor needed to perform certain DMA transfer
+*
+*
+*  @return  On failure : -1
+*           On success : Number of descriptor count
+*
+*
+*/
+/****************************************************************************/
+int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,   /*   [ IN ] Configuration settings */
+                                    void *pSrcAddr,     /*   [ IN ] Source (Peripheral/Memory) address */
+                                    void *pDstAddr,     /*   [ IN ] Destination (Peripheral/Memory) address */
+                                    size_t dataLen      /*   [ IN ] Data length in bytes */
+    ) {
+        int srcTs = 0;
+        int oddSize = 0;
+        int descCount = 0;
+        int dstTrSize = 0;
+        int srcTrSize = 0;
+        uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
+        dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
+        dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
+
+        dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
+        srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
+
+        /* Skip Tx if buffer is NULL  or length is unknown */
+        if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
+                /* Do not initiate transfer */
+                return -1;
+        }
+
+        /* Ensure scatter and gather are transaction aligned */
+        if (pConfig->srcGatherWidth % srcTrSize
+            || pConfig->dstScatterWidth % dstTrSize) {
+                return -1;
+        }
+
+        /*
+           Background 1: DMAC can not perform DMA if source and destination addresses are
+           not properly aligned with the channel's transaction width. So, for successful
+           DMA transfer, transaction width must be set according to the alignment of the
+           source and destination address.
+         */
+
+        /* Adjust destination transaction width if destination address is not aligned properly */
+        dstTrWidth = pConfig->dstMaxTransactionWidth;
+        while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
+                dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
+                dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
+        }
+
+        /* Adjust source transaction width if source address is not aligned properly */
+        srcTrWidth = pConfig->srcMaxTransactionWidth;
+        while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
+                srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
+                srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
+        }
+
+        /* Find the maximum transaction per descriptor */
+        if (pConfig->maxDataPerBlock
+            && ((pConfig->maxDataPerBlock / srcTrSize) <
+                dmacHw_MAX_BLOCKSIZE)) {
+                maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
+        }
+
+        /* Find number of source transactions needed to complete the DMA transfer */
+        srcTs = dataLen / srcTrSize;
+        /* Find the odd number of bytes that need to be transferred as single byte transaction width */
+        if (srcTs && (dstTrSize > srcTrSize)) {
+                oddSize = dataLen % dstTrSize;
+                /* Adjust source transaction count due to "oddSize" */
+                srcTs = srcTs - (oddSize / srcTrSize);
+        } else {
+                oddSize = dataLen % srcTrSize;
+        }
+        /* Adjust "descCount" due to "oddSize" */
+        if (oddSize) {
+                descCount++;
+        }
+
+        /* Find the number of descriptor needed for total "srcTs" */
+        if (srcTs) {
+                descCount += ((srcTs - 1) / maxBlockSize) + 1;
+        }
+
+        return descCount;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Check the existance of pending descriptor
+*
+*  This function confirmes if there is any pending descriptor in the chain
+*  to program the channel
+*
+*  @return  1 : Channel need to be programmed with pending descriptor
+*           0 : No more pending descriptor to programe the channel
+*
+*  @note
+*     - This function should be called from ISR in case there are pending
+*       descriptor to program the channel.
+*
+*     Example:
+*
+*     dmac_isr ()
+*     {
+*         ...
+*         if (dmacHw_descriptorPending (handle))
+*         {
+*            dmacHw_initiateTransfer (handle);
+*         }
+*     }
+*
+*/
+/****************************************************************************/
+uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,       /*   [ IN ] DMA Channel handle */
+                                  void *pDescriptor     /*   [ IN ] Descriptor buffer */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
+
+        /* Make sure channel is not busy */
+        if (!CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
+                /* Check if pEnd is not processed */
+                if (pRing->pEnd) {
+                        /* Something left for processing */
+                        return 1;
+                }
+        }
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Program channel register to stop transfer
+*
+*  Ensures the channel is not doing any transfer after calling this function
+*
+*  @return  void
+*
+*/
+/****************************************************************************/
+void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /*   [ IN ] DMA Channel handle */
+    ) {
+        dmacHw_CBLK_t *pCblk;
+
+        pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+
+        /* Stop the channel */
+        dmacHw_DMA_STOP(pCblk->module, pCblk->channel);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Deallocates source or destination memory, allocated
+*
+*  This function can be called to deallocate data memory that was DMAed successfully
+*
+*  @return  On failure : -1
+*           On success : Number of buffer freed
+*
+*  @note
+*     This function will be called ONLY, when source OR destination address is pointing
+*     to dynamic memory
+*/
+/****************************************************************************/
+int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,    /*   [ IN ] Configuration settings */
+                   void *pDescriptor,   /*   [ IN ] Descriptor buffer */
+                   void (*fpFree) (void *)      /*   [ IN ] Function pointer to free data memory */
+    ) {
+        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
+        uint32_t count = 0;
+
+        if (fpFree == NULL) {
+                return -1;
+        }
+
+        while ((pRing->pFree != pRing->pTail)
+               && (pRing->pFree->ctl.lo & dmacHw_DESC_FREE)) {
+                if (pRing->pFree->devCtl == dmacHw_FREE_USER_MEMORY) {
+                        /* Identify, which memory to free */
+                        if (dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
+                                (*fpFree) ((void *)pRing->pFree->dar);
+                        } else {
+                                /* Destination was a peripheral */
+                                (*fpFree) ((void *)pRing->pFree->sar);
+                        }
+                        /* Unmark user memory to indicate it is freed */
+                        pRing->pFree->devCtl = ~dmacHw_FREE_USER_MEMORY;
+                }
+                dmacHw_NEXT_DESC(pRing, pFree);
+
+                count++;
+        }
+
+        return count;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Prepares descriptor ring, when source peripheral working as a flow controller
+*
+*  This function will update the discriptor ring by allocating buffers, when source peripheral
+*  has to work as a flow controller to transfer data from:
+*           - Peripheral to memory.
+*
+*  @return  On failure : -1
+*           On success : Number of descriptor updated
+*
+*
+*  @note
+*     Channel must be configured for peripheral to memory transfer
+*
+*/
+/****************************************************************************/
+int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,    /*   [ IN ] DMA Channel handle */
+                                     dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
+                                     void *pDescriptor, /*   [ IN ] Descriptor buffer */
+                                     uint32_t srcAddr,  /*   [ IN ] Source peripheral address */
+                                     void *(*fpAlloc) (int len),        /*   [ IN ] Function pointer  that provides destination memory */
+                                     int len,   /*   [ IN ] Number of bytes "fpAlloc" will allocate for destination */
+                                     int num    /*   [ IN ] Number of descriptor to set */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        dmacHw_DESC_t *pProg = NULL;
+        dmacHw_DESC_t *pLast = NULL;
+        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
+        uint32_t dstAddr;
+        uint32_t controlParam;
+        int i;
+
+        dmacHw_ASSERT(pConfig->transferType ==
+                      dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM);
+
+        if (num > pRing->num) {
+                return -1;
+        }
+
+        pLast = pRing->pEnd;    /* Last descriptor updated */
+        pProg = pRing->pHead;   /* First descriptor in the new list */
+
+        controlParam = pConfig->srcUpdate |
+            pConfig->dstUpdate |
+            pConfig->srcMaxTransactionWidth |
+            pConfig->dstMaxTransactionWidth |
+            pConfig->srcMasterInterface |
+            pConfig->dstMasterInterface |
+            pConfig->srcMaxBurstWidth |
+            pConfig->dstMaxBurstWidth |
+            dmacHw_REG_CTL_TTFC_PM_PERI |
+            dmacHw_REG_CTL_LLP_DST_EN |
+            dmacHw_REG_CTL_LLP_SRC_EN | dmacHw_REG_CTL_INT_EN;
+
+        for (i = 0; i < num; i++) {
+                /* Allocate Rx buffer only for idle descriptor */
+                if (((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) ||
+                    ((dmacHw_DESC_t *) pRing->pHead->llp == pRing->pTail)
+                    ) {
+                        /* Rx descriptor is not idle */
+                        break;
+                }
+                /* Set source address */
+                pRing->pHead->sar = srcAddr;
+                if (fpAlloc) {
+                        /* Allocate memory for buffer in descriptor */
+                        dstAddr = (uint32_t) (*fpAlloc) (len);
+                        /* Check the destination address */
+                        if (dstAddr == 0) {
+                                if (i == 0) {
+                                        /* Not a single descriptor is available */
+                                        return -1;
+                                }
+                                break;
+                        }
+                        /* Set destination address */
+                        pRing->pHead->dar = dstAddr;
+                }
+                /* Set control information */
+                pRing->pHead->ctl.lo = controlParam;
+                /* Use "devCtl" to mark the memory that need to be freed later */
+                pRing->pHead->devCtl = dmacHw_FREE_USER_MEMORY;
+                /* Descriptor is now owned by the channel */
+                pRing->pHead->ctl.hi = 0;
+                /* Remember the descriptor last updated */
+                pRing->pEnd = pRing->pHead;
+                /* Update next descriptor */
+                dmacHw_NEXT_DESC(pRing, pHead);
+        }
+
+        /* Mark the end of the list */
+        pRing->pEnd->ctl.lo &=
+            ~(dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN);
+        /* Connect the list */
+        if (pLast != pProg) {
+                pLast->ctl.lo |=
+                    dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN;
+        }
+        /* Mark the descriptors are updated */
+        pCblk->descUpdated = 1;
+        if (!pCblk->varDataStarted) {
+                /* LLP must be pointing to the first descriptor */
+                dmacHw_SET_LLP(pCblk->module, pCblk->channel,
+                               (uint32_t) pProg - pRing->virt2PhyOffset);
+                /* Channel, handling variable data started */
+                pCblk->varDataStarted = 1;
+        }
+
+        return i;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Read data DMAed to memory
+*
+*  This function will read data that has been DMAed to memory while transfering from:
+*          - Memory to memory
+*          - Peripheral to memory
+*
+*  @param    handle     -
+*  @param    ppBbuf     -
+*  @param    pLen       -
+*
+*  @return  0 - No more data is available to read
+*           1 - More data might be available to read
+*
+*/
+/****************************************************************************/
+int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle */
+                               dmacHw_CONFIG_t *pConfig,        /*   [ IN ]  Configuration settings */
+                               void *pDescriptor,       /*   [ IN ] Descriptor buffer */
+                               void **ppBbuf,   /*   [ OUT ] Data received */
+                               size_t *pLlen    /*   [ OUT ] Length of the data received */
+    ) {
+        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
+
+        (void)handle;
+
+        if (pConfig->transferMode != dmacHw_TRANSFER_MODE_CONTINUOUS) {
+                if (((pRing->pTail->ctl.hi & dmacHw_DESC_FREE) == 0) ||
+                    (pRing->pTail == pRing->pHead)
+                    ) {
+                        /* No receive data available */
+                        *ppBbuf = (char *)NULL;
+                        *pLlen = 0;
+
+                        return 0;
+                }
+        }
+
+        /* Return read buffer and length */
+        *ppBbuf = (char *)pRing->pTail->dar;
+
+        /* Extract length of the received data */
+        if (DmaIsFlowController(pDescriptor)) {
+                uint32_t srcTrSize = 0;
+
+                switch (pRing->pTail->ctl.lo & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
+                case dmacHw_REG_CTL_SRC_TR_WIDTH_8:
+                        srcTrSize = 1;
+                        break;
+                case dmacHw_REG_CTL_SRC_TR_WIDTH_16:
+                        srcTrSize = 2;
+                        break;
+                case dmacHw_REG_CTL_SRC_TR_WIDTH_32:
+                        srcTrSize = 4;
+                        break;
+                case dmacHw_REG_CTL_SRC_TR_WIDTH_64:
+                        srcTrSize = 8;
+                        break;
+                default:
+                        dmacHw_ASSERT(0);
+                }
+                /* Calculate length from the block size */
+                *pLlen =
+                    (pRing->pTail->ctl.hi & dmacHw_REG_CTL_BLOCK_TS_MASK) *
+                    srcTrSize;
+        } else {
+                /* Extract length from the source peripheral */
+                *pLlen = pRing->pTail->sstat;
+        }
+
+        /* Advance tail to next descriptor */
+        dmacHw_NEXT_DESC(pRing, pTail);
+
+        return 1;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Set descriptor carrying control information
+*
+*  This function will be used to send specific control information to the device
+*  using the DMA channel
+*
+*
+*  @return  -1 - On failure
+*            0 - On success
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,       /*   [ IN ] Configuration settings */
+                                void *pDescriptor,      /*   [ IN ] Descriptor buffer */
+                                uint32_t ctlAddress,    /*   [ IN ] Address of the device control register */
+                                uint32_t control        /*   [ IN ] Device control information */
+    ) {
+        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
+
+        if (ctlAddress == 0) {
+                return -1;
+        }
+
+        /* Check the availability of descriptors in the ring */
+        if ((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) {
+                return -1;
+        }
+        /* Set control information */
+        pRing->pHead->devCtl = control;
+        /* Set source and destination address */
+        pRing->pHead->sar = (uint32_t) &pRing->pHead->devCtl;
+        pRing->pHead->dar = ctlAddress;
+        /* Set control parameters */
+        if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
+                pRing->pHead->ctl.lo = pConfig->transferType |
+                    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
+                    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
+                    dmacHw_SRC_TRANSACTION_WIDTH_32 |
+                    pConfig->dstMaxTransactionWidth |
+                    dmacHw_SRC_BURST_WIDTH_0 |
+                    dmacHw_DST_BURST_WIDTH_0 |
+                    pConfig->srcMasterInterface |
+                    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
+        } else {
+                uint32_t transferType = 0;
+                switch (pConfig->transferType) {
+                case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
+                        transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
+                        break;
+                case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
+                        transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
+                        break;
+                default:
+                        dmacHw_ASSERT(0);
+                }
+                pRing->pHead->ctl.lo = transferType |
+                    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
+                    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
+                    dmacHw_SRC_TRANSACTION_WIDTH_32 |
+                    pConfig->dstMaxTransactionWidth |
+                    dmacHw_SRC_BURST_WIDTH_0 |
+                    dmacHw_DST_BURST_WIDTH_0 |
+                    pConfig->srcMasterInterface |
+                    pConfig->dstMasterInterface |
+                    pConfig->flowControler | dmacHw_REG_CTL_INT_EN;
+        }
+
+        /* Set block transaction size to one 32 bit transaction */
+        pRing->pHead->ctl.hi = dmacHw_REG_CTL_BLOCK_TS_MASK & 1;
+
+        /* Remember the descriptor to initialize the registers */
+        if (pRing->pProg == dmacHw_DESC_INIT) {
+                pRing->pProg = pRing->pHead;
+        }
+        pRing->pEnd = pRing->pHead;
+
+        /* Advance the descriptor */
+        dmacHw_NEXT_DESC(pRing, pHead);
+
+        /* Update Tail pointer if destination is a peripheral */
+        if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
+                pRing->pTail = pRing->pHead;
+        }
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Sets channel specific user data
+*
+*  This function associates user data to a specif DMA channel
+*
+*/
+/****************************************************************************/
+void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle */
+                               void *userData   /*  [ IN ] User data */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+
+        pCblk->userData = userData;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Gets channel specific user data
+*
+*  This function returns user data specific to a DMA channel
+*
+*  @return   user data
+*/
+/****************************************************************************/
+void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle  /*  [ IN ] DMA Channel handle */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+
+        return pCblk->userData;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Resets descriptor control information
+*
+*  @return  void
+*/
+/****************************************************************************/
+void dmacHw_resetDescriptorControl(void *pDescriptor    /*   [ IN ] Descriptor buffer  */
+    ) {
+        int i;
+        dmacHw_DESC_RING_t *pRing;
+        dmacHw_DESC_t *pDesc;
+
+        pRing = dmacHw_GET_DESC_RING(pDescriptor);
+        pDesc = pRing->pHead;
+
+        for (i = 0; i < pRing->num; i++) {
+                /* Mark descriptor is ready to use */
+                pDesc->ctl.hi = dmacHw_DESC_FREE;
+                /* Look into next link list item */
+                pDesc++;
+        }
+        pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
+        pRing->pProg = dmacHw_DESC_INIT;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Displays channel specific registers and other control parameters
+*
+*  @return  void
+*
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,      /*  [ IN ] DMA Channel handle */
+                           void *pDescriptor,   /*   [ IN ] Descriptor buffer */
+                           int (*fpPrint) (const char *, ...)   /*  [ IN ] Print callback function */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+
+        DisplayRegisterContents(pCblk->module, pCblk->channel, fpPrint);
+        DisplayDescRing(pDescriptor, fpPrint);
+}
diff --git a/arch/arm/mach-bcmring/csp/tmr/Makefile b/arch/arm/mach-bcmring/csp/tmr/Makefile
new file mode 100644
index 000000000000..244a61ab7697
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/tmr/Makefile
@@ -0,0 +1 @@
+obj-y += tmrHw.o
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
new file mode 100644
index 000000000000..5c1c9a0e5ed2
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
@@ -0,0 +1,576 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    tmrHw.c
+*
+*  @brief   Low level Timer driver routines
+*
+*  @note
+*
+*   These routines provide basic timer functionality only.
+*/
+/****************************************************************************/
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#include <csp/errno.h>
+#include <csp/stdint.h>
+
+#include <csp/tmrHw.h>
+#include <mach/csp/tmrHw_reg.h>
+
+#define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
+#define tmrHw_MILLISEC_PER_SEC              (1000)
+
+#define tmrHw_LOW_1_RESOLUTION_COUNT        (tmrHw_LOW_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
+#define tmrHw_LOW_1_MAX_MILLISEC            (0xFFFFFFFF / tmrHw_LOW_1_RESOLUTION_COUNT)
+#define tmrHw_LOW_16_RESOLUTION_COUNT       (tmrHw_LOW_1_RESOLUTION_COUNT / 16)
+#define tmrHw_LOW_16_MAX_MILLISEC           (0xFFFFFFFF / tmrHw_LOW_16_RESOLUTION_COUNT)
+#define tmrHw_LOW_256_RESOLUTION_COUNT      (tmrHw_LOW_1_RESOLUTION_COUNT / 256)
+#define tmrHw_LOW_256_MAX_MILLISEC          (0xFFFFFFFF / tmrHw_LOW_256_RESOLUTION_COUNT)
+
+#define tmrHw_HIGH_1_RESOLUTION_COUNT       (tmrHw_HIGH_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
+#define tmrHw_HIGH_1_MAX_MILLISEC           (0xFFFFFFFF / tmrHw_HIGH_1_RESOLUTION_COUNT)
+#define tmrHw_HIGH_16_RESOLUTION_COUNT      (tmrHw_HIGH_1_RESOLUTION_COUNT / 16)
+#define tmrHw_HIGH_16_MAX_MILLISEC          (0xFFFFFFFF / tmrHw_HIGH_16_RESOLUTION_COUNT)
+#define tmrHw_HIGH_256_RESOLUTION_COUNT     (tmrHw_HIGH_1_RESOLUTION_COUNT / 256)
+#define tmrHw_HIGH_256_MAX_MILLISEC         (0xFFFFFFFF / tmrHw_HIGH_256_RESOLUTION_COUNT)
+
+static void ResetTimer(tmrHw_ID_t timerId)
+    __attribute__ ((section(".aramtext")));
+static int tmrHw_divide(int num, int denom)
+    __attribute__ ((section(".aramtext")));
+
+/****************************************************************************/
+/**
+*  @brief   Get timer capability
+*
+*  This function returns various capabilities/attributes of a timer
+*
+*  @return  Capability
+*
+*/
+/****************************************************************************/
+uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,   /*  [ IN ] Timer Id */
+                                  tmrHw_CAPABILITY_e capability /*  [ IN ] Timer capability */
+) {
+        switch (capability) {
+        case tmrHw_CAPABILITY_CLOCK:
+                return (timerId <=
+                        1) ? tmrHw_LOW_RESOLUTION_CLOCK :
+                    tmrHw_HIGH_RESOLUTION_CLOCK;
+        case tmrHw_CAPABILITY_RESOLUTION:
+                return 32;
+        default:
+                return 0;
+        }
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Resets a timer
+*
+*  This function initializes  timer
+*
+*  @return  void
+*
+*/
+/****************************************************************************/
+static void ResetTimer(tmrHw_ID_t timerId       /*  [ IN ] Timer Id */
+) {
+        /* Reset timer */
+        pTmrHw[timerId].LoadValue = 0;
+        pTmrHw[timerId].CurrentValue = 0xFFFFFFFF;
+        pTmrHw[timerId].Control = 0;
+        pTmrHw[timerId].BackgroundLoad = 0;
+        /* Always configure as a 32 bit timer */
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT;
+        /* Clear interrupt only if raw status interrupt is set */
+        if (pTmrHw[timerId].RawInterruptStatus) {
+                pTmrHw[timerId].InterruptClear = 0xFFFFFFFF;
+        }
+}
+
+/****************************************************************************/
+/**
+*  @brief   Sets counter value for an interval in ms
+*
+*  @return   On success: Effective counter value set
+*            On failure: 0
+*
+*/
+/****************************************************************************/
+static tmrHw_INTERVAL_t SetTimerPeriod(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
+                                       tmrHw_INTERVAL_t msec    /*  [ IN ] Interval in milli-second */
+) {
+        uint32_t scale = 0;
+        uint32_t count = 0;
+
+        if (timerId == 0 || timerId == 1) {
+                if (msec <= tmrHw_LOW_1_MAX_MILLISEC) {
+                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
+                        scale = tmrHw_LOW_1_RESOLUTION_COUNT;
+                } else if (msec <= tmrHw_LOW_16_MAX_MILLISEC) {
+                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
+                        scale = tmrHw_LOW_16_RESOLUTION_COUNT;
+                } else if (msec <= tmrHw_LOW_256_MAX_MILLISEC) {
+                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
+                        scale = tmrHw_LOW_256_RESOLUTION_COUNT;
+                } else {
+                        return 0;
+                }
+
+                count = msec * scale;
+                /* Set counter value */
+                pTmrHw[timerId].LoadValue = count;
+                pTmrHw[timerId].BackgroundLoad = count;
+
+        } else if (timerId == 2 || timerId == 3) {
+                if (msec <= tmrHw_HIGH_1_MAX_MILLISEC) {
+                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
+                        scale = tmrHw_HIGH_1_RESOLUTION_COUNT;
+                } else if (msec <= tmrHw_HIGH_16_MAX_MILLISEC) {
+                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
+                        scale = tmrHw_HIGH_16_RESOLUTION_COUNT;
+                } else if (msec <= tmrHw_HIGH_256_MAX_MILLISEC) {
+                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
+                        scale = tmrHw_HIGH_256_RESOLUTION_COUNT;
+                } else {
+                        return 0;
+                }
+
+                count = msec * scale;
+                /* Set counter value */
+                pTmrHw[timerId].LoadValue = count;
+                pTmrHw[timerId].BackgroundLoad = count;
+        }
+        return count / scale;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Configures a periodic timer in terms of timer interrupt rate
+*
+*  This function initializes a periodic timer to generate specific number of
+*  timer interrupt per second
+*
+*  @return   On success: Effective timer frequency
+*            On failure: 0
+*
+*/
+/****************************************************************************/
+tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
+                                        tmrHw_RATE_t rate       /*  [ IN ] Number of timer interrupt per second */
+) {
+        uint32_t resolution = 0;
+        uint32_t count = 0;
+        ResetTimer(timerId);
+
+        /* Set timer mode periodic */
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
+        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
+        /* Set timer in highest resolution */
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
+
+        if (rate && (timerId == 0 || timerId == 1)) {
+                if (rate > tmrHw_LOW_RESOLUTION_CLOCK) {
+                        return 0;
+                }
+                resolution = tmrHw_LOW_RESOLUTION_CLOCK;
+        } else if (rate && (timerId == 2 || timerId == 3)) {
+                if (rate > tmrHw_HIGH_RESOLUTION_CLOCK) {
+                        return 0;
+                } else {
+                        resolution = tmrHw_HIGH_RESOLUTION_CLOCK;
+                }
+        } else {
+                return 0;
+        }
+        /* Find the counter value */
+        count = resolution / rate;
+        /* Set counter value */
+        pTmrHw[timerId].LoadValue = count;
+        pTmrHw[timerId].BackgroundLoad = count;
+
+        return resolution / count;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Configures a periodic timer to generate timer interrupt after
+*           certain time interval
+*
+*  This function initializes a periodic timer to generate timer interrupt
+*  after every time interval in millisecond
+*
+*  @return   On success: Effective interval set in milli-second
+*            On failure: 0
+*
+*/
+/****************************************************************************/
+tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
+                                                tmrHw_INTERVAL_t msec   /*  [ IN ] Interval in milli-second */
+) {
+        ResetTimer(timerId);
+
+        /* Set timer mode periodic */
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
+        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
+
+        return SetTimerPeriod(timerId, msec);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Configures a periodic timer to generate timer interrupt just once
+*           after certain time interval
+*
+*  This function initializes a periodic timer to generate a single ticks after
+*  certain time interval in millisecond
+*
+*  @return   On success: Effective interval set in milli-second
+*            On failure: 0
+*
+*/
+/****************************************************************************/
+tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
+                                               tmrHw_INTERVAL_t msec    /*  [ IN ] Interval in milli-second */
+) {
+        ResetTimer(timerId);
+
+        /* Set timer mode oneshot */
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_ONESHOT;
+
+        return SetTimerPeriod(timerId, msec);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Configures a timer to run as a free running timer
+*
+*  This function initializes a timer to run as a free running timer
+*
+*  @return   Timer resolution (count / sec)
+*
+*/
+/****************************************************************************/
+tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
+                                       uint32_t divider /*  [ IN ] Dividing the clock frequency */
+) {
+        uint32_t scale = 0;
+
+        ResetTimer(timerId);
+        /* Set timer as free running mode */
+        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_PERIODIC;
+        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
+
+        if (divider >= 64) {
+                pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
+                scale = 256;
+        } else if (divider >= 8) {
+                pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
+                scale = 16;
+        } else {
+                pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
+                scale = 1;
+        }
+
+        if (timerId == 0 || timerId == 1) {
+                return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, scale);
+        } else if (timerId == 2 || timerId == 3) {
+                return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, scale);
+        }
+
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Starts a timer
+*
+*  This function starts a preconfigured timer
+*
+*  @return  -1     - On Failure
+*            0     - On Success
+*
+*/
+/****************************************************************************/
+int tmrHw_startTimer(tmrHw_ID_t timerId /*  [ IN ] Timer id */
+) {
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_TIMER_ENABLE;
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Stops a timer
+*
+*  This function stops a running timer
+*
+*  @return  -1     - On Failure
+*            0     - On Success
+*
+*/
+/****************************************************************************/
+int tmrHw_stopTimer(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
+) {
+        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_TIMER_ENABLE;
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Gets current timer count
+*
+*  This function returns the current timer value
+*
+*  @return  Current downcounting timer value
+*
+*/
+/****************************************************************************/
+uint32_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId       /*  [ IN ] Timer id */
+) {
+        /* return 32 bit timer value */
+        switch (pTmrHw[timerId].Control & tmrHw_CONTROL_MODE_MASK) {
+        case tmrHw_CONTROL_FREE_RUNNING:
+                if (pTmrHw[timerId].CurrentValue) {
+                        return tmrHw_MAX_COUNT - pTmrHw[timerId].CurrentValue;
+                }
+                break;
+        case tmrHw_CONTROL_PERIODIC:
+        case tmrHw_CONTROL_ONESHOT:
+                return pTmrHw[timerId].BackgroundLoad -
+                    pTmrHw[timerId].CurrentValue;
+        }
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Gets timer count rate
+*
+*  This function returns the number of counts per second
+*
+*  @return  Count rate
+*
+*/
+/****************************************************************************/
+tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId      /*  [ IN ] Timer id */
+) {
+        uint32_t divider = 0;
+
+        switch (pTmrHw[timerId].Control & tmrHw_CONTROL_PRESCALE_MASK) {
+        case tmrHw_CONTROL_PRESCALE_1:
+                divider = 1;
+                break;
+        case tmrHw_CONTROL_PRESCALE_16:
+                divider = 16;
+                break;
+        case tmrHw_CONTROL_PRESCALE_256:
+                divider = 256;
+                break;
+        default:
+                tmrHw_ASSERT(0);
+        }
+
+        if (timerId == 0 || timerId == 1) {
+                return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, divider);
+        } else {
+                return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, divider);
+        }
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Enables timer interrupt
+*
+*  This function enables the timer interrupt
+*
+*  @return   N/A
+*
+*/
+/****************************************************************************/
+void tmrHw_enableInterrupt(tmrHw_ID_t timerId   /*  [ IN ] Timer id */
+) {
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_INTERRUPT_ENABLE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Disables timer interrupt
+*
+*  This function disable the timer interrupt
+*
+*  @return   N/A
+*
+*/
+/****************************************************************************/
+void tmrHw_disableInterrupt(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
+) {
+        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_INTERRUPT_ENABLE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Clears the interrupt
+*
+*  This function clears the timer interrupt
+*
+*  @return   N/A
+*
+*  @note
+*     Must be called under the context of ISR
+*/
+/****************************************************************************/
+void tmrHw_clearInterrupt(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
+) {
+        pTmrHw[timerId].InterruptClear = 0x1;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Gets the interrupt status
+*
+*  This function returns timer interrupt status
+*
+*  @return   Interrupt status
+*/
+/****************************************************************************/
+tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
+) {
+        if (pTmrHw[timerId].InterruptStatus) {
+                return tmrHw_INTERRUPT_STATUS_SET;
+        } else {
+                return tmrHw_INTERRUPT_STATUS_UNSET;
+        }
+}
+
+/****************************************************************************/
+/**
+*  @brief   Indentifies a timer causing interrupt
+*
+*  This functions returns a timer causing interrupt
+*
+*  @return  0xFFFFFFFF   : No timer causing an interrupt
+*           ! 0xFFFFFFFF : timer causing an interrupt
+*  @note
+*     tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
+*/
+/****************************************************************************/
+tmrHw_ID_t tmrHw_getInterruptSource(void        /*  void */
+) {
+        int i;
+
+        for (i = 0; i < tmrHw_TIMER_NUM_COUNT; i++) {
+                if (pTmrHw[i].InterruptStatus) {
+                        return i;
+                }
+        }
+
+        return 0xFFFFFFFF;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Displays specific timer registers
+*
+*
+*  @return  void
+*
+*/
+/****************************************************************************/
+void tmrHw_printDebugInfo(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
+                          int (*fpPrint) (const char *, ...)    /*  [ IN ] Print callback function */
+) {
+        (*fpPrint) ("Displaying register contents \n\n");
+        (*fpPrint) ("Timer %d: Load value              0x%X\n", timerId,
+                    pTmrHw[timerId].LoadValue);
+        (*fpPrint) ("Timer %d: Background load value   0x%X\n", timerId,
+                    pTmrHw[timerId].BackgroundLoad);
+        (*fpPrint) ("Timer %d: Control                 0x%X\n", timerId,
+                    pTmrHw[timerId].Control);
+        (*fpPrint) ("Timer %d: Interrupt clear         0x%X\n", timerId,
+                    pTmrHw[timerId].InterruptClear);
+        (*fpPrint) ("Timer %d: Interrupt raw interrupt 0x%X\n", timerId,
+                    pTmrHw[timerId].RawInterruptStatus);
+        (*fpPrint) ("Timer %d: Interrupt status        0x%X\n", timerId,
+                    pTmrHw[timerId].InterruptStatus);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
+*
+*  @return   N/A
+*/
+/****************************************************************************/
+void tmrHw_udelay(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
+                  unsigned long usecs /*  [ IN ] usec to delay */
+) {
+        tmrHw_RATE_t usec_tick_rate;
+        tmrHw_COUNT_t start_time;
+        tmrHw_COUNT_t delta_time;
+
+        start_time = tmrHw_GetCurrentCount(timerId);
+        usec_tick_rate = tmrHw_divide(tmrHw_getCountRate(timerId), 1000000);
+        delta_time = usecs * usec_tick_rate;
+
+        /* Busy wait */
+        while (delta_time > (tmrHw_GetCurrentCount(timerId) - start_time))
+                ;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Local Divide function
+*
+*  This function does the divide
+*
+*  @return divide value
+*
+*/
+/****************************************************************************/
+static int tmrHw_divide(int num, int denom)
+{
+        int r;
+        int t = 1;
+
+        /* Shift denom and t up to the largest value to optimize algorithm */
+        /* t contains the units of each divide */
+        while ((denom & 0x40000000) == 0) {     /* fails if denom=0 */
+                denom = denom << 1;
+                t = t << 1;
+        }
+
+        /* Intialize the result */
+        r = 0;
+
+        do {
+                /* Determine if there exists a positive remainder */
+                if ((num - denom) >= 0) {
+                        /* Accumlate t to the result and calculate a new remainder */
+                        num = num - denom;
+                        r = r + t;
+                }
+                /* Continue to shift denom and shift t down to 0 */
+                denom = denom >> 1;
+                t = t >> 1;
+        } while (t != 0);
+        return r;
+}
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
new file mode 100644
index 000000000000..7b20fccb9d4e
--- /dev/null
+++ b/arch/arm/mach-bcmring/dma.c
@@ -0,0 +1,2321 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*   @file   dma.c
+*
+*   @brief  Implements the DMA interface.
+*/
+/****************************************************************************/
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/irqreturn.h>
+#include <linux/proc_fs.h>
+
+#include <mach/timer.h>
+
+#include <linux/mm.h>
+#include <linux/pfn.h>
+#include <asm/atomic.h>
+#include <mach/dma.h>
+
+/* I don't quite understand why dc4 fails when this is set to 1 and DMA is enabled */
+/* especially since dc4 doesn't use kmalloc'd memory. */
+
+#define ALLOW_MAP_OF_KMALLOC_MEMORY 0
+
+/* ---- Public Variables ------------------------------------------------- */
+
+/* ---- Private Constants and Types -------------------------------------- */
+
+#define MAKE_HANDLE(controllerIdx, channelIdx)    (((controllerIdx) << 4) | (channelIdx))
+
+#define CONTROLLER_FROM_HANDLE(handle)    (((handle) >> 4) & 0x0f)
+#define CHANNEL_FROM_HANDLE(handle)       ((handle) & 0x0f)
+
+#define DMA_MAP_DEBUG   0
+
+#if DMA_MAP_DEBUG
+#   define  DMA_MAP_PRINT(fmt, args...)   printk("%s: " fmt, __func__,  ## args)
+#else
+#   define  DMA_MAP_PRINT(fmt, args...)
+#endif
+
+/* ---- Private Variables ------------------------------------------------ */
+
+static DMA_Global_t gDMA;
+static struct proc_dir_entry *gDmaDir;
+
+static atomic_t gDmaStatMemTypeKmalloc = ATOMIC_INIT(0);
+static atomic_t gDmaStatMemTypeVmalloc = ATOMIC_INIT(0);
+static atomic_t gDmaStatMemTypeUser = ATOMIC_INIT(0);
+static atomic_t gDmaStatMemTypeCoherent = ATOMIC_INIT(0);
+
+#include "dma_device.c"
+
+/* ---- Private Function Prototypes -------------------------------------- */
+
+/* ---- Functions  ------------------------------------------------------- */
+
+/****************************************************************************/
+/**
+*   Displays information for /proc/dma/mem-type
+*/
+/****************************************************************************/
+
+static int dma_proc_read_mem_type(char *buf, char **start, off_t offset,
+                                  int count, int *eof, void *data)
+{
+        int len = 0;
+
+        len += sprintf(buf + len, "dma_map_mem statistics\n");
+        len +=
+            sprintf(buf + len, "coherent: %d\n",
+                    atomic_read(&gDmaStatMemTypeCoherent));
+        len +=
+            sprintf(buf + len, "kmalloc:  %d\n",
+                    atomic_read(&gDmaStatMemTypeKmalloc));
+        len +=
+            sprintf(buf + len, "vmalloc:  %d\n",
+                    atomic_read(&gDmaStatMemTypeVmalloc));
+        len +=
+            sprintf(buf + len, "user:     %d\n",
+                    atomic_read(&gDmaStatMemTypeUser));
+
+        return len;
+}
+
+/****************************************************************************/
+/**
+*   Displays information for /proc/dma/channels
+*/
+/****************************************************************************/
+
+static int dma_proc_read_channels(char *buf, char **start, off_t offset,
+                                  int count, int *eof, void *data)
+{
+        int controllerIdx;
+        int channelIdx;
+        int limit = count - 200;
+        int len = 0;
+        DMA_Channel_t *channel;
+
+        if (down_interruptible(&gDMA.lock) < 0) {
+                return -ERESTARTSYS;
+        }
+
+        for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
+             controllerIdx++) {
+                for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
+                     channelIdx++) {
+                        if (len >= limit) {
+                                break;
+                        }
+
+                        channel =
+                            &gDMA.controller[controllerIdx].channel[channelIdx];
+
+                        len +=
+                            sprintf(buf + len, "%d:%d ", controllerIdx,
+                                    channelIdx);
+
+                        if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
+                            0) {
+                                len +=
+                                    sprintf(buf + len, "Dedicated for %s ",
+                                            DMA_gDeviceAttribute[channel->
+                                                                 devType].name);
+                        } else {
+                                len += sprintf(buf + len, "Shared ");
+                        }
+
+                        if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) != 0) {
+                                len += sprintf(buf + len, "No ISR ");
+                        }
+
+                        if ((channel->flags & DMA_CHANNEL_FLAG_LARGE_FIFO) != 0) {
+                                len += sprintf(buf + len, "Fifo: 128 ");
+                        } else {
+                                len += sprintf(buf + len, "Fifo: 64  ");
+                        }
+
+                        if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
+                                len +=
+                                    sprintf(buf + len, "InUse by %s",
+                                            DMA_gDeviceAttribute[channel->
+                                                                 devType].name);
+#if (DMA_DEBUG_TRACK_RESERVATION)
+                                len +=
+                                    sprintf(buf + len, " (%s:%d)",
+                                            channel->fileName,
+                                            channel->lineNum);
+#endif
+                        } else {
+                                len += sprintf(buf + len, "Avail ");
+                        }
+
+                        if (channel->lastDevType != DMA_DEVICE_NONE) {
+                                len +=
+                                    sprintf(buf + len, "Last use: %s ",
+                                            DMA_gDeviceAttribute[channel->
+                                                                 lastDevType].
+                                            name);
+                        }
+
+                        len += sprintf(buf + len, "\n");
+                }
+        }
+        up(&gDMA.lock);
+        *eof = 1;
+
+        return len;
+}
+
+/****************************************************************************/
+/**
+*   Displays information for /proc/dma/devices
+*/
+/****************************************************************************/
+
+static int dma_proc_read_devices(char *buf, char **start, off_t offset,
+                                 int count, int *eof, void *data)
+{
+        int limit = count - 200;
+        int len = 0;
+        int devIdx;
+
+        if (down_interruptible(&gDMA.lock) < 0) {
+                return -ERESTARTSYS;
+        }
+
+        for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
+                DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
+
+                if (devAttr->name == NULL) {
+                        continue;
+                }
+
+                if (len >= limit) {
+                        break;
+                }
+
+                len += sprintf(buf + len, "%-12s ", devAttr->name);
+
+                if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
+                        len +=
+                            sprintf(buf + len, "Dedicated %d:%d ",
+                                    devAttr->dedicatedController,
+                                    devAttr->dedicatedChannel);
+                } else {
+                        len += sprintf(buf + len, "Shared DMA:");
+                        if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA0) != 0) {
+                                len += sprintf(buf + len, "0");
+                        }
+                        if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA1) != 0) {
+                                len += sprintf(buf + len, "1");
+                        }
+                        len += sprintf(buf + len, " ");
+                }
+                if ((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0) {
+                        len += sprintf(buf + len, "NoISR ");
+                }
+                if ((devAttr->flags & DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO) != 0) {
+                        len += sprintf(buf + len, "Allow-128 ");
+                }
+
+                len +=
+                    sprintf(buf + len,
+                            "Xfer #: %Lu Ticks: %Lu Bytes: %Lu DescLen: %u\n",
+                            devAttr->numTransfers, devAttr->transferTicks,
+                            devAttr->transferBytes,
+                            devAttr->ring.bytesAllocated);
+
+        }
+
+        up(&gDMA.lock);
+        *eof = 1;
+
+        return len;
+}
+
+/****************************************************************************/
+/**
+*   Determines if a DMA_Device_t is "valid".
+*
+*   @return
+*       TRUE        - dma device is valid
+*       FALSE       - dma device isn't valid
+*/
+/****************************************************************************/
+
+static inline int IsDeviceValid(DMA_Device_t device)
+{
+        return (device >= 0) && (device < DMA_NUM_DEVICE_ENTRIES);
+}
+
+/****************************************************************************/
+/**
+*   Translates a DMA handle into a pointer to a channel.
+*
+*   @return
+*       non-NULL    - pointer to DMA_Channel_t
+*       NULL        - DMA Handle was invalid
+*/
+/****************************************************************************/
+
+static inline DMA_Channel_t *HandleToChannel(DMA_Handle_t handle)
+{
+        int controllerIdx;
+        int channelIdx;
+
+        controllerIdx = CONTROLLER_FROM_HANDLE(handle);
+        channelIdx = CHANNEL_FROM_HANDLE(handle);
+
+        if ((controllerIdx > DMA_NUM_CONTROLLERS)
+            || (channelIdx > DMA_NUM_CHANNELS)) {
+                return NULL;
+        }
+        return &gDMA.controller[controllerIdx].channel[channelIdx];
+}
+
+/****************************************************************************/
+/**
+*   Interrupt handler which is called to process DMA interrupts.
+*/
+/****************************************************************************/
+
+static irqreturn_t dma_interrupt_handler(int irq, void *dev_id)
+{
+        DMA_Channel_t *channel;
+        DMA_DeviceAttribute_t *devAttr;
+        int irqStatus;
+
+        channel = (DMA_Channel_t *) dev_id;
+
+        /* Figure out why we were called, and knock down the interrupt */
+
+        irqStatus = dmacHw_getInterruptStatus(channel->dmacHwHandle);
+        dmacHw_clearInterrupt(channel->dmacHwHandle);
+
+        if ((channel->devType < 0)
+            || (channel->devType > DMA_NUM_DEVICE_ENTRIES)) {
+                printk(KERN_ERR "dma_interrupt_handler: Invalid devType: %d\n",
+                       channel->devType);
+                return IRQ_NONE;
+        }
+        devAttr = &DMA_gDeviceAttribute[channel->devType];
+
+        /* Update stats */
+
+        if ((irqStatus & dmacHw_INTERRUPT_STATUS_TRANS) != 0) {
+                devAttr->transferTicks +=
+                    (timer_get_tick_count() - devAttr->transferStartTime);
+        }
+
+        if ((irqStatus & dmacHw_INTERRUPT_STATUS_ERROR) != 0) {
+                printk(KERN_ERR
+                       "dma_interrupt_handler: devType :%d DMA error (%s)\n",
+                       channel->devType, devAttr->name);
+        } else {
+                devAttr->numTransfers++;
+                devAttr->transferBytes += devAttr->numBytes;
+        }
+
+        /* Call any installed handler */
+
+        if (devAttr->devHandler != NULL) {
+                devAttr->devHandler(channel->devType, irqStatus,
+                                    devAttr->userData);
+        }
+
+        return IRQ_HANDLED;
+}
+
+/****************************************************************************/
+/**
+*   Allocates memory to hold a descriptor ring. The descriptor ring then
+*   needs to be populated by making one or more calls to
+*   dna_add_descriptors.
+*
+*   The returned descriptor ring will be automatically initialized.
+*
+*   @return
+*       0           Descriptor ring was allocated successfully
+*       -EINVAL     Invalid parameters passed in
+*       -ENOMEM     Unable to allocate memory for the desired number of descriptors.
+*/
+/****************************************************************************/
+
+int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,       /* Descriptor ring to populate */
+                              int numDescriptors        /* Number of descriptors that need to be allocated. */
+    ) {
+        size_t bytesToAlloc = dmacHw_descriptorLen(numDescriptors);
+
+        if ((ring == NULL) || (numDescriptors <= 0)) {
+                return -EINVAL;
+        }
+
+        ring->physAddr = 0;
+        ring->descriptorsAllocated = 0;
+        ring->bytesAllocated = 0;
+
+        ring->virtAddr = dma_alloc_writecombine(NULL,
+                                                     bytesToAlloc,
+                                                     &ring->physAddr,
+                                                     GFP_KERNEL);
+        if (ring->virtAddr == NULL) {
+                return -ENOMEM;
+        }
+
+        ring->bytesAllocated = bytesToAlloc;
+        ring->descriptorsAllocated = numDescriptors;
+
+        return dma_init_descriptor_ring(ring, numDescriptors);
+}
+
+EXPORT_SYMBOL(dma_alloc_descriptor_ring);
+
+/****************************************************************************/
+/**
+*   Releases the memory which was previously allocated for a descriptor ring.
+*/
+/****************************************************************************/
+
+void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring        /* Descriptor to release */
+    ) {
+        if (ring->virtAddr != NULL) {
+                dma_free_writecombine(NULL,
+                                      ring->bytesAllocated,
+                                      ring->virtAddr, ring->physAddr);
+        }
+
+        ring->bytesAllocated = 0;
+        ring->descriptorsAllocated = 0;
+        ring->virtAddr = NULL;
+        ring->physAddr = 0;
+}
+
+EXPORT_SYMBOL(dma_free_descriptor_ring);
+
+/****************************************************************************/
+/**
+*   Initializes a descriptor ring, so that descriptors can be added to it.
+*   Once a descriptor ring has been allocated, it may be reinitialized for
+*   use with additional/different regions of memory.
+*
+*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
+*   initialize the ring with a smaller number of descriptors. The amount
+*   of memory allocated for the descriptor ring will not be reduced, and
+*   the descriptor ring may be reinitialized later
+*
+*   @return
+*       0           Descriptor ring was initialized successfully
+*       -ENOMEM     The descriptor which was passed in has insufficient space
+*                   to hold the desired number of descriptors.
+*/
+/****************************************************************************/
+
+int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,        /* Descriptor ring to initialize */
+                             int numDescriptors /* Number of descriptors to initialize. */
+    ) {
+        if (ring->virtAddr == NULL) {
+                return -EINVAL;
+        }
+        if (dmacHw_initDescriptor(ring->virtAddr,
+                                  ring->physAddr,
+                                  ring->bytesAllocated, numDescriptors) < 0) {
+                printk(KERN_ERR
+                       "dma_init_descriptor_ring: dmacHw_initDescriptor failed\n");
+                return -ENOMEM;
+        }
+
+        return 0;
+}
+
+EXPORT_SYMBOL(dma_init_descriptor_ring);
+
+/****************************************************************************/
+/**
+*   Determines the number of descriptors which would be required for a
+*   transfer of the indicated memory region.
+*
+*   This function also needs to know which DMA device this transfer will
+*   be destined for, so that the appropriate DMA configuration can be retrieved.
+*   DMA parameters such as transfer width, and whether this is a memory-to-memory
+*   or memory-to-peripheral, etc can all affect the actual number of descriptors
+*   required.
+*
+*   @return
+*       > 0     Returns the number of descriptors required for the indicated transfer
+*       -ENODEV - Device handed in is invalid.
+*       -EINVAL Invalid parameters
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+
+int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */
+                                   dma_addr_t srcData,  /* Place to get data to write to device */
+                                   dma_addr_t dstData,  /* Pointer to device data address */
+                                   size_t numBytes      /* Number of bytes to transfer to the device */
+    ) {
+        int numDescriptors;
+        DMA_DeviceAttribute_t *devAttr;
+
+        if (!IsDeviceValid(device)) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[device];
+
+        numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
+                                                              (void *)srcData,
+                                                              (void *)dstData,
+                                                              numBytes);
+        if (numDescriptors < 0) {
+                printk(KERN_ERR
+                       "dma_calculate_descriptor_count: dmacHw_calculateDescriptorCount failed\n");
+                return -EINVAL;
+        }
+
+        return numDescriptors;
+}
+
+EXPORT_SYMBOL(dma_calculate_descriptor_count);
+
+/****************************************************************************/
+/**
+*   Adds a region of memory to the descriptor ring. Note that it may take
+*   multiple descriptors for each region of memory. It is the callers
+*   responsibility to allocate a sufficiently large descriptor ring.
+*
+*   @return
+*       0       Descriptors were added successfully
+*       -ENODEV Device handed in is invalid.
+*       -EINVAL Invalid parameters
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+
+int dma_add_descriptors(DMA_DescriptorRing_t *ring,     /* Descriptor ring to add descriptors to */
+                        DMA_Device_t device,    /* DMA Device that descriptors are for */
+                        dma_addr_t srcData,     /* Place to get data (memory or device) */
+                        dma_addr_t dstData,     /* Place to put data (memory or device) */
+                        size_t numBytes /* Number of bytes to transfer to the device */
+    ) {
+        int rc;
+        DMA_DeviceAttribute_t *devAttr;
+
+        if (!IsDeviceValid(device)) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[device];
+
+        rc = dmacHw_setDataDescriptor(&devAttr->config,
+                                      ring->virtAddr,
+                                      (void *)srcData,
+                                      (void *)dstData, numBytes);
+        if (rc < 0) {
+                printk(KERN_ERR
+                       "dma_add_descriptors: dmacHw_setDataDescriptor failed with code: %d\n",
+                       rc);
+                return -ENOMEM;
+        }
+
+        return 0;
+}
+
+EXPORT_SYMBOL(dma_add_descriptors);
+
+/****************************************************************************/
+/**
+*   Sets the descriptor ring associated with a device.
+*
+*   Once set, the descriptor ring will be associated with the device, even
+*   across channel request/free calls. Passing in a NULL descriptor ring
+*   will release any descriptor ring currently associated with the device.
+*
+*   Note: If you call dma_transfer, or one of the other dma_alloc_ functions
+*         the descriptor ring may be released and reallocated.
+*
+*   Note: This function will release the descriptor memory for any current
+*         descriptor ring associated with this device.
+*
+*   @return
+*       0       Descriptors were added successfully
+*       -ENODEV Device handed in is invalid.
+*/
+/****************************************************************************/
+
+int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */
+                                   DMA_DescriptorRing_t *ring   /* Descriptor ring to add descriptors to */
+    ) {
+        DMA_DeviceAttribute_t *devAttr;
+
+        if (!IsDeviceValid(device)) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[device];
+
+        /* Free the previously allocated descriptor ring */
+
+        dma_free_descriptor_ring(&devAttr->ring);
+
+        if (ring != NULL) {
+                /* Copy in the new one */
+
+                devAttr->ring = *ring;
+        }
+
+        /* Set things up so that if dma_transfer is called then this descriptor */
+        /* ring will get freed. */
+
+        devAttr->prevSrcData = 0;
+        devAttr->prevDstData = 0;
+        devAttr->prevNumBytes = 0;
+
+        return 0;
+}
+
+EXPORT_SYMBOL(dma_set_device_descriptor_ring);
+
+/****************************************************************************/
+/**
+*   Retrieves the descriptor ring associated with a device.
+*
+*   @return
+*       0       Descriptors were added successfully
+*       -ENODEV Device handed in is invalid.
+*/
+/****************************************************************************/
+
+int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */
+                                   DMA_DescriptorRing_t *ring   /* Place to store retrieved ring */
+    ) {
+        DMA_DeviceAttribute_t *devAttr;
+
+        memset(ring, 0, sizeof(*ring));
+
+        if (!IsDeviceValid(device)) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[device];
+
+        *ring = devAttr->ring;
+
+        return 0;
+}
+
+EXPORT_SYMBOL(dma_get_device_descriptor_ring);
+
+/****************************************************************************/
+/**
+*   Configures a DMA channel.
+*
+*   @return
+*       >= 0    - Initialization was successfull.
+*
+*       -EBUSY  - Device is currently being used.
+*       -ENODEV - Device handed in is invalid.
+*/
+/****************************************************************************/
+
+static int ConfigChannel(DMA_Handle_t handle)
+{
+        DMA_Channel_t *channel;
+        DMA_DeviceAttribute_t *devAttr;
+        int controllerIdx;
+
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[channel->devType];
+        controllerIdx = CONTROLLER_FROM_HANDLE(handle);
+
+        if ((devAttr->flags & DMA_DEVICE_FLAG_PORT_PER_DMAC) != 0) {
+                if (devAttr->config.transferType ==
+                    dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL) {
+                        devAttr->config.dstPeripheralPort =
+                            devAttr->dmacPort[controllerIdx];
+                } else if (devAttr->config.transferType ==
+                           dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) {
+                        devAttr->config.srcPeripheralPort =
+                            devAttr->dmacPort[controllerIdx];
+                }
+        }
+
+        if (dmacHw_configChannel(channel->dmacHwHandle, &devAttr->config) != 0) {
+                printk(KERN_ERR "ConfigChannel: dmacHw_configChannel failed\n");
+                return -EIO;
+        }
+
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*   Intializes all of the data structures associated with the DMA.
+*   @return
+*       >= 0    - Initialization was successfull.
+*
+*       -EBUSY  - Device is currently being used.
+*       -ENODEV - Device handed in is invalid.
+*/
+/****************************************************************************/
+
+int dma_init(void)
+{
+        int rc = 0;
+        int controllerIdx;
+        int channelIdx;
+        DMA_Device_t devIdx;
+        DMA_Channel_t *channel;
+        DMA_Handle_t dedicatedHandle;
+
+        memset(&gDMA, 0, sizeof(gDMA));
+
+        init_MUTEX_LOCKED(&gDMA.lock);
+        init_waitqueue_head(&gDMA.freeChannelQ);
+
+        /* Initialize the Hardware */
+
+        dmacHw_initDma();
+
+        /* Start off by marking all of the DMA channels as shared. */
+
+        for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
+             controllerIdx++) {
+                for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
+                     channelIdx++) {
+                        channel =
+                            &gDMA.controller[controllerIdx].channel[channelIdx];
+
+                        channel->flags = 0;
+                        channel->devType = DMA_DEVICE_NONE;
+                        channel->lastDevType = DMA_DEVICE_NONE;
+
+#if (DMA_DEBUG_TRACK_RESERVATION)
+                        channel->fileName = "";
+                        channel->lineNum = 0;
+#endif
+
+                        channel->dmacHwHandle =
+                            dmacHw_getChannelHandle(dmacHw_MAKE_CHANNEL_ID
+                                                    (controllerIdx,
+                                                     channelIdx));
+                        dmacHw_initChannel(channel->dmacHwHandle);
+                }
+        }
+
+        /* Record any special attributes that channels may have */
+
+        gDMA.controller[0].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
+        gDMA.controller[0].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
+        gDMA.controller[1].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
+        gDMA.controller[1].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
+
+        /* Now walk through and record the dedicated channels. */
+
+        for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
+                DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
+
+                if (((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0)
+                    && ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0)) {
+                        printk(KERN_ERR
+                               "DMA Device: %s Can only request NO_ISR for dedicated devices\n",
+                               devAttr->name);
+                        rc = -EINVAL;
+                        goto out;
+                }
+
+                if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
+                        /* This is a dedicated device. Mark the channel as being reserved. */
+
+                        if (devAttr->dedicatedController >= DMA_NUM_CONTROLLERS) {
+                                printk(KERN_ERR
+                                       "DMA Device: %s DMA Controller %d is out of range\n",
+                                       devAttr->name,
+                                       devAttr->dedicatedController);
+                                rc = -EINVAL;
+                                goto out;
+                        }
+
+                        if (devAttr->dedicatedChannel >= DMA_NUM_CHANNELS) {
+                                printk(KERN_ERR
+                                       "DMA Device: %s DMA Channel %d is out of range\n",
+                                       devAttr->name,
+                                       devAttr->dedicatedChannel);
+                                rc = -EINVAL;
+                                goto out;
+                        }
+
+                        dedicatedHandle =
+                            MAKE_HANDLE(devAttr->dedicatedController,
+                                        devAttr->dedicatedChannel);
+                        channel = HandleToChannel(dedicatedHandle);
+
+                        if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
+                            0) {
+                                printk
+                                    ("DMA Device: %s attempting to use same DMA Controller:Channel (%d:%d) as %s\n",
+                                     devAttr->name,
+                                     devAttr->dedicatedController,
+                                     devAttr->dedicatedChannel,
+                                     DMA_gDeviceAttribute[channel->devType].
+                                     name);
+                                rc = -EBUSY;
+                                goto out;
+                        }
+
+                        channel->flags |= DMA_CHANNEL_FLAG_IS_DEDICATED;
+                        channel->devType = devIdx;
+
+                        if (devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) {
+                                channel->flags |= DMA_CHANNEL_FLAG_NO_ISR;
+                        }
+
+                        /* For dedicated channels, we can go ahead and configure the DMA channel now */
+                        /* as well. */
+
+                        ConfigChannel(dedicatedHandle);
+                }
+        }
+
+        /* Go through and register the interrupt handlers */
+
+        for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
+             controllerIdx++) {
+                for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
+                     channelIdx++) {
+                        channel =
+                            &gDMA.controller[controllerIdx].channel[channelIdx];
+
+                        if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) == 0) {
+                                snprintf(channel->name, sizeof(channel->name),
+                                         "dma %d:%d %s", controllerIdx,
+                                         channelIdx,
+                                         channel->devType ==
+                                         DMA_DEVICE_NONE ? "" :
+                                         DMA_gDeviceAttribute[channel->devType].
+                                         name);
+
+                                rc =
+                                     request_irq(IRQ_DMA0C0 +
+                                                 (controllerIdx *
+                                                  DMA_NUM_CHANNELS) +
+                                                 channelIdx,
+                                                 dma_interrupt_handler,
+                                                 IRQF_DISABLED, channel->name,
+                                                 channel);
+                                if (rc != 0) {
+                                        printk(KERN_ERR
+                                               "request_irq for IRQ_DMA%dC%d failed\n",
+                                               controllerIdx, channelIdx);
+                                }
+                        }
+                }
+        }
+
+        /* Create /proc/dma/channels and /proc/dma/devices */
+
+        gDmaDir = create_proc_entry("dma", S_IFDIR | S_IRUGO | S_IXUGO, NULL);
+
+        if (gDmaDir == NULL) {
+                printk(KERN_ERR "Unable to create /proc/dma\n");
+        } else {
+                create_proc_read_entry("channels", 0, gDmaDir,
+                                       dma_proc_read_channels, NULL);
+                create_proc_read_entry("devices", 0, gDmaDir,
+                                       dma_proc_read_devices, NULL);
+                create_proc_read_entry("mem-type", 0, gDmaDir,
+                                       dma_proc_read_mem_type, NULL);
+        }
+
+out:
+
+        up(&gDMA.lock);
+
+        return rc;
+}
+
+/****************************************************************************/
+/**
+*   Reserves a channel for use with @a dev. If the device is setup to use
+*   a shared channel, then this function will block until a free channel
+*   becomes available.
+*
+*   @return
+*       >= 0    - A valid DMA Handle.
+*       -EBUSY  - Device is currently being used.
+*       -ENODEV - Device handed in is invalid.
+*/
+/****************************************************************************/
+
+#if (DMA_DEBUG_TRACK_RESERVATION)
+DMA_Handle_t dma_request_channel_dbg
+    (DMA_Device_t dev, const char *fileName, int lineNum)
+#else
+DMA_Handle_t dma_request_channel(DMA_Device_t dev)
+#endif
+{
+        DMA_Handle_t handle;
+        DMA_DeviceAttribute_t *devAttr;
+        DMA_Channel_t *channel;
+        int controllerIdx;
+        int controllerIdx2;
+        int channelIdx;
+
+        if (down_interruptible(&gDMA.lock) < 0) {
+                return -ERESTARTSYS;
+        }
+
+        if ((dev < 0) || (dev >= DMA_NUM_DEVICE_ENTRIES)) {
+                handle = -ENODEV;
+                goto out;
+        }
+        devAttr = &DMA_gDeviceAttribute[dev];
+
+#if (DMA_DEBUG_TRACK_RESERVATION)
+        {
+                char *s;
+
+                s = strrchr(fileName, '/');
+                if (s != NULL) {
+                        fileName = s + 1;
+                }
+        }
+#endif
+        if ((devAttr->flags & DMA_DEVICE_FLAG_IN_USE) != 0) {
+                /* This device has already been requested and not been freed */
+
+                printk(KERN_ERR "%s: device %s is already requested\n",
+                       __func__, devAttr->name);
+                handle = -EBUSY;
+                goto out;
+        }
+
+        if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
+                /* This device has a dedicated channel. */
+
+                channel =
+                    &gDMA.controller[devAttr->dedicatedController].
+                    channel[devAttr->dedicatedChannel];
+                if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
+                        handle = -EBUSY;
+                        goto out;
+                }
+
+                channel->flags |= DMA_CHANNEL_FLAG_IN_USE;
+                devAttr->flags |= DMA_DEVICE_FLAG_IN_USE;
+
+#if (DMA_DEBUG_TRACK_RESERVATION)
+                channel->fileName = fileName;
+                channel->lineNum = lineNum;
+#endif
+                handle =
+                    MAKE_HANDLE(devAttr->dedicatedController,
+                                devAttr->dedicatedChannel);
+                goto out;
+        }
+
+        /* This device needs to use one of the shared channels. */
+
+        handle = DMA_INVALID_HANDLE;
+        while (handle == DMA_INVALID_HANDLE) {
+                /* Scan through the shared channels and see if one is available */
+
+                for (controllerIdx2 = 0; controllerIdx2 < DMA_NUM_CONTROLLERS;
+                     controllerIdx2++) {
+                        /* Check to see if we should try on controller 1 first. */
+
+                        controllerIdx = controllerIdx2;
+                        if ((devAttr->
+                             flags & DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST) != 0) {
+                                controllerIdx = 1 - controllerIdx;
+                        }
+
+                        /* See if the device is available on the controller being tested */
+
+                        if ((devAttr->
+                             flags & (DMA_DEVICE_FLAG_ON_DMA0 << controllerIdx))
+                            != 0) {
+                                for (channelIdx = 0;
+                                     channelIdx < DMA_NUM_CHANNELS;
+                                     channelIdx++) {
+                                        channel =
+                                            &gDMA.controller[controllerIdx].
+                                            channel[channelIdx];
+
+                                        if (((channel->
+                                              flags &
+                                              DMA_CHANNEL_FLAG_IS_DEDICATED) ==
+                                             0)
+                                            &&
+                                            ((channel->
+                                              flags & DMA_CHANNEL_FLAG_IN_USE)
+                                             == 0)) {
+                                                if (((channel->
+                                                      flags &
+                                                      DMA_CHANNEL_FLAG_LARGE_FIFO)
+                                                     != 0)
+                                                    &&
+                                                    ((devAttr->
+                                                      flags &
+                                                      DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO)
+                                                     == 0)) {
+                                                        /* This channel is a large fifo - don't tie it up */
+                                                        /* with devices that we don't want using it. */
+
+                                                        continue;
+                                                }
+
+                                                channel->flags |=
+                                                    DMA_CHANNEL_FLAG_IN_USE;
+                                                channel->devType = dev;
+                                                devAttr->flags |=
+                                                    DMA_DEVICE_FLAG_IN_USE;
+
+#if (DMA_DEBUG_TRACK_RESERVATION)
+                                                channel->fileName = fileName;
+                                                channel->lineNum = lineNum;
+#endif
+                                                handle =
+                                                    MAKE_HANDLE(controllerIdx,
+                                                                channelIdx);
+
+                                                /* Now that we've reserved the channel - we can go ahead and configure it */
+
+                                                if (ConfigChannel(handle) != 0) {
+                                                        handle = -EIO;
+                                                        printk(KERN_ERR
+                                                               "dma_request_channel: ConfigChannel failed\n");
+                                                }
+                                                goto out;
+                                        }
+                                }
+                        }
+                }
+
+                /* No channels are currently available. Let's wait for one to free up. */
+
+                {
+                        DEFINE_WAIT(wait);
+
+                        prepare_to_wait(&gDMA.freeChannelQ, &wait,
+                                        TASK_INTERRUPTIBLE);
+                        up(&gDMA.lock);
+                        schedule();
+                        finish_wait(&gDMA.freeChannelQ, &wait);
+
+                        if (signal_pending(current)) {
+                                /* We don't currently hold gDMA.lock, so we return directly */
+
+                                return -ERESTARTSYS;
+                        }
+                }
+
+                if (down_interruptible(&gDMA.lock)) {
+                        return -ERESTARTSYS;
+                }
+        }
+
+out:
+        up(&gDMA.lock);
+
+        return handle;
+}
+
+/* Create both _dbg and non _dbg functions for modules. */
+
+#if (DMA_DEBUG_TRACK_RESERVATION)
+#undef dma_request_channel
+DMA_Handle_t dma_request_channel(DMA_Device_t dev)
+{
+        return dma_request_channel_dbg(dev, __FILE__, __LINE__);
+}
+
+EXPORT_SYMBOL(dma_request_channel_dbg);
+#endif
+EXPORT_SYMBOL(dma_request_channel);
+
+/****************************************************************************/
+/**
+*   Frees a previously allocated DMA Handle.
+*/
+/****************************************************************************/
+
+int dma_free_channel(DMA_Handle_t handle        /* DMA handle. */
+    ) {
+        int rc = 0;
+        DMA_Channel_t *channel;
+        DMA_DeviceAttribute_t *devAttr;
+
+        if (down_interruptible(&gDMA.lock) < 0) {
+                return -ERESTARTSYS;
+        }
+
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                rc = -EINVAL;
+                goto out;
+        }
+
+        devAttr = &DMA_gDeviceAttribute[channel->devType];
+
+        if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) == 0) {
+                channel->lastDevType = channel->devType;
+                channel->devType = DMA_DEVICE_NONE;
+        }
+        channel->flags &= ~DMA_CHANNEL_FLAG_IN_USE;
+        devAttr->flags &= ~DMA_DEVICE_FLAG_IN_USE;
+
+out:
+        up(&gDMA.lock);
+
+        wake_up_interruptible(&gDMA.freeChannelQ);
+
+        return rc;
+}
+
+EXPORT_SYMBOL(dma_free_channel);
+
+/****************************************************************************/
+/**
+*   Determines if a given device has been configured as using a shared
+*   channel.
+*
+*   @return
+*       0           Device uses a dedicated channel
+*       > zero      Device uses a shared channel
+*       < zero      Error code
+*/
+/****************************************************************************/
+
+int dma_device_is_channel_shared(DMA_Device_t device    /* Device to check. */
+    ) {
+        DMA_DeviceAttribute_t *devAttr;
+
+        if (!IsDeviceValid(device)) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[device];
+
+        return ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0);
+}
+
+EXPORT_SYMBOL(dma_device_is_channel_shared);
+
+/****************************************************************************/
+/**
+*   Allocates buffers for the descriptors. This is normally done automatically
+*   but needs to be done explicitly when initiating a dma from interrupt
+*   context.
+*
+*   @return
+*       0       Descriptors were allocated successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+
+int dma_alloc_descriptors(DMA_Handle_t handle,  /* DMA Handle */
+                          dmacHw_TRANSFER_TYPE_e transferType,  /* Type of transfer being performed */
+                          dma_addr_t srcData,   /* Place to get data to write to device */
+                          dma_addr_t dstData,   /* Pointer to device data address */
+                          size_t numBytes       /* Number of bytes to transfer to the device */
+    ) {
+        DMA_Channel_t *channel;
+        DMA_DeviceAttribute_t *devAttr;
+        int numDescriptors;
+        size_t ringBytesRequired;
+        int rc = 0;
+
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                return -ENODEV;
+        }
+
+        devAttr = &DMA_gDeviceAttribute[channel->devType];
+
+        if (devAttr->config.transferType != transferType) {
+                return -EINVAL;
+        }
+
+        /* Figure out how many descriptors we need. */
+
+        /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
+        /*        srcData, dstData, numBytes); */
+
+        numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
+                                                              (void *)srcData,
+                                                              (void *)dstData,
+                                                              numBytes);
+        if (numDescriptors < 0) {
+                printk(KERN_ERR "%s: dmacHw_calculateDescriptorCount failed\n",
+                       __func__);
+                return -EINVAL;
+        }
+
+        /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */
+        /* a new one. */
+
+        ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
+
+        /* printk("ringBytesRequired: %d\n", ringBytesRequired); */
+
+        if (ringBytesRequired > devAttr->ring.bytesAllocated) {
+                /* Make sure that this code path is never taken from interrupt context. */
+                /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */
+                /* allocation needs to have already been done. */
+
+                might_sleep();
+
+                /* Free the old descriptor ring and allocate a new one. */
+
+                dma_free_descriptor_ring(&devAttr->ring);
+
+                /* And allocate a new one. */
+
+                rc =
+                     dma_alloc_descriptor_ring(&devAttr->ring,
+                                               numDescriptors);
+                if (rc < 0) {
+                        printk(KERN_ERR
+                               "%s: dma_alloc_descriptor_ring(%d) failed\n",
+                               __func__, numDescriptors);
+                        return rc;
+                }
+                /* Setup the descriptor for this transfer */
+
+                if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
+                                          devAttr->ring.physAddr,
+                                          devAttr->ring.bytesAllocated,
+                                          numDescriptors) < 0) {
+                        printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n",
+                               __func__);
+                        return -EINVAL;
+                }
+        } else {
+                /* We've already got enough ring buffer allocated. All we need to do is reset */
+                /* any control information, just in case the previous DMA was stopped. */
+
+                dmacHw_resetDescriptorControl(devAttr->ring.virtAddr);
+        }
+
+        /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */
+        /* as last time, then we don't need to call setDataDescriptor again. */
+
+        if (dmacHw_setDataDescriptor(&devAttr->config,
+                                     devAttr->ring.virtAddr,
+                                     (void *)srcData,
+                                     (void *)dstData, numBytes) < 0) {
+                printk(KERN_ERR "%s: dmacHw_setDataDescriptor failed\n",
+                       __func__);
+                return -EINVAL;
+        }
+
+        /* Remember the critical information for this transfer so that we can eliminate */
+        /* another call to dma_alloc_descriptors if the caller reuses the same buffers */
+
+        devAttr->prevSrcData = srcData;
+        devAttr->prevDstData = dstData;
+        devAttr->prevNumBytes = numBytes;
+
+        return 0;
+}
+
+EXPORT_SYMBOL(dma_alloc_descriptors);
+
+/****************************************************************************/
+/**
+*   Allocates and sets up descriptors for a double buffered circular buffer.
+*
+*   This is primarily intended to be used for things like the ingress samples
+*   from a microphone.
+*
+*   @return
+*       > 0     Number of descriptors actually allocated.
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+
+int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,       /* DMA Handle */
+                                     dma_addr_t srcData,        /* Physical address of source data */
+                                     dma_addr_t dstData1,       /* Physical address of first destination buffer */
+                                     dma_addr_t dstData2,       /* Physical address of second destination buffer */
+                                     size_t numBytes    /* Number of bytes in each destination buffer */
+    ) {
+        DMA_Channel_t *channel;
+        DMA_DeviceAttribute_t *devAttr;
+        int numDst1Descriptors;
+        int numDst2Descriptors;
+        int numDescriptors;
+        size_t ringBytesRequired;
+        int rc = 0;
+
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                return -ENODEV;
+        }
+
+        devAttr = &DMA_gDeviceAttribute[channel->devType];
+
+        /* Figure out how many descriptors we need. */
+
+        /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
+        /*        srcData, dstData, numBytes); */
+
+        numDst1Descriptors =
+             dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
+                                             (void *)dstData1, numBytes);
+        if (numDst1Descriptors < 0) {
+                return -EINVAL;
+        }
+        numDst2Descriptors =
+             dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
+                                             (void *)dstData2, numBytes);
+        if (numDst2Descriptors < 0) {
+                return -EINVAL;
+        }
+        numDescriptors = numDst1Descriptors + numDst2Descriptors;
+        /* printk("numDescriptors: %d\n", numDescriptors); */
+
+        /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */
+        /* a new one. */
+
+        ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
+
+        /* printk("ringBytesRequired: %d\n", ringBytesRequired); */
+
+        if (ringBytesRequired > devAttr->ring.bytesAllocated) {
+                /* Make sure that this code path is never taken from interrupt context. */
+                /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */
+                /* allocation needs to have already been done. */
+
+                might_sleep();
+
+                /* Free the old descriptor ring and allocate a new one. */
+
+                dma_free_descriptor_ring(&devAttr->ring);
+
+                /* And allocate a new one. */
+
+                rc =
+                     dma_alloc_descriptor_ring(&devAttr->ring,
+                                               numDescriptors);
+                if (rc < 0) {
+                        printk(KERN_ERR
+                               "%s: dma_alloc_descriptor_ring(%d) failed\n",
+                               __func__, ringBytesRequired);
+                        return rc;
+                }
+        }
+
+        /* Setup the descriptor for this transfer. Since this function is used with */
+        /* CONTINUOUS DMA operations, we need to reinitialize every time, otherwise */
+        /* setDataDescriptor will keep trying to append onto the end. */
+
+        if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
+                                  devAttr->ring.physAddr,
+                                  devAttr->ring.bytesAllocated,
+                                  numDescriptors) < 0) {
+                printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n", __func__);
+                return -EINVAL;
+        }
+
+        /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */
+        /* as last time, then we don't need to call setDataDescriptor again. */
+
+        if (dmacHw_setDataDescriptor(&devAttr->config,
+                                     devAttr->ring.virtAddr,
+                                     (void *)srcData,
+                                     (void *)dstData1, numBytes) < 0) {
+                printk(KERN_ERR "%s: dmacHw_setDataDescriptor 1 failed\n",
+                       __func__);
+                return -EINVAL;
+        }
+        if (dmacHw_setDataDescriptor(&devAttr->config,
+                                     devAttr->ring.virtAddr,
+                                     (void *)srcData,
+                                     (void *)dstData2, numBytes) < 0) {
+                printk(KERN_ERR "%s: dmacHw_setDataDescriptor 2 failed\n",
+                       __func__);
+                return -EINVAL;
+        }
+
+        /* You should use dma_start_transfer rather than dma_transfer_xxx so we don't */
+        /* try to make the 'prev' variables right. */
+
+        devAttr->prevSrcData = 0;
+        devAttr->prevDstData = 0;
+        devAttr->prevNumBytes = 0;
+
+        return numDescriptors;
+}
+
+EXPORT_SYMBOL(dma_alloc_double_dst_descriptors);
+
+/****************************************************************************/
+/**
+*   Initiates a transfer when the descriptors have already been setup.
+*
+*   This is a special case, and normally, the dma_transfer_xxx functions should
+*   be used.
+*
+*   @return
+*       0       Transfer was started successfully
+*       -ENODEV Invalid handle
+*/
+/****************************************************************************/
+
+int dma_start_transfer(DMA_Handle_t handle)
+{
+        DMA_Channel_t *channel;
+        DMA_DeviceAttribute_t *devAttr;
+
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[channel->devType];
+
+        dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
+                                devAttr->ring.virtAddr);
+
+        /* Since we got this far, everything went successfully */
+
+        return 0;
+}
+
+EXPORT_SYMBOL(dma_start_transfer);
+
+/****************************************************************************/
+/**
+*   Stops a previously started DMA transfer.
+*
+*   @return
+*       0       Transfer was stopped successfully
+*       -ENODEV Invalid handle
+*/
+/****************************************************************************/
+
+int dma_stop_transfer(DMA_Handle_t handle)
+{
+        DMA_Channel_t *channel;
+
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                return -ENODEV;
+        }
+
+        dmacHw_stopTransfer(channel->dmacHwHandle);
+
+        return 0;
+}
+
+EXPORT_SYMBOL(dma_stop_transfer);
+
+/****************************************************************************/
+/**
+*   Waits for a DMA to complete by polling. This function is only intended
+*   to be used for testing. Interrupts should be used for most DMA operations.
+*/
+/****************************************************************************/
+
+int dma_wait_transfer_done(DMA_Handle_t handle)
+{
+        DMA_Channel_t *channel;
+        dmacHw_TRANSFER_STATUS_e status;
+
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                return -ENODEV;
+        }
+
+        while ((status =
+                dmacHw_transferCompleted(channel->dmacHwHandle)) ==
+               dmacHw_TRANSFER_STATUS_BUSY) {
+                ;
+        }
+
+        if (status == dmacHw_TRANSFER_STATUS_ERROR) {
+                printk(KERN_ERR "%s: DMA transfer failed\n", __func__);
+                return -EIO;
+        }
+        return 0;
+}
+
+EXPORT_SYMBOL(dma_wait_transfer_done);
+
+/****************************************************************************/
+/**
+*   Initiates a DMA, allocating the descriptors as required.
+*
+*   @return
+*       0       Transfer was started successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
+*/
+/****************************************************************************/
+
+int dma_transfer(DMA_Handle_t handle,   /* DMA Handle */
+                 dmacHw_TRANSFER_TYPE_e transferType,   /* Type of transfer being performed */
+                 dma_addr_t srcData,    /* Place to get data to write to device */
+                 dma_addr_t dstData,    /* Pointer to device data address */
+                 size_t numBytes        /* Number of bytes to transfer to the device */
+    ) {
+        DMA_Channel_t *channel;
+        DMA_DeviceAttribute_t *devAttr;
+        int rc = 0;
+
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                return -ENODEV;
+        }
+
+        devAttr = &DMA_gDeviceAttribute[channel->devType];
+
+        if (devAttr->config.transferType != transferType) {
+                return -EINVAL;
+        }
+
+        /* We keep track of the information about the previous request for this */
+        /* device, and if the attributes match, then we can use the descriptors we setup */
+        /* the last time, and not have to reinitialize everything. */
+
+        {
+                rc =
+                     dma_alloc_descriptors(handle, transferType, srcData,
+                                           dstData, numBytes);
+                if (rc != 0) {
+                        return rc;
+                }
+        }
+
+        /* And kick off the transfer */
+
+        devAttr->numBytes = numBytes;
+        devAttr->transferStartTime = timer_get_tick_count();
+
+        dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
+                                devAttr->ring.virtAddr);
+
+        /* Since we got this far, everything went successfully */
+
+        return 0;
+}
+
+EXPORT_SYMBOL(dma_transfer);
+
+/****************************************************************************/
+/**
+*   Set the callback function which will be called when a transfer completes.
+*   If a NULL callback function is set, then no callback will occur.
+*
+*   @note   @a devHandler will be called from IRQ context.
+*
+*   @return
+*       0       - Success
+*       -ENODEV - Device handed in is invalid.
+*/
+/****************************************************************************/
+
+int dma_set_device_handler(DMA_Device_t dev,    /* Device to set the callback for. */
+                           DMA_DeviceHandler_t devHandler,      /* Function to call when the DMA completes */
+                           void *userData       /* Pointer which will be passed to devHandler. */
+    ) {
+        DMA_DeviceAttribute_t *devAttr;
+        unsigned long flags;
+
+        if (!IsDeviceValid(dev)) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[dev];
+
+        local_irq_save(flags);
+
+        devAttr->userData = userData;
+        devAttr->devHandler = devHandler;
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+EXPORT_SYMBOL(dma_set_device_handler);
+
+/****************************************************************************/
+/**
+*   Initializes a memory mapping structure
+*/
+/****************************************************************************/
+
+int dma_init_mem_map(DMA_MemMap_t *memMap)
+{
+        memset(memMap, 0, sizeof(*memMap));
+
+        init_MUTEX(&memMap->lock);
+
+        return 0;
+}
+
+EXPORT_SYMBOL(dma_init_mem_map);
+
+/****************************************************************************/
+/**
+*   Releases any memory currently being held by a memory mapping structure.
+*/
+/****************************************************************************/
+
+int dma_term_mem_map(DMA_MemMap_t *memMap)
+{
+        down(&memMap->lock);    /* Just being paranoid */
+
+        /* Free up any allocated memory */
+
+        up(&memMap->lock);
+        memset(memMap, 0, sizeof(*memMap));
+
+        return 0;
+}
+
+EXPORT_SYMBOL(dma_term_mem_map);
+
+/****************************************************************************/
+/**
+*   Looks at a memory address and categorizes it.
+*
+*   @return One of the values from the DMA_MemType_t enumeration.
+*/
+/****************************************************************************/
+
+DMA_MemType_t dma_mem_type(void *addr)
+{
+        unsigned long addrVal = (unsigned long)addr;
+
+        if (addrVal >= VMALLOC_END) {
+                /* NOTE: DMA virtual memory space starts at 0xFFxxxxxx */
+
+                /* dma_alloc_xxx pages are physically and virtually contiguous */
+
+                return DMA_MEM_TYPE_DMA;
+        }
+
+        /* Technically, we could add one more classification. Addresses between VMALLOC_END */
+        /* and the beginning of the DMA virtual address could be considered to be I/O space. */
+        /* Right now, nobody cares about this particular classification, so we ignore it. */
+
+        if (is_vmalloc_addr(addr)) {
+                /* Address comes from the vmalloc'd region. Pages are virtually */
+                /* contiguous but NOT physically contiguous */
+
+                return DMA_MEM_TYPE_VMALLOC;
+        }
+
+        if (addrVal >= PAGE_OFFSET) {
+                /* PAGE_OFFSET is typically 0xC0000000 */
+
+                /* kmalloc'd pages are physically contiguous */
+
+                return DMA_MEM_TYPE_KMALLOC;
+        }
+
+        return DMA_MEM_TYPE_USER;
+}
+
+EXPORT_SYMBOL(dma_mem_type);
+
+/****************************************************************************/
+/**
+*   Looks at a memory address and determines if we support DMA'ing to/from
+*   that type of memory.
+*
+*   @return boolean -
+*               return value != 0 means dma supported
+*               return value == 0 means dma not supported
+*/
+/****************************************************************************/
+
+int dma_mem_supports_dma(void *addr)
+{
+        DMA_MemType_t memType = dma_mem_type(addr);
+
+        return (memType == DMA_MEM_TYPE_DMA)
+#if ALLOW_MAP_OF_KMALLOC_MEMORY
+            || (memType == DMA_MEM_TYPE_KMALLOC)
+#endif
+            || (memType == DMA_MEM_TYPE_USER);
+}
+
+EXPORT_SYMBOL(dma_mem_supports_dma);
+
+/****************************************************************************/
+/**
+*   Maps in a memory region such that it can be used for performing a DMA.
+*
+*   @return
+*/
+/****************************************************************************/
+
+int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */
+                  enum dma_data_direction dir   /* Direction that the mapping will be going */
+    ) {
+        int rc;
+
+        down(&memMap->lock);
+
+        DMA_MAP_PRINT("memMap: %p\n", memMap);
+
+        if (memMap->inUse) {
+                printk(KERN_ERR "%s: memory map %p is already being used\n",
+                       __func__, memMap);
+                rc = -EBUSY;
+                goto out;
+        }
+
+        memMap->inUse = 1;
+        memMap->dir = dir;
+        memMap->numRegionsUsed = 0;
+
+        rc = 0;
+
+out:
+
+        DMA_MAP_PRINT("returning %d", rc);
+
+        up(&memMap->lock);
+
+        return rc;
+}
+
+EXPORT_SYMBOL(dma_map_start);
+
+/****************************************************************************/
+/**
+*   Adds a segment of memory to a memory map. Each segment is both
+*   physically and virtually contiguous.
+*
+*   @return     0 on success, error code otherwise.
+*/
+/****************************************************************************/
+
+static int dma_map_add_segment(DMA_MemMap_t *memMap,    /* Stores state information about the map */
+                               DMA_Region_t *region,    /* Region that the segment belongs to */
+                               void *virtAddr,  /* Virtual address of the segment being added */
+                               dma_addr_t physAddr,     /* Physical address of the segment being added */
+                               size_t numBytes  /* Number of bytes of the segment being added */
+    ) {
+        DMA_Segment_t *segment;
+
+        DMA_MAP_PRINT("memMap:%p va:%p pa:0x%x #:%d\n", memMap, virtAddr,
+                      physAddr, numBytes);
+
+        /* Sanity check */
+
+        if (((unsigned long)virtAddr < (unsigned long)region->virtAddr)
+            || (((unsigned long)virtAddr + numBytes)) >
+            ((unsigned long)region->virtAddr + region->numBytes)) {
+                printk(KERN_ERR
+                       "%s: virtAddr %p is outside region @ %p len: %d\n",
+                       __func__, virtAddr, region->virtAddr, region->numBytes);
+                return -EINVAL;
+        }
+
+        if (region->numSegmentsUsed > 0) {
+                /* Check to see if this segment is physically contiguous with the previous one */
+
+                segment = &region->segment[region->numSegmentsUsed - 1];
+
+                if ((segment->physAddr + segment->numBytes) == physAddr) {
+                        /* It is - just add on to the end */
+
+                        DMA_MAP_PRINT("appending %d bytes to last segment\n",
+                                      numBytes);
+
+                        segment->numBytes += numBytes;
+
+                        return 0;
+                }
+        }
+
+        /* Reallocate to hold more segments, if required. */
+
+        if (region->numSegmentsUsed >= region->numSegmentsAllocated) {
+                DMA_Segment_t *newSegment;
+                size_t oldSize =
+                    region->numSegmentsAllocated * sizeof(*newSegment);
+                int newAlloc = region->numSegmentsAllocated + 4;
+                size_t newSize = newAlloc * sizeof(*newSegment);
+
+                newSegment = kmalloc(newSize, GFP_KERNEL);
+                if (newSegment == NULL) {
+                        return -ENOMEM;
+                }
+                memcpy(newSegment, region->segment, oldSize);
+                memset(&((uint8_t *) newSegment)[oldSize], 0,
+                       newSize - oldSize);
+                kfree(region->segment);
+
+                region->numSegmentsAllocated = newAlloc;
+                region->segment = newSegment;
+        }
+
+        segment = &region->segment[region->numSegmentsUsed];
+        region->numSegmentsUsed++;
+
+        segment->virtAddr = virtAddr;
+        segment->physAddr = physAddr;
+        segment->numBytes = numBytes;
+
+        DMA_MAP_PRINT("returning success\n");
+
+        return 0;
+}
+
+/****************************************************************************/
+/**
+*   Adds a region of memory to a memory map. Each region is virtually
+*   contiguous, but not necessarily physically contiguous.
+*
+*   @return     0 on success, error code otherwise.
+*/
+/****************************************************************************/
+
+int dma_map_add_region(DMA_MemMap_t *memMap,    /* Stores state information about the map */
+                       void *mem,       /* Virtual address that we want to get a map of */
+                       size_t numBytes  /* Number of bytes being mapped */
+    ) {
+        unsigned long addr = (unsigned long)mem;
+        unsigned int offset;
+        int rc = 0;
+        DMA_Region_t *region;
+        dma_addr_t physAddr;
+
+        down(&memMap->lock);
+
+        DMA_MAP_PRINT("memMap:%p va:%p #:%d\n", memMap, mem, numBytes);
+
+        if (!memMap->inUse) {
+                printk(KERN_ERR "%s: Make sure you call dma_map_start first\n",
+                       __func__);
+                rc = -EINVAL;
+                goto out;
+        }
+
+        /* Reallocate to hold more regions. */
+
+        if (memMap->numRegionsUsed >= memMap->numRegionsAllocated) {
+                DMA_Region_t *newRegion;
+                size_t oldSize =
+                    memMap->numRegionsAllocated * sizeof(*newRegion);
+                int newAlloc = memMap->numRegionsAllocated + 4;
+                size_t newSize = newAlloc * sizeof(*newRegion);
+
+                newRegion = kmalloc(newSize, GFP_KERNEL);
+                if (newRegion == NULL) {
+                        rc = -ENOMEM;
+                        goto out;
+                }
+                memcpy(newRegion, memMap->region, oldSize);
+                memset(&((uint8_t *) newRegion)[oldSize], 0, newSize - oldSize);
+
+                kfree(memMap->region);
+
+                memMap->numRegionsAllocated = newAlloc;
+                memMap->region = newRegion;
+        }
+
+        region = &memMap->region[memMap->numRegionsUsed];
+        memMap->numRegionsUsed++;
+
+        offset = addr & ~PAGE_MASK;
+
+        region->memType = dma_mem_type(mem);
+        region->virtAddr = mem;
+        region->numBytes = numBytes;
+        region->numSegmentsUsed = 0;
+        region->numLockedPages = 0;
+        region->lockedPages = NULL;
+
+        switch (region->memType) {
+        case DMA_MEM_TYPE_VMALLOC:
+                {
+                        atomic_inc(&gDmaStatMemTypeVmalloc);
+
+                        /* printk(KERN_ERR "%s: vmalloc'd pages are not supported\n", __func__); */
+
+                        /* vmalloc'd pages are not physically contiguous */
+
+                        rc = -EINVAL;
+                        break;
+                }
+
+        case DMA_MEM_TYPE_KMALLOC:
+                {
+                        atomic_inc(&gDmaStatMemTypeKmalloc);
+
+                        /* kmalloc'd pages are physically contiguous, so they'll have exactly */
+                        /* one segment */
+
+#if ALLOW_MAP_OF_KMALLOC_MEMORY
+                        physAddr =
+                            dma_map_single(NULL, mem, numBytes, memMap->dir);
+                        rc = dma_map_add_segment(memMap, region, mem, physAddr,
+                                                 numBytes);
+#else
+                        rc = -EINVAL;
+#endif
+                        break;
+                }
+
+        case DMA_MEM_TYPE_DMA:
+                {
+                        /* dma_alloc_xxx pages are physically contiguous */
+
+                        atomic_inc(&gDmaStatMemTypeCoherent);
+
+                        physAddr = (vmalloc_to_pfn(mem) << PAGE_SHIFT) + offset;
+
+                        dma_sync_single_for_cpu(NULL, physAddr, numBytes,
+                                                memMap->dir);
+                        rc = dma_map_add_segment(memMap, region, mem, physAddr,
+                                                 numBytes);
+                        break;
+                }
+
+        case DMA_MEM_TYPE_USER:
+                {
+                        size_t firstPageOffset;
+                        size_t firstPageSize;
+                        struct page **pages;
+                        struct task_struct *userTask;
+
+                        atomic_inc(&gDmaStatMemTypeUser);
+
+#if 1
+                        /* If the pages are user pages, then the dma_mem_map_set_user_task function */
+                        /* must have been previously called. */
+
+                        if (memMap->userTask == NULL) {
+                                printk(KERN_ERR
+                                       "%s: must call dma_mem_map_set_user_task when using user-mode memory\n",
+                                       __func__);
+                                return -EINVAL;
+                        }
+
+                        /* User pages need to be locked. */
+
+                        firstPageOffset =
+                            (unsigned long)region->virtAddr & (PAGE_SIZE - 1);
+                        firstPageSize = PAGE_SIZE - firstPageOffset;
+
+                        region->numLockedPages = (firstPageOffset
+                                                  + region->numBytes +
+                                                  PAGE_SIZE - 1) / PAGE_SIZE;
+                        pages =
+                            kmalloc(region->numLockedPages *
+                                    sizeof(struct page *), GFP_KERNEL);
+
+                        if (pages == NULL) {
+                                region->numLockedPages = 0;
+                                return -ENOMEM;
+                        }
+
+                        userTask = memMap->userTask;
+
+                        down_read(&userTask->mm->mmap_sem);
+                        rc = get_user_pages(userTask,   /* task */
+                                            userTask->mm,       /* mm */
+                                            (unsigned long)region->virtAddr,    /* start */
+                                            region->numLockedPages,     /* len */
+                                            memMap->dir == DMA_FROM_DEVICE,     /* write */
+                                            0,  /* force */
+                                            pages,      /* pages (array of pointers to page) */
+                                            NULL);      /* vmas */
+                        up_read(&userTask->mm->mmap_sem);
+
+                        if (rc != region->numLockedPages) {
+                                kfree(pages);
+                                region->numLockedPages = 0;
+
+                                if (rc >= 0) {
+                                        rc = -EINVAL;
+                                }
+                        } else {
+                                uint8_t *virtAddr = region->virtAddr;
+                                size_t bytesRemaining;
+                                int pageIdx;
+
+                                rc = 0; /* Since get_user_pages returns +ve number */
+
+                                region->lockedPages = pages;
+
+                                /* We've locked the user pages. Now we need to walk them and figure */
+                                /* out the physical addresses. */
+
+                                /* The first page may be partial */
+
+                                dma_map_add_segment(memMap,
+                                                    region,
+                                                    virtAddr,
+                                                    PFN_PHYS(page_to_pfn
+                                                             (pages[0])) +
+                                                    firstPageOffset,
+                                                    firstPageSize);
+
+                                virtAddr += firstPageSize;
+                                bytesRemaining =
+                                    region->numBytes - firstPageSize;
+
+                                for (pageIdx = 1;
+                                     pageIdx < region->numLockedPages;
+                                     pageIdx++) {
+                                        size_t bytesThisPage =
+                                            (bytesRemaining >
+                                             PAGE_SIZE ? PAGE_SIZE :
+                                             bytesRemaining);
+
+                                        DMA_MAP_PRINT
+                                            ("pageIdx:%d pages[pageIdx]=%p pfn=%u phys=%u\n",
+                                             pageIdx, pages[pageIdx],
+                                             page_to_pfn(pages[pageIdx]),
+                                             PFN_PHYS(page_to_pfn
+                                                      (pages[pageIdx])));
+
+                                        dma_map_add_segment(memMap,
+                                                            region,
+                                                            virtAddr,
+                                                            PFN_PHYS(page_to_pfn
+                                                                     (pages
+                                                                      [pageIdx])),
+                                                            bytesThisPage);
+
+                                        virtAddr += bytesThisPage;
+                                        bytesRemaining -= bytesThisPage;
+                                }
+                        }
+#else
+                        printk(KERN_ERR
+                               "%s: User mode pages are not yet supported\n",
+                               __func__);
+
+                        /* user pages are not physically contiguous */
+
+                        rc = -EINVAL;
+#endif
+                        break;
+                }
+
+        default:
+                {
+                        printk(KERN_ERR "%s: Unsupported memory type: %d\n",
+                               __func__, region->memType);
+
+                        rc = -EINVAL;
+                        break;
+                }
+        }
+
+        if (rc != 0) {
+                memMap->numRegionsUsed--;
+        }
+
+out:
+
+        DMA_MAP_PRINT("returning %d\n", rc);
+
+        up(&memMap->lock);
+
+        return rc;
+}
+
+EXPORT_SYMBOL(dma_map_add_segment);
+
+/****************************************************************************/
+/**
+*   Maps in a memory region such that it can be used for performing a DMA.
+*
+*   @return     0 on success, error code otherwise.
+*/
+/****************************************************************************/
+
+int dma_map_mem(DMA_MemMap_t *memMap,   /* Stores state information about the map */
+                void *mem,      /* Virtual address that we want to get a map of */
+                size_t numBytes,        /* Number of bytes being mapped */
+                enum dma_data_direction dir     /* Direction that the mapping will be going */
+    ) {
+        int rc;
+
+        rc = dma_map_start(memMap, dir);
+        if (rc == 0) {
+                rc = dma_map_add_region(memMap, mem, numBytes);
+                if (rc < 0) {
+                        /* Since the add fails, this function will fail, and the caller won't */
+                        /* call unmap, so we need to do it here. */
+
+                        dma_unmap(memMap, 0);
+                }
+        }
+
+        return rc;
+}
+
+EXPORT_SYMBOL(dma_map_mem);
+
+/****************************************************************************/
+/**
+*   Setup a descriptor ring for a given memory map.
+*
+*   It is assumed that the descriptor ring has already been initialized, and
+*   this routine will only reallocate a new descriptor ring if the existing
+*   one is too small.
+*
+*   @return     0 on success, error code otherwise.
+*/
+/****************************************************************************/
+
+int dma_map_create_descriptor_ring(DMA_Device_t dev,    /* DMA device (where the ring is stored) */
+                                   DMA_MemMap_t *memMap,        /* Memory map that will be used */
+                                   dma_addr_t devPhysAddr       /* Physical address of device */
+    ) {
+        int rc;
+        int numDescriptors;
+        DMA_DeviceAttribute_t *devAttr;
+        DMA_Region_t *region;
+        DMA_Segment_t *segment;
+        dma_addr_t srcPhysAddr;
+        dma_addr_t dstPhysAddr;
+        int regionIdx;
+        int segmentIdx;
+
+        devAttr = &DMA_gDeviceAttribute[dev];
+
+        down(&memMap->lock);
+
+        /* Figure out how many descriptors we need */
+
+        numDescriptors = 0;
+        for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
+                region = &memMap->region[regionIdx];
+
+                for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
+                     segmentIdx++) {
+                        segment = &region->segment[segmentIdx];
+
+                        if (memMap->dir == DMA_TO_DEVICE) {
+                                srcPhysAddr = segment->physAddr;
+                                dstPhysAddr = devPhysAddr;
+                        } else {
+                                srcPhysAddr = devPhysAddr;
+                                dstPhysAddr = segment->physAddr;
+                        }
+
+                        rc =
+                             dma_calculate_descriptor_count(dev, srcPhysAddr,
+                                                            dstPhysAddr,
+                                                            segment->
+                                                            numBytes);
+                        if (rc < 0) {
+                                printk(KERN_ERR
+                                       "%s: dma_calculate_descriptor_count failed: %d\n",
+                                       __func__, rc);
+                                goto out;
+                        }
+                        numDescriptors += rc;
+                }
+        }
+
+        /* Adjust the size of the ring, if it isn't big enough */
+
+        if (numDescriptors > devAttr->ring.descriptorsAllocated) {
+                dma_free_descriptor_ring(&devAttr->ring);
+                rc =
+                     dma_alloc_descriptor_ring(&devAttr->ring,
+                                               numDescriptors);
+                if (rc < 0) {
+                        printk(KERN_ERR
+                               "%s: dma_alloc_descriptor_ring failed: %d\n",
+                               __func__, rc);
+                        goto out;
+                }
+        } else {
+                rc =
+                     dma_init_descriptor_ring(&devAttr->ring,
+                                              numDescriptors);
+                if (rc < 0) {
+                        printk(KERN_ERR
+                               "%s: dma_init_descriptor_ring failed: %d\n",
+                               __func__, rc);
+                        goto out;
+                }
+        }
+
+        /* Populate the descriptors */
+
+        for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
+                region = &memMap->region[regionIdx];
+
+                for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
+                     segmentIdx++) {
+                        segment = &region->segment[segmentIdx];
+
+                        if (memMap->dir == DMA_TO_DEVICE) {
+                                srcPhysAddr = segment->physAddr;
+                                dstPhysAddr = devPhysAddr;
+                        } else {
+                                srcPhysAddr = devPhysAddr;
+                                dstPhysAddr = segment->physAddr;
+                        }
+
+                        rc =
+                             dma_add_descriptors(&devAttr->ring, dev,
+                                                 srcPhysAddr, dstPhysAddr,
+                                                 segment->numBytes);
+                        if (rc < 0) {
+                                printk(KERN_ERR
+                                       "%s: dma_add_descriptors failed: %d\n",
+                                       __func__, rc);
+                                goto out;
+                        }
+                }
+        }
+
+        rc = 0;
+
+out:
+
+        up(&memMap->lock);
+        return rc;
+}
+
+EXPORT_SYMBOL(dma_map_create_descriptor_ring);
+
+/****************************************************************************/
+/**
+*   Maps in a memory region such that it can be used for performing a DMA.
+*
+*   @return
+*/
+/****************************************************************************/
+
+int dma_unmap(DMA_MemMap_t *memMap,     /* Stores state information about the map */
+              int dirtied       /* non-zero if any of the pages were modified */
+    ) {
+        int regionIdx;
+        int segmentIdx;
+        DMA_Region_t *region;
+        DMA_Segment_t *segment;
+
+        for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
+                region = &memMap->region[regionIdx];
+
+                for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
+                     segmentIdx++) {
+                        segment = &region->segment[segmentIdx];
+
+                        switch (region->memType) {
+                        case DMA_MEM_TYPE_VMALLOC:
+                                {
+                                        printk(KERN_ERR
+                                               "%s: vmalloc'd pages are not yet supported\n",
+                                               __func__);
+                                        return -EINVAL;
+                                }
+
+                        case DMA_MEM_TYPE_KMALLOC:
+                                {
+#if ALLOW_MAP_OF_KMALLOC_MEMORY
+                                        dma_unmap_single(NULL,
+                                                         segment->physAddr,
+                                                         segment->numBytes,
+                                                         memMap->dir);
+#endif
+                                        break;
+                                }
+
+                        case DMA_MEM_TYPE_DMA:
+                                {
+                                        dma_sync_single_for_cpu(NULL,
+                                                                segment->
+                                                                physAddr,
+                                                                segment->
+                                                                numBytes,
+                                                                memMap->dir);
+                                        break;
+                                }
+
+                        case DMA_MEM_TYPE_USER:
+                                {
+                                        /* Nothing to do here. */
+
+                                        break;
+                                }
+
+                        default:
+                                {
+                                        printk(KERN_ERR
+                                               "%s: Unsupported memory type: %d\n",
+                                               __func__, region->memType);
+                                        return -EINVAL;
+                                }
+                        }
+
+                        segment->virtAddr = NULL;
+                        segment->physAddr = 0;
+                        segment->numBytes = 0;
+                }
+
+                if (region->numLockedPages > 0) {
+                        int pageIdx;
+
+                        /* Some user pages were locked. We need to go and unlock them now. */
+
+                        for (pageIdx = 0; pageIdx < region->numLockedPages;
+                             pageIdx++) {
+                                struct page *page =
+                                    region->lockedPages[pageIdx];
+
+                                if (memMap->dir == DMA_FROM_DEVICE) {
+                                        SetPageDirty(page);
+                                }
+                                page_cache_release(page);
+                        }
+                        kfree(region->lockedPages);
+                        region->numLockedPages = 0;
+                        region->lockedPages = NULL;
+                }
+
+                region->memType = DMA_MEM_TYPE_NONE;
+                region->virtAddr = NULL;
+                region->numBytes = 0;
+                region->numSegmentsUsed = 0;
+        }
+        memMap->userTask = NULL;
+        memMap->numRegionsUsed = 0;
+        memMap->inUse = 0;
+
+        up(&memMap->lock);
+
+        return 0;
+}
+
+EXPORT_SYMBOL(dma_unmap);
diff --git a/arch/arm/mach-bcmring/dma_device.c b/arch/arm/mach-bcmring/dma_device.c
new file mode 100644
index 000000000000..ca0ad736870b
--- /dev/null
+++ b/arch/arm/mach-bcmring/dma_device.c
@@ -0,0 +1,593 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*   @file   dma_device.c
+*
+*   @brief  private array of DMA_DeviceAttribute_t
+*/
+/****************************************************************************/
+
+DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = {
+        [DMA_DEVICE_MEM_TO_MEM] =       /* MEM 2 MEM */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "mem-to-mem",
+         .config = {
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+
+                    },
+         },
+        [DMA_DEVICE_VPM_MEM_TO_MEM] =   /* VPM */
+        {
+         .flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR,
+         .name = "vpm",
+         .dedicatedController = 0,
+         .dedicatedChannel = 0,
+         /* reserve DMA0:0 for VPM */
+         },
+        [DMA_DEVICE_NAND_MEM_TO_MEM] =  /* NAND */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "nand",
+         .config = {
+                    .srcPeripheralPort = 0,
+                    .dstPeripheralPort = 0,
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_6,
+                    },
+         },
+        [DMA_DEVICE_PIF_MEM_TO_DEV] =   /* PIF TX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
+         | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
+         | DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC,
+         .name = "pif_tx",
+         .dmacPort = {14, 5},
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    /* dstPeripheralPort          = 5 or 14 */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
+                    .maxDataPerBlock = 16256,
+                    },
+         },
+        [DMA_DEVICE_PIF_DEV_TO_MEM] =   /* PIF RX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
+         | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
+         /* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */
+         | DMA_DEVICE_FLAG_PORT_PER_DMAC,
+         .name = "pif_rx",
+         .dmacPort = {14, 5},
+         .config = {
+                    /* srcPeripheralPort          = 5 or 14 */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
+                    .maxDataPerBlock = 16256,
+                    },
+         },
+        [DMA_DEVICE_I2S0_DEV_TO_MEM] =  /* I2S RX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "i2s0_rx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: I2S0 */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
+                    },
+         },
+        [DMA_DEVICE_I2S0_MEM_TO_DEV] =  /* I2S TX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "i2s0_tx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 1,     /* DST: I2S0 */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    },
+         },
+        [DMA_DEVICE_I2S1_DEV_TO_MEM] =  /* I2S1 RX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "i2s1_rx",
+         .config = {
+                    .srcPeripheralPort = 2,     /* SRC: I2S1 */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
+                    },
+         },
+        [DMA_DEVICE_I2S1_MEM_TO_DEV] =  /* I2S1 TX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "i2s1_tx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 3,     /* DST: I2S1 */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    },
+         },
+        [DMA_DEVICE_ESW_MEM_TO_DEV] =   /* ESW TX */
+        {
+         .name = "esw_tx",
+         .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
+         .dedicatedController = 1,
+         .dedicatedChannel = 3,
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 1,     /* DST: ESW (MTP) */
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    /* DMAx_AHB_SSTATARy */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    /* DMAx_AHB_DSTATARy */
+                    .dstStatusRegisterAddress = 0x30490010,
+                    /* DMAx_AHB_CFGy */
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    /* DMAx_AHB_CTLy */
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    },
+         },
+        [DMA_DEVICE_ESW_DEV_TO_MEM] =   /* ESW RX */
+        {
+         .name = "esw_rx",
+         .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
+         .dedicatedController = 1,
+         .dedicatedChannel = 2,
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: ESW (PTM) */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    /* DMAx_AHB_SSTATARy */
+                    .srcStatusRegisterAddress = 0x30480010,
+                    /* DMAx_AHB_DSTATARy */
+                    .dstStatusRegisterAddress = 0x00000000,
+                    /* DMAx_AHB_CFGy */
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    /* DMAx_AHB_CTLy */
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    },
+         },
+        [DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] =   /* APM Codec A Ingress */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "apm_a_rx",
+         .config = {
+                    .srcPeripheralPort = 2,     /* SRC: Codec A Ingress FIFO */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
+                    },
+         },
+        [DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] =   /* APM Codec A Egress */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "apm_a_tx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 3,     /* DST: Codec A Egress FIFO */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    },
+         },
+        [DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] =   /* APM Codec B Ingress */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "apm_b_rx",
+         .config = {
+                    .srcPeripheralPort = 4,     /* SRC: Codec B Ingress FIFO */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
+                    },
+         },
+        [DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] =   /* APM Codec B Egress */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "apm_b_tx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 5,     /* DST: Codec B Egress FIFO */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    },
+         },
+        [DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] =   /* APM Codec C Ingress */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "apm_c_rx",
+         .config = {
+                    .srcPeripheralPort = 4,     /* SRC: Codec C Ingress FIFO */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
+                    },
+         },
+        [DMA_DEVICE_APM_PCM0_DEV_TO_MEM] =      /* PCM0 RX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "pcm0_rx",
+         .config = {
+                    .srcPeripheralPort = 12,    /* SRC: PCM0 */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
+                    },
+         },
+        [DMA_DEVICE_APM_PCM0_MEM_TO_DEV] =      /* PCM0 TX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "pcm0_tx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 13,    /* DST: PCM0 */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    },
+         },
+        [DMA_DEVICE_APM_PCM1_DEV_TO_MEM] =      /* PCM1 RX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "pcm1_rx",
+         .config = {
+                    .srcPeripheralPort = 14,    /* SRC: PCM1 */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
+                    },
+         },
+        [DMA_DEVICE_APM_PCM1_MEM_TO_DEV] =      /* PCM1 TX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "pcm1_tx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 15,    /* DST: PCM1 */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    },
+         },
+        [DMA_DEVICE_SPUM_DEV_TO_MEM] =  /* SPUM RX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "spum_rx",
+         .config = {
+                    .srcPeripheralPort = 6,     /* SRC: Codec A Ingress FIFO */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    /* Busrt size **MUST** be 16 for SPUM to work */
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    /* on the RX side, SPU needs to be the flow controller */
+                    .flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL,
+                    },
+         },
+        [DMA_DEVICE_SPUM_MEM_TO_DEV] =  /* SPUM TX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "spum_tx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 7,     /* DST: SPUM */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    /* Busrt size **MUST** be 16 for SPUM to work */
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    },
+         },
+        [DMA_DEVICE_MEM_TO_VRAM] =      /* MEM 2 VRAM */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "mem-to-vram",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
+                    },
+         },
+        [DMA_DEVICE_VRAM_TO_MEM] =      /* VRAM 2 MEM */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "vram-to-mem",
+         .config = {
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
+                    },
+         },
+};
+EXPORT_SYMBOL(DMA_gDeviceAttribute);    /* primarily for dma-test.c */
diff --git a/arch/arm/mach-bcmring/include/cfg_global.h b/arch/arm/mach-bcmring/include/cfg_global.h
new file mode 100644
index 000000000000..f01da877148e
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/cfg_global.h
@@ -0,0 +1,13 @@
+#ifndef _CFG_GLOBAL_H_
+#define _CFG_GLOBAL_H_
+
+#include <cfg_global_defines.h>
+
+#define CFG_GLOBAL_CHIP                         BCM11107
+#define CFG_GLOBAL_CHIP_FAMILY                  CFG_GLOBAL_CHIP_FAMILY_BCMRING
+#define CFG_GLOBAL_CHIP_REV                     0xB0
+#define CFG_GLOBAL_RAM_SIZE                     0x10000000
+#define CFG_GLOBAL_RAM_BASE                     0x00000000
+#define CFG_GLOBAL_RAM_RESERVED_SIZE            0x000000
+
+#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h b/arch/arm/mach-bcmring/include/cfg_global_defines.h
new file mode 100644
index 000000000000..b5beb0b30734
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/cfg_global_defines.h
@@ -0,0 +1,40 @@
+/*****************************************************************************
+* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+#ifndef CFG_GLOBAL_DEFINES_H
+#define CFG_GLOBAL_DEFINES_H
+
+/* CHIP */
+#define BCM1103 1
+
+#define BCM1191 4
+#define BCM2153 5
+#define BCM2820 6
+
+#define BCM2826 8
+#define FPGA11107 9
+#define BCM11107   10
+#define BCM11109   11
+#define BCM11170   12
+#define BCM11110   13
+#define BCM11211   14
+
+/* CFG_GLOBAL_CHIP_FAMILY types */
+#define CFG_GLOBAL_CHIP_FAMILY_NONE        0
+#define CFG_GLOBAL_CHIP_FAMILY_BCM116X     2
+#define CFG_GLOBAL_CHIP_FAMILY_BCMRING     4
+#define CFG_GLOBAL_CHIP_FAMILY_BCM1103     8
+
+#define IMAGE_HEADER_SIZE_CHECKSUM    4
+#endif
diff --git a/arch/arm/mach-bcmring/include/csp/cache.h b/arch/arm/mach-bcmring/include/csp/cache.h
new file mode 100644
index 000000000000..caa20e59db99
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/cache.h
@@ -0,0 +1,35 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+#ifndef CSP_CACHE_H
+#define CSP_CACHE_H
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#include <csp/stdint.h>
+
+/* ---- Public Constants and Types --------------------------------------- */
+
+#if defined(__KERNEL__) && !defined(STANDALONE)
+#include <asm/cacheflush.h>
+
+#define CSP_CACHE_FLUSH_ALL      flush_cache_all()
+
+#else
+
+#define CSP_CACHE_FLUSH_ALL
+
+#endif
+
+#endif /* CSP_CACHE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/delay.h b/arch/arm/mach-bcmring/include/csp/delay.h
new file mode 100644
index 000000000000..8b3d80367293
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/delay.h
@@ -0,0 +1,36 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+
+#ifndef CSP_DELAY_H
+#define CSP_DELAY_H
+
+/* ---- Include Files ---------------------------------------------------- */
+
+/* Some CSP routines require use of the following delay routines. Use the OS */
+/* version if available, otherwise use a CSP specific definition. */
+/* void udelay(unsigned long usecs); */
+/* void mdelay(unsigned long msecs); */
+
+#if defined(__KERNEL__) && !defined(STANDALONE)
+   #include <linux/delay.h>
+#else
+   #include <mach/csp/delay.h>
+#endif
+
+/* ---- Public Constants and Types --------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+
+#endif /*  CSP_DELAY_H */
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h
new file mode 100644
index 000000000000..5d510130a25f
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/dmacHw.h
@@ -0,0 +1,596 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    dmacHw.h
+*
+*  @brief   API definitions for low level DMA controller driver
+*
+*/
+/****************************************************************************/
+#ifndef _DMACHW_H
+#define _DMACHW_H
+
+#include <stddef.h>
+
+#include <csp/stdint.h>
+#include <mach/csp/dmacHw_reg.h>
+
+/* Define DMA Channel ID using DMA controller number (m) and channel number (c).
+
+   System specific channel ID should be defined as follows
+
+   For example:
+
+   #include <dmacHw.h>
+   ...
+   #define systemHw_LCD_CHANNEL_ID                dmacHw_MAKE_CHANNEL_ID(0,5)
+   #define systemHw_SWITCH_RX_CHANNEL_ID          dmacHw_MAKE_CHANNEL_ID(0,0)
+   #define systemHw_SWITCH_TX_CHANNEL_ID          dmacHw_MAKE_CHANNEL_ID(0,1)
+   #define systemHw_APM_RX_CHANNEL_ID             dmacHw_MAKE_CHANNEL_ID(0,3)
+   #define systemHw_APM_TX_CHANNEL_ID             dmacHw_MAKE_CHANNEL_ID(0,4)
+   ...
+   #define systemHw_SHARED1_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(1,4)
+   #define systemHw_SHARED2_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(1,5)
+   #define systemHw_SHARED3_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(0,6)
+   ...
+*/
+#define dmacHw_MAKE_CHANNEL_ID(m, c)         (m << 8 | c)
+
+typedef enum {
+        dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0,    /* Channel priority 0. Lowest priority DMA channel */
+        dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1,    /* Channel priority 1 */
+        dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2,    /* Channel priority 2 */
+        dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3,    /* Channel priority 3 */
+        dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4,    /* Channel priority 4 */
+        dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5,    /* Channel priority 5 */
+        dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6,    /* Channel priority 6 */
+        dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7     /* Channel priority 7. Highest priority DMA channel */
+} dmacHw_CHANNEL_PRIORITY_e;
+
+/* Source destination master interface */
+typedef enum {
+        dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1,   /* Source DMA master interface 1 */
+        dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2,   /* Source DMA master interface 2 */
+        dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1,   /* Destination DMA master interface 1 */
+        dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2    /* Destination DMA master interface 2 */
+} dmacHw_MASTER_INTERFACE_e;
+
+typedef enum {
+        dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, /* Source 8 bit  (1 byte) per transaction */
+        dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16,       /* Source 16 bit (2 byte) per transaction */
+        dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32,       /* Source 32 bit (4 byte) per transaction */
+        dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64,       /* Source 64 bit (8 byte) per transaction */
+        dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, /* Destination 8 bit  (1 byte) per transaction */
+        dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16,       /* Destination 16 bit (2 byte) per transaction */
+        dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32,       /* Destination 32 bit (4 byte) per transaction */
+        dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64        /* Destination 64 bit (8 byte) per transaction */
+} dmacHw_TRANSACTION_WIDTH_e;
+
+typedef enum {
+        dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0,  /* Source No burst */
+        dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4,  /* Source 4  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
+        dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8,  /* Source 8  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
+        dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16,        /* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
+        dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0,  /* Destination No burst */
+        dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4,  /* Destination 4  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
+        dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8,  /* Destination 8  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
+        dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16 /* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
+} dmacHw_BURST_WIDTH_e;
+
+typedef enum {
+        dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC,  /* Memory to memory transfer */
+        dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC,   /* Peripheral to memory transfer */
+        dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC,   /* Memory to peripheral transfer */
+        dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC     /* Peripheral to peripheral transfer */
+} dmacHw_TRANSFER_TYPE_e;
+
+typedef enum {
+        dmacHw_TRANSFER_MODE_PERREQUEST,        /* Block transfer per DMA request */
+        dmacHw_TRANSFER_MODE_CONTINUOUS,        /* Continuous transfer of streaming data */
+        dmacHw_TRANSFER_MODE_PERIODIC   /* Periodic transfer of streaming data */
+} dmacHw_TRANSFER_MODE_e;
+
+typedef enum {
+        dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC,   /* Increment source address after every transaction */
+        dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC,   /* Decrement source address after every transaction */
+        dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC,   /* Increment destination address after every transaction */
+        dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC,   /* Decrement destination address after every transaction */
+        dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC,     /* No change in source address after every transaction */
+        dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC      /* No change in destination address after every transaction */
+} dmacHw_ADDRESS_UPDATE_MODE_e;
+
+typedef enum {
+        dmacHw_FLOW_CONTROL_DMA,        /* DMA working as flow controller (default) */
+        dmacHw_FLOW_CONTROL_PERIPHERAL  /* Peripheral working as flow controller */
+} dmacHw_FLOW_CONTROL_e;
+
+typedef enum {
+        dmacHw_TRANSFER_STATUS_BUSY,    /* DMA Transfer ongoing */
+        dmacHw_TRANSFER_STATUS_DONE,    /* DMA Transfer completed */
+        dmacHw_TRANSFER_STATUS_ERROR    /* DMA Transfer error */
+} dmacHw_TRANSFER_STATUS_e;
+
+typedef enum {
+        dmacHw_INTERRUPT_DISABLE,       /* Interrupt disable  */
+        dmacHw_INTERRUPT_ENABLE /* Interrupt enable */
+} dmacHw_INTERRUPT_e;
+
+typedef enum {
+        dmacHw_INTERRUPT_STATUS_NONE = 0x0,     /* No DMA interrupt */
+        dmacHw_INTERRUPT_STATUS_TRANS = 0x1,    /* End of DMA transfer interrupt */
+        dmacHw_INTERRUPT_STATUS_BLOCK = 0x2,    /* End of block transfer interrupt */
+        dmacHw_INTERRUPT_STATUS_ERROR = 0x4     /* Error interrupt */
+} dmacHw_INTERRUPT_STATUS_e;
+
+typedef enum {
+        dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM,   /* Number of DMA channel */
+        dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE,        /* Maximum channel burst size */
+        dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM,       /* Number of DMA master interface */
+        dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH,     /* Channel Data bus width */
+        dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE      /* Channel FIFO size */
+} dmacHw_CONTROLLER_ATTRIB_e;
+
+typedef unsigned long dmacHw_HANDLE_t;  /* DMA channel handle */
+typedef uint32_t dmacHw_ID_t;   /* DMA channel Id.  Must be created using
+                                   "dmacHw_MAKE_CHANNEL_ID" macro
+                                 */
+/* DMA channel configuration parameters */
+typedef struct {
+        uint32_t srcPeripheralPort;     /* Source peripheral port */
+        uint32_t dstPeripheralPort;     /* Destination peripheral port */
+        uint32_t srcStatusRegisterAddress;      /* Source status register address */
+        uint32_t dstStatusRegisterAddress;      /* Destination status register address of type  */
+
+        uint32_t srcGatherWidth;        /* Number of bytes gathered before successive gather opearation */
+        uint32_t srcGatherJump; /* Number of bytes jumpped before successive gather opearation */
+        uint32_t dstScatterWidth;       /* Number of bytes sacattered before successive scatter opearation */
+        uint32_t dstScatterJump;        /* Number of bytes jumpped  before successive scatter opearation */
+        uint32_t maxDataPerBlock;       /* Maximum number of bytes to be transferred per block/descrptor.
+                                           0 = Maximum possible.
+                                         */
+
+        dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate; /* Source address update mode */
+        dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate; /* Destination address update mode */
+        dmacHw_TRANSFER_TYPE_e transferType;    /* DMA transfer type  */
+        dmacHw_TRANSFER_MODE_e transferMode;    /* DMA transfer mode */
+        dmacHw_MASTER_INTERFACE_e srcMasterInterface;   /* DMA source interface  */
+        dmacHw_MASTER_INTERFACE_e dstMasterInterface;   /* DMA destination interface */
+        dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth;      /* Source transaction width   */
+        dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth;      /* Destination transaction width */
+        dmacHw_BURST_WIDTH_e srcMaxBurstWidth;  /* Source burst width */
+        dmacHw_BURST_WIDTH_e dstMaxBurstWidth;  /* Destination burst width */
+        dmacHw_INTERRUPT_e blockTransferInterrupt;      /* Block trsnafer interrupt */
+        dmacHw_INTERRUPT_e completeTransferInterrupt;   /* Complete DMA trsnafer interrupt */
+        dmacHw_INTERRUPT_e errorInterrupt;      /* Error interrupt */
+        dmacHw_CHANNEL_PRIORITY_e channelPriority;      /* Channel priority */
+        dmacHw_FLOW_CONTROL_e flowControler;    /* Data flow controller */
+} dmacHw_CONFIG_t;
+
+/****************************************************************************/
+/**
+*  @brief   Initializes DMA
+*
+*  This function initializes DMA CSP driver
+*
+*  @note
+*     Must be called before using any DMA channel
+*/
+/****************************************************************************/
+void dmacHw_initDma(void);
+
+/****************************************************************************/
+/**
+*  @brief   Exit function for  DMA
+*
+*  This function isolates DMA from the system
+*
+*/
+/****************************************************************************/
+void dmacHw_exitDma(void);
+
+/****************************************************************************/
+/**
+*  @brief   Gets a handle to a DMA channel
+*
+*  This function returns a handle, representing a control block of a particular DMA channel
+*
+*  @return  -1       - On Failure
+*            handle  - On Success, representing a channel control block
+*
+*  @note
+*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
+*/
+/****************************************************************************/
+dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId   /* [ IN ] DMA Channel Id */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Initializes a DMA channel for use
+*
+*  This function initializes and resets a DMA channel for use
+*
+*  @return  -1     - On Failure
+*            0     - On Success
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+int dmacHw_initChannel(dmacHw_HANDLE_t handle   /*  [ IN ] DMA Channel handle  */
+    );
+
+/****************************************************************************/
+/**
+*  @brief  Estimates number of descriptor needed to perform certain DMA transfer
+*
+*
+*  @return  On failure : -1
+*           On success : Number of descriptor count
+*
+*
+*/
+/****************************************************************************/
+int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,   /*   [ IN ] Configuration settings */
+                                    void *pSrcAddr,     /*   [ IN ] Source (Peripheral/Memory) address */
+                                    void *pDstAddr,     /*   [ IN ] Destination (Peripheral/Memory) address */
+                                    size_t dataLen      /*   [ IN ] Data length in bytes */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Initializes descriptor ring
+*
+*  This function will initializes the descriptor ring of a DMA channel
+*
+*
+*  @return   -1 - On failure
+*             0 - On success
+*  @note
+*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
+*     - Descriptor buffer MUST be 32 bit aligned and uncached as it
+*       is accessed by ARM and DMA
+*/
+/****************************************************************************/
+int dmacHw_initDescriptor(void *pDescriptorVirt,        /*  [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
+                          uint32_t descriptorPhyAddr,   /*  [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
+                          uint32_t len, /*  [ IN ] Size of the pBuf */
+                          uint32_t num  /*  [ IN ] Number of descriptor in the ring */
+    );
+
+/****************************************************************************/
+/**
+*  @brief  Finds amount of memory required to form a descriptor ring
+*
+*
+*  @return   Number of bytes required to form a descriptor ring
+*
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+uint32_t dmacHw_descriptorLen(uint32_t descCnt  /*  [ IN ] Number of descriptor in the ring */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Configure DMA channel
+*
+*  @return  0  : On success
+*           -1 : On failure
+*/
+/****************************************************************************/
+int dmacHw_configChannel(dmacHw_HANDLE_t handle,        /*  [ IN ] DMA Channel handle  */
+                         dmacHw_CONFIG_t *pConfig       /*   [ IN ] Configuration settings */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Set descriptors for known data length
+*
+*  When DMA has to work as a flow controller, this function prepares the
+*  descriptor chain to transfer data
+*
+*  from:
+*          - Memory to memory
+*          - Peripheral to memory
+*          - Memory to Peripheral
+*          - Peripheral to Peripheral
+*
+*  @return   -1 - On failure
+*             0 - On success
+*
+*/
+/****************************************************************************/
+int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,  /*  [ IN ] Configuration settings */
+                             void *pDescriptor, /*  [ IN ] Descriptor buffer  */
+                             void *pSrcAddr,    /*  [ IN ] Source (Peripheral/Memory) address */
+                             void *pDstAddr,    /*  [ IN ] Destination (Peripheral/Memory) address */
+                             size_t dataLen     /*  [ IN ] Length in bytes   */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Indicates whether DMA transfer is in progress or completed
+*
+*  @return   DMA transfer status
+*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
+*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
+*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
+*
+*/
+/****************************************************************************/
+dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle        /*   [ IN ] DMA Channel handle  */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Set descriptor carrying control information
+*
+*  This function will be used to send specific control information to the device
+*  using the DMA channel
+*
+*
+*  @return  -1 - On failure
+*            0 - On success
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,       /*  [ IN ] Configuration settings */
+                                void *pDescriptor,      /*  [ IN ] Descriptor buffer  */
+                                uint32_t ctlAddress,    /*  [ IN ] Address of the device control register  */
+                                uint32_t control        /*  [ IN ] Device control information */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Read data DMA transferred to memory
+*
+*  This function will read data that has been DMAed to memory while transfering from:
+*          - Memory to memory
+*          - Peripheral to memory
+*
+*  @return  0 - No more data is available to read
+*           1 - More data might be available to read
+*
+*/
+/****************************************************************************/
+int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle    */
+                               dmacHw_CONFIG_t *pConfig,        /*  [ IN ]  Configuration settings */
+                               void *pDescriptor,       /*  [ IN ] Descriptor buffer  */
+                               void **ppBbuf,   /*  [ OUT ] Data received */
+                               size_t *pLlen    /*  [ OUT ] Length of the data received */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Prepares descriptor ring, when source peripheral working as a flow controller
+*
+*  This function will form the descriptor ring by allocating buffers, when source peripheral
+*  has to work as a flow controller to transfer data from:
+*           - Peripheral to memory.
+*
+*  @return  -1 - On failure
+*            0 - On success
+*
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,    /*  [ IN ] DMA Channel handle   */
+                                     dmacHw_CONFIG_t *pConfig,  /*  [ IN ] Configuration settings */
+                                     void *pDescriptor, /*  [ IN ] Descriptor buffer  */
+                                     uint32_t srcAddr,  /*  [ IN ] Source peripheral address */
+                                     void *(*fpAlloc) (int len),        /*  [ IN ] Function pointer  that provides destination memory */
+                                     int len,   /*  [ IN ] Number of bytes "fpAlloc" will allocate for destination */
+                                     int num    /*  [ IN ] Number of descriptor to set */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Program channel register to initiate transfer
+*
+*  @return  void
+*
+*
+*  @note
+*     - Descriptor buffer MUST ALWAYS be flushed before calling this function
+*     - This function should also be called from ISR to program the channel with
+*       pending descriptors
+*/
+/****************************************************************************/
+void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,    /*   [ IN ] DMA Channel handle */
+                             dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
+                             void *pDescriptor  /*   [ IN ] Descriptor buffer  */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Resets descriptor control information
+*
+*  @return  void
+*/
+/****************************************************************************/
+void dmacHw_resetDescriptorControl(void *pDescriptor    /*   [ IN ] Descriptor buffer  */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Program channel register to stop transfer
+*
+*  Ensures the channel is not doing any transfer after calling this function
+*
+*  @return  void
+*
+*/
+/****************************************************************************/
+void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /*   [ IN ] DMA Channel handle */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Check the existance of pending descriptor
+*
+*  This function confirmes if there is any pending descriptor in the chain
+*  to program the channel
+*
+*  @return  1 : Channel need to be programmed with pending descriptor
+*           0 : No more pending descriptor to programe the channel
+*
+*  @note
+*     - This function should be called from ISR in case there are pending
+*       descriptor to program the channel.
+*
+*     Example:
+*
+*     dmac_isr ()
+*     {
+*         ...
+*         if (dmacHw_descriptorPending (handle))
+*         {
+*            dmacHw_initiateTransfer (handle);
+*         }
+*     }
+*
+*/
+/****************************************************************************/
+uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,       /*   [ IN ] DMA Channel handle */
+                                  void *pDescriptor     /*   [ IN ] Descriptor buffer */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Deallocates source or destination memory, allocated
+*
+*  This function can be called to deallocate data memory that was DMAed successfully
+*
+*  @return  -1  - On failure
+*            0  - On success
+*
+*  @note
+*     This function will be called ONLY, when source OR destination address is pointing
+*     to dynamic memory
+*/
+/****************************************************************************/
+int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,    /*  [ IN ] Configuration settings */
+                   void *pDescriptor,   /*  [ IN ] Descriptor buffer  */
+                   void (*fpFree) (void *)      /*  [ IN ] Function pointer to free data memory */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Clears the interrupt
+*
+*  This function clears the DMA channel specific interrupt
+*
+*  @return   N/A
+*
+*  @note
+*     Must be called under the context of ISR
+*/
+/****************************************************************************/
+void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle       /*  [ IN ] DMA Channel handle  */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Returns the cause of channel specific DMA interrupt
+*
+*  This function returns the cause of interrupt
+*
+*  @return  Interrupt status, each bit representing a specific type of interrupt
+*           of type dmacHw_INTERRUPT_STATUS_e
+*  @note
+*           This function should be called under the context of ISR
+*/
+/****************************************************************************/
+dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle      /*  [ IN ] DMA Channel handle  */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Indentifies a DMA channel causing interrupt
+*
+*  This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
+*
+*  @return  NULL   : No channel causing DMA interrupt
+*           ! NULL : Handle to a channel causing DMA interrupt
+*  @note
+*     dmacHw_clearInterrupt() must be called with a valid handle after calling this function
+*/
+/****************************************************************************/
+dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
+
+/****************************************************************************/
+/**
+*  @brief   Sets channel specific user data
+*
+*  This function associates user data to a specif DMA channel
+*
+*/
+/****************************************************************************/
+void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle  */
+                               void *userData   /*  [ IN ] User data  */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Gets channel specific user data
+*
+*  This function returns user data specific to a DMA channel
+*
+*  @return   user data
+*/
+/****************************************************************************/
+void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle  /*  [ IN ] DMA Channel handle  */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Displays channel specific registers and other control parameters
+*
+*
+*  @return  void
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,      /*  [ IN ] DMA Channel handle  */
+                           void *pDescriptor,   /*  [ IN ] Descriptor buffer  */
+                           int (*fpPrint) (const char *, ...)   /*  [ IN ] Print callback function */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Provides DMA controller attributes
+*
+*
+*  @return  DMA controller attributes
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,       /*  [ IN ]  DMA Channel handle  */
+                                          dmacHw_CONTROLLER_ATTRIB_e attr       /*  [ IN ]  DMA Controler attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
+    );
+
+#endif /* _DMACHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/errno.h b/arch/arm/mach-bcmring/include/csp/errno.h
new file mode 100644
index 000000000000..51357dd5b666
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/errno.h
@@ -0,0 +1,32 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+#ifndef CSP_ERRNO_H
+#define CSP_ERRNO_H
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#if   defined(__KERNEL__)
+#include <linux/errno.h>
+#elif defined(CSP_SIMULATION)
+#include <asm-generic/errno.h>
+#else
+#include <errno.h>
+#endif
+
+/* ---- Public Constants and Types --------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+
+#endif /* CSP_ERRNO_H */
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h
new file mode 100644
index 000000000000..1c639c8ee08f
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/intcHw.h
@@ -0,0 +1,40 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+
+/****************************************************************************/
+/**
+*  @file    intcHw.h
+*
+*  @brief   generic interrupt controller API
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+
+#ifndef _INTCHW_H
+#define _INTCHW_H
+
+/* ---- Include Files ---------------------------------------------------- */
+#include <mach/csp/intcHw_reg.h>
+
+/* ---- Public Constants and Types --------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+static inline void intcHw_irq_disable(void *basep, uint32_t mask);
+static inline void intcHw_irq_enable(void *basep, uint32_t mask);
+
+#endif /* _INTCHW_H */
+
diff --git a/arch/arm/mach-bcmring/include/csp/module.h b/arch/arm/mach-bcmring/include/csp/module.h
new file mode 100644
index 000000000000..c30d2a5975a6
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/module.h
@@ -0,0 +1,32 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+
+#ifndef CSP_MODULE_H
+#define CSP_MODULE_H
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#ifdef __KERNEL__
+    #include <linux/module.h>
+#else
+    #define EXPORT_SYMBOL(symbol)
+#endif
+
+/* ---- Public Constants and Types --------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+
+
+#endif /* CSP_MODULE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/csp/reg.h
new file mode 100644
index 000000000000..e5f60bf5a1f3
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/reg.h
@@ -0,0 +1,114 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    reg.h
+*
+*  @brief   Generic register defintions used in CSP
+*/
+/****************************************************************************/
+
+#ifndef CSP_REG_H
+#define CSP_REG_H
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#include <csp/stdint.h>
+
+/* ---- Public Constants and Types --------------------------------------- */
+
+#define __REG32(x)      (*((volatile uint32_t *)(x)))
+#define __REG16(x)      (*((volatile uint16_t *)(x)))
+#define __REG8(x)       (*((volatile uint8_t *) (x)))
+
+/* Macros used to define a sequence of reserved registers. The start / end */
+/* are byte offsets in the particular register definition, with the "end" */
+/* being the offset of the next un-reserved register. E.g. if offsets */
+/* 0x10 through to 0x1f are reserved, then this reserved area could be */
+/* specified as follows. */
+/*  typedef struct */
+/*  { */
+/*      uint32_t reg1;           offset 0x00 */
+/*      uint32_t reg2;           offset 0x04 */
+/*      uint32_t reg3;           offset 0x08 */
+/*      uint32_t reg4;           offset 0x0c */
+/*      REG32_RSVD(0x10, 0x20); */
+/*      uint32_t reg5;           offset 0x20 */
+/*      ... */
+/*  } EXAMPLE_REG_t; */
+#define REG8_RSVD(start, end)   uint8_t rsvd_##start[(end - start) / sizeof(uint8_t)]
+#define REG16_RSVD(start, end)  uint16_t rsvd_##start[(end - start) / sizeof(uint16_t)]
+#define REG32_RSVD(start, end)  uint32_t rsvd_##start[(end - start) / sizeof(uint32_t)]
+
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+
+/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */
+/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the  */
+/* flags variable to be declared locally. */
+/* e.g. */
+/*    statement1; */
+/*    { */
+/*       REG_LOCAL_IRQ_SAVE; */
+/*       <multiple statements here> */
+/*       REG_LOCAL_IRQ_RESTORE; */
+/*    } */
+/*    statement2; */
+/*  */
+
+#if defined(__KERNEL__) && !defined(STANDALONE)
+#include <mach/hardware.h>
+#include <linux/interrupt.h>
+
+#define REG_LOCAL_IRQ_SAVE      HW_DECLARE_SPINLOCK(reg32) \
+        unsigned long flags; HW_IRQ_SAVE(reg32, flags)
+
+#define REG_LOCAL_IRQ_RESTORE   HW_IRQ_RESTORE(reg32, flags)
+
+#else
+
+#define REG_LOCAL_IRQ_SAVE
+#define REG_LOCAL_IRQ_RESTORE
+
+#endif
+
+static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *reg &= value;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *reg |= value;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
+                                     uint32_t value)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *reg = (*reg & mask) | value;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
+{
+        *reg = value;
+}
+
+#endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h b/arch/arm/mach-bcmring/include/csp/secHw.h
new file mode 100644
index 000000000000..b9d7e0732dfc
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/secHw.h
@@ -0,0 +1,65 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    secHw.h
+*
+*  @brief   Definitions for accessing low level security features
+*
+*/
+/****************************************************************************/
+#ifndef SECHW_H
+#define SECHW_H
+
+typedef void (*secHw_FUNC_t) (void);
+
+typedef enum {
+        secHw_MODE_SECURE = 0x0,        /* Switches processor into secure mode */
+        secHw_MODE_NONSECURE = 0x1      /* Switches processor into non-secure mode */
+} secHw_MODE;
+
+/****************************************************************************/
+/**
+*  @brief   Requesting to execute the function in secure mode
+*
+*  This function requests the given function to run in secure mode
+*
+*/
+/****************************************************************************/
+void secHw_RunSecure(secHw_FUNC_t       /* Function to run in secure mode */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Sets the  mode
+*
+*  his function sets the processor mode (secure/non-secure)
+*
+*/
+/****************************************************************************/
+void secHw_SetMode(secHw_MODE   /* Processor mode */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Get the current mode
+*
+*  This function retieves the processor mode (secure/non-secure)
+*
+*/
+/****************************************************************************/
+void secHw_GetMode(secHw_MODE *);
+
+#endif /* SECHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h b/arch/arm/mach-bcmring/include/csp/stdint.h
new file mode 100644
index 000000000000..3a8718bbf700
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/stdint.h
@@ -0,0 +1,30 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+#ifndef CSP_STDINT_H
+#define CSP_STDINT_H
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+
+/* ---- Public Constants and Types --------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+
+#endif /* CSP_STDINT_H */
diff --git a/arch/arm/mach-bcmring/include/csp/string.h b/arch/arm/mach-bcmring/include/csp/string.h
new file mode 100644
index 000000000000..ad9e4005f141
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/string.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+
+
+#ifndef CSP_STRING_H
+#define CSP_STRING_H
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#ifdef __KERNEL__
+   #include <linux/string.h>
+#else
+   #include <string.h>
+#endif
+
+/* ---- Public Constants and Types --------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+
+
+#endif /* CSP_STRING_H */
+
diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h b/arch/arm/mach-bcmring/include/csp/tmrHw.h
new file mode 100644
index 000000000000..f1236d00cb97
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/tmrHw.h
@@ -0,0 +1,263 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    tmrHw.h
+*
+*  @brief   API definitions for low level Timer driver
+*
+*/
+/****************************************************************************/
+#ifndef _TMRHW_H
+#define _TMRHW_H
+
+#include <csp/stdint.h>
+
+typedef uint32_t tmrHw_ID_t;    /* Timer ID */
+typedef uint32_t tmrHw_COUNT_t; /* Timer count */
+typedef uint32_t tmrHw_INTERVAL_t;      /* Timer interval */
+typedef uint32_t tmrHw_RATE_t;  /* Timer event (count/interrupt) rate */
+
+typedef enum {
+        tmrHw_INTERRUPT_STATUS_SET,     /* Interrupted  */
+        tmrHw_INTERRUPT_STATUS_UNSET    /* No Interrupt */
+} tmrHw_INTERRUPT_STATUS_e;
+
+typedef enum {
+        tmrHw_CAPABILITY_CLOCK, /* Clock speed in HHz */
+        tmrHw_CAPABILITY_RESOLUTION     /* Timer resolution in bits */
+} tmrHw_CAPABILITY_e;
+
+/****************************************************************************/
+/**
+*  @brief   Get timer capability
+*
+*  This function returns various capabilities/attributes of a timer
+*
+*  @return  Numeric capability
+*
+*/
+/****************************************************************************/
+uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,   /*  [ IN ] Timer Id */
+                                  tmrHw_CAPABILITY_e capability /*  [ IN ] Timer capability */
+);
+
+/****************************************************************************/
+/**
+*  @brief   Configures a periodic timer in terms of timer interrupt rate
+*
+*  This function initializes a periodic timer to generate specific number of
+*  timer interrupt per second
+*
+*  @return   On success: Effective timer frequency
+*            On failure: 0
+*
+*/
+/****************************************************************************/
+tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
+                                        tmrHw_RATE_t rate       /*  [ IN ] Number of timer interrupt per second */
+);
+
+/****************************************************************************/
+/**
+*  @brief   Configures a periodic timer to generate timer interrupt after
+*           certain time interval
+*
+*  This function initializes a periodic timer to generate timer interrupt
+*  after every time interval in milisecond
+*
+*  @return   On success: Effective interval set in mili-second
+*            On failure: 0
+*
+*/
+/****************************************************************************/
+tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
+                                                tmrHw_INTERVAL_t msec   /*  [ IN ] Interval in mili-second */
+);
+
+/****************************************************************************/
+/**
+*  @brief   Configures a periodic timer to generate timer interrupt just once
+*           after certain time interval
+*
+*  This function initializes a periodic timer to generate a single ticks after
+*  certain time interval in milisecond
+*
+*  @return   On success: Effective interval set in mili-second
+*            On failure: 0
+*
+*/
+/****************************************************************************/
+tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
+                                               tmrHw_INTERVAL_t msec    /*  [ IN ] Interval in mili-second */
+);
+
+/****************************************************************************/
+/**
+*  @brief   Configures a timer to run as a free running timer
+*
+*  This function initializes a timer to run as a free running timer
+*
+*  @return   Timer resolution (count / sec)
+*
+*/
+/****************************************************************************/
+tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
+                                       uint32_t divider /*  [ IN ] Dividing the clock frequency */
+) __attribute__ ((section(".aramtext")));
+
+/****************************************************************************/
+/**
+*  @brief   Starts a timer
+*
+*  This function starts a preconfigured timer
+*
+*  @return  -1     - On Failure
+*            0     - On Success
+*/
+/****************************************************************************/
+int tmrHw_startTimer(tmrHw_ID_t timerId /*  [ IN ] Timer id */
+) __attribute__ ((section(".aramtext")));
+
+/****************************************************************************/
+/**
+*  @brief   Stops a timer
+*
+*  This function stops a running timer
+*
+*  @return  -1     - On Failure
+*            0     - On Success
+*/
+/****************************************************************************/
+int tmrHw_stopTimer(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
+);
+
+/****************************************************************************/
+/**
+*  @brief   Gets current timer count
+*
+*  This function returns the current timer value
+*
+*  @return  Current downcounting timer value
+*
+*/
+/****************************************************************************/
+tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
+) __attribute__ ((section(".aramtext")));
+
+/****************************************************************************/
+/**
+*  @brief   Gets timer count rate
+*
+*  This function returns the number of counts per second
+*
+*  @return  Count rate
+*
+*/
+/****************************************************************************/
+tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId      /*  [ IN ] Timer id */
+) __attribute__ ((section(".aramtext")));
+
+/****************************************************************************/
+/**
+*  @brief   Enables timer interrupt
+*
+*  This function enables the timer interrupt
+*
+*  @return   N/A
+*
+*/
+/****************************************************************************/
+void tmrHw_enableInterrupt(tmrHw_ID_t timerId   /*  [ IN ] Timer id */
+);
+
+/****************************************************************************/
+/**
+*  @brief   Disables timer interrupt
+*
+*  This function disable the timer interrupt
+*
+*  @return   N/A
+*/
+/****************************************************************************/
+void tmrHw_disableInterrupt(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
+);
+
+/****************************************************************************/
+/**
+*  @brief   Clears the interrupt
+*
+*  This function clears the timer interrupt
+*
+*  @return   N/A
+*
+*  @note
+*     Must be called under the context of ISR
+*/
+/****************************************************************************/
+void tmrHw_clearInterrupt(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
+);
+
+/****************************************************************************/
+/**
+*  @brief   Gets the interrupt status
+*
+*  This function returns timer interrupt status
+*
+*  @return   Interrupt status
+*/
+/****************************************************************************/
+tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
+);
+
+/****************************************************************************/
+/**
+*  @brief   Indentifies a timer causing interrupt
+*
+*  This functions returns a timer causing interrupt
+*
+*  @return  0xFFFFFFFF   : No timer causing an interrupt
+*           ! 0xFFFFFFFF : timer causing an interrupt
+*  @note
+*     tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
+*/
+/****************************************************************************/
+tmrHw_ID_t tmrHw_getInterruptSource(void);
+
+/****************************************************************************/
+/**
+*  @brief   Displays specific timer registers
+*
+*
+*  @return  void
+*
+*/
+/****************************************************************************/
+void tmrHw_printDebugInfo(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
+                          int (*fpPrint) (const char *, ...)    /*  [ IN ] Print callback function */
+);
+
+/****************************************************************************/
+/**
+*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
+*
+*  @return   N/A
+*/
+/****************************************************************************/
+void tmrHw_udelay(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
+                  unsigned long usecs   /*  [ IN ] usec to delay */
+) __attribute__ ((section(".aramtext")));
+
+#endif /* _TMRHW_H */
diff --git a/arch/arm/mach-bcmring/include/mach/clkdev.h b/arch/arm/mach-bcmring/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap.h b/arch/arm/mach-bcmring/include/mach/csp/cap.h
new file mode 100644
index 000000000000..30fa2d540630
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/cap.h
@@ -0,0 +1,63 @@
+/*****************************************************************************
+* Copyright 2009 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+#ifndef CAP_H
+#define CAP_H
+
+/* ---- Include Files ---------------------------------------------------- */
+/* ---- Public Constants and Types --------------------------------------- */
+typedef enum {
+        CAP_NOT_PRESENT = 0,
+        CAP_PRESENT
+} CAP_RC_T;
+
+typedef enum {
+        CAP_VPM,
+        CAP_ETH_PHY,
+        CAP_ETH_GMII,
+        CAP_ETH_SGMII,
+        CAP_USB,
+        CAP_TSC,
+        CAP_EHSS,
+        CAP_SDIO,
+        CAP_UARTB,
+        CAP_KEYPAD,
+        CAP_CLCD,
+        CAP_GE,
+        CAP_LEDM,
+        CAP_BBL,
+        CAP_VDEC,
+        CAP_PIF,
+        CAP_APM,
+        CAP_SPU,
+        CAP_PKA,
+        CAP_RNG,
+} CAP_CAPABILITY_T;
+
+typedef enum {
+        CAP_LCD_WVGA = 0,
+        CAP_LCD_VGA = 0x1,
+        CAP_LCD_WQVGA = 0x2,
+        CAP_LCD_QVGA = 0x3
+} CAP_LCD_RES_T;
+
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+
+static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index);
+static inline uint32_t cap_getMaxArmSpeedHz(void);
+static inline uint32_t cap_getMaxVpmSpeedHz(void);
+static inline CAP_LCD_RES_T cap_getMaxLcdRes(void);
+
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
new file mode 100644
index 000000000000..933ce68ed90b
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
@@ -0,0 +1,409 @@
+/*****************************************************************************
+* Copyright 2009 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+#ifndef CAP_INLINE_H
+#define CAP_INLINE_H
+
+/* ---- Include Files ---------------------------------------------------- */
+#include <mach/csp/cap.h>
+#include <cfg_global.h>
+
+/* ---- Public Constants and Types --------------------------------------- */
+#define CAP_CONFIG0_VPM_DIS          0x00000001
+#define CAP_CONFIG0_ETH_PHY0_DIS     0x00000002
+#define CAP_CONFIG0_ETH_PHY1_DIS     0x00000004
+#define CAP_CONFIG0_ETH_GMII0_DIS    0x00000008
+#define CAP_CONFIG0_ETH_GMII1_DIS    0x00000010
+#define CAP_CONFIG0_ETH_SGMII0_DIS   0x00000020
+#define CAP_CONFIG0_ETH_SGMII1_DIS   0x00000040
+#define CAP_CONFIG0_USB0_DIS         0x00000080
+#define CAP_CONFIG0_USB1_DIS         0x00000100
+#define CAP_CONFIG0_TSC_DIS          0x00000200
+#define CAP_CONFIG0_EHSS0_DIS        0x00000400
+#define CAP_CONFIG0_EHSS1_DIS        0x00000800
+#define CAP_CONFIG0_SDIO0_DIS        0x00001000
+#define CAP_CONFIG0_SDIO1_DIS        0x00002000
+#define CAP_CONFIG0_UARTB_DIS        0x00004000
+#define CAP_CONFIG0_KEYPAD_DIS       0x00008000
+#define CAP_CONFIG0_CLCD_DIS         0x00010000
+#define CAP_CONFIG0_GE_DIS           0x00020000
+#define CAP_CONFIG0_LEDM_DIS         0x00040000
+#define CAP_CONFIG0_BBL_DIS          0x00080000
+#define CAP_CONFIG0_VDEC_DIS         0x00100000
+#define CAP_CONFIG0_PIF_DIS          0x00200000
+#define CAP_CONFIG0_RESERVED1_DIS    0x00400000
+#define CAP_CONFIG0_RESERVED2_DIS    0x00800000
+
+#define CAP_CONFIG1_APMA_DIS         0x00000001
+#define CAP_CONFIG1_APMB_DIS         0x00000002
+#define CAP_CONFIG1_APMC_DIS         0x00000004
+#define CAP_CONFIG1_CLCD_RES_MASK    0x00000600
+#define CAP_CONFIG1_CLCD_RES_SHIFT   9
+#define CAP_CONFIG1_CLCD_RES_WVGA    (CAP_LCD_WVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
+#define CAP_CONFIG1_CLCD_RES_VGA     (CAP_LCD_VGA << CAP_CONFIG1_CLCD_RES_SHIFT)
+#define CAP_CONFIG1_CLCD_RES_WQVGA   (CAP_LCD_WQVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
+#define CAP_CONFIG1_CLCD_RES_QVGA    (CAP_LCD_QVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
+
+#define CAP_CONFIG2_SPU_DIS          0x00000010
+#define CAP_CONFIG2_PKA_DIS          0x00000020
+#define CAP_CONFIG2_RNG_DIS          0x00000080
+
+#if   (CFG_GLOBAL_CHIP == BCM11107)
+#define capConfig0 0
+#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
+#define capConfig2 0
+#define CAP_APM_MAX_NUM_CHANS 3
+#elif (CFG_GLOBAL_CHIP == FPGA11107)
+#define capConfig0 0
+#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
+#define capConfig2 0
+#define CAP_APM_MAX_NUM_CHANS 3
+#elif (CFG_GLOBAL_CHIP == BCM11109)
+#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
+#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
+#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
+#define CAP_APM_MAX_NUM_CHANS 2
+#elif (CFG_GLOBAL_CHIP == BCM11170)
+#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
+#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
+#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
+#define CAP_APM_MAX_NUM_CHANS 2
+#elif (CFG_GLOBAL_CHIP == BCM11110)
+#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
+#define capConfig1 CAP_CONFIG1_APMC_DIS
+#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
+#define CAP_APM_MAX_NUM_CHANS 2
+#elif (CFG_GLOBAL_CHIP == BCM11211)
+#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | CAP_CONFIG0_CLCD_DIS)
+#define capConfig1 CAP_CONFIG1_APMC_DIS
+#define capConfig2 0
+#define CAP_APM_MAX_NUM_CHANS 2
+#else
+#error CFG_GLOBAL_CHIP type capabilities not defined
+#endif
+
+#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
+#define CAP_HW_CFG_ARM_CLK_HZ 500000000
+#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
+#define CAP_HW_CFG_ARM_CLK_HZ 300000000
+#elif (CFG_GLOBAL_CHIP == BCM11211)
+#define CAP_HW_CFG_ARM_CLK_HZ 666666666
+#else
+#error CFG_GLOBAL_CHIP type capabilities not defined
+#endif
+
+#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
+#define CAP_HW_CFG_VPM_CLK_HZ 333333333
+#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
+#define CAP_HW_CFG_VPM_CLK_HZ 200000000
+#else
+#error CFG_GLOBAL_CHIP type capabilities not defined
+#endif
+
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+
+/****************************************************************************
+*  cap_isPresent -
+*
+*  PURPOSE:
+*     Determines if the chip has a certain capability present
+*
+*  PARAMETERS:
+*     capability - type of capability to determine if present
+*
+*  RETURNS:
+*     CAP_PRESENT or CAP_NOT_PRESENT
+****************************************************************************/
+static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index)
+{
+        CAP_RC_T returnVal = CAP_NOT_PRESENT;
+
+        switch (capability) {
+        case CAP_VPM:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_ETH_PHY:
+                {
+                        if ((index == 0)
+                            && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 1)
+                            && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_ETH_GMII:
+                {
+                        if ((index == 0)
+                            && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 1)
+                            && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_ETH_SGMII:
+                {
+                        if ((index == 0)
+                            && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 1)
+                            && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_USB:
+                {
+                        if ((index == 0)
+                            && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 1)
+                            && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_TSC:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_EHSS:
+                {
+                        if ((index == 0)
+                            && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 1)
+                            && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_SDIO:
+                {
+                        if ((index == 0)
+                            && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 1)
+                            && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_UARTB:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_KEYPAD:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_CLCD:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_GE:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_LEDM:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_BBL:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_VDEC:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_PIF:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_APM:
+                {
+                        if ((index == 0)
+                            && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 1)
+                            && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 2)
+                            && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_SPU:
+                {
+                        if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_PKA:
+                {
+                        if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        case CAP_RNG:
+                {
+                        if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+
+        default:
+                {
+                }
+                break;
+        }
+        return returnVal;
+}
+
+/****************************************************************************
+*  cap_getMaxArmSpeedHz -
+*
+*  PURPOSE:
+*     Determines the maximum speed of the ARM CPU
+*
+*  PARAMETERS:
+*     none
+*
+*  RETURNS:
+*     clock speed in Hz that the ARM processor is able to run at
+****************************************************************************/
+static inline uint32_t cap_getMaxArmSpeedHz(void)
+{
+#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
+        return 500000000;
+#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
+        return 300000000;
+#elif (CFG_GLOBAL_CHIP == BCM11211)
+        return 666666666;
+#else
+#error CFG_GLOBAL_CHIP type capabilities not defined
+#endif
+}
+
+/****************************************************************************
+*  cap_getMaxVpmSpeedHz -
+*
+*  PURPOSE:
+*     Determines the maximum speed of the VPM
+*
+*  PARAMETERS:
+*     none
+*
+*  RETURNS:
+*     clock speed in Hz that the VPM is able to run at
+****************************************************************************/
+static inline uint32_t cap_getMaxVpmSpeedHz(void)
+{
+#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
+        return 333333333;
+#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
+        return 200000000;
+#else
+#error CFG_GLOBAL_CHIP type capabilities not defined
+#endif
+}
+
+/****************************************************************************
+*  cap_getMaxLcdRes -
+*
+*  PURPOSE:
+*     Determines the maximum LCD resolution capabilities
+*
+*  PARAMETERS:
+*     none
+*
+*  RETURNS:
+*   CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA
+*
+****************************************************************************/
+static inline CAP_LCD_RES_T cap_getMaxLcdRes(void)
+{
+        return (CAP_LCD_RES_T)
+                ((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >>
+                 CAP_CONFIG1_CLCD_RES_SHIFT);
+}
+
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
new file mode 100644
index 000000000000..70eaea866cfe
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
@@ -0,0 +1,1123 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+#ifndef CHIPC_DEF_H
+#define CHIPC_DEF_H
+
+/* ---- Include Files ----------------------------------------------------- */
+
+#include <csp/stdint.h>
+#include <csp/errno.h>
+#include <csp/reg.h>
+#include <mach/csp/chipcHw_reg.h>
+
+/* ---- Public Constants and Types ---------------------------------------- */
+
+/* Set 1 to configure DDR/VPM phase alignment by HW */
+#define chipcHw_DDR_HW_PHASE_ALIGN    0
+#define chipcHw_VPM_HW_PHASE_ALIGN    0
+
+typedef uint32_t chipcHw_freq;
+
+/* Configurable miscellaneous clocks */
+typedef enum {
+        chipcHw_CLOCK_DDR,      /* DDR PHY Clock */
+        chipcHw_CLOCK_ARM,      /* ARM Clock */
+        chipcHw_CLOCK_ESW,      /* Ethernet Switch Clock */
+        chipcHw_CLOCK_VPM,      /* VPM Clock */
+        chipcHw_CLOCK_ESW125,   /* Ethernet MII Clock */
+        chipcHw_CLOCK_UART,     /* UART Clock */
+        chipcHw_CLOCK_SDIO0,    /* SDIO 0 Clock */
+        chipcHw_CLOCK_SDIO1,    /* SDIO 1 Clock */
+        chipcHw_CLOCK_SPI,      /* SPI Clock */
+        chipcHw_CLOCK_ETM,      /* ARM ETM Clock */
+
+        chipcHw_CLOCK_BUS,      /* BUS Clock */
+        chipcHw_CLOCK_OTP,      /* OTP Clock */
+        chipcHw_CLOCK_I2C,      /* I2C Host Clock */
+        chipcHw_CLOCK_I2S0,     /* I2S 0 Host Clock */
+        chipcHw_CLOCK_RTBUS,    /* DDR PHY Configuration Clock */
+        chipcHw_CLOCK_APM100,   /* APM100 Clock */
+        chipcHw_CLOCK_TSC,      /* Touch screen Clock */
+        chipcHw_CLOCK_LED,      /* LED Clock */
+
+        chipcHw_CLOCK_USB,      /* USB Clock */
+        chipcHw_CLOCK_LCD,      /* LCD CLock */
+        chipcHw_CLOCK_APM,      /* APM Clock */
+
+        chipcHw_CLOCK_I2S1,     /* I2S 1 Host Clock */
+} chipcHw_CLOCK_e;
+
+/* System booting strap options */
+typedef enum {
+        chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART,
+        chipcHw_BOOT_DEVICE_SERIAL_FLASH =
+            chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH,
+        chipcHw_BOOT_DEVICE_NOR_FLASH_16 =
+            chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16,
+        chipcHw_BOOT_DEVICE_NAND_FLASH_8 =
+            chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8,
+        chipcHw_BOOT_DEVICE_NAND_FLASH_16 =
+            chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16
+} chipcHw_BOOT_DEVICE_e;
+
+/* System booting modes */
+typedef enum {
+        chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL,
+        chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW,
+        chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT,
+        chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET
+} chipcHw_BOOT_MODE_e;
+
+/* NAND Flash page size strap options */
+typedef enum {
+        chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512,
+        chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048,
+        chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096,
+        chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT
+} chipcHw_NAND_PAGESIZE_e;
+
+/* GPIO Pin function */
+typedef enum {
+        chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD,
+        chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH,
+        chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI,
+        chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART,
+        chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP,
+        chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS,
+        chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0,
+        chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1,
+        chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM,
+        chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S,
+        chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM,
+        chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG,
+        chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC,
+        chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO
+} chipcHw_GPIO_FUNCTION_e;
+
+/* PIN Output slew rate */
+typedef enum {
+        chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH,
+        chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL
+} chipcHw_PIN_SLEW_RATE_e;
+
+/* PIN Current drive strength */
+typedef enum {
+        chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA,
+        chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA,
+        chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA,
+        chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA,
+        chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA,
+        chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA
+} chipcHw_PIN_CURRENT_STRENGTH_e;
+
+/* PIN Pull up register settings */
+typedef enum {
+        chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE,
+        chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP,
+        chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN
+} chipcHw_PIN_PULL_e;
+
+/* PIN input type settings */
+typedef enum {
+        chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS,
+        chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST
+} chipcHw_PIN_INPUTTYPE_e;
+
+/* Allow/Disalow the support of spread spectrum  */
+typedef enum {
+        chipcHw_SPREAD_SPECTRUM_DISALLOW,       /* Spread spectrum support is not allowed */
+        chipcHw_SPREAD_SPECTRUM_ALLOW   /* Spread spectrum support is allowed */
+} chipcHw_SPREAD_SPECTRUM_e;
+
+typedef struct {
+        chipcHw_SPREAD_SPECTRUM_e ssSupport;    /* Allow/Disalow to support spread spectrum.
+                                                   If supported, call chipcHw_enableSpreadSpectrum ()
+                                                   to activate the spread spectrum with desired spread. */
+        uint32_t pllVcoFreqHz;  /* PLL VCO frequency in Hz */
+        uint32_t pll2VcoFreqHz; /* PLL2 VCO frequency in Hz */
+        uint32_t busClockFreqHz;        /* Bus clock frequency in Hz */
+        uint32_t armBusRatio;   /* ARM clock : Bus clock */
+        uint32_t vpmBusRatio;   /* VPM clock : Bus clock */
+        uint32_t ddrBusRatio;   /* DDR clock : Bus clock */
+} chipcHw_INIT_PARAM_t;
+
+/* CHIP revision number */
+typedef enum {
+        chipcHw_REV_NUMBER_A0 = chipcHw_REG_REV_A0,
+        chipcHw_REV_NUMBER_B0 = chipcHw_REG_REV_B0
+} chipcHw_REV_NUMBER_e;
+
+typedef enum {
+        chipcHw_VPM_HW_PHASE_INTR_DISABLE = chipcHw_REG_VPM_INTR_DISABLE,
+        chipcHw_VPM_HW_PHASE_INTR_FAST = chipcHw_REG_VPM_INTR_FAST,
+        chipcHw_VPM_HW_PHASE_INTR_MEDIUM = chipcHw_REG_VPM_INTR_MEDIUM,
+        chipcHw_VPM_HW_PHASE_INTR_SLOW = chipcHw_REG_VPM_INTR_SLOW
+} chipcHw_VPM_HW_PHASE_INTR_e;
+
+typedef enum {
+        chipcHw_DDR_HW_PHASE_MARGIN_STRICT,     /*  Strict margin for DDR phase align condition */
+        chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM,     /*  Medium margin for DDR phase align condition */
+        chipcHw_DDR_HW_PHASE_MARGIN_WIDE        /*  Wider margin for DDR phase align condition */
+} chipcHw_DDR_HW_PHASE_MARGIN_e;
+
+typedef enum {
+        chipcHw_VPM_HW_PHASE_MARGIN_STRICT,     /*  Strict margin for VPM phase align condition */
+        chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM,     /*  Medium margin for VPM phase align condition */
+        chipcHw_VPM_HW_PHASE_MARGIN_WIDE        /*  Wider margin for VPM phase align condition */
+} chipcHw_VPM_HW_PHASE_MARGIN_e;
+
+#define chipcHw_XTAL_FREQ_Hz                    25000000        /* Reference clock frequency in Hz */
+
+/* Programable pin defines */
+#define chipcHw_PIN_GPIO(n)                     ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF)
+                                                                             /* GPIO pin 0 - 60 */
+#define chipcHw_PIN_UARTTXD                     (chipcHw_GPIO_COUNT + 0)        /* UART Transmit */
+#define chipcHw_PIN_NVI_A                       (chipcHw_GPIO_COUNT + 1)        /* NVI Interface */
+#define chipcHw_PIN_NVI_D                       (chipcHw_GPIO_COUNT + 2)        /* NVI Interface */
+#define chipcHw_PIN_NVI_OEB                     (chipcHw_GPIO_COUNT + 3)        /* NVI Interface */
+#define chipcHw_PIN_NVI_WEB                     (chipcHw_GPIO_COUNT + 4)        /* NVI Interface */
+#define chipcHw_PIN_NVI_CS                      (chipcHw_GPIO_COUNT + 5)        /* NVI Interface */
+#define chipcHw_PIN_NVI_NAND_CSB                (chipcHw_GPIO_COUNT + 6)        /* NVI Interface */
+#define chipcHw_PIN_NVI_FLASHWP                 (chipcHw_GPIO_COUNT + 7)        /* NVI Interface */
+#define chipcHw_PIN_NVI_NAND_RDYB               (chipcHw_GPIO_COUNT + 8)        /* NVI Interface */
+#define chipcHw_PIN_CL_DATA_0_17                (chipcHw_GPIO_COUNT + 9)        /* LCD Data 0 - 17 */
+#define chipcHw_PIN_CL_DATA_18_20               (chipcHw_GPIO_COUNT + 10)       /* LCD Data 18 - 20 */
+#define chipcHw_PIN_CL_DATA_21_23               (chipcHw_GPIO_COUNT + 11)       /* LCD Data 21 - 23 */
+#define chipcHw_PIN_CL_POWER                    (chipcHw_GPIO_COUNT + 12)       /* LCD Power */
+#define chipcHw_PIN_CL_ACK                      (chipcHw_GPIO_COUNT + 13)       /* LCD Ack */
+#define chipcHw_PIN_CL_FP                       (chipcHw_GPIO_COUNT + 14)       /* LCD FP */
+#define chipcHw_PIN_CL_LP                       (chipcHw_GPIO_COUNT + 15)       /* LCD LP */
+#define chipcHw_PIN_UARTRXD                     (chipcHw_GPIO_COUNT + 16)       /* UART Receive */
+
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+
+/****************************************************************************/
+/**
+*  @brief  Initializes the clock module
+*
+*/
+/****************************************************************************/
+void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam       /*  [ IN ] Misc chip initialization parameter */
+    ) __attribute__ ((section(".aramtext")));
+
+/****************************************************************************/
+/**
+*  @brief  Enables the PLL1
+*
+*  This function enables the PLL1
+*
+*/
+/****************************************************************************/
+void chipcHw_pll1Enable(uint32_t vcoFreqHz,     /*  [ IN ] VCO frequency in Hz */
+                        chipcHw_SPREAD_SPECTRUM_e ssSupport     /*  [ IN ] SS status */
+    ) __attribute__ ((section(".aramtext")));
+
+/****************************************************************************/
+/**
+*  @brief  Enables the PLL2
+*
+*  This function enables the PLL2
+*
+*/
+/****************************************************************************/
+void chipcHw_pll2Enable(uint32_t vcoFreqHz      /*  [ IN ] VCO frequency in Hz */
+    ) __attribute__ ((section(".aramtext")));
+
+/****************************************************************************/
+/**
+*  @brief  Disable the PLL1
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_pll1Disable(void);
+
+/****************************************************************************/
+/**
+*  @brief  Disable the PLL2
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_pll2Disable(void);
+
+/****************************************************************************/
+/**
+*  @brief   Set clock fequency for miscellaneous configurable clocks
+*
+*  This function sets clock frequency
+*
+*  @return  Configured clock frequency in KHz
+*
+*/
+/****************************************************************************/
+chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock    /*  [ IN ] Configurable clock */
+    ) __attribute__ ((section(".aramtext")));
+
+/****************************************************************************/
+/**
+*  @brief   Set clock fequency for miscellaneous configurable clocks
+*
+*  This function sets clock frequency
+*
+*  @return  Configured clock frequency in Hz
+*
+*/
+/****************************************************************************/
+chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,   /*  [ IN ] Configurable clock */
+                                       uint32_t freq    /*  [ IN ] Clock frequency in Hz */
+    ) __attribute__ ((section(".aramtext")));
+
+/****************************************************************************/
+/**
+*  @brief   Set VPM clock in sync with BUS clock
+*
+*  This function does the phase adjustment between VPM and BUS clock
+*
+*  @return >= 0 : On success ( # of adjustment required )
+*            -1 : On failure
+*/
+/****************************************************************************/
+int chipcHw_vpmPhaseAlign(void);
+
+/****************************************************************************/
+/**
+*  @brief   Enables core a clock of a certain device
+*
+*  This function enables a core clock
+*
+*  @return  void
+*
+*  @note    Doesnot affect the bus interface clock
+*/
+/****************************************************************************/
+static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock /*  [ IN ] Configurable clock */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Disabled a core clock of a certain device
+*
+*  This function disables a core clock
+*
+*  @return  void
+*
+*  @note    Doesnot affect the bus interface clock
+*/
+/****************************************************************************/
+static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock        /*  [ IN ] Configurable clock */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Enables bypass clock of a certain device
+*
+*  This function enables bypass clock
+*
+*  @note    Doesnot affect the bus interface clock
+*/
+/****************************************************************************/
+static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock      /*  [ IN ] Configurable clock */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Disabled bypass clock of a certain device
+*
+*  This function disables bypass clock
+*
+*  @note    Doesnot affect the bus interface clock
+*/
+/****************************************************************************/
+static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock     /*  [ IN ] Configurable clock */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Get Numeric Chip ID
+*
+*  This function returns Chip ID that includes the revison number
+*
+*  @return  Complete numeric Chip ID
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getChipId(void);
+
+/****************************************************************************/
+/**
+*  @brief   Get Chip Product ID
+*
+*  This function returns Chip Product ID
+*
+*  @return  Chip Product ID
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getChipProductId(void);
+
+/****************************************************************************/
+/**
+*  @brief   Get revision number
+*
+*  This function returns revision number of the chip
+*
+*  @return  Revision number
+*/
+/****************************************************************************/
+static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void);
+
+/****************************************************************************/
+/**
+*  @brief   Enables bus interface clock
+*
+*  Enables  bus interface clock of various device
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_busInterfaceClockEnable(uint32_t mask        /*  [ IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Disables bus interface clock
+*
+*  Disables  bus interface clock of various device
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_busInterfaceClockDisable(uint32_t mask       /*  [ IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Enables various audio channels
+*
+*  Enables audio channel
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_audioChannelEnable(uint32_t mask     /*  [ IN ] Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Disables various audio channels
+*
+*  Disables audio channel
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_audioChannelDisable(uint32_t mask    /*  [ IN ] Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
+    );
+
+/****************************************************************************/
+/**
+*  @brief    Soft resets devices
+*
+*  Soft resets various devices
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
+*/
+/****************************************************************************/
+static inline void chipcHw_softReset(uint64_t mask      /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
+    );
+
+static inline void chipcHw_softResetDisable(uint64_t mask       /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
+    );
+
+static inline void chipcHw_softResetEnable(uint64_t mask        /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
+    );
+
+/****************************************************************************/
+/**
+*  @brief    Configures misc CHIP functionality
+*
+*  Configures CHIP functionality
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_miscControl(uint32_t mask    /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
+    );
+
+static inline void chipcHw_miscControlDisable(uint32_t mask     /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
+    );
+
+static inline void chipcHw_miscControlEnable(uint32_t mask      /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
+    );
+
+/****************************************************************************/
+/**
+*  @brief    Set OTP options
+*
+*  Set OTP options
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_OTP_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_setOTPOption(uint64_t mask   /*  [ IN ] Bit map of type chipcHw_REG_OTP_XXXXXX */
+    );
+
+/****************************************************************************/
+/**
+*  @brief    Get sticky bits
+*
+*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getStickyBits(void);
+
+/****************************************************************************/
+/**
+*  @brief    Set sticky bits
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_STICKY_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_setStickyBits(uint32_t mask  /*  [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
+    );
+
+/****************************************************************************/
+/**
+*  @brief    Clear sticky bits
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_STICKY_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_clearStickyBits(uint32_t mask        /*  [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
+    );
+
+/****************************************************************************/
+/**
+*  @brief    Get software override strap options
+*
+*  Retrieves software override strap options
+*
+*  @return   Software override strap value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getSoftStraps(void);
+
+/****************************************************************************/
+/**
+*  @brief    Set software override strap options
+*
+*  set software override strap options
+*
+*  @return   nothing
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setSoftStraps(uint32_t strapOptions);
+
+/****************************************************************************/
+/**
+*  @brief    Get pin strap options
+*
+*  Retrieves pin strap options
+*
+*  @return   Pin strap value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getPinStraps(void);
+
+/****************************************************************************/
+/**
+*  @brief    Get valid pin strap options
+*
+*  Retrieves valid pin strap options
+*
+*  @return   valid Pin strap value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getValidStraps(void);
+
+/****************************************************************************/
+/**
+*  @brief    Initialize valid pin strap options
+*
+*  Retrieves valid pin strap options by copying HW strap options to soft register
+*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
+*
+*  @return   nothing
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_initValidStraps(void);
+
+/****************************************************************************/
+/**
+*  @brief   Get status (enabled/disabled) of bus interface clock
+*
+*  This function returns the status of devices' bus interface clock
+*
+*  @return  Bus interface clock
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getBusInterfaceClockStatus(void);
+
+/****************************************************************************/
+/**
+*  @brief   Get boot device
+*
+*  This function returns the device type used in booting the system
+*
+*  @return  Boot device of type chipcHw_BOOT_DEVICE_e
+*
+*/
+/****************************************************************************/
+static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void);
+
+/****************************************************************************/
+/**
+*  @brief   Get boot mode
+*
+*  This function returns the way the system was booted
+*
+*  @return  Boot mode of type chipcHw_BOOT_MODE_e
+*
+*/
+/****************************************************************************/
+static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void);
+
+/****************************************************************************/
+/**
+*  @brief   Get NAND flash page size
+*
+*  This function returns the NAND device page size
+*
+*  @return  Boot NAND device page size
+*
+*/
+/****************************************************************************/
+static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void);
+
+/****************************************************************************/
+/**
+*  @brief   Get NAND flash address cycle configuration
+*
+*  This function returns the NAND flash address cycle configuration
+*
+*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
+*
+*/
+/****************************************************************************/
+static inline int chipcHw_getNandExtraCycle(void);
+
+/****************************************************************************/
+/**
+*  @brief   Activates PIF interface
+*
+*  This function activates PIF interface by taking control of LCD pins
+*
+*  @note
+*       When activated, LCD pins will be defined as follows for PIF operation
+*
+*       CLD[17:0]  = pif_data[17:0]
+*       CLD[23:18] = pif_address[5:0]
+*       CLPOWER    = pif_wr_str
+*       CLCP       = pif_rd_str
+*       CLAC       = pif_hat1
+*       CLFP       = pif_hrdy1
+*       CLLP       = pif_hat2
+*       GPIO[42]   = pif_hrdy2
+*
+*       In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_activatePifInterface(void);
+
+/****************************************************************************/
+/**
+*  @brief   Activates LCD interface
+*
+*  This function activates LCD interface
+*
+*  @note
+*       When activated, LCD pins will be defined as follows
+*
+*       CLD[17:0]  = LCD data
+*       CLD[23:18] = LCD data
+*       CLPOWER    = LCD power
+*       CLCP       =
+*       CLAC       = LCD ack
+*       CLFP       =
+*       CLLP       =
+*/
+/****************************************************************************/
+static inline void chipcHw_activateLcdInterface(void);
+
+/****************************************************************************/
+/**
+*  @brief   Deactivates PIF/LCD interface
+*
+*  This function deactivates PIF/LCD interface
+*
+*  @note
+*       When deactivated LCD pins will be in rti-stated
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_deactivatePifLcdInterface(void);
+
+/****************************************************************************/
+/**
+*  @brief   Get to know the configuration of GPIO pin
+*
+*/
+/****************************************************************************/
+static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin        /* GPIO Pin number */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Configure GPIO pin function
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setGpioPinFunction(int pin,  /* GPIO Pin number */
+                                              chipcHw_GPIO_FUNCTION_e func      /* Configuration function */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Set Pin slew rate
+*
+*  This function sets the slew of individual pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinSlewRate(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
+                                          chipcHw_PIN_SLEW_RATE_e slewRate      /* Pin slew rate */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Set Pin output drive current
+*
+*  This function sets output drive current of individual pin
+*
+*  Note: Avoid the use of the word 'current' since linux headers define this
+*        to be the current task.
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinOutputCurrent(uint32_t pin,    /* Pin of type chipcHw_PIN_XXXXX */
+                                               chipcHw_PIN_CURRENT_STRENGTH_e curr      /* Pin current rating */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Set Pin pullup register
+*
+*  This function sets pullup register of individual  pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinPullup(uint32_t pin,   /* Pin of type chipcHw_PIN_XXXXX */
+                                        chipcHw_PIN_PULL_e pullup       /* Pullup register settings */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Set Pin input type
+*
+*  This function sets input type of individual Pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinInputType(uint32_t pin,        /* Pin of type chipcHw_PIN_XXXXX */
+                                           chipcHw_PIN_INPUTTYPE_e inputType    /* Pin input type */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Retrieves a string representation of the mux setting for a pin.
+*
+*  @return  Pointer to a character string.
+*/
+/****************************************************************************/
+
+const char *chipcHw_getGpioPinFunctionStr(int pin);
+
+/****************************************************************************/
+/**  @brief issue warmReset
+ */
+/****************************************************************************/
+void chipcHw_reset(uint32_t mask);
+
+/****************************************************************************/
+/**  @brief clock reconfigure
+ */
+/****************************************************************************/
+void chipcHw_clockReconfig(uint32_t busHz, uint32_t armRatio, uint32_t vpmRatio,
+                           uint32_t ddrRatio);
+
+/****************************************************************************/
+/**
+*  @brief   Enable Spread Spectrum
+*
+*  @note chipcHw_Init() must be called earlier
+*/
+/****************************************************************************/
+static inline void chipcHw_enableSpreadSpectrum(void);
+
+/****************************************************************************/
+/**
+*  @brief   Disable Spread Spectrum
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_disableSpreadSpectrum(void);
+
+/****************************************************************************/
+/**  @brief Checks if software strap is enabled
+ *
+ *   @return 1 : When enable
+ *           0 : When disable
+ */
+/****************************************************************************/
+static inline int chipcHw_isSoftwareStrapsEnable(void);
+
+/****************************************************************************/
+/**  @brief Enable software strap
+ */
+/****************************************************************************/
+static inline void chipcHw_softwareStrapsEnable(void);
+
+/****************************************************************************/
+/**  @brief Disable software strap
+ */
+/****************************************************************************/
+static inline void chipcHw_softwareStrapsDisable(void);
+
+/****************************************************************************/
+/**  @brief PLL test enable
+ */
+/****************************************************************************/
+static inline void chipcHw_pllTestEnable(void);
+
+/****************************************************************************/
+/**  @brief PLL2 test enable
+ */
+/****************************************************************************/
+static inline void chipcHw_pll2TestEnable(void);
+
+/****************************************************************************/
+/**  @brief PLL test disable
+ */
+/****************************************************************************/
+static inline void chipcHw_pllTestDisable(void);
+
+/****************************************************************************/
+/**  @brief PLL2 test disable
+ */
+/****************************************************************************/
+static inline void chipcHw_pll2TestDisable(void);
+
+/****************************************************************************/
+/**  @brief Get PLL test status
+ */
+/****************************************************************************/
+static inline int chipcHw_isPllTestEnable(void);
+
+/****************************************************************************/
+/**  @brief Get PLL2 test status
+ */
+/****************************************************************************/
+static inline int chipcHw_isPll2TestEnable(void);
+
+/****************************************************************************/
+/**  @brief PLL test select
+ */
+/****************************************************************************/
+static inline void chipcHw_pllTestSelect(uint32_t val);
+
+/****************************************************************************/
+/**  @brief PLL2 test select
+ */
+/****************************************************************************/
+static inline void chipcHw_pll2TestSelect(uint32_t val);
+
+/****************************************************************************/
+/**  @brief Get PLL test selected option
+ */
+/****************************************************************************/
+static inline uint8_t chipcHw_getPllTestSelected(void);
+
+/****************************************************************************/
+/**  @brief Get PLL2 test selected option
+ */
+/****************************************************************************/
+static inline uint8_t chipcHw_getPll2TestSelected(void);
+
+/****************************************************************************/
+/**
+*  @brief   Enables DDR SW phase alignment interrupt
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrPhaseAlignInterruptEnable(void);
+
+/****************************************************************************/
+/**
+*  @brief   Disables DDR SW phase alignment interrupt
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrPhaseAlignInterruptDisable(void);
+
+/****************************************************************************/
+/**
+*  @brief   Set VPM SW phase alignment interrupt mode
+*
+*  This function sets VPM phase alignment interrupt
+*
+*/
+/****************************************************************************/
+static inline void
+chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode);
+
+/****************************************************************************/
+/**
+*  @brief   Enable DDR phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrSwPhaseAlignEnable(void);
+
+/****************************************************************************/
+/**
+*  @brief   Disable DDR phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrSwPhaseAlignDisable(void);
+
+/****************************************************************************/
+/**
+*  @brief   Enable DDR phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignEnable(void);
+
+/****************************************************************************/
+/**
+*  @brief   Disable DDR phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignDisable(void);
+
+/****************************************************************************/
+/**
+*  @brief   Enable VPM phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmSwPhaseAlignEnable(void);
+
+/****************************************************************************/
+/**
+*  @brief   Disable VPM phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmSwPhaseAlignDisable(void);
+
+/****************************************************************************/
+/**
+*  @brief   Enable VPM phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignEnable(void);
+
+/****************************************************************************/
+/**
+*  @brief   Disable VPM phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignDisable(void);
+
+/****************************************************************************/
+/**
+*  @brief   Set DDR phase alignment margin in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin        /* Margin alinging DDR  phase */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Set VPM phase alignment margin in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin        /* Margin alinging VPM  phase */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   Checks DDR phase aligned status done by HW
+*
+*  @return  1: When aligned
+*           0: When not aligned
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_isDdrHwPhaseAligned(void);
+
+/****************************************************************************/
+/**
+*  @brief   Checks VPM phase aligned status done by HW
+*
+*  @return  1: When aligned
+*           0: When not aligned
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_isVpmHwPhaseAligned(void);
+
+/****************************************************************************/
+/**
+*  @brief   Get DDR phase aligned status done by HW
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void);
+
+/****************************************************************************/
+/**
+*  @brief   Get VPM phase aligned status done by HW
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void);
+
+/****************************************************************************/
+/**
+*  @brief   Get DDR phase control value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getDdrPhaseControl(void);
+
+/****************************************************************************/
+/**
+*  @brief   Get VPM phase control value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getVpmPhaseControl(void);
+
+/****************************************************************************/
+/**
+*  @brief   DDR phase alignment timeout count
+*
+*  @note    If HW fails to perform the phase alignment, it will trigger
+*           a DDR phase alignment timeout interrupt.
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle     /* Timeout in bus cycle */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   VPM phase alignment timeout count
+*
+*  @note    If HW fails to perform the phase alignment, it will trigger
+*           a VPM phase alignment timeout interrupt.
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle     /* Timeout in bus cycle */
+    );
+
+/****************************************************************************/
+/**
+*  @brief   DDR phase alignment timeout interrupt enable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void);
+
+/****************************************************************************/
+/**
+*  @brief   VPM phase alignment timeout interrupt enable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void);
+
+/****************************************************************************/
+/**
+*  @brief   DDR phase alignment timeout interrupt disable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void);
+
+/****************************************************************************/
+/**
+*  @brief   VPM phase alignment timeout interrupt disable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void);
+
+/****************************************************************************/
+/**
+*  @brief   Clear DDR phase alignment timeout interrupt
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void);
+
+/****************************************************************************/
+/**
+*  @brief   Clear VPM phase alignment timeout interrupt
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void);
+
+/* ---- Private Constants and Types -------------------------------------- */
+
+#endif /* CHIPC_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
new file mode 100644
index 000000000000..c78833acb37a
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
@@ -0,0 +1,1673 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+#ifndef CHIPC_INLINE_H
+#define CHIPC_INLINE_H
+
+/* ---- Include Files ----------------------------------------------------- */
+
+#include <csp/errno.h>
+#include <csp/reg.h>
+#include <mach/csp/chipcHw_reg.h>
+#include <mach/csp/chipcHw_def.h>
+
+/* ---- Private Constants and Types --------------------------------------- */
+typedef enum {
+        chipcHw_OPTYPE_BYPASS,  /* Bypass operation */
+        chipcHw_OPTYPE_OUTPUT   /* Output operation */
+} chipcHw_OPTYPE_e;
+
+/* ---- Public Constants and Types ---------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------- */
+/* ---- Public Function Prototypes ---------------------------------------- */
+/* ---- Private Function Prototypes --------------------------------------- */
+static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
+                                    chipcHw_OPTYPE_e type, int mode);
+
+/****************************************************************************/
+/**
+*  @brief   Get Numeric Chip ID
+*
+*  This function returns Chip ID that includes the revison number
+*
+*  @return  Complete numeric Chip ID
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getChipId(void)
+{
+        return pChipcHw->ChipId;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Enable Spread Spectrum
+*
+*  @note chipcHw_Init() must be called earlier
+*/
+/****************************************************************************/
+static inline void chipcHw_enableSpreadSpectrum(void)
+{
+        if ((pChipcHw->
+             PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
+            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+                ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
+                    (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
+                    (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
+                     ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
+                ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
+                    ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
+        }
+}
+
+/****************************************************************************/
+/**
+*  @brief   Disable Spread Spectrum
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_disableSpreadSpectrum(void)
+{
+        ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get Chip Product ID
+*
+*  This function returns Chip Product ID
+*
+*  @return  Chip Product ID
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getChipProductId(void)
+{
+        return (pChipcHw->
+                 ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
+                chipcHw_REG_CHIPID_BASE_SHIFT;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get revision number
+*
+*  This function returns revision number of the chip
+*
+*  @return  Revision number
+*/
+/****************************************************************************/
+static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
+{
+        return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Enables bus interface clock
+*
+*  Enables  bus interface clock of various device
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_BUS_CLOCK_XXXX for mask
+*/
+/****************************************************************************/
+static inline void chipcHw_busInterfaceClockEnable(uint32_t mask)
+{
+        reg32_modify_or(&pChipcHw->BusIntfClock, mask);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Disables bus interface clock
+*
+*  Disables  bus interface clock of various device
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
+{
+        reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get status (enabled/disabled) of bus interface clock
+*
+*  This function returns the status of devices' bus interface clock
+*
+*  @return  Bus interface clock
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
+{
+        return pChipcHw->BusIntfClock;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Enables various audio channels
+*
+*  Enables audio channel
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_audioChannelEnable(uint32_t mask)
+{
+        reg32_modify_or(&pChipcHw->AudioEnable, mask);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Disables various audio channels
+*
+*  Disables audio channel
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_audioChannelDisable(uint32_t mask)
+{
+        reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
+}
+
+/****************************************************************************/
+/**
+*  @brief    Soft resets devices
+*
+*  Soft resets various devices
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
+*/
+/****************************************************************************/
+static inline void chipcHw_softReset(uint64_t mask)
+{
+        chipcHw_softResetEnable(mask);
+        chipcHw_softResetDisable(mask);
+}
+
+static inline void chipcHw_softResetDisable(uint64_t mask)
+{
+        uint32_t ctrl1 = (uint32_t) mask;
+        uint32_t ctrl2 = (uint32_t) (mask >> 32);
+
+        /* Deassert module soft reset */
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->SoftReset1 ^= ctrl1;
+        pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+static inline void chipcHw_softResetEnable(uint64_t mask)
+{
+        uint32_t ctrl1 = (uint32_t) mask;
+        uint32_t ctrl2 = (uint32_t) (mask >> 32);
+        uint32_t unhold = 0;
+
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->SoftReset1 |= ctrl1;
+        /* Mask out unhold request bits */
+        pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
+
+        /* Process unhold requests */
+        if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
+                unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD;
+        }
+
+        if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) {
+                unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD;
+        }
+
+        if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) {
+                unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD;
+        }
+
+        if (unhold) {
+                /* Make sure unhold request is effective */
+                pChipcHw->SoftReset1 &= ~unhold;
+        }
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief    Configures misc CHIP functionality
+*
+*  Configures CHIP functionality
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_miscControl(uint32_t mask)
+{
+        reg32_write(&pChipcHw->MiscCtrl, mask);
+}
+
+static inline void chipcHw_miscControlDisable(uint32_t mask)
+{
+        reg32_modify_and(&pChipcHw->MiscCtrl, ~mask);
+}
+
+static inline void chipcHw_miscControlEnable(uint32_t mask)
+{
+        reg32_modify_or(&pChipcHw->MiscCtrl, mask);
+}
+
+/****************************************************************************/
+/**
+*  @brief    Set OTP options
+*
+*  Set OTP options
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_OTP_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_setOTPOption(uint64_t mask)
+{
+        uint32_t ctrl1 = (uint32_t) mask;
+        uint32_t ctrl2 = (uint32_t) (mask >> 32);
+
+        reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1);
+        reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2);
+}
+
+/****************************************************************************/
+/**
+*  @brief    Get sticky bits
+*
+*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getStickyBits(void)
+{
+        return pChipcHw->Sticky;
+}
+
+/****************************************************************************/
+/**
+*  @brief    Set sticky bits
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_STICKY_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_setStickyBits(uint32_t mask)
+{
+        uint32_t bits = 0;
+
+        REG_LOCAL_IRQ_SAVE;
+        if (mask & chipcHw_REG_STICKY_POR_BROM) {
+                bits |= chipcHw_REG_STICKY_POR_BROM;
+        } else {
+                uint32_t sticky;
+                sticky = pChipcHw->Sticky;
+
+                if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
+                    && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
+                        bits |= chipcHw_REG_STICKY_BOOT_DONE;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_1)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_1;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_2)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_2;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_3)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_3;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_4)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_4;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_5)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_5;
+                }
+        }
+        pChipcHw->Sticky = bits;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief    Clear sticky bits
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_STICKY_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_clearStickyBits(uint32_t mask)
+{
+        uint32_t bits = 0;
+
+        REG_LOCAL_IRQ_SAVE;
+        if (mask &
+            (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
+             chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
+             chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
+                uint32_t sticky = pChipcHw->Sticky;
+
+                if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
+                    && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
+                        bits = chipcHw_REG_STICKY_BOOT_DONE;
+                        mask &= ~chipcHw_REG_STICKY_BOOT_DONE;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_1)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_1)) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_1;
+                        mask &= ~chipcHw_REG_STICKY_GENERAL_1;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_2)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_2)) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_2;
+                        mask &= ~chipcHw_REG_STICKY_GENERAL_2;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_3)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_3)) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_3;
+                        mask &= ~chipcHw_REG_STICKY_GENERAL_3;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_4)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_4)) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_4;
+                        mask &= ~chipcHw_REG_STICKY_GENERAL_4;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_5)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_5)) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_5;
+                        mask &= ~chipcHw_REG_STICKY_GENERAL_5;
+                }
+        }
+        pChipcHw->Sticky = bits | mask;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief    Get software strap value
+*
+*  Retrieves software strap value
+*
+*  @return   Software strap value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getSoftStraps(void)
+{
+        return pChipcHw->SoftStraps;
+}
+
+/****************************************************************************/
+/**
+*  @brief    Set software override strap options
+*
+*  set software override strap options
+*
+*  @return   nothing
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
+{
+        reg32_write(&pChipcHw->SoftStraps, strapOptions);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get Pin Strap Options
+*
+*  This function returns the raw boot strap options
+*
+*  @return  strap options
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getPinStraps(void)
+{
+        return pChipcHw->PinStraps;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get Valid Strap Options
+*
+*  This function returns the valid raw boot strap options
+*
+*  @return  strap options
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getValidStraps(void)
+{
+        uint32_t softStraps;
+
+        /*
+         ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps
+         ** which copies HW straps to soft straps if there is no override
+         */
+        softStraps = chipcHw_getSoftStraps();
+
+        return softStraps;
+}
+
+/****************************************************************************/
+/**
+*  @brief    Initialize valid pin strap options
+*
+*  Retrieves valid pin strap options by copying HW strap options to soft register
+*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
+*
+*  @return   nothing
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_initValidStraps(void)
+{
+        uint32_t softStraps;
+
+        REG_LOCAL_IRQ_SAVE;
+        softStraps = chipcHw_getSoftStraps();
+
+        if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) {
+                /* Copy HW straps to software straps */
+                chipcHw_setSoftStraps(chipcHw_getPinStraps());
+        }
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get boot device
+*
+*  This function returns the device type used in booting the system
+*
+*  @return  Boot device of type chipcHw_BOOT_DEVICE
+*
+*/
+/****************************************************************************/
+static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void)
+{
+        return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get boot mode
+*
+*  This function returns the way the system was booted
+*
+*  @return  Boot mode of type chipcHw_BOOT_MODE
+*
+*/
+/****************************************************************************/
+static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void)
+{
+        return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get NAND flash page size
+*
+*  This function returns the NAND device page size
+*
+*  @return  Boot NAND device page size
+*
+*/
+/****************************************************************************/
+static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void)
+{
+        return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get NAND flash address cycle configuration
+*
+*  This function returns the NAND flash address cycle configuration
+*
+*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
+*
+*/
+/****************************************************************************/
+static inline int chipcHw_getNandExtraCycle(void)
+{
+        if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) {
+                return 1;
+        } else {
+                return 0;
+        }
+}
+
+/****************************************************************************/
+/**
+*  @brief   Activates PIF interface
+*
+*  This function activates PIF interface by taking control of LCD pins
+*
+*  @note
+*       When activated, LCD pins will be defined as follows for PIF operation
+*
+*       CLD[17:0]  = pif_data[17:0]
+*       CLD[23:18] = pif_address[5:0]
+*       CLPOWER    = pif_wr_str
+*       CLCP       = pif_rd_str
+*       CLAC       = pif_hat1
+*       CLFP       = pif_hrdy1
+*       CLLP       = pif_hat2
+*       GPIO[42]   = pif_hrdy2
+*
+*       In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_activatePifInterface(void)
+{
+        reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Activates LCD interface
+*
+*  This function activates LCD interface
+*
+*  @note
+*       When activated, LCD pins will be defined as follows
+*
+*       CLD[17:0]  = LCD data
+*       CLD[23:18] = LCD data
+*       CLPOWER    = LCD power
+*       CLCP       =
+*       CLAC       = LCD ack
+*       CLFP       =
+*       CLLP       =
+*/
+/****************************************************************************/
+static inline void chipcHw_activateLcdInterface(void)
+{
+        reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Deactivates PIF/LCD interface
+*
+*  This function deactivates PIF/LCD interface
+*
+*  @note
+*       When deactivated LCD pins will be in rti-stated
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_deactivatePifLcdInterface(void)
+{
+        reg32_write(&pChipcHw->LcdPifMode, 0);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Select GE2
+*
+*  This function select GE2 as the graphic engine
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_selectGE2(void)
+{
+        reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Select GE3
+*
+*  This function select GE3 as the graphic engine
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_selectGE3(void)
+{
+        reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get to know the configuration of GPIO pin
+*
+*/
+/****************************************************************************/
+static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
+{
+        return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
+                (chipcHw_REG_GPIO_MUX_MASK <<
+                 chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
+            chipcHw_REG_GPIO_MUX_POSITION(pin);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Configure GPIO pin function
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setGpioPinFunction(int pin,
+                                              chipcHw_GPIO_FUNCTION_e func)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &=
+            ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin));
+        *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |=
+            func << chipcHw_REG_GPIO_MUX_POSITION(pin);
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Set Pin slew rate
+*
+*  This function sets the slew of individual pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinSlewRate(uint32_t pin,
+                                          chipcHw_PIN_SLEW_RATE_e slewRate)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &=
+            ~(chipcHw_REG_SLEW_RATE_MASK <<
+              chipcHw_REG_SLEW_RATE_POSITION(pin));
+        *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |=
+            (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin);
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Set Pin output drive current
+*
+*  This function sets output drive current of individual pin
+*
+*  Note: Avoid the use of the word 'current' since linux headers define this
+*        to be the current task.
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinOutputCurrent(uint32_t pin,
+                                               chipcHw_PIN_CURRENT_STRENGTH_e
+                                               curr)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *((uint32_t *) chipcHw_REG_CURRENT(pin)) &=
+            ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin));
+        *((uint32_t *) chipcHw_REG_CURRENT(pin)) |=
+            (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin);
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Set Pin pullup register
+*
+*  This function sets pullup register of individual pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinPullup(uint32_t pin, chipcHw_PIN_PULL_e pullup)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *((uint32_t *) chipcHw_REG_PULLUP(pin)) &=
+            ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin));
+        *((uint32_t *) chipcHw_REG_PULLUP(pin)) |=
+            (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin);
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Set Pin input type
+*
+*  This function sets input type of individual pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinInputType(uint32_t pin,
+                                           chipcHw_PIN_INPUTTYPE_e inputType)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &=
+            ~(chipcHw_REG_INPUTTYPE_MASK <<
+              chipcHw_REG_INPUTTYPE_POSITION(pin));
+        *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |=
+            (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin);
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Power up the USB PHY
+*
+*  This function powers up the USB PHY
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_powerUpUsbPhy(void)
+{
+        reg32_modify_and(&pChipcHw->MiscCtrl,
+                         chipcHw_REG_MISC_CTRL_USB_POWERON);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Power down the USB PHY
+*
+*  This function powers down the USB PHY
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_powerDownUsbPhy(void)
+{
+        reg32_modify_or(&pChipcHw->MiscCtrl,
+                        chipcHw_REG_MISC_CTRL_USB_POWEROFF);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Set the 2nd USB as host
+*
+*  This function sets the 2nd USB as host
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setUsbHost(void)
+{
+        reg32_modify_or(&pChipcHw->MiscCtrl,
+                        chipcHw_REG_MISC_CTRL_USB_MODE_HOST);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Set the 2nd USB as device
+*
+*  This function sets the 2nd USB as device
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setUsbDevice(void)
+{
+        reg32_modify_and(&pChipcHw->MiscCtrl,
+                         chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Lower layer funtion to enable/disable a clock of a certain device
+*
+*  This function enables/disables a core clock
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
+                                    chipcHw_OPTYPE_e type, int mode)
+{
+        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
+        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
+
+        switch (clock) {
+        case chipcHw_CLOCK_DDR:
+                pPLLReg = &pChipcHw->DDRClock;
+                break;
+        case chipcHw_CLOCK_ARM:
+                pPLLReg = &pChipcHw->ARMClock;
+                break;
+        case chipcHw_CLOCK_ESW:
+                pPLLReg = &pChipcHw->ESWClock;
+                break;
+        case chipcHw_CLOCK_VPM:
+                pPLLReg = &pChipcHw->VPMClock;
+                break;
+        case chipcHw_CLOCK_ESW125:
+                pPLLReg = &pChipcHw->ESW125Clock;
+                break;
+        case chipcHw_CLOCK_UART:
+                pPLLReg = &pChipcHw->UARTClock;
+                break;
+        case chipcHw_CLOCK_SDIO0:
+                pPLLReg = &pChipcHw->SDIO0Clock;
+                break;
+        case chipcHw_CLOCK_SDIO1:
+                pPLLReg = &pChipcHw->SDIO1Clock;
+                break;
+        case chipcHw_CLOCK_SPI:
+                pPLLReg = &pChipcHw->SPIClock;
+                break;
+        case chipcHw_CLOCK_ETM:
+                pPLLReg = &pChipcHw->ETMClock;
+                break;
+        case chipcHw_CLOCK_USB:
+                pPLLReg = &pChipcHw->USBClock;
+                if (type == chipcHw_OPTYPE_OUTPUT) {
+                        if (mode) {
+                                reg32_modify_and(pPLLReg,
+                                                 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
+                        } else {
+                                reg32_modify_or(pPLLReg,
+                                                chipcHw_REG_PLL_CLOCK_POWER_DOWN);
+                        }
+                }
+                break;
+        case chipcHw_CLOCK_LCD:
+                pPLLReg = &pChipcHw->LCDClock;
+                if (type == chipcHw_OPTYPE_OUTPUT) {
+                        if (mode) {
+                                reg32_modify_and(pPLLReg,
+                                                 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
+                        } else {
+                                reg32_modify_or(pPLLReg,
+                                                chipcHw_REG_PLL_CLOCK_POWER_DOWN);
+                        }
+                }
+                break;
+        case chipcHw_CLOCK_APM:
+                pPLLReg = &pChipcHw->APMClock;
+                if (type == chipcHw_OPTYPE_OUTPUT) {
+                        if (mode) {
+                                reg32_modify_and(pPLLReg,
+                                                 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
+                        } else {
+                                reg32_modify_or(pPLLReg,
+                                                chipcHw_REG_PLL_CLOCK_POWER_DOWN);
+                        }
+                }
+                break;
+        case chipcHw_CLOCK_BUS:
+                pClockCtrl = &pChipcHw->ACLKClock;
+                break;
+        case chipcHw_CLOCK_OTP:
+                pClockCtrl = &pChipcHw->OTPClock;
+                break;
+        case chipcHw_CLOCK_I2C:
+                pClockCtrl = &pChipcHw->I2CClock;
+                break;
+        case chipcHw_CLOCK_I2S0:
+                pClockCtrl = &pChipcHw->I2S0Clock;
+                break;
+        case chipcHw_CLOCK_RTBUS:
+                pClockCtrl = &pChipcHw->RTBUSClock;
+                break;
+        case chipcHw_CLOCK_APM100:
+                pClockCtrl = &pChipcHw->APM100Clock;
+                break;
+        case chipcHw_CLOCK_TSC:
+                pClockCtrl = &pChipcHw->TSCClock;
+                break;
+        case chipcHw_CLOCK_LED:
+                pClockCtrl = &pChipcHw->LEDClock;
+                break;
+        case chipcHw_CLOCK_I2S1:
+                pClockCtrl = &pChipcHw->I2S1Clock;
+                break;
+        }
+
+        if (pPLLReg) {
+                switch (type) {
+                case chipcHw_OPTYPE_OUTPUT:
+                        /* PLL clock output enable/disable */
+                        if (mode) {
+                                if (clock == chipcHw_CLOCK_DDR) {
+                                        /* DDR clock enable is inverted */
+                                        reg32_modify_and(pPLLReg,
+                                                         ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
+                                } else {
+                                        reg32_modify_or(pPLLReg,
+                                                        chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
+                                }
+                        } else {
+                                if (clock == chipcHw_CLOCK_DDR) {
+                                        /* DDR clock disable is inverted */
+                                        reg32_modify_or(pPLLReg,
+                                                        chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
+                                } else {
+                                        reg32_modify_and(pPLLReg,
+                                                         ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
+                                }
+                        }
+                        break;
+                case chipcHw_OPTYPE_BYPASS:
+                        /* PLL clock bypass enable/disable */
+                        if (mode) {
+                                reg32_modify_or(pPLLReg,
+                                                chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
+                        } else {
+                                reg32_modify_and(pPLLReg,
+                                                 ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
+                        }
+                        break;
+                }
+        } else if (pClockCtrl) {
+                switch (type) {
+                case chipcHw_OPTYPE_OUTPUT:
+                        if (mode) {
+                                reg32_modify_or(pClockCtrl,
+                                                chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
+                        } else {
+                                reg32_modify_and(pClockCtrl,
+                                                 ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
+                        }
+                        break;
+                case chipcHw_OPTYPE_BYPASS:
+                        if (mode) {
+                                reg32_modify_or(pClockCtrl,
+                                                chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
+                        } else {
+                                reg32_modify_and(pClockCtrl,
+                                                 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
+                        }
+                        break;
+                }
+        }
+}
+
+/****************************************************************************/
+/**
+*  @brief   Disables a core clock of a certain device
+*
+*  This function disables a core clock
+*
+*  @note    no change in power consumption
+*/
+/****************************************************************************/
+static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock)
+{
+
+        /* Disable output of the clock */
+        chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Enable a core clock of a certain device
+*
+*  This function enables a core clock
+*
+*  @note    no change in power consumption
+*/
+/****************************************************************************/
+static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock)
+{
+
+        /* Enable output of the clock */
+        chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Enables bypass clock of a certain device
+*
+*  This function enables bypass clock
+*
+*  @note    Doesnot affect the bus interface clock
+*/
+/****************************************************************************/
+static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock)
+{
+        /* Enable bypass clock */
+        chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1);
+}
+
+/****************************************************************************/
+/**
+*  @brief   Disabled bypass clock of a certain device
+*
+*  This function disables bypass clock
+*
+*  @note    Doesnot affect the bus interface clock
+*/
+/****************************************************************************/
+static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
+{
+        /* Disable bypass clock */
+        chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0);
+
+}
+
+/****************************************************************************/
+/**  @brief Checks if software strap is enabled
+ *
+ *   @return 1 : When enable
+ *           0 : When disable
+ */
+/****************************************************************************/
+static inline int chipcHw_isSoftwareStrapsEnable(void)
+{
+        return pChipcHw->SoftStraps & 0x00000001;
+}
+
+/****************************************************************************/
+/**  @brief Enable software strap
+ */
+/****************************************************************************/
+static inline void chipcHw_softwareStrapsEnable(void)
+{
+        reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001);
+}
+
+/****************************************************************************/
+/**  @brief Disable software strap
+ */
+/****************************************************************************/
+static inline void chipcHw_softwareStrapsDisable(void)
+{
+        reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001));
+}
+
+/****************************************************************************/
+/**  @brief PLL test enable
+ */
+/****************************************************************************/
+static inline void chipcHw_pllTestEnable(void)
+{
+        reg32_modify_or(&pChipcHw->PLLConfig,
+                        chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
+}
+
+/****************************************************************************/
+/**  @brief PLL2 test enable
+ */
+/****************************************************************************/
+static inline void chipcHw_pll2TestEnable(void)
+{
+        reg32_modify_or(&pChipcHw->PLLConfig2,
+                        chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
+}
+
+/****************************************************************************/
+/**  @brief PLL test disable
+ */
+/****************************************************************************/
+static inline void chipcHw_pllTestDisable(void)
+{
+        reg32_modify_and(&pChipcHw->PLLConfig,
+                         ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
+}
+
+/****************************************************************************/
+/**  @brief PLL2 test disable
+ */
+/****************************************************************************/
+static inline void chipcHw_pll2TestDisable(void)
+{
+        reg32_modify_and(&pChipcHw->PLLConfig2,
+                         ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
+}
+
+/****************************************************************************/
+/**  @brief Get PLL test status
+ */
+/****************************************************************************/
+static inline int chipcHw_isPllTestEnable(void)
+{
+        return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
+}
+
+/****************************************************************************/
+/**  @brief Get PLL2 test status
+ */
+/****************************************************************************/
+static inline int chipcHw_isPll2TestEnable(void)
+{
+        return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
+}
+
+/****************************************************************************/
+/**  @brief PLL test select
+ */
+/****************************************************************************/
+static inline void chipcHw_pllTestSelect(uint32_t val)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
+        pChipcHw->PLLConfig |=
+            (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**  @brief PLL2 test select
+ */
+/****************************************************************************/
+static inline void chipcHw_pll2TestSelect(uint32_t val)
+{
+
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
+        pChipcHw->PLLConfig2 |=
+            (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**  @brief Get PLL test selected option
+ */
+/****************************************************************************/
+static inline uint8_t chipcHw_getPllTestSelected(void)
+{
+        return (uint8_t) ((pChipcHw->
+                           PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
+                          >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
+}
+
+/****************************************************************************/
+/**  @brief Get PLL2 test selected option
+ */
+/****************************************************************************/
+static inline uint8_t chipcHw_getPll2TestSelected(void)
+{
+        return (uint8_t) ((pChipcHw->
+                           PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
+                          >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
+}
+
+/****************************************************************************/
+/**
+*  @brief  Disable the PLL1
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_pll1Disable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief  Disable the PLL2
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_pll2Disable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Enables DDR SW phase alignment interrupt
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Disables DDR SW phase alignment interrupt
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Set VPM SW phase alignment interrupt mode
+*
+*  This function sets VPM phase alignment interrupt
+*/
+/****************************************************************************/
+static inline void
+chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode)
+{
+        REG_LOCAL_IRQ_SAVE;
+        if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) {
+                pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
+        } else {
+                pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
+        }
+        pChipcHw->VPMPhaseCtrl2 =
+            (pChipcHw->
+             VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK <<
+                               chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Enable DDR phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrSwPhaseAlignEnable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Disable DDR phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrSwPhaseAlignDisable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Enable DDR phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignEnable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Disable DDR phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignDisable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Enable VPM phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmSwPhaseAlignEnable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Disable VPM phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmSwPhaseAlignDisable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Enable VPM phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignEnable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Disable VPM phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignDisable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Set DDR phase alignment margin in hardware
+*
+*/
+/****************************************************************************/
+static inline void
+chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin)
+{
+        uint32_t ge = 0;
+        uint32_t le = 0;
+
+        switch (margin) {
+        case chipcHw_DDR_HW_PHASE_MARGIN_STRICT:
+                ge = 0x0F;
+                le = 0x0F;
+                break;
+        case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM:
+                ge = 0x03;
+                le = 0x3F;
+                break;
+        case chipcHw_DDR_HW_PHASE_MARGIN_WIDE:
+                ge = 0x01;
+                le = 0x7F;
+                break;
+        }
+
+        {
+                REG_LOCAL_IRQ_SAVE;
+
+                pChipcHw->DDRPhaseCtrl1 &=
+                    ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK <<
+                       chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
+                      || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK <<
+                          chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
+
+                pChipcHw->DDRPhaseCtrl1 |=
+                    ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
+                     || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
+
+                REG_LOCAL_IRQ_RESTORE;
+        }
+}
+
+/****************************************************************************/
+/**
+*  @brief   Set VPM phase alignment margin in hardware
+*
+*/
+/****************************************************************************/
+static inline void
+chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
+{
+        uint32_t ge = 0;
+        uint32_t le = 0;
+
+        switch (margin) {
+        case chipcHw_VPM_HW_PHASE_MARGIN_STRICT:
+                ge = 0x0F;
+                le = 0x0F;
+                break;
+        case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM:
+                ge = 0x03;
+                le = 0x3F;
+                break;
+        case chipcHw_VPM_HW_PHASE_MARGIN_WIDE:
+                ge = 0x01;
+                le = 0x7F;
+                break;
+        }
+
+        {
+                REG_LOCAL_IRQ_SAVE;
+
+                pChipcHw->VPMPhaseCtrl1 &=
+                    ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK <<
+                       chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
+                      || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK <<
+                          chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
+
+                pChipcHw->VPMPhaseCtrl1 |=
+                    ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
+                     || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
+
+                REG_LOCAL_IRQ_RESTORE;
+        }
+}
+
+/****************************************************************************/
+/**
+*  @brief   Checks DDR phase aligned status done by HW
+*
+*  @return  1: When aligned
+*           0: When not aligned
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
+{
+        return (pChipcHw->
+                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Checks VPM phase aligned status done by HW
+*
+*  @return  1: When aligned
+*           0: When not aligned
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
+{
+        return (pChipcHw->
+                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get DDR phase aligned status done by HW
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
+{
+        return (pChipcHw->
+                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
+            chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get VPM phase aligned status done by HW
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
+{
+        return (pChipcHw->
+                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
+            chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get DDR phase control value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getDdrPhaseControl(void)
+{
+        return (pChipcHw->
+                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
+            chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get VPM phase control value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getVpmPhaseControl(void)
+{
+        return (pChipcHw->
+                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
+            chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
+}
+
+/****************************************************************************/
+/**
+*  @brief   DDR phase alignment timeout count
+*
+*  @note    If HW fails to perform the phase alignment, it will trigger
+*           a DDR phase alignment timeout interrupt.
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->DDRPhaseCtrl2 &=
+            ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK <<
+              chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT);
+        pChipcHw->DDRPhaseCtrl2 |=
+            (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) <<
+            chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   VPM phase alignment timeout count
+*
+*  @note    If HW fails to perform the phase alignment, it will trigger
+*           a VPM phase alignment timeout interrupt.
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->VPMPhaseCtrl2 &=
+            ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK <<
+              chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT);
+        pChipcHw->VPMPhaseCtrl2 |=
+            (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) <<
+            chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Clear DDR phase alignment timeout interrupt
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        /* Clear timeout interrupt service bit */
+        pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED;
+        pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Clear VPM phase alignment timeout interrupt
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        /* Clear timeout interrupt service bit */
+        pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED;
+        pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   DDR phase alignment timeout interrupt enable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
+        /* Enable timeout interrupt */
+        pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   VPM phase alignment timeout interrupt enable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
+        /* Enable timeout interrupt */
+        pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   DDR phase alignment timeout interrupt disable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+/****************************************************************************/
+/**
+*  @brief   VPM phase alignment timeout interrupt disable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+
+#endif /* CHIPC_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
new file mode 100644
index 000000000000..b162448f613c
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
@@ -0,0 +1,530 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    chipcHw_reg.h
+*
+*  @brief   Definitions for low level chip control registers
+*
+*/
+/****************************************************************************/
+#ifndef CHIPCHW_REG_H
+#define CHIPCHW_REG_H
+
+#include <mach/csp/mm_io.h>
+#include <csp/reg.h>
+#include <mach/csp/ddrcReg.h>
+
+#define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
+
+typedef struct {
+        uint32_t ChipId;        /* Chip ID */
+        uint32_t DDRClock;      /* PLL1 Channel 1 for DDR clock */
+        uint32_t ARMClock;      /* PLL1 Channel 2 for ARM clock */
+        uint32_t ESWClock;      /* PLL1 Channel 3 for ESW system clock */
+        uint32_t VPMClock;      /* PLL1 Channel 4 for VPM clock */
+        uint32_t ESW125Clock;   /* PLL1 Channel 5 for ESW 125MHz clock */
+        uint32_t UARTClock;     /* PLL1 Channel 6 for UART clock */
+        uint32_t SDIO0Clock;    /* PLL1 Channel 7 for SDIO 0 clock */
+        uint32_t SDIO1Clock;    /* PLL1 Channel 8 for SDIO 1 clock */
+        uint32_t SPIClock;      /* PLL1 Channel 9 for SPI master Clock  */
+        uint32_t ETMClock;      /* PLL1 Channel 10 for ARM ETM Clock  */
+
+        uint32_t ACLKClock;     /* ACLK Clock (Divider) */
+        uint32_t OTPClock;      /* OTP Clock  (Divider) */
+        uint32_t I2CClock;      /* I2C Clock (CK_13m) (Divider) */
+        uint32_t I2S0Clock;     /* I2S0 Clock (Divider) */
+        uint32_t RTBUSClock;    /* RTBUS (DDR PHY Config.) Clock (Divider) */
+        uint32_t pad1;
+        uint32_t APM100Clock;   /* APM 100MHz CLK Clock (Divider) */
+        uint32_t TSCClock;      /* TSC Clock (Divider) */
+        uint32_t LEDClock;      /* LED Clock (Divider) */
+
+        uint32_t USBClock;      /* PLL2 Channel 1 for USB clock */
+        uint32_t LCDClock;      /* PLL2 Channel 2 for LCD clock */
+        uint32_t APMClock;      /* PLL2 Channel 3 for APM 200 MHz clock */
+
+        uint32_t BusIntfClock;  /* Bus interface clock */
+
+        uint32_t PLLStatus;     /* PLL status register (PLL1) */
+        uint32_t PLLConfig;     /* PLL configuration register  (PLL1) */
+        uint32_t PLLPreDivider; /* PLL pre-divider control register (PLL1) */
+        uint32_t PLLDivider;    /* PLL divider control register (PLL1) */
+        uint32_t PLLControl1;   /* PLL analog control register #1 (PLL1) */
+        uint32_t PLLControl2;   /* PLL analog control register #2 (PLL1) */
+
+        uint32_t I2S1Clock;     /* I2S1 Clock  */
+        uint32_t AudioEnable;   /* Enable/ disable audio channel */
+        uint32_t SoftReset1;    /* Reset blocks */
+        uint32_t SoftReset2;    /* Reset blocks */
+        uint32_t Spare1;        /* Phase align interrupts */
+        uint32_t Sticky;        /* Sticky bits */
+        uint32_t MiscCtrl;      /* Misc. control */
+        uint32_t pad3[3];
+
+        uint32_t PLLStatus2;    /* PLL status register (PLL2) */
+        uint32_t PLLConfig2;    /* PLL configuration register  (PLL2) */
+        uint32_t PLLPreDivider2;        /* PLL pre-divider control register (PLL2) */
+        uint32_t PLLDivider2;   /* PLL divider control register (PLL2) */
+        uint32_t PLLControl12;  /* PLL analog control register #1 (PLL2) */
+        uint32_t PLLControl22;  /* PLL analog control register #2 (PLL2) */
+
+        uint32_t DDRPhaseCtrl1; /* DDR Clock Phase Alignment control1 */
+        uint32_t VPMPhaseCtrl1; /* VPM Clock Phase Alignment control1 */
+        uint32_t PhaseAlignStatus;      /* DDR/VPM Clock Phase Alignment Status */
+        uint32_t PhaseCtrlStatus;       /* DDR/VPM Clock HW DDR/VPM ph_ctrl and load_ch Status */
+        uint32_t DDRPhaseCtrl2; /* DDR Clock Phase Alignment control2 */
+        uint32_t VPMPhaseCtrl2; /* VPM Clock Phase Alignment control2 */
+        uint32_t pad4[9];
+
+        uint32_t SoftOTP1;      /* Software OTP control */
+        uint32_t SoftOTP2;      /* Software OTP control */
+        uint32_t SoftStraps;    /* Software strap */
+        uint32_t PinStraps;     /* Pin Straps */
+        uint32_t DiffOscCtrl;   /* Diff oscillator control */
+        uint32_t DiagsCtrl;     /* Diagnostic control */
+        uint32_t DiagsOutputCtrl;       /* Diagnostic output enable */
+        uint32_t DiagsReadBackCtrl;     /* Diagnostic read back control */
+
+        uint32_t LcdPifMode;    /* LCD/PIF Pin Sharing MUX Mode */
+
+        uint32_t GpioMux_0_7;   /* Pin Sharing MUX0 Control */
+        uint32_t GpioMux_8_15;  /* Pin Sharing MUX1 Control */
+        uint32_t GpioMux_16_23; /* Pin Sharing MUX2 Control */
+        uint32_t GpioMux_24_31; /* Pin Sharing MUX3 Control */
+        uint32_t GpioMux_32_39; /* Pin Sharing MUX4 Control */
+        uint32_t GpioMux_40_47; /* Pin Sharing MUX5 Control */
+        uint32_t GpioMux_48_55; /* Pin Sharing MUX6 Control */
+        uint32_t GpioMux_56_63; /* Pin Sharing MUX7 Control */
+
+        uint32_t GpioSR_0_7;    /* Slew rate for GPIO 0 - 7 */
+        uint32_t GpioSR_8_15;   /* Slew rate for GPIO 8 - 15 */
+        uint32_t GpioSR_16_23;  /* Slew rate for GPIO 16 - 23 */
+        uint32_t GpioSR_24_31;  /* Slew rate for GPIO 24 - 31 */
+        uint32_t GpioSR_32_39;  /* Slew rate for GPIO 32 - 39 */
+        uint32_t GpioSR_40_47;  /* Slew rate for GPIO 40 - 47 */
+        uint32_t GpioSR_48_55;  /* Slew rate for GPIO 48 - 55 */
+        uint32_t GpioSR_56_63;  /* Slew rate for GPIO 56 - 63 */
+        uint32_t MiscSR_0_7;    /* Slew rate for MISC 0 - 7 */
+        uint32_t MiscSR_8_15;   /* Slew rate for MISC 8 - 15 */
+
+        uint32_t GpioPull_0_15; /* Pull up registers for GPIO 0 - 15 */
+        uint32_t GpioPull_16_31;        /* Pull up registers for GPIO 16 - 31 */
+        uint32_t GpioPull_32_47;        /* Pull up registers for GPIO 32 - 47 */
+        uint32_t GpioPull_48_63;        /* Pull up registers for GPIO 48 - 63 */
+        uint32_t MiscPull_0_15; /* Pull up registers for MISC 0 - 15 */
+
+        uint32_t GpioInput_0_31;        /* Input type for GPIO 0 - 31 */
+        uint32_t GpioInput_32_63;       /* Input type for GPIO 32 - 63 */
+        uint32_t MiscInput_0_15;        /* Input type for MISC 0 - 16 */
+} chipcHw_REG_t;
+
+#define pChipcHw  ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
+#define pChipcPhysical  ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
+
+#define chipcHw_REG_CHIPID_BASE_MASK                    0xFFFFF000
+#define chipcHw_REG_CHIPID_BASE_SHIFT                   12
+#define chipcHw_REG_CHIPID_REV_MASK                     0x00000FFF
+#define chipcHw_REG_REV_A0                              0xA00
+#define chipcHw_REG_REV_B0                              0x0B0
+
+#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE           0x80000000      /* Allow controlling PLL registers */
+#define chipcHw_REG_PLL_STATUS_LOCKED                   0x00000001      /* PLL is settled */
+#define chipcHw_REG_PLL_CONFIG_D_RESET                  0x00000008      /* Digital reset */
+#define chipcHw_REG_PLL_CONFIG_A_RESET                  0x00000004      /* Analog reset */
+#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE            0x00000020      /* Bypass enable */
+#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE            0x00000010      /* Output enable */
+#define chipcHw_REG_PLL_CONFIG_POWER_DOWN               0x00000001      /* Power down */
+#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ           1600000000      /* 1.6GHz VCO split frequency */
+#define chipcHw_REG_PLL_CONFIG_VCO_800_1600             0x00000000      /* VCO range 800-1600 MHz */
+#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200            0x00000080      /* VCO range 1601-3200 MHz */
+#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE              0x00010000      /* PLL test output enable */
+#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK         0x003E0000      /* Mask to set test values */
+#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT        17
+
+#define chipcHw_REG_PLL_CLOCK_PHASE_COMP                0x00800000      /* Phase comparator output */
+#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK         0x00300000      /* Clock to bus ratio mask */
+#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT        20      /* Number of bits to be shifted */
+#define chipcHw_REG_PLL_CLOCK_POWER_DOWN                0x00080000      /* PLL channel power down */
+#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO               0x00040000      /* Use GPIO as source */
+#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT             0x00020000      /* Select bypass clock */
+#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE             0x00010000      /* Clock gated ON */
+#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE       0x00008000      /* Clock phase update enable */
+#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT       8       /* Number of bits to be shifted */
+#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK        0x00003F00      /* Phase control mask */
+#define chipcHw_REG_PLL_CLOCK_MDIV_MASK                 0x000000FF      /* Clock post divider mask
+
+                                                                           00000000 = divide-by-256
+                                                                           00000001 = divide-by-1
+                                                                           00000010 = divide-by-2
+                                                                           00000011 = divide-by-3
+                                                                           00000100 = divide-by-4
+                                                                           00000101 = divide-by-5
+                                                                           00000110 = divide-by-6
+                                                                           .
+                                                                           .
+                                                                           11111011 = divide-by-251
+                                                                           11111100 = divide-by-252
+                                                                           11111101 = divide-by-253
+                                                                           11111110 = divide-by-254
+                                                                         */
+
+#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER              0x00040000      /* NON-PLL clock source select */
+#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT             0x00020000      /* NON-PLL clock bypass enable */
+#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE             0x00010000      /* NON-PLL clock output enable */
+#define chipcHw_REG_DIV_CLOCK_DIV_MASK                  0x000000FF      /* NON-PLL clock post-divide mask */
+#define chipcHw_REG_DIV_CLOCK_DIV_256                   0x00000000      /* NON-PLL clock post-divide by 256 */
+
+#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT             0
+#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT             4
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT           8
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK            0x0001FF00
+#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN           0x02000000
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK       0x00700000      /* Divider mask */
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER    0x00000000      /* Integer-N Mode */
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT  0x00100000      /* MASH Sigma-Delta Modulator Unit Mode */
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT   0x00200000      /* MFB Sigma-Delta Modulator Unit Mode */
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8   0x00300000      /* MASH Sigma-Delta Modulator 1/8 Mode */
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8    0x00400000      /* MFB Sigma-Delta Modulator 1/8 Mode */
+
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco)          ((vco) / chipcHw_XTAL_FREQ_Hz)
+#define chipcHw_REG_PLL_PREDIVIDER_P1                   1
+#define chipcHw_REG_PLL_PREDIVIDER_P2                   1
+
+#define chipcHw_REG_PLL_DIVIDER_M1DIV                   0x03000000
+#define chipcHw_REG_PLL_DIVIDER_FRAC                    0x00FFFFFF      /* Fractional divider */
+
+#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS               (0x00FFFFFF)    /* To attain spread with max frequency */
+
+#define chipcHw_REG_PLL_DIVIDER_NDIV_f                  0       /* ndiv_frac = chipcHw_REG_PLL_DIVIDER_NDIV_f /
+                                                                   chipcHw_REG_PLL_DIVIDER_FRAC
+                                                                   = 0, when SS is disable
+                                                                 */
+
+#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz)           ((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz)))
+
+#define chipcHw_REG_ACLKClock_CLK_DIV_MASK              0x3
+
+/* System booting strap options */
+#define chipcHw_STRAPS_SOFT_OVERRIDE                    0x00000001      /* Software Strap Override */
+
+#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8         0x00000000      /* 8 bit NAND FLASH Boot */
+#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16         0x00000002      /* 16 bit NOR FLASH Boot */
+#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH         0x00000004      /* Serial FLASH Boot */
+#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16        0x00000006      /* 16 bit NAND FLASH Boot */
+#define chipcHw_STRAPS_BOOT_DEVICE_UART                 0x00000008      /* UART Boot */
+#define chipcHw_STRAPS_BOOT_DEVICE_MASK                 0x0000000E      /* Mask */
+
+/* System boot option */
+#define chipcHw_STRAPS_BOOT_OPTION_BROM                 0x00000000      /* Boot from Boot ROM */
+#define chipcHw_STRAPS_BOOT_OPTION_ARAM                 0x00000020      /* Boot from ARAM */
+#define chipcHw_STRAPS_BOOT_OPTION_NOR                  0x00000030      /* Boot from NOR flash */
+
+/* NAND Flash page size strap options */
+#define chipcHw_STRAPS_NAND_PAGESIZE_512                0x00000000      /* NAND FLASH page size of 512 bytes */
+#define chipcHw_STRAPS_NAND_PAGESIZE_2048               0x00000040      /* NAND FLASH page size of 2048 bytes */
+#define chipcHw_STRAPS_NAND_PAGESIZE_4096               0x00000080      /* NAND FLASH page size of 4096 bytes */
+#define chipcHw_STRAPS_NAND_PAGESIZE_EXT                0x000000C0      /* NAND FLASH page of extened size */
+#define chipcHw_STRAPS_NAND_PAGESIZE_MASK               0x000000C0      /* Mask */
+
+#define chipcHw_STRAPS_NAND_EXTRA_CYCLE                 0x00000400      /* NAND FLASH address cycle configuration */
+#define chipcHw_STRAPS_REBOOT_TO_UART                   0x00000800      /* Reboot to UART on error */
+
+/* Secure boot mode strap options */
+#define chipcHw_STRAPS_BOOT_MODE_NORMAL                 0x00000000      /* Normal Boot */
+#define chipcHw_STRAPS_BOOT_MODE_DBG_SW                 0x00000100      /* Software debugging Boot */
+#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT               0x00000200      /* Boot rom debugging Boot */
+#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET           0x00000300      /* Normal Boot (Quiet BootRom) */
+#define chipcHw_STRAPS_BOOT_MODE_MASK                   0x00000300      /* Mask */
+
+/* Slave Mode straps */
+#define chipcHw_STRAPS_I2CS                             0x02000000      /* I2C Slave  */
+#define chipcHw_STRAPS_SPIS                             0x01000000      /* SPI Slave  */
+
+/* Strap pin options */
+#define chipcHw_REG_SW_STRAPS                           ((pChipcHw->PinStraps & 0x0000FC00) >> 10)
+
+/* PIF/LCD pin sharing defines */
+#define chipcHw_REG_LCD_PIN_ENABLE                      0x00000001      /* LCD Controller is used and the pins have LCD functions */
+#define chipcHw_REG_PIF_PIN_ENABLE                      0x00000002      /* LCD pins are used to perform PIF functions  */
+
+#define chipcHw_GPIO_COUNT                              61      /* Number of GPIO pin accessible thorugh CHIPC */
+
+/* NOTE: Any changes to these constants will require a corresponding change to chipcHw_str.c */
+#define chipcHw_REG_GPIO_MUX_KEYPAD                     0x00000001      /* GPIO mux for Keypad */
+#define chipcHw_REG_GPIO_MUX_I2CH                       0x00000002      /* GPIO mux for I2CH */
+#define chipcHw_REG_GPIO_MUX_SPI                        0x00000003      /* GPIO mux for SPI */
+#define chipcHw_REG_GPIO_MUX_UART                       0x00000004      /* GPIO mux for UART */
+#define chipcHw_REG_GPIO_MUX_LEDMTXP                    0x00000005      /* GPIO mux for LEDMTXP */
+#define chipcHw_REG_GPIO_MUX_LEDMTXS                    0x00000006      /* GPIO mux for LEDMTXS */
+#define chipcHw_REG_GPIO_MUX_SDIO0                      0x00000007      /* GPIO mux for SDIO0 */
+#define chipcHw_REG_GPIO_MUX_SDIO1                      0x00000008      /* GPIO mux for SDIO1 */
+#define chipcHw_REG_GPIO_MUX_PCM                        0x00000009      /* GPIO mux for PCM */
+#define chipcHw_REG_GPIO_MUX_I2S                        0x0000000A      /* GPIO mux for I2S */
+#define chipcHw_REG_GPIO_MUX_ETM                        0x0000000B      /* GPIO mux for ETM */
+#define chipcHw_REG_GPIO_MUX_DEBUG                      0x0000000C      /* GPIO mux for DEBUG */
+#define chipcHw_REG_GPIO_MUX_MISC                       0x0000000D      /* GPIO mux for MISC */
+#define chipcHw_REG_GPIO_MUX_GPIO                       0x00000000      /* GPIO mux for GPIO */
+#define chipcHw_REG_GPIO_MUX(pin)                       (&pChipcHw->GpioMux_0_7 + ((pin) >> 3))
+#define chipcHw_REG_GPIO_MUX_POSITION(pin)              (((pin) & 0x00000007) << 2)
+#define chipcHw_REG_GPIO_MUX_MASK                       0x0000000F      /* Mask */
+
+#define chipcHw_REG_SLEW_RATE_HIGH                      0x00000000      /* High speed slew rate */
+#define chipcHw_REG_SLEW_RATE_NORMAL                    0x00000008      /* Normal slew rate */
+                                                        /* Pins beyond 42 are defined by skipping 8 bits within the register */
+#define chipcHw_REG_SLEW_RATE(pin)                      (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
+#define chipcHw_REG_SLEW_RATE_POSITION(pin)             (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
+#define chipcHw_REG_SLEW_RATE_MASK                      0x00000008      /* Mask */
+
+#define chipcHw_REG_CURRENT_STRENGTH_2mA                0x00000001      /* Current driving strength 2 milli ampere */
+#define chipcHw_REG_CURRENT_STRENGTH_4mA                0x00000002      /* Current driving strength 4 milli ampere */
+#define chipcHw_REG_CURRENT_STRENGTH_6mA                0x00000004      /* Current driving strength 6 milli ampere */
+#define chipcHw_REG_CURRENT_STRENGTH_8mA                0x00000005      /* Current driving strength 8 milli ampere */
+#define chipcHw_REG_CURRENT_STRENGTH_10mA               0x00000006      /* Current driving strength 10 milli ampere */
+#define chipcHw_REG_CURRENT_STRENGTH_12mA               0x00000007      /* Current driving strength 12 milli ampere */
+#define chipcHw_REG_CURRENT_MASK                        0x00000007      /* Mask */
+                                                        /* Pins beyond 42 are defined by skipping 8 bits */
+#define chipcHw_REG_CURRENT(pin)                        (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
+#define chipcHw_REG_CURRENT_POSITION(pin)               (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
+
+#define chipcHw_REG_PULL_NONE                           0x00000000      /* No pull up register */
+#define chipcHw_REG_PULL_UP                             0x00000001      /* Pull up register enable */
+#define chipcHw_REG_PULL_DOWN                           0x00000002      /* Pull down register enable */
+#define chipcHw_REG_PULLUP_MASK                         0x00000003      /* Mask */
+                                                        /* Pins beyond 42 are defined by skipping 4 bits */
+#define chipcHw_REG_PULLUP(pin)                         (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChipcHw->GpioPull_0_15 + ((pin) >> 4)))
+#define chipcHw_REG_PULLUP_POSITION(pin)                (((pin) > 42) ? ((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1))
+
+#define chipcHw_REG_INPUTTYPE_CMOS                      0x00000000      /* Normal CMOS logic */
+#define chipcHw_REG_INPUTTYPE_ST                        0x00000001      /* High speed Schmitt Trigger */
+#define chipcHw_REG_INPUTTYPE_MASK                      0x00000001      /* Mask */
+                                                        /* Pins beyond 42 are defined by skipping 2 bits */
+#define chipcHw_REG_INPUTTYPE(pin)                      (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&pChipcHw->GpioInput_0_31 + ((pin) >> 5)))
+#define chipcHw_REG_INPUTTYPE_POSITION(pin)             (((pin) > 42) ? ((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F)))
+
+/* Device connected to the bus clock */
+#define chipcHw_REG_BUS_CLOCK_ARM                       0x00000001      /* Bus interface clock for ARM */
+#define chipcHw_REG_BUS_CLOCK_VDEC                      0x00000002      /* Bus interface clock for VDEC */
+#define chipcHw_REG_BUS_CLOCK_ARAM                      0x00000004      /* Bus interface clock for ARAM */
+#define chipcHw_REG_BUS_CLOCK_HPM                       0x00000008      /* Bus interface clock for HPM */
+#define chipcHw_REG_BUS_CLOCK_DDRC                      0x00000010      /* Bus interface clock for DDRC */
+#define chipcHw_REG_BUS_CLOCK_DMAC0                     0x00000020      /* Bus interface clock for DMAC0 */
+#define chipcHw_REG_BUS_CLOCK_DMAC1                     0x00000040      /* Bus interface clock for DMAC1 */
+#define chipcHw_REG_BUS_CLOCK_NVI                       0x00000080      /* Bus interface clock for NVI */
+#define chipcHw_REG_BUS_CLOCK_ESW                       0x00000100      /* Bus interface clock for ESW */
+#define chipcHw_REG_BUS_CLOCK_GE                        0x00000200      /* Bus interface clock for GE */
+#define chipcHw_REG_BUS_CLOCK_I2CH                      0x00000400      /* Bus interface clock for I2CH */
+#define chipcHw_REG_BUS_CLOCK_I2S0                      0x00000800      /* Bus interface clock for I2S0 */
+#define chipcHw_REG_BUS_CLOCK_I2S1                      0x00001000      /* Bus interface clock for I2S1 */
+#define chipcHw_REG_BUS_CLOCK_VRAM                      0x00002000      /* Bus interface clock for VRAM */
+#define chipcHw_REG_BUS_CLOCK_CLCD                      0x00004000      /* Bus interface clock for CLCD */
+#define chipcHw_REG_BUS_CLOCK_LDK                       0x00008000      /* Bus interface clock for LDK */
+#define chipcHw_REG_BUS_CLOCK_LED                       0x00010000      /* Bus interface clock for LED */
+#define chipcHw_REG_BUS_CLOCK_OTP                       0x00020000      /* Bus interface clock for OTP */
+#define chipcHw_REG_BUS_CLOCK_PIF                       0x00040000      /* Bus interface clock for PIF */
+#define chipcHw_REG_BUS_CLOCK_SPU                       0x00080000      /* Bus interface clock for SPU */
+#define chipcHw_REG_BUS_CLOCK_SDIO0                     0x00100000      /* Bus interface clock for SDIO0 */
+#define chipcHw_REG_BUS_CLOCK_SDIO1                     0x00200000      /* Bus interface clock for SDIO1 */
+#define chipcHw_REG_BUS_CLOCK_SPIH                      0x00400000      /* Bus interface clock for SPIH */
+#define chipcHw_REG_BUS_CLOCK_SPIS                      0x00800000      /* Bus interface clock for SPIS */
+#define chipcHw_REG_BUS_CLOCK_UART0                     0x01000000      /* Bus interface clock for UART0 */
+#define chipcHw_REG_BUS_CLOCK_UART1                     0x02000000      /* Bus interface clock for UART1 */
+#define chipcHw_REG_BUS_CLOCK_BBL                       0x04000000      /* Bus interface clock for BBL */
+#define chipcHw_REG_BUS_CLOCK_I2CS                      0x08000000      /* Bus interface clock for I2CS */
+#define chipcHw_REG_BUS_CLOCK_USBH                      0x10000000      /* Bus interface clock for USB Host */
+#define chipcHw_REG_BUS_CLOCK_USBD                      0x20000000      /* Bus interface clock for USB Device */
+#define chipcHw_REG_BUS_CLOCK_BROM                      0x40000000      /* Bus interface clock for Boot ROM */
+#define chipcHw_REG_BUS_CLOCK_TSC                       0x80000000      /* Bus interface clock for Touch screen */
+
+/* Software resets defines */
+#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD          0x0000000080000000ULL   /* Reset Global VPM and hold */
+#define chipcHw_REG_SOFT_RESET_VPM_HOLD                 0x0000000040000000ULL   /* Reset VPM and hold */
+#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL               0x0000000020000000ULL   /* Reset Global VPM */
+#define chipcHw_REG_SOFT_RESET_VPM                      0x0000000010000000ULL   /* Reset VPM */
+#define chipcHw_REG_SOFT_RESET_KEYPAD                   0x0000000008000000ULL   /* Reset Key pad */
+#define chipcHw_REG_SOFT_RESET_LED                      0x0000000004000000ULL   /* Reset LED */
+#define chipcHw_REG_SOFT_RESET_SPU                      0x0000000002000000ULL   /* Reset SPU */
+#define chipcHw_REG_SOFT_RESET_RNG                      0x0000000001000000ULL   /* Reset RNG */
+#define chipcHw_REG_SOFT_RESET_PKA                      0x0000000000800000ULL   /* Reset PKA */
+#define chipcHw_REG_SOFT_RESET_LCD                      0x0000000000400000ULL   /* Reset LCD */
+#define chipcHw_REG_SOFT_RESET_PIF                      0x0000000000200000ULL   /* Reset PIF */
+#define chipcHw_REG_SOFT_RESET_I2CS                     0x0000000000100000ULL   /* Reset I2C Slave */
+#define chipcHw_REG_SOFT_RESET_I2CH                     0x0000000000080000ULL   /* Reset I2C Host */
+#define chipcHw_REG_SOFT_RESET_SDIO1                    0x0000000000040000ULL   /* Reset SDIO 1 */
+#define chipcHw_REG_SOFT_RESET_SDIO0                    0x0000000000020000ULL   /* Reset SDIO 0 */
+#define chipcHw_REG_SOFT_RESET_BBL                      0x0000000000010000ULL   /* Reset BBL */
+#define chipcHw_REG_SOFT_RESET_I2S1                     0x0000000000008000ULL   /* Reset I2S1 */
+#define chipcHw_REG_SOFT_RESET_I2S0                     0x0000000000004000ULL   /* Reset I2S0 */
+#define chipcHw_REG_SOFT_RESET_SPIS                     0x0000000000002000ULL   /* Reset SPI Slave */
+#define chipcHw_REG_SOFT_RESET_SPIH                     0x0000000000001000ULL   /* Reset SPI Host */
+#define chipcHw_REG_SOFT_RESET_GPIO1                    0x0000000000000800ULL   /* Reset GPIO block 1 */
+#define chipcHw_REG_SOFT_RESET_GPIO0                    0x0000000000000400ULL   /* Reset GPIO block 0 */
+#define chipcHw_REG_SOFT_RESET_UART1                    0x0000000000000200ULL   /* Reset UART 1 */
+#define chipcHw_REG_SOFT_RESET_UART0                    0x0000000000000100ULL   /* Reset UART 0 */
+#define chipcHw_REG_SOFT_RESET_NVI                      0x0000000000000080ULL   /* Reset NVI */
+#define chipcHw_REG_SOFT_RESET_WDOG                     0x0000000000000040ULL   /* Reset Watch dog */
+#define chipcHw_REG_SOFT_RESET_TMR                      0x0000000000000020ULL   /* Reset Timer */
+#define chipcHw_REG_SOFT_RESET_ETM                      0x0000000000000010ULL   /* Reset ETM */
+#define chipcHw_REG_SOFT_RESET_ARM_HOLD                 0x0000000000000008ULL   /* Reset ARM and HOLD */
+#define chipcHw_REG_SOFT_RESET_ARM                      0x0000000000000004ULL   /* Reset ARM */
+#define chipcHw_REG_SOFT_RESET_CHIP_WARM                0x0000000000000002ULL   /* Chip warm reset */
+#define chipcHw_REG_SOFT_RESET_CHIP_SOFT                0x0000000000000001ULL   /* Chip soft reset */
+#define chipcHw_REG_SOFT_RESET_VDEC                     0x0000100000000000ULL   /* Video decoder */
+#define chipcHw_REG_SOFT_RESET_GE                       0x0000080000000000ULL   /* Graphics engine */
+#define chipcHw_REG_SOFT_RESET_OTP                      0x0000040000000000ULL   /* Reset OTP */
+#define chipcHw_REG_SOFT_RESET_USB2                     0x0000020000000000ULL   /* Reset USB2 */
+#define chipcHw_REG_SOFT_RESET_USB1                     0x0000010000000000ULL   /* Reset USB 1 */
+#define chipcHw_REG_SOFT_RESET_USB                      0x0000008000000000ULL   /* Reset USB 1 and USB2 soft reset */
+#define chipcHw_REG_SOFT_RESET_ESW                      0x0000004000000000ULL   /* Reset Ethernet switch */
+#define chipcHw_REG_SOFT_RESET_ESWCLK                   0x0000002000000000ULL   /* Reset Ethernet switch clock */
+#define chipcHw_REG_SOFT_RESET_DDRPHY                   0x0000001000000000ULL   /* Reset DDR Physical */
+#define chipcHw_REG_SOFT_RESET_DDR                      0x0000000800000000ULL   /* Reset DDR Controller */
+#define chipcHw_REG_SOFT_RESET_TSC                      0x0000000400000000ULL   /* Reset Touch screen */
+#define chipcHw_REG_SOFT_RESET_PCM                      0x0000000200000000ULL   /* Reset PCM device */
+#define chipcHw_REG_SOFT_RESET_APM                      0x0000200100000000ULL   /* Reset APM device */
+
+#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD        0x8000000000000000ULL   /* Unhold Global VPM */
+#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD               0x4000000000000000ULL   /* Unhold VPM */
+#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD               0x2000000000000000ULL   /* Unhold ARM reset  */
+#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK              0xF000000000000000ULL   /* Mask to handle unhold request */
+
+/* Audio channel control defines */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL            0x00000001      /* Enable all audio channel */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A              0x00000002      /* Enable channel A */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B              0x00000004      /* Enable channel B */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C              0x00000008      /* Enable channel C */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK      0x00000010      /* Enable NTP clock */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK     0x00000020      /* Enable PCM0 clock */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK     0x00000040      /* Enable PCM1 clock */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK      0x00000080      /* Enable APM clock */
+
+/* Misc. chip control defines */
+#define chipcHw_REG_MISC_CTRL_GE_SEL                    0x00040000      /* Select GE2/GE3 */
+#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP         0x00000000      /* Use on chip clock for I2S1 */
+#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO           0x00020000      /* Use external clock via GPIO pin 26 for I2S1 */
+#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP         0x00000000      /* Use on chip clock for I2S0 */
+#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO           0x00010000      /* Use external clock via GPIO pin 45 for I2S0 */
+#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE          0x00008000      /* Disable ARM CP15 bit */
+#define chipcHw_REG_MISC_CTRL_RTC_DISABLE               0x00000008      /* Disable RTC registers */
+#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE             0x00000004      /* Disable Battery Backed RAM */
+#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST             0x00000002      /* Set USB as host */
+#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE           0xFFFFFFFD      /* Set USB as device */
+#define chipcHw_REG_MISC_CTRL_USB_POWERON               0xFFFFFFFE      /* Power up USB */
+#define chipcHw_REG_MISC_CTRL_USB_POWEROFF              0x00000001      /* Power down USB */
+
+/* OTP configuration defines */
+#define chipcHw_REG_OTP_SECURITY_OFF                    0x0000020000000000ULL   /* Security support is OFF */
+#define chipcHw_REG_OTP_SPU_SLOW                        0x0000010000000000ULL   /* Limited SPU throughput */
+#define chipcHw_REG_OTP_LCD_SPEED                       0x0000000600000000ULL   /* Set VPM speed one */
+#define chipcHw_REG_OTP_VPM_SPEED_1                     0x0000000100000000ULL   /* Set VPM speed one */
+#define chipcHw_REG_OTP_VPM_SPEED_0                     0x0000000080000000ULL   /* Set VPM speed zero */
+#define chipcHw_REG_OTP_AXI_SPEED                       0x0000000060000000ULL   /* Set maximum AXI bus speed */
+#define chipcHw_REG_OTP_APM_DISABLE                     0x000000001F000000ULL   /* Disable APM */
+#define chipcHw_REG_OTP_PIF_DISABLE                     0x0000000000200000ULL   /* Disable PIF */
+#define chipcHw_REG_OTP_VDEC_DISABLE                    0x0000000000100000ULL   /* Disable Video decoder */
+#define chipcHw_REG_OTP_BBL_DISABLE                     0x0000000000080000ULL   /* Disable RTC and BBRAM */
+#define chipcHw_REG_OTP_LED_DISABLE                     0x0000000000040000ULL   /* Disable LED */
+#define chipcHw_REG_OTP_GE_DISABLE                      0x0000000000020000ULL   /* Disable Graphics Engine */
+#define chipcHw_REG_OTP_LCD_DISABLE                     0x0000000000010000ULL   /* Disable LCD */
+#define chipcHw_REG_OTP_KEYPAD_DISABLE                  0x0000000000008000ULL   /* Disable keypad */
+#define chipcHw_REG_OTP_UART_DISABLE                    0x0000000000004000ULL   /* Disable UART */
+#define chipcHw_REG_OTP_SDIOH_DISABLE                   0x0000000000003000ULL   /* Disable SDIO host */
+#define chipcHw_REG_OTP_HSS_DISABLE                     0x0000000000000C00ULL   /* Disable HSS */
+#define chipcHw_REG_OTP_TSC_DISABLE                     0x0000000000000200ULL   /* Disable touch screen */
+#define chipcHw_REG_OTP_USB_DISABLE                     0x0000000000000180ULL   /* Disable USB */
+#define chipcHw_REG_OTP_SGMII_DISABLE                   0x0000000000000060ULL   /* Disable SGMII */
+#define chipcHw_REG_OTP_ETH_DISABLE                     0x0000000000000018ULL   /* Disable gigabit ethernet */
+#define chipcHw_REG_OTP_ETH_PHY_DISABLE                 0x0000000000000006ULL   /* Disable ethernet PHY */
+#define chipcHw_REG_OTP_VPM_DISABLE                     0x0000000000000001ULL   /* Disable VPM */
+
+/* Sticky bit defines */
+#define chipcHw_REG_STICKY_BOOT_DONE                    0x00000001      /* Boot done */
+#define chipcHw_REG_STICKY_SOFT_RESET                   0x00000002      /* ARM soft reset */
+#define chipcHw_REG_STICKY_GENERAL_1                    0x00000004      /* General purpose bit 1 */
+#define chipcHw_REG_STICKY_GENERAL_2                    0x00000008      /* General purpose bit 2 */
+#define chipcHw_REG_STICKY_GENERAL_3                    0x00000010      /* General purpose bit 3 */
+#define chipcHw_REG_STICKY_GENERAL_4                    0x00000020      /* General purpose bit 4 */
+#define chipcHw_REG_STICKY_GENERAL_5                    0x00000040      /* General purpose bit 5 */
+#define chipcHw_REG_STICKY_POR_BROM                     0x00000080      /* Special sticky bit for security - set in BROM to avoid other modes being entered */
+#define chipcHw_REG_STICKY_ARM_RESET                    0x00000100      /* ARM reset */
+#define chipcHw_REG_STICKY_CHIP_SOFT_RESET              0x00000200      /* Chip soft reset */
+#define chipcHw_REG_STICKY_CHIP_WARM_RESET              0x00000400      /* Chip warm reset */
+#define chipcHw_REG_STICKY_WDOG_RESET                   0x00000800      /* Watchdog reset */
+#define chipcHw_REG_STICKY_OTP_RESET                    0x00001000      /* OTP reset */
+
+                                                        /* HW phase alignment defines *//* Spare1 register definitions */
+#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE        0x80000000      /* Enable DDR phase align panic interrupt */
+#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE        0x40000000      /* Enable VPM phase align panic interrupt */
+#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE        0x00000002      /* Enable access to VPM using system BUS */
+#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE        0x00000001      /* Enable access to DDR using system BUS */
+                                                        /* DDRPhaseCtrl1 register definitions */
+#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE            0x80000000      /* Enable DDR SW phase alignment */
+#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE            0x40000000      /* Enable DDR HW phase alignment */
+#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK             0x0000007F      /* DDR lower threshold for phase alignment */
+#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT            23
+#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK             0x0000007F      /* DDR upper threshold for phase alignment */
+#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT            16
+#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF      /* BUS Cycle to wait to run next DDR phase alignment */
+#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
+                                                        /* VPMPhaseCtrl1 register definitions */
+#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE            0x80000000      /* Enable VPM SW phase alignment */
+#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE            0x40000000      /* Enable VPM HW phase alignment */
+#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK             0x0000007F      /* VPM lower threshold for phase alignment */
+#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT            23
+#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK             0x0000007F      /* VPM upper threshold for phase alignment */
+#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT            16
+#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF      /* BUS Cycle to wait to complete the VPM phase alignment */
+#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
+                                                        /* PhaseAlignStatus register definitions */
+#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS             0x80000000      /* DDR time out interrupt status */
+#define chipcHw_REG_DDR_PHASE_STATUS_MASK               0x0000007F      /* DDR phase status value */
+#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT              24
+#define chipcHw_REG_DDR_PHASE_ALIGNED                   0x00800000      /* DDR Phase aligned status */
+#define chipcHw_REG_DDR_LOAD                            0x00400000      /* Load DDR phase status */
+#define chipcHw_REG_DDR_PHASE_CTRL_MASK                 0x0000003F      /* DDR phase control value */
+#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT                16
+#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS             0x80000000      /* VPM time out interrupt status */
+#define chipcHw_REG_VPM_PHASE_STATUS_MASK               0x0000007F      /* VPM phase status value */
+#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT              8
+#define chipcHw_REG_VPM_PHASE_ALIGNED                   0x00000080      /* VPM Phase aligned status */
+#define chipcHw_REG_VPM_LOAD                            0x00000040      /* Load VPM phase status */
+#define chipcHw_REG_VPM_PHASE_CTRL_MASK                 0x0000003F      /* VPM phase control value */
+#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT                0
+                                                        /* DDRPhaseCtrl2 register definitions */
+#define chipcHw_REG_DDR_INTR_SERVICED                   0x02000000      /* Acknowledge that interrupt was serviced */
+#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE             0x01000000      /* Enable time out interrupt */
+#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F      /* Wait before toggling load_ch */
+#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT     20
+#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F      /* Total wait to settle ph_ctrl and load_ch */
+#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
+#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF      /* Time out value for DDR HW phase alignment */
+#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT       0
+                                                        /* VPMPhaseCtrl2 register definitions */
+#define chipcHw_REG_VPM_INTR_SELECT_MASK                0x00000003      /* Interrupt select */
+#define chipcHw_REG_VPM_INTR_SELECT_SHIFT               26
+#define chipcHw_REG_VPM_INTR_DISABLE                    0x00000000
+#define chipcHw_REG_VPM_INTR_FAST                       (0x1 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
+#define chipcHw_REG_VPM_INTR_MEDIUM                     (0x2 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
+#define chipcHw_REG_VPM_INTR_SLOW                       (0x3 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
+#define chipcHw_REG_VPM_INTR_SERVICED                   0x02000000      /* Acknowledge that interrupt was serviced */
+#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE             0x01000000      /* Enable time out interrupt */
+#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F      /* Wait before toggling load_ch */
+#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT     20
+#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F      /* Total wait cycle to settle ph_ctrl and load_ch */
+#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
+#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF      /* Time out value for VPM HW phase alignment */
+#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT       0
+
+#endif /* CHIPCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
new file mode 100644
index 000000000000..f1b68e26fa6d
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
@@ -0,0 +1,872 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    ddrcReg.h
+*
+*  @brief   Register definitions for BCMRING DDR2 Controller and PHY
+*
+*/
+/****************************************************************************/
+
+#ifndef DDRC_REG_H
+#define DDRC_REG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#include <csp/reg.h>
+#include <csp/stdint.h>
+
+#include <mach/csp/mm_io.h>
+
+/* ---- Public Constants and Types --------------------------------------- */
+
+/*********************************************************************/
+/* DDR2 Controller (ARM PL341) register definitions */
+/*********************************************************************/
+
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+/* ARM PL341 DDR2 configuration registers, offset 0x000 */
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+
+        typedef struct {
+                uint32_t memcStatus;
+                uint32_t memcCmd;
+                uint32_t directCmd;
+                uint32_t memoryCfg;
+                uint32_t refreshPrd;
+                uint32_t casLatency;
+                uint32_t writeLatency;
+                uint32_t tMrd;
+                uint32_t tRas;
+                uint32_t tRc;
+                uint32_t tRcd;
+                uint32_t tRfc;
+                uint32_t tRp;
+                uint32_t tRrd;
+                uint32_t tWr;
+                uint32_t tWtr;
+                uint32_t tXp;
+                uint32_t tXsr;
+                uint32_t tEsr;
+                uint32_t memoryCfg2;
+                uint32_t memoryCfg3;
+                uint32_t tFaw;
+        } ddrcReg_CTLR_MEMC_REG_t;
+
+#define ddrcReg_CTLR_MEMC_REG_OFFSET                    0x0000
+#define ddrcReg_CTLR_MEMC_REGP                          ((volatile ddrcReg_CTLR_MEMC_REG_t *)  (MM_IO_BASE_DDRC + ddrcReg_CTLR_MEMC_REG_OFFSET))
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK             (0x3 << 12)
+#define ddrcReg_CTLR_MEMC_STATUS_BANKS_4                (0x0 << 12)
+#define ddrcReg_CTLR_MEMC_STATUS_BANKS_8                (0x3 << 12)
+
+#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK          (0x3 << 10)
+#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0             (0x0 << 10)
+#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1             (0x1 << 10)
+#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2             (0x2 << 10)
+#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4             (0x3 << 10)
+
+#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK             (0x3 << 7)
+#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1                (0x0 << 7)
+#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2                (0x1 << 7)
+#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3                (0x2 << 7)
+#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4                (0x3 << 7)
+
+#define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK              (0x7 << 4)
+#define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2              (0x5 << 4)
+
+#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK             (0x3 << 2)
+#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16               (0x0 << 2)
+#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32               (0x1 << 2)
+#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64               (0x2 << 2)
+#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128              (0x3 << 2)
+
+#define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK             (0x3 << 0)
+#define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG           (0x0 << 0)
+#define ddrcReg_CTLR_MEMC_STATUS_STATE_READY            (0x1 << 0)
+#define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED           (0x2 << 0)
+#define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR           (0x3 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_MEMC_CMD_MASK                      (0x7 << 0)
+#define ddrcReg_CTLR_MEMC_CMD_GO                        (0x0 << 0)
+#define ddrcReg_CTLR_MEMC_CMD_SLEEP                     (0x1 << 0)
+#define ddrcReg_CTLR_MEMC_CMD_WAKEUP                    (0x2 << 0)
+#define ddrcReg_CTLR_MEMC_CMD_PAUSE                     (0x3 << 0)
+#define ddrcReg_CTLR_MEMC_CMD_CONFIGURE                 (0x4 << 0)
+#define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE              (0x7 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT              20
+#define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK               (0x3 << ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT)
+
+#define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL       (0x0 << 18)
+#define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH        (0x1 << 18)
+#define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG            (0x2 << 18)
+#define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP                (0x3 << 18)
+
+#define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT              16
+#define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK               (0x3 << ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT)
+
+#define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT              0
+#define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK               (0x1ffff << ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK           (0x3 << 21)
+#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1              (0x0 << 21)
+#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2              (0x1 << 21)
+#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3              (0x2 << 21)
+#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4              (0x3 << 21)
+
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK           (0x7 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0            (0x0 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1            (0x1 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2            (0x2 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3            (0x3 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4            (0x4 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5            (0x5 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6            (0x6 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7           (0x7 << 18)
+
+#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK          (0x7 << 15)
+#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4             (0x2 << 15)
+#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8             (0x3 << 15)     /* @note Not supported in PL341 */
+
+#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE          (0x1 << 13)
+
+#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT    7
+#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK     (0x3f << ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT)
+
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK       (0x7 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11         (0x0 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12         (0x1 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13         (0x2 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14         (0x3 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15         (0x4 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16         (0x5 << 3)
+
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK       (0x7 << 0)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9          (0x1 << 0)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10         (0x2 << 0)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11         (0x3 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_REFRESH_PRD_SHIFT                  0
+#define ddrcReg_CTLR_REFRESH_PRD_MASK                   (0x7fff << ddrcReg_CTLR_REFRESH_PRD_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_CAS_LATENCY_SHIFT                  1
+#define ddrcReg_CTLR_CAS_LATENCY_MASK                   (0x7 << ddrcReg_CTLR_CAS_LATENCY_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_WRITE_LATENCY_SHIFT                0
+#define ddrcReg_CTLR_WRITE_LATENCY_MASK                 (0x7 << ddrcReg_CTLR_WRITE_LATENCY_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_T_MRD_SHIFT                        0
+#define ddrcReg_CTLR_T_MRD_MASK                         (0x7f << ddrcReg_CTLR_T_MRD_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_T_RAS_SHIFT                        0
+#define ddrcReg_CTLR_T_RAS_MASK                         (0x1f << ddrcReg_CTLR_T_RAS_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_T_RC_SHIFT                         0
+#define ddrcReg_CTLR_T_RC_MASK                          (0x1f << ddrcReg_CTLR_T_RC_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT         8
+#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK          (0x7 << ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT)
+
+#define ddrcReg_CTLR_T_RCD_SHIFT                        0
+#define ddrcReg_CTLR_T_RCD_MASK                         (0x7 << ddrcReg_CTLR_T_RCD_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT         8
+#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK          (0x7f << ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT)
+
+#define ddrcReg_CTLR_T_RFC_SHIFT                        0
+#define ddrcReg_CTLR_T_RFC_MASK                         (0x7f << ddrcReg_CTLR_T_RFC_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT          8
+#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK           (0x7 << ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT)
+
+#define ddrcReg_CTLR_T_RP_SHIFT                         0
+#define ddrcReg_CTLR_T_RP_MASK                          (0xf << ddrcReg_CTLR_T_RP_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_T_RRD_SHIFT                        0
+#define ddrcReg_CTLR_T_RRD_MASK                         (0xf << ddrcReg_CTLR_T_RRD_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_T_WR_SHIFT                         0
+#define ddrcReg_CTLR_T_WR_MASK                          (0x7 << ddrcReg_CTLR_T_WR_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_T_WTR_SHIFT                        0
+#define ddrcReg_CTLR_T_WTR_MASK                         (0x7 << ddrcReg_CTLR_T_WTR_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_T_XP_SHIFT                         0
+#define ddrcReg_CTLR_T_XP_MASK                          (0xff << ddrcReg_CTLR_T_XP_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_T_XSR_SHIFT                        0
+#define ddrcReg_CTLR_T_XSR_MASK                         (0xff << ddrcReg_CTLR_T_XSR_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_T_ESR_SHIFT                        0
+#define ddrcReg_CTLR_T_ESR_MASK                         (0xff << ddrcReg_CTLR_T_ESR_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK             (0x3 << 6)
+#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS           (0 << 6)
+#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS           (1 << 6)
+#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS           (2 << 6)
+
+#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK     (0x3 << 4)
+#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2        (0 << 4)
+#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3        (3 << 4)
+
+#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW     (0 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH    (1 << 3)
+
+#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW     (0 << 2)
+#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH    (1 << 2)
+
+#define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK               (0x3 << 0)
+#define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC              (0 << 0)
+#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M        (1 << 0)
+#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M        (3 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT       0
+#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK        (0x7 << ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT         8
+#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK          (0x1f << ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT)
+
+#define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT                 0
+#define ddrcReg_CTLR_T_FAW_PERIOD_MASK                  (0x1f << ddrcReg_CTLR_T_FAW_PERIOD_SHIFT)
+
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+/* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+
+#define ddrcReg_CTLR_QOS_CNT                            16
+#define ddrcReg_CTLR_QOS_MAX                            (ddrcReg_CTLR_QOS_CNT - 1)
+
+        typedef struct {
+                uint32_t cfg[ddrcReg_CTLR_QOS_CNT];
+        } ddrcReg_CTLR_QOS_REG_t;
+
+#define ddrcReg_CTLR_QOS_REG_OFFSET                     0x100
+#define ddrcReg_CTLR_QOS_REGP                           ((volatile ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET))
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT                  2
+#define ddrcReg_CTLR_QOS_CFG_MAX_MASK                   (0xff << ddrcReg_CTLR_QOS_CFG_MAX_SHIFT)
+
+#define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT                  1
+#define ddrcReg_CTLR_QOS_CFG_MIN_MASK                   (1 << ddrcReg_CTLR_QOS_CFG_MIN_SHIFT)
+
+#define ddrcReg_CTLR_QOS_CFG_ENABLE                     (1 << 0)
+
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+/* ARM PL341 Memory chip configuration registers, offset 0x200 */
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+
+#define ddrcReg_CTLR_CHIP_CNT                           4
+#define ddrcReg_CTLR_CHIP_MAX                           (ddrcReg_CTLR_CHIP_CNT - 1)
+
+        typedef struct {
+                uint32_t cfg[ddrcReg_CTLR_CHIP_CNT];
+        } ddrcReg_CTLR_CHIP_REG_t;
+
+#define ddrcReg_CTLR_CHIP_REG_OFFSET                    0x200
+#define ddrcReg_CTLR_CHIP_REGP                          ((volatile ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET))
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK              (1 << 16)
+#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL      (0 << 16)
+#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL      (1 << 16)
+
+#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT      8
+#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK       (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT)
+
+#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT       0
+#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK        (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT)
+
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+/* ARM PL341 User configuration registers, offset 0x300 */
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+
+#define ddrcReg_CTLR_USER_OUTPUT_CNT                    2
+
+        typedef struct {
+                uint32_t input;
+                uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT];
+                uint32_t feature;
+        } ddrcReg_CTLR_USER_REG_t;
+
+#define ddrcReg_CTLR_USER_REG_OFFSET                    0x300
+#define ddrcReg_CTLR_USER_REGP                          ((volatile ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET))
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT            0
+#define ddrcReg_CTLR_USER_INPUT_STATUS_MASK             (0xff << ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT              0
+#define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK               (0xff << ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT)
+
+#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT      1
+#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK       (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
+#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134      (0 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
+#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301      (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
+#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE        (1 << 2)
+#define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE    (1 << 0)
+
+/*********************************************************************/
+/* Broadcom DDR23 PHY register definitions */
+/*********************************************************************/
+
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+/* Broadcom DDR23 PHY Address and Control register definitions */
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+
+        typedef struct {
+                uint32_t revision;
+                uint32_t pmCtl;
+                 REG32_RSVD(0x0008, 0x0010);
+                uint32_t pllStatus;
+                uint32_t pllCfg;
+                uint32_t pllPreDiv;
+                uint32_t pllDiv;
+                uint32_t pllCtl1;
+                uint32_t pllCtl2;
+                uint32_t ssCtl;
+                uint32_t ssCfg;
+                uint32_t vdlStatic;
+                uint32_t vdlDynamic;
+                uint32_t padIdle;
+                uint32_t pvtComp;
+                uint32_t padDrive;
+                uint32_t clkRgltrCtl;
+        } ddrcReg_PHY_ADDR_CTL_REG_t;
+
+#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET                 0x0400
+#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
+
+/* @todo These SS definitions are duplicates of ones below */
+
+#define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE                 0x00000001
+#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK     0xFFFF0000
+#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT    16
+#define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK      10      /* Higher the value, lower the SS modulation frequency */
+#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK     0x0000FFFF
+#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT    0
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT       8
+#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK        (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT       0
+#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK        (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED          (1 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET     (1 << 31)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT     17
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK      (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE        (1 << 16)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT     12
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG            (1 << 7)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN         (1 << 6)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE      (1 << 5)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE      (1 << 4)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET            (1 << 3)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET            (1 << 2)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN             (1 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB     (1 << 26)
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN         (1 << 25)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT     20
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT      8
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK       (0x1ff << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT       4
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT       0
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT           24
+#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK            (0xff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT         0
+#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK          (0xffffff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT       30
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK        (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT     27
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT     24
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT      22
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER          (0x1 << 21)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT          19
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT          17
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT          15
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT          13
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT          10
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK           (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT        5
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK         (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT     0
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK      (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT)
+
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT    4
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK     (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT    2
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK     (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE     (0x1 << 1)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE     (0x1 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE           (0x1 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT  16
+#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK   (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT      0
+#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK       (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE           (1 << 20)
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE          (1 << 16)
+
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT      12
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT      8
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT      0
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK       (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE         (1 << 16)
+
+#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT     12
+#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK      (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT     8
+#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK      (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT     0
+#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK      (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE            (1u << 31)
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE     (1 << 8)
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE  (1 << 6)
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE   (1 << 5)
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE   (1 << 4)
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE  (1 << 2)
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE   (1 << 1)
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE   (1 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE           (1 << 30)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE           (1 << 29)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE       (1 << 28)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE    (1 << 27)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE     (1 << 26)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE   (1 << 25)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE     (1 << 24)
+
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT          20
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK           (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT          16
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK           (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT     12
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT     8
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT       4
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT)
+
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT       0
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B            (1 << 4)
+#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18       (1 << 3)
+#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI      (1 << 2)
+#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV         (1 << 1)
+#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW             (1 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF     (1 << 1)
+#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF      (1 << 0)
+
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+/* Broadcom DDR23 PHY Byte Lane register definitions */
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+
+#define ddrcReg_PHY_BYTE_LANE_CNT                       2
+#define ddrcReg_PHY_BYTE_LANE_MAX                       (ddrcReg_CTLR_BYTE_LANE_CNT - 1)
+
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT               8
+
+        typedef struct {
+                uint32_t revision;
+                uint32_t vdlCalibrate;
+                uint32_t vdlStatus;
+                 REG32_RSVD(0x000c, 0x0010);
+                uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT];
+                uint32_t readCtl;
+                uint32_t readStatus;
+                uint32_t readClear;
+                uint32_t padIdleCtl;
+                uint32_t padDriveCtl;
+                uint32_t padClkCtl;
+                uint32_t writeCtl;
+                uint32_t clkRegCtl;
+        } ddrcReg_PHY_BYTE_LANE_REG_t;
+
+/* There are 2 instances of the byte Lane registers, one for each byte lane. */
+#define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET              0x0500
+#define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET              0x0600
+
+#define ddrcReg_PHY_BYTE_LANE_1_REGP                    ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET))
+#define ddrcReg_PHY_BYTE_LANE_2_REGP                    ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET))
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT      8
+#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK       (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT)
+
+#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT      0
+#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK       (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE      (1 << 4)
+#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE      (0 << 4)
+
+#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST            (1 << 3)
+#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS          (1 << 2)
+#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE            (1 << 1)
+#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST            (1 << 0)
+
+/* ----------------------------------------------------- */
+
+/* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step value, [3:2] fine fall */
+/* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 in the VDL status */
+/* register. The fine rise and fall are no longer used, so add some definitions for just */
+/* the step setting to simplify things. */
+
+#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT     8
+#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK      (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT)
+
+#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT    4
+#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK     (0x3ff << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT)
+
+#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK           (1 << 1)
+#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE           (1 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE            (1 << 16)
+
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT        12
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK         (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT)
+
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT        8
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK         (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT)
+
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT        0
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK         (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT)
+
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P     0
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N     1
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN        2
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM   3
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P    4
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N    5
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN       6
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM  7
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT      8
+#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK       (0x3 << ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT)
+
+#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE    (1 << 3)
+#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST    (1 << 2)
+#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE    (1 << 1)
+#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST    (1 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT   0
+#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK    (0xf << ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS         (1 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE                   (1u << 31)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE         (1 << 19)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE          (1 << 18)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE           (1 << 17)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE           (1 << 16)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE         (1 << 15)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE          (1 << 14)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE           (1 << 13)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE           (1 << 12)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE   (1 << 11)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE    (1 << 10)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE     (1 << 9)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE     (1 << 8)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE        (1 << 7)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE         (1 << 6)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE          (1 << 5)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE          (1 << 4)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE        (1 << 3)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE         (1 << 2)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE          (1 << 1)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE          (1 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB      (1 << 5)
+#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B                   (1 << 4)
+#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18              (1 << 3)
+#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI             (1 << 2)
+#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV                (1 << 1)
+#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW                    (1 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE                   (1 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3               (1 << 0)
+
+/* ----------------------------------------------------- */
+
+#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF                  (1 << 1)
+#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF                   (1 << 0)
+
+/*********************************************************************/
+/* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */
+/*********************************************************************/
+
+        typedef struct {
+                uint32_t cfg;
+                uint32_t actMonCnt;
+                uint32_t ctl;
+                uint32_t lbistCtl;
+                uint32_t lbistSeed;
+                uint32_t lbistStatus;
+                uint32_t tieOff;
+                uint32_t actMonClear;
+                uint32_t status;
+                uint32_t user;
+        } ddrcReg_CTLR_PHY_GLUE_REG_t;
+
+#define ddrcReg_CTLR_PHY_GLUE_OFFSET                            0x0700
+#define ddrcReg_CTLR_PHY_GLUE_REGP                              ((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_PHY_GLUE_OFFSET))
+
+/* ----------------------------------------------------- */
+
+/* DDR2 / AXI block phase alignment interrupt control */
+#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT                     18
+#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK                      (0x3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF                       (0 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT                  (1 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM                 (2 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE                  (3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
+
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT              17
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK               (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL       (0 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS               (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
+
+#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT            16
+#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK             (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP             (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW          (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED   ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW
+
+#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT             15
+#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK              (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134             (0 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301             (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED        ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301
+
+/* Software control of PHY VDL updates from control register settings. Bit 13 enables the use of Bit 14. */
+/* If software control is not enabled, then updates occur when a refresh command is issued by the hardware */
+/* controller. If 2 chips selects are being used, then software control must be enabled. */
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD    (1 << 14)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE  (1 << 13)
+
+/* Use these to bypass a pipeline stage. By default the ADDR is off but the BYTE LANE in / out are on. */
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE (1 << 12)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10)
+
+/* Chip select count */
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT                  9
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK                   (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1                      (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2                      (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
+
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT                     8
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC                     (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC                      (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
+
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT                7
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW                  (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH                 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
+
+#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT                6
+#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW                  (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH                 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
+
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT             0
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK              (0x7 << ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT)
+
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT                0
+#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK                 (0x7f << ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT)
+
+/* ---- Public Function Prototypes --------------------------------------- */
+
+#ifdef __cplusplus
+}                               /* end extern "C" */
+#endif
+#endif                          /* DDRC_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
new file mode 100644
index 000000000000..375066ad0186
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
@@ -0,0 +1,145 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    dmacHw_priv.h
+*
+*  @brief   Private Definitions for low level DMA driver
+*
+*/
+/****************************************************************************/
+
+#ifndef _DMACHW_PRIV_H
+#define _DMACHW_PRIV_H
+
+#include <csp/stdint.h>
+
+/* Data type for DMA Link List Item */
+typedef struct {
+        uint32_t sar;           /* Source Adress Register.
+                                   Address must be aligned to CTLx.SRC_TR_WIDTH.             */
+        uint32_t dar;           /* Destination Address Register.
+                                   Address must be aligned to CTLx.DST_TR_WIDTH.             */
+        uint32_t llpPhy;        /* LLP contains the physical address of the next descriptor for block chaining using linked lists.
+                                   Address MUST be aligned to a 32-bit boundary.             */
+        dmacHw_REG64_t ctl;     /* Control Register. 64 bits */
+        uint32_t sstat;         /* Source Status Register */
+        uint32_t dstat;         /* Destination Status Register */
+        uint32_t devCtl;        /* Device specific control information */
+        uint32_t llp;           /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */
+} dmacHw_DESC_t;
+
+/*
+ *  Descriptor ring pointers
+ */
+typedef struct {
+        int num;                /* Number of link items */
+        dmacHw_DESC_t *pHead;   /* Head of descriptor ring (for writing) */
+        dmacHw_DESC_t *pTail;   /* Tail of descriptor ring (for reading) */
+        dmacHw_DESC_t *pProg;   /* Descriptor to program the channel (for programming the channel register) */
+        dmacHw_DESC_t *pEnd;    /* End of current descriptor chain */
+        dmacHw_DESC_t *pFree;   /* Descriptor to free memory (freeing dynamic memory) */
+        uint32_t virt2PhyOffset;        /* Virtual to physical address offset for the descriptor ring */
+} dmacHw_DESC_RING_t;
+
+/*
+ *  DMA channel control block
+ */
+typedef struct {
+        uint32_t module;        /* DMA controller module (0-1) */
+        uint32_t channel;       /* DMA channel (0-7) */
+        volatile uint32_t varDataStarted;       /* Flag indicating variable data channel is enabled */
+        volatile uint32_t descUpdated;  /* Flag to indicate descriptor update is complete */
+        void *userData;         /* Channel specifc user data */
+} dmacHw_CBLK_t;
+
+#define dmacHw_ASSERT(a)                  if (!(a)) while (1)
+#define dmacHw_MAX_CHANNEL_COUNT          16
+#define dmacHw_FREE_USER_MEMORY           0xFFFFFFFF
+#define dmacHw_DESC_FREE                  dmacHw_REG_CTL_DONE
+#define dmacHw_DESC_INIT                  ((dmacHw_DESC_t *) 0xFFFFFFFF)
+#define dmacHw_MAX_BLOCKSIZE              4064
+#define dmacHw_GET_DESC_RING(addr)        (dmacHw_DESC_RING_t *)(addr)
+#define dmacHw_ADDRESS_MASK(byte)         ((byte) - 1)
+#define dmacHw_NEXT_DESC(rp, dp)           ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp)
+#define dmacHw_HANDLE_TO_CBLK(handle)     ((dmacHw_CBLK_t *) (handle))
+#define dmacHw_CBLK_TO_HANDLE(cblkp)      ((dmacHw_HANDLE_t) (cblkp))
+#define dmacHw_DST_IS_MEMORY(tt)          (((tt) ==  dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
+
+/****************************************************************************/
+/**
+*  @brief   Get next available transaction width
+*
+*
+*  @return  On sucess  : Next avail able transaction width
+*           On failure : dmacHw_TRANSACTION_WIDTH_8
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw    /*   [ IN ] Current transaction width */
+    ) {
+        if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
+                return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
+                         1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
+        } else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
+                return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
+                         1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
+        }
+
+        /* Default return  */
+        return dmacHw_SRC_TRANSACTION_WIDTH_8;
+}
+
+/****************************************************************************/
+/**
+*  @brief   Get number of bytes per transaction
+*
+*  @return  Number of bytes per transaction
+*
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw        /*   [ IN ]  Transaction width */
+    ) {
+        int width = 1;
+        switch (tw) {
+        case dmacHw_SRC_TRANSACTION_WIDTH_8:
+                width = 1;
+                break;
+        case dmacHw_SRC_TRANSACTION_WIDTH_16:
+        case dmacHw_DST_TRANSACTION_WIDTH_16:
+                width = 2;
+                break;
+        case dmacHw_SRC_TRANSACTION_WIDTH_32:
+        case dmacHw_DST_TRANSACTION_WIDTH_32:
+                width = 4;
+                break;
+        case dmacHw_SRC_TRANSACTION_WIDTH_64:
+        case dmacHw_DST_TRANSACTION_WIDTH_64:
+                width = 8;
+                break;
+        default:
+                dmacHw_ASSERT(0);
+        }
+
+        /* Default transaction width */
+        return width;
+}
+
+#endif /* _DMACHW_PRIV_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
new file mode 100644
index 000000000000..891cea87e333
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
@@ -0,0 +1,406 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    dmacHw_reg.h
+*
+*  @brief   Definitions for low level DMA registers
+*
+*/
+/****************************************************************************/
+
+#ifndef _DMACHW_REG_H
+#define _DMACHW_REG_H
+
+#include <csp/stdint.h>
+#include <mach/csp/mm_io.h>
+
+/* Data type for 64 bit little endian register */
+typedef struct {
+        volatile uint32_t lo;   /* Lower 32 bit in little endian mode */
+        volatile uint32_t hi;   /* Upper 32 bit in little endian mode */
+} dmacHw_REG64_t;
+
+/* Data type representing DMA channel registers */
+typedef struct {
+        dmacHw_REG64_t ChannelSar;      /*  Source Adress Register. 64 bits (upper 32 bits are reserved)
+                                           Address must be aligned to CTLx.SRC_TR_WIDTH.
+                                         */
+        dmacHw_REG64_t ChannelDar;      /*  Destination Address Register.64 bits (upper 32 bits are reserved)
+                                           Address must be aligned to CTLx.DST_TR_WIDTH.
+                                         */
+        dmacHw_REG64_t ChannelLlp;      /*  Link List Pointer.64 bits (upper 32 bits are reserved)
+                                           LLP contains the pointer to the next LLI for block chaining using linked lists.
+                                           If LLPis set to 0x0, then transfers using linked lists are not enabled.
+                                           Address MUST be aligned to a 32-bit boundary.
+                                         */
+        dmacHw_REG64_t ChannelCtl;      /* Control Register. 64 bits */
+        dmacHw_REG64_t ChannelSstat;    /* Source Status Register */
+        dmacHw_REG64_t ChannelDstat;    /* Destination Status Register */
+        dmacHw_REG64_t ChannelSstatAddr;        /* Source Status Address Register */
+        dmacHw_REG64_t ChannelDstatAddr;        /* Destination Status Address Register */
+        dmacHw_REG64_t ChannelConfig;   /* Channel Configuration Register */
+        dmacHw_REG64_t SrcGather;       /* Source gather register */
+        dmacHw_REG64_t DstScatter;      /* Destination scatter register */
+} dmacHw_CH_REG_t;
+
+/* Data type for RAW interrupt status registers */
+typedef struct {
+        dmacHw_REG64_t RawTfr;  /* Raw Status for IntTfr Interrupt */
+        dmacHw_REG64_t RawBlock;        /* Raw Status for IntBlock Interrupt */
+        dmacHw_REG64_t RawSrcTran;      /* Raw Status for IntSrcTran Interrupt */
+        dmacHw_REG64_t RawDstTran;      /* Raw Status for IntDstTran Interrupt */
+        dmacHw_REG64_t RawErr;  /* Raw Status for IntErr Interrupt */
+} dmacHw_INT_RAW_t;
+
+/* Data type for interrupt status registers */
+typedef struct {
+        dmacHw_REG64_t StatusTfr;       /* Status for IntTfr Interrupt */
+        dmacHw_REG64_t StatusBlock;     /* Status for IntBlock Interrupt */
+        dmacHw_REG64_t StatusSrcTran;   /* Status for IntSrcTran Interrupt */
+        dmacHw_REG64_t StatusDstTran;   /* Status for IntDstTran Interrupt */
+        dmacHw_REG64_t StatusErr;       /* Status for IntErr Interrupt */
+} dmacHw_INT_STATUS_t;
+
+/* Data type for interrupt mask registers*/
+typedef struct {
+        dmacHw_REG64_t MaskTfr; /* Mask for IntTfr Interrupt */
+        dmacHw_REG64_t MaskBlock;       /* Mask for IntBlock Interrupt */
+        dmacHw_REG64_t MaskSrcTran;     /* Mask for IntSrcTran Interrupt */
+        dmacHw_REG64_t MaskDstTran;     /* Mask for IntDstTran Interrupt */
+        dmacHw_REG64_t MaskErr; /* Mask for IntErr Interrupt */
+} dmacHw_INT_MASK_t;
+
+/* Data type for interrupt clear registers */
+typedef struct {
+        dmacHw_REG64_t ClearTfr;        /* Clear for IntTfr Interrupt */
+        dmacHw_REG64_t ClearBlock;      /* Clear for IntBlock Interrupt */
+        dmacHw_REG64_t ClearSrcTran;    /* Clear for IntSrcTran Interrupt */
+        dmacHw_REG64_t ClearDstTran;    /* Clear for IntDstTran Interrupt */
+        dmacHw_REG64_t ClearErr;        /* Clear for IntErr Interrupt */
+        dmacHw_REG64_t StatusInt;       /* Status for each interrupt type */
+} dmacHw_INT_CLEAR_t;
+
+/* Data type for software handshaking registers */
+typedef struct {
+        dmacHw_REG64_t ReqSrcReg;       /* Source Software Transaction Request Register */
+        dmacHw_REG64_t ReqDstReg;       /* Destination Software Transaction Request Register */
+        dmacHw_REG64_t SglReqSrcReg;    /* Single Source Transaction Request Register */
+        dmacHw_REG64_t SglReqDstReg;    /* Single Destination Transaction Request Register */
+        dmacHw_REG64_t LstSrcReg;       /* Last Source Transaction Request Register */
+        dmacHw_REG64_t LstDstReg;       /* Last Destination Transaction Request Register */
+} dmacHw_SW_HANDSHAKE_t;
+
+/* Data type for misc. registers */
+typedef struct {
+        dmacHw_REG64_t DmaCfgReg;       /* DMA Configuration Register */
+        dmacHw_REG64_t ChEnReg; /* DMA Channel Enable Register */
+        dmacHw_REG64_t DmaIdReg;        /* DMA ID Register */
+        dmacHw_REG64_t DmaTestReg;      /* DMA Test Register */
+        dmacHw_REG64_t Reserved0;       /* Reserved */
+        dmacHw_REG64_t Reserved1;       /* Reserved */
+        dmacHw_REG64_t CompParm6;       /* Component Parameter 6 */
+        dmacHw_REG64_t CompParm5;       /* Component Parameter 5 */
+        dmacHw_REG64_t CompParm4;       /* Component Parameter 4 */
+        dmacHw_REG64_t CompParm3;       /* Component Parameter 3 */
+        dmacHw_REG64_t CompParm2;       /* Component Parameter 2 */
+        dmacHw_REG64_t CompParm1;       /* Component Parameter 1 */
+        dmacHw_REG64_t CompId;  /* Compoent ID */
+} dmacHw_MISC_t;
+
+/* Base registers */
+#define dmacHw_0_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA0       /* DMAC 0 module's base address */
+#define dmacHw_1_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA1       /* DMAC 1 module's base address */
+
+extern uint32_t dmaChannelCount_0;
+extern uint32_t dmaChannelCount_1;
+
+/* Define channel specific registers */
+#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
+
+/* Raw interrupt status registers */
+#define dmacHw_REG_INT_RAW_BASE(module)         ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
+#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
+#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
+#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
+#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
+#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
+
+/* Interrupt status registers */
+#define dmacHw_REG_INT_STAT_BASE(module)        ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
+#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
+#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
+#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
+#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
+#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
+
+/* Interrupt status registers */
+#define dmacHw_REG_INT_MASK_BASE(module)        ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
+#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
+#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
+#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
+#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
+#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
+
+/* Interrupt clear registers */
+#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
+#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
+#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
+#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
+#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
+#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
+#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
+
+/* Software handshaking registers */
+#define dmacHw_REG_SW_HS_BASE(module)           ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
+#define dmacHw_REG_SW_HS_SRC_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
+#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
+#define dmacHw_REG_SW_HS_SRC_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
+
+/* Miscellaneous registers */
+#define dmacHw_REG_MISC_BASE(module)            ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
+#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
+#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
+#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
+#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
+#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
+#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
+#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
+#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
+#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
+#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
+#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
+#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
+#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
+#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
+#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
+#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
+
+/* Channel control registers */
+#define dmacHw_REG_SAR(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
+#define dmacHw_REG_DAR(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo)
+#define dmacHw_REG_LLP(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo)
+
+#define dmacHw_REG_CTL_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo)
+#define dmacHw_REG_CTL_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi)
+
+#define dmacHw_REG_SSTAT(module, chan)          (dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo)
+#define dmacHw_REG_DSTAT(module, chan)          (dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo)
+#define dmacHw_REG_SSTATAR(module, chan)        (dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo)
+#define dmacHw_REG_DSTATAR(module, chan)        (dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo)
+
+#define dmacHw_REG_CFG_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo)
+#define dmacHw_REG_CFG_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi)
+
+#define dmacHw_REG_SGR_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo)
+#define dmacHw_REG_SGR_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi)
+
+#define dmacHw_REG_DSR_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo)
+#define dmacHw_REG_DSR_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi)
+
+#define INT_STATUS_MASK(channel)                (0x00000001 << (channel))
+#define CHANNEL_BUSY(mod, channel)              (dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel)))
+
+/* Bit mask for REG_DMACx_CTL_LO */
+
+#define dmacHw_REG_CTL_INT_EN                       0x00000001  /* Channel interrupt enable */
+
+#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK            0x0000000E  /* Destination transaction width mask */
+#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT           1
+#define dmacHw_REG_CTL_DST_TR_WIDTH_8               0x00000000  /* Destination transaction width 8 bit */
+#define dmacHw_REG_CTL_DST_TR_WIDTH_16              0x00000002  /* Destination transaction width 16 bit */
+#define dmacHw_REG_CTL_DST_TR_WIDTH_32              0x00000004  /* Destination transaction width 32 bit */
+#define dmacHw_REG_CTL_DST_TR_WIDTH_64              0x00000006  /* Destination transaction width 64 bit */
+
+#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK            0x00000070  /* Source transaction width mask */
+#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT           4
+#define dmacHw_REG_CTL_SRC_TR_WIDTH_8               0x00000000  /* Source transaction width 8 bit */
+#define dmacHw_REG_CTL_SRC_TR_WIDTH_16              0x00000010  /* Source transaction width 16 bit */
+#define dmacHw_REG_CTL_SRC_TR_WIDTH_32              0x00000020  /* Source transaction width 32 bit */
+#define dmacHw_REG_CTL_SRC_TR_WIDTH_64              0x00000030  /* Source transaction width 64 bit */
+
+#define dmacHw_REG_CTL_DS_ENABLE                    0x00040000  /* Destination scatter enable */
+#define dmacHw_REG_CTL_SG_ENABLE                    0x00020000  /* Source gather enable */
+
+#define dmacHw_REG_CTL_DINC_MASK                    0x00000180  /* Destination address inc/dec mask */
+#define dmacHw_REG_CTL_DINC_INC                     0x00000000  /* Destination address increment */
+#define dmacHw_REG_CTL_DINC_DEC                     0x00000080  /* Destination address decrement */
+#define dmacHw_REG_CTL_DINC_NC                      0x00000100  /* Destination address no change */
+
+#define dmacHw_REG_CTL_SINC_MASK                    0x00000600  /* Source address inc/dec mask */
+#define dmacHw_REG_CTL_SINC_INC                     0x00000000  /* Source address increment */
+#define dmacHw_REG_CTL_SINC_DEC                     0x00000200  /* Source address decrement */
+#define dmacHw_REG_CTL_SINC_NC                      0x00000400  /* Source address no change */
+
+#define dmacHw_REG_CTL_DST_MSIZE_MASK               0x00003800  /* Destination burst transaction length */
+#define dmacHw_REG_CTL_DST_MSIZE_0                  0x00000000  /* No Destination burst */
+#define dmacHw_REG_CTL_DST_MSIZE_4                  0x00000800  /* Destination burst transaction length 4 */
+#define dmacHw_REG_CTL_DST_MSIZE_8                  0x00001000  /* Destination burst transaction length 8 */
+#define dmacHw_REG_CTL_DST_MSIZE_16                 0x00001800  /* Destination burst transaction length 16 */
+
+#define dmacHw_REG_CTL_SRC_MSIZE_MASK               0x0001C000  /* Source burst transaction length */
+#define dmacHw_REG_CTL_SRC_MSIZE_0                  0x00000000  /* No Source burst */
+#define dmacHw_REG_CTL_SRC_MSIZE_4                  0x00004000  /* Source burst transaction length 4 */
+#define dmacHw_REG_CTL_SRC_MSIZE_8                  0x00008000  /* Source burst transaction length 8 */
+#define dmacHw_REG_CTL_SRC_MSIZE_16                 0x0000C000  /* Source burst transaction length 16 */
+
+#define dmacHw_REG_CTL_TTFC_MASK                    0x00700000  /* Transfer type and flow controller */
+#define dmacHw_REG_CTL_TTFC_MM_DMAC                 0x00000000  /* Memory to Memory with DMAC as flow controller */
+#define dmacHw_REG_CTL_TTFC_MP_DMAC                 0x00100000  /* Memory to Peripheral with DMAC as flow controller */
+#define dmacHw_REG_CTL_TTFC_PM_DMAC                 0x00200000  /* Peripheral to Memory with DMAC as flow controller */
+#define dmacHw_REG_CTL_TTFC_PP_DMAC                 0x00300000  /* Peripheral to Peripheral with DMAC as flow controller */
+#define dmacHw_REG_CTL_TTFC_PM_PERI                 0x00400000  /* Peripheral to Memory with Peripheral as flow controller */
+#define dmacHw_REG_CTL_TTFC_PP_SPERI                0x00500000  /* Peripheral to Peripheral with Source Peripheral as flow controller */
+#define dmacHw_REG_CTL_TTFC_MP_PERI                 0x00600000  /* Memory to Peripheral with Peripheral as flow controller */
+#define dmacHw_REG_CTL_TTFC_PP_DPERI                0x00700000  /* Peripheral to Peripheral with Destination Peripheral as flow controller */
+
+#define dmacHw_REG_CTL_DMS_MASK                     0x01800000  /* Destination AHB master interface */
+#define dmacHw_REG_CTL_DMS_1                        0x00000000  /* Destination AHB master interface 1 */
+#define dmacHw_REG_CTL_DMS_2                        0x00800000  /* Destination AHB master interface 2 */
+
+#define dmacHw_REG_CTL_SMS_MASK                     0x06000000  /* Source AHB master interface */
+#define dmacHw_REG_CTL_SMS_1                        0x00000000  /* Source AHB master interface 1 */
+#define dmacHw_REG_CTL_SMS_2                        0x02000000  /* Source AHB master interface 2 */
+
+#define dmacHw_REG_CTL_LLP_DST_EN                   0x08000000  /* Block chaining enable for destination side */
+#define dmacHw_REG_CTL_LLP_SRC_EN                   0x10000000  /* Block chaining enable for source side */
+
+/* Bit mask for REG_DMACx_CTL_HI */
+#define dmacHw_REG_CTL_BLOCK_TS_MASK                0x00000FFF  /* Block transfer size */
+#define dmacHw_REG_CTL_DONE                         0x00001000  /* Block trasnfer done */
+
+/* Bit mask for REG_DMACx_CFG_LO */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT                  5  /* Channel priority shift */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK          0x000000E0  /* Channel priority mask */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_0             0x00000000  /* Channel priority 0 */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_1             0x00000020  /* Channel priority 1 */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_2             0x00000040  /* Channel priority 2 */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_3             0x00000060  /* Channel priority 3 */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_4             0x00000080  /* Channel priority 4 */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_5             0x000000A0  /* Channel priority 5 */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_6             0x000000C0  /* Channel priority 6 */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_7             0x000000E0  /* Channel priority 7 */
+
+#define dmacHw_REG_CFG_LO_CH_SUSPEND                0x00000100  /* Channel suspend */
+#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY             0x00000200  /* Channel FIFO empty */
+#define dmacHw_REG_CFG_LO_DST_CH_SW_HS              0x00000400  /* Destination channel SW handshaking */
+#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS              0x00000800  /* Source channel SW handshaking */
+
+#define dmacHw_REG_CFG_LO_CH_LOCK_MASK              0x00003000  /* Channel locking mask */
+#define dmacHw_REG_CFG_LO_CH_LOCK_DMA               0x00000000  /* Channel lock over the entire DMA transfer operation */
+#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK             0x00001000  /* Channel lock over the block transfer operation */
+#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS             0x00002000  /* Channel lock over the transaction */
+#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE            0x00010000  /* Channel lock enable */
+
+#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK             0x0000C000  /* Bus locking mask */
+#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA              0x00000000  /* Bus lock over the entire DMA transfer operation */
+#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK            0x00004000  /* Bus lock over the block transfer operation */
+#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS            0x00008000  /* Bus lock over the transaction */
+#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE           0x00020000  /* Bus lock enable */
+
+#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW       0x00040000  /* Destination channel handshaking signal polarity low */
+#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW       0x00080000  /* Source channel handshaking signal polarity low */
+
+#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK   0x3FF00000  /* Maximum AMBA burst length */
+
+#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC           0x40000000  /* Source address auto reload */
+#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST           0x80000000  /* Destination address auto reload */
+
+/* Bit mask for REG_DMACx_CFG_HI */
+#define dmacHw_REG_CFG_HI_FC_DST_READY              0x00000001  /* Source transaction request is serviced when destination is ready */
+#define dmacHw_REG_CFG_HI_FIFO_ENOUGH               0x00000002  /* Initiate burst transaction when enough data in available in FIFO */
+
+#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK            0x0000001C  /* AHB protection mask */
+#define dmacHw_REG_CFG_HI_AHB_HPROT_1               0x00000004  /* AHB protection 1 */
+#define dmacHw_REG_CFG_HI_AHB_HPROT_2               0x00000008  /* AHB protection 2 */
+#define dmacHw_REG_CFG_HI_AHB_HPROT_3               0x00000010  /* AHB protection 3 */
+
+#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT           0x00000020  /* Destination status update enable */
+#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT           0x00000040  /* Source status update enable */
+
+#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK        0x00000780  /* Source peripheral hardware interface mask */
+#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK        0x00007800  /* Destination peripheral hardware interface mask */
+
+/* DMA Configuration Parameters */
+#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS          0x00000700  /* Number of channels */
+#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE         0x00001800  /* Number of master interface */
+#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE          0x0000000f  /* Maximum brust size */
+#define dmacHw_REG_COMP_PARAM_DATA_WIDTH            0x00006000  /* Data transfer width */
+
+/* Define GET/SET macros to program the registers */
+#define dmacHw_SET_SAR(module, channel, addr)          (dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr))
+#define dmacHw_SET_DAR(module, channel, addr)          (dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr))
+#define dmacHw_SET_LLP(module, channel, ptr)           (dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr))
+
+#define dmacHw_GET_SSTAT(module, channel)              (dmacHw_REG_SSTAT((module), (channel)))
+#define dmacHw_GET_DSTAT(module, channel)              (dmacHw_REG_DSTAT((module), (channel)))
+
+#define dmacHw_SET_SSTATAR(module, channel, addr)      (dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr))
+#define dmacHw_SET_DSTATAR(module, channel, addr)      (dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr))
+
+#define dmacHw_SET_CONTROL_LO(module, channel, ctl)    (dmacHw_REG_CTL_LO((module), (channel)) |= (ctl))
+#define dmacHw_RESET_CONTROL_LO(module, channel)       (dmacHw_REG_CTL_LO((module), (channel)) = 0)
+#define dmacHw_GET_CONTROL_LO(module, channel)         (dmacHw_REG_CTL_LO((module), (channel)))
+
+#define dmacHw_SET_CONTROL_HI(module, channel, ctl)    (dmacHw_REG_CTL_HI((module), (channel)) |= (ctl))
+#define dmacHw_RESET_CONTROL_HI(module, channel)       (dmacHw_REG_CTL_HI((module), (channel)) = 0)
+#define dmacHw_GET_CONTROL_HI(module, channel)         (dmacHw_REG_CTL_HI((module), (channel)))
+
+#define dmacHw_GET_BLOCK_SIZE(module, channel)         (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK)
+#define dmacHw_DMA_COMPLETE(module, channel)           (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE)
+
+#define dmacHw_SET_CONFIG_LO(module, channel, cfg)     (dmacHw_REG_CFG_LO((module), (channel)) |= (cfg))
+#define dmacHw_RESET_CONFIG_LO(module, channel)        (dmacHw_REG_CFG_LO((module), (channel)) = 0)
+#define dmacHw_GET_CONFIG_LO(module, channel)          (dmacHw_REG_CFG_LO((module), (channel)))
+#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len)    (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK))
+#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio))
+#define dmacHw_SET_AHB_HPROT(module, channel, protect)  (dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect))
+
+#define dmacHw_SET_CONFIG_HI(module, channel, cfg)      (dmacHw_REG_CFG_HI((module), (channel)) |= (cfg))
+#define dmacHw_RESET_CONFIG_HI(module, channel)         (dmacHw_REG_CFG_HI((module), (channel)) = 0)
+#define dmacHw_GET_CONFIG_HI(module, channel)           (dmacHw_REG_CFG_HI((module), (channel)))
+#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK))
+#define dmacHw_SRC_PERI_INTF(intf)                      (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)
+#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK))
+#define dmacHw_DST_PERI_INTF(intf)                      (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)
+
+#define dmacHw_DMA_START(module, channel)              (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
+#define dmacHw_DMA_STOP(module, channel)               (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)))
+#define dmacHw_DMA_ENABLE(module)                      (dmacHw_REG_MISC_CFG((module)) = 1)
+#define dmacHw_DMA_DISABLE(module)                     (dmacHw_REG_MISC_CFG((module)) = 0)
+
+#define dmacHw_TRAN_INT_ENABLE(module, channel)        (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
+#define dmacHw_BLOCK_INT_ENABLE(module, channel)       (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
+#define dmacHw_ERROR_INT_ENABLE(module, channel)       (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
+
+#define dmacHw_TRAN_INT_DISABLE(module, channel)       (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)))
+#define dmacHw_BLOCK_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)))
+#define dmacHw_ERROR_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)))
+#define dmacHw_STRAN_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8)))
+#define dmacHw_DTRAN_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8)))
+
+#define dmacHw_TRAN_INT_CLEAR(module, channel)         (dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel)))
+#define dmacHw_BLOCK_INT_CLEAR(module, channel)        (dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel)))
+#define dmacHw_ERROR_INT_CLEAR(module, channel)        (dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel)))
+
+#define dmacHw_GET_NUM_CHANNEL(module)                 (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1)
+#define dmacHw_GET_NUM_INTERFACE(module)               (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1)
+#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel)     ((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE)
+#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13)
+
+#endif /* _DMACHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
new file mode 100644
index 000000000000..cfa91bed9d34
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
@@ -0,0 +1,73 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+
+#ifndef CSP_HW_CFG_H
+#define CSP_HW_CFG_H
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#include <cfg_global.h>
+#include <mach/csp/cap_inline.h>
+
+#if defined(__KERNEL__)
+#include <mach/memory_settings.h>
+#else
+#include <hw_cfg.h>
+#endif
+
+/* Some items that can be defined externally, but will be set to default values */
+/* if they are not defined. */
+/*      HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE   Default undefined and SS is enabled. */
+/*      HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
+/*      HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
+/*      HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values [400,533,667,800] */
+/*      HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules [8,16] */
+/*      HW_CFG_SDRAM_ADDR_BRC                Default undefined and Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */
+/*      HW_CFG_SDRAM_CLK_ASYNC               Default undefined and DDR clock is synchronous with AXI BUS clock. Define for ASYNC mode. */
+
+#if defined(CFG_GLOBAL_CHIP)
+  #if (CFG_GLOBAL_CHIP == FPGA11107)
+     #define HW_CFG_BUS_CLK_HZ            5000000
+     #define HW_CFG_DDR_CTLR_CLK_HZ      10000000
+     #define HW_CFG_DDR_PHY_OMIT
+     #define HW_CFG_UART_CLK_HZ           7500000
+  #else
+     #define HW_CFG_PLL_VCO_HZ           2000000000
+     #define HW_CFG_PLL2_VCO_HZ          1800000000
+     #define HW_CFG_ARM_CLK_HZ            CAP_HW_CFG_ARM_CLK_HZ
+     #define HW_CFG_BUS_CLK_HZ            166666666
+     #define HW_CFG_DDR_CTLR_CLK_HZ       333333333
+     #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
+     #define HW_CFG_UART_CLK_HZ           142857142
+     #define HW_CFG_VPM_CLK_HZ            CAP_HW_CFG_VPM_CLK_HZ
+  #endif
+#else
+   #define HW_CFG_PLL_VCO_HZ           1800000000
+   #define HW_CFG_PLL2_VCO_HZ          1800000000
+   #define HW_CFG_ARM_CLK_HZ            450000000
+   #define HW_CFG_BUS_CLK_HZ            150000000
+   #define HW_CFG_DDR_CTLR_CLK_HZ       300000000
+   #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
+   #define HW_CFG_UART_CLK_HZ           150000000
+   #define HW_CFG_VPM_CLK_HZ            300000000
+#endif
+
+/* ---- Public Constants and Types --------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+
+
+#endif /* CSP_HW_CFG_H */
+
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
new file mode 100644
index 000000000000..e01fc4607c91
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
@@ -0,0 +1,246 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    intcHw_reg.h
+*
+*  @brief   platform specific interrupt controller bit assignments
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+
+#ifndef _INTCHW_REG_H
+#define _INTCHW_REG_H
+
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/stdint.h>
+#include <csp/reg.h>
+#include <mach/csp/mm_io.h>
+
+/* ---- Public Constants and Types --------------------------------------- */
+
+#define INTCHW_NUM_IRQ_PER_INTC   32    /* Maximum number of interrupt controllers */
+#define INTCHW_NUM_INTC           3
+
+/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
+#define INTCHW_INTC0    ((void *)MM_IO_BASE_INTC0)
+#define INTCHW_INTC1    ((void *)MM_IO_BASE_INTC1)
+#define INTCHW_SINTC    ((void *)MM_IO_BASE_SINTC)
+
+/* INTC0 - interrupt controller 0 */
+#define INTCHW_INTC0_PIF_BITNUM           31    /* Peripheral interface interrupt */
+#define INTCHW_INTC0_CLCD_BITNUM          30    /* LCD Controller interrupt */
+#define INTCHW_INTC0_GE_BITNUM            29    /* Graphic engine interrupt */
+#define INTCHW_INTC0_APM_BITNUM           28    /* Audio process module interrupt */
+#define INTCHW_INTC0_ESW_BITNUM           27    /* Ethernet switch interrupt */
+#define INTCHW_INTC0_SPIH_BITNUM          26    /* SPI host interrupt */
+#define INTCHW_INTC0_TIMER3_BITNUM        25    /* Timer3 interrupt */
+#define INTCHW_INTC0_TIMER2_BITNUM        24    /* Timer2 interrupt */
+#define INTCHW_INTC0_TIMER1_BITNUM        23    /* Timer1 interrupt */
+#define INTCHW_INTC0_TIMER0_BITNUM        22    /* Timer0 interrupt */
+#define INTCHW_INTC0_SDIOH1_BITNUM        21    /* SDIO1 host interrupt */
+#define INTCHW_INTC0_SDIOH0_BITNUM        20    /* SDIO0 host interrupt */
+#define INTCHW_INTC0_USBD_BITNUM          19    /* USB device interrupt */
+#define INTCHW_INTC0_USBH1_BITNUM         18    /* USB1 host interrupt */
+#define INTCHW_INTC0_USBHD2_BITNUM        17    /* USB host2/device2 interrupt */
+#define INTCHW_INTC0_VPM_BITNUM           16    /* Voice process module interrupt */
+#define INTCHW_INTC0_DMA1C7_BITNUM        15    /* DMA1 channel 7 interrupt */
+#define INTCHW_INTC0_DMA1C6_BITNUM        14    /* DMA1 channel 6 interrupt */
+#define INTCHW_INTC0_DMA1C5_BITNUM        13    /* DMA1 channel 5 interrupt */
+#define INTCHW_INTC0_DMA1C4_BITNUM        12    /* DMA1 channel 4 interrupt */
+#define INTCHW_INTC0_DMA1C3_BITNUM        11    /* DMA1 channel 3 interrupt */
+#define INTCHW_INTC0_DMA1C2_BITNUM        10    /* DMA1 channel 2 interrupt */
+#define INTCHW_INTC0_DMA1C1_BITNUM         9    /* DMA1 channel 1 interrupt */
+#define INTCHW_INTC0_DMA1C0_BITNUM         8    /* DMA1 channel 0 interrupt */
+#define INTCHW_INTC0_DMA0C7_BITNUM         7    /* DMA0 channel 7 interrupt */
+#define INTCHW_INTC0_DMA0C6_BITNUM         6    /* DMA0 channel 6 interrupt */
+#define INTCHW_INTC0_DMA0C5_BITNUM         5    /* DMA0 channel 5 interrupt */
+#define INTCHW_INTC0_DMA0C4_BITNUM         4    /* DMA0 channel 4 interrupt */
+#define INTCHW_INTC0_DMA0C3_BITNUM         3    /* DMA0 channel 3 interrupt */
+#define INTCHW_INTC0_DMA0C2_BITNUM         2    /* DMA0 channel 2 interrupt */
+#define INTCHW_INTC0_DMA0C1_BITNUM         1    /* DMA0 channel 1 interrupt */
+#define INTCHW_INTC0_DMA0C0_BITNUM         0    /* DMA0 channel 0 interrupt */
+
+#define INTCHW_INTC0_PIF                  (1<<INTCHW_INTC0_PIF_BITNUM)
+#define INTCHW_INTC0_CLCD                 (1<<INTCHW_INTC0_CLCD_BITNUM)
+#define INTCHW_INTC0_GE                   (1<<INTCHW_INTC0_GE_BITNUM)
+#define INTCHW_INTC0_APM                  (1<<INTCHW_INTC0_APM_BITNUM)
+#define INTCHW_INTC0_ESW                  (1<<INTCHW_INTC0_ESW_BITNUM)
+#define INTCHW_INTC0_SPIH                 (1<<INTCHW_INTC0_SPIH_BITNUM)
+#define INTCHW_INTC0_TIMER3               (1<<INTCHW_INTC0_TIMER3_BITNUM)
+#define INTCHW_INTC0_TIMER2               (1<<INTCHW_INTC0_TIMER2_BITNUM)
+#define INTCHW_INTC0_TIMER1               (1<<INTCHW_INTC0_TIMER1_BITNUM)
+#define INTCHW_INTC0_TIMER0               (1<<INTCHW_INTC0_TIMER0_BITNUM)
+#define INTCHW_INTC0_SDIOH1               (1<<INTCHW_INTC0_SDIOH1_BITNUM)
+#define INTCHW_INTC0_SDIOH0               (1<<INTCHW_INTC0_SDIOH0_BITNUM)
+#define INTCHW_INTC0_USBD                 (1<<INTCHW_INTC0_USBD_BITNUM)
+#define INTCHW_INTC0_USBH1                (1<<INTCHW_INTC0_USBH1_BITNUM)
+#define INTCHW_INTC0_USBHD2               (1<<INTCHW_INTC0_USBHD2_BITNUM)
+#define INTCHW_INTC0_VPM                  (1<<INTCHW_INTC0_VPM_BITNUM)
+#define INTCHW_INTC0_DMA1C7               (1<<INTCHW_INTC0_DMA1C7_BITNUM)
+#define INTCHW_INTC0_DMA1C6               (1<<INTCHW_INTC0_DMA1C6_BITNUM)
+#define INTCHW_INTC0_DMA1C5               (1<<INTCHW_INTC0_DMA1C5_BITNUM)
+#define INTCHW_INTC0_DMA1C4               (1<<INTCHW_INTC0_DMA1C4_BITNUM)
+#define INTCHW_INTC0_DMA1C3               (1<<INTCHW_INTC0_DMA1C3_BITNUM)
+#define INTCHW_INTC0_DMA1C2               (1<<INTCHW_INTC0_DMA1C2_BITNUM)
+#define INTCHW_INTC0_DMA1C1               (1<<INTCHW_INTC0_DMA1C1_BITNUM)
+#define INTCHW_INTC0_DMA1C0               (1<<INTCHW_INTC0_DMA1C0_BITNUM)
+#define INTCHW_INTC0_DMA0C7               (1<<INTCHW_INTC0_DMA0C7_BITNUM)
+#define INTCHW_INTC0_DMA0C6               (1<<INTCHW_INTC0_DMA0C6_BITNUM)
+#define INTCHW_INTC0_DMA0C5               (1<<INTCHW_INTC0_DMA0C5_BITNUM)
+#define INTCHW_INTC0_DMA0C4               (1<<INTCHW_INTC0_DMA0C4_BITNUM)
+#define INTCHW_INTC0_DMA0C3               (1<<INTCHW_INTC0_DMA0C3_BITNUM)
+#define INTCHW_INTC0_DMA0C2               (1<<INTCHW_INTC0_DMA0C2_BITNUM)
+#define INTCHW_INTC0_DMA0C1               (1<<INTCHW_INTC0_DMA0C1_BITNUM)
+#define INTCHW_INTC0_DMA0C0               (1<<INTCHW_INTC0_DMA0C0_BITNUM)
+
+/* INTC1 - interrupt controller 1 */
+#define INTCHW_INTC1_DDRVPMP_BITNUM       27    /* DDR and VPM PLL clock phase relationship interupt (Not for A0) */
+#define INTCHW_INTC1_DDRVPMT_BITNUM       26    /* DDR and VPM HW phase align timeout interrupt (Not for A0) */
+#define INTCHW_INTC1_DDRP_BITNUM          26    /* DDR and PLL clock phase relationship interupt (For A0 only)) */
+#define INTCHW_INTC1_RTC2_BITNUM          25    /* Real time clock tamper interrupt */
+#define INTCHW_INTC1_VDEC_BITNUM          24    /* Hantro Video Decoder interrupt */
+/* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */
+#define INTCHW_INTC1_SPUM_BITNUM          23    /* Secure process module interrupt */
+#define INTCHW_INTC1_RTC1_BITNUM          22    /* Real time clock one-shot interrupt */
+#define INTCHW_INTC1_RTC0_BITNUM          21    /* Real time clock periodic interrupt */
+#define INTCHW_INTC1_RNG_BITNUM           20    /* Random number generator interrupt */
+#define INTCHW_INTC1_FMPU_BITNUM          19    /* Flash memory parition unit interrupt */
+#define INTCHW_INTC1_VMPU_BITNUM          18    /* VRAM memory partition interrupt */
+#define INTCHW_INTC1_DMPU_BITNUM          17    /* DDR2 memory partition interrupt */
+#define INTCHW_INTC1_KEYC_BITNUM          16    /* Key pad controller interrupt */
+#define INTCHW_INTC1_TSC_BITNUM           15    /* Touch screen controller interrupt */
+#define INTCHW_INTC1_UART0_BITNUM         14    /* UART 0 */
+#define INTCHW_INTC1_WDOG_BITNUM          13    /* Watchdog timer interrupt */
+
+#define INTCHW_INTC1_UART1_BITNUM         12    /* UART 1 */
+#define INTCHW_INTC1_PMUIRQ_BITNUM        11    /* ARM performance monitor interrupt */
+#define INTCHW_INTC1_COMMRX_BITNUM        10    /* ARM DDC receive interrupt */
+#define INTCHW_INTC1_COMMTX_BITNUM         9    /* ARM DDC transmit interrupt */
+#define INTCHW_INTC1_FLASHC_BITNUM         8    /* Flash controller interrupt */
+#define INTCHW_INTC1_GPHY_BITNUM           7    /* Gigabit Phy interrupt */
+#define INTCHW_INTC1_SPIS_BITNUM           6    /* SPI slave interrupt */
+#define INTCHW_INTC1_I2CS_BITNUM           5    /* I2C slave interrupt */
+#define INTCHW_INTC1_I2CH_BITNUM           4    /* I2C host interrupt */
+#define INTCHW_INTC1_I2S1_BITNUM           3    /* I2S1 interrupt */
+#define INTCHW_INTC1_I2S0_BITNUM           2    /* I2S0 interrupt */
+#define INTCHW_INTC1_GPIO1_BITNUM          1    /* GPIO bit 64//32 combined interrupt */
+#define INTCHW_INTC1_GPIO0_BITNUM          0    /* GPIO bit 31//0 combined interrupt */
+
+#define INTCHW_INTC1_DDRVPMT              (1<<INTCHW_INTC1_DDRVPMT_BITNUM)
+#define INTCHW_INTC1_DDRVPMP              (1<<INTCHW_INTC1_DDRVPMP_BITNUM)
+#define INTCHW_INTC1_DDRP                 (1<<INTCHW_INTC1_DDRP_BITNUM)
+#define INTCHW_INTC1_VDEC                 (1<<INTCHW_INTC1_VDEC_BITNUM)
+#define INTCHW_INTC1_SPUM                 (1<<INTCHW_INTC1_SPUM_BITNUM)
+#define INTCHW_INTC1_RTC2                 (1<<INTCHW_INTC1_RTC2_BITNUM)
+#define INTCHW_INTC1_RTC1                 (1<<INTCHW_INTC1_RTC1_BITNUM)
+#define INTCHW_INTC1_RTC0                 (1<<INTCHW_INTC1_RTC0_BITNUM)
+#define INTCHW_INTC1_RNG                  (1<<INTCHW_INTC1_RNG_BITNUM)
+#define INTCHW_INTC1_FMPU                 (1<<INTCHW_INTC1_FMPU_BITNUM)
+#define INTCHW_INTC1_IMPU                 (1<<INTCHW_INTC1_IMPU_BITNUM)
+#define INTCHW_INTC1_DMPU                 (1<<INTCHW_INTC1_DMPU_BITNUM)
+#define INTCHW_INTC1_KEYC                 (1<<INTCHW_INTC1_KEYC_BITNUM)
+#define INTCHW_INTC1_TSC                  (1<<INTCHW_INTC1_TSC_BITNUM)
+#define INTCHW_INTC1_UART0                (1<<INTCHW_INTC1_UART0_BITNUM)
+#define INTCHW_INTC1_WDOG                 (1<<INTCHW_INTC1_WDOG_BITNUM)
+#define INTCHW_INTC1_UART1                (1<<INTCHW_INTC1_UART1_BITNUM)
+#define INTCHW_INTC1_PMUIRQ               (1<<INTCHW_INTC1_PMUIRQ_BITNUM)
+#define INTCHW_INTC1_COMMRX               (1<<INTCHW_INTC1_COMMRX_BITNUM)
+#define INTCHW_INTC1_COMMTX               (1<<INTCHW_INTC1_COMMTX_BITNUM)
+#define INTCHW_INTC1_FLASHC               (1<<INTCHW_INTC1_FLASHC_BITNUM)
+#define INTCHW_INTC1_GPHY                 (1<<INTCHW_INTC1_GPHY_BITNUM)
+#define INTCHW_INTC1_SPIS                 (1<<INTCHW_INTC1_SPIS_BITNUM)
+#define INTCHW_INTC1_I2CS                 (1<<INTCHW_INTC1_I2CS_BITNUM)
+#define INTCHW_INTC1_I2CH                 (1<<INTCHW_INTC1_I2CH_BITNUM)
+#define INTCHW_INTC1_I2S1                 (1<<INTCHW_INTC1_I2S1_BITNUM)
+#define INTCHW_INTC1_I2S0                 (1<<INTCHW_INTC1_I2S0_BITNUM)
+#define INTCHW_INTC1_GPIO1                (1<<INTCHW_INTC1_GPIO1_BITNUM)
+#define INTCHW_INTC1_GPIO0                (1<<INTCHW_INTC1_GPIO0_BITNUM)
+
+/* SINTC secure int controller */
+#define INTCHW_SINTC_RTC2_BITNUM          15    /* Real time clock tamper interrupt */
+#define INTCHW_SINTC_TIMER3_BITNUM        14    /* Secure timer3 interrupt */
+#define INTCHW_SINTC_TIMER2_BITNUM        13    /* Secure timer2 interrupt */
+#define INTCHW_SINTC_TIMER1_BITNUM        12    /* Secure timer1 interrupt */
+#define INTCHW_SINTC_TIMER0_BITNUM        11    /* Secure timer0 interrupt */
+#define INTCHW_SINTC_SPUM_BITNUM          10    /* Secure process module interrupt */
+#define INTCHW_SINTC_RTC1_BITNUM           9    /* Real time clock one-shot interrupt */
+#define INTCHW_SINTC_RTC0_BITNUM           8    /* Real time clock periodic interrupt */
+#define INTCHW_SINTC_RNG_BITNUM            7    /* Random number generator interrupt */
+#define INTCHW_SINTC_FMPU_BITNUM           6    /* Flash memory parition unit interrupt */
+#define INTCHW_SINTC_VMPU_BITNUM           5    /* VRAM memory partition interrupt */
+#define INTCHW_SINTC_DMPU_BITNUM           4    /* DDR2 memory partition interrupt */
+#define INTCHW_SINTC_KEYC_BITNUM           3    /* Key pad controller interrupt */
+#define INTCHW_SINTC_TSC_BITNUM            2    /* Touch screen controller interrupt */
+#define INTCHW_SINTC_UART0_BITNUM          1    /* UART0 interrupt */
+#define INTCHW_SINTC_WDOG_BITNUM           0    /* Watchdog timer interrupt */
+
+#define INTCHW_SINTC_TIMER3               (1<<INTCHW_SINTC_TIMER3_BITNUM)
+#define INTCHW_SINTC_TIMER2               (1<<INTCHW_SINTC_TIMER2_BITNUM)
+#define INTCHW_SINTC_TIMER1               (1<<INTCHW_SINTC_TIMER1_BITNUM)
+#define INTCHW_SINTC_TIMER0               (1<<INTCHW_SINTC_TIMER0_BITNUM)
+#define INTCHW_SINTC_SPUM                 (1<<INTCHW_SINTC_SPUM_BITNUM)
+#define INTCHW_SINTC_RTC2                 (1<<INTCHW_SINTC_RTC2_BITNUM)
+#define INTCHW_SINTC_RTC1                 (1<<INTCHW_SINTC_RTC1_BITNUM)
+#define INTCHW_SINTC_RTC0                 (1<<INTCHW_SINTC_RTC0_BITNUM)
+#define INTCHW_SINTC_RNG                  (1<<INTCHW_SINTC_RNG_BITNUM)
+#define INTCHW_SINTC_FMPU                 (1<<INTCHW_SINTC_FMPU_BITNUM)
+#define INTCHW_SINTC_IMPU                 (1<<INTCHW_SINTC_IMPU_BITNUM)
+#define INTCHW_SINTC_DMPU                 (1<<INTCHW_SINTC_DMPU_BITNUM)
+#define INTCHW_SINTC_KEYC                 (1<<INTCHW_SINTC_KEYC_BITNUM)
+#define INTCHW_SINTC_TSC                  (1<<INTCHW_SINTC_TSC_BITNUM)
+#define INTCHW_SINTC_UART0                (1<<INTCHW_SINTC_UART0_BITNUM)
+#define INTCHW_SINTC_WDOG                 (1<<INTCHW_SINTC_WDOG_BITNUM)
+
+/* PL192 Vectored Interrupt Controller (VIC) layout */
+#define INTCHW_IRQSTATUS      0x00      /* IRQ status register */
+#define INTCHW_FIQSTATUS      0x04      /* FIQ status register */
+#define INTCHW_RAWINTR        0x08      /* Raw Interrupt Status register */
+#define INTCHW_INTSELECT      0x0c      /* Interrupt Select Register */
+#define INTCHW_INTENABLE      0x10      /* Interrupt Enable Register */
+#define INTCHW_INTENCLEAR     0x14      /* Interrupt Enable Clear Register */
+#define INTCHW_SOFTINT        0x18      /* Soft Interrupt Register */
+#define INTCHW_SOFTINTCLEAR   0x1c      /* Soft Interrupt Clear Register */
+#define INTCHW_PROTECTION     0x20      /* Protection Enable Register */
+#define INTCHW_SWPRIOMASK     0x24      /* Software Priority Mask Register */
+#define INTCHW_PRIODAISY      0x28      /* Priority Daisy Chain Register */
+#define INTCHW_VECTADDR0      0x100     /* Vector Address Registers */
+#define INTCHW_VECTPRIO0      0x200     /* Vector Priority Registers 0-31 */
+#define INTCHW_ADDRESS        0xf00     /* Vector Address Register 0-31 */
+#define INTCHW_PID            0xfe0     /* Peripheral ID Register 0-3 */
+#define INTCHW_PCELLID        0xff0     /* PrimeCell ID Register 0-3 */
+
+/* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
+/*                intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
+/*                uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */
+/*                uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */
+
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+/* Clear one or more IRQ interrupts. */
+static inline void intcHw_irq_disable(void *basep, uint32_t mask)
+{
+        __REG32(basep + INTCHW_INTENCLEAR) = mask;
+}
+
+/* Enables one or more IRQ interrupts. */
+static inline void intcHw_irq_enable(void *basep, uint32_t mask)
+{
+        __REG32(basep + INTCHW_INTENABLE) = mask;
+}
+
+#endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
new file mode 100644
index 000000000000..86bb58d4f58c
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    mm_addr.h
+*
+*  @brief   Memory Map address defintions
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+
+#ifndef _MM_ADDR_H
+#define _MM_ADDR_H
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#if !defined(CSP_SIMULATION)
+#include <cfg_global.h>
+#endif
+
+/* ---- Public Constants and Types --------------------------------------- */
+
+/*  Memory Map address definitions */
+
+#define MM_ADDR_DDR                0x00000000
+
+#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000   /* 16 MB - Reserved external memory for VPM use */
+
+#define MM_ADDR_IO_FLASHC          0x20000000
+#define MM_ADDR_IO_BROM            0x30000000
+#define MM_ADDR_IO_ARAM            0x30100000   /* 64 KB - extra cycle latency - WS switch */
+#define MM_ADDR_IO_DMA0            0x30200000
+#define MM_ADDR_IO_DMA1            0x30300000
+#define MM_ADDR_IO_ESW             0x30400000
+#define MM_ADDR_IO_CLCD            0x30500000
+#define MM_ADDR_IO_PIF             0x30580000
+#define MM_ADDR_IO_APM             0x30600000
+#define MM_ADDR_IO_SPUM            0x30700000
+#define MM_ADDR_IO_VPM_PROG        0x30800000
+#define MM_ADDR_IO_VPM_DATA        0x30A00000
+#define MM_ADDR_IO_VRAM            0x40000000   /* 64 KB  - security block in front of it */
+#define MM_ADDR_IO_CHIPC           0x80000000
+#define MM_ADDR_IO_UMI             0x80001000
+#define MM_ADDR_IO_NAND            0x80001800
+#define MM_ADDR_IO_LEDM            0x80002000
+#define MM_ADDR_IO_PWM             0x80002040
+#define MM_ADDR_IO_VINTC           0x80003000
+#define MM_ADDR_IO_GPIO0           0x80004000
+#define MM_ADDR_IO_GPIO1           0x80004800
+#define MM_ADDR_IO_I2CS            0x80005000
+#define MM_ADDR_IO_SPIS            0x80006000
+#define MM_ADDR_IO_HPM             0x80007400
+#define MM_ADDR_IO_HPM_REMAP       0x80007800
+#define MM_ADDR_IO_TZPC            0x80008000
+#define MM_ADDR_IO_MPU             0x80009000
+#define MM_ADDR_IO_SPUMP           0x8000a000
+#define MM_ADDR_IO_PKA             0x8000b000
+#define MM_ADDR_IO_RNG             0x8000c000
+#define MM_ADDR_IO_KEYC            0x8000d000
+#define MM_ADDR_IO_BBL             0x8000e000
+#define MM_ADDR_IO_OTP             0x8000f000
+#define MM_ADDR_IO_I2S0            0x80010000
+#define MM_ADDR_IO_I2S1            0x80011000
+#define MM_ADDR_IO_UARTA           0x80012000
+#define MM_ADDR_IO_UARTB           0x80013000
+#define MM_ADDR_IO_I2CH            0x80014020
+#define MM_ADDR_IO_SPIH            0x80015000
+#define MM_ADDR_IO_TSC             0x80016000
+#define MM_ADDR_IO_TMR             0x80017000
+#define MM_ADDR_IO_WATCHDOG        0x80017800
+#define MM_ADDR_IO_ETM             0x80018000
+#define MM_ADDR_IO_DDRC            0x80019000
+#define MM_ADDR_IO_SINTC           0x80100000
+#define MM_ADDR_IO_INTC0           0x80200000
+#define MM_ADDR_IO_INTC1           0x80201000
+#define MM_ADDR_IO_GE              0x80300000
+#define MM_ADDR_IO_USB_CTLR0       0x80400000
+#define MM_ADDR_IO_USB_CTLR1       0x80410000
+#define MM_ADDR_IO_USB_PHY         0x80420000
+#define MM_ADDR_IO_SDIOH0          0x80500000
+#define MM_ADDR_IO_SDIOH1          0x80600000
+#define MM_ADDR_IO_VDEC            0x80700000
+
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+
+#endif /* _MM_ADDR_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
new file mode 100644
index 000000000000..de92ec6a01aa
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
@@ -0,0 +1,147 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    mm_io.h
+*
+*  @brief   Memory Map I/O definitions
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+
+#ifndef _MM_IO_H
+#define _MM_IO_H
+
+/* ---- Include Files ---------------------------------------------------- */
+#include <mach/csp/mm_addr.h>
+
+#if !defined(CSP_SIMULATION)
+#include <cfg_global.h>
+#endif
+
+/* ---- Public Constants and Types --------------------------------------- */
+
+#if defined(CONFIG_MMU)
+
+/* This macro is referenced in <mach/io.h>
+ * Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx
+ * This macro is referenced in <asm/arch/io.h>
+ *
+ * Assume VPM address is the last x MB of memory.  For VPM, map to
+ * 0xf0000000 and up.
+ */
+
+#ifndef MM_IO_PHYS_TO_VIRT
+#ifdef __ASSEMBLY__
+#define MM_IO_PHYS_TO_VIRT(phys)       (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
+#else
+#define MM_IO_PHYS_TO_VIRT(phys)       (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
+                        (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
+#endif
+#endif
+
+/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */
+
+#ifndef MM_IO_VIRT_TO_PHYS
+#ifdef __ASSEMBLY__
+#define MM_IO_VIRT_TO_PHYS(virt)       ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
+#else
+#define MM_IO_VIRT_TO_PHYS(virt)       (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
+                        ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
+#endif
+#endif
+
+#else
+
+#ifndef MM_IO_PHYS_TO_VIRT
+#define MM_IO_PHYS_TO_VIRT(phys)       (phys)
+#endif
+
+#ifndef MM_IO_VIRT_TO_PHYS
+#define MM_IO_VIRT_TO_PHYS(virt)       (virt)
+#endif
+
+#endif
+
+/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */
+#define MM_IO_BASE_FLASHC              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC)
+#define MM_IO_BASE_NAND                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND)
+#define MM_IO_BASE_UMI                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI)
+
+#define MM_IO_START MM_ADDR_IO_FLASHC   /* Physical beginning of IO mapped memory */
+#define MM_IO_BASE  MM_IO_BASE_FLASHC   /* Virtual beginning of IO mapped memory */
+
+#define MM_IO_BASE_BROM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM)
+#define MM_IO_BASE_ARAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM)
+#define MM_IO_BASE_DMA0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0)
+#define MM_IO_BASE_DMA1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1)
+#define MM_IO_BASE_ESW                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW)
+#define MM_IO_BASE_CLCD                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD)
+#define MM_IO_BASE_PIF                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF)
+#define MM_IO_BASE_APM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM)
+#define MM_IO_BASE_SPUM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM)
+#define MM_IO_BASE_VPM_PROG            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG)
+#define MM_IO_BASE_VPM_DATA            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA)
+
+#define MM_IO_BASE_VRAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM)
+
+#define MM_IO_BASE_CHIPC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC)
+#define MM_IO_BASE_DDRC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC)
+#define MM_IO_BASE_LEDM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM)
+#define MM_IO_BASE_PWM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM)
+#define MM_IO_BASE_VINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC)
+#define MM_IO_BASE_GPIO0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0)
+#define MM_IO_BASE_GPIO1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1)
+#define MM_IO_BASE_TMR                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR)
+#define MM_IO_BASE_WATCHDOG            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG)
+#define MM_IO_BASE_ETM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM)
+#define MM_IO_BASE_HPM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM)
+#define MM_IO_BASE_HPM_REMAP           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP)
+#define MM_IO_BASE_TZPC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC)
+#define MM_IO_BASE_MPU                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU)
+#define MM_IO_BASE_SPUMP               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP)
+#define MM_IO_BASE_PKA                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA)
+#define MM_IO_BASE_RNG                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG)
+#define MM_IO_BASE_KEYC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC)
+#define MM_IO_BASE_BBL                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL)
+#define MM_IO_BASE_OTP                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP)
+#define MM_IO_BASE_I2S0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0)
+#define MM_IO_BASE_I2S1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1)
+#define MM_IO_BASE_UARTA               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA)
+#define MM_IO_BASE_UARTB               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB)
+#define MM_IO_BASE_I2CH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH)
+#define MM_IO_BASE_SPIH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH)
+#define MM_IO_BASE_TSC                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC)
+#define MM_IO_BASE_I2CS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS)
+#define MM_IO_BASE_SPIS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS)
+#define MM_IO_BASE_SINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC)
+#define MM_IO_BASE_INTC0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0)
+#define MM_IO_BASE_INTC1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1)
+#define MM_IO_BASE_GE                  MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE)
+#define MM_IO_BASE_USB_CTLR0           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0)
+#define MM_IO_BASE_USB_CTLR1           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1)
+#define MM_IO_BASE_USB_PHY             MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY)
+#define MM_IO_BASE_SDIOH0              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0)
+#define MM_IO_BASE_SDIOH1              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1)
+#define MM_IO_BASE_VDEC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC)
+
+#define MM_IO_BASE_VPM_EXTMEM_RSVD     MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD)
+
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+
+#endif /* _MM_IO_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
new file mode 100644
index 000000000000..d15f5f3ec2d8
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
@@ -0,0 +1,100 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    secHw_def.h
+*
+*  @brief   Definitions for configuring/testing secure blocks
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+
+#ifndef SECHW_DEF_H
+#define SECHW_DEF_H
+
+#include <mach/csp/mm_io.h>
+
+/* Bit mask for various secure device */
+#define secHw_BLK_MASK_CHIP_CONTROL     0x00000001
+#define secHw_BLK_MASK_KEY_SCAN         0x00000002
+#define secHw_BLK_MASK_TOUCH_SCREEN     0x00000004
+#define secHw_BLK_MASK_UART0            0x00000008
+#define secHw_BLK_MASK_UART1            0x00000010
+#define secHw_BLK_MASK_WATCHDOG         0x00000020
+#define secHw_BLK_MASK_SPUM             0x00000040
+#define secHw_BLK_MASK_DDR2             0x00000080
+#define secHw_BLK_MASK_EXT_MEM          0x00000100
+#define secHw_BLK_MASK_ESW              0x00000200
+#define secHw_BLK_MASK_SPU              0x00010000
+#define secHw_BLK_MASK_PKA              0x00020000
+#define secHw_BLK_MASK_RNG              0x00040000
+#define secHw_BLK_MASK_RTC              0x00080000
+#define secHw_BLK_MASK_OTP              0x00100000
+#define secHw_BLK_MASK_BOOT             0x00200000
+#define secHw_BLK_MASK_MPU              0x00400000
+#define secHw_BLK_MASK_TZCTRL           0x00800000
+#define secHw_BLK_MASK_INTR             0x01000000
+
+/* Trustzone register set */
+typedef struct {
+        volatile uint32_t status;       /* read only - reflects status of writes of 2 write registers */
+        volatile uint32_t setUnsecure;  /* write only. reads back as 0 */
+        volatile uint32_t setSecure;    /* write only. reads back as 0 */
+} secHw_TZREG_t;
+
+/* There are 2 register sets. The first is for the lower 16 bits, the 2nd */
+/* is for the higher 16 bits. */
+
+typedef enum {
+        secHw_IDX_LS = 0,
+        secHw_IDX_MS = 1,
+        secHw_IDX_NUM
+} secHw_IDX_e;
+
+typedef struct {
+        volatile secHw_TZREG_t reg[secHw_IDX_NUM];
+} secHw_REGS_t;
+
+/****************************************************************************/
+/**
+*  @brief  Configures a device as a secure device
+*
+*/
+/****************************************************************************/
+static inline void secHw_setSecure(uint32_t mask        /*  mask of type secHw_BLK_MASK_XXXXXX */
+    );
+
+/****************************************************************************/
+/**
+*  @brief  Configures a device as a non-secure device
+*
+*/
+/****************************************************************************/
+static inline void secHw_setUnsecure(uint32_t mask      /*  mask of type secHw_BLK_MASK_XXXXXX */
+    );
+
+/****************************************************************************/
+/**
+*  @brief  Get the trustzone status for all components. 1 = non-secure, 0 = secure
+*
+*/
+/****************************************************************************/
+static inline uint32_t secHw_getStatus(void);
+
+#include <mach/csp/secHw_inline.h>
+
+#endif /* SECHW_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
new file mode 100644
index 000000000000..9cd6a032ab71
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
@@ -0,0 +1,79 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    secHw_inline.h
+*
+*  @brief   Definitions for configuring/testing secure blocks
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+
+#ifndef SECHW_INLINE_H
+#define SECHW_INLINE_H
+
+/****************************************************************************/
+/**
+*  @brief  Configures a device as a secure device
+*
+*/
+/****************************************************************************/
+static inline void secHw_setSecure(uint32_t mask        /*  mask of type secHw_BLK_MASK_XXXXXX */
+    ) {
+        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+
+        if (mask & 0x0000FFFF) {
+                regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
+        }
+
+        if (mask & 0xFFFF0000) {
+                regp->reg[secHw_IDX_MS].setSecure = mask >> 16;
+        }
+}
+
+/****************************************************************************/
+/**
+*  @brief  Configures a device as a non-secure device
+*
+*/
+/****************************************************************************/
+static inline void secHw_setUnsecure(uint32_t mask      /*  mask of type secHw_BLK_MASK_XXXXXX */
+    ) {
+        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+
+        if (mask & 0x0000FFFF) {
+                regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
+        }
+        if (mask & 0xFFFF0000) {
+                regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
+        }
+}
+
+/****************************************************************************/
+/**
+*  @brief  Get the trustzone status for all components. 1 = non-secure, 0 = secure
+*
+*/
+/****************************************************************************/
+static inline uint32_t secHw_getStatus(void)
+{
+        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+
+        return (regp->reg[1].status << 16) + regp->reg[0].status;
+}
+
+#endif /* SECHW_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
new file mode 100644
index 000000000000..3080ac7239a1
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
@@ -0,0 +1,82 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*  @file    tmrHw_reg.h
+*
+*  @brief   Definitions for low level Timer registers
+*
+*/
+/****************************************************************************/
+#ifndef _TMRHW_REG_H
+#define _TMRHW_REG_H
+
+#include <mach/csp/mm_io.h>
+#include <mach/csp/hw_cfg.h>
+/* Base address */
+#define tmrHw_MODULE_BASE_ADDR          MM_IO_BASE_TMR
+
+/*
+This platform has four different timers running at different clock speed
+
+Timer one   (Timer ID 0) runs at  25 MHz
+Timer two   (Timer ID 1) runs at  25 MHz
+Timer three (Timer ID 2) runs at 150 MHz
+Timer four  (Timer ID 3) runs at 150 MHz
+*/
+#define tmrHw_LOW_FREQUENCY_MHZ         25      /* Always 25MHz from XTAL */
+#define tmrHw_LOW_FREQUENCY_HZ          25000000
+
+#if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107)
+#define tmrHw_HIGH_FREQUENCY_MHZ        150     /* Always 150MHz for FPGA */
+#define tmrHw_HIGH_FREQUENCY_HZ         150000000
+#else
+#define tmrHw_HIGH_FREQUENCY_HZ         HW_CFG_BUS_CLK_HZ
+#define tmrHw_HIGH_FREQUENCY_MHZ        (HW_CFG_BUS_CLK_HZ / 1000000)
+#endif
+
+#define tmrHw_LOW_RESOLUTION_CLOCK      tmrHw_LOW_FREQUENCY_HZ
+#define tmrHw_HIGH_RESOLUTION_CLOCK     tmrHw_HIGH_FREQUENCY_HZ
+#define tmrHw_MAX_COUNT                 (0xFFFFFFFF)    /* maximum number of count a timer can count */
+#define tmrHw_TIMER_NUM_COUNT           (4)     /* Number of timer module supported */
+
+typedef struct {
+        uint32_t LoadValue;     /* Load value for timer */
+        uint32_t CurrentValue;  /* Current value for timer */
+        uint32_t Control;       /* Control register */
+        uint32_t InterruptClear;        /* Interrupt clear register */
+        uint32_t RawInterruptStatus;    /* Raw interrupt status */
+        uint32_t InterruptStatus;       /* Masked interrupt status */
+        uint32_t BackgroundLoad;        /* Background load value */
+        uint32_t padding;       /* Padding register */
+} tmrHw_REG_t;
+
+/* Control bot masks */
+#define tmrHw_CONTROL_TIMER_ENABLE            0x00000080
+#define tmrHw_CONTROL_PERIODIC                0x00000040
+#define tmrHw_CONTROL_INTERRUPT_ENABLE        0x00000020
+#define tmrHw_CONTROL_PRESCALE_MASK           0x0000000C
+#define tmrHw_CONTROL_PRESCALE_1              0x00000000
+#define tmrHw_CONTROL_PRESCALE_16             0x00000004
+#define tmrHw_CONTROL_PRESCALE_256            0x00000008
+#define tmrHw_CONTROL_32BIT                   0x00000002
+#define tmrHw_CONTROL_ONESHOT                 0x00000001
+#define tmrHw_CONTROL_FREE_RUNNING            0x00000000
+
+#define tmrHw_CONTROL_MODE_MASK               (tmrHw_CONTROL_PERIODIC | tmrHw_CONTROL_ONESHOT)
+
+#define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR)
+
+#endif /* _TMRHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h
new file mode 100644
index 000000000000..847980c85c88
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/dma.h
@@ -0,0 +1,826 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*   @file   dma.h
+*
+*   @brief  API definitions for the linux DMA interface.
+*/
+/****************************************************************************/
+
+#if !defined(ASM_ARM_ARCH_BCMRING_DMA_H)
+#define ASM_ARM_ARCH_BCMRING_DMA_H
+
+/* ---- Include Files ---------------------------------------------------- */
+
+#include <linux/kernel.h>
+#include <linux/wait.h>
+#include <linux/semaphore.h>
+#include <csp/dmacHw.h>
+#include <mach/timer.h>
+#include <linux/scatterlist.h>
+#include <linux/dma-mapping.h>
+#include <linux/mm.h>
+#include <linux/vmalloc.h>
+#include <linux/pagemap.h>
+
+/* ---- Constants and Types ---------------------------------------------- */
+
+/* If DMA_DEBUG_TRACK_RESERVATION is set to a non-zero value, then the filename */
+/* and line number of the reservation request will be recorded in the channel table */
+
+#define DMA_DEBUG_TRACK_RESERVATION   1
+
+#define DMA_NUM_CONTROLLERS     2
+#define DMA_NUM_CHANNELS        8       /* per controller */
+
+typedef enum {
+        DMA_DEVICE_MEM_TO_MEM,  /* For memory to memory transfers */
+        DMA_DEVICE_I2S0_DEV_TO_MEM,
+        DMA_DEVICE_I2S0_MEM_TO_DEV,
+        DMA_DEVICE_I2S1_DEV_TO_MEM,
+        DMA_DEVICE_I2S1_MEM_TO_DEV,
+        DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM,
+        DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV,
+        DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM,
+        DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV,
+        DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM,      /* Additional mic input for beam-forming */
+        DMA_DEVICE_APM_PCM0_DEV_TO_MEM,
+        DMA_DEVICE_APM_PCM0_MEM_TO_DEV,
+        DMA_DEVICE_APM_PCM1_DEV_TO_MEM,
+        DMA_DEVICE_APM_PCM1_MEM_TO_DEV,
+        DMA_DEVICE_SPUM_DEV_TO_MEM,
+        DMA_DEVICE_SPUM_MEM_TO_DEV,
+        DMA_DEVICE_SPIH_DEV_TO_MEM,
+        DMA_DEVICE_SPIH_MEM_TO_DEV,
+        DMA_DEVICE_UART_A_DEV_TO_MEM,
+        DMA_DEVICE_UART_A_MEM_TO_DEV,
+        DMA_DEVICE_UART_B_DEV_TO_MEM,
+        DMA_DEVICE_UART_B_MEM_TO_DEV,
+        DMA_DEVICE_PIF_MEM_TO_DEV,
+        DMA_DEVICE_PIF_DEV_TO_MEM,
+        DMA_DEVICE_ESW_DEV_TO_MEM,
+        DMA_DEVICE_ESW_MEM_TO_DEV,
+        DMA_DEVICE_VPM_MEM_TO_MEM,
+        DMA_DEVICE_CLCD_MEM_TO_MEM,
+        DMA_DEVICE_NAND_MEM_TO_MEM,
+        DMA_DEVICE_MEM_TO_VRAM,
+        DMA_DEVICE_VRAM_TO_MEM,
+
+        /* Add new entries before this line. */
+
+        DMA_NUM_DEVICE_ENTRIES,
+        DMA_DEVICE_NONE = 0xff, /* Special value to indicate that no device is currently assigned. */
+
+} DMA_Device_t;
+
+/****************************************************************************
+*
+*   The DMA_Handle_t is the primary object used by callers of the API.
+*
+*****************************************************************************/
+
+#define DMA_INVALID_HANDLE  ((DMA_Handle_t) -1)
+
+typedef int DMA_Handle_t;
+
+/****************************************************************************
+*
+*   The DMA_DescriptorRing_t contains a ring of descriptors which is used
+*   to point to regions of memory.
+*
+*****************************************************************************/
+
+typedef struct {
+        void *virtAddr;         /* Virtual Address of the descriptor ring */
+        dma_addr_t physAddr;    /* Physical address of the descriptor ring */
+        int descriptorsAllocated;       /* Number of descriptors allocated in the descriptor ring */
+        size_t bytesAllocated;  /* Number of bytes allocated in the descriptor ring */
+
+} DMA_DescriptorRing_t;
+
+/****************************************************************************
+*
+*   The DMA_MemType_t and DMA_MemMap_t are helper structures used to setup
+*   DMA chains from a variety of memory sources.
+*
+*****************************************************************************/
+
+#define DMA_MEM_MAP_MIN_SIZE    4096    /* Pages less than this size are better */
+                                        /* off not being DMA'd. */
+
+typedef enum {
+        DMA_MEM_TYPE_NONE,      /* Not a valid setting */
+        DMA_MEM_TYPE_VMALLOC,   /* Memory came from vmalloc call */
+        DMA_MEM_TYPE_KMALLOC,   /* Memory came from kmalloc call */
+        DMA_MEM_TYPE_DMA,       /* Memory came from dma_alloc_xxx call */
+        DMA_MEM_TYPE_USER,      /* Memory came from user space. */
+
+} DMA_MemType_t;
+
+/* A segment represents a physically and virtually contiguous chunk of memory. */
+/* i.e. each segment can be DMA'd */
+/* A user of the DMA code will add memory regions. Each region may need to be */
+/* represented by one or more segments. */
+
+typedef struct {
+        void *virtAddr;         /* Virtual address used for this segment */
+        dma_addr_t physAddr;    /* Physical address this segment maps to */
+        size_t numBytes;        /* Size of the segment, in bytes */
+
+} DMA_Segment_t;
+
+/* A region represents a virtually contiguous chunk of memory, which may be */
+/* made up of multiple segments. */
+
+typedef struct {
+        DMA_MemType_t memType;
+        void *virtAddr;
+        size_t numBytes;
+
+        /* Each region (virtually contiguous) consists of one or more segments. Each */
+        /* segment is virtually and physically contiguous. */
+
+        int numSegmentsUsed;
+        int numSegmentsAllocated;
+        DMA_Segment_t *segment;
+
+        /* When a region corresponds to user memory, we need to lock all of the pages */
+        /* down before we can figure out the physical addresses. The lockedPage array contains */
+        /* the pages that were locked, and which subsequently need to be unlocked once the */
+        /* memory is unmapped. */
+
+        unsigned numLockedPages;
+        struct page **lockedPages;
+
+} DMA_Region_t;
+
+typedef struct {
+        int inUse;              /* Is this mapping currently being used? */
+        struct semaphore lock;  /* Acquired when using this structure */
+        enum dma_data_direction dir;    /* Direction this transfer is intended for */
+
+        /* In the event that we're mapping user memory, we need to know which task */
+        /* the memory is for, so that we can obtain the correct mm locks. */
+
+        struct task_struct *userTask;
+
+        int numRegionsUsed;
+        int numRegionsAllocated;
+        DMA_Region_t *region;
+
+} DMA_MemMap_t;
+
+/****************************************************************************
+*
+*   The DMA_DeviceAttribute_t contains information which describes a
+*   particular DMA device (or peripheral).
+*
+*   It is anticipated that the arrary of DMA_DeviceAttribute_t's will be
+*   statically initialized.
+*
+*****************************************************************************/
+
+/* The device handler is called whenever a DMA operation completes. The reaon */
+/* for it to be called will be a bitmask with one or more of the following bits */
+/* set. */
+
+#define DMA_HANDLER_REASON_BLOCK_COMPLETE       dmacHw_INTERRUPT_STATUS_BLOCK
+#define DMA_HANDLER_REASON_TRANSFER_COMPLETE    dmacHw_INTERRUPT_STATUS_TRANS
+#define DMA_HANDLER_REASON_ERROR                dmacHw_INTERRUPT_STATUS_ERROR
+
+typedef void (*DMA_DeviceHandler_t) (DMA_Device_t dev, int reason,
+                                     void *userData);
+
+#define DMA_DEVICE_FLAG_ON_DMA0             0x00000001
+#define DMA_DEVICE_FLAG_ON_DMA1             0x00000002
+#define DMA_DEVICE_FLAG_PORT_PER_DMAC       0x00000004  /* If set, it means that the port used on DMAC0 is different from the port used on DMAC1 */
+#define DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST    0x00000008  /* If set, allocate from DMA1 before allocating from DMA0 */
+#define DMA_DEVICE_FLAG_IS_DEDICATED        0x00000100
+#define DMA_DEVICE_FLAG_NO_ISR              0x00000200
+#define DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO    0x00000400
+#define DMA_DEVICE_FLAG_IN_USE              0x00000800  /* If set, device is in use on a channel */
+
+/* Note: Some DMA devices can be used from multiple DMA Controllers. The bitmask is used to */
+/*       determine which DMA controllers a given device can be used from, and the interface */
+/*       array determeines the actual interface number to use for a given controller. */
+
+typedef struct {
+        uint32_t flags;         /* Bitmask of DMA_DEVICE_FLAG_xxx constants */
+        uint8_t dedicatedController;    /* Controller number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
+        uint8_t dedicatedChannel;       /* Channel number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
+        const char *name;       /* Will show up in the /proc entry */
+
+        uint32_t dmacPort[DMA_NUM_CONTROLLERS]; /* Specifies the port number when DMA_DEVICE_FLAG_PORT_PER_DMAC flag is set */
+
+        dmacHw_CONFIG_t config; /* Configuration to use when DMA'ing using this device */
+
+        void *userData;         /* Passed to the devHandler */
+        DMA_DeviceHandler_t devHandler; /* Called when DMA operations finish. */
+
+        timer_tick_count_t transferStartTime;   /* Time the current transfer was started */
+
+        /* The following statistical information will be collected and presented in a proc entry. */
+        /* Note: With a contiuous bandwidth of 1 Gb/sec, it would take 584 years to overflow */
+        /*       a 64 bit counter. */
+
+        uint64_t numTransfers;  /* Number of DMA transfers performed */
+        uint64_t transferTicks; /* Total time spent doing DMA transfers (measured in timer_tick_count_t's) */
+        uint64_t transferBytes; /* Total bytes transferred */
+        uint32_t timesBlocked;  /* Number of times a channel was unavailable */
+        uint32_t numBytes;      /* Last transfer size */
+
+        /* It's not possible to free memory which is allocated for the descriptors from within */
+        /* the ISR. So make the presumption that a given device will tend to use the */
+        /* same sized buffers over and over again, and we keep them around. */
+
+        DMA_DescriptorRing_t ring;      /* Ring of descriptors allocated for this device */
+
+        /* We stash away some of the information from the previous transfer. If back-to-back */
+        /* transfers are performed from the same buffer, then we don't have to keep re-initializing */
+        /* the descriptor buffers. */
+
+        uint32_t prevNumBytes;
+        dma_addr_t prevSrcData;
+        dma_addr_t prevDstData;
+
+} DMA_DeviceAttribute_t;
+
+/****************************************************************************
+*
+*   DMA_Channel_t, DMA_Controller_t, and DMA_State_t are really internal
+*   data structures and don't belong in this header file, but are included
+*   merely for discussion.
+*
+*   By the time this is implemented, these structures will be moved out into
+*   the appropriate C source file instead.
+*
+*****************************************************************************/
+
+/****************************************************************************
+*
+*   The DMA_Channel_t contains state information about each DMA channel. Some
+*   of the channels are dedicated. Non-dedicated channels are shared
+*   amongst the other devices.
+*
+*****************************************************************************/
+
+#define DMA_CHANNEL_FLAG_IN_USE         0x00000001
+#define DMA_CHANNEL_FLAG_IS_DEDICATED   0x00000002
+#define DMA_CHANNEL_FLAG_NO_ISR         0x00000004
+#define DMA_CHANNEL_FLAG_LARGE_FIFO     0x00000008
+
+typedef struct {
+        uint32_t flags;         /* bitmask of DMA_CHANNEL_FLAG_xxx constants */
+        DMA_Device_t devType;   /* Device this channel is currently reserved for */
+        DMA_Device_t lastDevType;       /* Device type that used this previously */
+        char name[20];          /* Name passed onto request_irq */
+
+#if (DMA_DEBUG_TRACK_RESERVATION)
+        const char *fileName;   /* Place where channel reservation took place */
+        int lineNum;            /* Place where channel reservation took place */
+#endif
+        dmacHw_HANDLE_t dmacHwHandle;   /* low level channel handle. */
+
+} DMA_Channel_t;
+
+/****************************************************************************
+*
+*   The DMA_Controller_t contains state information about each DMA controller.
+*
+*   The freeChannelQ is stored in the controller data structure rather than
+*   the channel data structure since several of the devices are accessible
+*   from multiple controllers, and there is no way to know which controller
+*   will become available first.
+*
+*****************************************************************************/
+
+typedef struct {
+        DMA_Channel_t channel[DMA_NUM_CHANNELS];
+
+} DMA_Controller_t;
+
+/****************************************************************************
+*
+*   The DMA_Global_t contains all of the global state information used by
+*   the DMA code.
+*
+*   Callers which need to allocate a shared channel will be queued up
+*   on the freeChannelQ until a channel becomes available.
+*
+*****************************************************************************/
+
+typedef struct {
+        struct semaphore lock;  /* acquired when manipulating table entries */
+        wait_queue_head_t freeChannelQ;
+
+        DMA_Controller_t controller[DMA_NUM_CONTROLLERS];
+
+} DMA_Global_t;
+
+/* ---- Variable Externs ------------------------------------------------- */
+
+extern DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES];
+
+/* ---- Function Prototypes ---------------------------------------------- */
+
+#if defined(__KERNEL__)
+
+/****************************************************************************/
+/**
+*   Initializes the DMA module.
+*
+*   @return
+*       0       - Success
+*       < 0     - Error
+*/
+/****************************************************************************/
+
+int dma_init(void);
+
+#if (DMA_DEBUG_TRACK_RESERVATION)
+DMA_Handle_t dma_request_channel_dbg(DMA_Device_t dev, const char *fileName,
+                                     int lineNum);
+#define dma_request_channel(dev)  dma_request_channel_dbg(dev, __FILE__, __LINE__)
+#else
+
+/****************************************************************************/
+/**
+*   Reserves a channel for use with @a dev. If the device is setup to use
+*   a shared channel, then this function will block until a free channel
+*   becomes available.
+*
+*   @return
+*       >= 0    - A valid DMA Handle.
+*       -EBUSY  - Device is currently being used.
+*       -ENODEV - Device handed in is invalid.
+*/
+/****************************************************************************/
+
+DMA_Handle_t dma_request_channel(DMA_Device_t dev       /* Device to use with the allocated channel. */
+    );
+#endif
+
+/****************************************************************************/
+/**
+*   Frees a previously allocated DMA Handle.
+*
+*   @return
+*        0      - DMA Handle was released successfully.
+*       -EINVAL - Invalid DMA handle
+*/
+/****************************************************************************/
+
+int dma_free_channel(DMA_Handle_t channel       /* DMA handle. */
+    );
+
+/****************************************************************************/
+/**
+*   Determines if a given device has been configured as using a shared
+*   channel.
+*
+*   @return boolean
+*       0           Device uses a dedicated channel
+*       non-zero    Device uses a shared channel
+*/
+/****************************************************************************/
+
+int dma_device_is_channel_shared(DMA_Device_t dev       /* Device to check. */
+    );
+
+/****************************************************************************/
+/**
+*   Allocates memory to hold a descriptor ring. The descriptor ring then
+*   needs to be populated by making one or more calls to
+*   dna_add_descriptors.
+*
+*   The returned descriptor ring will be automatically initialized.
+*
+*   @return
+*       0           Descriptor ring was allocated successfully
+*       -ENOMEM     Unable to allocate memory for the desired number of descriptors.
+*/
+/****************************************************************************/
+
+int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,       /* Descriptor ring to populate */
+                              int numDescriptors        /* Number of descriptors that need to be allocated. */
+    );
+
+/****************************************************************************/
+/**
+*   Releases the memory which was previously allocated for a descriptor ring.
+*/
+/****************************************************************************/
+
+void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring        /* Descriptor to release */
+    );
+
+/****************************************************************************/
+/**
+*   Initializes a descriptor ring, so that descriptors can be added to it.
+*   Once a descriptor ring has been allocated, it may be reinitialized for
+*   use with additional/different regions of memory.
+*
+*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
+*   initialize the ring with a smaller number of descriptors. The amount
+*   of memory allocated for the descriptor ring will not be reduced, and
+*   the descriptor ring may be reinitialized later
+*
+*   @return
+*       0           Descriptor ring was initialized successfully
+*       -ENOMEM     The descriptor which was passed in has insufficient space
+*                   to hold the desired number of descriptors.
+*/
+/****************************************************************************/
+
+int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,        /* Descriptor ring to initialize */
+                             int numDescriptors /* Number of descriptors to initialize. */
+    );
+
+/****************************************************************************/
+/**
+*   Determines the number of descriptors which would be required for a
+*   transfer of the indicated memory region.
+*
+*   This function also needs to know which DMA device this transfer will
+*   be destined for, so that the appropriate DMA configuration can be retrieved.
+*   DMA parameters such as transfer width, and whether this is a memory-to-memory
+*   or memory-to-peripheral, etc can all affect the actual number of descriptors
+*   required.
+*
+*   @return
+*       > 0     Returns the number of descriptors required for the indicated transfer
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+
+int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */
+                                   dma_addr_t srcData,  /* Place to get data to write to device */
+                                   dma_addr_t dstData,  /* Pointer to device data address */
+                                   size_t numBytes      /* Number of bytes to transfer to the device */
+    );
+
+/****************************************************************************/
+/**
+*   Adds a region of memory to the descriptor ring. Note that it may take
+*   multiple descriptors for each region of memory. It is the callers
+*   responsibility to allocate a sufficiently large descriptor ring.
+*
+*   @return
+*       0       Descriptors were added successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+
+int dma_add_descriptors(DMA_DescriptorRing_t *ring,     /* Descriptor ring to add descriptors to */
+                        DMA_Device_t device,    /* DMA Device that descriptors are for */
+                        dma_addr_t srcData,     /* Place to get data (memory or device) */
+                        dma_addr_t dstData,     /* Place to put data (memory or device) */
+                        size_t numBytes /* Number of bytes to transfer to the device */
+    );
+
+/****************************************************************************/
+/**
+*   Sets the descriptor ring associated with a device.
+*
+*   Once set, the descriptor ring will be associated with the device, even
+*   across channel request/free calls. Passing in a NULL descriptor ring
+*   will release any descriptor ring currently associated with the device.
+*
+*   Note: If you call dma_transfer, or one of the other dma_alloc_ functions
+*         the descriptor ring may be released and reallocated.
+*
+*   Note: This function will release the descriptor memory for any current
+*         descriptor ring associated with this device.
+*/
+/****************************************************************************/
+
+int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */
+                                   DMA_DescriptorRing_t *ring   /* Descriptor ring to add descriptors to */
+    );
+
+/****************************************************************************/
+/**
+*   Retrieves the descriptor ring associated with a device.
+*/
+/****************************************************************************/
+
+int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */
+                                   DMA_DescriptorRing_t *ring   /* Place to store retrieved ring */
+    );
+
+/****************************************************************************/
+/**
+*   Allocates buffers for the descriptors. This is normally done automatically
+*   but needs to be done explicitly when initiating a dma from interrupt
+*   context.
+*
+*   @return
+*       0       Descriptors were allocated successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+
+int dma_alloc_descriptors(DMA_Handle_t handle,  /* DMA Handle */
+                          dmacHw_TRANSFER_TYPE_e transferType,  /* Type of transfer being performed */
+                          dma_addr_t srcData,   /* Place to get data to write to device */
+                          dma_addr_t dstData,   /* Pointer to device data address */
+                          size_t numBytes       /* Number of bytes to transfer to the device */
+    );
+
+/****************************************************************************/
+/**
+*   Allocates and sets up descriptors for a double buffered circular buffer.
+*
+*   This is primarily intended to be used for things like the ingress samples
+*   from a microphone.
+*
+*   @return
+*       > 0     Number of descriptors actually allocated.
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+
+int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,       /* DMA Handle */
+                                     dma_addr_t srcData,        /* Physical address of source data */
+                                     dma_addr_t dstData1,       /* Physical address of first destination buffer */
+                                     dma_addr_t dstData2,       /* Physical address of second destination buffer */
+                                     size_t numBytes    /* Number of bytes in each destination buffer */
+    );
+
+/****************************************************************************/
+/**
+*   Initializes a DMA_MemMap_t data structure
+*/
+/****************************************************************************/
+
+int dma_init_mem_map(DMA_MemMap_t *memMap       /* Stores state information about the map */
+    );
+
+/****************************************************************************/
+/**
+*   Releases any memory currently being held by a memory mapping structure.
+*/
+/****************************************************************************/
+
+int dma_term_mem_map(DMA_MemMap_t *memMap       /* Stores state information about the map */
+    );
+
+/****************************************************************************/
+/**
+*   Looks at a memory address and categorizes it.
+*
+*   @return One of the values from the DMA_MemType_t enumeration.
+*/
+/****************************************************************************/
+
+DMA_MemType_t dma_mem_type(void *addr);
+
+/****************************************************************************/
+/**
+*   Sets the process (aka userTask) associated with a mem map. This is
+*   required if user-mode segments will be added to the mapping.
+*/
+/****************************************************************************/
+
+static inline void dma_mem_map_set_user_task(DMA_MemMap_t *memMap,
+                                             struct task_struct *task)
+{
+        memMap->userTask = task;
+}
+
+/****************************************************************************/
+/**
+*   Looks at a memory address and determines if we support DMA'ing to/from
+*   that type of memory.
+*
+*   @return boolean -
+*               return value != 0 means dma supported
+*               return value == 0 means dma not supported
+*/
+/****************************************************************************/
+
+int dma_mem_supports_dma(void *addr);
+
+/****************************************************************************/
+/**
+*   Initializes a memory map for use. Since this function acquires a
+*   sempaphore within the memory map, it is VERY important that dma_unmap
+*   be called when you're finished using the map.
+*/
+/****************************************************************************/
+
+int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */
+                  enum dma_data_direction dir   /* Direction that the mapping will be going */
+    );
+
+/****************************************************************************/
+/**
+*   Adds a segment of memory to a memory map.
+*
+*   @return     0 on success, error code otherwise.
+*/
+/****************************************************************************/
+
+int dma_map_add_region(DMA_MemMap_t *memMap,    /* Stores state information about the map */
+                       void *mem,       /* Virtual address that we want to get a map of */
+                       size_t numBytes  /* Number of bytes being mapped */
+    );
+
+/****************************************************************************/
+/**
+*   Creates a descriptor ring from a memory mapping.
+*
+*   @return 0 on sucess, error code otherwise.
+*/
+/****************************************************************************/
+
+int dma_map_create_descriptor_ring(DMA_Device_t dev,    /* DMA device (where the ring is stored) */
+                                   DMA_MemMap_t *memMap,        /* Memory map that will be used */
+                                   dma_addr_t devPhysAddr       /* Physical address of device */
+    );
+
+/****************************************************************************/
+/**
+*   Maps in a memory region such that it can be used for performing a DMA.
+*
+*   @return
+*/
+/****************************************************************************/
+
+int dma_map_mem(DMA_MemMap_t *memMap,   /* Stores state information about the map */
+                void *addr,     /* Virtual address that we want to get a map of */
+                size_t count,   /* Number of bytes being mapped */
+                enum dma_data_direction dir     /* Direction that the mapping will be going */
+    );
+
+/****************************************************************************/
+/**
+*   Maps in a memory region such that it can be used for performing a DMA.
+*
+*   @return
+*/
+/****************************************************************************/
+
+int dma_unmap(DMA_MemMap_t *memMap,     /* Stores state information about the map */
+              int dirtied       /* non-zero if any of the pages were modified */
+    );
+
+/****************************************************************************/
+/**
+*   Initiates a transfer when the descriptors have already been setup.
+*
+*   This is a special case, and normally, the dma_transfer_xxx functions should
+*   be used.
+*
+*   @return
+*       0       Transfer was started successfully
+*       -ENODEV Invalid handle
+*/
+/****************************************************************************/
+
+int dma_start_transfer(DMA_Handle_t handle);
+
+/****************************************************************************/
+/**
+*   Stops a previously started DMA transfer.
+*
+*   @return
+*       0       Transfer was stopped successfully
+*       -ENODEV Invalid handle
+*/
+/****************************************************************************/
+
+int dma_stop_transfer(DMA_Handle_t handle);
+
+/****************************************************************************/
+/**
+*   Waits for a DMA to complete by polling. This function is only intended
+*   to be used for testing. Interrupts should be used for most DMA operations.
+*/
+/****************************************************************************/
+
+int dma_wait_transfer_done(DMA_Handle_t handle);
+
+/****************************************************************************/
+/**
+*   Initiates a DMA transfer
+*
+*   @return
+*       0       Transfer was started successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*/
+/****************************************************************************/
+
+int dma_transfer(DMA_Handle_t handle,   /* DMA Handle */
+                 dmacHw_TRANSFER_TYPE_e transferType,   /* Type of transfer being performed */
+                 dma_addr_t srcData,    /* Place to get data to write to device */
+                 dma_addr_t dstData,    /* Pointer to device data address */
+                 size_t numBytes        /* Number of bytes to transfer to the device */
+    );
+
+/****************************************************************************/
+/**
+*   Initiates a transfer from memory to a device.
+*
+*   @return
+*       0       Transfer was started successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
+*/
+/****************************************************************************/
+
+static inline int dma_transfer_to_device(DMA_Handle_t handle,   /* DMA Handle */
+                                         dma_addr_t srcData,    /* Place to get data to write to device (physical address) */
+                                         dma_addr_t dstData,    /* Pointer to device data address (physical address) */
+                                         size_t numBytes        /* Number of bytes to transfer to the device */
+    ) {
+        return dma_transfer(handle,
+                            dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                            srcData, dstData, numBytes);
+}
+
+/****************************************************************************/
+/**
+*   Initiates a transfer from a device to memory.
+*
+*   @return
+*       0       Transfer was started successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*/
+/****************************************************************************/
+
+static inline int dma_transfer_from_device(DMA_Handle_t handle, /* DMA Handle */
+                                           dma_addr_t srcData,  /* Pointer to the device data address (physical address) */
+                                           dma_addr_t dstData,  /* Place to store data retrieved from the device (physical address) */
+                                           size_t numBytes      /* Number of bytes to retrieve from the device */
+    ) {
+        return dma_transfer(handle,
+                            dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                            srcData, dstData, numBytes);
+}
+
+/****************************************************************************/
+/**
+*   Initiates a memory to memory transfer.
+*
+*   @return
+*       0       Transfer was started successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device wasn't DMA_DEVICE_MEM_TO_MEM)
+*/
+/****************************************************************************/
+
+static inline int dma_transfer_mem_to_mem(DMA_Handle_t handle,  /* DMA Handle */
+                                          dma_addr_t srcData,   /* Place to transfer data from (physical address) */
+                                          dma_addr_t dstData,   /* Place to transfer data to (physical address) */
+                                          size_t numBytes       /* Number of bytes to transfer */
+    ) {
+        return dma_transfer(handle,
+                            dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
+                            srcData, dstData, numBytes);
+}
+
+/****************************************************************************/
+/**
+*   Set the callback function which will be called when a transfer completes.
+*   If a NULL callback function is set, then no callback will occur.
+*
+*   @note   @a devHandler will be called from IRQ context.
+*
+*   @return
+*       0       - Success
+*       -ENODEV - Device handed in is invalid.
+*/
+/****************************************************************************/
+
+int dma_set_device_handler(DMA_Device_t dev,    /* Device to set the callback for. */
+                           DMA_DeviceHandler_t devHandler,      /* Function to call when the DMA completes */
+                           void *userData       /* Pointer which will be passed to devHandler. */
+    );
+
+#endif
+
+#endif /* ASM_ARM_ARCH_BCMRING_DMA_H */
diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S b/arch/arm/mach-bcmring/include/mach/entry-macro.S
new file mode 100644
index 000000000000..7d393ca010ac
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/entry-macro.S
@@ -0,0 +1,86 @@
+/*****************************************************************************
+* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/*
+ *
+ * Low-level IRQ helper macros for BCMRing-based platforms
+ *
+ */
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/csp/mm_io.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =(MM_IO_BASE_INTC0)
+                ldr     \irqstat, [\base, #0]           @ get status
+                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
+                ands    \irqstat, \irqstat, \irqnr
+                mov     \irqnr, #IRQ_INTC0_START
+                cmp     \irqstat, #0
+                bne     1001f
+
+                ldr     \base, =(MM_IO_BASE_INTC1)
+                ldr     \irqstat, [\base, #0]           @ get status
+                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
+                ands    \irqstat, \irqstat, \irqnr
+                mov     \irqnr, #IRQ_INTC1_START
+                cmp     \irqstat, #0
+                bne     1001f
+
+                ldr     \base, =(MM_IO_BASE_SINTC)
+                ldr     \irqstat, [\base, #0]           @ get status
+                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
+                ands    \irqstat, \irqstat, \irqnr
+                mov     \irqnr, #0xffffffff             @ code meaning no interrupt bits set
+                cmp     \irqstat, #0
+                beq     1002f
+
+                mov     \irqnr, #IRQ_SINTC_START        @ something is set, so fixup return value
+
+1001:
+                movs    \tmp, \irqstat, lsl #16
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #16
+
+                movs    \tmp, \irqstat, lsl #8
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #8
+
+                movs    \tmp, \irqstat, lsl #4
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #4
+
+                movs    \tmp, \irqstat, lsl #2
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #2
+
+                movs    \tmp, \irqstat, lsl #1
+                addeq   \irqnr, \irqnr, #1
+                orrs    \base, \base, #1
+
+1002:           @ irqnr will be set to 0xffffffff if no irq bits are set
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  irq_prio_table
+                .endm
+
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h
new file mode 100644
index 000000000000..447eb340c611
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/hardware.h
@@ -0,0 +1,60 @@
+/*
+ *
+ *  This file contains the hardware definitions of the BCMRing.
+ *
+ *  Copyright (C) 1999 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <mach/memory.h>
+#include <cfg_global.h>
+#include <mach/csp/mm_io.h>
+
+/* Hardware addresses of major areas.
+ *  *_START is the physical address
+ *  *_SIZE  is the size of the region
+ *  *_BASE  is the virtual address
+ */
+#define RAM_START               PHYS_OFFSET
+
+#define RAM_SIZE                (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
+#define RAM_BASE                PAGE_OFFSET
+
+#define pcibios_assign_all_busses()     1
+
+/* Macros to make managing spinlocks a bit more controlled in terms of naming. */
+/* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */
+#if defined(__KERNEL__)
+#define HW_DECLARE_SPINLOCK(name)  DEFINE_SPINLOCK(bcmring_##name##_reg_lock);
+#define HW_EXTERN_SPINLOCK(name)   extern spinlock_t bcmring_##name##_reg_lock;
+#define HW_IRQ_SAVE(name, val)     spin_lock_irqsave(&bcmring_##name##_reg_lock, (val))
+#define HW_IRQ_RESTORE(name, val)  spin_unlock_irqrestore(&bcmring_##name##_reg_lock, (val))
+#else
+#define HW_DECLARE_SPINLOCK(name)
+#define HW_EXTERN_SPINLOCK(name)
+#define HW_IRQ_SAVE(name, val)     {(void)(name); (void)(val); }
+#define HW_IRQ_RESTORE(name, val)  {(void)(name); (void)(val); }
+#endif
+
+#ifndef HW_IO_PHYS_TO_VIRT
+#define HW_IO_PHYS_TO_VIRT MM_IO_PHYS_TO_VIRT
+#endif
+#define HW_IO_VIRT_TO_PHYS MM_IO_VIRT_TO_PHYS
+
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/io.h b/arch/arm/mach-bcmring/include/mach/io.h
new file mode 100644
index 000000000000..4db0eff90357
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/io.h
@@ -0,0 +1,56 @@
+/*
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)         ((void __iomem *)HW_IO_PHYS_TO_VIRT(a))
+
+/* Do not enable mem_pci for a big endian arm architecture or unexpected byteswaps will */
+/* happen in readw/writew etc. */
+
+#define readb(c)        __raw_readb(c)
+#define readw(c)        __raw_readw(c)
+#define readl(c)        __raw_readl(c)
+#define readb_relaxed(addr) readb(addr)
+#define readw_relaxed(addr) readw(addr)
+#define readl_relaxed(addr) readl(addr)
+
+#define readsb(p, d, l)   __raw_readsb(p, d, l)
+#define readsw(p, d, l)   __raw_readsw(p, d, l)
+#define readsl(p, d, l)   __raw_readsl(p, d, l)
+
+#define writeb(v, c)     __raw_writeb(v, c)
+#define writew(v, c)     __raw_writew(v, c)
+#define writel(v, c)     __raw_writel(v, c)
+
+#define writesb(p, d, l)  __raw_writesb(p, d, l)
+#define writesw(p, d, l)  __raw_writesw(p, d, l)
+#define writesl(p, d, l)  __raw_writesl(p, d, l)
+
+#define memset_io(c, v, l)    _memset_io((c), (v), (l))
+#define memcpy_fromio(a, c, l)    _memcpy_fromio((a), (c), (l))
+#define memcpy_toio(c, a, l)  _memcpy_toio((c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) eth_copy_and_sum((s), (c), (l), (b))
+
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/irqs.h b/arch/arm/mach-bcmring/include/mach/irqs.h
new file mode 100644
index 000000000000..b279b825d4a7
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/irqs.h
@@ -0,0 +1,132 @@
+/*
+ *  Copyright (C) 2007 Broadcom
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#if !defined(ARCH_BCMRING_IRQS_H)
+#define ARCH_BCMRING_IRQS_H
+
+/* INTC0 - interrupt controller 0 */
+#define IRQ_INTC0_START     0
+#define IRQ_DMA0C0          0   /* DMA0 channel 0 interrupt */
+#define IRQ_DMA0C1          1   /* DMA0 channel 1 interrupt */
+#define IRQ_DMA0C2          2   /* DMA0 channel 2 interrupt */
+#define IRQ_DMA0C3          3   /* DMA0 channel 3 interrupt */
+#define IRQ_DMA0C4          4   /* DMA0 channel 4 interrupt */
+#define IRQ_DMA0C5          5   /* DMA0 channel 5 interrupt */
+#define IRQ_DMA0C6          6   /* DMA0 channel 6 interrupt */
+#define IRQ_DMA0C7          7   /* DMA0 channel 7 interrupt */
+#define IRQ_DMA1C0          8   /* DMA1 channel 0 interrupt */
+#define IRQ_DMA1C1          9   /* DMA1 channel 1 interrupt */
+#define IRQ_DMA1C2         10   /* DMA1 channel 2 interrupt */
+#define IRQ_DMA1C3         11   /* DMA1 channel 3 interrupt */
+#define IRQ_DMA1C4         12   /* DMA1 channel 4 interrupt */
+#define IRQ_DMA1C5         13   /* DMA1 channel 5 interrupt */
+#define IRQ_DMA1C6         14   /* DMA1 channel 6 interrupt */
+#define IRQ_DMA1C7         15   /* DMA1 channel 7 interrupt */
+#define IRQ_VPM            16   /* Voice process module interrupt */
+#define IRQ_USBHD2         17   /* USB host2/device2 interrupt */
+#define IRQ_USBH1          18   /* USB1 host interrupt */
+#define IRQ_USBD           19   /* USB device interrupt */
+#define IRQ_SDIOH0         20   /* SDIO0 host interrupt */
+#define IRQ_SDIOH1         21   /* SDIO1 host interrupt */
+#define IRQ_TIMER0         22   /* Timer0 interrupt */
+#define IRQ_TIMER1         23   /* Timer1 interrupt */
+#define IRQ_TIMER2         24   /* Timer2 interrupt */
+#define IRQ_TIMER3         25   /* Timer3 interrupt */
+#define IRQ_SPIH           26   /* SPI host interrupt */
+#define IRQ_ESW            27   /* Ethernet switch interrupt */
+#define IRQ_APM            28   /* Audio process module interrupt */
+#define IRQ_GE             29   /* Graphic engine interrupt */
+#define IRQ_CLCD           30   /* LCD Controller interrupt */
+#define IRQ_PIF            31   /* Peripheral interface interrupt */
+#define IRQ_INTC0_END      31
+
+/* INTC1 - interrupt controller 1 */
+#define IRQ_INTC1_START    32
+#define IRQ_GPIO0          32   /*  0 GPIO bit 31//0 combined interrupt */
+#define IRQ_GPIO1          33   /*  1 GPIO bit 64//32 combined interrupt */
+#define IRQ_I2S0           34   /*  2 I2S0 interrupt */
+#define IRQ_I2S1           35   /*  3 I2S1 interrupt */
+#define IRQ_I2CH           36   /*  4 I2C host interrupt */
+#define IRQ_I2CS           37   /*  5 I2C slave interrupt */
+#define IRQ_SPIS           38   /*  6 SPI slave interrupt */
+#define IRQ_GPHY           39   /*  7 Gigabit Phy interrupt */
+#define IRQ_FLASHC         40   /*  8 Flash controller interrupt */
+#define IRQ_COMMTX         41   /*  9 ARM DDC transmit interrupt */
+#define IRQ_COMMRX         42   /* 10 ARM DDC receive interrupt */
+#define IRQ_PMUIRQ         43   /* 11 ARM performance monitor interrupt */
+#define IRQ_UARTB          44   /* 12 UARTB */
+#define IRQ_WATCHDOG       45   /* 13 Watchdog timer interrupt */
+#define IRQ_UARTA          46   /* 14 UARTA */
+#define IRQ_TSC            47   /* 15 Touch screen controller interrupt */
+#define IRQ_KEYC           48   /* 16 Key pad controller interrupt */
+#define IRQ_DMPU           49   /* 17 DDR2 memory partition interrupt */
+#define IRQ_VMPU           50   /* 18 VRAM memory partition interrupt */
+#define IRQ_FMPU           51   /* 19 Flash memory parition unit interrupt */
+#define IRQ_RNG            52   /* 20 Random number generator interrupt */
+#define IRQ_RTC0           53   /* 21 Real time clock periodic interrupt */
+#define IRQ_RTC1           54   /* 22 Real time clock one-shot interrupt */
+#define IRQ_SPUM           55   /* 23 Secure process module interrupt */
+#define IRQ_VDEC           56   /* 24 Hantro video decoder interrupt */
+#define IRQ_RTC2           57   /* 25 Real time clock tamper interrupt */
+#define IRQ_DDRP           58   /* 26 DDR Panic interrupt */
+#define IRQ_INTC1_END      58
+
+/* SINTC secure int controller */
+#define IRQ_SINTC_START    59
+#define IRQ_SEC_WATCHDOG   59   /*  0 Watchdog timer interrupt */
+#define IRQ_SEC_UARTA      60   /*  1 UARTA interrupt */
+#define IRQ_SEC_TSC        61   /*  2 Touch screen controller interrupt */
+#define IRQ_SEC_KEYC       62   /*  3 Key pad controller interrupt */
+#define IRQ_SEC_DMPU       63   /*  4 DDR2 memory partition interrupt */
+#define IRQ_SEC_VMPU       64   /*  5 VRAM memory partition interrupt */
+#define IRQ_SEC_FMPU       65   /*  6 Flash memory parition unit interrupt */
+#define IRQ_SEC_RNG        66   /*  7 Random number generator interrupt */
+#define IRQ_SEC_RTC0       67   /*  8 Real time clock periodic interrupt */
+#define IRQ_SEC_RTC1       68   /*  9 Real time clock one-shot interrupt */
+#define IRQ_SEC_SPUM       69   /* 10 Secure process module interrupt */
+#define IRQ_SEC_TIMER0     70   /* 11 Secure timer0 interrupt */
+#define IRQ_SEC_TIMER1     71   /* 12 Secure timer1 interrupt */
+#define IRQ_SEC_TIMER2     72   /* 13 Secure timer2 interrupt */
+#define IRQ_SEC_TIMER3     73   /* 14 Secure timer3 interrupt */
+#define IRQ_SEC_RTC2       74   /* 15 Real time clock tamper interrupt */
+
+#define IRQ_SINTC_END      74
+
+/* Note: there are 3 INTC registers of 32 bits each. So internal IRQs could go from 0-95 */
+/*       Since IRQs are typically viewed in decimal, we start the gpio based IRQs off at 100 */
+/*       to make the mapping easy for humans to decipher. */
+
+#define IRQ_GPIO_0                  100
+
+#define NUM_INTERNAL_IRQS          (IRQ_SINTC_END+1)
+
+/* I couldn't get the gpioHw_reg.h file to be included cleanly, so I hardcoded it */
+/* define NUM_GPIO_IRQS               GPIOHW_TOTAL_NUM_PINS */
+#define NUM_GPIO_IRQS               62
+
+#define NR_IRQS                     (IRQ_GPIO_0 + NUM_GPIO_IRQS)
+
+#define IRQ_UNKNOWN                 -1
+
+/* Tune these bits to preclude noisy or unsupported interrupt sources as required. */
+#define IRQ_INTC0_VALID_MASK        0xffffffff
+#define IRQ_INTC1_VALID_MASK        0x07ffffff
+#define IRQ_SINTC_VALID_MASK        0x0000ffff
+
+#endif /* ARCH_BCMRING_IRQS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/memory.h b/arch/arm/mach-bcmring/include/mach/memory.h
new file mode 100644
index 000000000000..114f942bb4f3
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/memory.h
@@ -0,0 +1,33 @@
+/*****************************************************************************
+* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <cfg_global.h>
+
+/*
+ * Physical vs virtual RAM address space conversion.  These are
+ * private definitions which should NOT be used outside memory.h
+ * files.  Use virt_to_phys/phys_to_virt/__pa/__va instead.
+ */
+
+#define PHYS_OFFSET CFG_GLOBAL_RAM_BASE
+
+/*
+ * Maximum DMA memory allowed is 14M
+ */
+#define CONSISTENT_DMA_SIZE (SZ_16M - SZ_2M)
+
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/memory_settings.h b/arch/arm/mach-bcmring/include/mach/memory_settings.h
new file mode 100644
index 000000000000..ce5cd16f2ac4
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/memory_settings.h
@@ -0,0 +1,67 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+#ifndef MEMORY_SETTINGS_H
+#define MEMORY_SETTINGS_H
+
+/* ---- Include Files ---------------------------------------- */
+/* ---- Constants and Types ---------------------------------- */
+
+/* Memory devices */
+/* NAND Flash timing for 166 MHz setting */
+#define HW_CFG_NAND_tBTA  (5 << 16)     /* Bus turnaround cycle (n)        0-7  (30 ns) */
+#define HW_CFG_NAND_tWP   (4 << 11)     /* Write pulse width cycle (n+1)   0-31 (25 ns) */
+#define HW_CFG_NAND_tWR   (1 << 9)      /* Write recovery cycle (n+1)      0-3  (10 ns) */
+#define HW_CFG_NAND_tAS   (0 << 7)      /* Write address setup cycle (n+1) 0-3  ( 0 ns) */
+#define HW_CFG_NAND_tOE   (3 << 5)      /* Output enable delay cycle (n)   0-3  (15 ns) */
+#define HW_CFG_NAND_tRC   (7 << 0)      /* Read access cycle (n+2)         0-31 (50 ns) */
+
+#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \
+        | HW_CFG_NAND_tWP  \
+        | HW_CFG_NAND_tWR  \
+        | HW_CFG_NAND_tAS  \
+        | HW_CFG_NAND_tOE  \
+        | HW_CFG_NAND_tRC)
+
+/* NOR Flash timing for 166 MHz setting */
+#define HW_CFG_NOR_TPRC_TWLC (0 << 19)  /* Page read access cycle / Burst write latency (n+2 / n+1) (max 25ns) */
+#define HW_CFG_NOR_TBTA      (0 << 16)  /* Bus turnaround cycle (n)                                 (DNA)      */
+#define HW_CFG_NOR_TWP       (6 << 11)  /* Write pulse width cycle (n+1)                            (35ns)     */
+#define HW_CFG_NOR_TWR       (0 << 9)   /* Write recovery cycle (n+1)                               (0ns)      */
+#define HW_CFG_NOR_TAS       (0 << 7)   /* Write address setup cycle (n+1)                          (0ns)      */
+#define HW_CFG_NOR_TOE       (0 << 5)   /* Output enable delay cycle (n)                            (max 25ns) */
+#define HW_CFG_NOR_TRC_TLC   (0x10 << 0)        /* Read access cycle / Burst read latency (n+2 / n+1)       (100ns)    */
+
+#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \
+        | HW_CFG_NOR_TBTA      \
+        | HW_CFG_NOR_TWP       \
+        | HW_CFG_NOR_TWR       \
+        | HW_CFG_NOR_TAS       \
+        | HW_CFG_NOR_TOE       \
+        | HW_CFG_NOR_TRC_TLC)
+
+#define HW_CFG_FLASH1_TCR    HW_CFG_FLASH0_TCR
+#define HW_CFG_FLASH2_TCR    HW_CFG_FLASH0_TCR
+
+/* SDRAM Settings */
+/* #define HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
+/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
+/* #define HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values [400,533,667,800] */
+/* #define HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules [8,16] */
+#define HW_CFG_SDRAM_SIZE_BYTES         0x10000000      /* Total memory, not per device size */
+
+/* ---- Variable Externs ------------------------------------- */
+/* ---- Function Prototypes ---------------------------------- */
+
+#endif /* MEMORY_SETTINGS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/system.h b/arch/arm/mach-bcmring/include/mach/system.h
new file mode 100644
index 000000000000..cdbf93c694a6
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/system.h
@@ -0,0 +1,54 @@
+/*
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <mach/csp/chipcHw_inline.h>
+
+extern int bcmring_arch_warm_reboot;
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, char *cmd)
+{
+        printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
+
+        if (mode == 'h') {
+                /* Reboot configured in proc entry */
+                if (bcmring_arch_warm_reboot) {
+                        printk("warm reset\n");
+                        /* Issue Warm reset (do not reset ethernet switch, keep alive) */
+                        chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
+                } else {
+                        /* Force reset of everything */
+                        printk("force reset\n");
+                        chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
+                }
+        } else {
+                /* Force reset of everything */
+                printk("force reset\n");
+                chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
+        }
+}
+
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/timer.h b/arch/arm/mach-bcmring/include/mach/timer.h
new file mode 100644
index 000000000000..5a94bbb032b6
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/timer.h
@@ -0,0 +1,77 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/*
+*
+*****************************************************************************
+*
+*  timer.h
+*
+*  PURPOSE:
+*
+*
+*
+*  NOTES:
+*
+*****************************************************************************/
+
+#if !defined(BCM_LINUX_TIMER_H)
+#define BCM_LINUX_TIMER_H
+
+#if defined(__KERNEL__)
+
+/* ---- Include Files ---------------------------------------------------- */
+/* ---- Constants and Types ---------------------------------------------- */
+
+typedef unsigned int timer_tick_count_t;
+typedef unsigned int timer_tick_rate_t;
+typedef unsigned int timer_msec_t;
+
+/* ---- Variable Externs ------------------------------------------------- */
+/* ---- Function Prototypes ---------------------------------------------- */
+
+/****************************************************************************
+*
+*  timer_get_tick_count
+*
+*
+***************************************************************************/
+timer_tick_count_t timer_get_tick_count(void);
+
+/****************************************************************************
+*
+*  timer_get_tick_rate
+*
+*
+***************************************************************************/
+timer_tick_rate_t timer_get_tick_rate(void);
+
+/****************************************************************************
+*
+*  timer_get_msec
+*
+*
+***************************************************************************/
+timer_msec_t timer_get_msec(void);
+
+/****************************************************************************
+*
+*  timer_ticks_to_msec
+*
+*
+***************************************************************************/
+timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks);
+
+#endif /* __KERNEL__ */
+#endif /* BCM_LINUX_TIMER_H */
diff --git a/arch/arm/mach-bcmring/include/mach/timex.h b/arch/arm/mach-bcmring/include/mach/timex.h
new file mode 100644
index 000000000000..40d033ec5892
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/timex.h
@@ -0,0 +1,25 @@
+/*
+ *
+ *  Integrator architecture timex specifications
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Specifies the number of ticks per second
+ */
+#define CLOCK_TICK_RATE         100000 /* REG_SMT_TICKS_PER_SEC */
diff --git a/arch/arm/mach-bcmring/include/mach/uncompress.h b/arch/arm/mach-bcmring/include/mach/uncompress.h
new file mode 100644
index 000000000000..9c9821b77977
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/uncompress.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#include <mach/csp/mm_addr.h>
+
+#define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
+#define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18))
+/*
+ * This does not append a newline
+ */
+static inline void putc(int c)
+{
+        /* Send out UARTA */
+        while (BCMRING_UART_0_FR & (1 << 5))
+                ;
+
+        BCMRING_UART_0_DR = c;
+}
+
+
+static inline void flush(void)
+{
+        /* Wait for the tx fifo to be empty */
+        while ((BCMRING_UART_0_FR & (1 << 7)) == 0)
+                ;
+
+        /* Wait for the final character to be sent on the txd line */
+        while (BCMRING_UART_0_FR & (1 << 3))
+                ;
+}
+
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-bcmring/include/mach/vmalloc.h b/arch/arm/mach-bcmring/include/mach/vmalloc.h
new file mode 100644
index 000000000000..35e2ead8395c
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/vmalloc.h
@@ -0,0 +1,25 @@
+/*
+ *
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Move VMALLOC_END to 0xf0000000 so that the vm space can range from
+ * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles
+ * larger physical memory designs better.
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
new file mode 100644
index 000000000000..dc1c4939b0ce
--- /dev/null
+++ b/arch/arm/mach-bcmring/irq.c
@@ -0,0 +1,127 @@
+/*
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/stddef.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/version.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/mach/irq.h>
+#include <mach/csp/intcHw_reg.h>
+#include <mach/csp/mm_io.h>
+
+static void bcmring_mask_irq0(unsigned int irq)
+{
+        writel(1 << (irq - IRQ_INTC0_START),
+               MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR);
+}
+
+static void bcmring_unmask_irq0(unsigned int irq)
+{
+        writel(1 << (irq - IRQ_INTC0_START),
+               MM_IO_BASE_INTC0 + INTCHW_INTENABLE);
+}
+
+static void bcmring_mask_irq1(unsigned int irq)
+{
+        writel(1 << (irq - IRQ_INTC1_START),
+               MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR);
+}
+
+static void bcmring_unmask_irq1(unsigned int irq)
+{
+        writel(1 << (irq - IRQ_INTC1_START),
+               MM_IO_BASE_INTC1 + INTCHW_INTENABLE);
+}
+
+static void bcmring_mask_irq2(unsigned int irq)
+{
+        writel(1 << (irq - IRQ_SINTC_START),
+               MM_IO_BASE_SINTC + INTCHW_INTENCLEAR);
+}
+
+static void bcmring_unmask_irq2(unsigned int irq)
+{
+        writel(1 << (irq - IRQ_SINTC_START),
+               MM_IO_BASE_SINTC + INTCHW_INTENABLE);
+}
+
+static struct irq_chip bcmring_irq0_chip = {
+        .typename = "ARM-INTC0",
+        .ack = bcmring_mask_irq0,
+        .mask = bcmring_mask_irq0,      /* mask a specific interrupt, blocking its delivery. */
+        .unmask = bcmring_unmask_irq0,  /* unmaks an interrupt */
+};
+
+static struct irq_chip bcmring_irq1_chip = {
+        .typename = "ARM-INTC1",
+        .ack = bcmring_mask_irq1,
+        .mask = bcmring_mask_irq1,
+        .unmask = bcmring_unmask_irq1,
+};
+
+static struct irq_chip bcmring_irq2_chip = {
+        .typename = "ARM-SINTC",
+        .ack = bcmring_mask_irq2,
+        .mask = bcmring_mask_irq2,
+        .unmask = bcmring_unmask_irq2,
+};
+
+static void vic_init(void __iomem *base, struct irq_chip *chip,
+                     unsigned int irq_start, unsigned int vic_sources)
+{
+        unsigned int i;
+        for (i = 0; i < 32; i++) {
+                unsigned int irq = irq_start + i;
+                set_irq_chip(irq, chip);
+                set_irq_chip_data(irq, base);
+
+                if (vic_sources & (1 << i)) {
+                        set_irq_handler(irq, handle_level_irq);
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                }
+        }
+        writel(0, base + INTCHW_INTSELECT);
+        writel(0, base + INTCHW_INTENABLE);
+        writel(~0, base + INTCHW_INTENCLEAR);
+        writel(0, base + INTCHW_IRQSTATUS);
+        writel(~0, base + INTCHW_SOFTINTCLEAR);
+}
+
+void __init bcmring_init_irq(void)
+{
+        vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip,
+                 IRQ_INTC0_START, IRQ_INTC0_VALID_MASK);
+        vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip,
+                 IRQ_INTC1_START, IRQ_INTC1_VALID_MASK);
+        vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip,
+                 IRQ_SINTC_START, IRQ_SINTC_VALID_MASK);
+
+        /* special cases */
+        if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
+                set_irq_handler(IRQ_GPIO0, handle_simple_irq);
+        }
+        if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
+                set_irq_handler(IRQ_GPIO1, handle_simple_irq);
+        }
+}
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
new file mode 100644
index 000000000000..0f1c37e4523a
--- /dev/null
+++ b/arch/arm/mach-bcmring/mm.c
@@ -0,0 +1,56 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+#include <linux/platform_device.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/csp/mm_io.h>
+
+#define IO_DESC(va, sz) { .virtual = va, \
+        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
+        .length = sz, \
+        .type = MT_DEVICE }
+
+#define MEM_DESC(va, sz) { .virtual = va, \
+        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
+        .length = sz, \
+        .type = MT_MEMORY }
+
+static struct map_desc bcmring_io_desc[] __initdata = {
+        IO_DESC(MM_IO_BASE_NAND, SZ_64K),       /* phys:0x28000000-0x28000FFF  virt:0xE8000000-0xE8000FFF  size:0x00010000 */
+        IO_DESC(MM_IO_BASE_UMI, SZ_64K),        /* phys:0x2C000000-0x2C000FFF  virt:0xEC000000-0xEC000FFF  size:0x00010000 */
+
+        IO_DESC(MM_IO_BASE_BROM, SZ_64K),       /* phys:0x30000000-0x3000FFFF  virt:0xF3000000-0xF300FFFF  size:0x00010000 */
+        MEM_DESC(MM_IO_BASE_ARAM, SZ_1M),       /* phys:0x31000000-0x31FFFFFF  virt:0xF3100000-0xF31FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_DMA0, SZ_1M),        /* phys:0x32000000-0x32FFFFFF  virt:0xF3200000-0xF32FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_DMA1, SZ_1M),        /* phys:0x33000000-0x33FFFFFF  virt:0xF3300000-0xF33FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_ESW, SZ_1M), /* phys:0x34000000-0x34FFFFFF  virt:0xF3400000-0xF34FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_CLCD, SZ_1M),        /* phys:0x35000000-0x35FFFFFF  virt:0xF3500000-0xF35FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_APM, SZ_1M), /* phys:0x36000000-0x36FFFFFF  virt:0xF3600000-0xF36FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_SPUM, SZ_1M),        /* phys:0x37000000-0x37FFFFFF  virt:0xF3700000-0xF37FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M),    /* phys:0x38000000-0x38FFFFFF  virt:0xF3800000-0xF38FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M),    /* phys:0x3A000000-0x3AFFFFFF  virt:0xF3A00000-0xF3AFFFFF  size:0x01000000 */
+
+        IO_DESC(MM_IO_BASE_VRAM, SZ_64K),       /* phys:0x40000000-0x4000FFFF  virt:0xF4000000-0xF400FFFF  size:0x00010000 */
+        IO_DESC(MM_IO_BASE_CHIPC, SZ_16M),      /* phys:0x80000000-0x80FFFFFF  virt:0xF8000000-0xF8FFFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
+                SZ_16M),        /* phys:0x0F000000-0x0FFFFFFF  virt:0xF0000000-0xF0FFFFFF  size:0x01000000 */
+};
+
+void __init bcmring_map_io(void)
+{
+
+        iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
+}
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
new file mode 100644
index 000000000000..2d415d2a8e68
--- /dev/null
+++ b/arch/arm/mach-bcmring/timer.c
@@ -0,0 +1,62 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <csp/tmrHw.h>
+
+#include <mach/timer.h>
+/* The core.c file initializes timers 1 and 3 as a linux clocksource. */
+/* The real time clock should probably be the real linux clocksource. */
+/* In the meantime, this file should agree with core.c as to the */
+/* profiling timer. If the clocksource is moved to rtc later, then */
+/* we can init the profiling timer here instead. */
+
+/* Timer 1 provides 25MHz resolution syncrhonized to scheduling and APM timing */
+/* Timer 3 provides bus freqeuncy sychronized to ACLK, but spread spectrum will */
+/* affect synchronization with scheduling and APM timing. */
+
+#define PROF_TIMER 1
+
+timer_tick_rate_t timer_get_tick_rate(void)
+{
+        return tmrHw_getCountRate(PROF_TIMER);
+}
+
+timer_tick_count_t timer_get_tick_count(void)
+{
+        return tmrHw_GetCurrentCount(PROF_TIMER);       /* change downcounter to upcounter */
+}
+
+timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks)
+{
+        static int tickRateMsec;
+
+        if (tickRateMsec == 0) {
+                tickRateMsec = timer_get_tick_rate() / 1000;
+        }
+
+        return ticks / tickRateMsec;
+}
+
+timer_msec_t timer_get_msec(void)
+{
+        return timer_ticks_to_msec(timer_get_tick_count());
+}
+
+EXPORT_SYMBOL(timer_get_tick_count);
+EXPORT_SYMBOL(timer_ticks_to_msec);
+EXPORT_SYMBOL(timer_get_tick_rate);
+EXPORT_SYMBOL(timer_get_msec);
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index be747f5c6cd8..40866c643f13 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -6,6 +6,9 @@ config AINTC
 config CP_INTC
         bool
 
+config ARCH_DAVINCI_DMx
+        bool
+
 menu "TI DaVinci Implementations"
 
 comment "DaVinci Core Type"
@@ -13,20 +16,41 @@ comment "DaVinci Core Type"
 config ARCH_DAVINCI_DM644x
         bool "DaVinci 644x based system"
         select AINTC
+        select ARCH_DAVINCI_DMx
 
 config ARCH_DAVINCI_DM355
         bool "DaVinci 355 based system"
         select AINTC
+        select ARCH_DAVINCI_DMx
 
 config ARCH_DAVINCI_DM646x
         bool "DaVinci 646x based system"
         select AINTC
+        select ARCH_DAVINCI_DMx
+
+config ARCH_DAVINCI_DA830
+        bool "DA830/OMAP-L137 based system"
+        select CP_INTC
+        select ARCH_DAVINCI_DA8XX
+
+config ARCH_DAVINCI_DA850
+        bool "DA850/OMAP-L138 based system"
+        select CP_INTC
+        select ARCH_DAVINCI_DA8XX
+
+config ARCH_DAVINCI_DA8XX
+        bool
+
+config ARCH_DAVINCI_DM365
+        bool "DaVinci 365 based system"
+        select AINTC
+        select ARCH_DAVINCI_DMx
 
 comment "DaVinci Board Type"
 
 config MACH_DAVINCI_EVM
         bool "TI DM644x EVM"
-        default y
+        default ARCH_DAVINCI_DM644x
         depends on ARCH_DAVINCI_DM644x
         help
           Configure this option to specify the whether the board used
@@ -41,6 +65,7 @@ config MACH_SFFSDR
 
 config MACH_DAVINCI_DM355_EVM
         bool "TI DM355 EVM"
+        default ARCH_DAVINCI_DM355
         depends on ARCH_DAVINCI_DM355
         help
           Configure this option to specify the whether the board used
@@ -55,11 +80,33 @@ config MACH_DM355_LEOPARD
 
 config MACH_DAVINCI_DM6467_EVM
         bool "TI DM6467 EVM"
+        default ARCH_DAVINCI_DM646x
         depends on ARCH_DAVINCI_DM646x
         help
           Configure this option to specify the whether the board used
           for development is a DM6467 EVM
 
+config MACH_DAVINCI_DM365_EVM
+        bool "TI DM365 EVM"
+        default ARCH_DAVINCI_DM365
+        depends on ARCH_DAVINCI_DM365
+        help
+          Configure this option to specify whether the board used
+          for development is a DM365 EVM
+
+config MACH_DAVINCI_DA830_EVM
+        bool "TI DA830/OMAP-L137 Reference Platform"
+        default ARCH_DAVINCI_DA830
+        depends on ARCH_DAVINCI_DA830
+        help
+          Say Y here to select the TI DA830/OMAP-L137 Evaluation Module.
+
+config MACH_DAVINCI_DA850_EVM
+        bool "TI DA850/OMAP-L138 Reference Platform"
+        default ARCH_DAVINCI_DA850
+        depends on ARCH_DAVINCI_DA850
+        help
+          Say Y here to select the TI DA850/OMAP-L138 Evaluation Module.
 
 config DAVINCI_MUX
         bool "DAVINCI multiplexing support"
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 059ab78084ba..2e11e847313b 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,14 +5,17 @@
 
 # Common objects
 obj-y                   := time.o clock.o serial.o io.o psc.o \
-                           gpio.o devices.o dma.o usb.o common.o sram.o
+                           gpio.o dma.o usb.o common.o sram.o
 
 obj-$(CONFIG_DAVINCI_MUX)               += mux.o
 
 # Chip specific
-obj-$(CONFIG_ARCH_DAVINCI_DM644x)       += dm644x.o
-obj-$(CONFIG_ARCH_DAVINCI_DM355)        += dm355.o
-obj-$(CONFIG_ARCH_DAVINCI_DM646x)       += dm646x.o
+obj-$(CONFIG_ARCH_DAVINCI_DM644x)       += dm644x.o devices.o
+obj-$(CONFIG_ARCH_DAVINCI_DM355)        += dm355.o devices.o
+obj-$(CONFIG_ARCH_DAVINCI_DM646x)       += dm646x.o devices.o
+obj-$(CONFIG_ARCH_DAVINCI_DM365)        += dm365.o devices.o
+obj-$(CONFIG_ARCH_DAVINCI_DA830)        += da830.o devices-da8xx.o
+obj-$(CONFIG_ARCH_DAVINCI_DA850)        += da850.o devices-da8xx.o
 
 obj-$(CONFIG_AINTC)                     += irq.o
 obj-$(CONFIG_CP_INTC)                   += cp_intc.o
@@ -23,3 +26,6 @@ obj-$(CONFIG_MACH_SFFSDR)		+= board-sffsdr.o
 obj-$(CONFIG_MACH_DAVINCI_DM355_EVM)    += board-dm355-evm.o
 obj-$(CONFIG_MACH_DM355_LEOPARD)        += board-dm355-leopard.o
 obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM)   += board-dm646x-evm.o
+obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)    += board-dm365-evm.o
+obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)    += board-da830-evm.o
+obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)    += board-da850-evm.o
diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot
index e1dd366f836b..db97ef2c6477 100644
--- a/arch/arm/mach-davinci/Makefile.boot
+++ b/arch/arm/mach-davinci/Makefile.boot
@@ -1,3 +1,13 @@
+ifeq ($(CONFIG_ARCH_DAVINCI_DA8XX),y)
+ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y)
+$(error Cannot enable DaVinci and DA8XX platforms concurrently)
+else
+   zreladdr-y   := 0xc0008000
+params_phys-y   := 0xc0000100
+initrd_phys-y   := 0xc0800000
+endif
+else
    zreladdr-y   := 0x80008000
 params_phys-y   := 0x80000100
 initrd_phys-y   := 0x80800000
+endif
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
new file mode 100644
index 000000000000..bfbb63936f33
--- /dev/null
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -0,0 +1,157 @@
+/*
+ * TI DA830/OMAP L137 EVM board
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ * Derived from: arch/arm/mach-davinci/board-dm644x-evm.c
+ *
+ * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <mach/cp_intc.h>
+#include <mach/da8xx.h>
+#include <mach/asp.h>
+
+#define DA830_EVM_PHY_MASK              0x0
+#define DA830_EVM_MDIO_FREQUENCY        2200000 /* PHY bus frequency */
+
+static struct at24_platform_data da830_evm_i2c_eeprom_info = {
+        .byte_len       = SZ_256K / 8,
+        .page_size      = 64,
+        .flags          = AT24_FLAG_ADDR16,
+        .setup          = davinci_get_mac_addr,
+        .context        = (void *)0x7f00,
+};
+
+static struct i2c_board_info __initdata da830_evm_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("24c256", 0x50),
+                .platform_data  = &da830_evm_i2c_eeprom_info,
+        },
+        {
+                I2C_BOARD_INFO("tlv320aic3x", 0x18),
+        }
+};
+
+static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = {
+        .bus_freq       = 100,  /* kHz */
+        .bus_delay      = 0,    /* usec */
+};
+
+static struct davinci_uart_config da830_evm_uart_config __initdata = {
+        .enabled_uarts = 0x7,
+};
+
+static u8 da830_iis_serializer_direction[] = {
+        RX_MODE,        INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
+        INACTIVE_MODE,  TX_MODE,        INACTIVE_MODE,  INACTIVE_MODE,
+        INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
+};
+
+static struct snd_platform_data da830_evm_snd_data = {
+        .tx_dma_offset  = 0x2000,
+        .rx_dma_offset  = 0x2000,
+        .op_mode        = DAVINCI_MCASP_IIS_MODE,
+        .num_serializer = ARRAY_SIZE(da830_iis_serializer_direction),
+        .tdm_slots      = 2,
+        .serial_dir     = da830_iis_serializer_direction,
+        .eventq_no      = EVENTQ_0,
+        .version        = MCASP_VERSION_2,
+        .txnumevt       = 1,
+        .rxnumevt       = 1,
+};
+
+static __init void da830_evm_init(void)
+{
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        int ret;
+
+        ret = da8xx_register_edma();
+        if (ret)
+                pr_warning("da830_evm_init: edma registration failed: %d\n",
+                                ret);
+
+        ret = da8xx_pinmux_setup(da830_i2c0_pins);
+        if (ret)
+                pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n",
+                                ret);
+
+        ret = da8xx_register_i2c(0, &da830_evm_i2c_0_pdata);
+        if (ret)
+                pr_warning("da830_evm_init: i2c0 registration failed: %d\n",
+                                ret);
+
+        soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK;
+        soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY;
+        soc_info->emac_pdata->rmii_en = 1;
+
+        ret = da8xx_pinmux_setup(da830_cpgmac_pins);
+        if (ret)
+                pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n",
+                                ret);
+
+        ret = da8xx_register_emac();
+        if (ret)
+                pr_warning("da830_evm_init: emac registration failed: %d\n",
+                                ret);
+
+        ret = da8xx_register_watchdog();
+        if (ret)
+                pr_warning("da830_evm_init: watchdog registration failed: %d\n",
+                                ret);
+
+        davinci_serial_init(&da830_evm_uart_config);
+        i2c_register_board_info(1, da830_evm_i2c_devices,
+                        ARRAY_SIZE(da830_evm_i2c_devices));
+
+        ret = da8xx_pinmux_setup(da830_mcasp1_pins);
+        if (ret)
+                pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n",
+                                ret);
+
+        da8xx_init_mcasp(1, &da830_evm_snd_data);
+}
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+static int __init da830_evm_console_init(void)
+{
+        return add_preferred_console("ttyS", 2, "115200");
+}
+console_initcall(da830_evm_console_init);
+#endif
+
+static __init void da830_evm_irq_init(void)
+{
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+        cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ,
+                        soc_info->intc_irq_prios);
+}
+
+static void __init da830_evm_map_io(void)
+{
+        da830_init();
+}
+
+MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP L137 EVM")
+        .phys_io        = IO_PHYS,
+        .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
+        .boot_params    = (DA8XX_DDR_BASE + 0x100),
+        .map_io         = da830_evm_map_io,
+        .init_irq       = da830_evm_irq_init,
+        .timer          = &davinci_timer,
+        .init_machine   = da830_evm_init,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
new file mode 100644
index 000000000000..c759d72494e0
--- /dev/null
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -0,0 +1,415 @@
+/*
+ * TI DA850/OMAP-L138 EVM board
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Derived from: arch/arm/mach-davinci/board-da830-evm.c
+ * Original Copyrights follow:
+ *
+ * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <mach/cp_intc.h>
+#include <mach/da8xx.h>
+#include <mach/nand.h>
+
+#define DA850_EVM_PHY_MASK              0x1
+#define DA850_EVM_MDIO_FREQUENCY        2200000 /* PHY bus frequency */
+
+#define DA850_LCD_BL_PIN                GPIO_TO_PIN(2, 15)
+#define DA850_LCD_PWR_PIN               GPIO_TO_PIN(8, 10)
+
+#define DA850_MMCSD_CD_PIN              GPIO_TO_PIN(4, 0)
+#define DA850_MMCSD_WP_PIN              GPIO_TO_PIN(4, 1)
+
+static struct mtd_partition da850_evm_norflash_partition[] = {
+        {
+                .name           = "NOR filesystem",
+                .offset         = 0,
+                .size           = MTDPART_SIZ_FULL,
+                .mask_flags     = 0,
+        },
+};
+
+static struct physmap_flash_data da850_evm_norflash_data = {
+        .width          = 2,
+        .parts          = da850_evm_norflash_partition,
+        .nr_parts       = ARRAY_SIZE(da850_evm_norflash_partition),
+};
+
+static struct resource da850_evm_norflash_resource[] = {
+        {
+                .start  = DA8XX_AEMIF_CS2_BASE,
+                .end    = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device da850_evm_norflash_device = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &da850_evm_norflash_data,
+        },
+        .num_resources  = 1,
+        .resource       = da850_evm_norflash_resource,
+};
+
+/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
+ * (128K blocks). It may be used instead of the (default) SPI flash
+ * to boot, using TI's tools to install the secondary boot loader
+ * (UBL) and U-Boot.
+ */
+struct mtd_partition da850_evm_nandflash_partition[] = {
+        {
+                .name           = "u-boot env",
+                .offset         = 0,
+                .size           = SZ_128K,
+                .mask_flags     = MTD_WRITEABLE,
+         },
+        {
+                .name           = "UBL",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_128K,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "u-boot",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 4 * SZ_128K,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "kernel",
+                .offset         = 0x200000,
+                .size           = SZ_2M,
+                .mask_flags     = 0,
+        },
+        {
+                .name           = "filesystem",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+                .mask_flags     = 0,
+        },
+};
+
+static struct davinci_nand_pdata da850_evm_nandflash_data = {
+        .parts          = da850_evm_nandflash_partition,
+        .nr_parts       = ARRAY_SIZE(da850_evm_nandflash_partition),
+        .ecc_mode       = NAND_ECC_HW,
+        .options        = NAND_USE_FLASH_BBT,
+};
+
+static struct resource da850_evm_nandflash_resource[] = {
+        {
+                .start  = DA8XX_AEMIF_CS3_BASE,
+                .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = DA8XX_AEMIF_CTL_BASE,
+                .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device da850_evm_nandflash_device = {
+        .name           = "davinci_nand",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &da850_evm_nandflash_data,
+        },
+        .num_resources  = ARRAY_SIZE(da850_evm_nandflash_resource),
+        .resource       = da850_evm_nandflash_resource,
+};
+
+static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("tlv320aic3x", 0x18),
+        }
+};
+
+static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
+        .bus_freq       = 100,  /* kHz */
+        .bus_delay      = 0,    /* usec */
+};
+
+static struct davinci_uart_config da850_evm_uart_config __initdata = {
+        .enabled_uarts = 0x7,
+};
+
+static struct platform_device *da850_evm_devices[] __initdata = {
+        &da850_evm_nandflash_device,
+        &da850_evm_norflash_device,
+};
+
+/* davinci da850 evm audio machine driver */
+static u8 da850_iis_serializer_direction[] = {
+        INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
+        INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
+        INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  TX_MODE,
+        RX_MODE,        INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
+};
+
+static struct snd_platform_data da850_evm_snd_data = {
+        .tx_dma_offset  = 0x2000,
+        .rx_dma_offset  = 0x2000,
+        .op_mode        = DAVINCI_MCASP_IIS_MODE,
+        .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction),
+        .tdm_slots      = 2,
+        .serial_dir     = da850_iis_serializer_direction,
+        .eventq_no      = EVENTQ_1,
+        .version        = MCASP_VERSION_2,
+        .txnumevt       = 1,
+        .rxnumevt       = 1,
+};
+
+static int da850_evm_mmc_get_ro(int index)
+{
+        return gpio_get_value(DA850_MMCSD_WP_PIN);
+}
+
+static int da850_evm_mmc_get_cd(int index)
+{
+        return !gpio_get_value(DA850_MMCSD_CD_PIN);
+}
+
+static struct davinci_mmc_config da850_mmc_config = {
+        .get_ro         = da850_evm_mmc_get_ro,
+        .get_cd         = da850_evm_mmc_get_cd,
+        .wires          = 4,
+        .version        = MMC_CTLR_VERSION_2,
+};
+
+static int da850_lcd_hw_init(void)
+{
+        int status;
+
+        status = gpio_request(DA850_LCD_BL_PIN, "lcd bl\n");
+        if (status < 0)
+                return status;
+
+        status = gpio_request(DA850_LCD_PWR_PIN, "lcd pwr\n");
+        if (status < 0) {
+                gpio_free(DA850_LCD_BL_PIN);
+                return status;
+        }
+
+        gpio_direction_output(DA850_LCD_BL_PIN, 0);
+        gpio_direction_output(DA850_LCD_PWR_PIN, 0);
+
+        /* disable lcd backlight */
+        gpio_set_value(DA850_LCD_BL_PIN, 0);
+
+        /* disable lcd power */
+        gpio_set_value(DA850_LCD_PWR_PIN, 0);
+
+        /* enable lcd power */
+        gpio_set_value(DA850_LCD_PWR_PIN, 1);
+
+        /* enable lcd backlight */
+        gpio_set_value(DA850_LCD_BL_PIN, 1);
+
+        return 0;
+}
+
+#define DA8XX_AEMIF_CE2CFG_OFFSET       0x10
+#define DA8XX_AEMIF_ASIZE_16BIT         0x1
+
+static void __init da850_evm_init_nor(void)
+{
+        void __iomem *aemif_addr;
+
+        aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K);
+
+        /* Configure data bus width of CS2 to 16 bit */
+        writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) |
+                DA8XX_AEMIF_ASIZE_16BIT,
+                aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET);
+
+        iounmap(aemif_addr);
+}
+
+#if defined(CONFIG_MTD_PHYSMAP) || \
+    defined(CONFIG_MTD_PHYSMAP_MODULE)
+#define HAS_NOR 1
+#else
+#define HAS_NOR 0
+#endif
+
+#if defined(CONFIG_MMC_DAVINCI) || \
+    defined(CONFIG_MMC_DAVINCI_MODULE)
+#define HAS_MMC 1
+#else
+#define HAS_MMC 0
+#endif
+
+static __init void da850_evm_init(void)
+{
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        int ret;
+
+        ret = da8xx_pinmux_setup(da850_nand_pins);
+        if (ret)
+                pr_warning("da850_evm_init: nand mux setup failed: %d\n",
+                                ret);
+
+        ret = da8xx_pinmux_setup(da850_nor_pins);
+        if (ret)
+                pr_warning("da850_evm_init: nor mux setup failed: %d\n",
+                                ret);
+
+        da850_evm_init_nor();
+
+        platform_add_devices(da850_evm_devices,
+                                ARRAY_SIZE(da850_evm_devices));
+
+        ret = da8xx_register_edma();
+        if (ret)
+                pr_warning("da850_evm_init: edma registration failed: %d\n",
+                                ret);
+
+        ret = da8xx_pinmux_setup(da850_i2c0_pins);
+        if (ret)
+                pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n",
+                                ret);
+
+        ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata);
+        if (ret)
+                pr_warning("da850_evm_init: i2c0 registration failed: %d\n",
+                                ret);
+
+        soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK;
+        soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY;
+        soc_info->emac_pdata->rmii_en = 0;
+
+        ret = da8xx_pinmux_setup(da850_cpgmac_pins);
+        if (ret)
+                pr_warning("da850_evm_init: cpgmac mux setup failed: %d\n",
+                                ret);
+
+        ret = da8xx_register_emac();
+        if (ret)
+                pr_warning("da850_evm_init: emac registration failed: %d\n",
+                                ret);
+
+        ret = da8xx_register_watchdog();
+        if (ret)
+                pr_warning("da830_evm_init: watchdog registration failed: %d\n",
+                                ret);
+
+        if (HAS_MMC) {
+                if (HAS_NOR)
+                        pr_warning("WARNING: both NOR Flash and MMC/SD are "
+                                "enabled, but they share AEMIF pins.\n"
+                                "\tDisable one of them.\n");
+
+                ret = da8xx_pinmux_setup(da850_mmcsd0_pins);
+                if (ret)
+                        pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
+                                        " %d\n", ret);
+
+                ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n");
+                if (ret)
+                        pr_warning("da850_evm_init: can not open GPIO %d\n",
+                                        DA850_MMCSD_CD_PIN);
+                gpio_direction_input(DA850_MMCSD_CD_PIN);
+
+                ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n");
+                if (ret)
+                        pr_warning("da850_evm_init: can not open GPIO %d\n",
+                                        DA850_MMCSD_WP_PIN);
+                gpio_direction_input(DA850_MMCSD_WP_PIN);
+
+                ret = da8xx_register_mmcsd0(&da850_mmc_config);
+                if (ret)
+                        pr_warning("da850_evm_init: mmcsd0 registration failed:"
+                                        " %d\n", ret);
+        }
+
+        davinci_serial_init(&da850_evm_uart_config);
+
+        i2c_register_board_info(1, da850_evm_i2c_devices,
+                        ARRAY_SIZE(da850_evm_i2c_devices));
+
+        /*
+         * shut down uart 0 and 1; they are not used on the board and
+         * accessing them causes endless "too much work in irq53" messages
+         * with arago fs
+         */
+        __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
+        __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
+
+        ret = da8xx_pinmux_setup(da850_mcasp_pins);
+        if (ret)
+                pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
+                                ret);
+
+        da8xx_init_mcasp(0, &da850_evm_snd_data);
+
+        ret = da8xx_pinmux_setup(da850_lcdcntl_pins);
+        if (ret)
+                pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
+                                ret);
+
+        ret = da850_lcd_hw_init();
+        if (ret)
+                pr_warning("da850_evm_init: lcd initialization failed: %d\n",
+                                ret);
+
+        ret = da8xx_register_lcdc();
+        if (ret)
+                pr_warning("da850_evm_init: lcdc registration failed: %d\n",
+                                ret);
+}
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+static int __init da850_evm_console_init(void)
+{
+        return add_preferred_console("ttyS", 2, "115200");
+}
+console_initcall(da850_evm_console_init);
+#endif
+
+static __init void da850_evm_irq_init(void)
+{
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+        cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA850_N_CP_INTC_IRQ,
+                        soc_info->intc_irq_prios);
+}
+
+static void __init da850_evm_map_io(void)
+{
+        da850_init();
+}
+
+MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM")
+        .phys_io        = IO_PHYS,
+        .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
+        .boot_params    = (DA8XX_DDR_BASE + 0x100),
+        .map_io         = da850_evm_map_io,
+        .init_irq       = da850_evm_irq_init,
+        .timer          = &davinci_timer,
+        .init_machine   = da850_evm_init,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index d6ab64ccd496..77e806798822 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -20,6 +20,8 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/clk.h>
+#include <linux/videodev2.h>
+#include <media/tvp514x.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/eeprom.h>
 
@@ -117,6 +119,8 @@ static struct davinci_i2c_platform_data i2c_pdata = {
         .bus_delay      = 0     /* usec */,
 };
 
+static struct snd_platform_data dm355_evm_snd_data;
+
 static int dm355evm_mmc_gpios = -EINVAL;
 
 static void dm355evm_mmcsd_gpios(unsigned gpio)
@@ -134,11 +138,11 @@ static void dm355evm_mmcsd_gpios(unsigned gpio)
 }
 
 static struct i2c_board_info dm355evm_i2c_info[] = {
-        { I2C_BOARD_INFO("dm355evm_msp", 0x25),
+        {       I2C_BOARD_INFO("dm355evm_msp", 0x25),
                 .platform_data = dm355evm_mmcsd_gpios,
-                /* plus irq */ },
-        /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */
-        /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */
+        },
+        /* { plus irq  }, */
+        { I2C_BOARD_INFO("tlv320aic33", 0x1b), },
 };
 
 static void __init evm_init_i2c(void)
@@ -177,6 +181,72 @@ static struct platform_device dm355evm_dm9000 = {
         .num_resources  = ARRAY_SIZE(dm355evm_dm9000_rsrc),
 };
 
+static struct tvp514x_platform_data tvp5146_pdata = {
+        .clk_polarity = 0,
+        .hs_polarity = 1,
+        .vs_polarity = 1
+};
+
+#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
+/* Inputs available at the TVP5146 */
+static struct v4l2_input tvp5146_inputs[] = {
+        {
+                .index = 0,
+                .name = "Composite",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = TVP514X_STD_ALL,
+        },
+        {
+                .index = 1,
+                .name = "S-Video",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = TVP514X_STD_ALL,
+        },
+};
+
+/*
+ * this is the route info for connecting each input to decoder
+ * ouput that goes to vpfe. There is a one to one correspondence
+ * with tvp5146_inputs
+ */
+static struct vpfe_route tvp5146_routes[] = {
+        {
+                .input = INPUT_CVBS_VI2B,
+                .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
+        },
+        {
+                .input = INPUT_SVIDEO_VI2C_VI1C,
+                .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
+        },
+};
+
+static struct vpfe_subdev_info vpfe_sub_devs[] = {
+        {
+                .name = "tvp5146",
+                .grp_id = 0,
+                .num_inputs = ARRAY_SIZE(tvp5146_inputs),
+                .inputs = tvp5146_inputs,
+                .routes = tvp5146_routes,
+                .can_route = 1,
+                .ccdc_if_params = {
+                        .if_type = VPFE_BT656,
+                        .hdpol = VPFE_PINPOL_POSITIVE,
+                        .vdpol = VPFE_PINPOL_POSITIVE,
+                },
+                .board_info = {
+                        I2C_BOARD_INFO("tvp5146", 0x5d),
+                        .platform_data = &tvp5146_pdata,
+                },
+        }
+};
+
+static struct vpfe_config vpfe_cfg = {
+        .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
+        .sub_devs = vpfe_sub_devs,
+        .card_name = "DM355 EVM",
+        .ccdc = "DM355 CCDC",
+};
+
 static struct platform_device *davinci_evm_devices[] __initdata = {
         &dm355evm_dm9000,
         &davinci_nand_device,
@@ -188,6 +258,8 @@ static struct davinci_uart_config uart_config __initdata = {
 
 static void __init dm355_evm_map_io(void)
 {
+        /* setup input configuration for VPFE input devices */
+        dm355_set_vpfe_config(&vpfe_cfg);
         dm355_init();
 }
 
@@ -279,6 +351,9 @@ static __init void dm355_evm_init(void)
 
         dm355_init_spi0(BIT(0), dm355_evm_spi_info,
                         ARRAY_SIZE(dm355_evm_spi_info));
+
+        /* DM335 EVM uses ASP1; line-out is a stereo mini-jack */
+        dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN, &dm355_evm_snd_data);
 }
 
 static __init void dm355_evm_irq_init(void)
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
new file mode 100644
index 000000000000..a1d5e7dac741
--- /dev/null
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -0,0 +1,492 @@
+/*
+ * TI DaVinci DM365 EVM board support
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/dma-mapping.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/i2c/at24.h>
+#include <linux/leds.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/mux.h>
+#include <mach/hardware.h>
+#include <mach/dm365.h>
+#include <mach/psc.h>
+#include <mach/common.h>
+#include <mach/i2c.h>
+#include <mach/serial.h>
+#include <mach/common.h>
+#include <mach/mmc.h>
+#include <mach/nand.h>
+
+
+static inline int have_imager(void)
+{
+        /* REVISIT when it's supported, trigger via Kconfig */
+        return 0;
+}
+
+static inline int have_tvp7002(void)
+{
+        /* REVISIT when it's supported, trigger via Kconfig */
+        return 0;
+}
+
+
+#define DM365_ASYNC_EMIF_CONTROL_BASE   0x01d10000
+#define DM365_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
+#define DM365_ASYNC_EMIF_DATA_CE1_BASE  0x04000000
+
+#define DM365_EVM_PHY_MASK              (0x2)
+#define DM365_EVM_MDIO_FREQUENCY        (2200000) /* PHY bus frequency */
+
+/*
+ * A MAX-II CPLD is used for various board control functions.
+ */
+#define CPLD_OFFSET(a13a8,a2a1)         (((a13a8) << 10) + ((a2a1) << 3))
+
+#define CPLD_VERSION    CPLD_OFFSET(0,0)        /* r/o */
+#define CPLD_TEST       CPLD_OFFSET(0,1)
+#define CPLD_LEDS       CPLD_OFFSET(0,2)
+#define CPLD_MUX        CPLD_OFFSET(0,3)
+#define CPLD_SWITCH     CPLD_OFFSET(1,0)        /* r/o */
+#define CPLD_POWER      CPLD_OFFSET(1,1)
+#define CPLD_VIDEO      CPLD_OFFSET(1,2)
+#define CPLD_CARDSTAT   CPLD_OFFSET(1,3)        /* r/o */
+
+#define CPLD_DILC_OUT   CPLD_OFFSET(2,0)
+#define CPLD_DILC_IN    CPLD_OFFSET(2,1)        /* r/o */
+
+#define CPLD_IMG_DIR0   CPLD_OFFSET(2,2)
+#define CPLD_IMG_MUX0   CPLD_OFFSET(2,3)
+#define CPLD_IMG_MUX1   CPLD_OFFSET(3,0)
+#define CPLD_IMG_DIR1   CPLD_OFFSET(3,1)
+#define CPLD_IMG_MUX2   CPLD_OFFSET(3,2)
+#define CPLD_IMG_MUX3   CPLD_OFFSET(3,3)
+#define CPLD_IMG_DIR2   CPLD_OFFSET(4,0)
+#define CPLD_IMG_MUX4   CPLD_OFFSET(4,1)
+#define CPLD_IMG_MUX5   CPLD_OFFSET(4,2)
+
+#define CPLD_RESETS     CPLD_OFFSET(4,3)
+
+#define CPLD_CCD_DIR1   CPLD_OFFSET(0x3e,0)
+#define CPLD_CCD_IO1    CPLD_OFFSET(0x3e,1)
+#define CPLD_CCD_DIR2   CPLD_OFFSET(0x3e,2)
+#define CPLD_CCD_IO2    CPLD_OFFSET(0x3e,3)
+#define CPLD_CCD_DIR3   CPLD_OFFSET(0x3f,0)
+#define CPLD_CCD_IO3    CPLD_OFFSET(0x3f,1)
+
+static void __iomem *cpld;
+
+
+/* NOTE:  this is geared for the standard config, with a socketed
+ * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
+ * swap chips with a different block size, partitioning will
+ * need to be changed. This NAND chip MT29F16G08FAA is the default
+ * NAND shipped with the Spectrum Digital DM365 EVM
+ */
+#define NAND_BLOCK_SIZE         SZ_128K
+
+static struct mtd_partition davinci_nand_partitions[] = {
+        {
+                /* UBL (a few copies) plus U-Boot */
+                .name           = "bootloader",
+                .offset         = 0,
+                .size           = 28 * NAND_BLOCK_SIZE,
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        }, {
+                /* U-Boot environment */
+                .name           = "params",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 2 * NAND_BLOCK_SIZE,
+                .mask_flags     = 0,
+        }, {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_4M,
+                .mask_flags     = 0,
+        }, {
+                .name           = "filesystem1",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_512M,
+                .mask_flags     = 0,
+        }, {
+                .name           = "filesystem2",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+                .mask_flags     = 0,
+        }
+        /* two blocks with bad block table (and mirror) at the end */
+};
+
+static struct davinci_nand_pdata davinci_nand_data = {
+        .mask_chipsel           = BIT(14),
+        .parts                  = davinci_nand_partitions,
+        .nr_parts               = ARRAY_SIZE(davinci_nand_partitions),
+        .ecc_mode               = NAND_ECC_HW,
+        .options                = NAND_USE_FLASH_BBT,
+};
+
+static struct resource davinci_nand_resources[] = {
+        {
+                .start          = DM365_ASYNC_EMIF_DATA_CE0_BASE,
+                .end            = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = DM365_ASYNC_EMIF_CONTROL_BASE,
+                .end            = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device davinci_nand_device = {
+        .name                   = "davinci_nand",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(davinci_nand_resources),
+        .resource               = davinci_nand_resources,
+        .dev                    = {
+                .platform_data  = &davinci_nand_data,
+        },
+};
+
+static struct at24_platform_data eeprom_info = {
+        .byte_len       = (256*1024) / 8,
+        .page_size      = 64,
+        .flags          = AT24_FLAG_ADDR16,
+        .setup          = davinci_get_mac_addr,
+        .context        = (void *)0x7f00,
+};
+
+static struct i2c_board_info i2c_info[] = {
+        {
+                I2C_BOARD_INFO("24c256", 0x50),
+                .platform_data  = &eeprom_info,
+        },
+};
+
+static struct davinci_i2c_platform_data i2c_pdata = {
+        .bus_freq       = 400   /* kHz */,
+        .bus_delay      = 0     /* usec */,
+};
+
+static int cpld_mmc_get_cd(int module)
+{
+        if (!cpld)
+                return -ENXIO;
+
+        /* low == card present */
+        return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
+}
+
+static int cpld_mmc_get_ro(int module)
+{
+        if (!cpld)
+                return -ENXIO;
+
+        /* high == card's write protect switch active */
+        return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
+}
+
+static struct davinci_mmc_config dm365evm_mmc_config = {
+        .get_cd         = cpld_mmc_get_cd,
+        .get_ro         = cpld_mmc_get_ro,
+        .wires          = 4,
+        .max_freq       = 50000000,
+        .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
+        .version        = MMC_CTLR_VERSION_2,
+};
+
+static void dm365evm_emac_configure(void)
+{
+        /*
+         * EMAC pins are multiplexed with GPIO and UART
+         * Further details are available at the DM365 ARM
+         * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
+         */
+        davinci_cfg_reg(DM365_EMAC_TX_EN);
+        davinci_cfg_reg(DM365_EMAC_TX_CLK);
+        davinci_cfg_reg(DM365_EMAC_COL);
+        davinci_cfg_reg(DM365_EMAC_TXD3);
+        davinci_cfg_reg(DM365_EMAC_TXD2);
+        davinci_cfg_reg(DM365_EMAC_TXD1);
+        davinci_cfg_reg(DM365_EMAC_TXD0);
+        davinci_cfg_reg(DM365_EMAC_RXD3);
+        davinci_cfg_reg(DM365_EMAC_RXD2);
+        davinci_cfg_reg(DM365_EMAC_RXD1);
+        davinci_cfg_reg(DM365_EMAC_RXD0);
+        davinci_cfg_reg(DM365_EMAC_RX_CLK);
+        davinci_cfg_reg(DM365_EMAC_RX_DV);
+        davinci_cfg_reg(DM365_EMAC_RX_ER);
+        davinci_cfg_reg(DM365_EMAC_CRS);
+        davinci_cfg_reg(DM365_EMAC_MDIO);
+        davinci_cfg_reg(DM365_EMAC_MDCLK);
+
+        /*
+         * EMAC interrupts are multiplexed with GPIO interrupts
+         * Details are available at the DM365 ARM
+         * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
+         */
+        davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
+        davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
+        davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
+        davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
+}
+
+static void dm365evm_mmc_configure(void)
+{
+        /*
+         * MMC/SD pins are multiplexed with GPIO and EMIF
+         * Further details are available at the DM365 ARM
+         * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
+         */
+        davinci_cfg_reg(DM365_SD1_CLK);
+        davinci_cfg_reg(DM365_SD1_CMD);
+        davinci_cfg_reg(DM365_SD1_DATA3);
+        davinci_cfg_reg(DM365_SD1_DATA2);
+        davinci_cfg_reg(DM365_SD1_DATA1);
+        davinci_cfg_reg(DM365_SD1_DATA0);
+}
+
+static void __init evm_init_i2c(void)
+{
+        davinci_init_i2c(&i2c_pdata);
+        i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
+}
+
+static struct platform_device *dm365_evm_nand_devices[] __initdata = {
+        &davinci_nand_device,
+};
+
+static inline int have_leds(void)
+{
+#ifdef CONFIG_LEDS_CLASS
+        return 1;
+#else
+        return 0;
+#endif
+}
+
+struct cpld_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+
+static const struct {
+        const char *name;
+        const char *trigger;
+} cpld_leds[] = {
+        { "dm365evm::ds2", },
+        { "dm365evm::ds3", },
+        { "dm365evm::ds4", },
+        { "dm365evm::ds5", },
+        { "dm365evm::ds6", "nand-disk", },
+        { "dm365evm::ds7", "mmc1", },
+        { "dm365evm::ds8", "mmc0", },
+        { "dm365evm::ds9", "heartbeat", },
+};
+
+static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
+{
+        struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
+        u8 reg = __raw_readb(cpld + CPLD_LEDS);
+
+        if (b != LED_OFF)
+                reg &= ~led->mask;
+        else
+                reg |= led->mask;
+        __raw_writeb(reg, cpld + CPLD_LEDS);
+}
+
+static enum led_brightness cpld_led_get(struct led_classdev *cdev)
+{
+        struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
+        u8 reg = __raw_readb(cpld + CPLD_LEDS);
+
+        return (reg & led->mask) ? LED_OFF : LED_FULL;
+}
+
+static int __init cpld_leds_init(void)
+{
+        int     i;
+
+        if (!have_leds() ||  !cpld)
+                return 0;
+
+        /* setup LEDs */
+        __raw_writeb(0xff, cpld + CPLD_LEDS);
+        for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
+                struct cpld_led *led;
+
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+
+                led->cdev.name = cpld_leds[i].name;
+                led->cdev.brightness_set = cpld_led_set;
+                led->cdev.brightness_get = cpld_led_get;
+                led->cdev.default_trigger = cpld_leds[i].trigger;
+                led->mask = BIT(i);
+
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+
+        return 0;
+}
+/* run after subsys_initcall() for LEDs */
+fs_initcall(cpld_leds_init);
+
+
+static void __init evm_init_cpld(void)
+{
+        u8 mux, resets;
+        const char *label;
+        struct clk *aemif_clk;
+
+        /* Make sure we can configure the CPLD through CS1.  Then
+         * leave it on for later access to MMC and LED registers.
+         */
+        aemif_clk = clk_get(NULL, "aemif");
+        if (IS_ERR(aemif_clk))
+                return;
+        clk_enable(aemif_clk);
+
+        if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
+                        "cpld") == NULL)
+                goto fail;
+        cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
+        if (!cpld) {
+                release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
+                                SECTION_SIZE);
+fail:
+                pr_err("ERROR: can't map CPLD\n");
+                clk_disable(aemif_clk);
+                return;
+        }
+
+        /* External muxing for some signals */
+        mux = 0;
+
+        /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
+         * NOTE:  SW4 bus width setting must match!
+         */
+        if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
+                /* external keypad mux */
+                mux |= BIT(7);
+
+                platform_add_devices(dm365_evm_nand_devices,
+                                ARRAY_SIZE(dm365_evm_nand_devices));
+        } else {
+                /* no OneNAND support yet */
+        }
+
+        /* Leave external chips in reset when unused. */
+        resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
+
+        /* Static video input config with SN74CBT16214 1-of-3 mux:
+         *  - port b1 == tvp7002 (mux lowbits == 1 or 6)
+         *  - port b2 == imager (mux lowbits == 2 or 7)
+         *  - port b3 == tvp5146 (mux lowbits == 5)
+         *
+         * Runtime switching could work too, with limitations.
+         */
+        if (have_imager()) {
+                label = "HD imager";
+                mux |= 1;
+
+                /* externally mux MMC1/ENET/AIC33 to imager */
+                mux |= BIT(6) | BIT(5) | BIT(3);
+        } else {
+                struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+                /* we can use MMC1 ... */
+                dm365evm_mmc_configure();
+                davinci_setup_mmc(1, &dm365evm_mmc_config);
+
+                /* ... and ENET ... */
+                dm365evm_emac_configure();
+                soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
+                soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
+                resets &= ~BIT(3);
+
+                /* ... and AIC33 */
+                resets &= ~BIT(1);
+
+                if (have_tvp7002()) {
+                        mux |= 2;
+                        resets &= ~BIT(2);
+                        label = "tvp7002 HD";
+                } else {
+                        /* default to tvp5146 */
+                        mux |= 5;
+                        resets &= ~BIT(0);
+                        label = "tvp5146 SD";
+                }
+        }
+        __raw_writeb(mux, cpld + CPLD_MUX);
+        __raw_writeb(resets, cpld + CPLD_RESETS);
+        pr_info("EVM: %s video input\n", label);
+
+        /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
+}
+
+static struct davinci_uart_config uart_config __initdata = {
+        .enabled_uarts = (1 << 0),
+};
+
+static void __init dm365_evm_map_io(void)
+{
+        dm365_init();
+}
+
+static __init void dm365_evm_init(void)
+{
+        evm_init_i2c();
+        davinci_serial_init(&uart_config);
+
+        dm365evm_emac_configure();
+        dm365evm_mmc_configure();
+
+        davinci_setup_mmc(0, &dm365evm_mmc_config);
+
+        /* maybe setup mmc1/etc ... _after_ mmc0 */
+        evm_init_cpld();
+}
+
+static __init void dm365_evm_irq_init(void)
+{
+        davinci_irq_init();
+}
+
+MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
+        .phys_io        = IO_PHYS,
+        .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
+        .boot_params    = (0x80000100),
+        .map_io         = dm365_evm_map_io,
+        .init_irq       = dm365_evm_irq_init,
+        .timer          = &davinci_timer,
+        .init_machine   = dm365_evm_init,
+MACHINE_END
+
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 56c8cd01de9a..1213a0087ad4 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -28,6 +28,9 @@
 #include <linux/io.h>
 #include <linux/phy.h>
 #include <linux/clk.h>
+#include <linux/videodev2.h>
+
+#include <media/tvp514x.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -194,6 +197,72 @@ static struct platform_device davinci_fb_device = {
         .num_resources = 0,
 };
 
+static struct tvp514x_platform_data tvp5146_pdata = {
+        .clk_polarity = 0,
+        .hs_polarity = 1,
+        .vs_polarity = 1
+};
+
+#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
+/* Inputs available at the TVP5146 */
+static struct v4l2_input tvp5146_inputs[] = {
+        {
+                .index = 0,
+                .name = "Composite",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = TVP514X_STD_ALL,
+        },
+        {
+                .index = 1,
+                .name = "S-Video",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = TVP514X_STD_ALL,
+        },
+};
+
+/*
+ * this is the route info for connecting each input to decoder
+ * ouput that goes to vpfe. There is a one to one correspondence
+ * with tvp5146_inputs
+ */
+static struct vpfe_route tvp5146_routes[] = {
+        {
+                .input = INPUT_CVBS_VI2B,
+                .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
+        },
+        {
+                .input = INPUT_SVIDEO_VI2C_VI1C,
+                .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
+        },
+};
+
+static struct vpfe_subdev_info vpfe_sub_devs[] = {
+        {
+                .name = "tvp5146",
+                .grp_id = 0,
+                .num_inputs = ARRAY_SIZE(tvp5146_inputs),
+                .inputs = tvp5146_inputs,
+                .routes = tvp5146_routes,
+                .can_route = 1,
+                .ccdc_if_params = {
+                        .if_type = VPFE_BT656,
+                        .hdpol = VPFE_PINPOL_POSITIVE,
+                        .vdpol = VPFE_PINPOL_POSITIVE,
+                },
+                .board_info = {
+                        I2C_BOARD_INFO("tvp5146", 0x5d),
+                        .platform_data = &tvp5146_pdata,
+                },
+        },
+};
+
+static struct vpfe_config vpfe_cfg = {
+        .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
+        .sub_devs = vpfe_sub_devs,
+        .card_name = "DM6446 EVM",
+        .ccdc = "DM6446 CCDC",
+};
+
 static struct platform_device rtc_dev = {
         .name           = "rtc_davinci_evm",
         .id             = -1,
@@ -225,6 +294,8 @@ static struct platform_device ide_dev = {
         },
 };
 
+static struct snd_platform_data dm644x_evm_snd_data;
+
 /*----------------------------------------------------------------------*/
 
 /*
@@ -557,10 +628,9 @@ static struct i2c_board_info __initdata i2c_info[] =  {
                 I2C_BOARD_INFO("24c256", 0x50),
                 .platform_data  = &eeprom_info,
         },
-        /* ALSO:
-         * - tvl320aic33 audio codec (0x1b)
-         * - tvp5146 video decoder (0x5d)
-         */
+        {
+                I2C_BOARD_INFO("tlv320aic33", 0x1b),
+        },
 };
 
 /* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
@@ -590,6 +660,8 @@ static struct davinci_uart_config uart_config __initdata = {
 static void __init
 davinci_evm_map_io(void)
 {
+        /* setup input configuration for VPFE input devices */
+        dm644x_set_vpfe_config(&vpfe_cfg);
         dm644x_init();
 }
 
@@ -666,6 +738,7 @@ static __init void davinci_evm_init(void)
         davinci_setup_mmc(0, &dm6446evm_mmc_config);
 
         davinci_serial_init(&uart_config);
+        dm644x_init_asp(&dm644x_evm_snd_data);
 
         soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK;
         soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY;
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 8657e72debc1..24e0e13b1492 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -34,6 +34,8 @@
 #include <linux/i2c/pcf857x.h>
 #include <linux/etherdevice.h>
 
+#include <media/tvp514x.h>
+
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -48,13 +50,89 @@
 #include <mach/mmc.h>
 #include <mach/emac.h>
 
+#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
+    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
+#define HAS_ATA 1
+#else
+#define HAS_ATA 0
+#endif
+
+/* CPLD Register 0 bits to control ATA */
+#define DM646X_EVM_ATA_RST              BIT(0)
+#define DM646X_EVM_ATA_PWD              BIT(1)
+
 #define DM646X_EVM_PHY_MASK             (0x2)
 #define DM646X_EVM_MDIO_FREQUENCY       (2200000) /* PHY bus frequency */
 
+#define VIDCLKCTL_OFFSET        (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
+#define VSCLKDIS_OFFSET         (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
+#define VCH2CLK_MASK            (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
+#define VCH2CLK_SYSCLK8         (BIT(9))
+#define VCH2CLK_AUXCLK          (BIT(9) | BIT(8))
+#define VCH3CLK_MASK            (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
+#define VCH3CLK_SYSCLK8         (BIT(13))
+#define VCH3CLK_AUXCLK          (BIT(14) | BIT(13))
+
+#define VIDCH2CLK               (BIT(10))
+#define VIDCH3CLK               (BIT(11))
+#define VIDCH1CLK               (BIT(4))
+#define TVP7002_INPUT           (BIT(4))
+#define TVP5147_INPUT           (~BIT(4))
+#define VPIF_INPUT_ONE_CHANNEL  (BIT(5))
+#define VPIF_INPUT_TWO_CHANNEL  (~BIT(5))
+#define TVP5147_CH0             "tvp514x-0"
+#define TVP5147_CH1             "tvp514x-1"
+
+static void __iomem *vpif_vidclkctl_reg;
+static void __iomem *vpif_vsclkdis_reg;
+/* spin lock for updating above registers */
+static spinlock_t vpif_reg_lock;
+
 static struct davinci_uart_config uart_config __initdata = {
         .enabled_uarts = (1 << 0),
 };
 
+/* CPLD Register 0 Client: used for I/O Control */
+static int cpld_reg0_probe(struct i2c_client *client,
+                           const struct i2c_device_id *id)
+{
+        if (HAS_ATA) {
+                u8 data;
+                struct i2c_msg msg[2] = {
+                        {
+                                .addr = client->addr,
+                                .flags = I2C_M_RD,
+                                .len = 1,
+                                .buf = &data,
+                        },
+                        {
+                                .addr = client->addr,
+                                .flags = 0,
+                                .len = 1,
+                                .buf = &data,
+                        },
+                };
+
+                /* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */
+                i2c_transfer(client->adapter, msg, 1);
+                data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD);
+                i2c_transfer(client->adapter, msg + 1, 1);
+        }
+
+        return 0;
+}
+
+static const struct i2c_device_id cpld_reg_ids[] = {
+        { "cpld_reg0", 0, },
+        { },
+};
+
+static struct i2c_driver dm6467evm_cpld_driver = {
+        .driver.name    = "cpld_reg0",
+        .id_table       = cpld_reg_ids,
+        .probe          = cpld_reg0_probe,
+};
+
 /* LEDS */
 
 static struct gpio_led evm_leds[] = {
@@ -206,6 +284,69 @@ static struct at24_platform_data eeprom_info = {
         .context        = (void *)0x7f00,
 };
 
+static u8 dm646x_iis_serializer_direction[] = {
+       TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE,
+};
+
+static u8 dm646x_dit_serializer_direction[] = {
+       TX_MODE,
+};
+
+static struct snd_platform_data dm646x_evm_snd_data[] = {
+        {
+                .tx_dma_offset  = 0x400,
+                .rx_dma_offset  = 0x400,
+                .op_mode        = DAVINCI_MCASP_IIS_MODE,
+                .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction),
+                .tdm_slots      = 2,
+                .serial_dir     = dm646x_iis_serializer_direction,
+                .eventq_no      = EVENTQ_0,
+        },
+        {
+                .tx_dma_offset  = 0x400,
+                .rx_dma_offset  = 0,
+                .op_mode        = DAVINCI_MCASP_DIT_MODE,
+                .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction),
+                .tdm_slots      = 32,
+                .serial_dir     = dm646x_dit_serializer_direction,
+                .eventq_no      = EVENTQ_0,
+        },
+};
+
+static struct i2c_client *cpld_client;
+
+static int cpld_video_probe(struct i2c_client *client,
+                        const struct i2c_device_id *id)
+{
+        cpld_client = client;
+        return 0;
+}
+
+static int __devexit cpld_video_remove(struct i2c_client *client)
+{
+        cpld_client = NULL;
+        return 0;
+}
+
+static const struct i2c_device_id cpld_video_id[] = {
+        { "cpld_video", 0 },
+        { }
+};
+
+static struct i2c_driver cpld_video_driver = {
+        .driver = {
+                .name   = "cpld_video",
+        },
+        .probe          = cpld_video_probe,
+        .remove         = cpld_video_remove,
+        .id_table       = cpld_video_id,
+};
+
+static void evm_init_cpld(void)
+{
+        i2c_add_driver(&cpld_video_driver);
+}
+
 static struct i2c_board_info __initdata i2c_info[] =  {
         {
                 I2C_BOARD_INFO("24c256", 0x50),
@@ -215,6 +356,15 @@ static struct i2c_board_info __initdata i2c_info[] =  {
                 I2C_BOARD_INFO("pcf8574a", 0x38),
                 .platform_data  = &pcf_data,
         },
+        {
+                I2C_BOARD_INFO("cpld_reg0", 0x3a),
+        },
+        {
+                I2C_BOARD_INFO("tlv320aic33", 0x18),
+        },
+        {
+                I2C_BOARD_INFO("cpld_video", 0x3b),
+        },
 };
 
 static struct davinci_i2c_platform_data i2c_pdata = {
@@ -222,10 +372,265 @@ static struct davinci_i2c_platform_data i2c_pdata = {
         .bus_delay      = 0 /* usec */,
 };
 
+static int set_vpif_clock(int mux_mode, int hd)
+{
+        unsigned long flags;
+        unsigned int value;
+        int val = 0;
+        int err = 0;
+
+        if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client)
+                return -ENXIO;
+
+        /* disable the clock */
+        spin_lock_irqsave(&vpif_reg_lock, flags);
+        value = __raw_readl(vpif_vsclkdis_reg);
+        value |= (VIDCH3CLK | VIDCH2CLK);
+        __raw_writel(value, vpif_vsclkdis_reg);
+        spin_unlock_irqrestore(&vpif_reg_lock, flags);
+
+        val = i2c_smbus_read_byte(cpld_client);
+        if (val < 0)
+                return val;
+
+        if (mux_mode == 1)
+                val &= ~0x40;
+        else
+                val |= 0x40;
+
+        err = i2c_smbus_write_byte(cpld_client, val);
+        if (err)
+                return err;
+
+        value = __raw_readl(vpif_vidclkctl_reg);
+        value &= ~(VCH2CLK_MASK);
+        value &= ~(VCH3CLK_MASK);
+
+        if (hd >= 1)
+                value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8);
+        else
+                value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);
+
+        __raw_writel(value, vpif_vidclkctl_reg);
+
+        spin_lock_irqsave(&vpif_reg_lock, flags);
+        value = __raw_readl(vpif_vsclkdis_reg);
+        /* enable the clock */
+        value &= ~(VIDCH3CLK | VIDCH2CLK);
+        __raw_writel(value, vpif_vsclkdis_reg);
+        spin_unlock_irqrestore(&vpif_reg_lock, flags);
+
+        return 0;
+}
+
+static struct vpif_subdev_info dm646x_vpif_subdev[] = {
+        {
+                .name   = "adv7343",
+                .board_info = {
+                        I2C_BOARD_INFO("adv7343", 0x2a),
+                },
+        },
+        {
+                .name   = "ths7303",
+                .board_info = {
+                        I2C_BOARD_INFO("ths7303", 0x2c),
+                },
+        },
+};
+
+static const char *output[] = {
+        "Composite",
+        "Component",
+        "S-Video",
+};
+
+static struct vpif_display_config dm646x_vpif_display_config = {
+        .set_clock      = set_vpif_clock,
+        .subdevinfo     = dm646x_vpif_subdev,
+        .subdev_count   = ARRAY_SIZE(dm646x_vpif_subdev),
+        .output         = output,
+        .output_count   = ARRAY_SIZE(output),
+        .card_name      = "DM646x EVM",
+};
+
+/**
+ * setup_vpif_input_path()
+ * @channel: channel id (0 - CH0, 1 - CH1)
+ * @sub_dev_name: ptr sub device name
+ *
+ * This will set vpif input to capture data from tvp514x or
+ * tvp7002.
+ */
+static int setup_vpif_input_path(int channel, const char *sub_dev_name)
+{
+        int err = 0;
+        int val;
+
+        /* for channel 1, we don't do anything */
+        if (channel != 0)
+                return 0;
+
+        if (!cpld_client)
+                return -ENXIO;
+
+        val = i2c_smbus_read_byte(cpld_client);
+        if (val < 0)
+                return val;
+
+        if (!strcmp(sub_dev_name, TVP5147_CH0) ||
+            !strcmp(sub_dev_name, TVP5147_CH1))
+                val &= TVP5147_INPUT;
+        else
+                val |= TVP7002_INPUT;
+
+        err = i2c_smbus_write_byte(cpld_client, val);
+        if (err)
+                return err;
+        return 0;
+}
+
+/**
+ * setup_vpif_input_channel_mode()
+ * @mux_mode:  mux mode. 0 - 1 channel or (1) - 2 channel
+ *
+ * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147)
+ */
+static int setup_vpif_input_channel_mode(int mux_mode)
+{
+        unsigned long flags;
+        int err = 0;
+        int val;
+        u32 value;
+
+        if (!vpif_vsclkdis_reg || !cpld_client)
+                return -ENXIO;
+
+        val = i2c_smbus_read_byte(cpld_client);
+        if (val < 0)
+                return val;
+
+        spin_lock_irqsave(&vpif_reg_lock, flags);
+        value = __raw_readl(vpif_vsclkdis_reg);
+        if (mux_mode) {
+                val &= VPIF_INPUT_TWO_CHANNEL;
+                value |= VIDCH1CLK;
+        } else {
+                val |= VPIF_INPUT_ONE_CHANNEL;
+                value &= ~VIDCH1CLK;
+        }
+        __raw_writel(value, vpif_vsclkdis_reg);
+        spin_unlock_irqrestore(&vpif_reg_lock, flags);
+
+        err = i2c_smbus_write_byte(cpld_client, val);
+        if (err)
+                return err;
+
+        return 0;
+}
+
+static struct tvp514x_platform_data tvp5146_pdata = {
+        .clk_polarity = 0,
+        .hs_polarity = 1,
+        .vs_polarity = 1
+};
+
+#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
+
+static struct vpif_subdev_info vpif_capture_sdev_info[] = {
+        {
+                .name   = TVP5147_CH0,
+                .board_info = {
+                        I2C_BOARD_INFO("tvp5146", 0x5d),
+                        .platform_data = &tvp5146_pdata,
+                },
+                .input = INPUT_CVBS_VI2B,
+                .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
+                .can_route = 1,
+                .vpif_if = {
+                        .if_type = VPIF_IF_BT656,
+                        .hd_pol = 1,
+                        .vd_pol = 1,
+                        .fid_pol = 0,
+                },
+        },
+        {
+                .name   = TVP5147_CH1,
+                .board_info = {
+                        I2C_BOARD_INFO("tvp5146", 0x5c),
+                        .platform_data = &tvp5146_pdata,
+                },
+                .input = INPUT_SVIDEO_VI2C_VI1C,
+                .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
+                .can_route = 1,
+                .vpif_if = {
+                        .if_type = VPIF_IF_BT656,
+                        .hd_pol = 1,
+                        .vd_pol = 1,
+                        .fid_pol = 0,
+                },
+        },
+};
+
+static const struct vpif_input dm6467_ch0_inputs[] = {
+        {
+                .input = {
+                        .index = 0,
+                        .name = "Composite",
+                        .type = V4L2_INPUT_TYPE_CAMERA,
+                        .std = TVP514X_STD_ALL,
+                },
+                .subdev_name = TVP5147_CH0,
+        },
+};
+
+static const struct vpif_input dm6467_ch1_inputs[] = {
+       {
+                .input = {
+                        .index = 0,
+                        .name = "S-Video",
+                        .type = V4L2_INPUT_TYPE_CAMERA,
+                        .std = TVP514X_STD_ALL,
+                },
+                .subdev_name = TVP5147_CH1,
+        },
+};
+
+static struct vpif_capture_config dm646x_vpif_capture_cfg = {
+        .setup_input_path = setup_vpif_input_path,
+        .setup_input_channel_mode = setup_vpif_input_channel_mode,
+        .subdev_info = vpif_capture_sdev_info,
+        .subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
+        .chan_config[0] = {
+                .inputs = dm6467_ch0_inputs,
+                .input_count = ARRAY_SIZE(dm6467_ch0_inputs),
+        },
+        .chan_config[1] = {
+                .inputs = dm6467_ch1_inputs,
+                .input_count = ARRAY_SIZE(dm6467_ch1_inputs),
+        },
+};
+
+static void __init evm_init_video(void)
+{
+        vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4);
+        vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4);
+        if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) {
+                pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n");
+                return;
+        }
+        spin_lock_init(&vpif_reg_lock);
+
+        dm646x_setup_vpif(&dm646x_vpif_display_config,
+                          &dm646x_vpif_capture_cfg);
+}
+
 static void __init evm_init_i2c(void)
 {
         davinci_init_i2c(&i2c_pdata);
+        i2c_add_driver(&dm6467evm_cpld_driver);
         i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
+        evm_init_cpld();
+        evm_init_video();
 }
 
 static void __init davinci_map_io(void)
@@ -239,6 +644,11 @@ static __init void evm_init(void)
 
         evm_init_i2c();
         davinci_serial_init(&uart_config);
+        dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
+        dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
+
+        if (HAS_ATA)
+                dm646x_init_ide();
 
         soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
         soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 39bf321d70a2..83d54d50b5ea 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -227,7 +227,10 @@ static void __init clk_pll_init(struct clk *clk)
         if (ctrl & PLLCTL_PLLEN) {
                 bypass = 0;
                 mult = __raw_readl(pll->base + PLLM);
-                mult = (mult & PLLM_PLLM_MASK) + 1;
+                if (cpu_is_davinci_dm365())
+                        mult = 2 * (mult & PLLM_PLLM_MASK);
+                else
+                        mult = (mult & PLLM_PLLM_MASK) + 1;
         } else
                 bypass = 1;
 
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
new file mode 100644
index 000000000000..19b2748357fc
--- /dev/null
+++ b/arch/arm/mach-davinci/da830.c
@@ -0,0 +1,1205 @@
+/*
+ * TI DA830/OMAP L137 chip specific setup
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2009 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/clock.h>
+#include <mach/psc.h>
+#include <mach/mux.h>
+#include <mach/irqs.h>
+#include <mach/cputype.h>
+#include <mach/common.h>
+#include <mach/time.h>
+#include <mach/da8xx.h>
+#include <mach/asp.h>
+
+#include "clock.h"
+#include "mux.h"
+
+/* Offsets of the 8 compare registers on the da830 */
+#define DA830_CMP12_0           0x60
+#define DA830_CMP12_1           0x64
+#define DA830_CMP12_2           0x68
+#define DA830_CMP12_3           0x6c
+#define DA830_CMP12_4           0x70
+#define DA830_CMP12_5           0x74
+#define DA830_CMP12_6           0x78
+#define DA830_CMP12_7           0x7c
+
+#define DA830_REF_FREQ          24000000
+
+static struct pll_data pll0_data = {
+        .num            = 1,
+        .phys_base      = DA8XX_PLL0_BASE,
+        .flags          = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
+};
+
+static struct clk ref_clk = {
+        .name           = "ref_clk",
+        .rate           = DA830_REF_FREQ,
+};
+
+static struct clk pll0_clk = {
+        .name           = "pll0",
+        .parent         = &ref_clk,
+        .pll_data       = &pll0_data,
+        .flags          = CLK_PLL,
+};
+
+static struct clk pll0_aux_clk = {
+        .name           = "pll0_aux_clk",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL | PRE_PLL,
+};
+
+static struct clk pll0_sysclk2 = {
+        .name           = "pll0_sysclk2",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV2,
+};
+
+static struct clk pll0_sysclk3 = {
+        .name           = "pll0_sysclk3",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV3,
+};
+
+static struct clk pll0_sysclk4 = {
+        .name           = "pll0_sysclk4",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV4,
+};
+
+static struct clk pll0_sysclk5 = {
+        .name           = "pll0_sysclk5",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV5,
+};
+
+static struct clk pll0_sysclk6 = {
+        .name           = "pll0_sysclk6",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV6,
+};
+
+static struct clk pll0_sysclk7 = {
+        .name           = "pll0_sysclk7",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV7,
+};
+
+static struct clk i2c0_clk = {
+        .name           = "i2c0",
+        .parent         = &pll0_aux_clk,
+};
+
+static struct clk timerp64_0_clk = {
+        .name           = "timer0",
+        .parent         = &pll0_aux_clk,
+};
+
+static struct clk timerp64_1_clk = {
+        .name           = "timer1",
+        .parent         = &pll0_aux_clk,
+};
+
+static struct clk arm_rom_clk = {
+        .name           = "arm_rom",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_ARM_RAM_ROM,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk scr0_ss_clk = {
+        .name           = "scr0_ss",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_SCR0_SS,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk scr1_ss_clk = {
+        .name           = "scr1_ss",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_SCR1_SS,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk scr2_ss_clk = {
+        .name           = "scr2_ss",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_SCR2_SS,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk dmax_clk = {
+        .name           = "dmax",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_DMAX,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk tpcc_clk = {
+        .name           = "tpcc",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_TPCC,
+        .flags          = ALWAYS_ENABLED | CLK_PSC,
+};
+
+static struct clk tptc0_clk = {
+        .name           = "tptc0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_TPTC0,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk tptc1_clk = {
+        .name           = "tptc1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_TPTC1,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk mmcsd_clk = {
+        .name           = "mmcsd",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_MMC_SD,
+};
+
+static struct clk uart0_clk = {
+        .name           = "uart0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_UART0,
+};
+
+static struct clk uart1_clk = {
+        .name           = "uart1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_UART1,
+        .psc_ctlr       = 1,
+};
+
+static struct clk uart2_clk = {
+        .name           = "uart2",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_UART2,
+        .psc_ctlr       = 1,
+};
+
+static struct clk spi0_clk = {
+        .name           = "spi0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_SPI0,
+};
+
+static struct clk spi1_clk = {
+        .name           = "spi1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_SPI1,
+        .psc_ctlr       = 1,
+};
+
+static struct clk ecap0_clk = {
+        .name           = "ecap0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_ECAP,
+        .psc_ctlr       = 1,
+};
+
+static struct clk ecap1_clk = {
+        .name           = "ecap1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_ECAP,
+        .psc_ctlr       = 1,
+};
+
+static struct clk ecap2_clk = {
+        .name           = "ecap2",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_ECAP,
+        .psc_ctlr       = 1,
+};
+
+static struct clk pwm0_clk = {
+        .name           = "pwm0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_PWM,
+        .psc_ctlr       = 1,
+};
+
+static struct clk pwm1_clk = {
+        .name           = "pwm1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_PWM,
+        .psc_ctlr       = 1,
+};
+
+static struct clk pwm2_clk = {
+        .name           = "pwm2",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_PWM,
+        .psc_ctlr       = 1,
+};
+
+static struct clk eqep0_clk = {
+        .name           = "eqep0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA830_LPSC1_EQEP,
+        .psc_ctlr       = 1,
+};
+
+static struct clk eqep1_clk = {
+        .name           = "eqep1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA830_LPSC1_EQEP,
+        .psc_ctlr       = 1,
+};
+
+static struct clk lcdc_clk = {
+        .name           = "lcdc",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_LCDC,
+        .psc_ctlr       = 1,
+};
+
+static struct clk mcasp0_clk = {
+        .name           = "mcasp0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_McASP0,
+        .psc_ctlr       = 1,
+};
+
+static struct clk mcasp1_clk = {
+        .name           = "mcasp1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA830_LPSC1_McASP1,
+        .psc_ctlr       = 1,
+};
+
+static struct clk mcasp2_clk = {
+        .name           = "mcasp2",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA830_LPSC1_McASP2,
+        .psc_ctlr       = 1,
+};
+
+static struct clk usb20_clk = {
+        .name           = "usb20",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_USB20,
+        .psc_ctlr       = 1,
+};
+
+static struct clk aemif_clk = {
+        .name           = "aemif",
+        .parent         = &pll0_sysclk3,
+        .lpsc           = DA8XX_LPSC0_EMIF25,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk aintc_clk = {
+        .name           = "aintc",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC0_AINTC,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk secu_mgr_clk = {
+        .name           = "secu_mgr",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC0_SECU_MGR,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk emac_clk = {
+        .name           = "emac",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC1_CPGMAC,
+        .psc_ctlr       = 1,
+};
+
+static struct clk gpio_clk = {
+        .name           = "gpio",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC1_GPIO,
+        .psc_ctlr       = 1,
+};
+
+static struct clk i2c1_clk = {
+        .name           = "i2c1",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC1_I2C,
+        .psc_ctlr       = 1,
+};
+
+static struct clk usb11_clk = {
+        .name           = "usb11",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC1_USB11,
+        .psc_ctlr       = 1,
+};
+
+static struct clk emif3_clk = {
+        .name           = "emif3",
+        .parent         = &pll0_sysclk5,
+        .lpsc           = DA8XX_LPSC1_EMIF3C,
+        .flags          = ALWAYS_ENABLED,
+        .psc_ctlr       = 1,
+};
+
+static struct clk arm_clk = {
+        .name           = "arm",
+        .parent         = &pll0_sysclk6,
+        .lpsc           = DA8XX_LPSC0_ARM,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk rmii_clk = {
+        .name           = "rmii",
+        .parent         = &pll0_sysclk7,
+};
+
+static struct davinci_clk da830_clks[] = {
+        CLK(NULL,               "ref",          &ref_clk),
+        CLK(NULL,               "pll0",         &pll0_clk),
+        CLK(NULL,               "pll0_aux",     &pll0_aux_clk),
+        CLK(NULL,               "pll0_sysclk2", &pll0_sysclk2),
+        CLK(NULL,               "pll0_sysclk3", &pll0_sysclk3),
+        CLK(NULL,               "pll0_sysclk4", &pll0_sysclk4),
+        CLK(NULL,               "pll0_sysclk5", &pll0_sysclk5),
+        CLK(NULL,               "pll0_sysclk6", &pll0_sysclk6),
+        CLK(NULL,               "pll0_sysclk7", &pll0_sysclk7),
+        CLK("i2c_davinci.1",    NULL,           &i2c0_clk),
+        CLK(NULL,               "timer0",       &timerp64_0_clk),
+        CLK("watchdog",         NULL,           &timerp64_1_clk),
+        CLK(NULL,               "arm_rom",      &arm_rom_clk),
+        CLK(NULL,               "scr0_ss",      &scr0_ss_clk),
+        CLK(NULL,               "scr1_ss",      &scr1_ss_clk),
+        CLK(NULL,               "scr2_ss",      &scr2_ss_clk),
+        CLK(NULL,               "dmax",         &dmax_clk),
+        CLK(NULL,               "tpcc",         &tpcc_clk),
+        CLK(NULL,               "tptc0",        &tptc0_clk),
+        CLK(NULL,               "tptc1",        &tptc1_clk),
+        CLK("davinci_mmc.0",    NULL,           &mmcsd_clk),
+        CLK(NULL,               "uart0",        &uart0_clk),
+        CLK(NULL,               "uart1",        &uart1_clk),
+        CLK(NULL,               "uart2",        &uart2_clk),
+        CLK("dm_spi.0",         NULL,           &spi0_clk),
+        CLK("dm_spi.1",         NULL,           &spi1_clk),
+        CLK(NULL,               "ecap0",        &ecap0_clk),
+        CLK(NULL,               "ecap1",        &ecap1_clk),
+        CLK(NULL,               "ecap2",        &ecap2_clk),
+        CLK(NULL,               "pwm0",         &pwm0_clk),
+        CLK(NULL,               "pwm1",         &pwm1_clk),
+        CLK(NULL,               "pwm2",         &pwm2_clk),
+        CLK("eqep.0",           NULL,           &eqep0_clk),
+        CLK("eqep.1",           NULL,           &eqep1_clk),
+        CLK("da830_lcdc",       NULL,           &lcdc_clk),
+        CLK("davinci-mcasp.0",  NULL,           &mcasp0_clk),
+        CLK("davinci-mcasp.1",  NULL,           &mcasp1_clk),
+        CLK("davinci-mcasp.2",  NULL,           &mcasp2_clk),
+        CLK("musb_hdrc",        NULL,           &usb20_clk),
+        CLK(NULL,               "aemif",        &aemif_clk),
+        CLK(NULL,               "aintc",        &aintc_clk),
+        CLK(NULL,               "secu_mgr",     &secu_mgr_clk),
+        CLK("davinci_emac.1",   NULL,           &emac_clk),
+        CLK(NULL,               "gpio",         &gpio_clk),
+        CLK("i2c_davinci.2",    NULL,           &i2c1_clk),
+        CLK(NULL,               "usb11",        &usb11_clk),
+        CLK(NULL,               "emif3",        &emif3_clk),
+        CLK(NULL,               "arm",          &arm_clk),
+        CLK(NULL,               "rmii",         &rmii_clk),
+        CLK(NULL,               NULL,           NULL),
+};
+
+/*
+ * Device specific mux setup
+ *
+ *           soc      description       mux    mode    mode   mux       dbg
+ *                                      reg   offset   mask   mode
+ */
+static const struct mux_config da830_pins[] = {
+#ifdef CONFIG_DAVINCI_MUX
+        MUX_CFG(DA830, GPIO7_14,        0,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, RTCK,            0,      0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_15,        0,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMU_0,           0,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, EMB_SDCKE,       0,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_CLK_GLUE,    0,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_CLK,         0,      12,     0xf,    2,      false)
+        MUX_CFG(DA830, NEMB_CS_0,       0,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMB_CAS,        0,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMB_RAS,        0,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMB_WE,         0,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_BA_1,        1,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_BA_0,        1,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_0,         1,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_1,         1,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_2,         1,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_3,         1,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_4,         1,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_5,         1,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, GPIO7_0,         1,      0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_1,         1,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_2,         1,      8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_3,         1,      12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_4,         1,      16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_5,         1,      20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_6,         1,      24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_7,         1,      28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMB_A_6,         2,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_7,         2,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_8,         2,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_9,         2,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_10,        2,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_11,        2,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_12,        2,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_31,        2,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, GPIO7_8,         2,      0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_9,         2,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_10,        2,      8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_11,        2,      12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_12,        2,      16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_13,        2,      20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_13,        2,      24,     0xf,    8,      false)
+        MUX_CFG(DA830, EMB_D_30,        3,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_29,        3,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_28,        3,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_27,        3,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_26,        3,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_25,        3,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_24,        3,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_23,        3,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_22,        4,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_21,        4,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_20,        4,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_19,        4,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_18,        4,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_17,        4,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_16,        4,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMB_WE_DQM_3,   4,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMB_WE_DQM_2,   5,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_0,         5,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_1,         5,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_2,         5,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_3,         5,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_4,         5,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_5,         5,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_6,         5,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, GPIO6_0,         5,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_1,         5,      8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_2,         5,      12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_3,         5,      16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_4,         5,      20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_5,         5,      24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_6,         5,      28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMB_D_7,         6,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_8,         6,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_9,         6,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_10,        6,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_11,        6,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_12,        6,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_13,        6,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_14,        6,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, GPIO6_7,         6,      0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_8,         6,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_9,         6,      8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_10,        6,      12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_11,        6,      16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_12,        6,      20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_13,        6,      24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_14,        6,      28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMB_D_15,        7,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, NEMB_WE_DQM_1,   7,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, NEMB_WE_DQM_0,   7,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, SPI0_SOMI_0,     7,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, SPI0_SIMO_0,     7,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, SPI0_CLK,        7,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, NSPI0_ENA,       7,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, NSPI0_SCS_0,     7,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, EQEP0I,          7,      12,     0xf,    2,      false)
+        MUX_CFG(DA830, EQEP0S,          7,      16,     0xf,    2,      false)
+        MUX_CFG(DA830, EQEP1I,          7,      20,     0xf,    2,      false)
+        MUX_CFG(DA830, NUART0_CTS,      7,      24,     0xf,    2,      false)
+        MUX_CFG(DA830, NUART0_RTS,      7,      28,     0xf,    2,      false)
+        MUX_CFG(DA830, EQEP0A,          7,      24,     0xf,    4,      false)
+        MUX_CFG(DA830, EQEP0B,          7,      28,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO6_15,        7,      0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_14,        7,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_15,        7,      8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_0,         7,      12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_1,         7,      16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_2,         7,      20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_3,         7,      24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_4,         7,      28,     0xf,    8,      false)
+        MUX_CFG(DA830, SPI1_SOMI_0,     8,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, SPI1_SIMO_0,     8,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, SPI1_CLK,        8,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, UART0_RXD,       8,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, UART0_TXD,       8,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_10,         8,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_11,         8,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, NSPI1_ENA,       8,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, I2C1_SCL,        8,      0,      0xf,    2,      false)
+        MUX_CFG(DA830, I2C1_SDA,        8,      4,      0xf,    2,      false)
+        MUX_CFG(DA830, EQEP1S,          8,      8,      0xf,    2,      false)
+        MUX_CFG(DA830, I2C0_SDA,        8,      12,     0xf,    2,      false)
+        MUX_CFG(DA830, I2C0_SCL,        8,      16,     0xf,    2,      false)
+        MUX_CFG(DA830, UART2_RXD,       8,      28,     0xf,    2,      false)
+        MUX_CFG(DA830, TM64P0_IN12,     8,      12,     0xf,    4,      false)
+        MUX_CFG(DA830, TM64P0_OUT12,    8,      16,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO5_5,         8,      0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_6,         8,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_7,         8,      8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_8,         8,      12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_9,         8,      16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_10,        8,      20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_11,        8,      24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_12,        8,      28,     0xf,    8,      false)
+        MUX_CFG(DA830, NSPI1_SCS_0,     9,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, USB0_DRVVBUS,    9,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, AHCLKX0,         9,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, ACLKX0,          9,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, AFSX0,           9,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, AHCLKR0,         9,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, ACLKR0,          9,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, AFSR0,           9,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, UART2_TXD,       9,      0,      0xf,    2,      false)
+        MUX_CFG(DA830, AHCLKX2,         9,      8,      0xf,    2,      false)
+        MUX_CFG(DA830, ECAP0_APWM0,     9,      12,     0xf,    2,      false)
+        MUX_CFG(DA830, RMII_MHZ_50_CLK, 9,      20,     0xf,    2,      false)
+        MUX_CFG(DA830, ECAP1_APWM1,     9,      24,     0xf,    2,      false)
+        MUX_CFG(DA830, USB_REFCLKIN,    9,      8,      0xf,    4,      false)
+        MUX_CFG(DA830, GPIO5_13,        9,      0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_15,        9,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_11,        9,      8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_12,        9,      12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_13,        9,      16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_14,        9,      20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_15,        9,      24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_12,        9,      28,     0xf,    8,      false)
+        MUX_CFG(DA830, AMUTE0,          10,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_0,          10,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_1,          10,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_2,          10,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_3,          10,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_4,          10,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_5,          10,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_6,          10,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, RMII_TXD_0,      10,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, RMII_TXD_1,      10,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, RMII_TXEN,       10,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, RMII_CRS_DV,     10,     16,     0xf,    2,      false)
+        MUX_CFG(DA830, RMII_RXD_0,      10,     20,     0xf,    2,      false)
+        MUX_CFG(DA830, RMII_RXD_1,      10,     24,     0xf,    2,      false)
+        MUX_CFG(DA830, RMII_RXER,       10,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, AFSR2,           10,     4,      0xf,    4,      false)
+        MUX_CFG(DA830, ACLKX2,          10,     8,      0xf,    4,      false)
+        MUX_CFG(DA830, AXR2_3,          10,     12,     0xf,    4,      false)
+        MUX_CFG(DA830, AXR2_2,          10,     16,     0xf,    4,      false)
+        MUX_CFG(DA830, AXR2_1,          10,     20,     0xf,    4,      false)
+        MUX_CFG(DA830, AFSX2,           10,     24,     0xf,    4,      false)
+        MUX_CFG(DA830, ACLKR2,          10,     28,     0xf,    4,      false)
+        MUX_CFG(DA830, NRESETOUT,       10,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_0,         10,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_1,         10,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_2,         10,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_3,         10,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_4,         10,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_5,         10,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_6,         10,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, AXR0_7,          11,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_8,          11,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, UART1_RXD,       11,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, UART1_TXD,       11,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_11,         11,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, AHCLKX1,         11,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, ACLKX1,          11,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, AFSX1,           11,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, MDIO_CLK,        11,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, MDIO_D,          11,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, AXR0_9,          11,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, AXR0_10,         11,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, EPWM0B,          11,     20,     0xf,    2,      false)
+        MUX_CFG(DA830, EPWM0A,          11,     24,     0xf,    2,      false)
+        MUX_CFG(DA830, EPWMSYNCI,       11,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, AXR2_0,          11,     16,     0xf,    4,      false)
+        MUX_CFG(DA830, EPWMSYNC0,       11,     28,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO3_7,         11,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_8,         11,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_9,         11,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_10,        11,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_11,        11,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_14,        11,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_15,        11,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_10,        11,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, AHCLKR1,         12,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, ACLKR1,          12,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, AFSR1,           12,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, AMUTE1,          12,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_0,          12,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_1,          12,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_2,          12,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_3,          12,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, ECAP2_APWM2,     12,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, EHRPWMGLUETZ,    12,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, EQEP1A,          12,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, GPIO4_11,        12,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_12,        12,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_13,        12,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_14,        12,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_0,         12,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_1,         12,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_2,         12,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_3,         12,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, AXR1_4,          13,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_5,          13,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_6,          13,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_7,          13,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_8,          13,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_9,          13,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_0,         13,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_1,         13,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, EQEP1B,          13,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, EPWM2B,          13,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, EPWM2A,          13,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, EPWM1B,          13,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, EPWM1A,          13,     16,     0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_DAT_0,     13,     24,     0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_DAT_1,     13,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_0,       13,     24,     0xf,    4,      false)
+        MUX_CFG(DA830, UHPI_HD_1,       13,     28,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO4_4,         13,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_5,         13,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_6,         13,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_7,         13,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_8,         13,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_9,         13,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_0,         13,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_1,         13,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMA_D_2,         14,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_3,         14,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_4,         14,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_5,         14,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_6,         14,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_7,         14,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_8,         14,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_9,         14,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, MMCSD_DAT_2,     14,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_DAT_3,     14,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_DAT_4,     14,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_DAT_5,     14,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_DAT_6,     14,     16,     0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_DAT_7,     14,     20,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_8,       14,     24,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_9,       14,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_2,       14,     0,      0xf,    4,      false)
+        MUX_CFG(DA830, UHPI_HD_3,       14,     4,      0xf,    4,      false)
+        MUX_CFG(DA830, UHPI_HD_4,       14,     8,      0xf,    4,      false)
+        MUX_CFG(DA830, UHPI_HD_5,       14,     12,     0xf,    4,      false)
+        MUX_CFG(DA830, UHPI_HD_6,       14,     16,     0xf,    4,      false)
+        MUX_CFG(DA830, UHPI_HD_7,       14,     20,     0xf,    4,      false)
+        MUX_CFG(DA830, LCD_D_8,         14,     24,     0xf,    4,      false)
+        MUX_CFG(DA830, LCD_D_9,         14,     28,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO0_2,         14,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_3,         14,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_4,         14,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_5,         14,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_6,         14,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_7,         14,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_8,         14,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_9,         14,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMA_D_10,        15,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_11,        15,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_12,        15,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_13,        15,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_14,        15,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_15,        15,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_0,         15,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_1,         15,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, UHPI_HD_10,      15,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_11,      15,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_12,      15,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_13,      15,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_14,      15,     16,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_15,      15,     20,     0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_7,         15,     24,     0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_CLK,       15,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_10,        15,     0,      0xf,    4,      false)
+        MUX_CFG(DA830, LCD_D_11,        15,     4,      0xf,    4,      false)
+        MUX_CFG(DA830, LCD_D_12,        15,     8,      0xf,    4,      false)
+        MUX_CFG(DA830, LCD_D_13,        15,     12,     0xf,    4,      false)
+        MUX_CFG(DA830, LCD_D_14,        15,     16,     0xf,    4,      false)
+        MUX_CFG(DA830, LCD_D_15,        15,     20,     0xf,    4,      false)
+        MUX_CFG(DA830, UHPI_HCNTL0,     15,     28,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO0_10,        15,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_11,        15,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_12,        15,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_13,        15,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_14,        15,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_15,        15,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_0,         15,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_1,         15,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMA_A_2,         16,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_3,         16,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_4,         16,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_5,         16,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_6,         16,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_7,         16,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_8,         16,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_9,         16,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, MMCSD_CMD,       16,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_6,         16,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_3,         16,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_2,         16,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_1,         16,     16,     0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_0,         16,     20,     0xf,    2,      false)
+        MUX_CFG(DA830, LCD_PCLK,        16,     24,     0xf,    2,      false)
+        MUX_CFG(DA830, LCD_HSYNC,       16,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HCNTL1,     16,     0,      0xf,    4,      false)
+        MUX_CFG(DA830, GPIO1_2,         16,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_3,         16,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_4,         16,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_5,         16,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_6,         16,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_7,         16,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_8,         16,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_9,         16,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMA_A_10,        17,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_11,        17,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_12,        17,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_BA_1,        17,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_BA_0,        17,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_CLK,         17,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_SDCKE,       17,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_CAS,        17,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, LCD_VSYNC,       17,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, NLCD_AC_ENB_CS,  17,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, LCD_MCLK,        17,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_5,         17,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_4,         17,     16,     0xf,    2,      false)
+        MUX_CFG(DA830, OBSCLK,          17,     20,     0xf,    2,      false)
+        MUX_CFG(DA830, NEMA_CS_4,       17,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HHWIL,      17,     12,     0xf,    4,      false)
+        MUX_CFG(DA830, AHCLKR2,         17,     20,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO1_10,        17,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_11,        17,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_12,        17,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_13,        17,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_14,        17,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_15,        17,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_0,         17,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_1,         17,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, NEMA_RAS,        18,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_WE,         18,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_CS_0,       18,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_CS_2,       18,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_CS_3,       18,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_OE,         18,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_WE_DQM_1,   18,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_WE_DQM_0,   18,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_CS_5,       18,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HRNW,       18,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, NUHPI_HAS,       18,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, NUHPI_HCS,       18,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, NUHPI_HDS1,      18,     20,     0xf,    2,      false)
+        MUX_CFG(DA830, NUHPI_HDS2,      18,     24,     0xf,    2,      false)
+        MUX_CFG(DA830, NUHPI_HINT,      18,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, AXR0_12,         18,     4,      0xf,    4,      false)
+        MUX_CFG(DA830, AMUTE2,          18,     16,     0xf,    4,      false)
+        MUX_CFG(DA830, AXR0_13,         18,     20,     0xf,    4,      false)
+        MUX_CFG(DA830, AXR0_14,         18,     24,     0xf,    4,      false)
+        MUX_CFG(DA830, AXR0_15,         18,     28,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO2_2,         18,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_3,         18,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_4,         18,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_5,         18,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_6,         18,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_7,         18,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_8,         18,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_9,         18,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMA_WAIT_0,      19,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, NUHPI_HRDY,      19,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, GPIO2_10,        19,     0,      0xf,    8,      false)
+#endif
+};
+
+const short da830_emif25_pins[] __initdata = {
+        DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
+        DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
+        DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11,
+        DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15,
+        DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
+        DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
+        DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
+        DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK,
+        DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE,
+        DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE,
+        DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0,
+        -1
+};
+
+const short da830_spi0_pins[] __initdata = {
+        DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA,
+        DA830_NSPI0_SCS_0,
+        -1
+};
+
+const short da830_spi1_pins[] __initdata = {
+        DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA,
+        DA830_NSPI1_SCS_0,
+        -1
+};
+
+const short da830_mmc_sd_pins[] __initdata = {
+        DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
+        DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
+        DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
+        DA830_MMCSD_CMD,
+        -1
+};
+
+const short da830_uart0_pins[] __initdata = {
+        DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD,
+        -1
+};
+
+const short da830_uart1_pins[] __initdata = {
+        DA830_UART1_RXD, DA830_UART1_TXD,
+        -1
+};
+
+const short da830_uart2_pins[] __initdata = {
+        DA830_UART2_RXD, DA830_UART2_TXD,
+        -1
+};
+
+const short da830_usb20_pins[] __initdata = {
+        DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN,
+        -1
+};
+
+const short da830_usb11_pins[] __initdata = {
+        DA830_USB_REFCLKIN,
+        -1
+};
+
+const short da830_uhpi_pins[] __initdata = {
+        DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3,
+        DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7,
+        DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11,
+        DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15,
+        DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW,
+        DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2,
+        DA830_NUHPI_HINT, DA830_NUHPI_HRDY,
+        -1
+};
+
+const short da830_cpgmac_pins[] __initdata = {
+        DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV,
+        DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK,
+        DA830_MDIO_D,
+        -1
+};
+
+const short da830_emif3c_pins[] __initdata = {
+        DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0,
+        DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1,
+        DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2,
+        DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6,
+        DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10,
+        DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3,
+        DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2,
+        DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6,
+        DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10,
+        DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14,
+        DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18,
+        DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22,
+        DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26,
+        DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30,
+        DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0,
+        -1
+};
+
+const short da830_mcasp0_pins[] __initdata = {
+        DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0,
+        DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0,
+        DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3,
+        DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7,
+        DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11,
+        DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15,
+        -1
+};
+
+const short da830_mcasp1_pins[] __initdata = {
+        DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1,
+        DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1,
+        DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3,
+        DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7,
+        DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11,
+        -1
+};
+
+const short da830_mcasp2_pins[] __initdata = {
+        DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2,
+        DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2,
+        DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3,
+        -1
+};
+
+const short da830_i2c0_pins[] __initdata = {
+        DA830_I2C0_SDA, DA830_I2C0_SCL,
+        -1
+};
+
+const short da830_i2c1_pins[] __initdata = {
+        DA830_I2C1_SCL, DA830_I2C1_SDA,
+        -1
+};
+
+const short da830_lcdcntl_pins[] __initdata = {
+        DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3,
+        DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7,
+        DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11,
+        DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15,
+        DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS,
+        DA830_LCD_MCLK,
+        -1
+};
+
+const short da830_pwm_pins[] __initdata = {
+        DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A,
+        DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ,
+        DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A,
+        -1
+};
+
+const short da830_ecap0_pins[] __initdata = {
+        DA830_ECAP0_APWM0,
+        -1
+};
+
+const short da830_ecap1_pins[] __initdata = {
+        DA830_ECAP1_APWM1,
+        -1
+};
+
+const short da830_ecap2_pins[] __initdata = {
+        DA830_ECAP2_APWM2,
+        -1
+};
+
+const short da830_eqep0_pins[] __initdata = {
+        DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B,
+        -1
+};
+
+const short da830_eqep1_pins[] __initdata = {
+        DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B,
+        -1
+};
+
+/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
+static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = {
+        [IRQ_DA8XX_COMMTX]              = 7,
+        [IRQ_DA8XX_COMMRX]              = 7,
+        [IRQ_DA8XX_NINT]                = 7,
+        [IRQ_DA8XX_EVTOUT0]             = 7,
+        [IRQ_DA8XX_EVTOUT1]             = 7,
+        [IRQ_DA8XX_EVTOUT2]             = 7,
+        [IRQ_DA8XX_EVTOUT3]             = 7,
+        [IRQ_DA8XX_EVTOUT4]             = 7,
+        [IRQ_DA8XX_EVTOUT5]             = 7,
+        [IRQ_DA8XX_EVTOUT6]             = 7,
+        [IRQ_DA8XX_EVTOUT6]             = 7,
+        [IRQ_DA8XX_EVTOUT7]             = 7,
+        [IRQ_DA8XX_CCINT0]              = 7,
+        [IRQ_DA8XX_CCERRINT]            = 7,
+        [IRQ_DA8XX_TCERRINT0]           = 7,
+        [IRQ_DA8XX_AEMIFINT]            = 7,
+        [IRQ_DA8XX_I2CINT0]             = 7,
+        [IRQ_DA8XX_MMCSDINT0]           = 7,
+        [IRQ_DA8XX_MMCSDINT1]           = 7,
+        [IRQ_DA8XX_ALLINT0]             = 7,
+        [IRQ_DA8XX_RTC]                 = 7,
+        [IRQ_DA8XX_SPINT0]              = 7,
+        [IRQ_DA8XX_TINT12_0]            = 7,
+        [IRQ_DA8XX_TINT34_0]            = 7,
+        [IRQ_DA8XX_TINT12_1]            = 7,
+        [IRQ_DA8XX_TINT34_1]            = 7,
+        [IRQ_DA8XX_UARTINT0]            = 7,
+        [IRQ_DA8XX_KEYMGRINT]           = 7,
+        [IRQ_DA8XX_SECINT]              = 7,
+        [IRQ_DA8XX_SECKEYERR]           = 7,
+        [IRQ_DA830_MPUERR]              = 7,
+        [IRQ_DA830_IOPUERR]             = 7,
+        [IRQ_DA830_BOOTCFGERR]          = 7,
+        [IRQ_DA8XX_CHIPINT0]            = 7,
+        [IRQ_DA8XX_CHIPINT1]            = 7,
+        [IRQ_DA8XX_CHIPINT2]            = 7,
+        [IRQ_DA8XX_CHIPINT3]            = 7,
+        [IRQ_DA8XX_TCERRINT1]           = 7,
+        [IRQ_DA8XX_C0_RX_THRESH_PULSE]  = 7,
+        [IRQ_DA8XX_C0_RX_PULSE]         = 7,
+        [IRQ_DA8XX_C0_TX_PULSE]         = 7,
+        [IRQ_DA8XX_C0_MISC_PULSE]       = 7,
+        [IRQ_DA8XX_C1_RX_THRESH_PULSE]  = 7,
+        [IRQ_DA8XX_C1_RX_PULSE]         = 7,
+        [IRQ_DA8XX_C1_TX_PULSE]         = 7,
+        [IRQ_DA8XX_C1_MISC_PULSE]       = 7,
+        [IRQ_DA8XX_MEMERR]              = 7,
+        [IRQ_DA8XX_GPIO0]               = 7,
+        [IRQ_DA8XX_GPIO1]               = 7,
+        [IRQ_DA8XX_GPIO2]               = 7,
+        [IRQ_DA8XX_GPIO3]               = 7,
+        [IRQ_DA8XX_GPIO4]               = 7,
+        [IRQ_DA8XX_GPIO5]               = 7,
+        [IRQ_DA8XX_GPIO6]               = 7,
+        [IRQ_DA8XX_GPIO7]               = 7,
+        [IRQ_DA8XX_GPIO8]               = 7,
+        [IRQ_DA8XX_I2CINT1]             = 7,
+        [IRQ_DA8XX_LCDINT]              = 7,
+        [IRQ_DA8XX_UARTINT1]            = 7,
+        [IRQ_DA8XX_MCASPINT]            = 7,
+        [IRQ_DA8XX_ALLINT1]             = 7,
+        [IRQ_DA8XX_SPINT1]              = 7,
+        [IRQ_DA8XX_UHPI_INT1]           = 7,
+        [IRQ_DA8XX_USB_INT]             = 7,
+        [IRQ_DA8XX_IRQN]                = 7,
+        [IRQ_DA8XX_RWAKEUP]             = 7,
+        [IRQ_DA8XX_UARTINT2]            = 7,
+        [IRQ_DA8XX_DFTSSINT]            = 7,
+        [IRQ_DA8XX_EHRPWM0]             = 7,
+        [IRQ_DA8XX_EHRPWM0TZ]           = 7,
+        [IRQ_DA8XX_EHRPWM1]             = 7,
+        [IRQ_DA8XX_EHRPWM1TZ]           = 7,
+        [IRQ_DA830_EHRPWM2]             = 7,
+        [IRQ_DA830_EHRPWM2TZ]           = 7,
+        [IRQ_DA8XX_ECAP0]               = 7,
+        [IRQ_DA8XX_ECAP1]               = 7,
+        [IRQ_DA8XX_ECAP2]               = 7,
+        [IRQ_DA830_EQEP0]               = 7,
+        [IRQ_DA830_EQEP1]               = 7,
+        [IRQ_DA830_T12CMPINT0_0]        = 7,
+        [IRQ_DA830_T12CMPINT1_0]        = 7,
+        [IRQ_DA830_T12CMPINT2_0]        = 7,
+        [IRQ_DA830_T12CMPINT3_0]        = 7,
+        [IRQ_DA830_T12CMPINT4_0]        = 7,
+        [IRQ_DA830_T12CMPINT5_0]        = 7,
+        [IRQ_DA830_T12CMPINT6_0]        = 7,
+        [IRQ_DA830_T12CMPINT7_0]        = 7,
+        [IRQ_DA830_T12CMPINT0_1]        = 7,
+        [IRQ_DA830_T12CMPINT1_1]        = 7,
+        [IRQ_DA830_T12CMPINT2_1]        = 7,
+        [IRQ_DA830_T12CMPINT3_1]        = 7,
+        [IRQ_DA830_T12CMPINT4_1]        = 7,
+        [IRQ_DA830_T12CMPINT5_1]        = 7,
+        [IRQ_DA830_T12CMPINT6_1]        = 7,
+        [IRQ_DA830_T12CMPINT7_1]        = 7,
+        [IRQ_DA8XX_ARMCLKSTOPREQ]       = 7,
+};
+
+static struct map_desc da830_io_desc[] = {
+        {
+                .virtual        = IO_VIRT,
+                .pfn            = __phys_to_pfn(IO_PHYS),
+                .length         = IO_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = DA8XX_CP_INTC_VIRT,
+                .pfn            = __phys_to_pfn(DA8XX_CP_INTC_BASE),
+                .length         = DA8XX_CP_INTC_SIZE,
+                .type           = MT_DEVICE
+        },
+};
+
+static void __iomem *da830_psc_bases[] = {
+        IO_ADDRESS(DA8XX_PSC0_BASE),
+        IO_ADDRESS(DA8XX_PSC1_BASE),
+};
+
+/* Contents of JTAG ID register used to identify exact cpu type */
+static struct davinci_id da830_ids[] = {
+        {
+                .variant        = 0x0,
+                .part_no        = 0xb7df,
+                .manufacturer   = 0x017,        /* 0x02f >> 1 */
+                .cpu_id         = DAVINCI_CPU_ID_DA830,
+                .name           = "da830/omap l137",
+        },
+};
+
+static struct davinci_timer_instance da830_timer_instance[2] = {
+        {
+                .base           = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
+                .bottom_irq     = IRQ_DA8XX_TINT12_0,
+                .top_irq        = IRQ_DA8XX_TINT34_0,
+                .cmp_off        = DA830_CMP12_0,
+                .cmp_irq        = IRQ_DA830_T12CMPINT0_0,
+        },
+        {
+                .base           = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
+                .bottom_irq     = IRQ_DA8XX_TINT12_1,
+                .top_irq        = IRQ_DA8XX_TINT34_1,
+                .cmp_off        = DA830_CMP12_0,
+                .cmp_irq        = IRQ_DA830_T12CMPINT0_1,
+        },
+};
+
+/*
+ * T0_BOT: Timer 0, bottom              : Used for clock_event & clocksource
+ * T0_TOP: Timer 0, top                 : Used by DSP
+ * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
+ */
+static struct davinci_timer_info da830_timer_info = {
+        .timers         = da830_timer_instance,
+        .clockevent_id  = T0_BOT,
+        .clocksource_id = T0_BOT,
+};
+
+static struct davinci_soc_info davinci_soc_info_da830 = {
+        .io_desc                = da830_io_desc,
+        .io_desc_num            = ARRAY_SIZE(da830_io_desc),
+        .jtag_id_base           = IO_ADDRESS(DA8XX_JTAG_ID_REG),
+        .ids                    = da830_ids,
+        .ids_num                = ARRAY_SIZE(da830_ids),
+        .cpu_clks               = da830_clks,
+        .psc_bases              = da830_psc_bases,
+        .psc_bases_num          = ARRAY_SIZE(da830_psc_bases),
+        .pinmux_base            = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120),
+        .pinmux_pins            = da830_pins,
+        .pinmux_pins_num        = ARRAY_SIZE(da830_pins),
+        .intc_base              = (void __iomem *)DA8XX_CP_INTC_VIRT,
+        .intc_type              = DAVINCI_INTC_TYPE_CP_INTC,
+        .intc_irq_prios         = da830_default_priorities,
+        .intc_irq_num           = DA830_N_CP_INTC_IRQ,
+        .timer_info             = &da830_timer_info,
+        .gpio_base              = IO_ADDRESS(DA8XX_GPIO_BASE),
+        .gpio_num               = 128,
+        .gpio_irq               = IRQ_DA8XX_GPIO0,
+        .serial_dev             = &da8xx_serial_device,
+        .emac_pdata             = &da8xx_emac_pdata,
+};
+
+void __init da830_init(void)
+{
+        davinci_common_init(&davinci_soc_info_da830);
+}
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
new file mode 100644
index 000000000000..192d719a47df
--- /dev/null
+++ b/arch/arm/mach-davinci/da850.c
@@ -0,0 +1,820 @@
+/*
+ * TI DA850/OMAP-L138 chip specific setup
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Derived from: arch/arm/mach-davinci/da830.c
+ * Original Copyrights follow:
+ *
+ * 2009 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/clock.h>
+#include <mach/psc.h>
+#include <mach/mux.h>
+#include <mach/irqs.h>
+#include <mach/cputype.h>
+#include <mach/common.h>
+#include <mach/time.h>
+#include <mach/da8xx.h>
+
+#include "clock.h"
+#include "mux.h"
+
+#define DA850_PLL1_BASE         0x01e1a000
+#define DA850_TIMER64P2_BASE    0x01f0c000
+#define DA850_TIMER64P3_BASE    0x01f0d000
+
+#define DA850_REF_FREQ          24000000
+
+static struct pll_data pll0_data = {
+        .num            = 1,
+        .phys_base      = DA8XX_PLL0_BASE,
+        .flags          = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
+};
+
+static struct clk ref_clk = {
+        .name           = "ref_clk",
+        .rate           = DA850_REF_FREQ,
+};
+
+static struct clk pll0_clk = {
+        .name           = "pll0",
+        .parent         = &ref_clk,
+        .pll_data       = &pll0_data,
+        .flags          = CLK_PLL,
+};
+
+static struct clk pll0_aux_clk = {
+        .name           = "pll0_aux_clk",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL | PRE_PLL,
+};
+
+static struct clk pll0_sysclk2 = {
+        .name           = "pll0_sysclk2",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV2,
+};
+
+static struct clk pll0_sysclk3 = {
+        .name           = "pll0_sysclk3",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV3,
+};
+
+static struct clk pll0_sysclk4 = {
+        .name           = "pll0_sysclk4",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV4,
+};
+
+static struct clk pll0_sysclk5 = {
+        .name           = "pll0_sysclk5",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV5,
+};
+
+static struct clk pll0_sysclk6 = {
+        .name           = "pll0_sysclk6",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV6,
+};
+
+static struct clk pll0_sysclk7 = {
+        .name           = "pll0_sysclk7",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV7,
+};
+
+static struct pll_data pll1_data = {
+        .num            = 2,
+        .phys_base      = DA850_PLL1_BASE,
+        .flags          = PLL_HAS_POSTDIV,
+};
+
+static struct clk pll1_clk = {
+        .name           = "pll1",
+        .parent         = &ref_clk,
+        .pll_data       = &pll1_data,
+        .flags          = CLK_PLL,
+};
+
+static struct clk pll1_aux_clk = {
+        .name           = "pll1_aux_clk",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL | PRE_PLL,
+};
+
+static struct clk pll1_sysclk2 = {
+        .name           = "pll1_sysclk2",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV2,
+};
+
+static struct clk pll1_sysclk3 = {
+        .name           = "pll1_sysclk3",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV3,
+};
+
+static struct clk pll1_sysclk4 = {
+        .name           = "pll1_sysclk4",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV4,
+};
+
+static struct clk pll1_sysclk5 = {
+        .name           = "pll1_sysclk5",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV5,
+};
+
+static struct clk pll1_sysclk6 = {
+        .name           = "pll0_sysclk6",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV6,
+};
+
+static struct clk pll1_sysclk7 = {
+        .name           = "pll1_sysclk7",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV7,
+};
+
+static struct clk i2c0_clk = {
+        .name           = "i2c0",
+        .parent         = &pll0_aux_clk,
+};
+
+static struct clk timerp64_0_clk = {
+        .name           = "timer0",
+        .parent         = &pll0_aux_clk,
+};
+
+static struct clk timerp64_1_clk = {
+        .name           = "timer1",
+        .parent         = &pll0_aux_clk,
+};
+
+static struct clk arm_rom_clk = {
+        .name           = "arm_rom",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_ARM_RAM_ROM,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk tpcc0_clk = {
+        .name           = "tpcc0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_TPCC,
+        .flags          = ALWAYS_ENABLED | CLK_PSC,
+};
+
+static struct clk tptc0_clk = {
+        .name           = "tptc0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_TPTC0,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk tptc1_clk = {
+        .name           = "tptc1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_TPTC1,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk tpcc1_clk = {
+        .name           = "tpcc1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA850_LPSC1_TPCC1,
+        .flags          = CLK_PSC | ALWAYS_ENABLED,
+        .psc_ctlr       = 1,
+};
+
+static struct clk tptc2_clk = {
+        .name           = "tptc2",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA850_LPSC1_TPTC2,
+        .flags          = ALWAYS_ENABLED,
+        .psc_ctlr       = 1,
+};
+
+static struct clk uart0_clk = {
+        .name           = "uart0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_UART0,
+};
+
+static struct clk uart1_clk = {
+        .name           = "uart1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_UART1,
+        .psc_ctlr       = 1,
+};
+
+static struct clk uart2_clk = {
+        .name           = "uart2",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_UART2,
+        .psc_ctlr       = 1,
+};
+
+static struct clk aintc_clk = {
+        .name           = "aintc",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC0_AINTC,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk gpio_clk = {
+        .name           = "gpio",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC1_GPIO,
+        .psc_ctlr       = 1,
+};
+
+static struct clk i2c1_clk = {
+        .name           = "i2c1",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC1_I2C,
+        .psc_ctlr       = 1,
+};
+
+static struct clk emif3_clk = {
+        .name           = "emif3",
+        .parent         = &pll0_sysclk5,
+        .lpsc           = DA8XX_LPSC1_EMIF3C,
+        .flags          = ALWAYS_ENABLED,
+        .psc_ctlr       = 1,
+};
+
+static struct clk arm_clk = {
+        .name           = "arm",
+        .parent         = &pll0_sysclk6,
+        .lpsc           = DA8XX_LPSC0_ARM,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk rmii_clk = {
+        .name           = "rmii",
+        .parent         = &pll0_sysclk7,
+};
+
+static struct clk emac_clk = {
+        .name           = "emac",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC1_CPGMAC,
+        .psc_ctlr       = 1,
+};
+
+static struct clk mcasp_clk = {
+        .name           = "mcasp",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_McASP0,
+        .psc_ctlr       = 1,
+};
+
+static struct clk lcdc_clk = {
+        .name           = "lcdc",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_LCDC,
+        .psc_ctlr       = 1,
+};
+
+static struct clk mmcsd_clk = {
+        .name           = "mmcsd",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_MMC_SD,
+};
+
+static struct clk aemif_clk = {
+        .name           = "aemif",
+        .parent         = &pll0_sysclk3,
+        .lpsc           = DA8XX_LPSC0_EMIF25,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct davinci_clk da850_clks[] = {
+        CLK(NULL,               "ref",          &ref_clk),
+        CLK(NULL,               "pll0",         &pll0_clk),
+        CLK(NULL,               "pll0_aux",     &pll0_aux_clk),
+        CLK(NULL,               "pll0_sysclk2", &pll0_sysclk2),
+        CLK(NULL,               "pll0_sysclk3", &pll0_sysclk3),
+        CLK(NULL,               "pll0_sysclk4", &pll0_sysclk4),
+        CLK(NULL,               "pll0_sysclk5", &pll0_sysclk5),
+        CLK(NULL,               "pll0_sysclk6", &pll0_sysclk6),
+        CLK(NULL,               "pll0_sysclk7", &pll0_sysclk7),
+        CLK(NULL,               "pll1",         &pll1_clk),
+        CLK(NULL,               "pll1_aux",     &pll1_aux_clk),
+        CLK(NULL,               "pll1_sysclk2", &pll1_sysclk2),
+        CLK(NULL,               "pll1_sysclk3", &pll1_sysclk3),
+        CLK(NULL,               "pll1_sysclk4", &pll1_sysclk4),
+        CLK(NULL,               "pll1_sysclk5", &pll1_sysclk5),
+        CLK(NULL,               "pll1_sysclk6", &pll1_sysclk6),
+        CLK(NULL,               "pll1_sysclk7", &pll1_sysclk7),
+        CLK("i2c_davinci.1",    NULL,           &i2c0_clk),
+        CLK(NULL,               "timer0",       &timerp64_0_clk),
+        CLK("watchdog",         NULL,           &timerp64_1_clk),
+        CLK(NULL,               "arm_rom",      &arm_rom_clk),
+        CLK(NULL,               "tpcc0",        &tpcc0_clk),
+        CLK(NULL,               "tptc0",        &tptc0_clk),
+        CLK(NULL,               "tptc1",        &tptc1_clk),
+        CLK(NULL,               "tpcc1",        &tpcc1_clk),
+        CLK(NULL,               "tptc2",        &tptc2_clk),
+        CLK(NULL,               "uart0",        &uart0_clk),
+        CLK(NULL,               "uart1",        &uart1_clk),
+        CLK(NULL,               "uart2",        &uart2_clk),
+        CLK(NULL,               "aintc",        &aintc_clk),
+        CLK(NULL,               "gpio",         &gpio_clk),
+        CLK("i2c_davinci.2",    NULL,           &i2c1_clk),
+        CLK(NULL,               "emif3",        &emif3_clk),
+        CLK(NULL,               "arm",          &arm_clk),
+        CLK(NULL,               "rmii",         &rmii_clk),
+        CLK("davinci_emac.1",   NULL,           &emac_clk),
+        CLK("davinci-mcasp.0",  NULL,           &mcasp_clk),
+        CLK("da8xx_lcdc.0",     NULL,           &lcdc_clk),
+        CLK("davinci_mmc.0",    NULL,           &mmcsd_clk),
+        CLK(NULL,               "aemif",        &aemif_clk),
+        CLK(NULL,               NULL,           NULL),
+};
+
+/*
+ * Device specific mux setup
+ *
+ *              soc     description     mux     mode    mode    mux     dbg
+ *                                      reg     offset  mask    mode
+ */
+static const struct mux_config da850_pins[] = {
+#ifdef CONFIG_DAVINCI_MUX
+        /* UART0 function */
+        MUX_CFG(DA850, NUART0_CTS,      3,      24,     15,     2,      false)
+        MUX_CFG(DA850, NUART0_RTS,      3,      28,     15,     2,      false)
+        MUX_CFG(DA850, UART0_RXD,       3,      16,     15,     2,      false)
+        MUX_CFG(DA850, UART0_TXD,       3,      20,     15,     2,      false)
+        /* UART1 function */
+        MUX_CFG(DA850, UART1_RXD,       4,      24,     15,     2,      false)
+        MUX_CFG(DA850, UART1_TXD,       4,      28,     15,     2,      false)
+        /* UART2 function */
+        MUX_CFG(DA850, UART2_RXD,       4,      16,     15,     2,      false)
+        MUX_CFG(DA850, UART2_TXD,       4,      20,     15,     2,      false)
+        /* I2C1 function */
+        MUX_CFG(DA850, I2C1_SCL,        4,      16,     15,     4,      false)
+        MUX_CFG(DA850, I2C1_SDA,        4,      20,     15,     4,      false)
+        /* I2C0 function */
+        MUX_CFG(DA850, I2C0_SDA,        4,      12,     15,     2,      false)
+        MUX_CFG(DA850, I2C0_SCL,        4,      8,      15,     2,      false)
+        /* EMAC function */
+        MUX_CFG(DA850, MII_TXEN,        2,      4,      15,     8,      false)
+        MUX_CFG(DA850, MII_TXCLK,       2,      8,      15,     8,      false)
+        MUX_CFG(DA850, MII_COL,         2,      12,     15,     8,      false)
+        MUX_CFG(DA850, MII_TXD_3,       2,      16,     15,     8,      false)
+        MUX_CFG(DA850, MII_TXD_2,       2,      20,     15,     8,      false)
+        MUX_CFG(DA850, MII_TXD_1,       2,      24,     15,     8,      false)
+        MUX_CFG(DA850, MII_TXD_0,       2,      28,     15,     8,      false)
+        MUX_CFG(DA850, MII_RXCLK,       3,      0,      15,     8,      false)
+        MUX_CFG(DA850, MII_RXDV,        3,      4,      15,     8,      false)
+        MUX_CFG(DA850, MII_RXER,        3,      8,      15,     8,      false)
+        MUX_CFG(DA850, MII_CRS,         3,      12,     15,     8,      false)
+        MUX_CFG(DA850, MII_RXD_3,       3,      16,     15,     8,      false)
+        MUX_CFG(DA850, MII_RXD_2,       3,      20,     15,     8,      false)
+        MUX_CFG(DA850, MII_RXD_1,       3,      24,     15,     8,      false)
+        MUX_CFG(DA850, MII_RXD_0,       3,      28,     15,     8,      false)
+        MUX_CFG(DA850, MDIO_CLK,        4,      0,      15,     8,      false)
+        MUX_CFG(DA850, MDIO_D,          4,      4,      15,     8,      false)
+        /* McASP function */
+        MUX_CFG(DA850,  ACLKR,          0,      0,      15,     1,      false)
+        MUX_CFG(DA850,  ACLKX,          0,      4,      15,     1,      false)
+        MUX_CFG(DA850,  AFSR,           0,      8,      15,     1,      false)
+        MUX_CFG(DA850,  AFSX,           0,      12,     15,     1,      false)
+        MUX_CFG(DA850,  AHCLKR,         0,      16,     15,     1,      false)
+        MUX_CFG(DA850,  AHCLKX,         0,      20,     15,     1,      false)
+        MUX_CFG(DA850,  AMUTE,          0,      24,     15,     1,      false)
+        MUX_CFG(DA850,  AXR_15,         1,      0,      15,     1,      false)
+        MUX_CFG(DA850,  AXR_14,         1,      4,      15,     1,      false)
+        MUX_CFG(DA850,  AXR_13,         1,      8,      15,     1,      false)
+        MUX_CFG(DA850,  AXR_12,         1,      12,     15,     1,      false)
+        MUX_CFG(DA850,  AXR_11,         1,      16,     15,     1,      false)
+        MUX_CFG(DA850,  AXR_10,         1,      20,     15,     1,      false)
+        MUX_CFG(DA850,  AXR_9,          1,      24,     15,     1,      false)
+        MUX_CFG(DA850,  AXR_8,          1,      28,     15,     1,      false)
+        MUX_CFG(DA850,  AXR_7,          2,      0,      15,     1,      false)
+        MUX_CFG(DA850,  AXR_6,          2,      4,      15,     1,      false)
+        MUX_CFG(DA850,  AXR_5,          2,      8,      15,     1,      false)
+        MUX_CFG(DA850,  AXR_4,          2,      12,     15,     1,      false)
+        MUX_CFG(DA850,  AXR_3,          2,      16,     15,     1,      false)
+        MUX_CFG(DA850,  AXR_2,          2,      20,     15,     1,      false)
+        MUX_CFG(DA850,  AXR_1,          2,      24,     15,     1,      false)
+        MUX_CFG(DA850,  AXR_0,          2,      28,     15,     1,      false)
+        /* LCD function */
+        MUX_CFG(DA850, LCD_D_7,         16,     8,      15,     2,      false)
+        MUX_CFG(DA850, LCD_D_6,         16,     12,     15,     2,      false)
+        MUX_CFG(DA850, LCD_D_5,         16,     16,     15,     2,      false)
+        MUX_CFG(DA850, LCD_D_4,         16,     20,     15,     2,      false)
+        MUX_CFG(DA850, LCD_D_3,         16,     24,     15,     2,      false)
+        MUX_CFG(DA850, LCD_D_2,         16,     28,     15,     2,      false)
+        MUX_CFG(DA850, LCD_D_1,         17,     0,      15,     2,      false)
+        MUX_CFG(DA850, LCD_D_0,         17,     4,      15,     2,      false)
+        MUX_CFG(DA850, LCD_D_15,        17,     8,      15,     2,      false)
+        MUX_CFG(DA850, LCD_D_14,        17,     12,     15,     2,      false)
+        MUX_CFG(DA850, LCD_D_13,        17,     16,     15,     2,      false)
+        MUX_CFG(DA850, LCD_D_12,        17,     20,     15,     2,      false)
+        MUX_CFG(DA850, LCD_D_11,        17,     24,     15,     2,      false)
+        MUX_CFG(DA850, LCD_D_10,        17,     28,     15,     2,      false)
+        MUX_CFG(DA850, LCD_D_9,         18,     0,      15,     2,      false)
+        MUX_CFG(DA850, LCD_D_8,         18,     4,      15,     2,      false)
+        MUX_CFG(DA850, LCD_PCLK,        18,     24,     15,     2,      false)
+        MUX_CFG(DA850, LCD_HSYNC,       19,     0,      15,     2,      false)
+        MUX_CFG(DA850, LCD_VSYNC,       19,     4,      15,     2,      false)
+        MUX_CFG(DA850, NLCD_AC_ENB_CS,  19,     24,     15,     2,      false)
+        /* MMC/SD0 function */
+        MUX_CFG(DA850, MMCSD0_DAT_0,    10,     8,      15,     2,      false)
+        MUX_CFG(DA850, MMCSD0_DAT_1,    10,     12,     15,     2,      false)
+        MUX_CFG(DA850, MMCSD0_DAT_2,    10,     16,     15,     2,      false)
+        MUX_CFG(DA850, MMCSD0_DAT_3,    10,     20,     15,     2,      false)
+        MUX_CFG(DA850, MMCSD0_CLK,      10,     0,      15,     2,      false)
+        MUX_CFG(DA850, MMCSD0_CMD,      10,     4,      15,     2,      false)
+        /* EMIF2.5/EMIFA function */
+        MUX_CFG(DA850, EMA_D_7,         9,      0,      15,     1,      false)
+        MUX_CFG(DA850, EMA_D_6,         9,      4,      15,     1,      false)
+        MUX_CFG(DA850, EMA_D_5,         9,      8,      15,     1,      false)
+        MUX_CFG(DA850, EMA_D_4,         9,      12,     15,     1,      false)
+        MUX_CFG(DA850, EMA_D_3,         9,      16,     15,     1,      false)
+        MUX_CFG(DA850, EMA_D_2,         9,      20,     15,     1,      false)
+        MUX_CFG(DA850, EMA_D_1,         9,      24,     15,     1,      false)
+        MUX_CFG(DA850, EMA_D_0,         9,      28,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_1,         12,     24,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_2,         12,     20,     15,     1,      false)
+        MUX_CFG(DA850, NEMA_CS_3,       7,      4,      15,     1,      false)
+        MUX_CFG(DA850, NEMA_CS_4,       7,      8,      15,     1,      false)
+        MUX_CFG(DA850, NEMA_WE,         7,      16,     15,     1,      false)
+        MUX_CFG(DA850, NEMA_OE,         7,      20,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_0,         12,     28,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_3,         12,     16,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_4,         12,     12,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_5,         12,     8,      15,     1,      false)
+        MUX_CFG(DA850, EMA_A_6,         12,     4,      15,     1,      false)
+        MUX_CFG(DA850, EMA_A_7,         12,     0,      15,     1,      false)
+        MUX_CFG(DA850, EMA_A_8,         11,     28,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_9,         11,     24,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_10,        11,     20,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_11,        11,     16,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_12,        11,     12,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_13,        11,     8,      15,     1,      false)
+        MUX_CFG(DA850, EMA_A_14,        11,     4,      15,     1,      false)
+        MUX_CFG(DA850, EMA_A_15,        11,     0,      15,     1,      false)
+        MUX_CFG(DA850, EMA_A_16,        10,     28,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_17,        10,     24,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_18,        10,     20,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_19,        10,     16,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_20,        10,     12,     15,     1,      false)
+        MUX_CFG(DA850, EMA_A_21,        10,     8,      15,     1,      false)
+        MUX_CFG(DA850, EMA_A_22,        10,     4,      15,     1,      false)
+        MUX_CFG(DA850, EMA_A_23,        10,     0,      15,     1,      false)
+        MUX_CFG(DA850, EMA_D_8,         8,      28,     15,     1,      false)
+        MUX_CFG(DA850, EMA_D_9,         8,      24,     15,     1,      false)
+        MUX_CFG(DA850, EMA_D_10,        8,      20,     15,     1,      false)
+        MUX_CFG(DA850, EMA_D_11,        8,      16,     15,     1,      false)
+        MUX_CFG(DA850, EMA_D_12,        8,      12,     15,     1,      false)
+        MUX_CFG(DA850, EMA_D_13,        8,      8,      15,     1,      false)
+        MUX_CFG(DA850, EMA_D_14,        8,      4,      15,     1,      false)
+        MUX_CFG(DA850, EMA_D_15,        8,      0,      15,     1,      false)
+        MUX_CFG(DA850, EMA_BA_1,        5,      24,     15,     1,      false)
+        MUX_CFG(DA850, EMA_CLK,         6,      0,      15,     1,      false)
+        MUX_CFG(DA850, EMA_WAIT_1,      6,      24,     15,     1,      false)
+        MUX_CFG(DA850, NEMA_CS_2,       7,      0,      15,     1,      false)
+        /* GPIO function */
+        MUX_CFG(DA850, GPIO2_15,        5,      0,      15,     8,      false)
+        MUX_CFG(DA850, GPIO8_10,        18,     28,     15,     8,      false)
+        MUX_CFG(DA850, GPIO4_0,         10,     28,     15,     8,      false)
+        MUX_CFG(DA850, GPIO4_1,         10,     24,     15,     8,      false)
+#endif
+};
+
+const short da850_uart0_pins[] __initdata = {
+        DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
+        -1
+};
+
+const short da850_uart1_pins[] __initdata = {
+        DA850_UART1_RXD, DA850_UART1_TXD,
+        -1
+};
+
+const short da850_uart2_pins[] __initdata = {
+        DA850_UART2_RXD, DA850_UART2_TXD,
+        -1
+};
+
+const short da850_i2c0_pins[] __initdata = {
+        DA850_I2C0_SDA, DA850_I2C0_SCL,
+        -1
+};
+
+const short da850_i2c1_pins[] __initdata = {
+        DA850_I2C1_SCL, DA850_I2C1_SDA,
+        -1
+};
+
+const short da850_cpgmac_pins[] __initdata = {
+        DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
+        DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
+        DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
+        DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
+        DA850_MDIO_D,
+        -1
+};
+
+const short da850_mcasp_pins[] __initdata = {
+        DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
+        DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
+        DA850_AXR_11, DA850_AXR_12,
+        -1
+};
+
+const short da850_lcdcntl_pins[] __initdata = {
+        DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, DA850_LCD_D_4,
+        DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, DA850_LCD_D_8,
+        DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, DA850_LCD_D_12,
+        DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, DA850_LCD_PCLK,
+        DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, DA850_GPIO2_15,
+        DA850_GPIO8_10,
+        -1
+};
+
+const short da850_mmcsd0_pins[] __initdata = {
+        DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
+        DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
+        DA850_GPIO4_0, DA850_GPIO4_1,
+        -1
+};
+
+const short da850_nand_pins[] __initdata = {
+        DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
+        DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
+        DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
+        DA850_NEMA_WE, DA850_NEMA_OE,
+        -1
+};
+
+const short da850_nor_pins[] __initdata = {
+        DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
+        DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
+        DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
+        DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
+        DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
+        DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
+        DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
+        DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
+        DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
+        DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
+        DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
+        DA850_EMA_A_22, DA850_EMA_A_23,
+        -1
+};
+
+/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
+static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
+        [IRQ_DA8XX_COMMTX]              = 7,
+        [IRQ_DA8XX_COMMRX]              = 7,
+        [IRQ_DA8XX_NINT]                = 7,
+        [IRQ_DA8XX_EVTOUT0]             = 7,
+        [IRQ_DA8XX_EVTOUT1]             = 7,
+        [IRQ_DA8XX_EVTOUT2]             = 7,
+        [IRQ_DA8XX_EVTOUT3]             = 7,
+        [IRQ_DA8XX_EVTOUT4]             = 7,
+        [IRQ_DA8XX_EVTOUT5]             = 7,
+        [IRQ_DA8XX_EVTOUT6]             = 7,
+        [IRQ_DA8XX_EVTOUT6]             = 7,
+        [IRQ_DA8XX_EVTOUT7]             = 7,
+        [IRQ_DA8XX_CCINT0]              = 7,
+        [IRQ_DA8XX_CCERRINT]            = 7,
+        [IRQ_DA8XX_TCERRINT0]           = 7,
+        [IRQ_DA8XX_AEMIFINT]            = 7,
+        [IRQ_DA8XX_I2CINT0]             = 7,
+        [IRQ_DA8XX_MMCSDINT0]           = 7,
+        [IRQ_DA8XX_MMCSDINT1]           = 7,
+        [IRQ_DA8XX_ALLINT0]             = 7,
+        [IRQ_DA8XX_RTC]                 = 7,
+        [IRQ_DA8XX_SPINT0]              = 7,
+        [IRQ_DA8XX_TINT12_0]            = 7,
+        [IRQ_DA8XX_TINT34_0]            = 7,
+        [IRQ_DA8XX_TINT12_1]            = 7,
+        [IRQ_DA8XX_TINT34_1]            = 7,
+        [IRQ_DA8XX_UARTINT0]            = 7,
+        [IRQ_DA8XX_KEYMGRINT]           = 7,
+        [IRQ_DA8XX_SECINT]              = 7,
+        [IRQ_DA8XX_SECKEYERR]           = 7,
+        [IRQ_DA850_MPUADDRERR0]         = 7,
+        [IRQ_DA850_MPUPROTERR0]         = 7,
+        [IRQ_DA850_IOPUADDRERR0]        = 7,
+        [IRQ_DA850_IOPUPROTERR0]        = 7,
+        [IRQ_DA850_IOPUADDRERR1]        = 7,
+        [IRQ_DA850_IOPUPROTERR1]        = 7,
+        [IRQ_DA850_IOPUADDRERR2]        = 7,
+        [IRQ_DA850_IOPUPROTERR2]        = 7,
+        [IRQ_DA850_BOOTCFG_ADDR_ERR]    = 7,
+        [IRQ_DA850_BOOTCFG_PROT_ERR]    = 7,
+        [IRQ_DA850_MPUADDRERR1]         = 7,
+        [IRQ_DA850_MPUPROTERR1]         = 7,
+        [IRQ_DA850_IOPUADDRERR3]        = 7,
+        [IRQ_DA850_IOPUPROTERR3]        = 7,
+        [IRQ_DA850_IOPUADDRERR4]        = 7,
+        [IRQ_DA850_IOPUPROTERR4]        = 7,
+        [IRQ_DA850_IOPUADDRERR5]        = 7,
+        [IRQ_DA850_IOPUPROTERR5]        = 7,
+        [IRQ_DA850_MIOPU_BOOTCFG_ERR]   = 7,
+        [IRQ_DA8XX_CHIPINT0]            = 7,
+        [IRQ_DA8XX_CHIPINT1]            = 7,
+        [IRQ_DA8XX_CHIPINT2]            = 7,
+        [IRQ_DA8XX_CHIPINT3]            = 7,
+        [IRQ_DA8XX_TCERRINT1]           = 7,
+        [IRQ_DA8XX_C0_RX_THRESH_PULSE]  = 7,
+        [IRQ_DA8XX_C0_RX_PULSE]         = 7,
+        [IRQ_DA8XX_C0_TX_PULSE]         = 7,
+        [IRQ_DA8XX_C0_MISC_PULSE]       = 7,
+        [IRQ_DA8XX_C1_RX_THRESH_PULSE]  = 7,
+        [IRQ_DA8XX_C1_RX_PULSE]         = 7,
+        [IRQ_DA8XX_C1_TX_PULSE]         = 7,
+        [IRQ_DA8XX_C1_MISC_PULSE]       = 7,
+        [IRQ_DA8XX_MEMERR]              = 7,
+        [IRQ_DA8XX_GPIO0]               = 7,
+        [IRQ_DA8XX_GPIO1]               = 7,
+        [IRQ_DA8XX_GPIO2]               = 7,
+        [IRQ_DA8XX_GPIO3]               = 7,
+        [IRQ_DA8XX_GPIO4]               = 7,
+        [IRQ_DA8XX_GPIO5]               = 7,
+        [IRQ_DA8XX_GPIO6]               = 7,
+        [IRQ_DA8XX_GPIO7]               = 7,
+        [IRQ_DA8XX_GPIO8]               = 7,
+        [IRQ_DA8XX_I2CINT1]             = 7,
+        [IRQ_DA8XX_LCDINT]              = 7,
+        [IRQ_DA8XX_UARTINT1]            = 7,
+        [IRQ_DA8XX_MCASPINT]            = 7,
+        [IRQ_DA8XX_ALLINT1]             = 7,
+        [IRQ_DA8XX_SPINT1]              = 7,
+        [IRQ_DA8XX_UHPI_INT1]           = 7,
+        [IRQ_DA8XX_USB_INT]             = 7,
+        [IRQ_DA8XX_IRQN]                = 7,
+        [IRQ_DA8XX_RWAKEUP]             = 7,
+        [IRQ_DA8XX_UARTINT2]            = 7,
+        [IRQ_DA8XX_DFTSSINT]            = 7,
+        [IRQ_DA8XX_EHRPWM0]             = 7,
+        [IRQ_DA8XX_EHRPWM0TZ]           = 7,
+        [IRQ_DA8XX_EHRPWM1]             = 7,
+        [IRQ_DA8XX_EHRPWM1TZ]           = 7,
+        [IRQ_DA850_SATAINT]             = 7,
+        [IRQ_DA850_TINT12_2]            = 7,
+        [IRQ_DA850_TINT34_2]            = 7,
+        [IRQ_DA850_TINTALL_2]           = 7,
+        [IRQ_DA8XX_ECAP0]               = 7,
+        [IRQ_DA8XX_ECAP1]               = 7,
+        [IRQ_DA8XX_ECAP2]               = 7,
+        [IRQ_DA850_MMCSDINT0_1]         = 7,
+        [IRQ_DA850_MMCSDINT1_1]         = 7,
+        [IRQ_DA850_T12CMPINT0_2]        = 7,
+        [IRQ_DA850_T12CMPINT1_2]        = 7,
+        [IRQ_DA850_T12CMPINT2_2]        = 7,
+        [IRQ_DA850_T12CMPINT3_2]        = 7,
+        [IRQ_DA850_T12CMPINT4_2]        = 7,
+        [IRQ_DA850_T12CMPINT5_2]        = 7,
+        [IRQ_DA850_T12CMPINT6_2]        = 7,
+        [IRQ_DA850_T12CMPINT7_2]        = 7,
+        [IRQ_DA850_T12CMPINT0_3]        = 7,
+        [IRQ_DA850_T12CMPINT1_3]        = 7,
+        [IRQ_DA850_T12CMPINT2_3]        = 7,
+        [IRQ_DA850_T12CMPINT3_3]        = 7,
+        [IRQ_DA850_T12CMPINT4_3]        = 7,
+        [IRQ_DA850_T12CMPINT5_3]        = 7,
+        [IRQ_DA850_T12CMPINT6_3]        = 7,
+        [IRQ_DA850_T12CMPINT7_3]        = 7,
+        [IRQ_DA850_RPIINT]              = 7,
+        [IRQ_DA850_VPIFINT]             = 7,
+        [IRQ_DA850_CCINT1]              = 7,
+        [IRQ_DA850_CCERRINT1]           = 7,
+        [IRQ_DA850_TCERRINT2]           = 7,
+        [IRQ_DA850_TINT12_3]            = 7,
+        [IRQ_DA850_TINT34_3]            = 7,
+        [IRQ_DA850_TINTALL_3]           = 7,
+        [IRQ_DA850_MCBSP0RINT]          = 7,
+        [IRQ_DA850_MCBSP0XINT]          = 7,
+        [IRQ_DA850_MCBSP1RINT]          = 7,
+        [IRQ_DA850_MCBSP1XINT]          = 7,
+        [IRQ_DA8XX_ARMCLKSTOPREQ]       = 7,
+};
+
+static struct map_desc da850_io_desc[] = {
+        {
+                .virtual        = IO_VIRT,
+                .pfn            = __phys_to_pfn(IO_PHYS),
+                .length         = IO_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = DA8XX_CP_INTC_VIRT,
+                .pfn            = __phys_to_pfn(DA8XX_CP_INTC_BASE),
+                .length         = DA8XX_CP_INTC_SIZE,
+                .type           = MT_DEVICE
+        },
+};
+
+static void __iomem *da850_psc_bases[] = {
+        IO_ADDRESS(DA8XX_PSC0_BASE),
+        IO_ADDRESS(DA8XX_PSC1_BASE),
+};
+
+/* Contents of JTAG ID register used to identify exact cpu type */
+static struct davinci_id da850_ids[] = {
+        {
+                .variant        = 0x0,
+                .part_no        = 0xb7d1,
+                .manufacturer   = 0x017,        /* 0x02f >> 1 */
+                .cpu_id         = DAVINCI_CPU_ID_DA850,
+                .name           = "da850/omap-l138",
+        },
+};
+
+static struct davinci_timer_instance da850_timer_instance[4] = {
+        {
+                .base           = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
+                .bottom_irq     = IRQ_DA8XX_TINT12_0,
+                .top_irq        = IRQ_DA8XX_TINT34_0,
+        },
+        {
+                .base           = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
+                .bottom_irq     = IRQ_DA8XX_TINT12_1,
+                .top_irq        = IRQ_DA8XX_TINT34_1,
+        },
+        {
+                .base           = IO_ADDRESS(DA850_TIMER64P2_BASE),
+                .bottom_irq     = IRQ_DA850_TINT12_2,
+                .top_irq        = IRQ_DA850_TINT34_2,
+        },
+        {
+                .base           = IO_ADDRESS(DA850_TIMER64P3_BASE),
+                .bottom_irq     = IRQ_DA850_TINT12_3,
+                .top_irq        = IRQ_DA850_TINT34_3,
+        },
+};
+
+/*
+ * T0_BOT: Timer 0, bottom              : Used for clock_event
+ * T0_TOP: Timer 0, top                 : Used for clocksource
+ * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
+ */
+static struct davinci_timer_info da850_timer_info = {
+        .timers         = da850_timer_instance,
+        .clockevent_id  = T0_BOT,
+        .clocksource_id = T0_TOP,
+};
+
+static struct davinci_soc_info davinci_soc_info_da850 = {
+        .io_desc                = da850_io_desc,
+        .io_desc_num            = ARRAY_SIZE(da850_io_desc),
+        .jtag_id_base           = IO_ADDRESS(DA8XX_JTAG_ID_REG),
+        .ids                    = da850_ids,
+        .ids_num                = ARRAY_SIZE(da850_ids),
+        .cpu_clks               = da850_clks,
+        .psc_bases              = da850_psc_bases,
+        .psc_bases_num          = ARRAY_SIZE(da850_psc_bases),
+        .pinmux_base            = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120),
+        .pinmux_pins            = da850_pins,
+        .pinmux_pins_num        = ARRAY_SIZE(da850_pins),
+        .intc_base              = (void __iomem *)DA8XX_CP_INTC_VIRT,
+        .intc_type              = DAVINCI_INTC_TYPE_CP_INTC,
+        .intc_irq_prios         = da850_default_priorities,
+        .intc_irq_num           = DA850_N_CP_INTC_IRQ,
+        .timer_info             = &da850_timer_info,
+        .gpio_base              = IO_ADDRESS(DA8XX_GPIO_BASE),
+        .gpio_num               = 144,
+        .gpio_irq               = IRQ_DA8XX_GPIO0,
+        .serial_dev             = &da8xx_serial_device,
+        .emac_pdata             = &da8xx_emac_pdata,
+};
+
+void __init da850_init(void)
+{
+        davinci_common_init(&davinci_soc_info_da850);
+}
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
new file mode 100644
index 000000000000..58ad5b66fd60
--- /dev/null
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -0,0 +1,450 @@
+/*
+ * DA8XX/OMAP L1XX platform device data
+ *
+ * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
+ * Derived from code that was:
+ *      Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/serial_8250.h>
+
+#include <mach/cputype.h>
+#include <mach/common.h>
+#include <mach/time.h>
+#include <mach/da8xx.h>
+#include <video/da8xx-fb.h>
+
+#include "clock.h"
+
+#define DA8XX_TPCC_BASE                 0x01c00000
+#define DA8XX_TPTC0_BASE                0x01c08000
+#define DA8XX_TPTC1_BASE                0x01c08400
+#define DA8XX_WDOG_BASE                 0x01c21000 /* DA8XX_TIMER64P1_BASE */
+#define DA8XX_I2C0_BASE                 0x01c22000
+#define DA8XX_EMAC_CPPI_PORT_BASE       0x01e20000
+#define DA8XX_EMAC_CPGMACSS_BASE        0x01e22000
+#define DA8XX_EMAC_CPGMAC_BASE          0x01e23000
+#define DA8XX_EMAC_MDIO_BASE            0x01e24000
+#define DA8XX_GPIO_BASE                 0x01e26000
+#define DA8XX_I2C1_BASE                 0x01e28000
+
+#define DA8XX_EMAC_CTRL_REG_OFFSET      0x3000
+#define DA8XX_EMAC_MOD_REG_OFFSET       0x2000
+#define DA8XX_EMAC_RAM_OFFSET           0x0000
+#define DA8XX_MDIO_REG_OFFSET           0x4000
+#define DA8XX_EMAC_CTRL_RAM_SIZE        SZ_8K
+
+static struct plat_serial8250_port da8xx_serial_pdata[] = {
+        {
+                .mapbase        = DA8XX_UART0_BASE,
+                .irq            = IRQ_DA8XX_UARTINT0,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                        UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .mapbase        = DA8XX_UART1_BASE,
+                .irq            = IRQ_DA8XX_UARTINT1,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                        UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .mapbase        = DA8XX_UART2_BASE,
+                .irq            = IRQ_DA8XX_UARTINT2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                        UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .flags  = 0,
+        },
+};
+
+struct platform_device da8xx_serial_device = {
+        .name   = "serial8250",
+        .id     = PLAT8250_DEV_PLATFORM,
+        .dev    = {
+                .platform_data  = da8xx_serial_pdata,
+        },
+};
+
+static const s8 da8xx_dma_chan_no_event[] = {
+        20, 21,
+        -1
+};
+
+static const s8 da8xx_queue_tc_mapping[][2] = {
+        /* {event queue no, TC no} */
+        {0, 0},
+        {1, 1},
+        {-1, -1}
+};
+
+static const s8 da8xx_queue_priority_mapping[][2] = {
+        /* {event queue no, Priority} */
+        {0, 3},
+        {1, 7},
+        {-1, -1}
+};
+
+static struct edma_soc_info da8xx_edma_info[] = {
+        {
+                .n_channel              = 32,
+                .n_region               = 4,
+                .n_slot                 = 128,
+                .n_tc                   = 2,
+                .n_cc                   = 1,
+                .noevent                = da8xx_dma_chan_no_event,
+                .queue_tc_mapping       = da8xx_queue_tc_mapping,
+                .queue_priority_mapping = da8xx_queue_priority_mapping,
+        },
+};
+
+static struct resource da8xx_edma_resources[] = {
+        {
+                .name   = "edma_cc0",
+                .start  = DA8XX_TPCC_BASE,
+                .end    = DA8XX_TPCC_BASE + SZ_32K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc0",
+                .start  = DA8XX_TPTC0_BASE,
+                .end    = DA8XX_TPTC0_BASE + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc1",
+                .start  = DA8XX_TPTC1_BASE,
+                .end    = DA8XX_TPTC1_BASE + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma0",
+                .start  = IRQ_DA8XX_CCINT0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .name   = "edma0_err",
+                .start  = IRQ_DA8XX_CCERRINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device da8xx_edma_device = {
+        .name           = "edma",
+        .id             = -1,
+        .dev = {
+                .platform_data  = da8xx_edma_info,
+        },
+        .num_resources  = ARRAY_SIZE(da8xx_edma_resources),
+        .resource       = da8xx_edma_resources,
+};
+
+int __init da8xx_register_edma(void)
+{
+        return platform_device_register(&da8xx_edma_device);
+}
+
+static struct resource da8xx_i2c_resources0[] = {
+        {
+                .start  = DA8XX_I2C0_BASE,
+                .end    = DA8XX_I2C0_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_DA8XX_I2CINT0,
+                .end    = IRQ_DA8XX_I2CINT0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device da8xx_i2c_device0 = {
+        .name           = "i2c_davinci",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(da8xx_i2c_resources0),
+        .resource       = da8xx_i2c_resources0,
+};
+
+static struct resource da8xx_i2c_resources1[] = {
+        {
+                .start  = DA8XX_I2C1_BASE,
+                .end    = DA8XX_I2C1_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_DA8XX_I2CINT1,
+                .end    = IRQ_DA8XX_I2CINT1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device da8xx_i2c_device1 = {
+        .name           = "i2c_davinci",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(da8xx_i2c_resources1),
+        .resource       = da8xx_i2c_resources1,
+};
+
+int __init da8xx_register_i2c(int instance,
+                struct davinci_i2c_platform_data *pdata)
+{
+        struct platform_device *pdev;
+
+        if (instance == 0)
+                pdev = &da8xx_i2c_device0;
+        else if (instance == 1)
+                pdev = &da8xx_i2c_device1;
+        else
+                return -EINVAL;
+
+        pdev->dev.platform_data = pdata;
+        return platform_device_register(pdev);
+}
+
+static struct resource da8xx_watchdog_resources[] = {
+        {
+                .start  = DA8XX_WDOG_BASE,
+                .end    = DA8XX_WDOG_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device davinci_wdt_device = {
+        .name           = "watchdog",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(da8xx_watchdog_resources),
+        .resource       = da8xx_watchdog_resources,
+};
+
+int __init da8xx_register_watchdog(void)
+{
+        return platform_device_register(&davinci_wdt_device);
+}
+
+static struct resource da8xx_emac_resources[] = {
+        {
+                .start  = DA8XX_EMAC_CPPI_PORT_BASE,
+                .end    = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_DA8XX_C0_RX_THRESH_PULSE,
+                .end    = IRQ_DA8XX_C0_RX_THRESH_PULSE,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_C0_RX_PULSE,
+                .end    = IRQ_DA8XX_C0_RX_PULSE,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_C0_TX_PULSE,
+                .end    = IRQ_DA8XX_C0_TX_PULSE,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_C0_MISC_PULSE,
+                .end    = IRQ_DA8XX_C0_MISC_PULSE,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct emac_platform_data da8xx_emac_pdata = {
+        .ctrl_reg_offset        = DA8XX_EMAC_CTRL_REG_OFFSET,
+        .ctrl_mod_reg_offset    = DA8XX_EMAC_MOD_REG_OFFSET,
+        .ctrl_ram_offset        = DA8XX_EMAC_RAM_OFFSET,
+        .mdio_reg_offset        = DA8XX_MDIO_REG_OFFSET,
+        .ctrl_ram_size          = DA8XX_EMAC_CTRL_RAM_SIZE,
+        .version                = EMAC_VERSION_2,
+};
+
+static struct platform_device da8xx_emac_device = {
+        .name           = "davinci_emac",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &da8xx_emac_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(da8xx_emac_resources),
+        .resource       = da8xx_emac_resources,
+};
+
+static struct resource da830_mcasp1_resources[] = {
+        {
+                .name   = "mcasp1",
+                .start  = DAVINCI_DA830_MCASP1_REG_BASE,
+                .end    = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /* TX event */
+        {
+                .start  = DAVINCI_DA830_DMA_MCASP1_AXEVT,
+                .end    = DAVINCI_DA830_DMA_MCASP1_AXEVT,
+                .flags  = IORESOURCE_DMA,
+        },
+        /* RX event */
+        {
+                .start  = DAVINCI_DA830_DMA_MCASP1_AREVT,
+                .end    = DAVINCI_DA830_DMA_MCASP1_AREVT,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device da830_mcasp1_device = {
+        .name           = "davinci-mcasp",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(da830_mcasp1_resources),
+        .resource       = da830_mcasp1_resources,
+};
+
+static struct resource da850_mcasp_resources[] = {
+        {
+                .name   = "mcasp",
+                .start  = DAVINCI_DA8XX_MCASP0_REG_BASE,
+                .end    = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /* TX event */
+        {
+                .start  = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
+                .end    = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
+                .flags  = IORESOURCE_DMA,
+        },
+        /* RX event */
+        {
+                .start  = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
+                .end    = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device da850_mcasp_device = {
+        .name           = "davinci-mcasp",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(da850_mcasp_resources),
+        .resource       = da850_mcasp_resources,
+};
+
+int __init da8xx_register_emac(void)
+{
+        return platform_device_register(&da8xx_emac_device);
+}
+
+void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata)
+{
+        /* DA830/OMAP-L137 has 3 instances of McASP */
+        if (cpu_is_davinci_da830() && id == 1) {
+                da830_mcasp1_device.dev.platform_data = pdata;
+                platform_device_register(&da830_mcasp1_device);
+        } else if (cpu_is_davinci_da850()) {
+                da850_mcasp_device.dev.platform_data = pdata;
+                platform_device_register(&da850_mcasp_device);
+        }
+}
+
+static const struct display_panel disp_panel = {
+        QVGA,
+        16,
+        16,
+        COLOR_ACTIVE,
+};
+
+static struct lcd_ctrl_config lcd_cfg = {
+        &disp_panel,
+        .ac_bias                = 255,
+        .ac_bias_intrpt         = 0,
+        .dma_burst_sz           = 16,
+        .bpp                    = 16,
+        .fdd                    = 255,
+        .tft_alt_mode           = 0,
+        .stn_565_mode           = 0,
+        .mono_8bit_mode         = 0,
+        .invert_line_clock      = 1,
+        .invert_frm_clock       = 1,
+        .sync_edge              = 0,
+        .sync_ctrl              = 1,
+        .raster_order           = 0,
+};
+
+static struct da8xx_lcdc_platform_data da850_evm_lcdc_pdata = {
+        .manu_name = "sharp",
+        .controller_data = &lcd_cfg,
+        .type = "Sharp_LK043T1DG01",
+};
+
+static struct resource da8xx_lcdc_resources[] = {
+        [0] = { /* registers */
+                .start  = DA8XX_LCD_CNTRL_BASE,
+                .end    = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = { /* interrupt */
+                .start  = IRQ_DA8XX_LCDINT,
+                .end    = IRQ_DA8XX_LCDINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device da850_lcdc_device = {
+        .name           = "da8xx_lcdc",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(da8xx_lcdc_resources),
+        .resource       = da8xx_lcdc_resources,
+        .dev = {
+                .platform_data = &da850_evm_lcdc_pdata,
+        }
+};
+
+int __init da8xx_register_lcdc(void)
+{
+        return platform_device_register(&da850_lcdc_device);
+}
+
+static struct resource da8xx_mmcsd0_resources[] = {
+        {               /* registers */
+                .start  = DA8XX_MMCSD0_BASE,
+                .end    = DA8XX_MMCSD0_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {               /* interrupt */
+                .start  = IRQ_DA8XX_MMCSDINT0,
+                .end    = IRQ_DA8XX_MMCSDINT0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {               /* DMA RX */
+                .start  = EDMA_CTLR_CHAN(0, 16),
+                .end    = EDMA_CTLR_CHAN(0, 16),
+                .flags  = IORESOURCE_DMA,
+        },
+        {               /* DMA TX */
+                .start  = EDMA_CTLR_CHAN(0, 17),
+                .end    = EDMA_CTLR_CHAN(0, 17),
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device da8xx_mmcsd0_device = {
+        .name           = "davinci_mmc",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(da8xx_mmcsd0_resources),
+        .resource       = da8xx_mmcsd0_resources,
+};
+
+int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
+{
+        da8xx_mmcsd0_device.dev.platform_data = config;
+        return platform_device_register(&da8xx_mmcsd0_device);
+}
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index de16f347566a..a55b650db71e 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -31,6 +31,8 @@
 #define DAVINCI_MMCSD0_BASE          0x01E10000
 #define DM355_MMCSD0_BASE            0x01E11000
 #define DM355_MMCSD1_BASE            0x01E00000
+#define DM365_MMCSD0_BASE            0x01D11000
+#define DM365_MMCSD1_BASE            0x01D00000
 
 static struct resource i2c_resources[] = {
         {
@@ -82,10 +84,10 @@ static struct resource mmcsd0_resources[] = {
         },
         /* DMA channels: RX, then TX */
         {
-                .start = DAVINCI_DMA_MMCRXEVT,
+                .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCRXEVT),
                 .flags = IORESOURCE_DMA,
         }, {
-                .start = DAVINCI_DMA_MMCTXEVT,
+                .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCTXEVT),
                 .flags = IORESOURCE_DMA,
         },
 };
@@ -119,10 +121,10 @@ static struct resource mmcsd1_resources[] = {
         },
         /* DMA channels: RX, then TX */
         {
-                .start = 30,    /* rx */
+                .start = EDMA_CTLR_CHAN(0, 30), /* rx */
                 .flags = IORESOURCE_DMA,
         }, {
-                .start = 31,    /* tx */
+                .start = EDMA_CTLR_CHAN(0, 31), /* tx */
                 .flags = IORESOURCE_DMA,
         },
 };
@@ -154,19 +156,31 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
          */
         switch (module) {
         case 1:
-                if (!cpu_is_davinci_dm355())
+                if (cpu_is_davinci_dm355()) {
+                        /* REVISIT we may not need all these pins if e.g. this
+                         * is a hard-wired SDIO device...
+                         */
+                        davinci_cfg_reg(DM355_SD1_CMD);
+                        davinci_cfg_reg(DM355_SD1_CLK);
+                        davinci_cfg_reg(DM355_SD1_DATA0);
+                        davinci_cfg_reg(DM355_SD1_DATA1);
+                        davinci_cfg_reg(DM355_SD1_DATA2);
+                        davinci_cfg_reg(DM355_SD1_DATA3);
+                } else if (cpu_is_davinci_dm365()) {
+                        void __iomem *pupdctl1 =
+                                IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c);
+
+                        /* Configure pull down control */
+                        __raw_writel((__raw_readl(pupdctl1) & ~0x400),
+                                        pupdctl1);
+
+                        mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
+                        mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
+                                                        SZ_4K - 1;
+                        mmcsd0_resources[2].start = IRQ_DM365_SDIOINT1;
+                } else
                         break;
 
-                /* REVISIT we may not need all these pins if e.g. this
-                 * is a hard-wired SDIO device...
-                 */
-                davinci_cfg_reg(DM355_SD1_CMD);
-                davinci_cfg_reg(DM355_SD1_CLK);
-                davinci_cfg_reg(DM355_SD1_DATA0);
-                davinci_cfg_reg(DM355_SD1_DATA1);
-                davinci_cfg_reg(DM355_SD1_DATA2);
-                davinci_cfg_reg(DM355_SD1_DATA3);
-
                 pdev = &davinci_mmcsd1_device;
                 break;
         case 0:
@@ -180,9 +194,12 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
 
                         /* enable RX EDMA */
                         davinci_cfg_reg(DM355_EVT26_MMC0_RX);
-                }
-
-                else if (cpu_is_davinci_dm644x()) {
+                } else if (cpu_is_davinci_dm365()) {
+                        mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
+                        mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
+                                                        SZ_4K - 1;
+                        mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
+                } else if (cpu_is_davinci_dm644x()) {
                         /* REVISIT: should this be in board-init code? */
                         void __iomem *base =
                                 IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
@@ -216,6 +233,8 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
 
 static struct resource wdt_resources[] = {
         {
+                .start  = DAVINCI_WDOG_BASE,
+                .end    = DAVINCI_WDOG_BASE + SZ_1K - 1,
                 .flags  = IORESOURCE_MEM,
         },
 };
@@ -229,11 +248,6 @@ struct platform_device davinci_wdt_device = {
 
 static void davinci_init_wdt(void)
 {
-        struct davinci_soc_info *soc_info = &davinci_soc_info;
-
-        wdt_resources[0].start = (resource_size_t)soc_info->wdt_base;
-        wdt_resources[0].end = (resource_size_t)soc_info->wdt_base + SZ_1K - 1;
-
         platform_device_register(&davinci_wdt_device);
 }
 
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index baaaf328de2e..059670018aff 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -30,6 +30,7 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
+#include <mach/asp.h>
 
 #include "clock.h"
 #include "mux.h"
@@ -360,8 +361,8 @@ static struct davinci_clk dm355_clks[] = {
         CLK(NULL, "uart1", &uart1_clk),
         CLK(NULL, "uart2", &uart2_clk),
         CLK("i2c_davinci.1", NULL, &i2c_clk),
-        CLK("soc-audio.0", NULL, &asp0_clk),
-        CLK("soc-audio.1", NULL, &asp1_clk),
+        CLK("davinci-asp.0", NULL, &asp0_clk),
+        CLK("davinci-asp.1", NULL, &asp1_clk),
         CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
         CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
         CLK(NULL, "spi0", &spi0_clk),
@@ -481,6 +482,20 @@ INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
 EVT_CFG(DM355,  EVT8_ASP1_TX,         0,    1,    0,     false)
 EVT_CFG(DM355,  EVT9_ASP1_RX,         1,    1,    0,     false)
 EVT_CFG(DM355,  EVT26_MMC0_RX,        2,    1,    0,     false)
+
+MUX_CFG(DM355,  VOUT_FIELD,     1,   18,    3,    1,     false)
+MUX_CFG(DM355,  VOUT_FIELD_G70, 1,   18,    3,    0,     false)
+MUX_CFG(DM355,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
+MUX_CFG(DM355,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
+MUX_CFG(DM355,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
+
+MUX_CFG(DM355,  VIN_PCLK,       0,   14,    1,    1,     false)
+MUX_CFG(DM355,  VIN_CAM_WEN,    0,   13,    1,    1,     false)
+MUX_CFG(DM355,  VIN_CAM_VD,     0,   12,    1,    1,     false)
+MUX_CFG(DM355,  VIN_CAM_HD,     0,   11,    1,    1,     false)
+MUX_CFG(DM355,  VIN_YIN_EN,     0,   10,    1,    1,     false)
+MUX_CFG(DM355,  VIN_CINL_EN,    0,   0,   0xff, 0x55,    false)
+MUX_CFG(DM355,  VIN_CINH_EN,    0,   8,     3,    3,     false)
 #endif
 };
 
@@ -558,17 +573,38 @@ static const s8 dma_chan_dm355_no_event[] = {
         -1
 };
 
-static struct edma_soc_info dm355_edma_info = {
-        .n_channel      = 64,
-        .n_region       = 4,
-        .n_slot         = 128,
-        .n_tc           = 2,
-        .noevent        = dma_chan_dm355_no_event,
+static const s8
+queue_tc_mapping[][2] = {
+        /* {event queue no, TC no} */
+        {0, 0},
+        {1, 1},
+        {-1, -1},
+};
+
+static const s8
+queue_priority_mapping[][2] = {
+        /* {event queue no, Priority} */
+        {0, 3},
+        {1, 7},
+        {-1, -1},
+};
+
+static struct edma_soc_info dm355_edma_info[] = {
+        {
+                .n_channel              = 64,
+                .n_region               = 4,
+                .n_slot                 = 128,
+                .n_tc                   = 2,
+                .n_cc                   = 1,
+                .noevent                = dma_chan_dm355_no_event,
+                .queue_tc_mapping       = queue_tc_mapping,
+                .queue_priority_mapping = queue_priority_mapping,
+        },
 };
 
 static struct resource edma_resources[] = {
         {
-                .name   = "edma_cc",
+                .name   = "edma_cc0",
                 .start  = 0x01c00000,
                 .end    = 0x01c00000 + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
@@ -586,10 +622,12 @@ static struct resource edma_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
+                .name   = "edma0",
                 .start  = IRQ_CCINT0,
                 .flags  = IORESOURCE_IRQ,
         },
         {
+                .name   = "edma0_err",
                 .start  = IRQ_CCERRINT,
                 .flags  = IORESOURCE_IRQ,
         },
@@ -598,12 +636,98 @@ static struct resource edma_resources[] = {
 
 static struct platform_device dm355_edma_device = {
         .name                   = "edma",
-        .id                     = -1,
-        .dev.platform_data      = &dm355_edma_info,
+        .id                     = 0,
+        .dev.platform_data      = dm355_edma_info,
         .num_resources          = ARRAY_SIZE(edma_resources),
         .resource               = edma_resources,
 };
 
+static struct resource dm355_asp1_resources[] = {
+        {
+                .start  = DAVINCI_ASP1_BASE,
+                .end    = DAVINCI_ASP1_BASE + SZ_8K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = DAVINCI_DMA_ASP1_TX,
+                .end    = DAVINCI_DMA_ASP1_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        {
+                .start  = DAVINCI_DMA_ASP1_RX,
+                .end    = DAVINCI_DMA_ASP1_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device dm355_asp1_device = {
+        .name           = "davinci-asp",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(dm355_asp1_resources),
+        .resource       = dm355_asp1_resources,
+};
+
+static struct resource dm355_vpss_resources[] = {
+        {
+                /* VPSS BL Base address */
+                .name           = "vpss",
+                .start          = 0x01c70800,
+                .end            = 0x01c70800 + 0xff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                /* VPSS CLK Base address */
+                .name           = "vpss",
+                .start          = 0x01c70000,
+                .end            = 0x01c70000 + 0xf,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device dm355_vpss_device = {
+        .name                   = "vpss",
+        .id                     = -1,
+        .dev.platform_data      = "dm355_vpss",
+        .num_resources          = ARRAY_SIZE(dm355_vpss_resources),
+        .resource               = dm355_vpss_resources,
+};
+
+static struct resource vpfe_resources[] = {
+        {
+                .start          = IRQ_VDINT0,
+                .end            = IRQ_VDINT0,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = IRQ_VDINT1,
+                .end            = IRQ_VDINT1,
+                .flags          = IORESOURCE_IRQ,
+        },
+        /* CCDC Base address */
+        {
+                .flags          = IORESOURCE_MEM,
+                .start          = 0x01c70600,
+                .end            = 0x01c70600 + 0x1ff,
+        },
+};
+
+static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
+static struct platform_device vpfe_capture_dev = {
+        .name           = CAPTURE_DRV_NAME,
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(vpfe_resources),
+        .resource       = vpfe_resources,
+        .dev = {
+                .dma_mask               = &vpfe_capture_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void dm355_set_vpfe_config(struct vpfe_config *cfg)
+{
+        vpfe_capture_dev.dev.platform_data = cfg;
+}
+
 /*----------------------------------------------------------------------*/
 
 static struct map_desc dm355_io_desc[] = {
@@ -704,7 +828,6 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
         .intc_irq_prios         = dm355_default_priorities,
         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
         .timer_info             = &dm355_timer_info,
-        .wdt_base               = IO_ADDRESS(DAVINCI_WDOG_BASE),
         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
         .gpio_num               = 104,
         .gpio_irq               = IRQ_DM355_GPIOBNK0,
@@ -713,6 +836,19 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
         .sram_len               = SZ_32K,
 };
 
+void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
+{
+        /* we don't use ASP1 IRQs, or we'd need to mux them ... */
+        if (evt_enable & ASP1_TX_EVT_EN)
+                davinci_cfg_reg(DM355_EVT8_ASP1_TX);
+
+        if (evt_enable & ASP1_RX_EVT_EN)
+                davinci_cfg_reg(DM355_EVT9_ASP1_RX);
+
+        dm355_asp1_device.dev.platform_data = pdata;
+        platform_device_register(&dm355_asp1_device);
+}
+
 void __init dm355_init(void)
 {
         davinci_common_init(&davinci_soc_info_dm355);
@@ -725,6 +861,20 @@ static int __init dm355_init_devices(void)
 
         davinci_cfg_reg(DM355_INT_EDMA_CC);
         platform_device_register(&dm355_edma_device);
+        platform_device_register(&dm355_vpss_device);
+        /*
+         * setup Mux configuration for vpfe input and register
+         * vpfe capture platform device
+         */
+        davinci_cfg_reg(DM355_VIN_PCLK);
+        davinci_cfg_reg(DM355_VIN_CAM_WEN);
+        davinci_cfg_reg(DM355_VIN_CAM_VD);
+        davinci_cfg_reg(DM355_VIN_CAM_HD);
+        davinci_cfg_reg(DM355_VIN_YIN_EN);
+        davinci_cfg_reg(DM355_VIN_CINL_EN);
+        davinci_cfg_reg(DM355_VIN_CINH_EN);
+        platform_device_register(&vpfe_capture_dev);
+
         return 0;
 }
 postcore_initcall(dm355_init_devices);
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
new file mode 100644
index 000000000000..e81517434703
--- /dev/null
+++ b/arch/arm/mach-davinci/dm365.c
@@ -0,0 +1,926 @@
+/*
+ * TI DaVinci DM365 chip specific setup
+ *
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/dm365.h>
+#include <mach/clock.h>
+#include <mach/cputype.h>
+#include <mach/edma.h>
+#include <mach/psc.h>
+#include <mach/mux.h>
+#include <mach/irqs.h>
+#include <mach/time.h>
+#include <mach/serial.h>
+#include <mach/common.h>
+
+#include "clock.h"
+#include "mux.h"
+
+#define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
+
+static struct pll_data pll1_data = {
+        .num            = 1,
+        .phys_base      = DAVINCI_PLL1_BASE,
+        .flags          = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
+};
+
+static struct pll_data pll2_data = {
+        .num            = 2,
+        .phys_base      = DAVINCI_PLL2_BASE,
+        .flags          = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
+};
+
+static struct clk ref_clk = {
+        .name           = "ref_clk",
+        .rate           = DM365_REF_FREQ,
+};
+
+static struct clk pll1_clk = {
+        .name           = "pll1",
+        .parent         = &ref_clk,
+        .flags          = CLK_PLL,
+        .pll_data       = &pll1_data,
+};
+
+static struct clk pll1_aux_clk = {
+        .name           = "pll1_aux_clk",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL | PRE_PLL,
+};
+
+static struct clk pll1_sysclkbp = {
+        .name           = "pll1_sysclkbp",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL | PRE_PLL,
+        .div_reg        = BPDIV
+};
+
+static struct clk clkout0_clk = {
+        .name           = "clkout0",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL | PRE_PLL,
+};
+
+static struct clk pll1_sysclk1 = {
+        .name           = "pll1_sysclk1",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV1,
+};
+
+static struct clk pll1_sysclk2 = {
+        .name           = "pll1_sysclk2",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV2,
+};
+
+static struct clk pll1_sysclk3 = {
+        .name           = "pll1_sysclk3",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV3,
+};
+
+static struct clk pll1_sysclk4 = {
+        .name           = "pll1_sysclk4",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV4,
+};
+
+static struct clk pll1_sysclk5 = {
+        .name           = "pll1_sysclk5",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV5,
+};
+
+static struct clk pll1_sysclk6 = {
+        .name           = "pll1_sysclk6",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV6,
+};
+
+static struct clk pll1_sysclk7 = {
+        .name           = "pll1_sysclk7",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV7,
+};
+
+static struct clk pll1_sysclk8 = {
+        .name           = "pll1_sysclk8",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV8,
+};
+
+static struct clk pll1_sysclk9 = {
+        .name           = "pll1_sysclk9",
+        .parent         = &pll1_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV9,
+};
+
+static struct clk pll2_clk = {
+        .name           = "pll2",
+        .parent         = &ref_clk,
+        .flags          = CLK_PLL,
+        .pll_data       = &pll2_data,
+};
+
+static struct clk pll2_aux_clk = {
+        .name           = "pll2_aux_clk",
+        .parent         = &pll2_clk,
+        .flags          = CLK_PLL | PRE_PLL,
+};
+
+static struct clk clkout1_clk = {
+        .name           = "clkout1",
+        .parent         = &pll2_clk,
+        .flags          = CLK_PLL | PRE_PLL,
+};
+
+static struct clk pll2_sysclk1 = {
+        .name           = "pll2_sysclk1",
+        .parent         = &pll2_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV1,
+};
+
+static struct clk pll2_sysclk2 = {
+        .name           = "pll2_sysclk2",
+        .parent         = &pll2_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV2,
+};
+
+static struct clk pll2_sysclk3 = {
+        .name           = "pll2_sysclk3",
+        .parent         = &pll2_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV3,
+};
+
+static struct clk pll2_sysclk4 = {
+        .name           = "pll2_sysclk4",
+        .parent         = &pll2_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV4,
+};
+
+static struct clk pll2_sysclk5 = {
+        .name           = "pll2_sysclk5",
+        .parent         = &pll2_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV5,
+};
+
+static struct clk pll2_sysclk6 = {
+        .name           = "pll2_sysclk6",
+        .parent         = &pll2_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV6,
+};
+
+static struct clk pll2_sysclk7 = {
+        .name           = "pll2_sysclk7",
+        .parent         = &pll2_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV7,
+};
+
+static struct clk pll2_sysclk8 = {
+        .name           = "pll2_sysclk8",
+        .parent         = &pll2_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV8,
+};
+
+static struct clk pll2_sysclk9 = {
+        .name           = "pll2_sysclk9",
+        .parent         = &pll2_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV9,
+};
+
+static struct clk vpss_dac_clk = {
+        .name           = "vpss_dac",
+        .parent         = &pll1_sysclk3,
+        .lpsc           = DM365_LPSC_DAC_CLK,
+};
+
+static struct clk vpss_master_clk = {
+        .name           = "vpss_master",
+        .parent         = &pll1_sysclk5,
+        .lpsc           = DM365_LPSC_VPSSMSTR,
+        .flags          = CLK_PSC,
+};
+
+static struct clk arm_clk = {
+        .name           = "arm_clk",
+        .parent         = &pll2_sysclk2,
+        .lpsc           = DAVINCI_LPSC_ARM,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk uart0_clk = {
+        .name           = "uart0",
+        .parent         = &pll1_aux_clk,
+        .lpsc           = DAVINCI_LPSC_UART0,
+};
+
+static struct clk uart1_clk = {
+        .name           = "uart1",
+        .parent         = &pll1_sysclk4,
+        .lpsc           = DAVINCI_LPSC_UART1,
+};
+
+static struct clk i2c_clk = {
+        .name           = "i2c",
+        .parent         = &pll1_aux_clk,
+        .lpsc           = DAVINCI_LPSC_I2C,
+};
+
+static struct clk mmcsd0_clk = {
+        .name           = "mmcsd0",
+        .parent         = &pll1_sysclk8,
+        .lpsc           = DAVINCI_LPSC_MMC_SD,
+};
+
+static struct clk mmcsd1_clk = {
+        .name           = "mmcsd1",
+        .parent         = &pll1_sysclk4,
+        .lpsc           = DM365_LPSC_MMC_SD1,
+};
+
+static struct clk spi0_clk = {
+        .name           = "spi0",
+        .parent         = &pll1_sysclk4,
+        .lpsc           = DAVINCI_LPSC_SPI,
+};
+
+static struct clk spi1_clk = {
+        .name           = "spi1",
+        .parent         = &pll1_sysclk4,
+        .lpsc           = DM365_LPSC_SPI1,
+};
+
+static struct clk spi2_clk = {
+        .name           = "spi2",
+        .parent         = &pll1_sysclk4,
+        .lpsc           = DM365_LPSC_SPI2,
+};
+
+static struct clk spi3_clk = {
+        .name           = "spi3",
+        .parent         = &pll1_sysclk4,
+        .lpsc           = DM365_LPSC_SPI3,
+};
+
+static struct clk spi4_clk = {
+        .name           = "spi4",
+        .parent         = &pll1_aux_clk,
+        .lpsc           = DM365_LPSC_SPI4,
+};
+
+static struct clk gpio_clk = {
+        .name           = "gpio",
+        .parent         = &pll1_sysclk4,
+        .lpsc           = DAVINCI_LPSC_GPIO,
+};
+
+static struct clk aemif_clk = {
+        .name           = "aemif",
+        .parent         = &pll1_sysclk4,
+        .lpsc           = DAVINCI_LPSC_AEMIF,
+};
+
+static struct clk pwm0_clk = {
+        .name           = "pwm0",
+        .parent         = &pll1_aux_clk,
+        .lpsc           = DAVINCI_LPSC_PWM0,
+};
+
+static struct clk pwm1_clk = {
+        .name           = "pwm1",
+        .parent         = &pll1_aux_clk,
+        .lpsc           = DAVINCI_LPSC_PWM1,
+};
+
+static struct clk pwm2_clk = {
+        .name           = "pwm2",
+        .parent         = &pll1_aux_clk,
+        .lpsc           = DAVINCI_LPSC_PWM2,
+};
+
+static struct clk pwm3_clk = {
+        .name           = "pwm3",
+        .parent         = &ref_clk,
+        .lpsc           = DM365_LPSC_PWM3,
+};
+
+static struct clk timer0_clk = {
+        .name           = "timer0",
+        .parent         = &pll1_aux_clk,
+        .lpsc           = DAVINCI_LPSC_TIMER0,
+};
+
+static struct clk timer1_clk = {
+        .name           = "timer1",
+        .parent         = &pll1_aux_clk,
+        .lpsc           = DAVINCI_LPSC_TIMER1,
+};
+
+static struct clk timer2_clk = {
+        .name           = "timer2",
+        .parent         = &pll1_aux_clk,
+        .lpsc           = DAVINCI_LPSC_TIMER2,
+        .usecount       = 1,
+};
+
+static struct clk timer3_clk = {
+        .name           = "timer3",
+        .parent         = &pll1_aux_clk,
+        .lpsc           = DM365_LPSC_TIMER3,
+};
+
+static struct clk usb_clk = {
+        .name           = "usb",
+        .parent         = &pll2_sysclk1,
+        .lpsc           = DAVINCI_LPSC_USB,
+};
+
+static struct clk emac_clk = {
+        .name           = "emac",
+        .parent         = &pll1_sysclk4,
+        .lpsc           = DM365_LPSC_EMAC,
+};
+
+static struct clk voicecodec_clk = {
+        .name           = "voice_codec",
+        .parent         = &pll2_sysclk4,
+        .lpsc           = DM365_LPSC_VOICE_CODEC,
+};
+
+static struct clk asp0_clk = {
+        .name           = "asp0",
+        .parent         = &pll1_sysclk4,
+        .lpsc           = DM365_LPSC_McBSP1,
+};
+
+static struct clk rto_clk = {
+        .name           = "rto",
+        .parent         = &pll1_sysclk4,
+        .lpsc           = DM365_LPSC_RTO,
+};
+
+static struct clk mjcp_clk = {
+        .name           = "mjcp",
+        .parent         = &pll1_sysclk3,
+        .lpsc           = DM365_LPSC_MJCP,
+};
+
+static struct davinci_clk dm365_clks[] = {
+        CLK(NULL, "ref", &ref_clk),
+        CLK(NULL, "pll1", &pll1_clk),
+        CLK(NULL, "pll1_aux", &pll1_aux_clk),
+        CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
+        CLK(NULL, "clkout0", &clkout0_clk),
+        CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
+        CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
+        CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
+        CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
+        CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
+        CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
+        CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
+        CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
+        CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
+        CLK(NULL, "pll2", &pll2_clk),
+        CLK(NULL, "pll2_aux", &pll2_aux_clk),
+        CLK(NULL, "clkout1", &clkout1_clk),
+        CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
+        CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
+        CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
+        CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
+        CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
+        CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
+        CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
+        CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
+        CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
+        CLK(NULL, "vpss_dac", &vpss_dac_clk),
+        CLK(NULL, "vpss_master", &vpss_master_clk),
+        CLK(NULL, "arm", &arm_clk),
+        CLK(NULL, "uart0", &uart0_clk),
+        CLK(NULL, "uart1", &uart1_clk),
+        CLK("i2c_davinci.1", NULL, &i2c_clk),
+        CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
+        CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
+        CLK("spi_davinci.0", NULL, &spi0_clk),
+        CLK("spi_davinci.1", NULL, &spi1_clk),
+        CLK("spi_davinci.2", NULL, &spi2_clk),
+        CLK("spi_davinci.3", NULL, &spi3_clk),
+        CLK("spi_davinci.4", NULL, &spi4_clk),
+        CLK(NULL, "gpio", &gpio_clk),
+        CLK(NULL, "aemif", &aemif_clk),
+        CLK(NULL, "pwm0", &pwm0_clk),
+        CLK(NULL, "pwm1", &pwm1_clk),
+        CLK(NULL, "pwm2", &pwm2_clk),
+        CLK(NULL, "pwm3", &pwm3_clk),
+        CLK(NULL, "timer0", &timer0_clk),
+        CLK(NULL, "timer1", &timer1_clk),
+        CLK("watchdog", NULL, &timer2_clk),
+        CLK(NULL, "timer3", &timer3_clk),
+        CLK(NULL, "usb", &usb_clk),
+        CLK("davinci_emac.1", NULL, &emac_clk),
+        CLK("voice_codec", NULL, &voicecodec_clk),
+        CLK("soc-audio.0", NULL, &asp0_clk),
+        CLK(NULL, "rto", &rto_clk),
+        CLK(NULL, "mjcp", &mjcp_clk),
+        CLK(NULL, NULL, NULL),
+};
+
+/*----------------------------------------------------------------------*/
+
+#define PINMUX0         0x00
+#define PINMUX1         0x04
+#define PINMUX2         0x08
+#define PINMUX3         0x0c
+#define PINMUX4         0x10
+#define INTMUX          0x18
+#define EVTMUX          0x1c
+
+
+static const struct mux_config dm365_pins[] = {
+#ifdef CONFIG_DAVINCI_MUX
+MUX_CFG(DM365,  MMCSD0,         0,   24,     1,   0,     false)
+
+MUX_CFG(DM365,  SD1_CLK,        0,   16,    3,    1,     false)
+MUX_CFG(DM365,  SD1_CMD,        4,   30,    3,    1,     false)
+MUX_CFG(DM365,  SD1_DATA3,      4,   28,    3,    1,     false)
+MUX_CFG(DM365,  SD1_DATA2,      4,   26,    3,    1,     false)
+MUX_CFG(DM365,  SD1_DATA1,      4,   24,    3,    1,     false)
+MUX_CFG(DM365,  SD1_DATA0,      4,   22,    3,    1,     false)
+
+MUX_CFG(DM365,  I2C_SDA,        3,   23,    3,    2,     false)
+MUX_CFG(DM365,  I2C_SCL,        3,   21,    3,    2,     false)
+
+MUX_CFG(DM365,  AEMIF_AR,       2,   0,     3,    1,     false)
+MUX_CFG(DM365,  AEMIF_A3,       2,   2,     3,    1,     false)
+MUX_CFG(DM365,  AEMIF_A7,       2,   4,     3,    1,     false)
+MUX_CFG(DM365,  AEMIF_D15_8,    2,   6,     1,    1,     false)
+MUX_CFG(DM365,  AEMIF_CE0,      2,   7,     1,    0,     false)
+
+MUX_CFG(DM365,  MCBSP0_BDX,     0,   23,    1,    1,     false)
+MUX_CFG(DM365,  MCBSP0_X,       0,   22,    1,    1,     false)
+MUX_CFG(DM365,  MCBSP0_BFSX,    0,   21,    1,    1,     false)
+MUX_CFG(DM365,  MCBSP0_BDR,     0,   20,    1,    1,     false)
+MUX_CFG(DM365,  MCBSP0_R,       0,   19,    1,    1,     false)
+MUX_CFG(DM365,  MCBSP0_BFSR,    0,   18,    1,    1,     false)
+
+MUX_CFG(DM365,  SPI0_SCLK,      3,   28,    1,    1,     false)
+MUX_CFG(DM365,  SPI0_SDI,       3,   26,    3,    1,     false)
+MUX_CFG(DM365,  SPI0_SDO,       3,   25,    1,    1,     false)
+MUX_CFG(DM365,  SPI0_SDENA0,    3,   29,    3,    1,     false)
+MUX_CFG(DM365,  SPI0_SDENA1,    3,   26,    3,    2,     false)
+
+MUX_CFG(DM365,  UART0_RXD,      3,   20,    1,    1,     false)
+MUX_CFG(DM365,  UART0_TXD,      3,   19,    1,    1,     false)
+MUX_CFG(DM365,  UART1_RXD,      3,   17,    3,    2,     false)
+MUX_CFG(DM365,  UART1_TXD,      3,   15,    3,    2,     false)
+MUX_CFG(DM365,  UART1_RTS,      3,   23,    3,    1,     false)
+MUX_CFG(DM365,  UART1_CTS,      3,   21,    3,    1,     false)
+
+MUX_CFG(DM365,  EMAC_TX_EN,     3,   17,    3,    1,     false)
+MUX_CFG(DM365,  EMAC_TX_CLK,    3,   15,    3,    1,     false)
+MUX_CFG(DM365,  EMAC_COL,       3,   14,    1,    1,     false)
+MUX_CFG(DM365,  EMAC_TXD3,      3,   13,    1,    1,     false)
+MUX_CFG(DM365,  EMAC_TXD2,      3,   12,    1,    1,     false)
+MUX_CFG(DM365,  EMAC_TXD1,      3,   11,    1,    1,     false)
+MUX_CFG(DM365,  EMAC_TXD0,      3,   10,    1,    1,     false)
+MUX_CFG(DM365,  EMAC_RXD3,      3,   9,     1,    1,     false)
+MUX_CFG(DM365,  EMAC_RXD2,      3,   8,     1,    1,     false)
+MUX_CFG(DM365,  EMAC_RXD1,      3,   7,     1,    1,     false)
+MUX_CFG(DM365,  EMAC_RXD0,      3,   6,     1,    1,     false)
+MUX_CFG(DM365,  EMAC_RX_CLK,    3,   5,     1,    1,     false)
+MUX_CFG(DM365,  EMAC_RX_DV,     3,   4,     1,    1,     false)
+MUX_CFG(DM365,  EMAC_RX_ER,     3,   3,     1,    1,     false)
+MUX_CFG(DM365,  EMAC_CRS,       3,   2,     1,    1,     false)
+MUX_CFG(DM365,  EMAC_MDIO,      3,   1,     1,    1,     false)
+MUX_CFG(DM365,  EMAC_MDCLK,     3,   0,     1,    1,     false)
+
+MUX_CFG(DM365,  KEYPAD,         2,   0,     0x3f, 0x3f,  false)
+
+MUX_CFG(DM365,  PWM0,           1,   0,     3,    2,     false)
+MUX_CFG(DM365,  PWM0_G23,       3,   26,    3,    3,     false)
+MUX_CFG(DM365,  PWM1,           1,   2,     3,    2,     false)
+MUX_CFG(DM365,  PWM1_G25,       3,   29,    3,    2,     false)
+MUX_CFG(DM365,  PWM2_G87,       1,   10,    3,    2,     false)
+MUX_CFG(DM365,  PWM2_G88,       1,   8,     3,    2,     false)
+MUX_CFG(DM365,  PWM2_G89,       1,   6,     3,    2,     false)
+MUX_CFG(DM365,  PWM2_G90,       1,   4,     3,    2,     false)
+MUX_CFG(DM365,  PWM3_G80,       1,   20,    3,    3,     false)
+MUX_CFG(DM365,  PWM3_G81,       1,   18,    3,    3,     false)
+MUX_CFG(DM365,  PWM3_G85,       1,   14,    3,    2,     false)
+MUX_CFG(DM365,  PWM3_G86,       1,   12,    3,    2,     false)
+
+MUX_CFG(DM365,  SPI1_SCLK,      4,   2,     3,    1,     false)
+MUX_CFG(DM365,  SPI1_SDI,       3,   31,    1,    1,     false)
+MUX_CFG(DM365,  SPI1_SDO,       4,   0,     3,    1,     false)
+MUX_CFG(DM365,  SPI1_SDENA0,    4,   4,     3,    1,     false)
+MUX_CFG(DM365,  SPI1_SDENA1,    4,   0,     3,    2,     false)
+
+MUX_CFG(DM365,  SPI2_SCLK,      4,   10,    3,    1,     false)
+MUX_CFG(DM365,  SPI2_SDI,       4,   6,     3,    1,     false)
+MUX_CFG(DM365,  SPI2_SDO,       4,   8,     3,    1,     false)
+MUX_CFG(DM365,  SPI2_SDENA0,    4,   12,    3,    1,     false)
+MUX_CFG(DM365,  SPI2_SDENA1,    4,   8,     3,    2,     false)
+
+MUX_CFG(DM365,  SPI3_SCLK,      0,   0,     3,    2,     false)
+MUX_CFG(DM365,  SPI3_SDI,       0,   2,     3,    2,     false)
+MUX_CFG(DM365,  SPI3_SDO,       0,   6,     3,    2,     false)
+MUX_CFG(DM365,  SPI3_SDENA0,    0,   4,     3,    2,     false)
+MUX_CFG(DM365,  SPI3_SDENA1,    0,   6,     3,    3,     false)
+
+MUX_CFG(DM365,  SPI4_SCLK,      4,   18,    3,    1,     false)
+MUX_CFG(DM365,  SPI4_SDI,       4,   14,    3,    1,     false)
+MUX_CFG(DM365,  SPI4_SDO,       4,   16,    3,    1,     false)
+MUX_CFG(DM365,  SPI4_SDENA0,    4,   20,    3,    1,     false)
+MUX_CFG(DM365,  SPI4_SDENA1,    4,   16,    3,    2,     false)
+
+MUX_CFG(DM365,  GPIO20,         3,   21,    3,    0,     false)
+MUX_CFG(DM365,  GPIO33,         4,   12,    3,    0,     false)
+MUX_CFG(DM365,  GPIO40,         4,   26,    3,    0,     false)
+
+MUX_CFG(DM365,  VOUT_FIELD,     1,   18,    3,    1,     false)
+MUX_CFG(DM365,  VOUT_FIELD_G81, 1,   18,    3,    0,     false)
+MUX_CFG(DM365,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
+MUX_CFG(DM365,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
+MUX_CFG(DM365,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
+MUX_CFG(DM365,  VIN_CAM_WEN,    0,   14,    3,    0,     false)
+MUX_CFG(DM365,  VIN_CAM_VD,     0,   13,    1,    0,     false)
+MUX_CFG(DM365,  VIN_CAM_HD,     0,   12,    1,    0,     false)
+MUX_CFG(DM365,  VIN_YIN4_7_EN,  0,   0,     0xff, 0,     false)
+MUX_CFG(DM365,  VIN_YIN0_3_EN,  0,   8,     0xf,  0,     false)
+
+INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
+INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
+INT_CFG(DM365,  INT_EDMA_TC1_ERR,    4,     1,    1,     false)
+INT_CFG(DM365,  INT_EDMA_TC2_ERR,    22,    1,    1,     false)
+INT_CFG(DM365,  INT_EDMA_TC3_ERR,    23,    1,    1,     false)
+INT_CFG(DM365,  INT_PRTCSS,          10,    1,    1,     false)
+INT_CFG(DM365,  INT_EMAC_RXTHRESH,   14,    1,    1,     false)
+INT_CFG(DM365,  INT_EMAC_RXPULSE,    15,    1,    1,     false)
+INT_CFG(DM365,  INT_EMAC_TXPULSE,    16,    1,    1,     false)
+INT_CFG(DM365,  INT_EMAC_MISCPULSE,  17,    1,    1,     false)
+INT_CFG(DM365,  INT_IMX0_ENABLE,     0,     1,    0,     false)
+INT_CFG(DM365,  INT_IMX0_DISABLE,    0,     1,    1,     false)
+INT_CFG(DM365,  INT_HDVICP_ENABLE,   0,     1,    1,     false)
+INT_CFG(DM365,  INT_HDVICP_DISABLE,  0,     1,    0,     false)
+INT_CFG(DM365,  INT_IMX1_ENABLE,     24,    1,    1,     false)
+INT_CFG(DM365,  INT_IMX1_DISABLE,    24,    1,    0,     false)
+INT_CFG(DM365,  INT_NSF_ENABLE,      25,    1,    1,     false)
+INT_CFG(DM365,  INT_NSF_DISABLE,     25,    1,    0,     false)
+#endif
+};
+
+static struct emac_platform_data dm365_emac_pdata = {
+        .ctrl_reg_offset        = DM365_EMAC_CNTRL_OFFSET,
+        .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
+        .ctrl_ram_offset        = DM365_EMAC_CNTRL_RAM_OFFSET,
+        .mdio_reg_offset        = DM365_EMAC_MDIO_OFFSET,
+        .ctrl_ram_size          = DM365_EMAC_CNTRL_RAM_SIZE,
+        .version                = EMAC_VERSION_2,
+};
+
+static struct resource dm365_emac_resources[] = {
+        {
+                .start  = DM365_EMAC_BASE,
+                .end    = DM365_EMAC_BASE + 0x47ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_DM365_EMAC_RXTHRESH,
+                .end    = IRQ_DM365_EMAC_RXTHRESH,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DM365_EMAC_RXPULSE,
+                .end    = IRQ_DM365_EMAC_RXPULSE,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DM365_EMAC_TXPULSE,
+                .end    = IRQ_DM365_EMAC_TXPULSE,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DM365_EMAC_MISCPULSE,
+                .end    = IRQ_DM365_EMAC_MISCPULSE,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dm365_emac_device = {
+        .name           = "davinci_emac",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &dm365_emac_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(dm365_emac_resources),
+        .resource       = dm365_emac_resources,
+};
+
+static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
+        [IRQ_VDINT0]                    = 2,
+        [IRQ_VDINT1]                    = 6,
+        [IRQ_VDINT2]                    = 6,
+        [IRQ_HISTINT]                   = 6,
+        [IRQ_H3AINT]                    = 6,
+        [IRQ_PRVUINT]                   = 6,
+        [IRQ_RSZINT]                    = 6,
+        [IRQ_DM365_INSFINT]             = 7,
+        [IRQ_VENCINT]                   = 6,
+        [IRQ_ASQINT]                    = 6,
+        [IRQ_IMXINT]                    = 6,
+        [IRQ_DM365_IMCOPINT]            = 4,
+        [IRQ_USBINT]                    = 4,
+        [IRQ_DM365_RTOINT]              = 7,
+        [IRQ_DM365_TINT5]               = 7,
+        [IRQ_DM365_TINT6]               = 5,
+        [IRQ_CCINT0]                    = 5,
+        [IRQ_CCERRINT]                  = 5,
+        [IRQ_TCERRINT0]                 = 5,
+        [IRQ_TCERRINT]                  = 7,
+        [IRQ_PSCIN]                     = 4,
+        [IRQ_DM365_SPINT2_1]            = 7,
+        [IRQ_DM365_TINT7]               = 7,
+        [IRQ_DM365_SDIOINT0]            = 7,
+        [IRQ_MBXINT]                    = 7,
+        [IRQ_MBRINT]                    = 7,
+        [IRQ_MMCINT]                    = 7,
+        [IRQ_DM365_MMCINT1]             = 7,
+        [IRQ_DM365_PWMINT3]             = 7,
+        [IRQ_DDRINT]                    = 4,
+        [IRQ_AEMIFINT]                  = 2,
+        [IRQ_DM365_SDIOINT1]            = 2,
+        [IRQ_TINT0_TINT12]              = 7,
+        [IRQ_TINT0_TINT34]              = 7,
+        [IRQ_TINT1_TINT12]              = 7,
+        [IRQ_TINT1_TINT34]              = 7,
+        [IRQ_PWMINT0]                   = 7,
+        [IRQ_PWMINT1]                   = 3,
+        [IRQ_PWMINT2]                   = 3,
+        [IRQ_I2C]                       = 3,
+        [IRQ_UARTINT0]                  = 3,
+        [IRQ_UARTINT1]                  = 3,
+        [IRQ_DM365_SPIINT0_0]           = 3,
+        [IRQ_DM365_SPIINT3_0]           = 3,
+        [IRQ_DM365_GPIO0]               = 3,
+        [IRQ_DM365_GPIO1]               = 7,
+        [IRQ_DM365_GPIO2]               = 4,
+        [IRQ_DM365_GPIO3]               = 4,
+        [IRQ_DM365_GPIO4]               = 7,
+        [IRQ_DM365_GPIO5]               = 7,
+        [IRQ_DM365_GPIO6]               = 7,
+        [IRQ_DM365_GPIO7]               = 7,
+        [IRQ_DM365_EMAC_RXTHRESH]       = 7,
+        [IRQ_DM365_EMAC_RXPULSE]        = 7,
+        [IRQ_DM365_EMAC_TXPULSE]        = 7,
+        [IRQ_DM365_EMAC_MISCPULSE]      = 7,
+        [IRQ_DM365_GPIO12]              = 7,
+        [IRQ_DM365_GPIO13]              = 7,
+        [IRQ_DM365_GPIO14]              = 7,
+        [IRQ_DM365_GPIO15]              = 7,
+        [IRQ_DM365_KEYINT]              = 7,
+        [IRQ_DM365_TCERRINT2]           = 7,
+        [IRQ_DM365_TCERRINT3]           = 7,
+        [IRQ_DM365_EMUINT]              = 7,
+};
+
+/* Four Transfer Controllers on DM365 */
+static const s8
+dm365_queue_tc_mapping[][2] = {
+        /* {event queue no, TC no} */
+        {0, 0},
+        {1, 1},
+        {2, 2},
+        {3, 3},
+        {-1, -1},
+};
+
+static const s8
+dm365_queue_priority_mapping[][2] = {
+        /* {event queue no, Priority} */
+        {0, 7},
+        {1, 7},
+        {2, 7},
+        {3, 0},
+        {-1, -1},
+};
+
+static struct edma_soc_info dm365_edma_info[] = {
+        {
+                .n_channel              = 64,
+                .n_region               = 4,
+                .n_slot                 = 256,
+                .n_tc                   = 4,
+                .n_cc                   = 1,
+                .queue_tc_mapping       = dm365_queue_tc_mapping,
+                .queue_priority_mapping = dm365_queue_priority_mapping,
+                .default_queue          = EVENTQ_2,
+        },
+};
+
+static struct resource edma_resources[] = {
+        {
+                .name   = "edma_cc0",
+                .start  = 0x01c00000,
+                .end    = 0x01c00000 + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc0",
+                .start  = 0x01c10000,
+                .end    = 0x01c10000 + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc1",
+                .start  = 0x01c10400,
+                .end    = 0x01c10400 + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc2",
+                .start  = 0x01c10800,
+                .end    = 0x01c10800 + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc3",
+                .start  = 0x01c10c00,
+                .end    = 0x01c10c00 + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma0",
+                .start  = IRQ_CCINT0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .name   = "edma0_err",
+                .start  = IRQ_CCERRINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        /* not using TC*_ERR */
+};
+
+static struct platform_device dm365_edma_device = {
+        .name                   = "edma",
+        .id                     = 0,
+        .dev.platform_data      = dm365_edma_info,
+        .num_resources          = ARRAY_SIZE(edma_resources),
+        .resource               = edma_resources,
+};
+
+static struct map_desc dm365_io_desc[] = {
+        {
+                .virtual        = IO_VIRT,
+                .pfn            = __phys_to_pfn(IO_PHYS),
+                .length         = IO_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = SRAM_VIRT,
+                .pfn            = __phys_to_pfn(0x00010000),
+                .length         = SZ_32K,
+                /* MT_MEMORY_NONCACHED requires supersection alignment */
+                .type           = MT_DEVICE,
+        },
+};
+
+/* Contents of JTAG ID register used to identify exact cpu type */
+static struct davinci_id dm365_ids[] = {
+        {
+                .variant        = 0x0,
+                .part_no        = 0xb83e,
+                .manufacturer   = 0x017,
+                .cpu_id         = DAVINCI_CPU_ID_DM365,
+                .name           = "dm365_rev1.1",
+        },
+        {
+                .variant        = 0x8,
+                .part_no        = 0xb83e,
+                .manufacturer   = 0x017,
+                .cpu_id         = DAVINCI_CPU_ID_DM365,
+                .name           = "dm365_rev1.2",
+        },
+};
+
+static void __iomem *dm365_psc_bases[] = {
+        IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
+};
+
+struct davinci_timer_info dm365_timer_info = {
+        .timers         = davinci_timer_instance,
+        .clockevent_id  = T0_BOT,
+        .clocksource_id = T0_TOP,
+};
+
+static struct plat_serial8250_port dm365_serial_platform_data[] = {
+        {
+                .mapbase        = DAVINCI_UART0_BASE,
+                .irq            = IRQ_UARTINT0,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .mapbase        = DAVINCI_UART1_BASE,
+                .irq            = IRQ_UARTINT1,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .flags          = 0
+        },
+};
+
+static struct platform_device dm365_serial_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev                    = {
+                .platform_data  = dm365_serial_platform_data,
+        },
+};
+
+static struct davinci_soc_info davinci_soc_info_dm365 = {
+        .io_desc                = dm365_io_desc,
+        .io_desc_num            = ARRAY_SIZE(dm365_io_desc),
+        .jtag_id_base           = IO_ADDRESS(0x01c40028),
+        .ids                    = dm365_ids,
+        .ids_num                = ARRAY_SIZE(dm365_ids),
+        .cpu_clks               = dm365_clks,
+        .psc_bases              = dm365_psc_bases,
+        .psc_bases_num          = ARRAY_SIZE(dm365_psc_bases),
+        .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
+        .pinmux_pins            = dm365_pins,
+        .pinmux_pins_num        = ARRAY_SIZE(dm365_pins),
+        .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+        .intc_type              = DAVINCI_INTC_TYPE_AINTC,
+        .intc_irq_prios         = dm365_default_priorities,
+        .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
+        .timer_info             = &dm365_timer_info,
+        .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
+        .gpio_num               = 104,
+        .gpio_irq               = IRQ_DM365_GPIO0,
+        .gpio_unbanked          = 8,    /* really 16 ... skip muxed GPIOs */
+        .serial_dev             = &dm365_serial_device,
+        .emac_pdata             = &dm365_emac_pdata,
+        .sram_dma               = 0x00010000,
+        .sram_len               = SZ_32K,
+};
+
+void __init dm365_init(void)
+{
+        davinci_common_init(&davinci_soc_info_dm365);
+}
+
+static int __init dm365_init_devices(void)
+{
+        if (!cpu_is_davinci_dm365())
+                return 0;
+
+        davinci_cfg_reg(DM365_INT_EDMA_CC);
+        platform_device_register(&dm365_edma_device);
+        platform_device_register(&dm365_emac_device);
+
+        return 0;
+}
+postcore_initcall(dm365_init_devices);
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index fb5449b3c97b..d6e0fa5a8d8a 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -27,6 +27,7 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
+#include <mach/asp.h>
 
 #include "clock.h"
 #include "mux.h"
@@ -303,7 +304,7 @@ struct davinci_clk dm644x_clks[] = {
         CLK("davinci_emac.1", NULL, &emac_clk),
         CLK("i2c_davinci.1", NULL, &i2c_clk),
         CLK("palm_bk3710", NULL, &ide_clk),
-        CLK("soc-audio.0", NULL, &asp_clk),
+        CLK("davinci-asp", NULL, &asp_clk),
         CLK("davinci_mmc.0", NULL, &mmcsd_clk),
         CLK(NULL, "spi", &spi_clk),
         CLK(NULL, "gpio", &gpio_clk),
@@ -484,17 +485,38 @@ static const s8 dma_chan_dm644x_no_event[] = {
         -1
 };
 
-static struct edma_soc_info dm644x_edma_info = {
-        .n_channel      = 64,
-        .n_region       = 4,
-        .n_slot         = 128,
-        .n_tc           = 2,
-        .noevent        = dma_chan_dm644x_no_event,
+static const s8
+queue_tc_mapping[][2] = {
+        /* {event queue no, TC no} */
+        {0, 0},
+        {1, 1},
+        {-1, -1},
+};
+
+static const s8
+queue_priority_mapping[][2] = {
+        /* {event queue no, Priority} */
+        {0, 3},
+        {1, 7},
+        {-1, -1},
+};
+
+static struct edma_soc_info dm644x_edma_info[] = {
+        {
+                .n_channel              = 64,
+                .n_region               = 4,
+                .n_slot                 = 128,
+                .n_tc                   = 2,
+                .n_cc                   = 1,
+                .noevent                = dma_chan_dm644x_no_event,
+                .queue_tc_mapping       = queue_tc_mapping,
+                .queue_priority_mapping = queue_priority_mapping,
+        },
 };
 
 static struct resource edma_resources[] = {
         {
-                .name   = "edma_cc",
+                .name   = "edma_cc0",
                 .start  = 0x01c00000,
                 .end    = 0x01c00000 + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
@@ -512,10 +534,12 @@ static struct resource edma_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
+                .name   = "edma0",
                 .start  = IRQ_CCINT0,
                 .flags  = IORESOURCE_IRQ,
         },
         {
+                .name   = "edma0_err",
                 .start  = IRQ_CCERRINT,
                 .flags  = IORESOURCE_IRQ,
         },
@@ -524,12 +548,91 @@ static struct resource edma_resources[] = {
 
 static struct platform_device dm644x_edma_device = {
         .name                   = "edma",
-        .id                     = -1,
-        .dev.platform_data      = &dm644x_edma_info,
+        .id                     = 0,
+        .dev.platform_data      = dm644x_edma_info,
         .num_resources          = ARRAY_SIZE(edma_resources),
         .resource               = edma_resources,
 };
 
+/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
+static struct resource dm644x_asp_resources[] = {
+        {
+                .start  = DAVINCI_ASP0_BASE,
+                .end    = DAVINCI_ASP0_BASE + SZ_8K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = DAVINCI_DMA_ASP0_TX,
+                .end    = DAVINCI_DMA_ASP0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        {
+                .start  = DAVINCI_DMA_ASP0_RX,
+                .end    = DAVINCI_DMA_ASP0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device dm644x_asp_device = {
+        .name           = "davinci-asp",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm644x_asp_resources),
+        .resource       = dm644x_asp_resources,
+};
+
+static struct resource dm644x_vpss_resources[] = {
+        {
+                /* VPSS Base address */
+                .name           = "vpss",
+                .start          = 0x01c73400,
+                .end            = 0x01c73400 + 0xff,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device dm644x_vpss_device = {
+        .name                   = "vpss",
+        .id                     = -1,
+        .dev.platform_data      = "dm644x_vpss",
+        .num_resources          = ARRAY_SIZE(dm644x_vpss_resources),
+        .resource               = dm644x_vpss_resources,
+};
+
+static struct resource vpfe_resources[] = {
+        {
+                .start          = IRQ_VDINT0,
+                .end            = IRQ_VDINT0,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = IRQ_VDINT1,
+                .end            = IRQ_VDINT1,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 0x01c70400,
+                .end            = 0x01c70400 + 0xff,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
+static struct platform_device vpfe_capture_dev = {
+        .name           = CAPTURE_DRV_NAME,
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(vpfe_resources),
+        .resource       = vpfe_resources,
+        .dev = {
+                .dma_mask               = &vpfe_capture_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void dm644x_set_vpfe_config(struct vpfe_config *cfg)
+{
+        vpfe_capture_dev.dev.platform_data = cfg;
+}
+
 /*----------------------------------------------------------------------*/
 
 static struct map_desc dm644x_io_desc[] = {
@@ -557,6 +660,13 @@ static struct davinci_id dm644x_ids[] = {
                 .cpu_id         = DAVINCI_CPU_ID_DM6446,
                 .name           = "dm6446",
         },
+        {
+                .variant        = 0x1,
+                .part_no        = 0xb700,
+                .manufacturer   = 0x017,
+                .cpu_id         = DAVINCI_CPU_ID_DM6446,
+                .name           = "dm6446a",
+        },
 };
 
 static void __iomem *dm644x_psc_bases[] = {
@@ -630,7 +740,6 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
         .intc_irq_prios         = dm644x_default_priorities,
         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
         .timer_info             = &dm644x_timer_info,
-        .wdt_base               = IO_ADDRESS(DAVINCI_WDOG_BASE),
         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
         .gpio_num               = 71,
         .gpio_irq               = IRQ_GPIOBNK0,
@@ -640,6 +749,13 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
         .sram_len               = SZ_16K,
 };
 
+void __init dm644x_init_asp(struct snd_platform_data *pdata)
+{
+        davinci_cfg_reg(DM644X_MCBSP);
+        dm644x_asp_device.dev.platform_data = pdata;
+        platform_device_register(&dm644x_asp_device);
+}
+
 void __init dm644x_init(void)
 {
         davinci_common_init(&davinci_soc_info_dm644x);
@@ -652,6 +768,9 @@ static int __init dm644x_init_devices(void)
 
         platform_device_register(&dm644x_edma_device);
         platform_device_register(&dm644x_emac_device);
+        platform_device_register(&dm644x_vpss_device);
+        platform_device_register(&vpfe_capture_dev);
+
         return 0;
 }
 postcore_initcall(dm644x_init_devices);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 334f0711e0f5..0976049c7b3b 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -27,10 +27,20 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
+#include <mach/asp.h>
 
 #include "clock.h"
 #include "mux.h"
 
+#define DAVINCI_VPIF_BASE       (0x01C12000)
+#define VDD3P3V_PWDN_OFFSET     (0x48)
+#define VSCLKDIS_OFFSET         (0x6C)
+
+#define VDD3P3V_VID_MASK        (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
+                                        BIT_MASK(0))
+#define VSCLKDIS_MASK           (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
+                                        BIT_MASK(8))
+
 /*
  * Device specific clocks
  */
@@ -162,6 +172,41 @@ static struct clk arm_clk = {
         .flags = ALWAYS_ENABLED,
 };
 
+static struct clk edma_cc_clk = {
+        .name = "edma_cc",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM646X_LPSC_TPCC,
+        .flags = ALWAYS_ENABLED,
+};
+
+static struct clk edma_tc0_clk = {
+        .name = "edma_tc0",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM646X_LPSC_TPTC0,
+        .flags = ALWAYS_ENABLED,
+};
+
+static struct clk edma_tc1_clk = {
+        .name = "edma_tc1",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM646X_LPSC_TPTC1,
+        .flags = ALWAYS_ENABLED,
+};
+
+static struct clk edma_tc2_clk = {
+        .name = "edma_tc2",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM646X_LPSC_TPTC2,
+        .flags = ALWAYS_ENABLED,
+};
+
+static struct clk edma_tc3_clk = {
+        .name = "edma_tc3",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM646X_LPSC_TPTC3,
+        .flags = ALWAYS_ENABLED,
+};
+
 static struct clk uart0_clk = {
         .name = "uart0",
         .parent = &aux_clkin,
@@ -192,6 +237,18 @@ static struct clk gpio_clk = {
         .lpsc = DM646X_LPSC_GPIO,
 };
 
+static struct clk mcasp0_clk = {
+        .name = "mcasp0",
+        .parent = &pll1_sysclk3,
+        .lpsc = DM646X_LPSC_McASP0,
+};
+
+static struct clk mcasp1_clk = {
+        .name = "mcasp1",
+        .parent = &pll1_sysclk3,
+        .lpsc = DM646X_LPSC_McASP1,
+};
+
 static struct clk aemif_clk = {
         .name = "aemif",
         .parent = &pll1_sysclk3,
@@ -237,6 +294,13 @@ static struct clk timer2_clk = {
         .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
 };
 
+
+static struct clk ide_clk = {
+        .name = "ide",
+        .parent = &pll1_sysclk4,
+        .lpsc = DAVINCI_LPSC_ATA,
+};
+
 static struct clk vpif0_clk = {
         .name = "vpif0",
         .parent = &ref_clk,
@@ -269,11 +333,18 @@ struct davinci_clk dm646x_clks[] = {
         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
         CLK(NULL, "dsp", &dsp_clk),
         CLK(NULL, "arm", &arm_clk),
+        CLK(NULL, "edma_cc", &edma_cc_clk),
+        CLK(NULL, "edma_tc0", &edma_tc0_clk),
+        CLK(NULL, "edma_tc1", &edma_tc1_clk),
+        CLK(NULL, "edma_tc2", &edma_tc2_clk),
+        CLK(NULL, "edma_tc3", &edma_tc3_clk),
         CLK(NULL, "uart0", &uart0_clk),
         CLK(NULL, "uart1", &uart1_clk),
         CLK(NULL, "uart2", &uart2_clk),
         CLK("i2c_davinci.1", NULL, &i2c_clk),
         CLK(NULL, "gpio", &gpio_clk),
+        CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
+        CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
         CLK(NULL, "aemif", &aemif_clk),
         CLK("davinci_emac.1", NULL, &emac_clk),
         CLK(NULL, "pwm0", &pwm0_clk),
@@ -281,6 +352,7 @@ struct davinci_clk dm646x_clks[] = {
         CLK(NULL, "timer0", &timer0_clk),
         CLK(NULL, "timer1", &timer1_clk),
         CLK("watchdog", NULL, &timer2_clk),
+        CLK("palm_bk3710", NULL, &ide_clk),
         CLK(NULL, "vpif0", &vpif0_clk),
         CLK(NULL, "vpif1", &vpif1_clk),
         CLK(NULL, NULL, NULL),
@@ -344,7 +416,7 @@ static struct platform_device dm646x_emac_device = {
  */
 static const struct mux_config dm646x_pins[] = {
 #ifdef CONFIG_DAVINCI_MUX
-MUX_CFG(DM646X, ATAEN,          0,   0,     1,    1,     true)
+MUX_CFG(DM646X, ATAEN,          0,   0,     5,    1,     true)
 
 MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
 
@@ -451,17 +523,43 @@ static const s8 dma_chan_dm646x_no_event[] = {
         -1
 };
 
-static struct edma_soc_info dm646x_edma_info = {
-        .n_channel      = 64,
-        .n_region       = 6,    /* 0-1, 4-7 */
-        .n_slot         = 512,
-        .n_tc           = 4,
-        .noevent        = dma_chan_dm646x_no_event,
+/* Four Transfer Controllers on DM646x */
+static const s8
+dm646x_queue_tc_mapping[][2] = {
+        /* {event queue no, TC no} */
+        {0, 0},
+        {1, 1},
+        {2, 2},
+        {3, 3},
+        {-1, -1},
+};
+
+static const s8
+dm646x_queue_priority_mapping[][2] = {
+        /* {event queue no, Priority} */
+        {0, 4},
+        {1, 0},
+        {2, 5},
+        {3, 1},
+        {-1, -1},
+};
+
+static struct edma_soc_info dm646x_edma_info[] = {
+        {
+                .n_channel              = 64,
+                .n_region               = 6,    /* 0-1, 4-7 */
+                .n_slot                 = 512,
+                .n_tc                   = 4,
+                .n_cc                   = 1,
+                .noevent                = dma_chan_dm646x_no_event,
+                .queue_tc_mapping       = dm646x_queue_tc_mapping,
+                .queue_priority_mapping = dm646x_queue_priority_mapping,
+        },
 };
 
 static struct resource edma_resources[] = {
         {
-                .name   = "edma_cc",
+                .name   = "edma_cc0",
                 .start  = 0x01c00000,
                 .end    = 0x01c00000 + SZ_64K - 1,
                 .flags  = IORESOURCE_MEM,
@@ -491,10 +589,12 @@ static struct resource edma_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
+                .name   = "edma0",
                 .start  = IRQ_CCINT0,
                 .flags  = IORESOURCE_IRQ,
         },
         {
+                .name   = "edma0_err",
                 .start  = IRQ_CCERRINT,
                 .flags  = IORESOURCE_IRQ,
         },
@@ -503,12 +603,167 @@ static struct resource edma_resources[] = {
 
 static struct platform_device dm646x_edma_device = {
         .name                   = "edma",
-        .id                     = -1,
-        .dev.platform_data      = &dm646x_edma_info,
+        .id                     = 0,
+        .dev.platform_data      = dm646x_edma_info,
         .num_resources          = ARRAY_SIZE(edma_resources),
         .resource               = edma_resources,
 };
 
+static struct resource ide_resources[] = {
+        {
+                .start          = DM646X_ATA_REG_BASE,
+                .end            = DM646X_ATA_REG_BASE + 0x7ff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = IRQ_DM646X_IDE,
+                .end            = IRQ_DM646X_IDE,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ide_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device ide_dev = {
+        .name           = "palm_bk3710",
+        .id             = -1,
+        .resource       = ide_resources,
+        .num_resources  = ARRAY_SIZE(ide_resources),
+        .dev = {
+                .dma_mask               = &ide_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource dm646x_mcasp0_resources[] = {
+        {
+                .name   = "mcasp0",
+                .start  = DAVINCI_DM646X_MCASP0_REG_BASE,
+                .end    = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /* first TX, then RX */
+        {
+                .start  = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
+                .end    = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
+                .flags  = IORESOURCE_DMA,
+        },
+        {
+                .start  = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
+                .end    = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct resource dm646x_mcasp1_resources[] = {
+        {
+                .name   = "mcasp1",
+                .start  = DAVINCI_DM646X_MCASP1_REG_BASE,
+                .end    = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /* DIT mode, only TX event */
+        {
+                .start  = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
+                .end    = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
+                .flags  = IORESOURCE_DMA,
+        },
+        /* DIT mode, dummy entry */
+        {
+                .start  = -1,
+                .end    = -1,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device dm646x_mcasp0_device = {
+        .name           = "davinci-mcasp",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dm646x_mcasp0_resources),
+        .resource       = dm646x_mcasp0_resources,
+};
+
+static struct platform_device dm646x_mcasp1_device = {
+        .name           = "davinci-mcasp",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(dm646x_mcasp1_resources),
+        .resource       = dm646x_mcasp1_resources,
+};
+
+static struct platform_device dm646x_dit_device = {
+        .name   = "spdif-dit",
+        .id     = -1,
+};
+
+static u64 vpif_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource vpif_resource[] = {
+        {
+                .start  = DAVINCI_VPIF_BASE,
+                .end    = DAVINCI_VPIF_BASE + 0x03ff,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device vpif_dev = {
+        .name           = "vpif",
+        .id             = -1,
+        .dev            = {
+                        .dma_mask               = &vpif_dma_mask,
+                        .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = vpif_resource,
+        .num_resources  = ARRAY_SIZE(vpif_resource),
+};
+
+static struct resource vpif_display_resource[] = {
+        {
+                .start = IRQ_DM646X_VP_VERTINT2,
+                .end   = IRQ_DM646X_VP_VERTINT2,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_DM646X_VP_VERTINT3,
+                .end   = IRQ_DM646X_VP_VERTINT3,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device vpif_display_dev = {
+        .name           = "vpif_display",
+        .id             = -1,
+        .dev            = {
+                        .dma_mask               = &vpif_dma_mask,
+                        .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = vpif_display_resource,
+        .num_resources  = ARRAY_SIZE(vpif_display_resource),
+};
+
+static struct resource vpif_capture_resource[] = {
+        {
+                .start = IRQ_DM646X_VP_VERTINT0,
+                .end   = IRQ_DM646X_VP_VERTINT0,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_DM646X_VP_VERTINT1,
+                .end   = IRQ_DM646X_VP_VERTINT1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device vpif_capture_dev = {
+        .name           = "vpif_capture",
+        .id             = -1,
+        .dev            = {
+                        .dma_mask               = &vpif_dma_mask,
+                        .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = vpif_capture_resource,
+        .num_resources  = ARRAY_SIZE(vpif_capture_resource),
+};
+
 /*----------------------------------------------------------------------*/
 
 static struct map_desc dm646x_io_desc[] = {
@@ -609,7 +864,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
         .intc_irq_prios         = dm646x_default_priorities,
         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
         .timer_info             = &dm646x_timer_info,
-        .wdt_base               = IO_ADDRESS(DAVINCI_WDOG_BASE),
         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
         .gpio_num               = 43, /* Only 33 usable */
         .gpio_irq               = IRQ_DM646X_GPIOBNK0,
@@ -619,6 +873,51 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
         .sram_len               = SZ_32K,
 };
 
+void __init dm646x_init_ide()
+{
+        davinci_cfg_reg(DM646X_ATAEN);
+        platform_device_register(&ide_dev);
+}
+
+void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
+{
+        dm646x_mcasp0_device.dev.platform_data = pdata;
+        platform_device_register(&dm646x_mcasp0_device);
+}
+
+void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
+{
+        dm646x_mcasp1_device.dev.platform_data = pdata;
+        platform_device_register(&dm646x_mcasp1_device);
+        platform_device_register(&dm646x_dit_device);
+}
+
+void dm646x_setup_vpif(struct vpif_display_config *display_config,
+                       struct vpif_capture_config *capture_config)
+{
+        unsigned int value;
+        void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
+
+        value = __raw_readl(base + VSCLKDIS_OFFSET);
+        value &= ~VSCLKDIS_MASK;
+        __raw_writel(value, base + VSCLKDIS_OFFSET);
+
+        value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
+        value &= ~VDD3P3V_VID_MASK;
+        __raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
+
+        davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
+        davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
+        davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
+        davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
+
+        vpif_display_dev.dev.platform_data = display_config;
+        vpif_capture_dev.dev.platform_data = capture_config;
+        platform_device_register(&vpif_dev);
+        platform_device_register(&vpif_display_dev);
+        platform_device_register(&vpif_capture_dev);
+}
+
 void __init dm646x_init(void)
 {
         davinci_common_init(&davinci_soc_info_dm646x);
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 15e9eb158bb7..f2e57d272958 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -100,132 +100,158 @@
 #define EDMA_SHADOW0    0x2000  /* 4 regions shadowing global channels */
 #define EDMA_PARM       0x4000  /* 128 param entries */
 
-#define DAVINCI_DMA_3PCC_BASE   0x01C00000
-
 #define PARM_OFFSET(param_no)   (EDMA_PARM + ((param_no) << 5))
 
+#define EDMA_DCHMAP     0x0100  /* 64 registers */
+#define CHMAP_EXIST     BIT(24)
+
 #define EDMA_MAX_DMACH           64
 #define EDMA_MAX_PARAMENTRY     512
-#define EDMA_MAX_EVQUE            2     /* FIXME too small */
+#define EDMA_MAX_CC               2
 
 
 /*****************************************************************************/
 
-static void __iomem *edmacc_regs_base;
+static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
 
-static inline unsigned int edma_read(int offset)
+static inline unsigned int edma_read(unsigned ctlr, int offset)
 {
-        return (unsigned int)__raw_readl(edmacc_regs_base + offset);
+        return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
 }
 
-static inline void edma_write(int offset, int val)
+static inline void edma_write(unsigned ctlr, int offset, int val)
 {
-        __raw_writel(val, edmacc_regs_base + offset);
+        __raw_writel(val, edmacc_regs_base[ctlr] + offset);
 }
-static inline void edma_modify(int offset, unsigned and, unsigned or)
+static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
+                unsigned or)
 {
-        unsigned val = edma_read(offset);
+        unsigned val = edma_read(ctlr, offset);
         val &= and;
         val |= or;
-        edma_write(offset, val);
+        edma_write(ctlr, offset, val);
 }
-static inline void edma_and(int offset, unsigned and)
+static inline void edma_and(unsigned ctlr, int offset, unsigned and)
 {
-        unsigned val = edma_read(offset);
+        unsigned val = edma_read(ctlr, offset);
         val &= and;
-        edma_write(offset, val);
+        edma_write(ctlr, offset, val);
 }
-static inline void edma_or(int offset, unsigned or)
+static inline void edma_or(unsigned ctlr, int offset, unsigned or)
 {
-        unsigned val = edma_read(offset);
+        unsigned val = edma_read(ctlr, offset);
         val |= or;
-        edma_write(offset, val);
+        edma_write(ctlr, offset, val);
 }
-static inline unsigned int edma_read_array(int offset, int i)
+static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
 {
-        return edma_read(offset + (i << 2));
+        return edma_read(ctlr, offset + (i << 2));
 }
-static inline void edma_write_array(int offset, int i, unsigned val)
+static inline void edma_write_array(unsigned ctlr, int offset, int i,
+                unsigned val)
 {
-        edma_write(offset + (i << 2), val);
+        edma_write(ctlr, offset + (i << 2), val);
 }
-static inline void edma_modify_array(int offset, int i,
+static inline void edma_modify_array(unsigned ctlr, int offset, int i,
                 unsigned and, unsigned or)
 {
-        edma_modify(offset + (i << 2), and, or);
+        edma_modify(ctlr, offset + (i << 2), and, or);
 }
-static inline void edma_or_array(int offset, int i, unsigned or)
+static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
 {
-        edma_or(offset + (i << 2), or);
+        edma_or(ctlr, offset + (i << 2), or);
 }
-static inline void edma_or_array2(int offset, int i, int j, unsigned or)
+static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
+                unsigned or)
 {
-        edma_or(offset + ((i*2 + j) << 2), or);
+        edma_or(ctlr, offset + ((i*2 + j) << 2), or);
 }
-static inline void edma_write_array2(int offset, int i, int j, unsigned val)
+static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
+                unsigned val)
 {
-        edma_write(offset + ((i*2 + j) << 2), val);
+        edma_write(ctlr, offset + ((i*2 + j) << 2), val);
 }
-static inline unsigned int edma_shadow0_read(int offset)
+static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
 {
-        return edma_read(EDMA_SHADOW0 + offset);
+        return edma_read(ctlr, EDMA_SHADOW0 + offset);
 }
-static inline unsigned int edma_shadow0_read_array(int offset, int i)
+static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
+                int i)
 {
-        return edma_read(EDMA_SHADOW0 + offset + (i << 2));
+        return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
 }
-static inline void edma_shadow0_write(int offset, unsigned val)
+static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
 {
-        edma_write(EDMA_SHADOW0 + offset, val);
+        edma_write(ctlr, EDMA_SHADOW0 + offset, val);
 }
-static inline void edma_shadow0_write_array(int offset, int i, unsigned val)
+static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
+                unsigned val)
 {
-        edma_write(EDMA_SHADOW0 + offset + (i << 2), val);
+        edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
 }
-static inline unsigned int edma_parm_read(int offset, int param_no)
+static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
+                int param_no)
 {
-        return edma_read(EDMA_PARM + offset + (param_no << 5));
+        return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
 }
-static inline void edma_parm_write(int offset, int param_no, unsigned val)
+static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
+                unsigned val)
 {
-        edma_write(EDMA_PARM + offset + (param_no << 5), val);
+        edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
 }
-static inline void edma_parm_modify(int offset, int param_no,
+static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
                 unsigned and, unsigned or)
 {
-        edma_modify(EDMA_PARM + offset + (param_no << 5), and, or);
+        edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
 }
-static inline void edma_parm_and(int offset, int param_no, unsigned and)
+static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
+                unsigned and)
 {
-        edma_and(EDMA_PARM + offset + (param_no << 5), and);
+        edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
 }
-static inline void edma_parm_or(int offset, int param_no, unsigned or)
+static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
+                unsigned or)
 {
-        edma_or(EDMA_PARM + offset + (param_no << 5), or);
+        edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
 }
 
 /*****************************************************************************/
 
 /* actual number of DMA channels and slots on this silicon */
-static unsigned num_channels;
-static unsigned num_slots;
+struct edma {
+        /* how many dma resources of each type */
+        unsigned        num_channels;
+        unsigned        num_region;
+        unsigned        num_slots;
+        unsigned        num_tc;
+        unsigned        num_cc;
+        enum dma_event_q        default_queue;
+
+        /* list of channels with no even trigger; terminated by "-1" */
+        const s8        *noevent;
+
+        /* The edma_inuse bit for each PaRAM slot is clear unless the
+         * channel is in use ... by ARM or DSP, for QDMA, or whatever.
+         */
+        DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
 
-static struct dma_interrupt_data {
-        void (*callback)(unsigned channel, unsigned short ch_status,
-                         void *data);
-        void *data;
-} intr_data[EDMA_MAX_DMACH];
+        /* The edma_noevent bit for each channel is clear unless
+         * it doesn't trigger DMA events on this platform.  It uses a
+         * bit of SOC-specific initialization code.
+         */
+        DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH);
 
-/* The edma_inuse bit for each PaRAM slot is clear unless the
- * channel is in use ... by ARM or DSP, for QDMA, or whatever.
- */
-static DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
+        unsigned        irq_res_start;
+        unsigned        irq_res_end;
 
-/* The edma_noevent bit for each channel is clear unless
- * it doesn't trigger DMA events on this platform.  It uses a
- * bit of SOC-specific initialization code.
- */
-static DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH);
+        struct dma_interrupt_data {
+                void (*callback)(unsigned channel, unsigned short ch_status,
+                                void *data);
+                void *data;
+        } intr_data[EDMA_MAX_DMACH];
+};
+
+static struct edma *edma_info[EDMA_MAX_CC];
 
 /* dummy param set used to (re)initialize parameter RAM slots */
 static const struct edmacc_param dummy_paramset = {
@@ -233,47 +259,52 @@ static const struct edmacc_param dummy_paramset = {
         .ccnt = 1,
 };
 
-static const int __initconst
-queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = {
-/* {event queue no, TC no} */
-        {0, 0},
-        {1, 1},
-        {-1, -1}
-};
-
-static const int __initconst
-queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = {
-        /* {event queue no, Priority} */
-        {0, 3},
-        {1, 7},
-        {-1, -1}
-};
-
 /*****************************************************************************/
 
-static void map_dmach_queue(unsigned ch_no, enum dma_event_q queue_no)
+static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
+                enum dma_event_q queue_no)
 {
         int bit = (ch_no & 0x7) * 4;
 
         /* default to low priority queue */
         if (queue_no == EVENTQ_DEFAULT)
-                queue_no = EVENTQ_1;
+                queue_no = edma_info[ctlr]->default_queue;
 
         queue_no &= 7;
-        edma_modify_array(EDMA_DMAQNUM, (ch_no >> 3),
+        edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
                         ~(0x7 << bit), queue_no << bit);
 }
 
-static void __init map_queue_tc(int queue_no, int tc_no)
+static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
 {
         int bit = queue_no * 4;
-        edma_modify(EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
+        edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
 }
 
-static void __init assign_priority_to_queue(int queue_no, int priority)
+static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
+                int priority)
 {
         int bit = queue_no * 4;
-        edma_modify(EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
+        edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
+                        ((priority & 0x7) << bit));
+}
+
+/**
+ * map_dmach_param - Maps channel number to param entry number
+ *
+ * This maps the dma channel number to param entry numberter. In
+ * other words using the DMA channel mapping registers a param entry
+ * can be mapped to any channel
+ *
+ * Callers are responsible for ensuring the channel mapping logic is
+ * included in that particular EDMA variant (Eg : dm646x)
+ *
+ */
+static void __init map_dmach_param(unsigned ctlr)
+{
+        int i;
+        for (i = 0; i < EDMA_MAX_DMACH; i++)
+                edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
 }
 
 static inline void
@@ -281,22 +312,39 @@ setup_dma_interrupt(unsigned lch,
         void (*callback)(unsigned channel, u16 ch_status, void *data),
         void *data)
 {
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(lch);
+        lch = EDMA_CHAN_SLOT(lch);
+
         if (!callback) {
-                edma_shadow0_write_array(SH_IECR, lch >> 5,
+                edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
                                 (1 << (lch & 0x1f)));
         }
 
-        intr_data[lch].callback = callback;
-        intr_data[lch].data = data;
+        edma_info[ctlr]->intr_data[lch].callback = callback;
+        edma_info[ctlr]->intr_data[lch].data = data;
 
         if (callback) {
-                edma_shadow0_write_array(SH_ICR, lch >> 5,
+                edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
                                 (1 << (lch & 0x1f)));
-                edma_shadow0_write_array(SH_IESR, lch >> 5,
+                edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
                                 (1 << (lch & 0x1f)));
         }
 }
 
+static int irq2ctlr(int irq)
+{
+        if (irq >= edma_info[0]->irq_res_start &&
+                irq <= edma_info[0]->irq_res_end)
+                return 0;
+        else if (irq >= edma_info[1]->irq_res_start &&
+                irq <= edma_info[1]->irq_res_end)
+                return 1;
+
+        return -1;
+}
+
 /******************************************************************************
  *
  * DMA interrupt handler
@@ -305,32 +353,39 @@ setup_dma_interrupt(unsigned lch,
 static irqreturn_t dma_irq_handler(int irq, void *data)
 {
         int i;
+        unsigned ctlr;
         unsigned int cnt = 0;
 
+        ctlr = irq2ctlr(irq);
+
         dev_dbg(data, "dma_irq_handler\n");
 
-        if ((edma_shadow0_read_array(SH_IPR, 0) == 0)
-            && (edma_shadow0_read_array(SH_IPR, 1) == 0))
+        if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0)
+            && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
                 return IRQ_NONE;
 
         while (1) {
                 int j;
-                if (edma_shadow0_read_array(SH_IPR, 0))
+                if (edma_shadow0_read_array(ctlr, SH_IPR, 0))
                         j = 0;
-                else if (edma_shadow0_read_array(SH_IPR, 1))
+                else if (edma_shadow0_read_array(ctlr, SH_IPR, 1))
                         j = 1;
                 else
                         break;
                 dev_dbg(data, "IPR%d %08x\n", j,
-                                edma_shadow0_read_array(SH_IPR, j));
+                                edma_shadow0_read_array(ctlr, SH_IPR, j));
                 for (i = 0; i < 32; i++) {
                         int k = (j << 5) + i;
-                        if (edma_shadow0_read_array(SH_IPR, j) & (1 << i)) {
+                        if (edma_shadow0_read_array(ctlr, SH_IPR, j) &
+                                                        (1 << i)) {
                                 /* Clear the corresponding IPR bits */
-                                edma_shadow0_write_array(SH_ICR, j, (1 << i));
-                                if (intr_data[k].callback) {
-                                        intr_data[k].callback(k, DMA_COMPLETE,
-                                                intr_data[k].data);
+                                edma_shadow0_write_array(ctlr, SH_ICR, j,
+                                                        (1 << i));
+                                if (edma_info[ctlr]->intr_data[k].callback) {
+                                        edma_info[ctlr]->intr_data[k].callback(
+                                                k, DMA_COMPLETE,
+                                                edma_info[ctlr]->intr_data[k].
+                                                data);
                                 }
                         }
                 }
@@ -338,7 +393,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
                 if (cnt > 10)
                         break;
         }
-        edma_shadow0_write(SH_IEVAL, 1);
+        edma_shadow0_write(ctlr, SH_IEVAL, 1);
         return IRQ_HANDLED;
 }
 
@@ -350,78 +405,87 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 static irqreturn_t dma_ccerr_handler(int irq, void *data)
 {
         int i;
+        unsigned ctlr;
         unsigned int cnt = 0;
 
+        ctlr = irq2ctlr(irq);
+
         dev_dbg(data, "dma_ccerr_handler\n");
 
-        if ((edma_read_array(EDMA_EMR, 0) == 0) &&
-            (edma_read_array(EDMA_EMR, 1) == 0) &&
-            (edma_read(EDMA_QEMR) == 0) && (edma_read(EDMA_CCERR) == 0))
+        if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
+            (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
+            (edma_read(ctlr, EDMA_QEMR) == 0) &&
+            (edma_read(ctlr, EDMA_CCERR) == 0))
                 return IRQ_NONE;
 
         while (1) {
                 int j = -1;
-                if (edma_read_array(EDMA_EMR, 0))
+                if (edma_read_array(ctlr, EDMA_EMR, 0))
                         j = 0;
-                else if (edma_read_array(EDMA_EMR, 1))
+                else if (edma_read_array(ctlr, EDMA_EMR, 1))
                         j = 1;
                 if (j >= 0) {
                         dev_dbg(data, "EMR%d %08x\n", j,
-                                        edma_read_array(EDMA_EMR, j));
+                                        edma_read_array(ctlr, EDMA_EMR, j));
                         for (i = 0; i < 32; i++) {
                                 int k = (j << 5) + i;
-                                if (edma_read_array(EDMA_EMR, j) & (1 << i)) {
+                                if (edma_read_array(ctlr, EDMA_EMR, j) &
+                                                        (1 << i)) {
                                         /* Clear the corresponding EMR bits */
-                                        edma_write_array(EDMA_EMCR, j, 1 << i);
+                                        edma_write_array(ctlr, EDMA_EMCR, j,
+                                                        1 << i);
                                         /* Clear any SER */
-                                        edma_shadow0_write_array(SH_SECR, j,
-                                                        (1 << i));
-                                        if (intr_data[k].callback) {
-                                                intr_data[k].callback(k,
-                                                                DMA_CC_ERROR,
-                                                                intr_data
-                                                                [k].data);
+                                        edma_shadow0_write_array(ctlr, SH_SECR,
+                                                                j, (1 << i));
+                                        if (edma_info[ctlr]->intr_data[k].
+                                                                callback) {
+                                                edma_info[ctlr]->intr_data[k].
+                                                callback(k,
+                                                DMA_CC_ERROR,
+                                                edma_info[ctlr]->intr_data
+                                                [k].data);
                                         }
                                 }
                         }
-                } else if (edma_read(EDMA_QEMR)) {
+                } else if (edma_read(ctlr, EDMA_QEMR)) {
                         dev_dbg(data, "QEMR %02x\n",
-                                edma_read(EDMA_QEMR));
+                                edma_read(ctlr, EDMA_QEMR));
                         for (i = 0; i < 8; i++) {
-                                if (edma_read(EDMA_QEMR) & (1 << i)) {
+                                if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) {
                                         /* Clear the corresponding IPR bits */
-                                        edma_write(EDMA_QEMCR, 1 << i);
-                                        edma_shadow0_write(SH_QSECR, (1 << i));
+                                        edma_write(ctlr, EDMA_QEMCR, 1 << i);
+                                        edma_shadow0_write(ctlr, SH_QSECR,
+                                                                (1 << i));
 
                                         /* NOTE:  not reported!! */
                                 }
                         }
-                } else if (edma_read(EDMA_CCERR)) {
+                } else if (edma_read(ctlr, EDMA_CCERR)) {
                         dev_dbg(data, "CCERR %08x\n",
-                                edma_read(EDMA_CCERR));
+                                edma_read(ctlr, EDMA_CCERR));
                         /* FIXME:  CCERR.BIT(16) ignored!  much better
                          * to just write CCERRCLR with CCERR value...
                          */
                         for (i = 0; i < 8; i++) {
-                                if (edma_read(EDMA_CCERR) & (1 << i)) {
+                                if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) {
                                         /* Clear the corresponding IPR bits */
-                                        edma_write(EDMA_CCERRCLR, 1 << i);
+                                        edma_write(ctlr, EDMA_CCERRCLR, 1 << i);
 
                                         /* NOTE:  not reported!! */
                                 }
                         }
                 }
-                if ((edma_read_array(EDMA_EMR, 0) == 0)
-                    && (edma_read_array(EDMA_EMR, 1) == 0)
-                    && (edma_read(EDMA_QEMR) == 0)
-                    && (edma_read(EDMA_CCERR) == 0)) {
+                if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
+                    && (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
+                    && (edma_read(ctlr, EDMA_QEMR) == 0)
+                    && (edma_read(ctlr, EDMA_CCERR) == 0)) {
                         break;
                 }
                 cnt++;
                 if (cnt > 10)
                         break;
         }
-        edma_write(EDMA_EEVAL, 1);
+        edma_write(ctlr, EDMA_EEVAL, 1);
         return IRQ_HANDLED;
 }
 
@@ -445,6 +509,45 @@ static irqreturn_t dma_tc1err_handler(int irq, void *data)
         return IRQ_HANDLED;
 }
 
+static int reserve_contiguous_params(int ctlr, unsigned int id,
+                                     unsigned int num_params,
+                                     unsigned int start_param)
+{
+        int i, j;
+        unsigned int count = num_params;
+
+        for (i = start_param; i < edma_info[ctlr]->num_slots; ++i) {
+                j = EDMA_CHAN_SLOT(i);
+                if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse))
+                        count--;
+                        if (count == 0)
+                                break;
+                else if (id == EDMA_CONT_PARAMS_FIXED_EXACT)
+                        break;
+                else
+                        count = num_params;
+        }
+
+        /*
+         * We have to clear any bits that we set
+         * if we run out parameter RAMs, i.e we do find a set
+         * of contiguous parameter RAMs but do not find the exact number
+         * requested as we may reach the total number of parameter RAMs
+         */
+        if (count) {
+                for (j = i - num_params + count + 1; j <= i ; ++j)
+                        clear_bit(j, edma_info[ctlr]->edma_inuse);
+
+                return -EBUSY;
+        }
+
+        for (j = i - num_params + 1; j <= i; ++j)
+                memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
+                        &dummy_paramset, PARM_SIZE);
+
+        return EDMA_CTLR_CHAN(ctlr, i - num_params + 1);
+}
+
 /*-----------------------------------------------------------------------*/
 
 /* Resource alloc/free:  dma channels, parameter RAM slots */
@@ -484,35 +587,53 @@ int edma_alloc_channel(int channel,
                 void *data,
                 enum dma_event_q eventq_no)
 {
+        unsigned i, done, ctlr = 0;
+
+        if (channel >= 0) {
+                ctlr = EDMA_CTLR(channel);
+                channel = EDMA_CHAN_SLOT(channel);
+        }
+
         if (channel < 0) {
-                channel = 0;
-                for (;;) {
-                        channel = find_next_bit(edma_noevent,
-                                        num_channels, channel);
-                        if (channel == num_channels)
-                                return -ENOMEM;
-                        if (!test_and_set_bit(channel, edma_inuse))
+                for (i = 0; i < EDMA_MAX_CC; i++) {
+                        channel = 0;
+                        for (;;) {
+                                channel = find_next_bit(edma_info[i]->
+                                                edma_noevent,
+                                                edma_info[i]->num_channels,
+                                                channel);
+                                if (channel == edma_info[i]->num_channels)
+                                        return -ENOMEM;
+                                if (!test_and_set_bit(channel,
+                                                edma_info[i]->edma_inuse)) {
+                                        done = 1;
+                                        ctlr = i;
+                                        break;
+                                }
+                                channel++;
+                        }
+                        if (done)
                                 break;
-                        channel++;
                 }
-        } else if (channel >= num_channels) {
+        } else if (channel >= edma_info[ctlr]->num_channels) {
                 return -EINVAL;
-        } else if (test_and_set_bit(channel, edma_inuse)) {
+        } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) {
                 return -EBUSY;
         }
 
         /* ensure access through shadow region 0 */
-        edma_or_array2(EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f));
+        edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f));
 
         /* ensure no events are pending */
-        edma_stop(channel);
-        memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel),
+        edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
+        memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
                         &dummy_paramset, PARM_SIZE);
 
         if (callback)
-                setup_dma_interrupt(channel, callback, data);
+                setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
+                                        callback, data);
 
-        map_dmach_queue(channel, eventq_no);
+        map_dmach_queue(ctlr, channel, eventq_no);
 
         return channel;
 }
@@ -532,15 +653,20 @@ EXPORT_SYMBOL(edma_alloc_channel);
  */
 void edma_free_channel(unsigned channel)
 {
-        if (channel >= num_channels)
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(channel);
+        channel = EDMA_CHAN_SLOT(channel);
+
+        if (channel >= edma_info[ctlr]->num_channels)
                 return;
 
         setup_dma_interrupt(channel, NULL, NULL);
         /* REVISIT should probably take out of shadow region 0 */
 
-        memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel),
+        memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
                         &dummy_paramset, PARM_SIZE);
-        clear_bit(channel, edma_inuse);
+        clear_bit(channel, edma_info[ctlr]->edma_inuse);
 }
 EXPORT_SYMBOL(edma_free_channel);
 
@@ -558,28 +684,33 @@ EXPORT_SYMBOL(edma_free_channel);
  *
  * Returns the number of the slot, else negative errno.
  */
-int edma_alloc_slot(int slot)
+int edma_alloc_slot(unsigned ctlr, int slot)
 {
+        if (slot >= 0)
+                slot = EDMA_CHAN_SLOT(slot);
+
         if (slot < 0) {
-                slot = num_channels;
+                slot = edma_info[ctlr]->num_channels;
                 for (;;) {
-                        slot = find_next_zero_bit(edma_inuse,
-                                        num_slots, slot);
-                        if (slot == num_slots)
+                        slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse,
+                                        edma_info[ctlr]->num_slots, slot);
+                        if (slot == edma_info[ctlr]->num_slots)
                                 return -ENOMEM;
-                        if (!test_and_set_bit(slot, edma_inuse))
+                        if (!test_and_set_bit(slot,
+                                                edma_info[ctlr]->edma_inuse))
                                 break;
                 }
-        } else if (slot < num_channels || slot >= num_slots) {
+        } else if (slot < edma_info[ctlr]->num_channels ||
+                        slot >= edma_info[ctlr]->num_slots) {
                 return -EINVAL;
-        } else if (test_and_set_bit(slot, edma_inuse)) {
+        } else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) {
                 return -EBUSY;
         }
 
-        memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot),
+        memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
                         &dummy_paramset, PARM_SIZE);
 
-        return slot;
+        return EDMA_CTLR_CHAN(ctlr, slot);
 }
 EXPORT_SYMBOL(edma_alloc_slot);
 
@@ -593,15 +724,119 @@ EXPORT_SYMBOL(edma_alloc_slot);
  */
 void edma_free_slot(unsigned slot)
 {
-        if (slot < num_channels || slot >= num_slots)
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(slot);
+        slot = EDMA_CHAN_SLOT(slot);
+
+        if (slot < edma_info[ctlr]->num_channels ||
+                slot >= edma_info[ctlr]->num_slots)
                 return;
 
-        memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot),
+        memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
                         &dummy_paramset, PARM_SIZE);
-        clear_bit(slot, edma_inuse);
+        clear_bit(slot, edma_info[ctlr]->edma_inuse);
 }
 EXPORT_SYMBOL(edma_free_slot);
 
+
+/**
+ * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
+ * The API will return the starting point of a set of
+ * contiguous PARAM's that have been requested
+ *
+ * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
+ * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
+ * @count: number of contiguous Paramter RAM's
+ * @param  - the start value of Parameter RAM that should be passed if id
+ * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
+ *
+ * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
+ * contiguous Parameter RAMs from parameter RAM 64 in the case of DaVinci SOCs
+ * and 32 in the case of Primus
+ *
+ * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
+ * set of contiguous parameter RAMs from the "param" that is passed as an
+ * argument to the API.
+ *
+ * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
+ * starts looking for a set of contiguous parameter RAMs from the "param"
+ * that is passed as an argument to the API. On failure the API will try to
+ * find a set of contiguous Parameter RAMs in the remaining Parameter RAMs
+ */
+int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
+{
+        /*
+         * The start slot requested should be greater than
+         * the number of channels and lesser than the total number
+         * of slots
+         */
+        if (slot < edma_info[ctlr]->num_channels ||
+                slot >= edma_info[ctlr]->num_slots)
+                return -EINVAL;
+
+        /*
+         * The number of parameter RAMs requested cannot be less than 1
+         * and cannot be more than the number of slots minus the number of
+         * channels
+         */
+        if (count < 1 || count >
+                (edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels))
+                return -EINVAL;
+
+        switch (id) {
+        case EDMA_CONT_PARAMS_ANY:
+                return reserve_contiguous_params(ctlr, id, count,
+                                                 edma_info[ctlr]->num_channels);
+        case EDMA_CONT_PARAMS_FIXED_EXACT:
+        case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
+                return reserve_contiguous_params(ctlr, id, count, slot);
+        default:
+                return -EINVAL;
+        }
+
+}
+EXPORT_SYMBOL(edma_alloc_cont_slots);
+
+/**
+ * edma_free_cont_slots - deallocate DMA parameter RAMs
+ * @slot: first parameter RAM of a set of parameter RAMs to be freed
+ * @count: the number of contiguous parameter RAMs to be freed
+ *
+ * This deallocates the parameter RAM slots allocated by
+ * edma_alloc_cont_slots.
+ * Callers/applications need to keep track of sets of contiguous
+ * parameter RAMs that have been allocated using the edma_alloc_cont_slots
+ * API.
+ * Callers are responsible for ensuring the slots are inactive, and will
+ * not be activated.
+ */
+int edma_free_cont_slots(unsigned slot, int count)
+{
+        unsigned ctlr;
+        int i;
+
+        ctlr = EDMA_CTLR(slot);
+        slot = EDMA_CHAN_SLOT(slot);
+
+        if (slot < edma_info[ctlr]->num_channels ||
+                slot >= edma_info[ctlr]->num_slots ||
+                count < 1)
+                return -EINVAL;
+
+        for (i = slot; i < slot + count; ++i) {
+                ctlr = EDMA_CTLR(i);
+                slot = EDMA_CHAN_SLOT(i);
+
+                memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
+                        &dummy_paramset, PARM_SIZE);
+                clear_bit(slot, edma_info[ctlr]->edma_inuse);
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL(edma_free_cont_slots);
+
 /*-----------------------------------------------------------------------*/
 
 /* Parameter RAM operations (i) -- read/write partial slots */
@@ -620,8 +855,13 @@ EXPORT_SYMBOL(edma_free_slot);
 void edma_set_src(unsigned slot, dma_addr_t src_port,
                                 enum address_mode mode, enum fifo_width width)
 {
-        if (slot < num_slots) {
-                unsigned int i = edma_parm_read(PARM_OPT, slot);
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(slot);
+        slot = EDMA_CHAN_SLOT(slot);
+
+        if (slot < edma_info[ctlr]->num_slots) {
+                unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
 
                 if (mode) {
                         /* set SAM and program FWID */
@@ -630,11 +870,11 @@ void edma_set_src(unsigned slot, dma_addr_t src_port,
                         /* clear SAM */
                         i &= ~SAM;
                 }
-                edma_parm_write(PARM_OPT, slot, i);
+                edma_parm_write(ctlr, PARM_OPT, slot, i);
 
                 /* set the source port address
                    in source register of param structure */
-                edma_parm_write(PARM_SRC, slot, src_port);
+                edma_parm_write(ctlr, PARM_SRC, slot, src_port);
         }
 }
 EXPORT_SYMBOL(edma_set_src);
@@ -653,8 +893,13 @@ EXPORT_SYMBOL(edma_set_src);
 void edma_set_dest(unsigned slot, dma_addr_t dest_port,
                                  enum address_mode mode, enum fifo_width width)
 {
-        if (slot < num_slots) {
-                unsigned int i = edma_parm_read(PARM_OPT, slot);
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(slot);
+        slot = EDMA_CHAN_SLOT(slot);
+
+        if (slot < edma_info[ctlr]->num_slots) {
+                unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
 
                 if (mode) {
                         /* set DAM and program FWID */
@@ -663,10 +908,10 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port,
                         /* clear DAM */
                         i &= ~DAM;
                 }
-                edma_parm_write(PARM_OPT, slot, i);
+                edma_parm_write(ctlr, PARM_OPT, slot, i);
                 /* set the destination port address
                    in dest register of param structure */
-                edma_parm_write(PARM_DST, slot, dest_port);
+                edma_parm_write(ctlr, PARM_DST, slot, dest_port);
         }
 }
 EXPORT_SYMBOL(edma_set_dest);
@@ -683,8 +928,12 @@ EXPORT_SYMBOL(edma_set_dest);
 void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
 {
         struct edmacc_param temp;
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(slot);
+        slot = EDMA_CHAN_SLOT(slot);
 
-        edma_read_slot(slot, &temp);
+        edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
         if (src != NULL)
                 *src = temp.src;
         if (dst != NULL)
@@ -704,10 +953,15 @@ EXPORT_SYMBOL(edma_get_position);
  */
 void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
 {
-        if (slot < num_slots) {
-                edma_parm_modify(PARM_SRC_DST_BIDX, slot,
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(slot);
+        slot = EDMA_CHAN_SLOT(slot);
+
+        if (slot < edma_info[ctlr]->num_slots) {
+                edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
                                 0xffff0000, src_bidx);
-                edma_parm_modify(PARM_SRC_DST_CIDX, slot,
+                edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
                                 0xffff0000, src_cidx);
         }
 }
@@ -725,10 +979,15 @@ EXPORT_SYMBOL(edma_set_src_index);
  */
 void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
 {
-        if (slot < num_slots) {
-                edma_parm_modify(PARM_SRC_DST_BIDX, slot,
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(slot);
+        slot = EDMA_CHAN_SLOT(slot);
+
+        if (slot < edma_info[ctlr]->num_slots) {
+                edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
                                 0x0000ffff, dest_bidx << 16);
-                edma_parm_modify(PARM_SRC_DST_CIDX, slot,
+                edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
                                 0x0000ffff, dest_cidx << 16);
         }
 }
@@ -767,16 +1026,21 @@ void edma_set_transfer_params(unsigned slot,
                 u16 acnt, u16 bcnt, u16 ccnt,
                 u16 bcnt_rld, enum sync_dimension sync_mode)
 {
-        if (slot < num_slots) {
-                edma_parm_modify(PARM_LINK_BCNTRLD, slot,
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(slot);
+        slot = EDMA_CHAN_SLOT(slot);
+
+        if (slot < edma_info[ctlr]->num_slots) {
+                edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
                                 0x0000ffff, bcnt_rld << 16);
                 if (sync_mode == ASYNC)
-                        edma_parm_and(PARM_OPT, slot, ~SYNCDIM);
+                        edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
                 else
-                        edma_parm_or(PARM_OPT, slot, SYNCDIM);
+                        edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
                 /* Set the acount, bcount, ccount registers */
-                edma_parm_write(PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
-                edma_parm_write(PARM_CCNT, slot, ccnt);
+                edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
+                edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
         }
 }
 EXPORT_SYMBOL(edma_set_transfer_params);
@@ -790,11 +1054,19 @@ EXPORT_SYMBOL(edma_set_transfer_params);
  */
 void edma_link(unsigned from, unsigned to)
 {
-        if (from >= num_slots)
+        unsigned ctlr_from, ctlr_to;
+
+        ctlr_from = EDMA_CTLR(from);
+        from = EDMA_CHAN_SLOT(from);
+        ctlr_to = EDMA_CTLR(to);
+        to = EDMA_CHAN_SLOT(to);
+
+        if (from >= edma_info[ctlr_from]->num_slots)
                 return;
-        if (to >= num_slots)
+        if (to >= edma_info[ctlr_to]->num_slots)
                 return;
-        edma_parm_modify(PARM_LINK_BCNTRLD, from, 0xffff0000, PARM_OFFSET(to));
+        edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
+                                PARM_OFFSET(to));
 }
 EXPORT_SYMBOL(edma_link);
 
@@ -807,9 +1079,14 @@ EXPORT_SYMBOL(edma_link);
  */
 void edma_unlink(unsigned from)
 {
-        if (from >= num_slots)
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(from);
+        from = EDMA_CHAN_SLOT(from);
+
+        if (from >= edma_info[ctlr]->num_slots)
                 return;
-        edma_parm_or(PARM_LINK_BCNTRLD, from, 0xffff);
+        edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
 }
 EXPORT_SYMBOL(edma_unlink);
 
@@ -829,9 +1106,15 @@ EXPORT_SYMBOL(edma_unlink);
  */
 void edma_write_slot(unsigned slot, const struct edmacc_param *param)
 {
-        if (slot >= num_slots)
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(slot);
+        slot = EDMA_CHAN_SLOT(slot);
+
+        if (slot >= edma_info[ctlr]->num_slots)
                 return;
-        memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), param, PARM_SIZE);
+        memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
+                        PARM_SIZE);
 }
 EXPORT_SYMBOL(edma_write_slot);
 
@@ -845,9 +1128,15 @@ EXPORT_SYMBOL(edma_write_slot);
  */
 void edma_read_slot(unsigned slot, struct edmacc_param *param)
 {
-        if (slot >= num_slots)
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(slot);
+        slot = EDMA_CHAN_SLOT(slot);
+
+        if (slot >= edma_info[ctlr]->num_slots)
                 return;
-        memcpy_fromio(param, edmacc_regs_base + PARM_OFFSET(slot), PARM_SIZE);
+        memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
+                        PARM_SIZE);
 }
 EXPORT_SYMBOL(edma_read_slot);
 
@@ -864,10 +1153,15 @@ EXPORT_SYMBOL(edma_read_slot);
  */
 void edma_pause(unsigned channel)
 {
-        if (channel < num_channels) {
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(channel);
+        channel = EDMA_CHAN_SLOT(channel);
+
+        if (channel < edma_info[ctlr]->num_channels) {
                 unsigned int mask = (1 << (channel & 0x1f));
 
-                edma_shadow0_write_array(SH_EECR, channel >> 5, mask);
+                edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
         }
 }
 EXPORT_SYMBOL(edma_pause);
@@ -880,10 +1174,15 @@ EXPORT_SYMBOL(edma_pause);
  */
 void edma_resume(unsigned channel)
 {
-        if (channel < num_channels) {
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(channel);
+        channel = EDMA_CHAN_SLOT(channel);
+
+        if (channel < edma_info[ctlr]->num_channels) {
                 unsigned int mask = (1 << (channel & 0x1f));
 
-                edma_shadow0_write_array(SH_EESR, channel >> 5, mask);
+                edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
         }
 }
 EXPORT_SYMBOL(edma_resume);
@@ -901,28 +1200,33 @@ EXPORT_SYMBOL(edma_resume);
  */
 int edma_start(unsigned channel)
 {
-        if (channel < num_channels) {
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(channel);
+        channel = EDMA_CHAN_SLOT(channel);
+
+        if (channel < edma_info[ctlr]->num_channels) {
                 int j = channel >> 5;
                 unsigned int mask = (1 << (channel & 0x1f));
 
                 /* EDMA channels without event association */
-                if (test_bit(channel, edma_noevent)) {
+                if (test_bit(channel, edma_info[ctlr]->edma_noevent)) {
                         pr_debug("EDMA: ESR%d %08x\n", j,
-                                edma_shadow0_read_array(SH_ESR, j));
-                        edma_shadow0_write_array(SH_ESR, j, mask);
+                                edma_shadow0_read_array(ctlr, SH_ESR, j));
+                        edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
                         return 0;
                 }
 
                 /* EDMA channel with event association */
                 pr_debug("EDMA: ER%d %08x\n", j,
-                        edma_shadow0_read_array(SH_ER, j));
+                        edma_shadow0_read_array(ctlr, SH_ER, j));
                 /* Clear any pending error */
-                edma_write_array(EDMA_EMCR, j, mask);
+                edma_write_array(ctlr, EDMA_EMCR, j, mask);
                 /* Clear any SER */
-                edma_shadow0_write_array(SH_SECR, j, mask);
-                edma_shadow0_write_array(SH_EESR, j, mask);
+                edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+                edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
                 pr_debug("EDMA: EER%d %08x\n", j,
-                        edma_shadow0_read_array(SH_EER, j));
+                        edma_shadow0_read_array(ctlr, SH_EER, j));
                 return 0;
         }
 
@@ -941,17 +1245,22 @@ EXPORT_SYMBOL(edma_start);
  */
 void edma_stop(unsigned channel)
 {
-        if (channel < num_channels) {
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(channel);
+        channel = EDMA_CHAN_SLOT(channel);
+
+        if (channel < edma_info[ctlr]->num_channels) {
                 int j = channel >> 5;
                 unsigned int mask = (1 << (channel & 0x1f));
 
-                edma_shadow0_write_array(SH_EECR, j, mask);
-                edma_shadow0_write_array(SH_ECR, j, mask);
-                edma_shadow0_write_array(SH_SECR, j, mask);
-                edma_write_array(EDMA_EMCR, j, mask);
+                edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
+                edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
+                edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+                edma_write_array(ctlr, EDMA_EMCR, j, mask);
 
                 pr_debug("EDMA: EER%d %08x\n", j,
-                                edma_shadow0_read_array(SH_EER, j));
+                                edma_shadow0_read_array(ctlr, SH_EER, j));
 
                 /* REVISIT:  consider guarding against inappropriate event
                  * chaining by overwriting with dummy_paramset.
@@ -975,18 +1284,23 @@ EXPORT_SYMBOL(edma_stop);
 
 void edma_clean_channel(unsigned channel)
 {
-        if (channel < num_channels) {
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(channel);
+        channel = EDMA_CHAN_SLOT(channel);
+
+        if (channel < edma_info[ctlr]->num_channels) {
                 int j = (channel >> 5);
                 unsigned int mask = 1 << (channel & 0x1f);
 
                 pr_debug("EDMA: EMR%d %08x\n", j,
-                                edma_read_array(EDMA_EMR, j));
-                edma_shadow0_write_array(SH_ECR, j, mask);
+                                edma_read_array(ctlr, EDMA_EMR, j));
+                edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
                 /* Clear the corresponding EMR bits */
-                edma_write_array(EDMA_EMCR, j, mask);
+                edma_write_array(ctlr, EDMA_EMCR, j, mask);
                 /* Clear any SER */
-                edma_shadow0_write_array(SH_SECR, j, mask);
-                edma_write(EDMA_CCERRCLR, (1 << 16) | 0x3);
+                edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+                edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3);
         }
 }
 EXPORT_SYMBOL(edma_clean_channel);
@@ -998,12 +1312,17 @@ EXPORT_SYMBOL(edma_clean_channel);
  */
 void edma_clear_event(unsigned channel)
 {
-        if (channel >= num_channels)
+        unsigned ctlr;
+
+        ctlr = EDMA_CTLR(channel);
+        channel = EDMA_CHAN_SLOT(channel);
+
+        if (channel >= edma_info[ctlr]->num_channels)
                 return;
         if (channel < 32)
-                edma_write(EDMA_ECR, 1 << channel);
+                edma_write(ctlr, EDMA_ECR, 1 << channel);
         else
-                edma_write(EDMA_ECRH, 1 << (channel - 32));
+                edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32));
 }
 EXPORT_SYMBOL(edma_clear_event);
 
@@ -1012,62 +1331,133 @@ EXPORT_SYMBOL(edma_clear_event);
 static int __init edma_probe(struct platform_device *pdev)
 {
         struct edma_soc_info    *info = pdev->dev.platform_data;
-        int                     i;
-        int                     status;
+        const s8                (*queue_priority_mapping)[2];
+        const s8                (*queue_tc_mapping)[2];
+        int                     i, j, found = 0;
+        int                     status = -1;
         const s8                *noevent;
-        int                     irq = 0, err_irq = 0;
-        struct resource         *r;
-        resource_size_t         len;
+        int                     irq[EDMA_MAX_CC] = {0, 0};
+        int                     err_irq[EDMA_MAX_CC] = {0, 0};
+        struct resource         *r[EDMA_MAX_CC] = {NULL};
+        resource_size_t         len[EDMA_MAX_CC];
+        char                    res_name[10];
+        char                    irq_name[10];
 
         if (!info)
                 return -ENODEV;
 
-        r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma_cc");
-        if (!r)
-                return -ENODEV;
+        for (j = 0; j < EDMA_MAX_CC; j++) {
+                sprintf(res_name, "edma_cc%d", j);
+                r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+                                                res_name);
+                if (!r[j]) {
+                        if (found)
+                                break;
+                        else
+                                return -ENODEV;
+                } else
+                        found = 1;
+
+                len[j] = resource_size(r[j]);
+
+                r[j] = request_mem_region(r[j]->start, len[j],
+                        dev_name(&pdev->dev));
+                if (!r[j]) {
+                        status = -EBUSY;
+                        goto fail1;
+                }
 
-        len = r->end - r->start + 1;
+                edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
+                if (!edmacc_regs_base[j]) {
+                        status = -EBUSY;
+                        goto fail1;
+                }
 
-        r = request_mem_region(r->start, len, r->name);
-        if (!r)
-                return -EBUSY;
+                edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
+                if (!edma_info[j]) {
+                        status = -ENOMEM;
+                        goto fail1;
+                }
+                memset(edma_info[j], 0, sizeof(struct edma));
+
+                edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel,
+                                                        EDMA_MAX_DMACH);
+                edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot,
+                                                        EDMA_MAX_PARAMENTRY);
+                edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc,
+                                                        EDMA_MAX_CC);
+
+                edma_info[j]->default_queue = info[j].default_queue;
+                if (!edma_info[j]->default_queue)
+                        edma_info[j]->default_queue = EVENTQ_1;
+
+                dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
+                        edmacc_regs_base[j]);
+
+                for (i = 0; i < edma_info[j]->num_slots; i++)
+                        memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
+                                        &dummy_paramset, PARM_SIZE);
+
+                noevent = info[j].noevent;
+                if (noevent) {
+                        while (*noevent != -1)
+                                set_bit(*noevent++, edma_info[j]->edma_noevent);
+                }
 
-        edmacc_regs_base = ioremap(r->start, len);
-        if (!edmacc_regs_base) {
-                status = -EBUSY;
-                goto fail1;
-        }
+                sprintf(irq_name, "edma%d", j);
+                irq[j] = platform_get_irq_byname(pdev, irq_name);
+                edma_info[j]->irq_res_start = irq[j];
+                status = request_irq(irq[j], dma_irq_handler, 0, "edma",
+                                        &pdev->dev);
+                if (status < 0) {
+                        dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+                                irq[j], status);
+                        goto fail;
+                }
 
-        num_channels = min_t(unsigned, info->n_channel, EDMA_MAX_DMACH);
-        num_slots = min_t(unsigned, info->n_slot, EDMA_MAX_PARAMENTRY);
+                sprintf(irq_name, "edma%d_err", j);
+                err_irq[j] = platform_get_irq_byname(pdev, irq_name);
+                edma_info[j]->irq_res_end = err_irq[j];
+                status = request_irq(err_irq[j], dma_ccerr_handler, 0,
+                                        "edma_error", &pdev->dev);
+                if (status < 0) {
+                        dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+                                err_irq[j], status);
+                        goto fail;
+                }
 
-        dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base);
+                /* Everything lives on transfer controller 1 until otherwise
+                 * specified. This way, long transfers on the low priority queue
+                 * started by the codec engine will not cause audio defects.
+                 */
+                for (i = 0; i < edma_info[j]->num_channels; i++)
+                        map_dmach_queue(j, i, EVENTQ_1);
 
-        for (i = 0; i < num_slots; i++)
-                memcpy_toio(edmacc_regs_base + PARM_OFFSET(i),
-                                &dummy_paramset, PARM_SIZE);
+                queue_tc_mapping = info[j].queue_tc_mapping;
+                queue_priority_mapping = info[j].queue_priority_mapping;
 
-        noevent = info->noevent;
-        if (noevent) {
-                while (*noevent != -1)
-                        set_bit(*noevent++, edma_noevent);
-        }
+                /* Event queue to TC mapping */
+                for (i = 0; queue_tc_mapping[i][0] != -1; i++)
+                        map_queue_tc(j, queue_tc_mapping[i][0],
+                                        queue_tc_mapping[i][1]);
 
-        irq = platform_get_irq(pdev, 0);
-        status = request_irq(irq, dma_irq_handler, 0, "edma", &pdev->dev);
-        if (status < 0) {
-                dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
-                        irq, status);
-                goto fail;
-        }
+                /* Event queue priority mapping */
+                for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+                        assign_priority_to_queue(j,
+                                                queue_priority_mapping[i][0],
+                                                queue_priority_mapping[i][1]);
+
+                /* Map the channel to param entry if channel mapping logic
+                 * exist
+                 */
+                if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
+                        map_dmach_param(j);
 
-        err_irq = platform_get_irq(pdev, 1);
-        status = request_irq(err_irq, dma_ccerr_handler, 0,
-                                "edma_error", &pdev->dev);
-        if (status < 0) {
-                dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
-                        err_irq, status);
-                goto fail;
+                for (i = 0; i < info[j].n_region; i++) {
+                        edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
+                        edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
+                        edma_write_array(j, EDMA_QRAE, i, 0x0);
+                }
         }
 
         if (tc_errs_handled) {
@@ -1087,38 +1477,23 @@ static int __init edma_probe(struct platform_device *pdev)
                 }
         }
 
-        /* Everything lives on transfer controller 1 until otherwise specified.
-         * This way, long transfers on the low priority queue
-         * started by the codec engine will not cause audio defects.
-         */
-        for (i = 0; i < num_channels; i++)
-                map_dmach_queue(i, EVENTQ_1);
-
-        /* Event queue to TC mapping */
-        for (i = 0; queue_tc_mapping[i][0] != -1; i++)
-                map_queue_tc(queue_tc_mapping[i][0], queue_tc_mapping[i][1]);
-
-        /* Event queue priority mapping */
-        for (i = 0; queue_priority_mapping[i][0] != -1; i++)
-                assign_priority_to_queue(queue_priority_mapping[i][0],
-                                         queue_priority_mapping[i][1]);
-
-        for (i = 0; i < info->n_region; i++) {
-                edma_write_array2(EDMA_DRAE, i, 0, 0x0);
-                edma_write_array2(EDMA_DRAE, i, 1, 0x0);
-                edma_write_array(EDMA_QRAE, i, 0x0);
-        }
-
         return 0;
 
 fail:
-        if (err_irq)
-                free_irq(err_irq, NULL);
-        if (irq)
-                free_irq(irq, NULL);
-        iounmap(edmacc_regs_base);
+        for (i = 0; i < EDMA_MAX_CC; i++) {
+                if (err_irq[i])
+                        free_irq(err_irq[i], &pdev->dev);
+                if (irq[i])
+                        free_irq(irq[i], &pdev->dev);
+        }
 fail1:
-        release_mem_region(r->start, len);
+        for (i = 0; i < EDMA_MAX_CC; i++) {
+                if (r[i])
+                        release_mem_region(r[i]->start, len[i]);
+                if (edmacc_regs_base[i])
+                        iounmap(edmacc_regs_base[i]);
+                kfree(edma_info[i]);
+        }
         return status;
 }
 
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 1b6532159c58..f6ea9db11f41 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -34,6 +34,7 @@ static DEFINE_SPINLOCK(gpio_lock);
 struct davinci_gpio {
         struct gpio_chip        chip;
         struct gpio_controller  *__iomem regs;
+        int                     irq_base;
 };
 
 static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
@@ -161,8 +162,7 @@ pure_initcall(davinci_gpio_setup);
  * used as output pins ... which is convenient for testing.
  *
  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
- * to their GPIOBNK0 irq, with a bit less overhead but less flexibility
- * on triggering (e.g. no edge options).  We don't try to use those.
+ * to their GPIOBNK0 irq, with a bit less overhead.
  *
  * All those INTC hookups (direct, plus several IRQ banks) can also
  * serve as EDMA event triggers.
@@ -171,7 +171,7 @@ pure_initcall(davinci_gpio_setup);
 static void gpio_irq_disable(unsigned irq)
 {
         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
-        u32 mask = __gpio_mask(irq_to_gpio(irq));
+        u32 mask = (u32) get_irq_data(irq);
 
         __raw_writel(mask, &g->clr_falling);
         __raw_writel(mask, &g->clr_rising);
@@ -180,7 +180,7 @@ static void gpio_irq_disable(unsigned irq)
 static void gpio_irq_enable(unsigned irq)
 {
         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
-        u32 mask = __gpio_mask(irq_to_gpio(irq));
+        u32 mask = (u32) get_irq_data(irq);
         unsigned status = irq_desc[irq].status;
 
         status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
@@ -196,7 +196,7 @@ static void gpio_irq_enable(unsigned irq)
 static int gpio_irq_type(unsigned irq, unsigned trigger)
 {
         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
-        u32 mask = __gpio_mask(irq_to_gpio(irq));
+        u32 mask = (u32) get_irq_data(irq);
 
         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
                 return -EINVAL;
@@ -260,6 +260,45 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
         /* now it may re-trigger */
 }
 
+static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
+{
+        struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+
+        if (d->irq_base >= 0)
+                return d->irq_base + offset;
+        else
+                return -ENODEV;
+}
+
+static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
+{
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+        /* NOTE:  we assume for now that only irqs in the first gpio_chip
+         * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
+         */
+        if (offset < soc_info->gpio_unbanked)
+                return soc_info->gpio_irq + offset;
+        else
+                return -ENODEV;
+}
+
+static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
+{
+        struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+        u32 mask = (u32) get_irq_data(irq);
+
+        if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
+                return -EINVAL;
+
+        __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
+                     ? &g->set_falling : &g->clr_falling);
+        __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
+                     ? &g->set_rising : &g->clr_rising);
+
+        return 0;
+}
+
 /*
  * NOTE:  for suspend/resume, probably best to make a platform_device with
  * suspend_late/resume_resume calls hooking into results of the set_wake()
@@ -275,6 +314,7 @@ static int __init davinci_gpio_irq_setup(void)
         u32             binten = 0;
         unsigned        ngpio, bank_irq;
         struct davinci_soc_info *soc_info = &davinci_soc_info;
+        struct gpio_controller  *__iomem g;
 
         ngpio = soc_info->gpio_num;
 
@@ -292,12 +332,63 @@ static int __init davinci_gpio_irq_setup(void)
         }
         clk_enable(clk);
 
+        /* Arrange gpio_to_irq() support, handling either direct IRQs or
+         * banked IRQs.  Having GPIOs in the first GPIO bank use direct
+         * IRQs, while the others use banked IRQs, would need some setup
+         * tweaks to recognize hardware which can do that.
+         */
+        for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
+                chips[bank].chip.to_irq = gpio_to_irq_banked;
+                chips[bank].irq_base = soc_info->gpio_unbanked
+                        ? -EINVAL
+                        : (soc_info->intc_irq_num + gpio);
+        }
+
+        /*
+         * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
+         * controller only handling trigger modes.  We currently assume no
+         * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
+         */
+        if (soc_info->gpio_unbanked) {
+                static struct irq_chip gpio_irqchip_unbanked;
+
+                /* pass "bank 0" GPIO IRQs to AINTC */
+                chips[0].chip.to_irq = gpio_to_irq_unbanked;
+                binten = BIT(0);
+
+                /* AINTC handles mask/unmask; GPIO handles triggering */
+                irq = bank_irq;
+                gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
+                gpio_irqchip_unbanked.name = "GPIO-AINTC";
+                gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
+
+                /* default trigger: both edges */
+                g = gpio2controller(0);
+                __raw_writel(~0, &g->set_falling);
+                __raw_writel(~0, &g->set_rising);
+
+                /* set the direct IRQs up to use that irqchip */
+                for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
+                        set_irq_chip(irq, &gpio_irqchip_unbanked);
+                        set_irq_data(irq, (void *) __gpio_mask(gpio));
+                        set_irq_chip_data(irq, g);
+                        irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
+                }
+
+                goto done;
+        }
+
+        /*
+         * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
+         * then chain through our own handler.
+         */
         for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
                         gpio < ngpio;
                         bank++, bank_irq++) {
-                struct gpio_controller  *__iomem g = gpio2controller(gpio);
                 unsigned                i;
 
+                /* disabled by default, enabled only as needed */
+                g = gpio2controller(gpio);
                 __raw_writel(~0, &g->clr_falling);
                 __raw_writel(~0, &g->clr_rising);
 
@@ -309,6 +400,7 @@ static int __init davinci_gpio_irq_setup(void)
                 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
                         set_irq_chip(irq, &gpio_irqchip);
                         set_irq_chip_data(irq, g);
+                        set_irq_data(irq, (void *) __gpio_mask(gpio));
                         set_irq_handler(irq, handle_simple_irq);
                         set_irq_flags(irq, IRQF_VALID);
                 }
@@ -316,6 +408,7 @@ static int __init davinci_gpio_irq_setup(void)
                 binten |= BIT(bank);
         }
 
+done:
         /* BINTEN -- per-bank interrupt enable. genirq would also let these
          * bits be set/cleared dynamically.
          */
diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
index e0abc437d796..18e4ce34ece6 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -5,21 +5,73 @@
 #define __ASM_ARCH_DAVINCI_ASP_H
 
 #include <mach/irqs.h>
+#include <mach/edma.h>
 
-/* Bases of register banks */
+/* Bases of dm644x and dm355 register banks */
 #define DAVINCI_ASP0_BASE       0x01E02000
 #define DAVINCI_ASP1_BASE       0x01E04000
 
-/* EDMA channels */
+/* Bases of dm646x register banks */
+#define DAVINCI_DM646X_MCASP0_REG_BASE          0x01D01000
+#define DAVINCI_DM646X_MCASP1_REG_BASE          0x01D01800
+
+/* Bases of da850/da830 McASP0  register banks */
+#define DAVINCI_DA8XX_MCASP0_REG_BASE   0x01D00000
+
+/* Bases of da830 McASP1 register banks */
+#define DAVINCI_DA830_MCASP1_REG_BASE   0x01D04000
+
+/* EDMA channels of dm644x and dm355 */
 #define DAVINCI_DMA_ASP0_TX     2
 #define DAVINCI_DMA_ASP0_RX     3
 #define DAVINCI_DMA_ASP1_TX     8
 #define DAVINCI_DMA_ASP1_RX     9
 
+/* EDMA channels of dm646x */
+#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0        6
+#define DAVINCI_DM646X_DMA_MCASP0_AREVT0        9
+#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1        12
+
+/* EDMA channels of da850/da830 McASP0 */
+#define DAVINCI_DA8XX_DMA_MCASP0_AREVT  0
+#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT  1
+
+/* EDMA channels of da830 McASP1 */
+#define DAVINCI_DA830_DMA_MCASP1_AREVT  2
+#define DAVINCI_DA830_DMA_MCASP1_AXEVT  3
+
 /* Interrupts */
 #define DAVINCI_ASP0_RX_INT     IRQ_MBRINT
 #define DAVINCI_ASP0_TX_INT     IRQ_MBXINT
 #define DAVINCI_ASP1_RX_INT     IRQ_MBRINT
 #define DAVINCI_ASP1_TX_INT     IRQ_MBXINT
 
+struct snd_platform_data {
+        u32 tx_dma_offset;
+        u32 rx_dma_offset;
+        enum dma_event_q eventq_no;     /* event queue number */
+        unsigned int codec_fmt;
+
+        /* McASP specific fields */
+        int tdm_slots;
+        u8 op_mode;
+        u8 num_serializer;
+        u8 *serial_dir;
+        u8 version;
+        u8 txnumevt;
+        u8 rxnumevt;
+};
+
+enum {
+        MCASP_VERSION_1 = 0,    /* DM646x */
+        MCASP_VERSION_2,        /* DA8xx/OMAPL1x */
+};
+
+#define INACTIVE_MODE   0
+#define TX_MODE         1
+#define RX_MODE         2
+
+#define DAVINCI_MCASP_IIS_MODE  0
+#define DAVINCI_MCASP_DIT_MODE  1
+
 #endif /* __ASM_ARCH_DAVINCI_ASP_H */
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index a1f03b606d8f..1fd3917cae4e 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -60,10 +60,10 @@ struct davinci_soc_info {
         u8                              *intc_irq_prios;
         unsigned long                   intc_irq_num;
         struct davinci_timer_info       *timer_info;
-        void __iomem                    *wdt_base;
         void __iomem                    *gpio_base;
         unsigned                        gpio_num;
         unsigned                        gpio_irq;
+        unsigned                        gpio_unbanked;
         struct platform_device          *serial_dev;
         struct emac_platform_data       *emac_pdata;
         dma_addr_t                      sram_dma;
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index d12a5ed2959a..189b1ff13642 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -30,6 +30,9 @@ struct davinci_id {
 #define DAVINCI_CPU_ID_DM6446           0x64460000
 #define DAVINCI_CPU_ID_DM6467           0x64670000
 #define DAVINCI_CPU_ID_DM355            0x03550000
+#define DAVINCI_CPU_ID_DM365            0x03650000
+#define DAVINCI_CPU_ID_DA830            0x08300000
+#define DAVINCI_CPU_ID_DA850            0x08500000
 
 #define IS_DAVINCI_CPU(type, id)                                        \
 static inline int is_davinci_ ##type(void)                              \
@@ -40,6 +43,9 @@ static inline int is_davinci_ ##type(void)				\
 IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446)
 IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467)
 IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
+IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
+IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
+IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
 
 #ifdef CONFIG_ARCH_DAVINCI_DM644x
 #define cpu_is_davinci_dm644x() is_davinci_dm644x()
@@ -59,4 +65,22 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
 #define cpu_is_davinci_dm355() 0
 #endif
 
+#ifdef CONFIG_ARCH_DAVINCI_DM365
+#define cpu_is_davinci_dm365() is_davinci_dm365()
+#else
+#define cpu_is_davinci_dm365() 0
+#endif
+
+#ifdef CONFIG_ARCH_DAVINCI_DA830
+#define cpu_is_davinci_da830() is_davinci_da830()
+#else
+#define cpu_is_davinci_da830() 0
+#endif
+
+#ifdef CONFIG_ARCH_DAVINCI_DA850
+#define cpu_is_davinci_da850() is_davinci_da850()
+#else
+#define cpu_is_davinci_da850() 0
+#endif
+
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
new file mode 100644
index 000000000000..d4095d0572c6
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -0,0 +1,121 @@
+/*
+ * Chip specific defines for DA8XX/OMAP L1XX SoC
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_DAVINCI_DA8XX_H
+#define __ASM_ARCH_DAVINCI_DA8XX_H
+
+#include <mach/serial.h>
+#include <mach/edma.h>
+#include <mach/i2c.h>
+#include <mach/emac.h>
+#include <mach/asp.h>
+#include <mach/mmc.h>
+
+/*
+ * The cp_intc interrupt controller for the da8xx isn't in the same
+ * chunk of physical memory space as the other registers (like it is
+ * on the davincis) so it needs to be mapped separately.  It will be
+ * mapped early on when the I/O space is mapped and we'll put it just
+ * before the I/O space in the processor's virtual memory space.
+ */
+#define DA8XX_CP_INTC_BASE      0xfffee000
+#define DA8XX_CP_INTC_SIZE      SZ_8K
+#define DA8XX_CP_INTC_VIRT      (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
+
+#define DA8XX_BOOT_CFG_BASE     (IO_PHYS + 0x14000)
+
+#define DA8XX_PSC0_BASE         0x01c10000
+#define DA8XX_PLL0_BASE         0x01c11000
+#define DA8XX_JTAG_ID_REG       0x01c14018
+#define DA8XX_TIMER64P0_BASE    0x01c20000
+#define DA8XX_TIMER64P1_BASE    0x01c21000
+#define DA8XX_GPIO_BASE         0x01e26000
+#define DA8XX_PSC1_BASE         0x01e27000
+#define DA8XX_LCD_CNTRL_BASE    0x01e13000
+#define DA8XX_MMCSD0_BASE       0x01c40000
+#define DA8XX_AEMIF_CS2_BASE    0x60000000
+#define DA8XX_AEMIF_CS3_BASE    0x62000000
+#define DA8XX_AEMIF_CTL_BASE    0x68000000
+
+#define PINMUX0                 0x00
+#define PINMUX1                 0x04
+#define PINMUX2                 0x08
+#define PINMUX3                 0x0c
+#define PINMUX4                 0x10
+#define PINMUX5                 0x14
+#define PINMUX6                 0x18
+#define PINMUX7                 0x1c
+#define PINMUX8                 0x20
+#define PINMUX9                 0x24
+#define PINMUX10                0x28
+#define PINMUX11                0x2c
+#define PINMUX12                0x30
+#define PINMUX13                0x34
+#define PINMUX14                0x38
+#define PINMUX15                0x3c
+#define PINMUX16                0x40
+#define PINMUX17                0x44
+#define PINMUX18                0x48
+#define PINMUX19                0x4c
+
+void __init da830_init(void);
+void __init da850_init(void);
+
+int da8xx_register_edma(void);
+int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
+int da8xx_register_watchdog(void);
+int da8xx_register_emac(void);
+int da8xx_register_lcdc(void);
+int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
+void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata);
+
+extern struct platform_device da8xx_serial_device;
+extern struct emac_platform_data da8xx_emac_pdata;
+
+extern const short da830_emif25_pins[];
+extern const short da830_spi0_pins[];
+extern const short da830_spi1_pins[];
+extern const short da830_mmc_sd_pins[];
+extern const short da830_uart0_pins[];
+extern const short da830_uart1_pins[];
+extern const short da830_uart2_pins[];
+extern const short da830_usb20_pins[];
+extern const short da830_usb11_pins[];
+extern const short da830_uhpi_pins[];
+extern const short da830_cpgmac_pins[];
+extern const short da830_emif3c_pins[];
+extern const short da830_mcasp0_pins[];
+extern const short da830_mcasp1_pins[];
+extern const short da830_mcasp2_pins[];
+extern const short da830_i2c0_pins[];
+extern const short da830_i2c1_pins[];
+extern const short da830_lcdcntl_pins[];
+extern const short da830_pwm_pins[];
+extern const short da830_ecap0_pins[];
+extern const short da830_ecap1_pins[];
+extern const short da830_ecap2_pins[];
+extern const short da830_eqep0_pins[];
+extern const short da830_eqep1_pins[];
+
+extern const short da850_uart0_pins[];
+extern const short da850_uart1_pins[];
+extern const short da850_uart2_pins[];
+extern const short da850_i2c0_pins[];
+extern const short da850_i2c1_pins[];
+extern const short da850_cpgmac_pins[];
+extern const short da850_mcasp_pins[];
+extern const short da850_lcdcntl_pins[];
+extern const short da850_mmcsd0_pins[];
+extern const short da850_nand_pins[];
+extern const short da850_nor_pins[];
+
+int da8xx_pinmux_setup(const short pins[]);
+
+#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index de3fc2182b47..17ab5236da66 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -24,7 +24,15 @@
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0x01000000        @ physical base address
                 movne   \rx, #0xfe000000        @ virtual base
+#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
+#error Cannot enable DaVinci and DA8XX platforms concurrently
+#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) || \
+        defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+                orr     \rx, \rx, #0x00d00000   @ physical base address
+                orr     \rx, \rx, #0x0000d000   @ of UART 2
+#else
                 orr     \rx, \rx, #0x00c20000   @ UART 0
+#endif
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h
index 54903b72438e..85536d8e8336 100644
--- a/arch/arm/mach-davinci/include/mach/dm355.h
+++ b/arch/arm/mach-davinci/include/mach/dm355.h
@@ -12,11 +12,18 @@
 #define __ASM_ARCH_DM355_H
 
 #include <mach/hardware.h>
+#include <mach/asp.h>
+#include <media/davinci/vpfe_capture.h>
+
+#define ASP1_TX_EVT_EN  1
+#define ASP1_RX_EVT_EN  2
 
 struct spi_board_info;
 
 void __init dm355_init(void);
 void dm355_init_spi0(unsigned chipselect_mask,
                 struct spi_board_info *info, unsigned len);
+void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
+void dm355_set_vpfe_config(struct vpfe_config *cfg);
 
 #endif /* __ASM_ARCH_DM355_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
new file mode 100644
index 000000000000..09db4343bb4c
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_DM365_H
+#define __ASM_ARCH_DM665_H
+
+#include <linux/platform_device.h>
+#include <mach/hardware.h>
+#include <mach/emac.h>
+
+#define DM365_EMAC_BASE                 (0x01D07000)
+#define DM365_EMAC_CNTRL_OFFSET         (0x0000)
+#define DM365_EMAC_CNTRL_MOD_OFFSET     (0x3000)
+#define DM365_EMAC_CNTRL_RAM_OFFSET     (0x1000)
+#define DM365_EMAC_MDIO_OFFSET          (0x4000)
+#define DM365_EMAC_CNTRL_RAM_SIZE       (0x2000)
+
+void __init dm365_init(void);
+
+#endif /* __ASM_ARCH_DM365_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 15d42b92a8c9..0efb73852c2c 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -25,6 +25,8 @@
 #include <linux/platform_device.h>
 #include <mach/hardware.h>
 #include <mach/emac.h>
+#include <mach/asp.h>
+#include <media/davinci/vpfe_capture.h>
 
 #define DM644X_EMAC_BASE                (0x01C80000)
 #define DM644X_EMAC_CNTRL_OFFSET        (0x0000)
@@ -34,5 +36,7 @@
 #define DM644X_EMAC_CNTRL_RAM_SIZE      (0x2000)
 
 void __init dm644x_init(void);
+void __init dm644x_init_asp(struct snd_platform_data *pdata);
+void dm644x_set_vpfe_config(struct vpfe_config *cfg);
 
 #endif /* __ASM_ARCH_DM644X_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 1fc764c8646e..8cec746ae9d2 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -13,6 +13,9 @@
 
 #include <mach/hardware.h>
 #include <mach/emac.h>
+#include <mach/asp.h>
+#include <linux/i2c.h>
+#include <linux/videodev2.h>
 
 #define DM646X_EMAC_BASE                (0x01C80000)
 #define DM646X_EMAC_CNTRL_OFFSET        (0x0000)
@@ -21,6 +24,68 @@
 #define DM646X_EMAC_MDIO_OFFSET         (0x4000)
 #define DM646X_EMAC_CNTRL_RAM_SIZE      (0x2000)
 
+#define DM646X_ATA_REG_BASE             (0x01C66000)
+
 void __init dm646x_init(void);
+void __init dm646x_init_ide(void);
+void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
+void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
+
+void dm646x_video_init(void);
+
+enum vpif_if_type {
+        VPIF_IF_BT656,
+        VPIF_IF_BT1120,
+        VPIF_IF_RAW_BAYER
+};
+
+struct vpif_interface {
+        enum vpif_if_type if_type;
+        unsigned hd_pol:1;
+        unsigned vd_pol:1;
+        unsigned fid_pol:1;
+};
+
+struct vpif_subdev_info {
+        const char *name;
+        struct i2c_board_info board_info;
+        u32 input;
+        u32 output;
+        unsigned can_route:1;
+        struct vpif_interface vpif_if;
+};
+
+struct vpif_display_config {
+        int (*set_clock)(int, int);
+        struct vpif_subdev_info *subdevinfo;
+        int subdev_count;
+        const char **output;
+        int output_count;
+        const char *card_name;
+};
+
+struct vpif_input {
+        struct v4l2_input input;
+        const char *subdev_name;
+};
+
+#define VPIF_CAPTURE_MAX_CHANNELS       2
+
+struct vpif_capture_chan_config {
+        const struct vpif_input *inputs;
+        int input_count;
+};
+
+struct vpif_capture_config {
+        int (*setup_input_channel_mode)(int);
+        int (*setup_input_path)(int, const char *);
+        struct vpif_capture_chan_config chan_config[VPIF_CAPTURE_MAX_CHANNELS];
+        struct vpif_subdev_info *subdev_info;
+        int subdev_count;
+        const char *card_name;
+};
+
+void dm646x_setup_vpif(struct vpif_display_config *,
+                       struct vpif_capture_config *);
 
 #endif /* __ASM_ARCH_DM646X_H */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index 24a379239d7f..eb8bfd7925e7 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -139,6 +139,54 @@ struct edmacc_param {
 #define DAVINCI_DMA_PWM1                 53
 #define DAVINCI_DMA_PWM2                 54
 
+/* DA830 specific EDMA3 information */
+#define EDMA_DA830_NUM_DMACH            32
+#define EDMA_DA830_NUM_TCC              32
+#define EDMA_DA830_NUM_PARAMENTRY       128
+#define EDMA_DA830_NUM_EVQUE            2
+#define EDMA_DA830_NUM_TC               2
+#define EDMA_DA830_CHMAP_EXIST          0
+#define EDMA_DA830_NUM_REGIONS          4
+#define DA830_DMACH2EVENT_MAP0          0x000FC03Fu
+#define DA830_DMACH2EVENT_MAP1          0x00000000u
+#define DA830_EDMA_ARM_OWN              0x30FFCCFFu
+
+/* DA830 specific EDMA3 Events Information */
+enum DA830_edma_ch {
+        DA830_DMACH_MCASP0_RX,
+        DA830_DMACH_MCASP0_TX,
+        DA830_DMACH_MCASP1_RX,
+        DA830_DMACH_MCASP1_TX,
+        DA830_DMACH_MCASP2_RX,
+        DA830_DMACH_MCASP2_TX,
+        DA830_DMACH_GPIO_BNK0INT,
+        DA830_DMACH_GPIO_BNK1INT,
+        DA830_DMACH_UART0_RX,
+        DA830_DMACH_UART0_TX,
+        DA830_DMACH_TMR64P0_EVTOUT12,
+        DA830_DMACH_TMR64P0_EVTOUT34,
+        DA830_DMACH_UART1_RX,
+        DA830_DMACH_UART1_TX,
+        DA830_DMACH_SPI0_RX,
+        DA830_DMACH_SPI0_TX,
+        DA830_DMACH_MMCSD_RX,
+        DA830_DMACH_MMCSD_TX,
+        DA830_DMACH_SPI1_RX,
+        DA830_DMACH_SPI1_TX,
+        DA830_DMACH_DMAX_EVTOUT6,
+        DA830_DMACH_DMAX_EVTOUT7,
+        DA830_DMACH_GPIO_BNK2INT,
+        DA830_DMACH_GPIO_BNK3INT,
+        DA830_DMACH_I2C0_RX,
+        DA830_DMACH_I2C0_TX,
+        DA830_DMACH_I2C1_RX,
+        DA830_DMACH_I2C1_TX,
+        DA830_DMACH_GPIO_BNK4INT,
+        DA830_DMACH_GPIO_BNK5INT,
+        DA830_DMACH_UART2_RX,
+        DA830_DMACH_UART2_TX
+};
+
 /*ch_status paramater of callback function possible values*/
 #define DMA_COMPLETE 1
 #define DMA_CC_ERROR 2
@@ -162,6 +210,8 @@ enum fifo_width {
 enum dma_event_q {
         EVENTQ_0 = 0,
         EVENTQ_1 = 1,
+        EVENTQ_2 = 2,
+        EVENTQ_3 = 3,
         EVENTQ_DEFAULT = -1
 };
 
@@ -170,8 +220,15 @@ enum sync_dimension {
         ABSYNC = 1
 };
 
+#define EDMA_CTLR_CHAN(ctlr, chan)      (((ctlr) << 16) | (chan))
+#define EDMA_CTLR(i)                    ((i) >> 16)
+#define EDMA_CHAN_SLOT(i)               ((i) & 0xffff)
+
 #define EDMA_CHANNEL_ANY                -1      /* for edma_alloc_channel() */
 #define EDMA_SLOT_ANY                   -1      /* for edma_alloc_slot() */
+#define EDMA_CONT_PARAMS_ANY             1001
+#define EDMA_CONT_PARAMS_FIXED_EXACT     1002
+#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
 
 /* alloc/free DMA channels and their dedicated parameter RAM slots */
 int edma_alloc_channel(int channel,
@@ -180,9 +237,13 @@ int edma_alloc_channel(int channel,
 void edma_free_channel(unsigned channel);
 
 /* alloc/free parameter RAM slots */
-int edma_alloc_slot(int slot);
+int edma_alloc_slot(unsigned ctlr, int slot);
 void edma_free_slot(unsigned slot);
 
+/* alloc/free a set of contiguous parameter RAM slots */
+int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
+int edma_free_cont_slots(unsigned slot, int count);
+
 /* calls that operate on part of a parameter RAM slot */
 void edma_set_src(unsigned slot, dma_addr_t src_port,
                                 enum address_mode mode, enum fifo_width);
@@ -216,9 +277,13 @@ struct edma_soc_info {
         unsigned        n_region;
         unsigned        n_slot;
         unsigned        n_tc;
+        unsigned        n_cc;
+        enum dma_event_q        default_queue;
 
         /* list of channels with no even trigger; terminated by "-1" */
         const s8        *noevent;
+        const s8        (*queue_tc_mapping)[2];
+        const s8        (*queue_priority_mapping)[2];
 };
 
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index ae0745568316..f3b8ef878158 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -42,6 +42,9 @@
  */
 #define GPIO(X)         (X)             /* 0 <= X <= (DAVINCI_N_GPIO - 1) */
 
+/* Convert GPIO signal to GPIO pin number */
+#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio))
+
 struct gpio_controller {
         u32     dir;
         u32     out_data;
@@ -78,6 +81,8 @@ __gpio_to_controller(unsigned gpio)
                 ptr = base + 0x60;
         else if (gpio < 32 * 4)
                 ptr = base + 0x88;
+        else if (gpio < 32 * 5)
+                ptr = base + 0xb0;
         else
                 ptr = NULL;
         return ptr;
@@ -142,15 +147,13 @@ static inline int gpio_cansleep(unsigned gpio)
 
 static inline int gpio_to_irq(unsigned gpio)
 {
-        if (gpio >= DAVINCI_N_GPIO)
-                return -EINVAL;
-        return davinci_soc_info.intc_irq_num + gpio;
+        return __gpio_to_irq(gpio);
 }
 
 static inline int irq_to_gpio(unsigned irq)
 {
-        /* caller guarantees gpio_to_irq() succeeded */
-        return irq - davinci_soc_info.intc_irq_num;
+        /* don't support the reverse mapping */
+        return -ENOSYS;
 }
 
 #endif                          /* __DAVINCI_GPIO_H */
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index 48c77934d519..41c89386e39b 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -24,4 +24,21 @@
 /* System control register offsets */
 #define DM64XX_VDD3P3V_PWDN     0x48
 
+/*
+ * I/O mapping
+ */
+#define IO_PHYS                         0x01c00000
+#define IO_OFFSET                       0xfd000000 /* Virtual IO = 0xfec00000 */
+#define IO_SIZE                         0x00400000
+#define IO_VIRT                         (IO_PHYS + IO_OFFSET)
+#define io_v2p(va)                      ((va) - IO_OFFSET)
+#define __IO_ADDRESS(x)                 ((x) + IO_OFFSET)
+#define IO_ADDRESS(pa)                  IOMEM(__IO_ADDRESS(pa))
+
+#ifdef __ASSEMBLER__
+#define IOMEM(x)                        x
+#else
+#define IOMEM(x)                        ((void __force __iomem *)(x))
+#endif
+
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index 2479785405af..62b0a90309ad 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -14,18 +14,6 @@
 #define IO_SPACE_LIMIT 0xffffffff
 
 /*
- * ----------------------------------------------------------------------------
- * I/O mapping
- * ----------------------------------------------------------------------------
- */
-#define IO_PHYS         0x01c00000
-#define IO_OFFSET       0xfd000000 /* Virtual IO = 0xfec00000 */
-#define IO_SIZE         0x00400000
-#define IO_VIRT         (IO_PHYS + IO_OFFSET)
-#define io_v2p(va)      ((va) - IO_OFFSET)
-#define __IO_ADDRESS(x) ((x) + IO_OFFSET)
-
-/*
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
  */
@@ -33,19 +21,12 @@
 #define __mem_pci(a)            (a)
 #define __mem_isa(a)            (a)
 
-#define IO_ADDRESS(pa)          IOMEM(__IO_ADDRESS(pa))
-
-#ifdef __ASSEMBLER__
-#define IOMEM(x)                x
-#else
-#define IOMEM(x)                ((void __force __iomem *)(x))
-
+#ifndef __ASSEMBLER__
 #define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t)
 #define __arch_iounmap(v)       davinci_iounmap(v)
 
 void __iomem *davinci_ioremap(unsigned long phys, size_t size,
                               unsigned int type);
 void davinci_iounmap(volatile void __iomem *addr);
-
-#endif /* __ASSEMBLER__ */
+#endif
 #endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index bc5d6aaa69a3..3c918a772619 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -99,9 +99,6 @@
 #define IRQ_EMUINT       63
 
 #define DAVINCI_N_AINTC_IRQ     64
-#define DAVINCI_N_GPIO          104
-
-#define NR_IRQS                 (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO)
 
 #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
 
@@ -206,4 +203,206 @@
 #define IRQ_DM355_GPIOBNK5      59
 #define IRQ_DM355_GPIOBNK6      60
 
+/* DaVinci DM365-specific Interrupts */
+#define IRQ_DM365_INSFINT       7
+#define IRQ_DM365_IMXINT1       8
+#define IRQ_DM365_IMXINT0       10
+#define IRQ_DM365_KLD_ARMINT    10
+#define IRQ_DM365_IMCOPINT      11
+#define IRQ_DM365_RTOINT        13
+#define IRQ_DM365_TINT5         14
+#define IRQ_DM365_TINT6         15
+#define IRQ_DM365_SPINT2_1      21
+#define IRQ_DM365_TINT7         22
+#define IRQ_DM365_SDIOINT0      23
+#define IRQ_DM365_MMCINT1       27
+#define IRQ_DM365_PWMINT3       28
+#define IRQ_DM365_SDIOINT1      31
+#define IRQ_DM365_SPIINT0_0     42
+#define IRQ_DM365_SPIINT3_0     43
+#define IRQ_DM365_GPIO0         44
+#define IRQ_DM365_GPIO1         45
+#define IRQ_DM365_GPIO2         46
+#define IRQ_DM365_GPIO3         47
+#define IRQ_DM365_GPIO4         48
+#define IRQ_DM365_GPIO5         49
+#define IRQ_DM365_GPIO6         50
+#define IRQ_DM365_GPIO7         51
+#define IRQ_DM365_EMAC_RXTHRESH 52
+#define IRQ_DM365_EMAC_RXPULSE  53
+#define IRQ_DM365_EMAC_TXPULSE  54
+#define IRQ_DM365_EMAC_MISCPULSE 55
+#define IRQ_DM365_GPIO12        56
+#define IRQ_DM365_GPIO13        57
+#define IRQ_DM365_GPIO14        58
+#define IRQ_DM365_GPIO15        59
+#define IRQ_DM365_ADCINT        59
+#define IRQ_DM365_KEYINT        60
+#define IRQ_DM365_TCERRINT2     61
+#define IRQ_DM365_TCERRINT3     62
+#define IRQ_DM365_EMUINT        63
+
+/* DA8XX interrupts */
+#define IRQ_DA8XX_COMMTX                0
+#define IRQ_DA8XX_COMMRX                1
+#define IRQ_DA8XX_NINT                  2
+#define IRQ_DA8XX_EVTOUT0               3
+#define IRQ_DA8XX_EVTOUT1               4
+#define IRQ_DA8XX_EVTOUT2               5
+#define IRQ_DA8XX_EVTOUT3               6
+#define IRQ_DA8XX_EVTOUT4               7
+#define IRQ_DA8XX_EVTOUT5               8
+#define IRQ_DA8XX_EVTOUT6               9
+#define IRQ_DA8XX_EVTOUT7               10
+#define IRQ_DA8XX_CCINT0                11
+#define IRQ_DA8XX_CCERRINT              12
+#define IRQ_DA8XX_TCERRINT0             13
+#define IRQ_DA8XX_AEMIFINT              14
+#define IRQ_DA8XX_I2CINT0               15
+#define IRQ_DA8XX_MMCSDINT0             16
+#define IRQ_DA8XX_MMCSDINT1             17
+#define IRQ_DA8XX_ALLINT0               18
+#define IRQ_DA8XX_RTC                   19
+#define IRQ_DA8XX_SPINT0                20
+#define IRQ_DA8XX_TINT12_0              21
+#define IRQ_DA8XX_TINT34_0              22
+#define IRQ_DA8XX_TINT12_1              23
+#define IRQ_DA8XX_TINT34_1              24
+#define IRQ_DA8XX_UARTINT0              25
+#define IRQ_DA8XX_KEYMGRINT             26
+#define IRQ_DA8XX_SECINT                26
+#define IRQ_DA8XX_SECKEYERR             26
+#define IRQ_DA8XX_CHIPINT0              28
+#define IRQ_DA8XX_CHIPINT1              29
+#define IRQ_DA8XX_CHIPINT2              30
+#define IRQ_DA8XX_CHIPINT3              31
+#define IRQ_DA8XX_TCERRINT1             32
+#define IRQ_DA8XX_C0_RX_THRESH_PULSE    33
+#define IRQ_DA8XX_C0_RX_PULSE           34
+#define IRQ_DA8XX_C0_TX_PULSE           35
+#define IRQ_DA8XX_C0_MISC_PULSE         36
+#define IRQ_DA8XX_C1_RX_THRESH_PULSE    37
+#define IRQ_DA8XX_C1_RX_PULSE           38
+#define IRQ_DA8XX_C1_TX_PULSE           39
+#define IRQ_DA8XX_C1_MISC_PULSE         40
+#define IRQ_DA8XX_MEMERR                41
+#define IRQ_DA8XX_GPIO0                 42
+#define IRQ_DA8XX_GPIO1                 43
+#define IRQ_DA8XX_GPIO2                 44
+#define IRQ_DA8XX_GPIO3                 45
+#define IRQ_DA8XX_GPIO4                 46
+#define IRQ_DA8XX_GPIO5                 47
+#define IRQ_DA8XX_GPIO6                 48
+#define IRQ_DA8XX_GPIO7                 49
+#define IRQ_DA8XX_GPIO8                 50
+#define IRQ_DA8XX_I2CINT1               51
+#define IRQ_DA8XX_LCDINT                52
+#define IRQ_DA8XX_UARTINT1              53
+#define IRQ_DA8XX_MCASPINT              54
+#define IRQ_DA8XX_ALLINT1               55
+#define IRQ_DA8XX_SPINT1                56
+#define IRQ_DA8XX_UHPI_INT1             57
+#define IRQ_DA8XX_USB_INT               58
+#define IRQ_DA8XX_IRQN                  59
+#define IRQ_DA8XX_RWAKEUP               60
+#define IRQ_DA8XX_UARTINT2              61
+#define IRQ_DA8XX_DFTSSINT              62
+#define IRQ_DA8XX_EHRPWM0               63
+#define IRQ_DA8XX_EHRPWM0TZ             64
+#define IRQ_DA8XX_EHRPWM1               65
+#define IRQ_DA8XX_EHRPWM1TZ             66
+#define IRQ_DA8XX_ECAP0                 69
+#define IRQ_DA8XX_ECAP1                 70
+#define IRQ_DA8XX_ECAP2                 71
+#define IRQ_DA8XX_ARMCLKSTOPREQ         90
+
+/* DA830 specific interrupts */
+#define IRQ_DA830_MPUERR                27
+#define IRQ_DA830_IOPUERR               27
+#define IRQ_DA830_BOOTCFGERR            27
+#define IRQ_DA830_EHRPWM2               67
+#define IRQ_DA830_EHRPWM2TZ             68
+#define IRQ_DA830_EQEP0                 72
+#define IRQ_DA830_EQEP1                 73
+#define IRQ_DA830_T12CMPINT0_0          74
+#define IRQ_DA830_T12CMPINT1_0          75
+#define IRQ_DA830_T12CMPINT2_0          76
+#define IRQ_DA830_T12CMPINT3_0          77
+#define IRQ_DA830_T12CMPINT4_0          78
+#define IRQ_DA830_T12CMPINT5_0          79
+#define IRQ_DA830_T12CMPINT6_0          80
+#define IRQ_DA830_T12CMPINT7_0          81
+#define IRQ_DA830_T12CMPINT0_1          82
+#define IRQ_DA830_T12CMPINT1_1          83
+#define IRQ_DA830_T12CMPINT2_1          84
+#define IRQ_DA830_T12CMPINT3_1          85
+#define IRQ_DA830_T12CMPINT4_1          86
+#define IRQ_DA830_T12CMPINT5_1          87
+#define IRQ_DA830_T12CMPINT6_1          88
+#define IRQ_DA830_T12CMPINT7_1          89
+
+#define DA830_N_CP_INTC_IRQ             96
+
+/* DA850 speicific interrupts */
+#define IRQ_DA850_MPUADDRERR0           27
+#define IRQ_DA850_MPUPROTERR0           27
+#define IRQ_DA850_IOPUADDRERR0          27
+#define IRQ_DA850_IOPUPROTERR0          27
+#define IRQ_DA850_IOPUADDRERR1          27
+#define IRQ_DA850_IOPUPROTERR1          27
+#define IRQ_DA850_IOPUADDRERR2          27
+#define IRQ_DA850_IOPUPROTERR2          27
+#define IRQ_DA850_BOOTCFG_ADDR_ERR      27
+#define IRQ_DA850_BOOTCFG_PROT_ERR      27
+#define IRQ_DA850_MPUADDRERR1           27
+#define IRQ_DA850_MPUPROTERR1           27
+#define IRQ_DA850_IOPUADDRERR3          27
+#define IRQ_DA850_IOPUPROTERR3          27
+#define IRQ_DA850_IOPUADDRERR4          27
+#define IRQ_DA850_IOPUPROTERR4          27
+#define IRQ_DA850_IOPUADDRERR5          27
+#define IRQ_DA850_IOPUPROTERR5          27
+#define IRQ_DA850_MIOPU_BOOTCFG_ERR     27
+#define IRQ_DA850_SATAINT               67
+#define IRQ_DA850_TINT12_2              68
+#define IRQ_DA850_TINT34_2              68
+#define IRQ_DA850_TINTALL_2             68
+#define IRQ_DA850_MMCSDINT0_1           72
+#define IRQ_DA850_MMCSDINT1_1           73
+#define IRQ_DA850_T12CMPINT0_2          74
+#define IRQ_DA850_T12CMPINT1_2          75
+#define IRQ_DA850_T12CMPINT2_2          76
+#define IRQ_DA850_T12CMPINT3_2          77
+#define IRQ_DA850_T12CMPINT4_2          78
+#define IRQ_DA850_T12CMPINT5_2          79
+#define IRQ_DA850_T12CMPINT6_2          80
+#define IRQ_DA850_T12CMPINT7_2          81
+#define IRQ_DA850_T12CMPINT0_3          82
+#define IRQ_DA850_T12CMPINT1_3          83
+#define IRQ_DA850_T12CMPINT2_3          84
+#define IRQ_DA850_T12CMPINT3_3          85
+#define IRQ_DA850_T12CMPINT4_3          86
+#define IRQ_DA850_T12CMPINT5_3          87
+#define IRQ_DA850_T12CMPINT6_3          88
+#define IRQ_DA850_T12CMPINT7_3          89
+#define IRQ_DA850_RPIINT                91
+#define IRQ_DA850_VPIFINT               92
+#define IRQ_DA850_CCINT1                93
+#define IRQ_DA850_CCERRINT1             94
+#define IRQ_DA850_TCERRINT2             95
+#define IRQ_DA850_TINT12_3              96
+#define IRQ_DA850_TINT34_3              96
+#define IRQ_DA850_TINTALL_3             96
+#define IRQ_DA850_MCBSP0RINT            97
+#define IRQ_DA850_MCBSP0XINT            98
+#define IRQ_DA850_MCBSP1RINT            99
+#define IRQ_DA850_MCBSP1XINT            100
+
+#define DA850_N_CP_INTC_IRQ             101
+
+/* da850 currently has the most gpio pins (144) */
+#define DAVINCI_N_GPIO                  144
+/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
+#define NR_IRQS                         (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO)
+
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index c712c7cdf38f..80309aed534a 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -20,9 +20,16 @@
 /**************************************************************************
  * Definitions
  **************************************************************************/
-#define DAVINCI_DDR_BASE    0x80000000
+#define DAVINCI_DDR_BASE        0x80000000
+#define DA8XX_DDR_BASE          0xc0000000
 
+#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
+#error Cannot enable DaVinci and DA8XX platforms concurrently
+#elif defined(CONFIG_ARCH_DAVINCI_DA8XX)
+#define PHYS_OFFSET DA8XX_DDR_BASE
+#else
 #define PHYS_OFFSET DAVINCI_DDR_BASE
+#endif
 
 /*
  * Increase size of DMA-consistent memory region
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 27378458542f..bb84893a4e83 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -154,6 +154,737 @@ enum davinci_dm355_index {
         DM355_EVT8_ASP1_TX,
         DM355_EVT9_ASP1_RX,
         DM355_EVT26_MMC0_RX,
+
+        /* Video Out */
+        DM355_VOUT_FIELD,
+        DM355_VOUT_FIELD_G70,
+        DM355_VOUT_HVSYNC,
+        DM355_VOUT_COUTL_EN,
+        DM355_VOUT_COUTH_EN,
+
+        /* Video In Pin Mux */
+        DM355_VIN_PCLK,
+        DM355_VIN_CAM_WEN,
+        DM355_VIN_CAM_VD,
+        DM355_VIN_CAM_HD,
+        DM355_VIN_YIN_EN,
+        DM355_VIN_CINL_EN,
+        DM355_VIN_CINH_EN,
+};
+
+enum davinci_dm365_index {
+        /* MMC/SD 0 */
+        DM365_MMCSD0,
+
+        /* MMC/SD 1 */
+        DM365_SD1_CLK,
+        DM365_SD1_CMD,
+        DM365_SD1_DATA3,
+        DM365_SD1_DATA2,
+        DM365_SD1_DATA1,
+        DM365_SD1_DATA0,
+
+        /* I2C */
+        DM365_I2C_SDA,
+        DM365_I2C_SCL,
+
+        /* AEMIF */
+        DM365_AEMIF_AR,
+        DM365_AEMIF_A3,
+        DM365_AEMIF_A7,
+        DM365_AEMIF_D15_8,
+        DM365_AEMIF_CE0,
+
+        /* ASP0 function */
+        DM365_MCBSP0_BDX,
+        DM365_MCBSP0_X,
+        DM365_MCBSP0_BFSX,
+        DM365_MCBSP0_BDR,
+        DM365_MCBSP0_R,
+        DM365_MCBSP0_BFSR,
+
+        /* SPI0 */
+        DM365_SPI0_SCLK,
+        DM365_SPI0_SDI,
+        DM365_SPI0_SDO,
+        DM365_SPI0_SDENA0,
+        DM365_SPI0_SDENA1,
+
+        /* UART */
+        DM365_UART0_RXD,
+        DM365_UART0_TXD,
+        DM365_UART1_RXD,
+        DM365_UART1_TXD,
+        DM365_UART1_RTS,
+        DM365_UART1_CTS,
+
+        /* EMAC */
+        DM365_EMAC_TX_EN,
+        DM365_EMAC_TX_CLK,
+        DM365_EMAC_COL,
+        DM365_EMAC_TXD3,
+        DM365_EMAC_TXD2,
+        DM365_EMAC_TXD1,
+        DM365_EMAC_TXD0,
+        DM365_EMAC_RXD3,
+        DM365_EMAC_RXD2,
+        DM365_EMAC_RXD1,
+        DM365_EMAC_RXD0,
+        DM365_EMAC_RX_CLK,
+        DM365_EMAC_RX_DV,
+        DM365_EMAC_RX_ER,
+        DM365_EMAC_CRS,
+        DM365_EMAC_MDIO,
+        DM365_EMAC_MDCLK,
+
+        /* Keypad */
+        DM365_KEYPAD,
+
+        /* PWM */
+        DM365_PWM0,
+        DM365_PWM0_G23,
+        DM365_PWM1,
+        DM365_PWM1_G25,
+        DM365_PWM2_G87,
+        DM365_PWM2_G88,
+        DM365_PWM2_G89,
+        DM365_PWM2_G90,
+        DM365_PWM3_G80,
+        DM365_PWM3_G81,
+        DM365_PWM3_G85,
+        DM365_PWM3_G86,
+
+        /* SPI1 */
+        DM365_SPI1_SCLK,
+        DM365_SPI1_SDO,
+        DM365_SPI1_SDI,
+        DM365_SPI1_SDENA0,
+        DM365_SPI1_SDENA1,
+
+        /* SPI2 */
+        DM365_SPI2_SCLK,
+        DM365_SPI2_SDO,
+        DM365_SPI2_SDI,
+        DM365_SPI2_SDENA0,
+        DM365_SPI2_SDENA1,
+
+        /* SPI3 */
+        DM365_SPI3_SCLK,
+        DM365_SPI3_SDO,
+        DM365_SPI3_SDI,
+        DM365_SPI3_SDENA0,
+        DM365_SPI3_SDENA1,
+
+        /* SPI4 */
+        DM365_SPI4_SCLK,
+        DM365_SPI4_SDO,
+        DM365_SPI4_SDI,
+        DM365_SPI4_SDENA0,
+        DM365_SPI4_SDENA1,
+
+        /* GPIO */
+        DM365_GPIO20,
+        DM365_GPIO33,
+        DM365_GPIO40,
+
+        /* Video */
+        DM365_VOUT_FIELD,
+        DM365_VOUT_FIELD_G81,
+        DM365_VOUT_HVSYNC,
+        DM365_VOUT_COUTL_EN,
+        DM365_VOUT_COUTH_EN,
+        DM365_VIN_CAM_WEN,
+        DM365_VIN_CAM_VD,
+        DM365_VIN_CAM_HD,
+        DM365_VIN_YIN4_7_EN,
+        DM365_VIN_YIN0_3_EN,
+
+        /* IRQ muxing */
+        DM365_INT_EDMA_CC,
+        DM365_INT_EDMA_TC0_ERR,
+        DM365_INT_EDMA_TC1_ERR,
+        DM365_INT_EDMA_TC2_ERR,
+        DM365_INT_EDMA_TC3_ERR,
+        DM365_INT_PRTCSS,
+        DM365_INT_EMAC_RXTHRESH,
+        DM365_INT_EMAC_RXPULSE,
+        DM365_INT_EMAC_TXPULSE,
+        DM365_INT_EMAC_MISCPULSE,
+        DM365_INT_IMX0_ENABLE,
+        DM365_INT_IMX0_DISABLE,
+        DM365_INT_HDVICP_ENABLE,
+        DM365_INT_HDVICP_DISABLE,
+        DM365_INT_IMX1_ENABLE,
+        DM365_INT_IMX1_DISABLE,
+        DM365_INT_NSF_ENABLE,
+        DM365_INT_NSF_DISABLE,
+
+        /* EDMA event muxing */
+        DM365_EVT2_ASP_TX,
+        DM365_EVT3_ASP_RX,
+        DM365_EVT26_MMC0_RX,
+};
+
+enum da830_index {
+        DA830_GPIO7_14,
+        DA830_RTCK,
+        DA830_GPIO7_15,
+        DA830_EMU_0,
+        DA830_EMB_SDCKE,
+        DA830_EMB_CLK_GLUE,
+        DA830_EMB_CLK,
+        DA830_NEMB_CS_0,
+        DA830_NEMB_CAS,
+        DA830_NEMB_RAS,
+        DA830_NEMB_WE,
+        DA830_EMB_BA_1,
+        DA830_EMB_BA_0,
+        DA830_EMB_A_0,
+        DA830_EMB_A_1,
+        DA830_EMB_A_2,
+        DA830_EMB_A_3,
+        DA830_EMB_A_4,
+        DA830_EMB_A_5,
+        DA830_GPIO7_0,
+        DA830_GPIO7_1,
+        DA830_GPIO7_2,
+        DA830_GPIO7_3,
+        DA830_GPIO7_4,
+        DA830_GPIO7_5,
+        DA830_GPIO7_6,
+        DA830_GPIO7_7,
+        DA830_EMB_A_6,
+        DA830_EMB_A_7,
+        DA830_EMB_A_8,
+        DA830_EMB_A_9,
+        DA830_EMB_A_10,
+        DA830_EMB_A_11,
+        DA830_EMB_A_12,
+        DA830_EMB_D_31,
+        DA830_GPIO7_8,
+        DA830_GPIO7_9,
+        DA830_GPIO7_10,
+        DA830_GPIO7_11,
+        DA830_GPIO7_12,
+        DA830_GPIO7_13,
+        DA830_GPIO3_13,
+        DA830_EMB_D_30,
+        DA830_EMB_D_29,
+        DA830_EMB_D_28,
+        DA830_EMB_D_27,
+        DA830_EMB_D_26,
+        DA830_EMB_D_25,
+        DA830_EMB_D_24,
+        DA830_EMB_D_23,
+        DA830_EMB_D_22,
+        DA830_EMB_D_21,
+        DA830_EMB_D_20,
+        DA830_EMB_D_19,
+        DA830_EMB_D_18,
+        DA830_EMB_D_17,
+        DA830_EMB_D_16,
+        DA830_NEMB_WE_DQM_3,
+        DA830_NEMB_WE_DQM_2,
+        DA830_EMB_D_0,
+        DA830_EMB_D_1,
+        DA830_EMB_D_2,
+        DA830_EMB_D_3,
+        DA830_EMB_D_4,
+        DA830_EMB_D_5,
+        DA830_EMB_D_6,
+        DA830_GPIO6_0,
+        DA830_GPIO6_1,
+        DA830_GPIO6_2,
+        DA830_GPIO6_3,
+        DA830_GPIO6_4,
+        DA830_GPIO6_5,
+        DA830_GPIO6_6,
+        DA830_EMB_D_7,
+        DA830_EMB_D_8,
+        DA830_EMB_D_9,
+        DA830_EMB_D_10,
+        DA830_EMB_D_11,
+        DA830_EMB_D_12,
+        DA830_EMB_D_13,
+        DA830_EMB_D_14,
+        DA830_GPIO6_7,
+        DA830_GPIO6_8,
+        DA830_GPIO6_9,
+        DA830_GPIO6_10,
+        DA830_GPIO6_11,
+        DA830_GPIO6_12,
+        DA830_GPIO6_13,
+        DA830_GPIO6_14,
+        DA830_EMB_D_15,
+        DA830_NEMB_WE_DQM_1,
+        DA830_NEMB_WE_DQM_0,
+        DA830_SPI0_SOMI_0,
+        DA830_SPI0_SIMO_0,
+        DA830_SPI0_CLK,
+        DA830_NSPI0_ENA,
+        DA830_NSPI0_SCS_0,
+        DA830_EQEP0I,
+        DA830_EQEP0S,
+        DA830_EQEP1I,
+        DA830_NUART0_CTS,
+        DA830_NUART0_RTS,
+        DA830_EQEP0A,
+        DA830_EQEP0B,
+        DA830_GPIO6_15,
+        DA830_GPIO5_14,
+        DA830_GPIO5_15,
+        DA830_GPIO5_0,
+        DA830_GPIO5_1,
+        DA830_GPIO5_2,
+        DA830_GPIO5_3,
+        DA830_GPIO5_4,
+        DA830_SPI1_SOMI_0,
+        DA830_SPI1_SIMO_0,
+        DA830_SPI1_CLK,
+        DA830_UART0_RXD,
+        DA830_UART0_TXD,
+        DA830_AXR1_10,
+        DA830_AXR1_11,
+        DA830_NSPI1_ENA,
+        DA830_I2C1_SCL,
+        DA830_I2C1_SDA,
+        DA830_EQEP1S,
+        DA830_I2C0_SDA,
+        DA830_I2C0_SCL,
+        DA830_UART2_RXD,
+        DA830_TM64P0_IN12,
+        DA830_TM64P0_OUT12,
+        DA830_GPIO5_5,
+        DA830_GPIO5_6,
+        DA830_GPIO5_7,
+        DA830_GPIO5_8,
+        DA830_GPIO5_9,
+        DA830_GPIO5_10,
+        DA830_GPIO5_11,
+        DA830_GPIO5_12,
+        DA830_NSPI1_SCS_0,
+        DA830_USB0_DRVVBUS,
+        DA830_AHCLKX0,
+        DA830_ACLKX0,
+        DA830_AFSX0,
+        DA830_AHCLKR0,
+        DA830_ACLKR0,
+        DA830_AFSR0,
+        DA830_UART2_TXD,
+        DA830_AHCLKX2,
+        DA830_ECAP0_APWM0,
+        DA830_RMII_MHZ_50_CLK,
+        DA830_ECAP1_APWM1,
+        DA830_USB_REFCLKIN,
+        DA830_GPIO5_13,
+        DA830_GPIO4_15,
+        DA830_GPIO2_11,
+        DA830_GPIO2_12,
+        DA830_GPIO2_13,
+        DA830_GPIO2_14,
+        DA830_GPIO2_15,
+        DA830_GPIO3_12,
+        DA830_AMUTE0,
+        DA830_AXR0_0,
+        DA830_AXR0_1,
+        DA830_AXR0_2,
+        DA830_AXR0_3,
+        DA830_AXR0_4,
+        DA830_AXR0_5,
+        DA830_AXR0_6,
+        DA830_RMII_TXD_0,
+        DA830_RMII_TXD_1,
+        DA830_RMII_TXEN,
+        DA830_RMII_CRS_DV,
+        DA830_RMII_RXD_0,
+        DA830_RMII_RXD_1,
+        DA830_RMII_RXER,
+        DA830_AFSR2,
+        DA830_ACLKX2,
+        DA830_AXR2_3,
+        DA830_AXR2_2,
+        DA830_AXR2_1,
+        DA830_AFSX2,
+        DA830_ACLKR2,
+        DA830_NRESETOUT,
+        DA830_GPIO3_0,
+        DA830_GPIO3_1,
+        DA830_GPIO3_2,
+        DA830_GPIO3_3,
+        DA830_GPIO3_4,
+        DA830_GPIO3_5,
+        DA830_GPIO3_6,
+        DA830_AXR0_7,
+        DA830_AXR0_8,
+        DA830_UART1_RXD,
+        DA830_UART1_TXD,
+        DA830_AXR0_11,
+        DA830_AHCLKX1,
+        DA830_ACLKX1,
+        DA830_AFSX1,
+        DA830_MDIO_CLK,
+        DA830_MDIO_D,
+        DA830_AXR0_9,
+        DA830_AXR0_10,
+        DA830_EPWM0B,
+        DA830_EPWM0A,
+        DA830_EPWMSYNCI,
+        DA830_AXR2_0,
+        DA830_EPWMSYNC0,
+        DA830_GPIO3_7,
+        DA830_GPIO3_8,
+        DA830_GPIO3_9,
+        DA830_GPIO3_10,
+        DA830_GPIO3_11,
+        DA830_GPIO3_14,
+        DA830_GPIO3_15,
+        DA830_GPIO4_10,
+        DA830_AHCLKR1,
+        DA830_ACLKR1,
+        DA830_AFSR1,
+        DA830_AMUTE1,
+        DA830_AXR1_0,
+        DA830_AXR1_1,
+        DA830_AXR1_2,
+        DA830_AXR1_3,
+        DA830_ECAP2_APWM2,
+        DA830_EHRPWMGLUETZ,
+        DA830_EQEP1A,
+        DA830_GPIO4_11,
+        DA830_GPIO4_12,
+        DA830_GPIO4_13,
+        DA830_GPIO4_14,
+        DA830_GPIO4_0,
+        DA830_GPIO4_1,
+        DA830_GPIO4_2,
+        DA830_GPIO4_3,
+        DA830_AXR1_4,
+        DA830_AXR1_5,
+        DA830_AXR1_6,
+        DA830_AXR1_7,
+        DA830_AXR1_8,
+        DA830_AXR1_9,
+        DA830_EMA_D_0,
+        DA830_EMA_D_1,
+        DA830_EQEP1B,
+        DA830_EPWM2B,
+        DA830_EPWM2A,
+        DA830_EPWM1B,
+        DA830_EPWM1A,
+        DA830_MMCSD_DAT_0,
+        DA830_MMCSD_DAT_1,
+        DA830_UHPI_HD_0,
+        DA830_UHPI_HD_1,
+        DA830_GPIO4_4,
+        DA830_GPIO4_5,
+        DA830_GPIO4_6,
+        DA830_GPIO4_7,
+        DA830_GPIO4_8,
+        DA830_GPIO4_9,
+        DA830_GPIO0_0,
+        DA830_GPIO0_1,
+        DA830_EMA_D_2,
+        DA830_EMA_D_3,
+        DA830_EMA_D_4,
+        DA830_EMA_D_5,
+        DA830_EMA_D_6,
+        DA830_EMA_D_7,
+        DA830_EMA_D_8,
+        DA830_EMA_D_9,
+        DA830_MMCSD_DAT_2,
+        DA830_MMCSD_DAT_3,
+        DA830_MMCSD_DAT_4,
+        DA830_MMCSD_DAT_5,
+        DA830_MMCSD_DAT_6,
+        DA830_MMCSD_DAT_7,
+        DA830_UHPI_HD_8,
+        DA830_UHPI_HD_9,
+        DA830_UHPI_HD_2,
+        DA830_UHPI_HD_3,
+        DA830_UHPI_HD_4,
+        DA830_UHPI_HD_5,
+        DA830_UHPI_HD_6,
+        DA830_UHPI_HD_7,
+        DA830_LCD_D_8,
+        DA830_LCD_D_9,
+        DA830_GPIO0_2,
+        DA830_GPIO0_3,
+        DA830_GPIO0_4,
+        DA830_GPIO0_5,
+        DA830_GPIO0_6,
+        DA830_GPIO0_7,
+        DA830_GPIO0_8,
+        DA830_GPIO0_9,
+        DA830_EMA_D_10,
+        DA830_EMA_D_11,
+        DA830_EMA_D_12,
+        DA830_EMA_D_13,
+        DA830_EMA_D_14,
+        DA830_EMA_D_15,
+        DA830_EMA_A_0,
+        DA830_EMA_A_1,
+        DA830_UHPI_HD_10,
+        DA830_UHPI_HD_11,
+        DA830_UHPI_HD_12,
+        DA830_UHPI_HD_13,
+        DA830_UHPI_HD_14,
+        DA830_UHPI_HD_15,
+        DA830_LCD_D_7,
+        DA830_MMCSD_CLK,
+        DA830_LCD_D_10,
+        DA830_LCD_D_11,
+        DA830_LCD_D_12,
+        DA830_LCD_D_13,
+        DA830_LCD_D_14,
+        DA830_LCD_D_15,
+        DA830_UHPI_HCNTL0,
+        DA830_GPIO0_10,
+        DA830_GPIO0_11,
+        DA830_GPIO0_12,
+        DA830_GPIO0_13,
+        DA830_GPIO0_14,
+        DA830_GPIO0_15,
+        DA830_GPIO1_0,
+        DA830_GPIO1_1,
+        DA830_EMA_A_2,
+        DA830_EMA_A_3,
+        DA830_EMA_A_4,
+        DA830_EMA_A_5,
+        DA830_EMA_A_6,
+        DA830_EMA_A_7,
+        DA830_EMA_A_8,
+        DA830_EMA_A_9,
+        DA830_MMCSD_CMD,
+        DA830_LCD_D_6,
+        DA830_LCD_D_3,
+        DA830_LCD_D_2,
+        DA830_LCD_D_1,
+        DA830_LCD_D_0,
+        DA830_LCD_PCLK,
+        DA830_LCD_HSYNC,
+        DA830_UHPI_HCNTL1,
+        DA830_GPIO1_2,
+        DA830_GPIO1_3,
+        DA830_GPIO1_4,
+        DA830_GPIO1_5,
+        DA830_GPIO1_6,
+        DA830_GPIO1_7,
+        DA830_GPIO1_8,
+        DA830_GPIO1_9,
+        DA830_EMA_A_10,
+        DA830_EMA_A_11,
+        DA830_EMA_A_12,
+        DA830_EMA_BA_1,
+        DA830_EMA_BA_0,
+        DA830_EMA_CLK,
+        DA830_EMA_SDCKE,
+        DA830_NEMA_CAS,
+        DA830_LCD_VSYNC,
+        DA830_NLCD_AC_ENB_CS,
+        DA830_LCD_MCLK,
+        DA830_LCD_D_5,
+        DA830_LCD_D_4,
+        DA830_OBSCLK,
+        DA830_NEMA_CS_4,
+        DA830_UHPI_HHWIL,
+        DA830_AHCLKR2,
+        DA830_GPIO1_10,
+        DA830_GPIO1_11,
+        DA830_GPIO1_12,
+        DA830_GPIO1_13,
+        DA830_GPIO1_14,
+        DA830_GPIO1_15,
+        DA830_GPIO2_0,
+        DA830_GPIO2_1,
+        DA830_NEMA_RAS,
+        DA830_NEMA_WE,
+        DA830_NEMA_CS_0,
+        DA830_NEMA_CS_2,
+        DA830_NEMA_CS_3,
+        DA830_NEMA_OE,
+        DA830_NEMA_WE_DQM_1,
+        DA830_NEMA_WE_DQM_0,
+        DA830_NEMA_CS_5,
+        DA830_UHPI_HRNW,
+        DA830_NUHPI_HAS,
+        DA830_NUHPI_HCS,
+        DA830_NUHPI_HDS1,
+        DA830_NUHPI_HDS2,
+        DA830_NUHPI_HINT,
+        DA830_AXR0_12,
+        DA830_AMUTE2,
+        DA830_AXR0_13,
+        DA830_AXR0_14,
+        DA830_AXR0_15,
+        DA830_GPIO2_2,
+        DA830_GPIO2_3,
+        DA830_GPIO2_4,
+        DA830_GPIO2_5,
+        DA830_GPIO2_6,
+        DA830_GPIO2_7,
+        DA830_GPIO2_8,
+        DA830_GPIO2_9,
+        DA830_EMA_WAIT_0,
+        DA830_NUHPI_HRDY,
+        DA830_GPIO2_10,
+};
+
+enum davinci_da850_index {
+        /* UART0 function */
+        DA850_NUART0_CTS,
+        DA850_NUART0_RTS,
+        DA850_UART0_RXD,
+        DA850_UART0_TXD,
+
+        /* UART1 function */
+        DA850_NUART1_CTS,
+        DA850_NUART1_RTS,
+        DA850_UART1_RXD,
+        DA850_UART1_TXD,
+
+        /* UART2 function */
+        DA850_NUART2_CTS,
+        DA850_NUART2_RTS,
+        DA850_UART2_RXD,
+        DA850_UART2_TXD,
+
+        /* I2C1 function */
+        DA850_I2C1_SCL,
+        DA850_I2C1_SDA,
+
+        /* I2C0 function */
+        DA850_I2C0_SDA,
+        DA850_I2C0_SCL,
+
+        /* EMAC function */
+        DA850_MII_TXEN,
+        DA850_MII_TXCLK,
+        DA850_MII_COL,
+        DA850_MII_TXD_3,
+        DA850_MII_TXD_2,
+        DA850_MII_TXD_1,
+        DA850_MII_TXD_0,
+        DA850_MII_RXER,
+        DA850_MII_CRS,
+        DA850_MII_RXCLK,
+        DA850_MII_RXDV,
+        DA850_MII_RXD_3,
+        DA850_MII_RXD_2,
+        DA850_MII_RXD_1,
+        DA850_MII_RXD_0,
+        DA850_MDIO_CLK,
+        DA850_MDIO_D,
+
+        /* McASP function */
+        DA850_ACLKR,
+        DA850_ACLKX,
+        DA850_AFSR,
+        DA850_AFSX,
+        DA850_AHCLKR,
+        DA850_AHCLKX,
+        DA850_AMUTE,
+        DA850_AXR_15,
+        DA850_AXR_14,
+        DA850_AXR_13,
+        DA850_AXR_12,
+        DA850_AXR_11,
+        DA850_AXR_10,
+        DA850_AXR_9,
+        DA850_AXR_8,
+        DA850_AXR_7,
+        DA850_AXR_6,
+        DA850_AXR_5,
+        DA850_AXR_4,
+        DA850_AXR_3,
+        DA850_AXR_2,
+        DA850_AXR_1,
+        DA850_AXR_0,
+
+        /* LCD function */
+        DA850_LCD_D_7,
+        DA850_LCD_D_6,
+        DA850_LCD_D_5,
+        DA850_LCD_D_4,
+        DA850_LCD_D_3,
+        DA850_LCD_D_2,
+        DA850_LCD_D_1,
+        DA850_LCD_D_0,
+        DA850_LCD_D_15,
+        DA850_LCD_D_14,
+        DA850_LCD_D_13,
+        DA850_LCD_D_12,
+        DA850_LCD_D_11,
+        DA850_LCD_D_10,
+        DA850_LCD_D_9,
+        DA850_LCD_D_8,
+        DA850_LCD_PCLK,
+        DA850_LCD_HSYNC,
+        DA850_LCD_VSYNC,
+        DA850_NLCD_AC_ENB_CS,
+
+        /* MMC/SD0 function */
+        DA850_MMCSD0_DAT_0,
+        DA850_MMCSD0_DAT_1,
+        DA850_MMCSD0_DAT_2,
+        DA850_MMCSD0_DAT_3,
+        DA850_MMCSD0_CLK,
+        DA850_MMCSD0_CMD,
+
+        /* EMIF2.5/EMIFA function */
+        DA850_EMA_D_7,
+        DA850_EMA_D_6,
+        DA850_EMA_D_5,
+        DA850_EMA_D_4,
+        DA850_EMA_D_3,
+        DA850_EMA_D_2,
+        DA850_EMA_D_1,
+        DA850_EMA_D_0,
+        DA850_EMA_A_1,
+        DA850_EMA_A_2,
+        DA850_NEMA_CS_3,
+        DA850_NEMA_CS_4,
+        DA850_NEMA_WE,
+        DA850_NEMA_OE,
+        DA850_EMA_D_15,
+        DA850_EMA_D_14,
+        DA850_EMA_D_13,
+        DA850_EMA_D_12,
+        DA850_EMA_D_11,
+        DA850_EMA_D_10,
+        DA850_EMA_D_9,
+        DA850_EMA_D_8,
+        DA850_EMA_A_0,
+        DA850_EMA_A_3,
+        DA850_EMA_A_4,
+        DA850_EMA_A_5,
+        DA850_EMA_A_6,
+        DA850_EMA_A_7,
+        DA850_EMA_A_8,
+        DA850_EMA_A_9,
+        DA850_EMA_A_10,
+        DA850_EMA_A_11,
+        DA850_EMA_A_12,
+        DA850_EMA_A_13,
+        DA850_EMA_A_14,
+        DA850_EMA_A_15,
+        DA850_EMA_A_16,
+        DA850_EMA_A_17,
+        DA850_EMA_A_18,
+        DA850_EMA_A_19,
+        DA850_EMA_A_20,
+        DA850_EMA_A_21,
+        DA850_EMA_A_22,
+        DA850_EMA_A_23,
+        DA850_EMA_BA_1,
+        DA850_EMA_CLK,
+        DA850_EMA_WAIT_1,
+        DA850_NEMA_CS_2,
+
+        /* GPIO function */
+        DA850_GPIO2_15,
+        DA850_GPIO8_10,
+        DA850_GPIO4_0,
+        DA850_GPIO4_1,
 };
 
 #ifdef CONFIG_DAVINCI_MUX
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index ab8a2586d1cc..171173c1dbad 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -81,6 +81,24 @@
 #define DM355_LPSC_RTO                  12
 #define DM355_LPSC_VPSS_DAC             41
 
+/* DM365 */
+#define DM365_LPSC_TIMER3       5
+#define DM365_LPSC_SPI1         6
+#define DM365_LPSC_MMC_SD1      7
+#define DM365_LPSC_McBSP1       8
+#define DM365_LPSC_PWM3         10
+#define DM365_LPSC_SPI2         11
+#define DM365_LPSC_RTO          12
+#define DM365_LPSC_TIMER4       17
+#define DM365_LPSC_SPI0         22
+#define DM365_LPSC_SPI3         38
+#define DM365_LPSC_SPI4         39
+#define DM365_LPSC_EMAC         40
+#define DM365_LPSC_VOICE_CODEC  44
+#define DM365_LPSC_DAC_CLK      46
+#define DM365_LPSC_VPSSMSTR     47
+#define DM365_LPSC_MJCP         50
+
 /*
  * LPSC Assignments
  */
@@ -118,6 +136,50 @@
 #define DM646X_LPSC_TIMER1         35
 #define DM646X_LPSC_ARM_INTC       45
 
+/* PSC0 defines */
+#define DA8XX_LPSC0_TPCC                0
+#define DA8XX_LPSC0_TPTC0               1
+#define DA8XX_LPSC0_TPTC1               2
+#define DA8XX_LPSC0_EMIF25              3
+#define DA8XX_LPSC0_SPI0                4
+#define DA8XX_LPSC0_MMC_SD              5
+#define DA8XX_LPSC0_AINTC               6
+#define DA8XX_LPSC0_ARM_RAM_ROM         7
+#define DA8XX_LPSC0_SECU_MGR            8
+#define DA8XX_LPSC0_UART0               9
+#define DA8XX_LPSC0_SCR0_SS             10
+#define DA8XX_LPSC0_SCR1_SS             11
+#define DA8XX_LPSC0_SCR2_SS             12
+#define DA8XX_LPSC0_DMAX                13
+#define DA8XX_LPSC0_ARM                 14
+#define DA8XX_LPSC0_GEM                 15
+
+/* PSC1 defines */
+#define DA850_LPSC1_TPCC1               0
+#define DA8XX_LPSC1_USB20               1
+#define DA8XX_LPSC1_USB11               2
+#define DA8XX_LPSC1_GPIO                3
+#define DA8XX_LPSC1_UHPI                4
+#define DA8XX_LPSC1_CPGMAC              5
+#define DA8XX_LPSC1_EMIF3C              6
+#define DA8XX_LPSC1_McASP0              7
+#define DA830_LPSC1_McASP1              8
+#define DA850_LPSC1_SATA                8
+#define DA830_LPSC1_McASP2              9
+#define DA8XX_LPSC1_SPI1                10
+#define DA8XX_LPSC1_I2C                 11
+#define DA8XX_LPSC1_UART1               12
+#define DA8XX_LPSC1_UART2               13
+#define DA8XX_LPSC1_LCDC                16
+#define DA8XX_LPSC1_PWM                 17
+#define DA8XX_LPSC1_ECAP                20
+#define DA830_LPSC1_EQEP                21
+#define DA850_LPSC1_TPTC2               21
+#define DA8XX_LPSC1_SCR_P0_SS           24
+#define DA8XX_LPSC1_SCR_P1_SS           25
+#define DA8XX_LPSC1_CR_P3_SS            26
+#define DA8XX_LPSC1_L3_CBA_RAM          31
+
 extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
 extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
                 unsigned int id, char enable);
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 794fa5cf93c1..a584697a9e70 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -11,13 +11,17 @@
 #ifndef __ASM_ARCH_SERIAL_H
 #define __ASM_ARCH_SERIAL_H
 
-#include <mach/io.h>
+#include <mach/hardware.h>
 
 #define DAVINCI_MAX_NR_UARTS    3
 #define DAVINCI_UART0_BASE      (IO_PHYS + 0x20000)
 #define DAVINCI_UART1_BASE      (IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE      (IO_PHYS + 0x20800)
 
+#define DA8XX_UART0_BASE        (IO_PHYS + 0x042000)
+#define DA8XX_UART1_BASE        (IO_PHYS + 0x10c000)
+#define DA8XX_UART2_BASE        (IO_PHYS + 0x10d000)
+
 /* DaVinci UART register offsets */
 #define UART_DAVINCI_PWREMU             0x0c
 #define UART_DM646X_SCR                 0x10
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
index b7e7036674fa..8e4f10fe1263 100644
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ b/arch/arm/mach-davinci/include/mach/system.h
@@ -16,12 +16,12 @@
 
 extern void davinci_watchdog_reset(void);
 
-static void arch_idle(void)
+static inline void arch_idle(void)
 {
         cpu_do_idle();
 }
 
-static void arch_reset(char mode, const char *cmd)
+static inline void arch_reset(char mode, const char *cmd)
 {
         davinci_watchdog_reset();
 }
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 1e27475f9a23..33796b4db17f 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -21,8 +21,11 @@ static u32 *uart;
 
 static u32 *get_uart_base(void)
 {
-        /* Add logic here for new platforms, using __macine_arch_type */
-        return (u32 *)DAVINCI_UART0_BASE;
+        if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM ||
+                __machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM)
+                return (u32 *)DA8XX_UART2_BASE;
+        else
+                return (u32 *)DAVINCI_UART0_BASE;
 }
 
 /* PORT_16C550A, in polled non-fifo mode */
diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h b/arch/arm/mach-davinci/include/mach/vmalloc.h
index ad51625b6609..d49646a8e206 100644
--- a/arch/arm/mach-davinci/include/mach/vmalloc.h
+++ b/arch/arm/mach-davinci/include/mach/vmalloc.h
@@ -8,7 +8,7 @@
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
  */
-#include <mach/io.h>
+#include <mach/hardware.h>
 
 /* Allow vmalloc range until the IO virtual range minus a 2M "hole" */
 #define VMALLOC_END       (IO_VIRT - (2<<20))
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index d310f579aa85..898905e48946 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -91,3 +91,17 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
         return 0;
 }
 EXPORT_SYMBOL(davinci_cfg_reg);
+
+int da8xx_pinmux_setup(const short pins[])
+{
+        int i, error = -EINVAL;
+
+        if (pins)
+                for (i = 0; pins[i] >= 0; i++) {
+                        error = davinci_cfg_reg(pins[i]);
+                        if (error)
+                                break;
+                }
+
+        return error;
+}
diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c
index db54b2a66b4d..4f1fc9b318b3 100644
--- a/arch/arm/mach-davinci/sram.c
+++ b/arch/arm/mach-davinci/sram.c
@@ -60,7 +60,7 @@ static int __init sram_init(void)
         int status = 0;
 
         if (len) {
-                len = min(len, SRAM_SIZE);
+                len = min_t(unsigned, len, SRAM_SIZE);
                 sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1);
                 if (!sram_pool)
                         status = -ENOMEM;
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 0884ca57bfb0..0d1b6d407b46 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -406,11 +406,11 @@ struct sys_timer davinci_timer = {
 void davinci_watchdog_reset(void)
 {
         u32 tgcr, wdtcr;
-        struct davinci_soc_info *soc_info = &davinci_soc_info;
-        void __iomem *base = soc_info->wdt_base;
+        struct platform_device *pdev = &davinci_wdt_device;
+        void __iomem *base = IO_ADDRESS(pdev->resource[0].start);
         struct clk *wd_clk;
 
-        wd_clk = clk_get(&davinci_wdt_device.dev, NULL);
+        wd_clk = clk_get(&pdev->dev, NULL);
         if (WARN_ON(IS_ERR(wd_clk)))
                 return;
         clk_enable(wd_clk);
@@ -420,11 +420,11 @@ void davinci_watchdog_reset(void)
 
         /* reset timer, set mode to 64-bit watchdog, and unreset */
         tgcr = 0;
-        __raw_writel(tgcr, base + TCR);
+        __raw_writel(tgcr, base + TGCR);
         tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
         tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
                 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
-        __raw_writel(tgcr, base + TCR);
+        __raw_writel(tgcr, base + TGCR);
 
         /* clear counter and period regs */
         __raw_writel(0, base + TIM12);
@@ -432,12 +432,8 @@ void davinci_watchdog_reset(void)
         __raw_writel(0, base + PRD12);
         __raw_writel(0, base + PRD34);
 
-        /* enable */
-        wdtcr = __raw_readl(base + WDTCR);
-        wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT;
-        __raw_writel(wdtcr, base + WDTCR);
-
         /* put watchdog in pre-active state */
+        wdtcr = __raw_readl(base + WDTCR);
         wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
                 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
         __raw_writel(wdtcr, base + WDTCR);
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index abedb6337182..06f55931620c 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -13,6 +13,7 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
+#include <mach/cputype.h>
 
 #define DAVINCI_USB_OTG_BASE 0x01C64000
 
@@ -64,6 +65,10 @@ static struct resource usb_resources[] = {
                 .start          = IRQ_USBINT,
                 .flags          = IORESOURCE_IRQ,
         },
+        {
+                /* placeholder for the dedicated CPPI IRQ */
+                .flags          = IORESOURCE_IRQ,
+        },
 };
 
 static u64 usb_dmamask = DMA_BIT_MASK(32);
@@ -84,6 +89,14 @@ void __init setup_usb(unsigned mA, unsigned potpgt_msec)
 {
         usb_data.power = mA / 2;
         usb_data.potpgt = potpgt_msec / 2;
+
+        if (cpu_is_davinci_dm646x()) {
+                /* Override the defaults as DM6467 uses different IRQs. */
+                usb_dev.resource[1].start = IRQ_DM646X_USBINT;
+                usb_dev.resource[2].start = IRQ_DM646X_USBDMAINT;
+        } else  /* other devices don't have dedicated CPPI IRQ */
+                usb_dev.num_resources = 2;
+
         platform_device_register(&usb_dev);
 }
 
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 3fbd9b0fbe24..caf6d5154aec 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -12,18 +12,15 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
+#include <linux/mtd/physmap.h>
+
 #include <mach/hardware.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+
 static struct physmap_flash_data adssphere_flash_data = {
         .width          = 4,
 };
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 6c4c1633ed12..3dd0e2a23095 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -22,48 +22,39 @@
 #include <mach/hardware.h>
 
 
-/*
- * The EP93xx has two external crystal oscillators.  To generate the
- * required high-frequency clocks, the processor uses two phase-locked-
- * loops (PLLs) to multiply the incoming external clock signal to much
- * higher frequencies that are then divided down by programmable dividers
- * to produce the needed clocks.  The PLLs operate independently of one
- * another.
- */
-#define EP93XX_EXT_CLK_RATE     14745600
-#define EP93XX_EXT_RTC_RATE     32768
-
-
 struct clk {
         unsigned long   rate;
         int             users;
         int             sw_locked;
-        u32             enable_reg;
+        void __iomem    *enable_reg;
         u32             enable_mask;
 
         unsigned long   (*get_rate)(struct clk *clk);
+        int             (*set_rate)(struct clk *clk, unsigned long rate);
 };
 
 
 static unsigned long get_uart_rate(struct clk *clk);
 
+static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
+
 
 static struct clk clk_uart1 = {
         .sw_locked      = 1,
-        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
-        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U1EN,
+        .enable_reg     = EP93XX_SYSCON_DEVCFG,
+        .enable_mask    = EP93XX_SYSCON_DEVCFG_U1EN,
         .get_rate       = get_uart_rate,
 };
 static struct clk clk_uart2 = {
         .sw_locked      = 1,
-        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
-        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U2EN,
+        .enable_reg     = EP93XX_SYSCON_DEVCFG,
+        .enable_mask    = EP93XX_SYSCON_DEVCFG_U2EN,
         .get_rate       = get_uart_rate,
 };
 static struct clk clk_uart3 = {
         .sw_locked      = 1,
-        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
-        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U3EN,
+        .enable_reg     = EP93XX_SYSCON_DEVCFG,
+        .enable_mask    = EP93XX_SYSCON_DEVCFG_U3EN,
         .get_rate       = get_uart_rate,
 };
 static struct clk clk_pll1;
@@ -75,6 +66,15 @@ static struct clk clk_usb_host = {
         .enable_reg     = EP93XX_SYSCON_PWRCNT,
         .enable_mask    = EP93XX_SYSCON_PWRCNT_USH_EN,
 };
+static struct clk clk_keypad = {
+        .sw_locked      = 1,
+        .enable_reg     = EP93XX_SYSCON_KEYTCHCLKDIV,
+        .enable_mask    = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
+        .set_rate       = set_keytchclk_rate,
+};
+static struct clk clk_pwm = {
+        .rate           = EP93XX_EXT_CLK_RATE,
+};
 
 /* DMA Clocks */
 static struct clk clk_m2p0 = {
@@ -130,27 +130,29 @@ static struct clk clk_m2m1 = {
         { .dev_id = dev, .con_id = con, .clk = ck }
 
 static struct clk_lookup clocks[] = {
-        INIT_CK("apb:uart1", NULL, &clk_uart1),
-        INIT_CK("apb:uart2", NULL, &clk_uart2),
-        INIT_CK("apb:uart3", NULL, &clk_uart3),
-        INIT_CK(NULL, "pll1", &clk_pll1),
-        INIT_CK(NULL, "fclk", &clk_f),
-        INIT_CK(NULL, "hclk", &clk_h),
-        INIT_CK(NULL, "pclk", &clk_p),
-        INIT_CK(NULL, "pll2", &clk_pll2),
-        INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
-        INIT_CK(NULL, "m2p0", &clk_m2p0),
-        INIT_CK(NULL, "m2p1", &clk_m2p1),
-        INIT_CK(NULL, "m2p2", &clk_m2p2),
-        INIT_CK(NULL, "m2p3", &clk_m2p3),
-        INIT_CK(NULL, "m2p4", &clk_m2p4),
-        INIT_CK(NULL, "m2p5", &clk_m2p5),
-        INIT_CK(NULL, "m2p6", &clk_m2p6),
-        INIT_CK(NULL, "m2p7", &clk_m2p7),
-        INIT_CK(NULL, "m2p8", &clk_m2p8),
-        INIT_CK(NULL, "m2p9", &clk_m2p9),
-        INIT_CK(NULL, "m2m0", &clk_m2m0),
-        INIT_CK(NULL, "m2m1", &clk_m2m1),
+        INIT_CK("apb:uart1",            NULL,           &clk_uart1),
+        INIT_CK("apb:uart2",            NULL,           &clk_uart2),
+        INIT_CK("apb:uart3",            NULL,           &clk_uart3),
+        INIT_CK(NULL,                   "pll1",         &clk_pll1),
+        INIT_CK(NULL,                   "fclk",         &clk_f),
+        INIT_CK(NULL,                   "hclk",         &clk_h),
+        INIT_CK(NULL,                   "pclk",         &clk_p),
+        INIT_CK(NULL,                   "pll2",         &clk_pll2),
+        INIT_CK("ep93xx-ohci",          NULL,           &clk_usb_host),
+        INIT_CK("ep93xx-keypad",        NULL,           &clk_keypad),
+        INIT_CK(NULL,                   "pwm_clk",      &clk_pwm),
+        INIT_CK(NULL,                   "m2p0",         &clk_m2p0),
+        INIT_CK(NULL,                   "m2p1",         &clk_m2p1),
+        INIT_CK(NULL,                   "m2p2",         &clk_m2p2),
+        INIT_CK(NULL,                   "m2p3",         &clk_m2p3),
+        INIT_CK(NULL,                   "m2p4",         &clk_m2p4),
+        INIT_CK(NULL,                   "m2p5",         &clk_m2p5),
+        INIT_CK(NULL,                   "m2p6",         &clk_m2p6),
+        INIT_CK(NULL,                   "m2p7",         &clk_m2p7),
+        INIT_CK(NULL,                   "m2p8",         &clk_m2p8),
+        INIT_CK(NULL,                   "m2p9",         &clk_m2p9),
+        INIT_CK(NULL,                   "m2m0",         &clk_m2m0),
+        INIT_CK(NULL,                   "m2m1",         &clk_m2m1),
 };
 
 
@@ -160,9 +162,11 @@ int clk_enable(struct clk *clk)
                 u32 value;
 
                 value = __raw_readl(clk->enable_reg);
+                value |= clk->enable_mask;
                 if (clk->sw_locked)
-                        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-                __raw_writel(value | clk->enable_mask, clk->enable_reg);
+                        ep93xx_syscon_swlocked_write(value, clk->enable_reg);
+                else
+                        __raw_writel(value, clk->enable_reg);
         }
 
         return 0;
@@ -175,9 +179,11 @@ void clk_disable(struct clk *clk)
                 u32 value;
 
                 value = __raw_readl(clk->enable_reg);
+                value &= ~clk->enable_mask;
                 if (clk->sw_locked)
-                        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-                __raw_writel(value & ~clk->enable_mask, clk->enable_reg);
+                        ep93xx_syscon_swlocked_write(value, clk->enable_reg);
+                else
+                        __raw_writel(value, clk->enable_reg);
         }
 }
 EXPORT_SYMBOL(clk_disable);
@@ -202,6 +208,43 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
 
+static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
+{
+        u32 val;
+        u32 div_bit;
+
+        val = __raw_readl(clk->enable_reg);
+
+        /*
+         * The Key Matrix and ADC clocks are configured using the same
+         * System Controller register.  The clock used will be either
+         * 1/4 or 1/16 the external clock rate depending on the
+         * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
+         * bit being set or cleared.
+         */
+        div_bit = clk->enable_mask >> 15;
+
+        if (rate == EP93XX_KEYTCHCLK_DIV4)
+                val |= div_bit;
+        else if (rate == EP93XX_KEYTCHCLK_DIV16)
+                val &= ~div_bit;
+        else
+                return -EINVAL;
+
+        ep93xx_syscon_swlocked_write(val, clk->enable_reg);
+        clk->rate = rate;
+        return 0;
+}
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        if (clk->set_rate)
+                return clk->set_rate(clk, rate);
+
+        return -EINVAL;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
 
 static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
 static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 204dc5cbd0b8..16b92c37ec99 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -16,40 +16,24 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/sched.h>
+#include <linux/platform_device.h>
 #include <linux/interrupt.h>
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/bitops.h>
-#include <linux/serial_8250.h>
-#include <linux/serial_core.h>
-#include <linux/device.h>
-#include <linux/mm.h>
 #include <linux/dma-mapping.h>
-#include <linux/time.h>
 #include <linux/timex.h>
-#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
 #include <linux/termios.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
-#include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
 #include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/system.h>
-#include <asm/tlbflush.h>
-#include <asm/pgtable.h>
 
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
-#include <mach/gpio.h>
 
 #include <asm/hardware/vic.h>
 
@@ -98,7 +82,7 @@ void __init ep93xx_map_io(void)
  */
 static unsigned int last_jiffy_time;
 
-#define TIMER4_TICKS_PER_JIFFY          ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
+#define TIMER4_TICKS_PER_JIFFY          DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
 
 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
 {
@@ -362,8 +346,8 @@ void __init ep93xx_init_irq(void)
 {
         int gpio_irq;
 
-        vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
-        vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
+        vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
+        vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
 
         for (gpio_irq = gpio_to_irq(0);
              gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
@@ -385,6 +369,47 @@ void __init ep93xx_init_irq(void)
 
 
 /*************************************************************************
+ * EP93xx System Controller Software Locked register handling
+ *************************************************************************/
+
+/*
+ * syscon_swlock prevents anything else from writing to the syscon
+ * block while a software locked register is being written.
+ */
+static DEFINE_SPINLOCK(syscon_swlock);
+
+void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&syscon_swlock, flags);
+
+        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
+        __raw_writel(val, reg);
+
+        spin_unlock_irqrestore(&syscon_swlock, flags);
+}
+EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
+
+void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
+{
+        unsigned long flags;
+        unsigned int val;
+
+        spin_lock_irqsave(&syscon_swlock, flags);
+
+        val = __raw_readl(EP93XX_SYSCON_DEVCFG);
+        val |= set_bits;
+        val &= ~clear_bits;
+        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
+        __raw_writel(val, EP93XX_SYSCON_DEVCFG);
+
+        spin_unlock_irqrestore(&syscon_swlock, flags);
+}
+EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
+
+
+/*************************************************************************
  * EP93xx peripheral handling
  *************************************************************************/
 #define EP93XX_UART_MCR_OFFSET          (0x0100)
@@ -517,10 +542,8 @@ static struct platform_device ep93xx_eth_device = {
 
 void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
 {
-        if (copy_addr) {
-                memcpy(data->dev_addr,
-                        (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
-        }
+        if (copy_addr)
+                memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
 
         ep93xx_eth_data = *data;
         platform_device_register(&ep93xx_eth_device);
@@ -546,19 +569,125 @@ void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num)
         platform_device_register(&ep93xx_i2c_device);
 }
 
+
+/*************************************************************************
+ * EP93xx LEDs
+ *************************************************************************/
+static struct gpio_led ep93xx_led_pins[] = {
+        {
+                .name                   = "platform:grled",
+                .gpio                   = EP93XX_GPIO_LINE_GRLED,
+        }, {
+                .name                   = "platform:rdled",
+                .gpio                   = EP93XX_GPIO_LINE_RDLED,
+        },
+};
+
+static struct gpio_led_platform_data ep93xx_led_data = {
+        .num_leds       = ARRAY_SIZE(ep93xx_led_pins),
+        .leds           = ep93xx_led_pins,
+};
+
+static struct platform_device ep93xx_leds = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &ep93xx_led_data,
+        },
+};
+
+
+/*************************************************************************
+ * EP93xx pwm peripheral handling
+ *************************************************************************/
+static struct resource ep93xx_pwm0_resource[] = {
+        {
+                .start  = EP93XX_PWM_PHYS_BASE,
+                .end    = EP93XX_PWM_PHYS_BASE + 0x10 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device ep93xx_pwm0_device = {
+        .name           = "ep93xx-pwm",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(ep93xx_pwm0_resource),
+        .resource       = ep93xx_pwm0_resource,
+};
+
+static struct resource ep93xx_pwm1_resource[] = {
+        {
+                .start  = EP93XX_PWM_PHYS_BASE + 0x20,
+                .end    = EP93XX_PWM_PHYS_BASE + 0x30 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device ep93xx_pwm1_device = {
+        .name           = "ep93xx-pwm",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(ep93xx_pwm1_resource),
+        .resource       = ep93xx_pwm1_resource,
+};
+
+void __init ep93xx_register_pwm(int pwm0, int pwm1)
+{
+        if (pwm0)
+                platform_device_register(&ep93xx_pwm0_device);
+
+        /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
+        if (pwm1)
+                platform_device_register(&ep93xx_pwm1_device);
+}
+
+int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
+{
+        int err;
+
+        if (pdev->id == 0) {
+                err = 0;
+        } else if (pdev->id == 1) {
+                err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
+                                   dev_name(&pdev->dev));
+                if (err)
+                        return err;
+                err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
+                if (err)
+                        goto fail;
+
+                /* PWM 1 output on EGPIO[14] */
+                ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
+        } else {
+                err = -ENODEV;
+        }
+
+        return err;
+
+fail:
+        gpio_free(EP93XX_GPIO_LINE_EGPIO14);
+        return err;
+}
+EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
+
+void ep93xx_pwm_release_gpio(struct platform_device *pdev)
+{
+        if (pdev->id == 1) {
+                gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
+                gpio_free(EP93XX_GPIO_LINE_EGPIO14);
+
+                /* EGPIO[14] used for GPIO */
+                ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
+        }
+}
+EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
+
+
 extern void ep93xx_gpio_init(void);
 
 void __init ep93xx_init_devices(void)
 {
-        unsigned int v;
-
-        /*
-         * Disallow access to MaverickCrunch initially.
-         */
-        v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
-        v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
-        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-        __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
+        /* Disallow access to MaverickCrunch initially */
+        ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
 
         ep93xx_gpio_init();
 
@@ -568,4 +697,5 @@ void __init ep93xx_init_devices(void)
 
         platform_device_register(&ep93xx_rtc_device);
         platform_device_register(&ep93xx_ohci_device);
+        platform_device_register(&ep93xx_leds);
 }
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index e9e45b92457e..73145ae5d3fa 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -26,18 +26,16 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <linux/io.h>
 #include <linux/i2c.h>
+#include <linux/mtd/physmap.h>
+
 #include <mach/hardware.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+
 static struct physmap_flash_data edb93xx_flash_data;
 
 static struct resource edb93xx_flash_resource = {
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index 3bad500b71b6..3da7ca816d19 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -12,18 +12,15 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
+#include <linux/mtd/physmap.h>
+
 #include <mach/hardware.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+
 static struct physmap_flash_data gesbc9312_flash_data = {
         .width          = 4,
 };
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index 482cf3d2fbcd..1ea8871e03a9 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -17,15 +17,16 @@
 #include <linux/module.h>
 #include <linux/seq_file.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
 
-#include <mach/ep93xx-regs.h>
-#include <asm/gpio.h>
+#include <mach/hardware.h>
 
 struct ep93xx_gpio_chip {
         struct gpio_chip        chip;
 
-        unsigned int            data_reg;
-        unsigned int            data_dir_reg;
+        void __iomem            *data_reg;
+        void __iomem            *data_dir_reg;
 };
 
 #define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
@@ -111,15 +112,61 @@ static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 {
         struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
         u8 data_reg, data_dir_reg;
-        int i;
+        int gpio, i;
 
         data_reg = __raw_readb(ep93xx_chip->data_reg);
         data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg);
 
-        for (i = 0; i < chip->ngpio; i++)
-                seq_printf(s, "GPIO %s%d: %s %s\n", chip->label, i,
-                           (data_reg & (1 << i)) ? "set" : "clear",
-                           (data_dir_reg & (1 << i)) ? "out" : "in");
+        gpio = ep93xx_chip->chip.base;
+        for (i = 0; i < chip->ngpio; i++, gpio++) {
+                int is_out = data_dir_reg & (1 << i);
+
+                seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s",
+                                chip->label, i, gpio,
+                                gpiochip_is_requested(chip, i) ? : "",
+                                is_out ? "out" : "in ",
+                                (data_reg & (1 << i)) ? "hi" : "lo");
+
+                if (!is_out) {
+                        int irq = gpio_to_irq(gpio);
+                        struct irq_desc *desc = irq_desc + irq;
+
+                        if (irq >= 0 && desc->action) {
+                                char *trigger;
+
+                                switch (desc->status & IRQ_TYPE_SENSE_MASK) {
+                                case IRQ_TYPE_NONE:
+                                        trigger = "(default)";
+                                        break;
+                                case IRQ_TYPE_EDGE_FALLING:
+                                        trigger = "edge-falling";
+                                        break;
+                                case IRQ_TYPE_EDGE_RISING:
+                                        trigger = "edge-rising";
+                                        break;
+                                case IRQ_TYPE_EDGE_BOTH:
+                                        trigger = "edge-both";
+                                        break;
+                                case IRQ_TYPE_LEVEL_HIGH:
+                                        trigger = "level-high";
+                                        break;
+                                case IRQ_TYPE_LEVEL_LOW:
+                                        trigger = "level-low";
+                                        break;
+                                default:
+                                        trigger = "?trigger?";
+                                        break;
+                                }
+
+                                seq_printf(s, " irq-%d %s%s",
+                                                irq, trigger,
+                                                (desc->status & IRQ_WAKEUP)
+                                                        ? " wakeup" : "");
+                        }
+                }
+
+                seq_printf(s, "\n");
+        }
 }
 
 #define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio)                      \
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index 967c079180db..ea78e908fc82 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -52,40 +52,43 @@
 #define EP93XX_AHB_VIRT_BASE            0xfef00000
 #define EP93XX_AHB_SIZE                 0x00100000
 
+#define EP93XX_AHB_IOMEM(x)             IOMEM(EP93XX_AHB_VIRT_BASE + (x))
+
 #define EP93XX_APB_PHYS_BASE            0x80800000
 #define EP93XX_APB_VIRT_BASE            0xfed00000
 #define EP93XX_APB_SIZE                 0x00200000
 
+#define EP93XX_APB_IOMEM(x)             IOMEM(EP93XX_APB_VIRT_BASE + (x))
+
 
 /* AHB peripherals */
-#define EP93XX_DMA_BASE                 ((void __iomem *)               \
-                                         (EP93XX_AHB_VIRT_BASE + 0x00000000))
+#define EP93XX_DMA_BASE                 EP93XX_AHB_IOMEM(0x00000000)
 
-#define EP93XX_ETHERNET_BASE            (EP93XX_AHB_VIRT_BASE + 0x00010000)
 #define EP93XX_ETHERNET_PHYS_BASE       (EP93XX_AHB_PHYS_BASE + 0x00010000)
+#define EP93XX_ETHERNET_BASE            EP93XX_AHB_IOMEM(0x00010000)
 
-#define EP93XX_USB_BASE                 (EP93XX_AHB_VIRT_BASE + 0x00020000)
 #define EP93XX_USB_PHYS_BASE            (EP93XX_AHB_PHYS_BASE + 0x00020000)
+#define EP93XX_USB_BASE                 EP93XX_AHB_IOMEM(0x00020000)
 
-#define EP93XX_RASTER_BASE              (EP93XX_AHB_VIRT_BASE + 0x00030000)
+#define EP93XX_RASTER_BASE              EP93XX_AHB_IOMEM(0x00030000)
 
-#define EP93XX_GRAPHICS_ACCEL_BASE      (EP93XX_AHB_VIRT_BASE + 0x00040000)
+#define EP93XX_GRAPHICS_ACCEL_BASE      EP93XX_AHB_IOMEM(0x00040000)
 
-#define EP93XX_SDRAM_CONTROLLER_BASE    (EP93XX_AHB_VIRT_BASE + 0x00060000)
+#define EP93XX_SDRAM_CONTROLLER_BASE    EP93XX_AHB_IOMEM(0x00060000)
 
-#define EP93XX_PCMCIA_CONTROLLER_BASE   (EP93XX_AHB_VIRT_BASE + 0x00080000)
+#define EP93XX_PCMCIA_CONTROLLER_BASE   EP93XX_AHB_IOMEM(0x00080000)
 
-#define EP93XX_BOOT_ROM_BASE            (EP93XX_AHB_VIRT_BASE + 0x00090000)
+#define EP93XX_BOOT_ROM_BASE            EP93XX_AHB_IOMEM(0x00090000)
 
-#define EP93XX_IDE_BASE                 (EP93XX_AHB_VIRT_BASE + 0x000a0000)
+#define EP93XX_IDE_BASE                 EP93XX_AHB_IOMEM(0x000a0000)
 
-#define EP93XX_VIC1_BASE                (EP93XX_AHB_VIRT_BASE + 0x000b0000)
+#define EP93XX_VIC1_BASE                EP93XX_AHB_IOMEM(0x000b0000)
 
-#define EP93XX_VIC2_BASE                (EP93XX_AHB_VIRT_BASE + 0x000c0000)
+#define EP93XX_VIC2_BASE                EP93XX_AHB_IOMEM(0x000c0000)
 
 
 /* APB peripherals */
-#define EP93XX_TIMER_BASE               (EP93XX_APB_VIRT_BASE + 0x00010000)
+#define EP93XX_TIMER_BASE               EP93XX_APB_IOMEM(0x00010000)
 #define EP93XX_TIMER_REG(x)             (EP93XX_TIMER_BASE + (x))
 #define EP93XX_TIMER1_LOAD              EP93XX_TIMER_REG(0x00)
 #define EP93XX_TIMER1_VALUE             EP93XX_TIMER_REG(0x04)
@@ -102,11 +105,11 @@
 #define EP93XX_TIMER3_CONTROL           EP93XX_TIMER_REG(0x88)
 #define EP93XX_TIMER3_CLEAR             EP93XX_TIMER_REG(0x8c)
 
-#define EP93XX_I2S_BASE                 (EP93XX_APB_VIRT_BASE + 0x00020000)
+#define EP93XX_I2S_BASE                 EP93XX_APB_IOMEM(0x00020000)
 
-#define EP93XX_SECURITY_BASE            (EP93XX_APB_VIRT_BASE + 0x00030000)
+#define EP93XX_SECURITY_BASE            EP93XX_APB_IOMEM(0x00030000)
 
-#define EP93XX_GPIO_BASE                (EP93XX_APB_VIRT_BASE + 0x00040000)
+#define EP93XX_GPIO_BASE                EP93XX_APB_IOMEM(0x00040000)
 #define EP93XX_GPIO_REG(x)              (EP93XX_GPIO_BASE + (x))
 #define EP93XX_GPIO_F_INT_TYPE1         EP93XX_GPIO_REG(0x4c)
 #define EP93XX_GPIO_F_INT_TYPE2         EP93XX_GPIO_REG(0x50)
@@ -124,32 +127,33 @@
 #define EP93XX_GPIO_B_INT_ENABLE        EP93XX_GPIO_REG(0xb8)
 #define EP93XX_GPIO_B_INT_STATUS        EP93XX_GPIO_REG(0xbc)
 
-#define EP93XX_AAC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00080000)
+#define EP93XX_AAC_BASE                 EP93XX_APB_IOMEM(0x00080000)
 
-#define EP93XX_SPI_BASE                 (EP93XX_APB_VIRT_BASE + 0x000a0000)
+#define EP93XX_SPI_BASE                 EP93XX_APB_IOMEM(0x000a0000)
 
-#define EP93XX_IRDA_BASE                (EP93XX_APB_VIRT_BASE + 0x000b0000)
+#define EP93XX_IRDA_BASE                EP93XX_APB_IOMEM(0x000b0000)
 
-#define EP93XX_UART1_BASE               (EP93XX_APB_VIRT_BASE + 0x000c0000)
 #define EP93XX_UART1_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000c0000)
+#define EP93XX_UART1_BASE               EP93XX_APB_IOMEM(0x000c0000)
 
-#define EP93XX_UART2_BASE               (EP93XX_APB_VIRT_BASE + 0x000d0000)
 #define EP93XX_UART2_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000d0000)
+#define EP93XX_UART2_BASE               EP93XX_APB_IOMEM(0x000d0000)
 
-#define EP93XX_UART3_BASE               (EP93XX_APB_VIRT_BASE + 0x000e0000)
 #define EP93XX_UART3_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000e0000)
+#define EP93XX_UART3_BASE               EP93XX_APB_IOMEM(0x000e0000)
 
-#define EP93XX_KEY_MATRIX_BASE          (EP93XX_APB_VIRT_BASE + 0x000f0000)
+#define EP93XX_KEY_MATRIX_BASE          EP93XX_APB_IOMEM(0x000f0000)
 
-#define EP93XX_ADC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00100000)
-#define EP93XX_TOUCHSCREEN_BASE         (EP93XX_APB_VIRT_BASE + 0x00100000)
+#define EP93XX_ADC_BASE                 EP93XX_APB_IOMEM(0x00100000)
+#define EP93XX_TOUCHSCREEN_BASE         EP93XX_APB_IOMEM(0x00100000)
 
-#define EP93XX_PWM_BASE                 (EP93XX_APB_VIRT_BASE + 0x00110000)
+#define EP93XX_PWM_PHYS_BASE            (EP93XX_APB_PHYS_BASE + 0x00110000)
+#define EP93XX_PWM_BASE                 EP93XX_APB_IOMEM(0x00110000)
 
-#define EP93XX_RTC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00120000)
 #define EP93XX_RTC_PHYS_BASE            (EP93XX_APB_PHYS_BASE + 0x00120000)
+#define EP93XX_RTC_BASE                 EP93XX_APB_IOMEM(0x00120000)
 
-#define EP93XX_SYSCON_BASE              (EP93XX_APB_VIRT_BASE + 0x00130000)
+#define EP93XX_SYSCON_BASE              EP93XX_APB_IOMEM(0x00130000)
 #define EP93XX_SYSCON_REG(x)            (EP93XX_SYSCON_BASE + (x))
 #define EP93XX_SYSCON_POWER_STATE       EP93XX_SYSCON_REG(0x00)
 #define EP93XX_SYSCON_PWRCNT            EP93XX_SYSCON_REG(0x04)
@@ -172,14 +176,45 @@
 #define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
 #define EP93XX_SYSCON_CLOCK_SET1        EP93XX_SYSCON_REG(0x20)
 #define EP93XX_SYSCON_CLOCK_SET2        EP93XX_SYSCON_REG(0x24)
-#define EP93XX_SYSCON_DEVICE_CONFIG     EP93XX_SYSCON_REG(0x80)
-#define EP93XX_SYSCON_DEVICE_CONFIG_U3EN                (1<<24)
-#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE       (1<<23)
-#define EP93XX_SYSCON_DEVICE_CONFIG_U2EN                (1<<20)
-#define EP93XX_SYSCON_DEVICE_CONFIG_U1EN                (1<<18)
+#define EP93XX_SYSCON_DEVCFG            EP93XX_SYSCON_REG(0x80)
+#define EP93XX_SYSCON_DEVCFG_SWRST      (1<<31)
+#define EP93XX_SYSCON_DEVCFG_D1ONG      (1<<30)
+#define EP93XX_SYSCON_DEVCFG_D0ONG      (1<<29)
+#define EP93XX_SYSCON_DEVCFG_IONU2      (1<<28)
+#define EP93XX_SYSCON_DEVCFG_GONK       (1<<27)
+#define EP93XX_SYSCON_DEVCFG_TONG       (1<<26)
+#define EP93XX_SYSCON_DEVCFG_MONG       (1<<25)
+#define EP93XX_SYSCON_DEVCFG_U3EN       (1<<24)
+#define EP93XX_SYSCON_DEVCFG_CPENA      (1<<23)
+#define EP93XX_SYSCON_DEVCFG_A2ONG      (1<<22)
+#define EP93XX_SYSCON_DEVCFG_A1ONG      (1<<21)
+#define EP93XX_SYSCON_DEVCFG_U2EN       (1<<20)
+#define EP93XX_SYSCON_DEVCFG_EXVC       (1<<19)
+#define EP93XX_SYSCON_DEVCFG_U1EN       (1<<18)
+#define EP93XX_SYSCON_DEVCFG_TIN        (1<<17)
+#define EP93XX_SYSCON_DEVCFG_HC3IN      (1<<15)
+#define EP93XX_SYSCON_DEVCFG_HC3EN      (1<<14)
+#define EP93XX_SYSCON_DEVCFG_HC1IN      (1<<13)
+#define EP93XX_SYSCON_DEVCFG_HC1EN      (1<<12)
+#define EP93XX_SYSCON_DEVCFG_HONIDE     (1<<11)
+#define EP93XX_SYSCON_DEVCFG_GONIDE     (1<<10)
+#define EP93XX_SYSCON_DEVCFG_PONG       (1<<9)
+#define EP93XX_SYSCON_DEVCFG_EONIDE     (1<<8)
+#define EP93XX_SYSCON_DEVCFG_I2SONSSP   (1<<7)
+#define EP93XX_SYSCON_DEVCFG_I2SONAC97  (1<<6)
+#define EP93XX_SYSCON_DEVCFG_RASONP3    (1<<4)
+#define EP93XX_SYSCON_DEVCFG_RAS        (1<<3)
+#define EP93XX_SYSCON_DEVCFG_ADCPD      (1<<2)
+#define EP93XX_SYSCON_DEVCFG_KEYS       (1<<1)
+#define EP93XX_SYSCON_DEVCFG_SHENA      (1<<0)
+#define EP93XX_SYSCON_KEYTCHCLKDIV      EP93XX_SYSCON_REG(0x90)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN  (1<<15)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
 #define EP93XX_SYSCON_SWLOCK            EP93XX_SYSCON_REG(0xc0)
 
-#define EP93XX_WATCHDOG_BASE            (EP93XX_APB_VIRT_BASE + 0x00140000)
+#define EP93XX_WATCHDOG_BASE            EP93XX_APB_IOMEM(0x00140000)
 
 
 #endif
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h
index 2866297310b7..349fa7cb72d5 100644
--- a/arch/arm/mach-ep93xx/include/mach/hardware.h
+++ b/arch/arm/mach-ep93xx/include/mach/hardware.h
@@ -4,12 +4,23 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
-#include "ep93xx-regs.h"
+#include <mach/ep93xx-regs.h>
+#include <mach/platform.h>
 
 #define pcibios_assign_all_busses()     0
 
-#include "platform.h"
+/*
+ * The EP93xx has two external crystal oscillators.  To generate the
+ * required high-frequency clocks, the processor uses two phase-locked-
+ * loops (PLLs) to multiply the incoming external clock signal to much
+ * higher frequencies that are then divided down by programmable dividers
+ * to produce the needed clocks.  The PLLs operate independently of one
+ * another.
+ */
+#define EP93XX_EXT_CLK_RATE     14745600
+#define EP93XX_EXT_RTC_RATE     32768
 
-#include "ts72xx.h"
+#define EP93XX_KEYTCHCLK_DIV4   (EP93XX_EXT_CLK_RATE / 4)
+#define EP93XX_KEYTCHCLK_DIV16  (EP93XX_EXT_CLK_RATE / 16)
 
 #endif
diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h
index fd5f081cc8b7..cebcc1c53d63 100644
--- a/arch/arm/mach-ep93xx/include/mach/io.h
+++ b/arch/arm/mach-ep93xx/include/mach/io.h
@@ -1,8 +1,21 @@
 /*
  * arch/arm/mach-ep93xx/include/mach/io.h
  */
+#ifndef __ASM_MACH_IO_H
+#define __ASM_MACH_IO_H
 
 #define IO_SPACE_LIMIT          0xffffffff
 
-#define __io(p)         __typesafe_io(p)
-#define __mem_pci(p)    (p)
+#define __io(p)                 __typesafe_io(p)
+#define __mem_pci(p)            (p)
+
+/*
+ * A typesafe __io() variation for variable initialisers
+ */
+#ifdef __ASSEMBLER__
+#define IOMEM(p)                p
+#else
+#define IOMEM(p)                ((void __iomem __force *)(p))
+#endif
+
+#endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 05f0f4f2f3ce..5f5fa6574d34 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -5,6 +5,7 @@
 #ifndef __ASSEMBLY__
 
 struct i2c_board_info;
+struct platform_device;
 
 struct ep93xx_eth_data
 {
@@ -15,8 +16,27 @@ struct ep93xx_eth_data
 void ep93xx_map_io(void);
 void ep93xx_init_irq(void);
 void ep93xx_init_time(unsigned long);
+
+/* EP93xx System Controller software locked register write */
+void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
+void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
+
+static inline void ep93xx_devcfg_set_bits(unsigned int bits)
+{
+        ep93xx_devcfg_set_clear(bits, 0x00);
+}
+
+static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
+{
+        ep93xx_devcfg_set_clear(0x00, bits);
+}
+
 void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
 void ep93xx_register_i2c(struct i2c_board_info *devices, int num);
+void ep93xx_register_pwm(int pwm0, int pwm1);
+int ep93xx_pwm_acquire_gpio(struct platform_device *pdev);
+void ep93xx_pwm_release_gpio(struct platform_device *pdev);
+
 void ep93xx_init_devices(void);
 extern struct sys_timer ep93xx_timer;
 
diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h
index ed8f35e4f068..6d661fe9d66c 100644
--- a/arch/arm/mach-ep93xx/include/mach/system.h
+++ b/arch/arm/mach-ep93xx/include/mach/system.h
@@ -11,15 +11,13 @@ static inline void arch_idle(void)
 
 static inline void arch_reset(char mode, const char *cmd)
 {
-        u32 devicecfg;
-
         local_irq_disable();
 
-        devicecfg = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
-        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-        __raw_writel(devicecfg | 0x80000000, EP93XX_SYSCON_DEVICE_CONFIG);
-        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-        __raw_writel(devicecfg & ~0x80000000, EP93XX_SYSCON_DEVICE_CONFIG);
+        /*
+         * Set then clear the SWRST bit to initiate a software reset
+         */
+        ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
+        ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
 
         while (1)
                 ;
diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
index 411734422c1d..3bd934e9a7f1 100644
--- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h
+++ b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
@@ -67,7 +67,6 @@
 
 
 #ifndef __ASSEMBLY__
-#include <linux/io.h>
 
 static inline int board_is_ts7200(void)
 {
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 15d6815d78c4..0a313e82fb74 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -9,21 +9,16 @@
  * published by the Free Software Foundation.
  */
 
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
 #include <linux/kernel.h>
-#include <linux/mm.h>
+#include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
 #include <linux/mtd/physmap.h>
 
 #include <mach/hardware.h>
 
-#include <asm/mach/arch.h>
 #include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
 
 static struct ep93xx_eth_data micro9_eth_data = {
         .phy_id         = 0x1f,
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index aaf1371412af..259f7822ba52 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -12,19 +12,18 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <linux/m48t86.h>
 #include <linux/io.h>
-#include <linux/i2c.h>
+#include <linux/m48t86.h>
+#include <linux/mtd/physmap.h>
+
 #include <mach/hardware.h>
+#include <mach/ts72xx.h>
+
 #include <asm/mach-types.h>
-#include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/mach/arch.h>
+
 
 static struct map_desc ts72xx_io_desc[] __initdata = {
         {
diff --git a/arch/arm/mach-integrator/include/mach/hardware.h b/arch/arm/mach-integrator/include/mach/hardware.h
index 1251319ef9ae..d795642fad22 100644
--- a/arch/arm/mach-integrator/include/mach/hardware.h
+++ b/arch/arm/mach-integrator/include/mach/hardware.h
@@ -36,8 +36,12 @@
 #define PCIO_BASE               PCI_IO_VADDR
 #define PCIMEM_BASE             PCI_MEMORY_VADDR
 
+#ifdef CONFIG_MMU
 /* macro to get at IO space when running virtually */
 #define IO_ADDRESS(x) (((x) >> 4) + IO_BASE) 
+#else
+#define IO_ADDRESS(x) (x)
+#endif
 
 #define pcibios_assign_all_busses()     1
 
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 4ac04055c2ea..2a318eba1b07 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -49,14 +49,14 @@
 
 #define INTCP_PA_CLCD_BASE              0xc0000000
 
-#define INTCP_VA_CIC_BASE               0xf1000040
-#define INTCP_VA_PIC_BASE               0xf1400000
-#define INTCP_VA_SIC_BASE               0xfca00000
+#define INTCP_VA_CIC_BASE               IO_ADDRESS(INTEGRATOR_HDR_BASE) + 0x40
+#define INTCP_VA_PIC_BASE               IO_ADDRESS(INTEGRATOR_IC_BASE)
+#define INTCP_VA_SIC_BASE               IO_ADDRESS(0xca000000)
 
 #define INTCP_PA_ETH_BASE               0xc8000000
 #define INTCP_ETH_SIZE                  0x10
 
-#define INTCP_VA_CTRL_BASE              0xfcb00000
+#define INTCP_VA_CTRL_BASE              IO_ADDRESS(0xcb000000)
 #define INTCP_FLASHPROG                 0x04
 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
@@ -121,12 +121,12 @@ static struct map_desc intcp_io_desc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = 0xfca00000,
+                .virtual        = IO_ADDRESS(0xca000000),
                 .pfn            = __phys_to_pfn(0xca000000),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = 0xfcb00000,
+                .virtual        = IO_ADDRESS(0xcb000000),
                 .pfn            = __phys_to_pfn(0xcb000000),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE
@@ -394,8 +394,8 @@ static struct platform_device *intcp_devs[] __initdata = {
  */
 static unsigned int mmc_status(struct device *dev)
 {
-        unsigned int status = readl(0xfca00004);
-        writel(8, 0xfcb00008);
+        unsigned int status = readl(IO_ADDRESS(0xca000000) + 4);
+        writel(8, IO_ADDRESS(0xcb000000) + 8);
 
         return status & 8;
 }
@@ -403,6 +403,8 @@ static unsigned int mmc_status(struct device *dev)
 static struct mmc_platform_data mmc_data = {
         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
         .status         = mmc_status,
+        .gpio_wp        = -1,
+        .gpio_cd        = -1,
 };
 
 static struct amba_device mmc_device = {
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 1e93dfee7543..5083f03e9b5e 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -416,6 +416,7 @@ static struct clocksource clocksource_ixp4xx = {
 };
 
 unsigned long ixp4xx_timer_freq = FREQ;
+EXPORT_SYMBOL(ixp4xx_timer_freq);
 static int __init ixp4xx_clocksource_init(void)
 {
         clocksource_ixp4xx.mult =
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 25100f7acf4c..0aca451b216d 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -38,6 +38,12 @@ config MACH_TS219
           Say 'Y' here if you want your kernel to support the
           QNAP TS-119 and TS-219 Turbo NAS devices.
 
+config MACH_OPENRD_BASE
+        bool "Marvell OpenRD Base Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell OpenRD Base Board.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 9dd680e964d6..80ab0ec90ee1 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -6,5 +6,6 @@ obj-$(CONFIG_MACH_RD88F6281)		+= rd88f6281-setup.o
 obj-$(CONFIG_MACH_MV88F6281GTW_GE)      += mv88f6281gtw_ge-setup.o
 obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
 obj-$(CONFIG_MACH_TS219)                += ts219-setup.o
+obj-$(CONFIG_MACH_OPENRD_BASE)          += openrd_base-setup.o
 
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 0f6919838011..0acb61f3c10b 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -838,7 +838,8 @@ int __init kirkwood_find_tclk(void)
         u32 dev, rev;
 
         kirkwood_pcie_id(&dev, &rev);
-        if (dev == MV88F6281_DEV_ID && rev == MV88F6281_REV_A0)
+        if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
+                                        rev == MV88F6281_REV_A1))
                 return 200000000;
 
         return 166666667;
@@ -872,6 +873,8 @@ static char * __init kirkwood_id(void)
                         return "MV88F6281-Z0";
                 else if (rev == MV88F6281_REV_A0)
                         return "MV88F6281-A0";
+                else if (rev == MV88F6281_REV_A1)
+                        return "MV88F6281-A1";
                 else
                         return "MV88F6281-Rev-Unsupported";
         } else if (dev == MV88F6192_DEV_ID) {
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 07af858814a0..54c132731d2d 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -101,6 +101,7 @@
 #define MV88F6281_DEV_ID        0x6281
 #define MV88F6281_REV_Z0        0
 #define MV88F6281_REV_A0        2
+#define MV88F6281_REV_A1        3
 
 #define MV88F6192_DEV_ID        0x6192
 #define MV88F6192_REV_Z0        0
diff --git a/arch/arm/mach-kirkwood/openrd_base-setup.c b/arch/arm/mach-kirkwood/openrd_base-setup.c
new file mode 100644
index 000000000000..947dfb8cd5b2
--- /dev/null
+++ b/arch/arm/mach-kirkwood/openrd_base-setup.c
@@ -0,0 +1,84 @@
+/*
+ * arch/arm/mach-kirkwood/openrd_base-setup.c
+ *
+ * Marvell OpenRD Base Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mtd_partition openrd_base_nand_parts[] = {
+        {
+                .name = "u-boot",
+                .offset = 0,
+                .size = SZ_1M
+        }, {
+                .name = "uImage",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = SZ_4M
+        }, {
+                .name = "root",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = MTDPART_SIZ_FULL
+        },
+};
+
+static struct mv643xx_eth_platform_data openrd_base_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+static struct mv_sata_platform_data openrd_base_sata_data = {
+        .n_ports        = 2,
+};
+
+static struct mvsdio_platform_data openrd_base_mvsdio_data = {
+        .gpio_card_detect = 29, /* MPP29 used as SD card detect */
+};
+
+static unsigned int openrd_base_mpp_config[] __initdata = {
+        MPP29_GPIO,
+        0
+};
+
+static void __init openrd_base_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(openrd_base_mpp_config);
+
+        kirkwood_uart0_init();
+        kirkwood_nand_init(ARRAY_AND_SIZE(openrd_base_nand_parts), 25);
+
+        kirkwood_ehci_init();
+
+        kirkwood_ge00_init(&openrd_base_ge00_data);
+        kirkwood_sata_init(&openrd_base_sata_data);
+        kirkwood_sdio_init(&openrd_base_mvsdio_data);
+}
+
+MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
+        /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = openrd_base_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c
index 0d0f306851d0..d1b588519ad2 100644
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-mx1/clock.c
@@ -18,11 +18,14 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/list.h>
 #include <linux/math64.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 
+#include <asm/clkdev.h>
+
 #include <mach/clock.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
@@ -94,7 +97,6 @@ static unsigned long clk16m_get_rate(struct clk *clk)
 }
 
 static struct clk clk16m = {
-        .name = "CLK16M",
         .get_rate = clk16m_get_rate,
         .enable = _clk_enable,
         .enable_reg = CCM_CSCR,
@@ -111,7 +113,6 @@ static unsigned long clk32_get_rate(struct clk *clk)
 }
 
 static struct clk clk32 = {
-        .name = "CLK32",
         .get_rate = clk32_get_rate,
 };
 
@@ -121,7 +122,6 @@ static unsigned long clk32_premult_get_rate(struct clk *clk)
 }
 
 static struct clk clk32_premult = {
-        .name = "CLK32_premultiplier",
         .parent = &clk32,
         .get_rate = clk32_premult_get_rate,
 };
@@ -156,7 +156,6 @@ static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
 }
 
 static struct clk prem_clk = {
-        .name = "prem_clk",
         .set_parent = prem_clk_set_parent,
 };
 
@@ -167,7 +166,6 @@ static unsigned long system_clk_get_rate(struct clk *clk)
 }
 
 static struct clk system_clk = {
-        .name = "system_clk",
         .parent = &prem_clk,
         .get_rate = system_clk_get_rate,
 };
@@ -179,7 +177,6 @@ static unsigned long mcu_clk_get_rate(struct clk *clk)
 }
 
 static struct clk mcu_clk = {
-        .name = "mcu_clk",
         .parent = &clk32_premult,
         .get_rate = mcu_clk_get_rate,
 };
@@ -195,7 +192,6 @@ static unsigned long fclk_get_rate(struct clk *clk)
 }
 
 static struct clk fclk = {
-        .name = "fclk",
         .parent = &mcu_clk,
         .get_rate = fclk_get_rate,
 };
@@ -238,7 +234,6 @@ static int hclk_set_rate(struct clk *clk, unsigned long rate)
 }
 
 static struct clk hclk = {
-        .name = "hclk",
         .parent = &system_clk,
         .get_rate = hclk_get_rate,
         .round_rate = hclk_round_rate,
@@ -280,7 +275,6 @@ static int clk48m_set_rate(struct clk *clk, unsigned long rate)
 }
 
 static struct clk clk48m = {
-        .name = "CLK48M",
         .parent = &system_clk,
         .get_rate = clk48m_get_rate,
         .round_rate = clk48m_round_rate,
@@ -400,21 +394,18 @@ static int perclk3_set_rate(struct clk *clk, unsigned long rate)
 
 static struct clk perclk[] = {
         {
-                .name = "perclk",
                 .id = 0,
                 .parent = &system_clk,
                 .get_rate = perclk1_get_rate,
                 .round_rate = perclk1_round_rate,
                 .set_rate = perclk1_set_rate,
         }, {
-                .name = "perclk",
                 .id = 1,
                 .parent = &system_clk,
                 .get_rate = perclk2_get_rate,
                 .round_rate = perclk2_round_rate,
                 .set_rate = perclk2_set_rate,
         }, {
-                .name = "perclk",
                 .id = 2,
                 .parent = &system_clk,
                 .get_rate = perclk3_get_rate,
@@ -457,12 +448,10 @@ static int clko_set_parent(struct clk *clk, struct clk *parent)
 }
 
 static struct clk clko_clk = {
-        .name = "clko_clk",
         .set_parent = clko_set_parent,
 };
 
 static struct clk dma_clk = {
-        .name = "dma",
         .parent = &hclk,
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
@@ -473,7 +462,6 @@ static struct clk dma_clk = {
 };
 
 static struct clk csi_clk = {
-        .name = "csi_clk",
         .parent = &hclk,
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
@@ -484,7 +472,6 @@ static struct clk csi_clk = {
 };
 
 static struct clk mma_clk = {
-        .name = "mma_clk",
         .parent = &hclk,
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
@@ -495,7 +482,6 @@ static struct clk mma_clk = {
 };
 
 static struct clk usbd_clk = {
-        .name = "usbd_clk",
         .parent = &clk48m,
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
@@ -506,99 +492,85 @@ static struct clk usbd_clk = {
 };
 
 static struct clk gpt_clk = {
-        .name = "gpt_clk",
         .parent = &perclk[0],
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk uart_clk = {
-        .name = "uart",
         .parent = &perclk[0],
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk i2c_clk = {
-        .name = "i2c_clk",
         .parent = &hclk,
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk spi_clk = {
-        .name = "spi_clk",
         .parent = &perclk[1],
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk sdhc_clk = {
-        .name = "sdhc_clk",
         .parent = &perclk[1],
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk lcdc_clk = {
-        .name = "lcdc_clk",
         .parent = &perclk[1],
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk mshc_clk = {
-        .name = "mshc_clk",
         .parent = &hclk,
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk ssi_clk = {
-        .name = "ssi_clk",
         .parent = &perclk[2],
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk rtc_clk = {
-        .name = "rtc_clk",
         .parent = &clk32,
 };
 
-static struct clk *mxc_clks[] = {
-        &clk16m,
-        &clk32,
-        &clk32_premult,
-        &prem_clk,
-        &system_clk,
-        &mcu_clk,
-        &fclk,
-        &hclk,
-        &clk48m,
-        &perclk[0],
-        &perclk[1],
-        &perclk[2],
-        &clko_clk,
-        &dma_clk,
-        &csi_clk,
-        &mma_clk,
-        &usbd_clk,
-        &gpt_clk,
-        &uart_clk,
-        &i2c_clk,
-        &spi_clk,
-        &sdhc_clk,
-        &lcdc_clk,
-        &mshc_clk,
-        &ssi_clk,
-        &rtc_clk,
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+static struct clk_lookup lookups[] __initdata = {
+        _REGISTER_CLOCK(NULL, "dma", dma_clk)
+        _REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
+        _REGISTER_CLOCK(NULL, "mma", mma_clk)
+        _REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
+        _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk)
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
+        _REGISTER_CLOCK("spi_imx.0", NULL, spi_clk)
+        _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
+        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+        _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
+        _REGISTER_CLOCK(NULL, "ssi", ssi_clk)
+        _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk)
 };
 
 int __init mx1_clocks_init(unsigned long fref)
 {
-        struct clk **clkp;
         unsigned int reg;
+        int i;
 
         /* disable clocks we are able to */
         __raw_writel(0, SCM_GCCR);
@@ -620,13 +592,13 @@ int __init mx1_clocks_init(unsigned long fref)
         reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
         clko_clk.parent = (struct clk *)clko_clocks[reg];
 
-        for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
-                clk_register(*clkp);
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
 
         clk_enable(&hclk);
         clk_enable(&fclk);
 
-        mxc_timer_init(&gpt_clk);
+        mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT);
 
         return 0;
 }
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
index 76d1ffb48079..b6be29d1cb08 100644
--- a/arch/arm/mach-mx1/devices.c
+++ b/arch/arm/mach-mx1/devices.c
@@ -29,12 +29,11 @@
 #include "devices.h"
 
 static struct resource imx_csi_resources[] = {
-        [0] = {
+        {
                 .start  = 0x00224000,
                 .end    = 0x00224010,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = CSI_INT,
                 .end    = CSI_INT,
                 .flags  = IORESOURCE_IRQ,
@@ -55,12 +54,11 @@ struct platform_device imx_csi_device = {
 };
 
 static struct resource imx_i2c_resources[] = {
-        [0] = {
+        {
                 .start  = 0x00217000,
                 .end    = 0x00217010,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = I2C_INT,
                 .end    = I2C_INT,
                 .flags  = IORESOURCE_IRQ,
@@ -75,22 +73,19 @@ struct platform_device imx_i2c_device = {
 };
 
 static struct resource imx_uart1_resources[] = {
-        [0] = {
+        {
                 .start  = UART1_BASE_ADDR,
                 .end    = UART1_BASE_ADDR + 0xD0,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = UART1_MINT_RX,
                 .end    = UART1_MINT_RX,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
+        }, {
                 .start  = UART1_MINT_TX,
                 .end    = UART1_MINT_TX,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
+        }, {
                 .start  = UART1_MINT_RTS,
                 .end    = UART1_MINT_RTS,
                 .flags  = IORESOURCE_IRQ,
@@ -105,22 +100,19 @@ struct platform_device imx_uart1_device = {
 };
 
 static struct resource imx_uart2_resources[] = {
-        [0] = {
+        {
                 .start  = UART2_BASE_ADDR,
                 .end    = UART2_BASE_ADDR + 0xD0,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = UART2_MINT_RX,
                 .end    = UART2_MINT_RX,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
+        }, {
                 .start  = UART2_MINT_TX,
                 .end    = UART2_MINT_TX,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
+        }, {
                 .start  = UART2_MINT_RTS,
                 .end    = UART2_MINT_RTS,
                 .flags  = IORESOURCE_IRQ,
@@ -135,17 +127,15 @@ struct platform_device imx_uart2_device = {
 };
 
 static struct resource imx_rtc_resources[] = {
-        [0] = {
+        {
                 .start  = 0x00204000,
                 .end    = 0x00204024,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = RTC_INT,
                 .end    = RTC_INT,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
+        }, {
                 .start  = RTC_SAMINT,
                 .end    = RTC_SAMINT,
                 .flags  = IORESOURCE_IRQ,
@@ -160,12 +150,11 @@ struct platform_device imx_rtc_device = {
 };
 
 static struct resource imx_wdt_resources[] = {
-        [0] = {
+        {
                 .start  = 0x00201000,
                 .end    = 0x00201008,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = WDT_INT,
                 .end    = WDT_INT,
                 .flags  = IORESOURCE_IRQ,
@@ -180,42 +169,35 @@ struct platform_device imx_wdt_device = {
 };
 
 static struct resource imx_usb_resources[] = {
-        [0] = {
+        {
                 .start  = 0x00212000,
                 .end    = 0x00212148,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = USBD_INT0,
                 .end    = USBD_INT0,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
+        }, {
                 .start  = USBD_INT1,
                 .end    = USBD_INT1,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
+        }, {
                 .start  = USBD_INT2,
                 .end    = USBD_INT2,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [4] = {
+        }, {
                 .start  = USBD_INT3,
                 .end    = USBD_INT3,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [5] = {
+        }, {
                 .start  = USBD_INT4,
                 .end    = USBD_INT4,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [6] = {
+        }, {
                 .start  = USBD_INT5,
                 .end    = USBD_INT5,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [7] = {
+        }, {
                 .start  = USBD_INT6,
                 .end    = USBD_INT6,
                 .flags  = IORESOURCE_IRQ,
@@ -231,29 +213,26 @@ struct platform_device imx_usb_device = {
 
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
-        [0] = {
+        {
                 .chip.label = "gpio-0",
                 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
                 .irq = GPIO_INT_PORTA,
-                .virtual_irq_start = MXC_GPIO_IRQ_START
-        },
-        [1] = {
+                .virtual_irq_start = MXC_GPIO_IRQ_START,
+        }, {
                 .chip.label = "gpio-1",
                 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
                 .irq = GPIO_INT_PORTB,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32
-        },
-        [2] = {
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
+        }, {
                 .chip.label = "gpio-2",
                 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
                 .irq = GPIO_INT_PORTC,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 64
-        },
-        [3] = {
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
+        }, {
                 .chip.label = "gpio-3",
                 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
                 .irq = GPIO_INT_PORTD,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 96
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
         }
 };
 
diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-mx1/generic.c
index 7622c9b38c97..7f9fc1034c08 100644
--- a/arch/arm/mach-mx1/generic.c
+++ b/arch/arm/mach-mx1/generic.c
@@ -41,6 +41,13 @@ static struct map_desc imx_io_desc[] __initdata = {
 void __init mx1_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX1);
+        mxc_arch_reset_init(IO_ADDRESS(WDT_BASE_ADDR));
 
         iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
 }
+
+void __init mx1_init_irq(void)
+{
+        mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+}
+
diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mx1ads.c
index e5b0c0a83c3b..30f04e56fafe 100644
--- a/arch/arm/mach-mx1/mx1ads.c
+++ b/arch/arm/mach-mx1/mx1ads.c
@@ -104,12 +104,10 @@ static struct imxi2c_platform_data mx1ads_i2c_data = {
 
 static struct i2c_board_info mx1ads_i2c_devices[] = {
         {
-                I2C_BOARD_INFO("pcf857x", 0x22),
-                .type = "pcf8575",
+                I2C_BOARD_INFO("pcf8575", 0x22),
                 .platform_data = &pcf857x_data[0],
         }, {
-                I2C_BOARD_INFO("pcf857x", 0x24),
-                .type = "pcf8575",
+                I2C_BOARD_INFO("pcf8575", 0x24),
                 .platform_data = &pcf857x_data[1],
         },
 };
@@ -151,7 +149,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
         .io_pg_offst    = (IMX_IO_BASE >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx1_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx1_init_irq,
         .timer          = &mx1ads_timer,
         .init_machine   = mx1ads_init,
 MACHINE_END
@@ -161,7 +159,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS")
         .io_pg_offst    = (IMX_IO_BASE >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx1_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx1_init_irq,
         .timer          = &mx1ads_timer,
         .init_machine   = mx1ads_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx1/scb9328.c b/arch/arm/mach-mx1/scb9328.c
index 20e0b5bcdffc..325d98df6053 100644
--- a/arch/arm/mach-mx1/scb9328.c
+++ b/arch/arm/mach-mx1/scb9328.c
@@ -68,22 +68,20 @@ static struct dm9000_plat_data dm9000_platdata = {
  * to gain access to address latch registers and the data path.
  */
 static struct resource dm9000x_resources[] = {
-        [0] = {
+        {
                 .name   = "address area",
                 .start  = IMX_CS5_PHYS,
                 .end    = IMX_CS5_PHYS + 1,
-                .flags  = IORESOURCE_MEM        /* address access */
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,       /* address access */
+        }, {
                 .name   = "data area",
                 .start  = IMX_CS5_PHYS + 4,
                 .end    = IMX_CS5_PHYS + 5,
-                .flags  = IORESOURCE_MEM        /* data access */
-        },
-        [2] = {
+                .flags  = IORESOURCE_MEM,       /* data access */
+        }, {
                 .start  = IRQ_GPIOC(3),
                 .end    = IRQ_GPIOC(3),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
         },
 };
 
@@ -154,7 +152,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328")
         .io_pg_offst    = ((0xe0200000) >> 18) & 0xfffc,
         .boot_params    = 0x08000100,
         .map_io         = mx1_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx1_init_irq,
         .timer          = &scb9328_timer,
         .init_machine   = scb9328_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
index c77da586b71d..c8a2eac4d13c 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-mx2/Kconfig
@@ -53,6 +53,34 @@ config MACH_PCM970_BASEBOARD
 
 endchoice
 
+config MACH_EUKREA_CPUIMX27
+        bool "Eukrea CPUIMX27 module"
+        depends on MACH_MX27
+        help
+          Include support for Eukrea CPUIMX27 platform. This includes
+          specific configurations for the module and its peripherals.
+
+config MACH_EUKREA_CPUIMX27_USESDHC2
+        bool "CPUIMX27 integrates SDHC2 module"
+        depends on MACH_EUKREA_CPUIMX27
+        help
+          This adds support for the internal SDHC2 used on CPUIMX27 used
+          for wifi or eMMC.
+
+choice
+        prompt "Baseboard"
+        depends on MACH_EUKREA_CPUIMX27
+        default MACH_EUKREA_MBIMX27_BASEBOARD
+
+config MACH_EUKREA_MBIMX27_BASEBOARD
+        prompt "Eukrea MBIMX27 development board"
+        bool
+        help
+          This adds board specific devices that can be found on Eukrea's
+          MBIMX27 evaluation board.
+
+endchoice
+
 config MACH_MX27_3DS
         bool "MX27PDK platform"
         depends on MACH_MX27
@@ -67,4 +95,11 @@ config MACH_MX27LITE
           Include support for MX27 LITEKIT platform. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_PCA100
+        bool "Phytec phyCARD-s (pca100)"
+        depends on MACH_MX27
+        help
+          Include support for phyCARD-s (aka pca100) platform. This
+          includes specific configurations for the module and its peripherals.
+
 endif
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index b9b1cca4e9bc..19560f045632 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -17,4 +17,7 @@ obj-$(CONFIG_MACH_PCM038) += pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
 obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o
 obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27.o
+obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
+obj-$(CONFIG_MACH_PCA100) += pca100.o
 
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c
index 0850fb88ec15..eede79855f4a 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-mx2/clock_imx21.c
@@ -1004,6 +1004,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
         clk_enable(&uart_clk[0]);
 #endif
 
-        mxc_timer_init(&gpt_clk[0]);
+        mxc_timer_init(&gpt_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);
         return 0;
 }
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index 2c971442f3f2..4089951acb47 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -643,7 +643,14 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "cspi3", cspi3_clk)
         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
         _REGISTER_CLOCK(NULL, "csi", csi_clk)
-        _REGISTER_CLOCK(NULL, "usb", usb_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
         _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk)
         _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk)
         _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
@@ -748,7 +755,7 @@ int __init mx27_clocks_init(unsigned long fref)
         clk_enable(&uart1_clk);
 #endif
 
-        mxc_timer_init(&gpt1_clk);
+        mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);
 
         return 0;
 }
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index a0f1b3674327..50199aff0143 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -40,45 +40,87 @@
 #include "devices.h"
 
 /*
- * Resource definition for the MXC IrDA
+ * SPI master controller
+ *
+ * - i.MX1: 2 channel (slighly different register setting)
+ * - i.MX21: 2 channel
+ * - i.MX27: 3 channel
  */
-static struct resource mxc_irda_resources[] = {
-        [0] = {
-                .start   = UART3_BASE_ADDR,
-                .end     = UART3_BASE_ADDR + SZ_4K - 1,
-                .flags   = IORESOURCE_MEM,
+static struct resource mxc_spi_resources0[] = {
+        {
+               .start = CSPI1_BASE_ADDR,
+               .end = CSPI1_BASE_ADDR + SZ_4K - 1,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = MXC_INT_CSPI1,
+               .end = MXC_INT_CSPI1,
+               .flags = IORESOURCE_IRQ,
         },
-        [1] = {
-                .start   = MXC_INT_UART3,
-                .end     = MXC_INT_UART3,
-                .flags   = IORESOURCE_IRQ,
+};
+
+static struct resource mxc_spi_resources1[] = {
+        {
+                .start = CSPI2_BASE_ADDR,
+                .end = CSPI2_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_CSPI2,
+                .end = MXC_INT_CSPI2,
+                .flags = IORESOURCE_IRQ,
         },
 };
 
-/* Platform Data for MXC IrDA */
-struct platform_device mxc_irda_device = {
-        .name = "mxc_irda",
+#ifdef CONFIG_MACH_MX27
+static struct resource mxc_spi_resources2[] = {
+        {
+                .start = CSPI3_BASE_ADDR,
+                .end = CSPI3_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_CSPI3,
+                .end = MXC_INT_CSPI3,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+#endif
+
+struct platform_device mxc_spi_device0 = {
+        .name = "spi_imx",
         .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_irda_resources),
-        .resource = mxc_irda_resources,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources0),
+        .resource = mxc_spi_resources0,
+};
+
+struct platform_device mxc_spi_device1 = {
+        .name = "spi_imx",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources1),
+        .resource = mxc_spi_resources1,
+};
+
+#ifdef CONFIG_MACH_MX27
+struct platform_device mxc_spi_device2 = {
+        .name = "spi_imx",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources2),
+        .resource = mxc_spi_resources2,
 };
+#endif
 
 /*
  * General Purpose Timer
- * - i.MX1: 2 timer (slighly different register handling)
- * - i.MX21: 3 timer
- * - i.MX27: 6 timer
+ * - i.MX21: 3 timers
+ * - i.MX27: 6 timers
  */
 
 /* We use gpt0 as system timer, so do not add a device for this one */
 
 static struct resource timer1_resources[] = {
-        [0] = {
+        {
                 .start  = GPT2_BASE_ADDR,
                 .end    = GPT2_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start   = MXC_INT_GPT2,
                 .end     = MXC_INT_GPT2,
                 .flags   = IORESOURCE_IRQ,
@@ -89,16 +131,15 @@ struct platform_device mxc_gpt1 = {
         .name = "imx_gpt",
         .id = 1,
         .num_resources = ARRAY_SIZE(timer1_resources),
-        .resource = timer1_resources
+        .resource = timer1_resources,
 };
 
 static struct resource timer2_resources[] = {
-        [0] = {
+        {
                 .start  = GPT3_BASE_ADDR,
                 .end    = GPT3_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start   = MXC_INT_GPT3,
                 .end     = MXC_INT_GPT3,
                 .flags   = IORESOURCE_IRQ,
@@ -109,17 +150,16 @@ struct platform_device mxc_gpt2 = {
         .name = "imx_gpt",
         .id = 2,
         .num_resources = ARRAY_SIZE(timer2_resources),
-        .resource = timer2_resources
+        .resource = timer2_resources,
 };
 
 #ifdef CONFIG_MACH_MX27
 static struct resource timer3_resources[] = {
-        [0] = {
+        {
                 .start  = GPT4_BASE_ADDR,
                 .end    = GPT4_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start   = MXC_INT_GPT4,
                 .end     = MXC_INT_GPT4,
                 .flags   = IORESOURCE_IRQ,
@@ -130,16 +170,15 @@ struct platform_device mxc_gpt3 = {
         .name = "imx_gpt",
         .id = 3,
         .num_resources = ARRAY_SIZE(timer3_resources),
-        .resource = timer3_resources
+        .resource = timer3_resources,
 };
 
 static struct resource timer4_resources[] = {
-        [0] = {
+        {
                 .start  = GPT5_BASE_ADDR,
                 .end    = GPT5_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start   = MXC_INT_GPT5,
                 .end     = MXC_INT_GPT5,
                 .flags   = IORESOURCE_IRQ,
@@ -150,16 +189,15 @@ struct platform_device mxc_gpt4 = {
         .name = "imx_gpt",
         .id = 4,
         .num_resources = ARRAY_SIZE(timer4_resources),
-        .resource = timer4_resources
+        .resource = timer4_resources,
 };
 
 static struct resource timer5_resources[] = {
-        [0] = {
+        {
                 .start  = GPT6_BASE_ADDR,
                 .end    = GPT6_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start   = MXC_INT_GPT6,
                 .end     = MXC_INT_GPT6,
                 .flags   = IORESOURCE_IRQ,
@@ -170,7 +208,7 @@ struct platform_device mxc_gpt5 = {
         .name = "imx_gpt",
         .id = 5,
         .num_resources = ARRAY_SIZE(timer5_resources),
-        .resource = timer5_resources
+        .resource = timer5_resources,
 };
 #endif
 
@@ -214,11 +252,11 @@ static struct resource mxc_nand_resources[] = {
         {
                 .start  = NFC_BASE_ADDR,
                 .end    = NFC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
         }, {
                 .start  = MXC_INT_NANDFC,
                 .end    = MXC_INT_NANDFC,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -240,8 +278,7 @@ static struct resource mxc_fb[] = {
                 .start = LCDC_BASE_ADDR,
                 .end   = LCDC_BASE_ADDR + 0xFFF,
                 .flags = IORESOURCE_MEM,
-        },
-        {
+        }, {
                 .start = MXC_INT_LCDC,
                 .end   = MXC_INT_LCDC,
                 .flags = IORESOURCE_IRQ,
@@ -264,11 +301,11 @@ static struct resource mxc_fec_resources[] = {
         {
                 .start  = FEC_BASE_ADDR,
                 .end    = FEC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
         }, {
                 .start  = MXC_INT_FEC,
                 .end    = MXC_INT_FEC,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -281,15 +318,14 @@ struct platform_device mxc_fec_device = {
 #endif
 
 static struct resource mxc_i2c_1_resources[] = {
-        [0] = {
+        {
                 .start  = I2C_BASE_ADDR,
                 .end    = I2C_BASE_ADDR + 0x0fff,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start  = MXC_INT_I2C,
                 .end    = MXC_INT_I2C,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
         }
 };
 
@@ -297,20 +333,19 @@ struct platform_device mxc_i2c_device0 = {
         .name = "imx-i2c",
         .id = 0,
         .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
-        .resource = mxc_i2c_1_resources
+        .resource = mxc_i2c_1_resources,
 };
 
 #ifdef CONFIG_MACH_MX27
 static struct resource mxc_i2c_2_resources[] = {
-        [0] = {
+        {
                 .start  = I2C2_BASE_ADDR,
                 .end    = I2C2_BASE_ADDR + 0x0fff,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start  = MXC_INT_I2C2,
                 .end    = MXC_INT_I2C2,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
         }
 };
 
@@ -318,17 +353,16 @@ struct platform_device mxc_i2c_device1 = {
         .name = "imx-i2c",
         .id = 1,
         .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
-        .resource = mxc_i2c_2_resources
+        .resource = mxc_i2c_2_resources,
 };
 #endif
 
 static struct resource mxc_pwm_resources[] = {
-        [0] = {
+        {
                 .start  = PWM_BASE_ADDR,
                 .end    = PWM_BASE_ADDR + 0x0fff,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start   = MXC_INT_PWM,
                 .end     = MXC_INT_PWM,
                 .flags   = IORESOURCE_IRQ,
@@ -339,28 +373,26 @@ struct platform_device mxc_pwm_device = {
         .name = "mxc_pwm",
         .id = 0,
         .num_resources = ARRAY_SIZE(mxc_pwm_resources),
-        .resource = mxc_pwm_resources
+        .resource = mxc_pwm_resources,
 };
 
 /*
  * Resource definition for the MXC SDHC
  */
 static struct resource mxc_sdhc1_resources[] = {
-        [0] = {
-                        .start = SDHC1_BASE_ADDR,
-                        .end   = SDHC1_BASE_ADDR + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                        },
-        [1] = {
-                        .start = MXC_INT_SDHC1,
-                        .end   = MXC_INT_SDHC1,
-                        .flags = IORESOURCE_IRQ,
-                        },
-        [2] = {
-                        .start  = DMA_REQ_SDHC1,
-                        .end    = DMA_REQ_SDHC1,
-                        .flags  = IORESOURCE_DMA
-                },
+        {
+                .start = SDHC1_BASE_ADDR,
+                .end   = SDHC1_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_SDHC1,
+                .end   = MXC_INT_SDHC1,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start  = DMA_REQ_SDHC1,
+                .end    = DMA_REQ_SDHC1,
+                .flags  = IORESOURCE_DMA,
+        },
 };
 
 static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
@@ -377,21 +409,19 @@ struct platform_device mxc_sdhc_device0 = {
 };
 
 static struct resource mxc_sdhc2_resources[] = {
-        [0] = {
-                        .start = SDHC2_BASE_ADDR,
-                        .end   = SDHC2_BASE_ADDR + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                        },
-        [1] = {
-                        .start = MXC_INT_SDHC2,
-                        .end   = MXC_INT_SDHC2,
-                        .flags = IORESOURCE_IRQ,
-                        },
-        [2] = {
-                        .start  = DMA_REQ_SDHC2,
-                        .end    = DMA_REQ_SDHC2,
-                        .flags  = IORESOURCE_DMA
-                },
+        {
+                .start = SDHC2_BASE_ADDR,
+                .end   = SDHC2_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_SDHC2,
+                .end   = MXC_INT_SDHC2,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start  = DMA_REQ_SDHC2,
+                .end    = DMA_REQ_SDHC2,
+                .flags  = IORESOURCE_DMA,
+        },
 };
 
 static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
@@ -407,35 +437,123 @@ struct platform_device mxc_sdhc_device1 = {
        .resource       = mxc_sdhc2_resources,
 };
 
+#ifdef CONFIG_MACH_MX27
+static struct resource otg_resources[] = {
+        {
+                .start  = OTG_BASE_ADDR,
+                .end    = OTG_BASE_ADDR + 0x1ff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MXC_INT_USB3,
+                .end    = MXC_INT_USB3,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 otg_dmamask = 0xffffffffUL;
+
+/* OTG gadget device */
+struct platform_device mxc_otg_udc_device = {
+        .name           = "fsl-usb2-udc",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &otg_dmamask,
+                .coherent_dma_mask      = 0xffffffffUL,
+        },
+        .resource       = otg_resources,
+        .num_resources  = ARRAY_SIZE(otg_resources),
+};
+
+/* OTG host */
+struct platform_device mxc_otg_host = {
+        .name = "mxc-ehci",
+        .id = 0,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &otg_dmamask,
+        },
+        .resource = otg_resources,
+        .num_resources = ARRAY_SIZE(otg_resources),
+};
+
+/* USB host 1 */
+
+static u64 usbh1_dmamask = 0xffffffffUL;
+
+static struct resource mxc_usbh1_resources[] = {
+        {
+                .start = OTG_BASE_ADDR + 0x200,
+                .end = OTG_BASE_ADDR + 0x3ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_USB1,
+                .end = MXC_INT_USB1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_usbh1 = {
+        .name = "mxc-ehci",
+        .id = 1,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh1_dmamask,
+        },
+        .resource = mxc_usbh1_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
+};
+
+/* USB host 2 */
+static u64 usbh2_dmamask = 0xffffffffUL;
+
+static struct resource mxc_usbh2_resources[] = {
+        {
+                .start = OTG_BASE_ADDR + 0x400,
+                .end = OTG_BASE_ADDR + 0x5ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_USB2,
+                .end = MXC_INT_USB2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_usbh2 = {
+        .name = "mxc-ehci",
+        .id = 2,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh2_dmamask,
+        },
+        .resource = mxc_usbh2_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
+};
+#endif
+
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
-        [0] = {
+        {
                 .chip.label = "gpio-0",
                 .irq = MXC_INT_GPIO,
                 .base = IO_ADDRESS(GPIO_BASE_ADDR),
                 .virtual_irq_start = MXC_GPIO_IRQ_START,
-        },
-        [1] = {
+        }, {
                 .chip.label = "gpio-1",
                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-        },
-        [2] = {
+        }, {
                 .chip.label = "gpio-2",
                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
-        },
-        [3] = {
+        }, {
                 .chip.label = "gpio-3",
                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
-        },
-        [4] = {
+        }, {
                 .chip.label = "gpio-4",
                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
-        },
-        [5] = {
+        }, {
                 .chip.label = "gpio-5",
                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
index 049005bb6aa9..d315406d6725 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-mx2/devices.h
@@ -4,7 +4,6 @@ extern struct platform_device mxc_gpt3;
 extern struct platform_device mxc_gpt4;
 extern struct platform_device mxc_gpt5;
 extern struct platform_device mxc_wdt;
-extern struct platform_device mxc_irda_device;
 extern struct platform_device mxc_uart_device0;
 extern struct platform_device mxc_uart_device1;
 extern struct platform_device mxc_uart_device2;
@@ -20,3 +19,11 @@ extern struct platform_device mxc_i2c_device0;
 extern struct platform_device mxc_i2c_device1;
 extern struct platform_device mxc_sdhc_device0;
 extern struct platform_device mxc_sdhc_device1;
+extern struct platform_device mxc_otg_udc_device;
+extern struct platform_device mxc_otg_host;
+extern struct platform_device mxc_usbh1;
+extern struct platform_device mxc_usbh2;
+extern struct platform_device mxc_spi_device0;
+extern struct platform_device mxc_spi_device1;
+extern struct platform_device mxc_spi_device2;
+
diff --git a/arch/arm/mach-mx2/eukrea_cpuimx27.c b/arch/arm/mach-mx2/eukrea_cpuimx27.c
new file mode 100644
index 000000000000..7b187606682c
--- /dev/null
+++ b/arch/arm/mach-mx2/eukrea_cpuimx27.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm038.c which is :
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/board-eukrea_cpuimx27.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/i2c.h>
+#include <mach/iomux.h>
+#include <mach/imx-uart.h>
+#include <mach/mxc_nand.h>
+
+#include "devices.h"
+
+static int eukrea_cpuimx27_pins[] = {
+        /* UART1 */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS,
+        /* UART4 */
+        PB26_AF_UART4_RTS,
+        PB28_AF_UART4_TXD,
+        PB29_AF_UART4_CTS,
+        PB31_AF_UART4_RXD,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+        /* I2C1 */
+        PD17_PF_I2C_DATA,
+        PD18_PF_I2C_CLK,
+        /* SDHC2 */
+        PB4_PF_SD2_D0,
+        PB5_PF_SD2_D1,
+        PB6_PF_SD2_D2,
+        PB7_PF_SD2_D3,
+        PB8_PF_SD2_CMD,
+        PB9_PF_SD2_CLK,
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+        /* Quad UART's IRQ */
+        GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN,
+#endif
+};
+
+static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
+        .width = 2,
+};
+
+static struct resource eukrea_cpuimx27_flash_resource = {
+        .start = 0xc0000000,
+        .end   = 0xc3ffffff,
+        .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &eukrea_cpuimx27_flash_data,
+        },
+        .num_resources = 1,
+        .resource = &eukrea_cpuimx27_flash_resource,
+};
+
+static struct imxuart_platform_data uart_pdata[] = {
+        {
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+};
+
+static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+        &eukrea_cpuimx27_nor_mtd_device,
+        &mxc_fec_device,
+};
+
+static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = {
+        .bitrate = 100000,
+};
+
+static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        },
+};
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+static struct plat_serial8250_port serial_platform_data[] = {
+        {
+                .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x200000),
+                .irq = IRQ_GPIOB(23),
+                .uartclk = 14745600,
+                .regshift = 1,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x400000),
+                .irq = IRQ_GPIOB(22),
+                .uartclk = 14745600,
+                .regshift = 1,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x800000),
+                .irq = IRQ_GPIOB(27),
+                .uartclk = 14745600,
+                .regshift = 1,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x1000000),
+                .irq = IRQ_GPIOB(30),
+                .uartclk = 14745600,
+                .regshift = 1,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+        }
+};
+
+static struct platform_device serial_device = {
+        .name = "serial8250",
+        .id = 0,
+        .dev = {
+                .platform_data = serial_platform_data,
+        },
+};
+#endif
+
+static void __init eukrea_cpuimx27_init(void)
+{
+        mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
+                ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
+
+        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+
+        mxc_register_device(&mxc_nand_device, &eukrea_cpuimx27_nand_board_info);
+
+        i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
+                                ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
+
+        mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data);
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
+        /* SDHC2 can be used for Wifi */
+        mxc_register_device(&mxc_sdhc_device1, NULL);
+        /* in which case UART4 is also used for Bluetooth */
+        mxc_register_device(&mxc_uart_device3, &uart_pdata[1]);
+#endif
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+        platform_device_register(&serial_device);
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
+        eukrea_mbimx27_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx27_timer_init(void)
+{
+        mx27_clocks_init(26000000);
+}
+
+static struct sys_timer eukrea_cpuimx27_timer = {
+        .init = eukrea_cpuimx27_timer_init,
+};
+
+MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx27_map_io,
+        .init_irq       = mx27_init_irq,
+        .init_machine   = eukrea_cpuimx27_init,
+        .timer          = &eukrea_cpuimx27_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
new file mode 100644
index 000000000000..7382b6d27ee1
--- /dev/null
+++ b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
+
+#include <asm/mach/arch.h>
+
+#include <mach/common.h>
+#include <mach/iomux.h>
+#include <mach/imxfb.h>
+#include <mach/hardware.h>
+#include <mach/mmc.h>
+#include <mach/imx-uart.h>
+
+#include "devices.h"
+
+static int eukrea_mbimx27_pins[] = {
+        /* UART2 */
+        PE3_PF_UART2_CTS,
+        PE4_PF_UART2_RTS,
+        PE6_PF_UART2_TXD,
+        PE7_PF_UART2_RXD,
+        /* UART3 */
+        PE8_PF_UART3_TXD,
+        PE9_PF_UART3_RXD,
+        PE10_PF_UART3_CTS,
+        PE11_PF_UART3_RTS,
+        /* UART4 */
+        PB26_AF_UART4_RTS,
+        PB28_AF_UART4_TXD,
+        PB29_AF_UART4_CTS,
+        PB31_AF_UART4_RXD,
+        /* SDHC1*/
+        PE18_PF_SD1_D0,
+        PE19_PF_SD1_D1,
+        PE20_PF_SD1_D2,
+        PE21_PF_SD1_D3,
+        PE22_PF_SD1_CMD,
+        PE23_PF_SD1_CLK,
+        /* display */
+        PA5_PF_LSCLK,
+        PA6_PF_LD0,
+        PA7_PF_LD1,
+        PA8_PF_LD2,
+        PA9_PF_LD3,
+        PA10_PF_LD4,
+        PA11_PF_LD5,
+        PA12_PF_LD6,
+        PA13_PF_LD7,
+        PA14_PF_LD8,
+        PA15_PF_LD9,
+        PA16_PF_LD10,
+        PA17_PF_LD11,
+        PA18_PF_LD12,
+        PA19_PF_LD13,
+        PA20_PF_LD14,
+        PA21_PF_LD15,
+        PA22_PF_LD16,
+        PA23_PF_LD17,
+        PA28_PF_HSYNC,
+        PA29_PF_VSYNC,
+        PA30_PF_CONTRAST,
+        PA31_PF_OE_ACD,
+        /* SPI1 */
+        PD28_PF_CSPI1_SS0,
+        PD29_PF_CSPI1_SCLK,
+        PD30_PF_CSPI1_MISO,
+        PD31_PF_CSPI1_MOSI,
+};
+
+static struct gpio_led gpio_leds[] = {
+        {
+                .name                   = "led1",
+                .default_trigger        = "heartbeat",
+                .active_low             = 1,
+                .gpio                   = GPIO_PORTF | 16,
+        },
+        {
+                .name                   = "led2",
+                .default_trigger        = "none",
+                .active_low             = 1,
+                .gpio                   = GPIO_PORTF | 19,
+        },
+        {
+                .name                   = "backlight",
+                .default_trigger        = "backlight",
+                .active_low             = 0,
+                .gpio                   = GPIO_PORTE | 5,
+        },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_led_info,
+        },
+};
+
+static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
+        {
+                .mode = {
+                        .name           = "CMO-QGVA",
+                        .refresh        = 60,
+                        .xres           = 320,
+                        .yres           = 240,
+                        .pixclock       = 156000,
+                        .hsync_len      = 30,
+                        .left_margin    = 38,
+                        .right_margin   = 20,
+                        .vsync_len      = 3,
+                        .upper_margin   = 15,
+                        .lower_margin   = 4,
+                },
+                .pcr            = 0xFAD08B80,
+                .bpp            = 16,
+        },
+};
+
+static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
+        .mode = eukrea_mbimx27_modes,
+        .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
+
+        .pwmr           = 0x00A903FF,
+        .lscr1          = 0x00120300,
+        .dmacr          = 0x00040060,
+};
+
+static struct imxuart_platform_data uart_pdata[] = {
+        {
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+        {
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+};
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846)
+        || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+
+#define ADS7846_PENDOWN (GPIO_PORTD | 25)
+
+static void ads7846_dev_init(void)
+{
+        if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
+                printk(KERN_ERR "can't get ads746 pen down GPIO\n");
+                return;
+        }
+
+        gpio_direction_input(ADS7846_PENDOWN);
+}
+
+static int ads7846_get_pendown_state(void)
+{
+        return !gpio_get_value(ADS7846_PENDOWN);
+}
+
+static struct ads7846_platform_data ads7846_config __initdata = {
+        .get_pendown_state      = ads7846_get_pendown_state,
+        .keep_vref_on           = 1,
+};
+
+static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
+        [0] = {
+                .modalias       = "ads7846",
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .max_speed_hz   = 1500000,
+                .irq            = IRQ_GPIOD(25),
+                .platform_data  = &ads7846_config,
+                .mode           = SPI_MODE_2,
+        },
+};
+
+static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
+
+static struct spi_imx_master eukrea_mbimx27_spi_0_data = {
+        .chipselect     = eukrea_mbimx27_spi_cs,
+        .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
+};
+#endif
+
+static struct platform_device *platform_devices[] __initdata = {
+        &leds_gpio,
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx27 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimx27_baseboard_init(void)
+{
+        mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
+                ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
+
+        mxc_register_device(&mxc_uart_device1, &uart_pdata[0]);
+        mxc_register_device(&mxc_uart_device2, &uart_pdata[1]);
+
+        mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
+        mxc_register_device(&mxc_sdhc_device0, NULL);
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846)
+        || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+        /* SPI and ADS7846 Touchscreen controler init */
+        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+        mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
+        mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data);
+        spi_register_board_info(eukrea_mbimx27_spi_board_info,
+                        ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
+        ads7846_dev_init();
+#endif
+
+        /* Leds configuration */
+        mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
+        mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
+        /* Backlight */
+        mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c
index 169372f69d8f..ae8f759134d1 100644
--- a/arch/arm/mach-mx2/generic.c
+++ b/arch/arm/mach-mx2/generic.c
@@ -72,6 +72,7 @@ static struct map_desc mxc_io_desc[] __initdata = {
 void __init mx21_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX21);
+        mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
 
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
@@ -79,7 +80,18 @@ void __init mx21_map_io(void)
 void __init mx27_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX27);
+        mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
 
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+void __init mx27_init_irq(void)
+{
+        mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+}
+
+void __init mx21_init_irq(void)
+{
+        mx27_init_irq();
+}
+
diff --git a/arch/arm/mach-mx2/mx21ads.c b/arch/arm/mach-mx2/mx21ads.c
index a5ee461cb405..cf5f77cbc2f1 100644
--- a/arch/arm/mach-mx2/mx21ads.c
+++ b/arch/arm/mach-mx2/mx21ads.c
@@ -164,25 +164,33 @@ static void mx21ads_fb_exit(struct platform_device *pdev)
  * Connected is a portrait Sharp-QVGA display
  * of type: LQ035Q7DB02
  */
-static struct imx_fb_platform_data mx21ads_fb_data = {
-        .pixclock       = 188679, /* in ps */
-        .xres           = 240,
-        .yres           = 320,
-
-        .bpp            = 16,
-        .hsync_len      = 2,
-        .left_margin    = 6,
-        .right_margin   = 16,
+static struct imx_fb_videomode mx21ads_modes[] = {
+        {
+                .mode = {
+                        .name           = "Sharp-LQ035Q7",
+                        .refresh        = 60,
+                        .xres           = 240,
+                        .yres           = 320,
+                        .pixclock       = 188679, /* in ps (5.3MHz) */
+                        .hsync_len      = 2,
+                        .left_margin    = 6,
+                        .right_margin   = 16,
+                        .vsync_len      = 1,
+                        .upper_margin   = 8,
+                        .lower_margin   = 10,
+                },
+                .pcr            = 0xfb108bc7,
+                .bpp            = 16,
+        },
+};
 
-        .vsync_len      = 1,
-        .upper_margin   = 8,
-        .lower_margin   = 10,
-        .fixed_screen_cpu = 0,
+static struct imx_fb_platform_data mx21ads_fb_data = {
+        .mode = mx21ads_modes,
+        .num_modes = ARRAY_SIZE(mx21ads_modes),
 
-        .pcr            = 0xFB108BC7,
-        .pwmr           = 0x00A901ff,
-        .lscr1          = 0x00120300,
-        .dmacr          = 0x00020008,
+        .pwmr           = 0x00a903ff,
+        .lscr1          = 0x00120300,
+        .dmacr          = 0x00020008,
 
         .init = mx21ads_fb_init,
         .exit = mx21ads_fb_exit,
@@ -280,7 +288,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
         .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx21ads_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx21_init_irq,
         .init_machine   = mx21ads_board_init,
         .timer          = &mx21ads_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
index 02daddac6995..83e412b713e6 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -183,20 +183,29 @@ void lcd_power(int on)
                 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
 }
 
-static struct imx_fb_platform_data mx27ads_fb_data = {
-        .pixclock       = 188679,
-        .xres           = 240,
-        .yres           = 320,
-
-        .bpp            = 16,
-        .hsync_len      = 1,
-        .left_margin    = 9,
-        .right_margin   = 16,
+static struct imx_fb_videomode mx27ads_modes[] = {
+        {
+                .mode = {
+                        .name           = "Sharp-LQ035Q7",
+                        .refresh        = 60,
+                        .xres           = 240,
+                        .yres           = 320,
+                        .pixclock       = 188679, /* in ps (5.3MHz) */
+                        .hsync_len      = 1,
+                        .left_margin    = 9,
+                        .right_margin   = 16,
+                        .vsync_len      = 1,
+                        .upper_margin   = 7,
+                        .lower_margin   = 9,
+                },
+                .bpp            = 16,
+                .pcr            = 0xFB008BC0,
+        },
+};
 
-        .vsync_len      = 1,
-        .upper_margin   = 7,
-        .lower_margin   = 9,
-        .fixed_screen_cpu = 0,
+static struct imx_fb_platform_data mx27ads_fb_data = {
+        .mode = mx27ads_modes,
+        .num_modes = ARRAY_SIZE(mx27ads_modes),
 
         /*
          * - HSYNC active high
@@ -207,7 +216,6 @@ static struct imx_fb_platform_data mx27ads_fb_data = {
          * - data enable low active
          * - enable sharp mode
          */
-        .pcr            = 0xFB008BC0,
         .pwmr           = 0x00A903FF,
         .lscr1          = 0x00120300,
         .dmacr          = 0x00020010,
@@ -330,7 +338,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
         .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx27ads_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx27_init_irq,
         .init_machine   = mx27ads_board_init,
         .timer          = &mx27ads_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27lite.c b/arch/arm/mach-mx2/mx27lite.c
index 3ae11cb8c04b..82ea227ea0cf 100644
--- a/arch/arm/mach-mx2/mx27lite.c
+++ b/arch/arm/mach-mx2/mx27lite.c
@@ -89,7 +89,7 @@ MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
         .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx27_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx27_init_irq,
         .init_machine   = mx27lite_init,
         .timer          = &mx27lite_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27pdk.c b/arch/arm/mach-mx2/mx27pdk.c
index 1d9238c7a6c3..6761d1b79e43 100644
--- a/arch/arm/mach-mx2/mx27pdk.c
+++ b/arch/arm/mach-mx2/mx27pdk.c
@@ -89,7 +89,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK")
         .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx27_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx27_init_irq,
         .init_machine   = mx27pdk_init,
         .timer          = &mx27pdk_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/pca100.c b/arch/arm/mach-mx2/pca100.c
new file mode 100644
index 000000000000..fe5b165b88cc
--- /dev/null
+++ b/arch/arm/mach-mx2/pca100.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/dma-mapping.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/eeprom.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux.h>
+#include <mach/i2c.h>
+#include <asm/mach/time.h>
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+#include <mach/spi.h>
+#endif
+#include <mach/imx-uart.h>
+#include <mach/mxc_nand.h>
+#include <mach/irqs.h>
+#include <mach/mmc.h>
+
+#include "devices.h"
+
+static int pca100_pins[] = {
+        /* UART1 */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS,
+        /* SDHC */
+        PB4_PF_SD2_D0,
+        PB5_PF_SD2_D1,
+        PB6_PF_SD2_D2,
+        PB7_PF_SD2_D3,
+        PB8_PF_SD2_CMD,
+        PB9_PF_SD2_CLK,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+        /* SSI1 */
+        PC20_PF_SSI1_FS,
+        PC21_PF_SSI1_RXD,
+        PC22_PF_SSI1_TXD,
+        PC23_PF_SSI1_CLK,
+        /* onboard I2C */
+        PC5_PF_I2C2_SDA,
+        PC6_PF_I2C2_SCL,
+        /* external I2C */
+        PD17_PF_I2C_DATA,
+        PD18_PF_I2C_CLK,
+        /* SPI1 */
+        PD25_PF_CSPI1_RDY,
+        PD29_PF_CSPI1_SCLK,
+        PD30_PF_CSPI1_MISO,
+        PD31_PF_CSPI1_MOSI,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct mxc_nand_platform_data pca100_nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+        &mxc_w1_master_device,
+        &mxc_fec_device,
+};
+
+static struct imxi2c_platform_data pca100_i2c_1_data = {
+        .bitrate = 100000,
+};
+
+static struct at24_platform_data board_eeprom = {
+        .byte_len = 4096,
+        .page_size = 32,
+        .flags = AT24_FLAG_ADDR16,
+};
+
+static struct i2c_board_info pca100_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
+                .platform_data = &board_eeprom,
+        }, {
+                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
+                .type = "pcf8563"
+        }, {
+                I2C_BOARD_INFO("lm75", 0x4a),
+                .type = "lm75"
+        }
+};
+
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+static struct spi_eeprom at25320 = {
+        .name           = "at25320an",
+        .byte_len       = 4096,
+        .page_size      = 32,
+        .flags          = EE_ADDR2,
+};
+
+static struct spi_board_info pca100_spi_board_info[] __initdata = {
+        {
+                .modalias = "at25",
+                .max_speed_hz = 30000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .platform_data = &at25320,
+        },
+};
+
+static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
+
+static struct spi_imx_master pca100_spi_0_data = {
+        .chipselect     = pca100_spi_cs,
+        .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
+};
+#endif
+
+static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
+                void *data)
+{
+        int ret;
+
+        ret = request_irq(IRQ_GPIOC(29), detect_irq,
+                          IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+                          "imx-mmc-detect", data);
+        if (ret)
+                printk(KERN_ERR
+                        "pca100: Failed to reuest irq for sd/mmc detection\n");
+
+        return ret;
+}
+
+static void pca100_sdhc2_exit(struct device *dev, void *data)
+{
+        free_irq(IRQ_GPIOC(29), data);
+}
+
+static struct imxmmc_platform_data sdhc_pdata = {
+        .init = pca100_sdhc2_init,
+        .exit = pca100_sdhc2_exit,
+};
+
+static void __init pca100_init(void)
+{
+        int ret;
+
+        ret = mxc_gpio_setup_multiple_pins(pca100_pins,
+                        ARRAY_SIZE(pca100_pins), "PCA100");
+        if (ret)
+                printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
+
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+
+        mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
+        mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
+
+        mxc_register_device(&mxc_nand_device, &pca100_nand_board_info);
+
+        /* only the i2c master 1 is used on this CPU card */
+        i2c_register_board_info(1, pca100_i2c_devices,
+                                ARRAY_SIZE(pca100_i2c_devices));
+
+        mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data);
+
+        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+        mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
+
+        /* GPIO0_IRQ */
+        mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
+        /* GPIO1_IRQ */
+        mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
+        /* GPIO2_IRQ */
+        mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
+
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+        spi_register_board_info(pca100_spi_board_info,
+                                ARRAY_SIZE(pca100_spi_board_info));
+        mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
+#endif
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+static void __init pca100_timer_init(void)
+{
+        mx27_clocks_init(26000000);
+}
+
+static struct sys_timer pca100_timer = {
+        .init = pca100_timer_init,
+};
+
+MACHINE_START(PCA100, "phyCARD-i.MX27")
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx27_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = pca100_init,
+        .timer          = &pca100_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
index a4628d004343..ee65dda584cf 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -186,17 +186,13 @@ static struct at24_platform_data board_eeprom = {
 };
 
 static struct i2c_board_info pcm038_i2c_devices[] = {
-        [0] = {
+        {
                 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
                 .platform_data = &board_eeprom,
-        },
-        [1] = {
-                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
-                .type = "pcf8563"
-        },
-        [2] = {
+        }, {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        }, {
                 I2C_BOARD_INFO("lm75", 0x4a),
-                .type = "lm75"
         }
 };
 
@@ -220,6 +216,9 @@ static void __init pcm038_init(void)
 
         mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
 
+        /* PE18 for user-LED D40 */
+        mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
+
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
 #ifdef CONFIG_MACH_PCM970_BASEBOARD
@@ -241,7 +240,7 @@ MACHINE_START(PCM038, "phyCORE-i.MX27")
         .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx27_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx27_init_irq,
         .init_machine   = pcm038_init,
         .timer          = &pcm038_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
index 6a3acaf57dd4..c261f59b0b4c 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -19,6 +19,7 @@
 #include <linux/gpio.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/can/platform/sja1000.h>
 
 #include <asm/mach/arch.h>
 
@@ -125,40 +126,96 @@ static struct imxmmc_platform_data sdhc_pdata = {
         .exit = pcm970_sdhc2_exit,
 };
 
-/*
- * Connected is a portrait Sharp-QVGA display
- * of type: LQ035Q7DH06
- */
-static struct imx_fb_platform_data pcm038_fb_data = {
-        .pixclock       = 188679, /* in ps (5.3MHz) */
-        .xres           = 240,
-        .yres           = 320,
-
-        .bpp            = 16,
-        .hsync_len      = 7,
-        .left_margin    = 5,
-        .right_margin   = 16,
+static struct imx_fb_videomode pcm970_modes[] = {
+        {
+                .mode = {
+                        .name           = "Sharp-LQ035Q7",
+                        .refresh        = 60,
+                        .xres           = 240,
+                        .yres           = 320,
+                        .pixclock       = 188679, /* in ps (5.3MHz) */
+                        .hsync_len      = 7,
+                        .left_margin    = 5,
+                        .right_margin   = 16,
+                        .vsync_len      = 1,
+                        .upper_margin   = 7,
+                        .lower_margin   = 9,
+                },
+                /*
+                 * - HSYNC active high
+                 * - VSYNC active high
+                 * - clk notenabled while idle
+                 * - clock not inverted
+                 * - data not inverted
+                 * - data enable low active
+                 * - enable sharp mode
+                 */
+                .pcr            = 0xF00080C0,
+                .bpp            = 16,
+        }, {
+                .mode = {
+                        .name           = "TX090",
+                        .refresh        = 60,
+                        .xres           = 240,
+                        .yres           = 320,
+                        .pixclock       = 38255,
+                        .left_margin    = 144,
+                        .right_margin   = 0,
+                        .upper_margin   = 7,
+                        .lower_margin   = 40,
+                        .hsync_len      = 96,
+                        .vsync_len      = 1,
+                },
+                /*
+                 * - HSYNC active low (1 << 22)
+                 * - VSYNC active low (1 << 23)
+                 * - clk notenabled while idle
+                 * - clock not inverted
+                 * - data not inverted
+                 * - data enable low active
+                 * - enable sharp mode
+                 */
+                .pcr = 0xF0008080 | (1<<22) | (1<<23) | (1<<19),
+                .bpp = 32,
+        },
+};
 
-        .vsync_len      = 1,
-        .upper_margin   = 7,
-        .lower_margin   = 9,
-        .fixed_screen_cpu = 0,
+static struct imx_fb_platform_data pcm038_fb_data = {
+        .mode = pcm970_modes,
+        .num_modes = ARRAY_SIZE(pcm970_modes),
 
-        /*
-         * - HSYNC active high
-         * - VSYNC active high
-         * - clk notenabled while idle
-         * - clock not inverted
-         * - data not inverted
-         * - data enable low active
-         * - enable sharp mode
-         */
-        .pcr            = 0xFA0080C0,
         .pwmr           = 0x00A903FF,
         .lscr1          = 0x00120300,
         .dmacr          = 0x00020010,
 };
 
+static struct resource pcm970_sja1000_resources[] = {
+        {
+                .start   = CS4_BASE_ADDR,
+                .end     = CS4_BASE_ADDR + 0x100 - 1,
+                .flags   = IORESOURCE_MEM,
+        }, {
+                .start   = IRQ_GPIOE(19),
+                .end     = IRQ_GPIOE(19),
+                .flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
+        },
+};
+
+struct sja1000_platform_data pcm970_sja1000_platform_data = {
+        .clock          = 16000000 / 2,
+        .ocr            = 0x40 | 0x18,
+        .cdr            = 0x40,
+};
+
+static struct platform_device pcm970_sja1000 = {
+        .name = "sja1000_platform",
+        .dev = {
+                .platform_data = &pcm970_sja1000_platform_data,
+        },
+        .resource = pcm970_sja1000_resources,
+        .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
+};
+
 /*
  * system init for baseboard usage. Will be called by pcm038 init.
  *
@@ -172,4 +229,5 @@ void __init pcm970_baseboard_init(void)
 
         mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
         mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
+        platform_device_register(&pcm970_sja1000);
 }
diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
new file mode 100644
index 000000000000..cc28f56eae80
--- /dev/null
+++ b/arch/arm/mach-mx25/Kconfig
@@ -0,0 +1,9 @@
+if ARCH_MX25
+
+comment "MX25 platforms:"
+
+config MACH_MX25_3DS
+        select ARCH_MXC_IOMUX_V3
+        bool "Support MX25PDK (3DS) Platform"
+
+endif
diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile
new file mode 100644
index 000000000000..fe23836a9f3d
--- /dev/null
+++ b/arch/arm/mach-mx25/Makefile
@@ -0,0 +1,3 @@
+obj-y                           := mm.o devices.o
+obj-$(CONFIG_ARCH_MX25)         += clock.o
+obj-$(CONFIG_MACH_MX25_3DS)     += mx25pdk.o
diff --git a/arch/arm/mach-mx25/Makefile.boot b/arch/arm/mach-mx25/Makefile.boot
new file mode 100644
index 000000000000..e1dd366f836b
--- /dev/null
+++ b/arch/arm/mach-mx25/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x80008000
+params_phys-y   := 0x80000100
+initrd_phys-y   := 0x80800000
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
new file mode 100644
index 000000000000..ef26951a5275
--- /dev/null
+++ b/arch/arm/mach-mx25/clock.c
@@ -0,0 +1,219 @@
+/*
+ * Copyright (C) 2009 by Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/clkdev.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/mx25.h>
+
+#define CRM_BASE        MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
+
+#define CCM_MPCTL       0x00
+#define CCM_UPCTL       0x04
+#define CCM_CCTL        0x08
+#define CCM_CGCR0       0x0C
+#define CCM_CGCR1       0x10
+#define CCM_CGCR2       0x14
+#define CCM_PCDR0       0x18
+#define CCM_PCDR1       0x1C
+#define CCM_PCDR2       0x20
+#define CCM_PCDR3       0x24
+#define CCM_RCSR        0x28
+#define CCM_CRDR        0x2C
+#define CCM_DCVR0       0x30
+#define CCM_DCVR1       0x34
+#define CCM_DCVR2       0x38
+#define CCM_DCVR3       0x3c
+#define CCM_LTR0        0x40
+#define CCM_LTR1        0x44
+#define CCM_LTR2        0x48
+#define CCM_LTR3        0x4c
+
+static unsigned long get_rate_mpll(void)
+{
+        ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL);
+
+        return mxc_decode_pll(mpctl, 24000000);
+}
+
+static unsigned long get_rate_upll(void)
+{
+        ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL);
+
+        return mxc_decode_pll(mpctl, 24000000);
+}
+
+unsigned long get_rate_arm(struct clk *clk)
+{
+        unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
+        unsigned long rate = get_rate_mpll();
+
+        if (cctl & (1 << 14))
+                rate = (rate * 3) >> 1;
+
+        return rate / ((cctl >> 30) + 1);
+}
+
+static unsigned long get_rate_ahb(struct clk *clk)
+{
+        unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
+
+        return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1);
+}
+
+static unsigned long get_rate_ipg(struct clk *clk)
+{
+        return get_rate_ahb(NULL) >> 1;
+}
+
+static unsigned long get_rate_per(int per)
+{
+        unsigned long ofs = (per & 0x3) * 8;
+        unsigned long reg = per & ~0x3;
+        unsigned long val = (readl(CRM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f;
+        unsigned long fref;
+
+        if (readl(CRM_BASE + 0x64) & (1 << per))
+                fref = get_rate_upll();
+        else
+                fref = get_rate_ipg(NULL);
+
+        return fref / (val + 1);
+}
+
+static unsigned long get_rate_uart(struct clk *clk)
+{
+        return get_rate_per(15);
+}
+
+static unsigned long get_rate_i2c(struct clk *clk)
+{
+        return get_rate_per(6);
+}
+
+static unsigned long get_rate_nfc(struct clk *clk)
+{
+        return get_rate_per(8);
+}
+
+static unsigned long get_rate_otg(struct clk *clk)
+{
+        return 48000000; /* FIXME */
+}
+
+static int clk_cgcr_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void clk_cgcr_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+#define DEFINE_CLOCK(name, i, er, es, gr, sr)           \
+        static struct clk name = {                      \
+                .id             = i,                    \
+                .enable_reg     = CRM_BASE + er,        \
+                .enable_shift   = es,                   \
+                .get_rate       = gr,                   \
+                .set_rate       = sr,                   \
+                .enable         = clk_cgcr_enable,      \
+                .disable        = clk_cgcr_disable,     \
+        }
+
+DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL);
+DEFINE_CLOCK(uart1_clk,  0, CCM_CGCR2, 14, get_rate_uart, NULL);
+DEFINE_CLOCK(uart2_clk,  0, CCM_CGCR2, 15, get_rate_uart, NULL);
+DEFINE_CLOCK(uart3_clk,  0, CCM_CGCR2, 16, get_rate_uart, NULL);
+DEFINE_CLOCK(uart4_clk,  0, CCM_CGCR2, 17, get_rate_uart, NULL);
+DEFINE_CLOCK(uart5_clk,  0, CCM_CGCR2, 18, get_rate_uart, NULL);
+DEFINE_CLOCK(nfc_clk,    0, CCM_CGCR0,  8, get_rate_nfc, NULL);
+DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL);
+DEFINE_CLOCK(pwm1_clk,   0, CCM_CGCR1, 31, get_rate_ipg, NULL);
+DEFINE_CLOCK(pwm2_clk,   0, CCM_CGCR2,  0, get_rate_ipg, NULL);
+DEFINE_CLOCK(pwm3_clk,   0, CCM_CGCR2,  1, get_rate_ipg, NULL);
+DEFINE_CLOCK(pwm4_clk,   0, CCM_CGCR2,  2, get_rate_ipg, NULL);
+DEFINE_CLOCK(kpp_clk,    0, CCM_CGCR1, 28, get_rate_ipg, NULL);
+DEFINE_CLOCK(tsc_clk,    0, CCM_CGCR2, 13, get_rate_ipg, NULL);
+DEFINE_CLOCK(i2c_clk,    0, CCM_CGCR0,  6, get_rate_i2c, NULL);
+
+#define _REGISTER_CLOCK(d, n, c)        \
+        {                               \
+                .dev_id = d,            \
+                .con_id = n,            \
+                .clk = &c,              \
+        },
+
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+        _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
+        _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
+        _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
+        _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
+        _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
+        _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
+        _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
+        _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
+        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
+        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
+};
+
+int __init mx25_clocks_init(unsigned long fref)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+
+        mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
+
+        return 0;
+}
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
new file mode 100644
index 000000000000..eb12de1da42d
--- /dev/null
+++ b/arch/arm/mach-mx25/devices.c
@@ -0,0 +1,402 @@
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <mach/mx25.h>
+#include <mach/irqs.h>
+
+static struct resource uart0[] = {
+        {
+                .start = 0x43f90000,
+                .end = 0x43f93fff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 45,
+                .end = 45,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device0 = {
+        .name = "imx-uart",
+        .id = 0,
+        .resource = uart0,
+        .num_resources = ARRAY_SIZE(uart0),
+};
+
+static struct resource uart1[] = {
+        {
+                .start = 0x43f94000,
+                .end = 0x43f97fff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 32,
+                .end = 32,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device1 = {
+        .name = "imx-uart",
+        .id = 1,
+        .resource = uart1,
+        .num_resources = ARRAY_SIZE(uart1),
+};
+
+static struct resource uart2[] = {
+        {
+                .start = 0x5000c000,
+                .end = 0x5000ffff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 18,
+                .end = 18,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device2 = {
+        .name = "imx-uart",
+        .id = 2,
+        .resource = uart2,
+        .num_resources = ARRAY_SIZE(uart2),
+};
+
+static struct resource uart3[] = {
+        {
+                .start = 0x50008000,
+                .end = 0x5000bfff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 5,
+                .end = 5,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device3 = {
+        .name = "imx-uart",
+        .id = 3,
+        .resource = uart3,
+        .num_resources = ARRAY_SIZE(uart3),
+};
+
+static struct resource uart4[] = {
+        {
+                .start = 0x5002c000,
+                .end = 0x5002ffff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 40,
+                .end = 40,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device4 = {
+        .name = "imx-uart",
+        .id = 4,
+        .resource = uart4,
+        .num_resources = ARRAY_SIZE(uart4),
+};
+
+#define MX25_OTG_BASE_ADDR 0x53FF4000
+
+static u64 otg_dmamask = DMA_BIT_MASK(32);
+
+static struct resource mxc_otg_resources[] = {
+        {
+                .start = MX25_OTG_BASE_ADDR,
+                .end = MX25_OTG_BASE_ADDR + 0x1ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 37,
+                .end = 37,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_otg = {
+        .name = "mxc-ehci",
+        .id = 0,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &otg_dmamask,
+        },
+        .resource = mxc_otg_resources,
+        .num_resources = ARRAY_SIZE(mxc_otg_resources),
+};
+
+/* OTG gadget device */
+struct platform_device otg_udc_device = {
+        .name = "fsl-usb2-udc",
+        .id   = -1,
+        .dev  = {
+                .dma_mask          = &otg_dmamask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+        .resource = mxc_otg_resources,
+        .num_resources = ARRAY_SIZE(mxc_otg_resources),
+};
+
+static u64 usbh2_dmamask = DMA_BIT_MASK(32);
+
+static struct resource mxc_usbh2_resources[] = {
+        {
+                .start = MX25_OTG_BASE_ADDR + 0x400,
+                .end = MX25_OTG_BASE_ADDR + 0x5ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 35,
+                .end = 35,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_usbh2 = {
+        .name = "mxc-ehci",
+        .id = 1,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh2_dmamask,
+        },
+        .resource = mxc_usbh2_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
+};
+
+static struct resource mxc_spi_resources0[] = {
+        {
+               .start = 0x43fa4000,
+               .end = 0x43fa7fff,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = 14,
+               .end = 14,
+               .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_spi_device0 = {
+        .name = "spi_imx",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources0),
+        .resource = mxc_spi_resources0,
+};
+
+static struct resource mxc_spi_resources1[] = {
+        {
+               .start = 0x50010000,
+               .end = 0x50013fff,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = 13,
+               .end = 13,
+               .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_spi_device1 = {
+        .name = "spi_imx",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources1),
+        .resource = mxc_spi_resources1,
+};
+
+static struct resource mxc_spi_resources2[] = {
+        {
+               .start = 0x50004000,
+               .end = 0x50007fff,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = 0,
+               .end = 0,
+               .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_spi_device2 = {
+        .name = "spi_imx",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources2),
+        .resource = mxc_spi_resources2,
+};
+
+static struct resource mxc_pwm_resources0[] = {
+        {
+                .start  = 0x53fe0000,
+                .end    = 0x53fe3fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 26,
+                .end     = 26,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_pwm_device0 = {
+        .name = "mxc_pwm",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_pwm_resources0),
+        .resource = mxc_pwm_resources0,
+};
+
+static struct resource mxc_pwm_resources1[] = {
+        {
+                .start  = 0x53fa0000,
+                .end    = 0x53fa3fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 36,
+                .end     = 36,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_pwm_device1 = {
+        .name = "mxc_pwm",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_pwm_resources1),
+        .resource = mxc_pwm_resources1,
+};
+
+static struct resource mxc_pwm_resources2[] = {
+        {
+                .start  = 0x53fa8000,
+                .end    = 0x53fabfff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 41,
+                .end     = 41,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_pwm_device2 = {
+        .name = "mxc_pwm",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_pwm_resources2),
+        .resource = mxc_pwm_resources2,
+};
+
+static struct resource mxc_keypad_resources[] = {
+        {
+                .start  = 0x43fa8000,
+                .end    = 0x43fabfff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 24,
+                .end     = 24,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_keypad_device = {
+        .name = "mxc-keypad",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(mxc_keypad_resources),
+        .resource = mxc_keypad_resources,
+};
+
+static struct resource mxc_pwm_resources3[] = {
+        {
+                .start  = 0x53fc8000,
+                .end    = 0x53fcbfff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 42,
+                .end     = 42,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_pwm_device3 = {
+        .name = "mxc_pwm",
+        .id = 3,
+        .num_resources = ARRAY_SIZE(mxc_pwm_resources3),
+        .resource = mxc_pwm_resources3,
+};
+
+static struct resource mxc_i2c_1_resources[] = {
+        {
+                .start  = 0x43f80000,
+                .end    = 0x43f83fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = 3,
+                .end    = 3,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_i2c_device0 = {
+        .name = "imx-i2c",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
+        .resource = mxc_i2c_1_resources,
+};
+
+static struct resource mxc_i2c_2_resources[] = {
+        {
+                .start  = 0x43f98000,
+                .end    = 0x43f9bfff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = 4,
+                .end    = 4,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_i2c_device1 = {
+        .name = "imx-i2c",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
+        .resource = mxc_i2c_2_resources,
+};
+
+static struct resource mxc_i2c_3_resources[] = {
+        {
+                .start  = 0x43f84000,
+                .end    = 0x43f87fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = 10,
+                .end    = 10,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_i2c_device2 = {
+        .name = "imx-i2c",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_i2c_3_resources),
+        .resource = mxc_i2c_3_resources,
+};
+
+static struct mxc_gpio_port imx_gpio_ports[] = {
+        {
+                .chip.label = "gpio-0",
+                .base = (void __iomem *)MX25_GPIO1_BASE_ADDR_VIRT,
+                .irq = 52,
+                .virtual_irq_start = MXC_GPIO_IRQ_START,
+        }, {
+                .chip.label = "gpio-1",
+                .base = (void __iomem *)MX25_GPIO2_BASE_ADDR_VIRT,
+                .irq = 51,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
+        }, {
+                .chip.label = "gpio-2",
+                .base = (void __iomem *)MX25_GPIO3_BASE_ADDR_VIRT,
+                .irq = 16,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
+        }, {
+                .chip.label = "gpio-3",
+                .base = (void __iomem *)MX25_GPIO4_BASE_ADDR_VIRT,
+                .irq = 23,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
+        }
+};
+
+int __init mxc_register_gpios(void)
+{
+        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
+}
+
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
new file mode 100644
index 000000000000..fe6bf88ad1dd
--- /dev/null
+++ b/arch/arm/mach-mx25/devices.h
@@ -0,0 +1,19 @@
+extern struct platform_device mxc_uart_device0;
+extern struct platform_device mxc_uart_device1;
+extern struct platform_device mxc_uart_device2;
+extern struct platform_device mxc_uart_device3;
+extern struct platform_device mxc_uart_device4;
+extern struct platform_device mxc_otg;
+extern struct platform_device otg_udc_device;
+extern struct platform_device mxc_usbh2;
+extern struct platform_device mxc_spi_device0;
+extern struct platform_device mxc_spi_device1;
+extern struct platform_device mxc_spi_device2;
+extern struct platform_device mxc_pwm_device0;
+extern struct platform_device mxc_pwm_device1;
+extern struct platform_device mxc_pwm_device2;
+extern struct platform_device mxc_pwm_device3;
+extern struct platform_device mxc_keypad_device;
+extern struct platform_device mxc_i2c_device0;
+extern struct platform_device mxc_i2c_device1;
+extern struct platform_device mxc_i2c_device2;
diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-mx25/mm.c
new file mode 100644
index 000000000000..a7e587ff3e9e
--- /dev/null
+++ b/arch/arm/mach-mx25/mm.c
@@ -0,0 +1,76 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MX31 specific definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/err.h>
+
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/mx25.h>
+#include <mach/iomux-v3.h>
+
+/*
+ * This table defines static virtual address mappings for I/O regions.
+ * These are the mappings common across all MX3 boards.
+ */
+static struct map_desc mxc_io_desc[] __initdata = {
+        {
+                .virtual        = MX25_AVIC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MX25_AVIC_BASE_ADDR),
+                .length         = MX25_AVIC_SIZE,
+                .type           = MT_DEVICE_NONSHARED
+        }, {
+                .virtual        = MX25_AIPS1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MX25_AIPS1_BASE_ADDR),
+                .length         = MX25_AIPS1_SIZE,
+                .type           = MT_DEVICE_NONSHARED
+        }, {
+                .virtual        = MX25_AIPS2_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MX25_AIPS2_BASE_ADDR),
+                .length         = MX25_AIPS2_SIZE,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mx25_map_io(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX25);
+        mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
+
+        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
+
+void __init mx25_init_irq(void)
+{
+        mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT);
+}
+
diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mx25pdk.c
new file mode 100644
index 000000000000..92aa4fd19d99
--- /dev/null
+++ b/arch/arm/mach-mx25/mx25pdk.c
@@ -0,0 +1,58 @@
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/mx25.h>
+#include <mach/mxc_nand.h>
+#include "devices.h"
+#include <mach/iomux-v3.h>
+
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct mxc_nand_platform_data nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
+
+static void __init mx25pdk_init(void)
+{
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_usbh2, NULL);
+        mxc_register_device(&mxc_nand_device, &nand_board_info);
+}
+
+
+static void __init mx25pdk_timer_init(void)
+{
+        mx25_clocks_init(26000000);
+}
+
+static struct sys_timer mx25pdk_timer = {
+        .init   = mx25pdk_timer_init,
+};
+
+MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
+        /* Maintainer: Freescale Semiconductor, Inc. */
+        .phys_io        = MX25_AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx25_map_io,
+        .init_irq       = mx25_init_irq,
+        .init_machine   = mx25pdk_init,
+        .timer          = &mx25pdk_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/armadillo5x0.c
index ee331fd6b1bd..776c0ee1b3cd 100644
--- a/arch/arm/mach-mx3/armadillo5x0.c
+++ b/arch/arm/mach-mx3/armadillo5x0.c
@@ -352,7 +352,7 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x00000100,
         .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
         .timer          = &armadillo5x0_timer,
         .init_machine   = armadillo5x0_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 577ee83d1f60..fe5c4217322e 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -273,6 +273,19 @@ static unsigned long get_rate_csi(struct clk *clk)
         return rate / get_3_3_div((pdr2 >> 16) & 0x3f);
 }
 
+static unsigned long get_rate_otg(struct clk *clk)
+{
+        unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+        unsigned long rate;
+
+        if (pdr4 & (1 << 9))
+                rate = get_rate_arm();
+        else
+                rate = get_rate_ppll();
+
+        return rate / get_3_3_div((pdr4 >> 22) & 0x3f);
+}
+
 static unsigned long get_rate_ipg_per(struct clk *clk)
 {
         unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
@@ -365,7 +378,7 @@ DEFINE_CLOCK(ssi2_clk,   1, CCM_CGR2, 14, get_rate_ssi, NULL);
 DEFINE_CLOCK(uart1_clk,  0, CCM_CGR2, 16, get_rate_uart, NULL);
 DEFINE_CLOCK(uart2_clk,  1, CCM_CGR2, 18, get_rate_uart, NULL);
 DEFINE_CLOCK(uart3_clk,  2, CCM_CGR2, 20, get_rate_uart, NULL);
-DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, NULL, NULL);
+DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
 DEFINE_CLOCK(wdog_clk,   0, CCM_CGR2, 24, NULL, NULL);
 DEFINE_CLOCK(max_clk,    0, CCM_CGR2, 26, NULL, NULL);
 DEFINE_CLOCK(admux_clk,  0, CCM_CGR2, 30, NULL, NULL);
@@ -426,7 +439,10 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
         _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
-        _REGISTER_CLOCK(NULL, "usbotg", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
         _REGISTER_CLOCK("mxc_wdt.0", NULL, wdog_clk)
         _REGISTER_CLOCK(NULL, "max", max_clk)
         _REGISTER_CLOCK(NULL, "admux", admux_clk)
@@ -456,7 +472,7 @@ int __init mx35_clocks_init()
         __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);
         __raw_writel(0, CCM_BASE + CCM_CGR3);
 
-        mxc_timer_init(&gpt_clk);
+        mxc_timer_init(&gpt_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT);
 
         return 0;
 }
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index 8b14239724c9..06bd6180bfc3 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -29,6 +29,7 @@
 
 #include <mach/clock.h>
 #include <mach/hardware.h>
+#include <mach/mx31.h>
 #include <mach/common.h>
 
 #include "crm_regs.h"
@@ -402,6 +403,11 @@ static unsigned long clk_ckih_get_rate(struct clk *clk)
         return ckih_rate;
 }
 
+static unsigned long clk_ckil_get_rate(struct clk *clk)
+{
+        return CKIL_CLK_FREQ;
+}
+
 static struct clk ckih_clk = {
         .get_rate = clk_ckih_get_rate,
 };
@@ -508,6 +514,7 @@ DEFINE_CLOCK(usb_clk1,    0, NULL,          0, usb_get_rate, NULL, &usb_pll_clk)
 DEFINE_CLOCK(nfc_clk,     0, NULL,          0, nfc_get_rate, NULL, &ahb_clk);
 DEFINE_CLOCK(scc_clk,     0, NULL,          0, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
+DEFINE_CLOCK(ckil_clk,    0, NULL,          0, clk_ckil_get_rate, NULL, NULL);
 
 #define _REGISTER_CLOCK(d, n, c) \
         { \
@@ -518,9 +525,9 @@ DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
 
 static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "emi", emi_clk)
-        _REGISTER_CLOCK(NULL, "cspi", cspi1_clk)
-        _REGISTER_CLOCK(NULL, "cspi", cspi2_clk)
-        _REGISTER_CLOCK(NULL, "cspi", cspi3_clk)
+        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
         _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
         _REGISTER_CLOCK(NULL, "wdog", wdog_clk)
@@ -531,6 +538,12 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
         _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
         _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
         _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
@@ -559,6 +572,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "iim", iim_clk)
         _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
         _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
+        _REGISTER_CLOCK("mxc_rtc", NULL, ckil_clk)
 };
 
 int __init mx31_clocks_init(unsigned long fref)
@@ -609,7 +623,7 @@ int __init mx31_clocks_init(unsigned long fref)
                 __raw_writel(reg, MXC_CCM_PMCR1);
         }
 
-        mxc_timer_init(&ipg_clk);
+        mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT);
 
         return 0;
 }
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index 9e87e08fb121..8a577f367250 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -129,19 +129,17 @@ struct platform_device mxc_uart_device4 = {
 
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
-        [0] = {
+        {
                 .chip.label = "gpio-0",
                 .base = IO_ADDRESS(GPIO1_BASE_ADDR),
                 .irq = MXC_INT_GPIO1,
                 .virtual_irq_start = MXC_GPIO_IRQ_START,
-        },
-        [1] = {
+        }, {
                 .chip.label = "gpio-1",
                 .base = IO_ADDRESS(GPIO2_BASE_ADDR),
                 .irq = MXC_INT_GPIO2,
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-        },
-        [2] = {
+        }, {
                 .chip.label = "gpio-2",
                 .base = IO_ADDRESS(GPIO3_BASE_ADDR),
                 .irq = MXC_INT_GPIO3,
@@ -173,11 +171,11 @@ static struct resource mxc_nand_resources[] = {
         {
                 .start  = 0, /* runtime dependent */
                 .end    = 0,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
         }, {
                 .start  = MXC_INT_NANDFC,
                 .end    = MXC_INT_NANDFC,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -193,8 +191,7 @@ static struct resource mxc_i2c0_resources[] = {
                 .start = I2C_BASE_ADDR,
                 .end = I2C_BASE_ADDR + SZ_4K - 1,
                 .flags = IORESOURCE_MEM,
-        },
-        {
+        }, {
                 .start = MXC_INT_I2C,
                 .end = MXC_INT_I2C,
                 .flags = IORESOURCE_IRQ,
@@ -213,8 +210,7 @@ static struct resource mxc_i2c1_resources[] = {
                 .start = I2C2_BASE_ADDR,
                 .end = I2C2_BASE_ADDR + SZ_4K - 1,
                 .flags = IORESOURCE_MEM,
-        },
-        {
+        }, {
                 .start = MXC_INT_I2C2,
                 .end = MXC_INT_I2C2,
                 .flags = IORESOURCE_IRQ,
@@ -233,8 +229,7 @@ static struct resource mxc_i2c2_resources[] = {
                 .start = I2C3_BASE_ADDR,
                 .end = I2C3_BASE_ADDR + SZ_4K - 1,
                 .flags = IORESOURCE_MEM,
-        },
-        {
+        }, {
                 .start = MXC_INT_I2C3,
                 .end = MXC_INT_I2C3,
                 .flags = IORESOURCE_IRQ,
@@ -371,8 +366,8 @@ struct platform_device mx3_camera = {
 
 static struct resource otg_resources[] = {
         {
-                .start  = OTG_BASE_ADDR,
-                .end    = OTG_BASE_ADDR + 0x1ff,
+                .start  = MX31_OTG_BASE_ADDR,
+                .end    = MX31_OTG_BASE_ADDR + 0x1ff,
                 .flags  = IORESOURCE_MEM,
         }, {
                 .start  = MXC_INT_USB3,
@@ -395,16 +390,142 @@ struct platform_device mxc_otg_udc_device = {
         .num_resources  = ARRAY_SIZE(otg_resources),
 };
 
+/* OTG host */
+struct platform_device mxc_otg_host = {
+        .name = "mxc-ehci",
+        .id = 0,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &otg_dmamask,
+        },
+        .resource = otg_resources,
+        .num_resources = ARRAY_SIZE(otg_resources),
+};
+
+/* USB host 1 */
+
+static u64 usbh1_dmamask = ~(u32)0;
+
+static struct resource mxc_usbh1_resources[] = {
+        {
+                .start = MX31_OTG_BASE_ADDR + 0x200,
+                .end = MX31_OTG_BASE_ADDR + 0x3ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_USB1,
+                .end = MXC_INT_USB1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_usbh1 = {
+        .name = "mxc-ehci",
+        .id = 1,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh1_dmamask,
+        },
+        .resource = mxc_usbh1_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
+};
+
+/* USB host 2 */
+static u64 usbh2_dmamask = ~(u32)0;
+
+static struct resource mxc_usbh2_resources[] = {
+        {
+                .start = MX31_OTG_BASE_ADDR + 0x400,
+                .end = MX31_OTG_BASE_ADDR + 0x5ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_USB2,
+                .end = MXC_INT_USB2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_usbh2 = {
+        .name = "mxc-ehci",
+        .id = 2,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh2_dmamask,
+        },
+        .resource = mxc_usbh2_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
+};
+
+/*
+ * SPI master controller
+ * 3 channels
+ */
+static struct resource imx_spi_0_resources[] = {
+        {
+               .start = CSPI1_BASE_ADDR,
+               .end = CSPI1_BASE_ADDR + SZ_4K - 1,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = MXC_INT_CSPI1,
+               .end = MXC_INT_CSPI1,
+               .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource imx_spi_1_resources[] = {
+        {
+                .start = CSPI2_BASE_ADDR,
+                .end = CSPI2_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_CSPI2,
+                .end = MXC_INT_CSPI2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource imx_spi_2_resources[] = {
+        {
+                .start = CSPI3_BASE_ADDR,
+                .end = CSPI3_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_CSPI3,
+                .end = MXC_INT_CSPI3,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device imx_spi_device0 = {
+        .name = "spi_imx",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(imx_spi_0_resources),
+        .resource = imx_spi_0_resources,
+};
+
+struct platform_device imx_spi_device1 = {
+        .name = "spi_imx",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(imx_spi_1_resources),
+        .resource = imx_spi_1_resources,
+};
+
+struct platform_device imx_spi_device2 = {
+        .name = "spi_imx",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(imx_spi_2_resources),
+        .resource = imx_spi_2_resources,
+};
+
 #ifdef CONFIG_ARCH_MX35
 static struct resource mxc_fec_resources[] = {
         {
                 .start  = MXC_FEC_BASE_ADDR,
                 .end    = MXC_FEC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
         }, {
                 .start  = MXC_INT_FEC,
                 .end    = MXC_INT_FEC,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -426,6 +547,14 @@ static int mx3_devices_init(void)
         if (cpu_is_mx35()) {
                 mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
                 mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
+                otg_resources[0].start = MX35_OTG_BASE_ADDR;
+                otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
+                otg_resources[1].start = MXC_INT_USBOTG;
+                otg_resources[1].end = MXC_INT_USBOTG;
+                mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
+                mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
+                mxc_usbh1_resources[1].start = MXC_INT_USBHS;
+                mxc_usbh1_resources[1].end = MXC_INT_USBHS;
         }
 
         return 0;
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index ffd494ddd4ac..79f2be45d139 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -16,5 +16,11 @@ extern struct platform_device mxc_fec_device;
 extern struct platform_device mxcsdhc_device0;
 extern struct platform_device mxcsdhc_device1;
 extern struct platform_device mxc_otg_udc_device;
+extern struct platform_device mxc_otg_host;
+extern struct platform_device mxc_usbh1;
+extern struct platform_device mxc_usbh2;
 extern struct platform_device mxc_rnga_device;
+extern struct platform_device imx_spi_device0;
+extern struct platform_device imx_spi_device1;
+extern struct platform_device imx_spi_device2;
 
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 1f5fdd456cb9..ad5a1122d765 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -30,6 +30,7 @@
 
 #include <mach/common.h>
 #include <mach/hardware.h>
+#include <mach/iomux-v3.h>
 
 /*!
  * @file mm.c
@@ -75,6 +76,7 @@ static struct map_desc mxc_io_desc[] __initdata = {
 void __init mx31_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX31);
+        mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
 
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
@@ -82,10 +84,22 @@ void __init mx31_map_io(void)
 void __init mx35_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX35);
+        mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
 
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+void __init mx31_init_irq(void)
+{
+        mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+}
+
+void __init mx35_init_irq(void)
+{
+        mx31_init_irq();
+}
+
 #ifdef CONFIG_CACHE_L2X0
 static int mxc_init_l2x0(void)
 {
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index 30e2767a78ae..0497c152be18 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -517,7 +517,7 @@ static void __init mx31ads_map_io(void)
 
 static void __init mx31ads_init_irq(void)
 {
-        mxc_init_irq();
+        mx31_init_irq();
         mx31ads_init_expio();
 }
 
diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mx31lilly.c
index 6ab2f163cb95..423025150f6f 100644
--- a/arch/arm/mach-mx3/mx31lilly.c
+++ b/arch/arm/mach-mx3/mx31lilly.c
@@ -148,7 +148,7 @@ MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
         .init_machine   = mx31lilly_board_init,
         .timer          = &mx31lilly_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
index 86fe70fa3e13..a8d57decdfdb 100644
--- a/arch/arm/mach-mx3/mx31lite.c
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -71,12 +71,11 @@ static struct smsc911x_platform_config smsc911x_config = {
 };
 
 static struct resource smsc911x_resources[] = {
-        [0] = {
+        {
                 .start          = CS4_BASE_ADDR,
                 .end            = CS4_BASE_ADDR + 0x100,
                 .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start          = IOMUX_TO_IRQ(MX31_PIN_SFS6),
                 .end            = IOMUX_TO_IRQ(MX31_PIN_SFS6),
                 .flags          = IORESOURCE_IRQ,
@@ -162,7 +161,7 @@ MACHINE_START(MX31LITE, "LogicPD MX31 LITEKIT")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx31lite_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &mx31lite_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index b48581e7dedd..5592cdb8d0ad 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -16,7 +16,6 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#include <linux/fsl_devices.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
@@ -40,18 +39,6 @@ static unsigned int devboard_pins[] = {
         MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
         MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
         MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
-        /* USB OTG */
-        MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
-        MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
-        MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
-        MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
-        MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
-        MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
-        MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
-        MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
-        MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
-        MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
-        MX31_PIN_USB_OC__GPIO1_30,
 };
 
 static struct imxuart_platform_data uart_pdata = {
@@ -111,33 +98,6 @@ static struct imxmmc_platform_data sdhc2_pdata = {
         .exit   = devboard_sdhc2_exit,
 };
 
-static struct fsl_usb2_platform_data usb_pdata = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_ULPI,
-};
-
-#define OTG_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)
-#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
-
-static void devboard_usbotg_init(void)
-{
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, OTG_PAD_CFG);
-
-        gpio_request(OTG_EN_B, "usb-udc-en");
-        gpio_direction_output(OTG_EN_B, 0);
-}
-
 /*
  * system init for baseboard usage. Will be called by mx31moboard init.
  */
@@ -151,7 +111,4 @@ void __init mx31moboard_devboard_init(void)
         mxc_register_device(&mxc_uart_device1, &uart_pdata);
 
         mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
-
-        devboard_usbotg_init();
-        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
 }
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 901fb0166c0e..2bfaffb344f0 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -16,7 +16,6 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#include <linux/fsl_devices.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
@@ -48,18 +47,8 @@ static unsigned int marxbot_pins[] = {
         MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
         MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
         MX31_PIN_TXD2__GPIO1_28,
-        /* USB OTG */
-        MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
-        MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
-        MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
-        MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
-        MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
-        MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
-        MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
-        MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
-        MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
-        MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
-        MX31_PIN_USB_OC__GPIO1_30,
+        /* dsPIC resets */
+        MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22,
 };
 
 #define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
@@ -115,31 +104,20 @@ static struct imxmmc_platform_data sdhc2_pdata = {
         .exit   = marxbot_sdhc2_exit,
 };
 
-static struct fsl_usb2_platform_data usb_pdata = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_ULPI,
-};
-
-#define OTG_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)
-#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
+#define TRSLAT_RST_B    IOMUX_TO_GPIO(MX31_PIN_STXD5)
+#define DSPICS_RST_B    IOMUX_TO_GPIO(MX31_PIN_SRXD5)
 
-static void marxbot_usbotg_init(void)
+static void dspics_resets_init(void)
 {
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, OTG_PAD_CFG);
-
-        gpio_request(OTG_EN_B, "usb-udc-en");
-        gpio_direction_output(OTG_EN_B, 0);
+        if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
+                gpio_direction_output(TRSLAT_RST_B, 1);
+                gpio_export(TRSLAT_RST_B, false);
+        }
+
+        if (!gpio_request(DSPICS_RST_B, "dspics-rst")) {
+                gpio_direction_output(DSPICS_RST_B, 1);
+                gpio_export(DSPICS_RST_B, false);
+        }
 }
 
 /*
@@ -152,8 +130,7 @@ void __init mx31moboard_marxbot_init(void)
         mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins),
                 "marxbot");
 
-        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
+        dspics_resets_init();
 
-        marxbot_usbotg_init();
-        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
 }
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c
index 2a2da4739ecf..9243de54041a 100644
--- a/arch/arm/mach-mx3/mx31moboard.c
+++ b/arch/arm/mach-mx3/mx31moboard.c
@@ -16,9 +16,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+#include <linux/delay.h>
+#include <linux/fsl_devices.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/leds.h>
 #include <linux/memory.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
@@ -36,6 +39,7 @@
 #include <mach/iomux-mx3.h>
 #include <mach/i2c.h>
 #include <mach/mmc.h>
+#include <mach/mx31.h>
 
 #include "devices.h"
 
@@ -55,6 +59,26 @@ static unsigned int moboard_pins[] = {
         MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0,
         MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD,
         MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27,
+        /* USB reset */
+        MX31_PIN_GPIO1_0__GPIO1_0,
+        /* USB OTG */
+        MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+        MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
+        MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
+        MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
+        MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
+        MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
+        MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
+        MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
+        MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
+        MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
+        MX31_PIN_USB_OC__GPIO1_30,
+        /* LEDs */
+        MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
+        MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
+        /* SEL */
+        MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
+        MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
 };
 
 static struct physmap_flash_data mx31moboard_flash_data = {
@@ -142,8 +166,109 @@ static struct imxmmc_platform_data sdhc1_pdata = {
         .exit   = moboard_sdhc1_exit,
 };
 
+/*
+ * this pin is dedicated for all mx31moboard systems, so we do it here
+ */
+#define USB_RESET_B     IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)
+
+static void usb_xcvr_reset(void)
+{
+        gpio_request(USB_RESET_B, "usb-reset");
+        gpio_direction_output(USB_RESET_B, 0);
+        mdelay(1);
+        gpio_set_value(USB_RESET_B, 1);
+}
+
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
+
+static void moboard_usbotg_init(void)
+{
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
+
+        gpio_request(OTG_EN_B, "usb-udc-en");
+        gpio_direction_output(OTG_EN_B, 0);
+}
+
+static struct fsl_usb2_platform_data usb_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_ULPI,
+};
+
+static struct gpio_led mx31moboard_leds[] = {
+        {
+                .name   = "coreboard-led-0:red:running",
+                .default_trigger = "heartbeat",
+                .gpio   = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
+        }, {
+                .name   = "coreboard-led-1:red",
+                .gpio   = IOMUX_TO_GPIO(MX31_PIN_STX0),
+        }, {
+                .name   = "coreboard-led-2:red",
+                .gpio   = IOMUX_TO_GPIO(MX31_PIN_SRX0),
+        }, {
+                .name   = "coreboard-led-3:red",
+                .gpio   = IOMUX_TO_GPIO(MX31_PIN_SIMPD0),
+        },
+};
+
+static struct gpio_led_platform_data mx31moboard_led_pdata = {
+        .num_leds       = ARRAY_SIZE(mx31moboard_leds),
+        .leds           = mx31moboard_leds,
+};
+
+static struct platform_device mx31moboard_leds_device = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &mx31moboard_led_pdata,
+        },
+};
+
+#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
+#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
+#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
+#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
+
+static void mx31moboard_init_sel_gpios(void)
+{
+        if (!gpio_request(SEL0, "sel0")) {
+                gpio_direction_input(SEL0);
+                gpio_export(SEL0, true);
+        }
+
+        if (!gpio_request(SEL1, "sel1")) {
+                gpio_direction_input(SEL1);
+                gpio_export(SEL1, true);
+        }
+
+        if (!gpio_request(SEL2, "sel2")) {
+                gpio_direction_input(SEL2);
+                gpio_export(SEL2, true);
+        }
+
+        if (!gpio_request(SEL3, "sel3")) {
+                gpio_direction_input(SEL3);
+                gpio_export(SEL3, true);
+        }
+}
+
 static struct platform_device *devices[] __initdata = {
         &mx31moboard_flash,
+        &mx31moboard_leds_device,
 };
 
 static int mx31moboard_baseboard;
@@ -162,11 +287,18 @@ static void __init mxc_board_init(void)
         mxc_register_device(&mxc_uart_device0, &uart_pdata);
         mxc_register_device(&mxc_uart_device4, &uart_pdata);
 
+        mx31moboard_init_sel_gpios();
+
         mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata);
         mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata);
 
         mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata);
 
+        usb_xcvr_reset();
+
+        moboard_usbotg_init();
+        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+
         switch (mx31moboard_baseboard) {
         case MX31NOBOARD:
                 break;
@@ -197,7 +329,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &mx31moboard_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c
index c19838d2e369..0f7a2f06bc2d 100644
--- a/arch/arm/mach-mx3/mx31pdk.c
+++ b/arch/arm/mach-mx3/mx31pdk.c
@@ -265,7 +265,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx31pdk_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &mx31pdk_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx35pdk.c b/arch/arm/mach-mx3/mx35pdk.c
index 6d15374414b9..6ff186e46ceb 100644
--- a/arch/arm/mach-mx3/mx35pdk.c
+++ b/arch/arm/mach-mx3/mx35pdk.c
@@ -98,7 +98,7 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx35_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx35_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &mx35pdk_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
index 840cfda341d0..6cbaabedf386 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -32,6 +32,7 @@
 #include <linux/spi/spi.h>
 #include <linux/irq.h>
 #include <linux/fsl_devices.h>
+#include <linux/can/platform/sja1000.h>
 
 #include <media/soc_camera.h>
 
@@ -169,6 +170,8 @@ static unsigned int pcm037_pins[] = {
         MX31_PIN_CSI_MCLK__CSI_MCLK,
         MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
         MX31_PIN_CSI_VSYNC__CSI_VSYNC,
+        /* GPIO */
+        IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
 };
 
 static struct physmap_flash_data pcm037_flash_data = {
@@ -244,12 +247,11 @@ static struct imxuart_platform_data uart_pdata = {
 };
 
 static struct resource smsc911x_resources[] = {
-        [0] = {
+        {
                 .start          = CS1_BASE_ADDR + 0x300,
                 .end            = CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
                 .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start          = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
                 .end            = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
                 .flags          = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
@@ -339,8 +341,7 @@ static struct i2c_board_info pcm037_i2c_devices[] = {
                 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
                 .platform_data = &board_eeprom,
         }, {
-                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
-                .type = "pcf8563",
+                I2C_BOARD_INFO("pcf8563", 0x51),
         }
 };
 
@@ -515,6 +516,33 @@ static struct mx3fb_platform_data mx3fb_pdata = {
         .num_modes      = ARRAY_SIZE(fb_modedb),
 };
 
+static struct resource pcm970_sja1000_resources[] = {
+        {
+                .start   = CS5_BASE_ADDR,
+                .end     = CS5_BASE_ADDR + 0x100 - 1,
+                .flags   = IORESOURCE_MEM,
+        }, {
+                .start   = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
+                .end     = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
+                .flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
+        },
+};
+
+struct sja1000_platform_data pcm970_sja1000_platform_data = {
+        .clock          = 16000000 / 2,
+        .ocr            = 0x40 | 0x18,
+        .cdr            = 0x40,
+};
+
+static struct platform_device pcm970_sja1000 = {
+        .name = "sja1000_platform",
+        .dev = {
+                .platform_data = &pcm970_sja1000_platform_data,
+        },
+        .resource = pcm970_sja1000_resources,
+        .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
+};
+
 /*
  * Board specific initialization.
  */
@@ -575,6 +603,8 @@ static void __init mxc_board_init(void)
 
         if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
                 mxc_register_device(&mx3_camera, &camera_pdata);
+
+        platform_device_register(&pcm970_sja1000);
 }
 
 static void __init pcm037_timer_init(void)
@@ -592,7 +622,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &pcm037_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/pcm043.c b/arch/arm/mach-mx3/pcm043.c
index 8d27c324abf2..e18a224671fa 100644
--- a/arch/arm/mach-mx3/pcm043.c
+++ b/arch/arm/mach-mx3/pcm043.c
@@ -133,8 +133,7 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
                 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
                 .platform_data = &board_eeprom,
         }, {
-                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
-                .type = "pcf8563",
+                I2C_BOARD_INFO("pcf8563", 0x51),
         }
 };
 #endif
@@ -203,7 +202,8 @@ static struct pad_desc pcm043_pads[] = {
         MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
         MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
         MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
-        MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL
+        /* gpio */
+        MX35_PAD_ATA_CS0__GPIO2_6,
 };
 
 /*
@@ -245,7 +245,7 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx35_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx35_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &pcm043_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/qong.c b/arch/arm/mach-mx3/qong.c
index 82b31c4ab11f..044511f1b9a9 100644
--- a/arch/arm/mach-mx3/qong.c
+++ b/arch/arm/mach-mx3/qong.c
@@ -81,13 +81,12 @@ static inline void mxc_init_imx_uart(void)
 }
 
 static struct resource dnet_resources[] = {
-        [0] = {
+        {
                 .name   = "dnet-memory",
                 .start  = QONG_DNET_BASEADDR,
                 .end    = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = QONG_FPGA_IRQ,
                 .end    = QONG_FPGA_IRQ,
                 .flags  = IORESOURCE_IRQ,
@@ -280,7 +279,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &qong_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mxc91231/Kconfig b/arch/arm/mach-mxc91231/Kconfig
new file mode 100644
index 000000000000..8e5fa38ebb67
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_MXC91231
+
+comment "MXC91231 platforms:"
+
+config MACH_MAGX_ZN5
+        bool "Support Motorola Zn5 GSM phone"
+        default n
+        help
+          Include support for Motorola Zn5 GSM phone.
+
+endif
diff --git a/arch/arm/mach-mxc91231/Makefile b/arch/arm/mach-mxc91231/Makefile
new file mode 100644
index 000000000000..011d5e197125
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Makefile
@@ -0,0 +1,2 @@
+obj-y   := mm.o clock.o devices.o system.o iomux.o
+obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o
diff --git a/arch/arm/mach-mxc91231/Makefile.boot b/arch/arm/mach-mxc91231/Makefile.boot
new file mode 100644
index 000000000000..9939a19d99a1
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x90008000
+params_phys-y   := 0x90000100
+initrd_phys-y   := 0x90800000
diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c
new file mode 100644
index 000000000000..ecfa37fef8ad
--- /dev/null
+++ b/arch/arm/mach-mxc91231/clock.c
@@ -0,0 +1,642 @@
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#include <asm/clkdev.h>
+#include <asm/bug.h>
+#include <asm/div64.h>
+
+#include "crm_regs.h"
+
+#define CRM_SMALL_DIVIDER(base, name) \
+        crm_small_divider(base, \
+                          base ## _ ## name ## _OFFSET, \
+                          base ## _ ## name ## _MASK)
+#define CRM_1DIVIDER(base, name) \
+        crm_divider(base, \
+                    base ## _ ## name ## _OFFSET, \
+                    base ## _ ## name ## _MASK, 1)
+#define CRM_16DIVIDER(base, name) \
+        crm_divider(base, \
+                    base ## _ ## name ## _OFFSET, \
+                    base ## _ ## name ## _MASK, 16)
+
+static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask)
+{
+        static const u32 crm_small_dividers[] = {
+                2, 3, 4, 5, 6, 8, 10, 12
+        };
+        u8 idx;
+
+        idx = (__raw_readl(reg) & mask) >> offset;
+        if (idx > 7)
+                return 1;
+
+        return crm_small_dividers[idx];
+}
+
+static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z)
+{
+        u32 div;
+        div = (__raw_readl(reg) & mask) >> offset;
+        return div ? div : z;
+}
+
+static int _clk_1bit_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void _clk_1bit_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_3bit_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 0x7 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void _clk_3bit_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(0x7 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static unsigned long ckih_rate;
+
+static unsigned long clk_ckih_get_rate(struct clk *clk)
+{
+        return ckih_rate;
+}
+
+static struct clk ckih_clk = {
+        .get_rate = clk_ckih_get_rate,
+};
+
+static unsigned long clk_ckih_x2_get_rate(struct clk *clk)
+{
+        return 2 * clk_get_rate(clk->parent);
+}
+
+static struct clk ckih_x2_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_ckih_x2_get_rate,
+};
+
+static unsigned long clk_ckil_get_rate(struct clk *clk)
+{
+        return CKIL_CLK_FREQ;
+}
+
+static struct clk ckil_clk = {
+        .get_rate = clk_ckil_get_rate,
+};
+
+/* plls stuff */
+static struct clk mcu_pll_clk;
+static struct clk dsp_pll_clk;
+static struct clk usb_pll_clk;
+
+static struct clk *pll_clk(u8 sel)
+{
+        switch (sel) {
+        case 0:
+                return &mcu_pll_clk;
+        case 1:
+                return &dsp_pll_clk;
+        case 2:
+                return &usb_pll_clk;
+        }
+        BUG();
+}
+
+static void __iomem *pll_base(struct clk *clk)
+{
+        if (clk == &mcu_pll_clk)
+                return MXC_PLL0_BASE;
+        else if (clk == &dsp_pll_clk)
+                return MXC_PLL1_BASE;
+        else if (clk == &usb_pll_clk)
+                return MXC_PLL2_BASE;
+        BUG();
+}
+
+static unsigned long clk_pll_get_rate(struct clk *clk)
+{
+        const void __iomem *pllbase;
+        unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi;
+        long mfn, mfn_abs, mfd, pdf;
+        s64 temp;
+        pllbase = pll_base(clk);
+
+        pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
+        if (pll_hfsm == 0) {
+                dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
+                dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
+                dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
+        } else {
+                dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
+                dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
+                dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
+        }
+
+        pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
+        mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK;
+        mfi = (mfi <= 5) ? 5 : mfi;
+        mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
+        mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
+        mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);
+
+        if (mfn < 0)
+                mfn_abs = -mfn;
+        else
+                mfn_abs = mfn;
+
+/* XXX: actually this asumes that ckih is fed to pll, but spec says
+ * that ckih_x2 is also possible. need to check this out.
+ */
+        ref_clk = clk_get_rate(&ckih_clk);
+
+        ref_clk *= 2;
+        ref_clk /= pdf + 1;
+
+        temp = (u64) ref_clk * mfn_abs;
+        do_div(temp, mfd);
+        if (mfn < 0)
+                temp = -temp;
+        temp += ref_clk * mfi;
+
+        return temp;
+}
+
+static int clk_pll_enable(struct clk *clk)
+{
+        void __iomem *ctl;
+        u32 reg;
+
+        ctl = pll_base(clk);
+        reg = __raw_readl(ctl);
+        reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
+        __raw_writel(reg, ctl);
+        do {
+                reg = __raw_readl(ctl);
+        } while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
+        return 0;
+}
+
+static void clk_pll_disable(struct clk *clk)
+{
+        void __iomem *ctl;
+        u32 reg;
+
+        ctl = pll_base(clk);
+        reg = __raw_readl(ctl);
+        reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
+        __raw_writel(reg, ctl);
+}
+
+static struct clk mcu_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_pll_get_rate,
+        .enable = clk_pll_enable,
+        .disable = clk_pll_disable,
+};
+
+static struct clk dsp_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_pll_get_rate,
+        .enable = clk_pll_enable,
+        .disable = clk_pll_disable,
+};
+
+static struct clk usb_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_pll_get_rate,
+        .enable = clk_pll_enable,
+        .disable = clk_pll_disable,
+};
+/* plls stuff end */
+
+/* ap_ref_clk stuff */
+static struct clk ap_ref_clk;
+
+static unsigned long clk_ap_ref_get_rate(struct clk *clk)
+{
+        u32 ascsr, acsr;
+        u8 ap_pat_ref_div_2, ap_isel, acs, ads;
+
+        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+        acsr = __raw_readl(MXC_CRMAP_ACSR);
+
+        /* 0 for ckih, 1 for ckih*2 */
+        ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL;
+        /* reg divider */
+        ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1;
+        /* undocumented, 1 for disabling divider */
+        ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1;
+        /* 0 for pat_ref, 1 for divider out */
+        acs = acsr & MXC_CRMAP_ACSR_ACS;
+
+        if (acs & !ads)
+                /* use divided clock */
+                return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1);
+
+        return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1);
+}
+
+static struct clk ap_ref_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_ap_ref_get_rate,
+};
+/* ap_ref_clk stuff end */
+
+/* ap_pre_dfs_clk stuff */
+static struct clk ap_pre_dfs_clk;
+
+static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk)
+{
+        u32 acsr, ascsr;
+
+        acsr = __raw_readl(MXC_CRMAP_ACSR);
+        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+
+        if (acsr & MXC_CRMAP_ACSR_ACS) {
+                u8 sel;
+                sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >>
+                        MXC_CRMAP_ASCSR_APSEL_OFFSET;
+                return clk_get_rate(pll_clk(sel)) /
+                        CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV);
+        }
+        return clk_get_rate(&ap_ref_clk);
+}
+
+static struct clk ap_pre_dfs_clk = {
+        .get_rate = clk_ap_pre_dfs_get_rate,
+};
+/* ap_pre_dfs_clk stuff end */
+
+/* usb_clk stuff */
+static struct clk usb_clk;
+
+static struct clk *clk_usb_parent(struct clk *clk)
+{
+        u32 acsr, ascsr;
+
+        acsr = __raw_readl(MXC_CRMAP_ACSR);
+        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+
+        if (acsr & MXC_CRMAP_ACSR_ACS) {
+                u8 sel;
+                sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >>
+                        MXC_CRMAP_ASCSR_USBSEL_OFFSET;
+                return pll_clk(sel);
+        }
+        return &ap_ref_clk;
+}
+
+static unsigned long clk_usb_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) /
+                CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV);
+}
+
+static struct clk usb_clk = {
+        .enable_reg = MXC_CRMAP_ACDER2,
+        .enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET,
+        .get_rate = clk_usb_get_rate,
+        .enable = _clk_1bit_enable,
+        .disable = _clk_1bit_disable,
+};
+/* usb_clk stuff end */
+
+static unsigned long clk_ipg_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV);
+}
+
+static unsigned long clk_ahb_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) /
+                CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV);
+}
+
+static struct clk ipg_clk = {
+        .parent = &ap_pre_dfs_clk,
+        .get_rate = clk_ipg_get_rate,
+};
+
+static struct clk ahb_clk = {
+        .parent = &ap_pre_dfs_clk,
+        .get_rate = clk_ahb_get_rate,
+};
+
+/* perclk_clk stuff */
+static struct clk perclk_clk;
+
+static unsigned long clk_perclk_get_rate(struct clk *clk)
+{
+        u32 acder2;
+
+        acder2 = __raw_readl(MXC_CRMAP_ACDER2);
+        if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK)
+                return 2 * clk_get_rate(clk->parent);
+
+        return clk_get_rate(clk->parent);
+}
+
+static struct clk perclk_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_perclk_get_rate,
+};
+/* perclk_clk stuff end */
+
+/* uart_clk stuff */
+static struct clk uart_clk[];
+
+static unsigned long clk_uart_get_rate(struct clk *clk)
+{
+        u32 div;
+
+        switch (clk->id) {
+        case 0:
+        case 1:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV);
+                break;
+        case 2:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV);
+                break;
+        default:
+                BUG();
+        }
+        return clk_get_rate(clk->parent) / div;
+}
+
+static struct clk uart_clk[] = {
+        {
+                .id = 0,
+                .parent = &perclk_clk,
+                .enable_reg = MXC_CRMAP_APRA,
+                .enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET,
+                .get_rate = clk_uart_get_rate,
+                .enable = _clk_1bit_enable,
+                .disable = _clk_1bit_disable,
+        }, {
+                .id = 1,
+                .parent = &perclk_clk,
+                .enable_reg = MXC_CRMAP_APRA,
+                .enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET,
+                .get_rate = clk_uart_get_rate,
+                .enable = _clk_1bit_enable,
+                .disable = _clk_1bit_disable,
+        }, {
+                .id = 2,
+                .parent = &perclk_clk,
+                .enable_reg = MXC_CRMAP_APRA,
+                .enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET,
+                .get_rate = clk_uart_get_rate,
+                .enable = _clk_1bit_enable,
+                .disable = _clk_1bit_disable,
+        },
+};
+/* uart_clk stuff end */
+
+/* sdhc_clk stuff */
+static struct clk nfc_clk;
+
+static unsigned long clk_nfc_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) /
+                CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV);
+}
+
+static struct clk nfc_clk = {
+        .parent = &ahb_clk,
+        .enable_reg = MXC_CRMAP_ACDER2,
+        .enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET,
+        .get_rate = clk_nfc_get_rate,
+        .enable = _clk_1bit_enable,
+        .disable = _clk_1bit_disable,
+};
+/* sdhc_clk stuff end */
+
+/* sdhc_clk stuff */
+static struct clk sdhc_clk[];
+
+static struct clk *clk_sdhc_parent(struct clk *clk)
+{
+        u32 aprb;
+        u8 sel;
+        u32 mask;
+        int offset;
+
+        aprb = __raw_readl(MXC_CRMAP_APRB);
+
+        switch (clk->id) {
+        case 0:
+                mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK;
+                offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET;
+                break;
+        case 1:
+                mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK;
+                offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET;
+                break;
+        default:
+                BUG();
+        }
+        sel = (aprb & mask) >> offset;
+
+        switch (sel) {
+        case 0:
+                return &ckih_clk;
+        case 1:
+                return &ckih_x2_clk;
+        }
+        return &usb_clk;
+}
+
+static unsigned long clk_sdhc_get_rate(struct clk *clk)
+{
+        u32 div;
+
+        switch (clk->id) {
+        case 0:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV);
+                break;
+        case 1:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV);
+                break;
+        default:
+                BUG();
+        }
+
+        return clk_get_rate(clk->parent) / div;
+}
+
+static int clk_sdhc_enable(struct clk *clk)
+{
+        u32 amlpmre1, aprb;
+
+        amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
+        aprb = __raw_readl(MXC_CRMAP_APRB);
+        switch (clk->id) {
+        case 0:
+                amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
+                aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
+                break;
+        case 1:
+                amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
+                aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
+                break;
+        }
+        __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
+        __raw_writel(aprb, MXC_CRMAP_APRB);
+        return 0;
+}
+
+static void clk_sdhc_disable(struct clk *clk)
+{
+        u32 amlpmre1, aprb;
+
+        amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
+        aprb = __raw_readl(MXC_CRMAP_APRB);
+        switch (clk->id) {
+        case 0:
+                amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
+                aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
+                break;
+        case 1:
+                amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
+                aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
+                break;
+        }
+        __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
+        __raw_writel(aprb, MXC_CRMAP_APRB);
+}
+
+static struct clk sdhc_clk[] = {
+        {
+                .id = 0,
+                .get_rate = clk_sdhc_get_rate,
+                .enable = clk_sdhc_enable,
+                .disable = clk_sdhc_disable,
+        }, {
+                .id = 1,
+                .get_rate = clk_sdhc_get_rate,
+                .enable = clk_sdhc_enable,
+                .disable = clk_sdhc_disable,
+        },
+};
+/* sdhc_clk stuff end */
+
+/* wdog_clk stuff */
+static struct clk wdog_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRD,
+                .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRD,
+                .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        },
+};
+/* wdog_clk stuff end */
+
+/* gpt_clk stuff */
+static struct clk gpt_clk = {
+        .parent = &ipg_clk,
+        .enable_reg = MXC_CRMAP_AMLPMRC,
+        .enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET,
+        .enable = _clk_3bit_enable,
+        .disable = _clk_3bit_disable,
+};
+/* gpt_clk stuff end */
+
+/* cspi_clk stuff */
+static struct clk cspi_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRE2,
+                .enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRE1,
+                .enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        },
+};
+/* cspi_clk stuff end */
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
+        _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0])
+        _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1])
+        _REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0])
+        _REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0])
+        _REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1])
+};
+
+int __init mxc91231_clocks_init(unsigned long fref)
+{
+        void __iomem *gpt_base;
+        int i;
+
+        ckih_rate = fref;
+
+        usb_clk.parent = clk_usb_parent(&usb_clk);
+        sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
+        sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
+
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+
+        gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
+        mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
+
+        return 0;
+}
diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
new file mode 100644
index 000000000000..ce4f59058189
--- /dev/null
+++ b/arch/arm/mach-mxc91231/crm_regs.h
@@ -0,0 +1,399 @@
+/*
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ * Copyright 2006-2007 Motorola, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
+#define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
+
+#define CKIL_CLK_FREQ                   32768
+
+#define MXC_CRM_AP_BASE                 MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR)
+#define MXC_CRM_COM_BASE                MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR)
+#define MXC_DSM_BASE                    MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR)
+#define MXC_PLL0_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR)
+#define MXC_PLL1_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR)
+#define MXC_PLL2_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR)
+#define MXC_CLKCTL_BASE                 MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR)
+
+/* PLL Register Offsets */
+#define MXC_PLL_DP_CTL                  0x00
+#define MXC_PLL_DP_CONFIG               0x04
+#define MXC_PLL_DP_OP                   0x08
+#define MXC_PLL_DP_MFD                  0x0C
+#define MXC_PLL_DP_MFN                  0x10
+#define MXC_PLL_DP_HFS_OP               0x1C
+#define MXC_PLL_DP_HFS_MFD              0x20
+#define MXC_PLL_DP_HFS_MFN              0x24
+
+/* PLL Register Bit definitions */
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN      0x1000
+#define MXC_PLL_DP_CTL_ADE              0x800
+#define MXC_PLL_DP_CTL_REF_CLK_DIV      0x400
+#define MXC_PLL_DP_CTL_HFSM             0x80
+#define MXC_PLL_DP_CTL_PRE              0x40
+#define MXC_PLL_DP_CTL_UPEN             0x20
+#define MXC_PLL_DP_CTL_RST              0x10
+#define MXC_PLL_DP_CTL_RCP              0x8
+#define MXC_PLL_DP_CTL_PLM              0x4
+#define MXC_PLL_DP_CTL_BRM0             0x2
+#define MXC_PLL_DP_CTL_LRF              0x1
+
+#define MXC_PLL_DP_OP_MFI_OFFSET        4
+#define MXC_PLL_DP_OP_MFI_MASK          0xF
+#define MXC_PLL_DP_OP_PDF_OFFSET        0
+#define MXC_PLL_DP_OP_PDF_MASK          0xF
+
+#define MXC_PLL_DP_MFD_OFFSET           0
+#define MXC_PLL_DP_MFD_MASK             0x7FFFFFF
+
+#define MXC_PLL_DP_MFN_OFFSET           0
+#define MXC_PLL_DP_MFN_MASK             0x7FFFFFF
+
+/* CRM AP Register Offsets */
+#define MXC_CRMAP_ASCSR                 (MXC_CRM_AP_BASE + 0x00)
+#define MXC_CRMAP_ACDR                  (MXC_CRM_AP_BASE + 0x04)
+#define MXC_CRMAP_ACDER1                (MXC_CRM_AP_BASE + 0x08)
+#define MXC_CRMAP_ACDER2                (MXC_CRM_AP_BASE + 0x0C)
+#define MXC_CRMAP_ACGCR                 (MXC_CRM_AP_BASE + 0x10)
+#define MXC_CRMAP_ACCGCR                (MXC_CRM_AP_BASE + 0x14)
+#define MXC_CRMAP_AMLPMRA               (MXC_CRM_AP_BASE + 0x18)
+#define MXC_CRMAP_AMLPMRB               (MXC_CRM_AP_BASE + 0x1C)
+#define MXC_CRMAP_AMLPMRC               (MXC_CRM_AP_BASE + 0x20)
+#define MXC_CRMAP_AMLPMRD               (MXC_CRM_AP_BASE + 0x24)
+#define MXC_CRMAP_AMLPMRE1              (MXC_CRM_AP_BASE + 0x28)
+#define MXC_CRMAP_AMLPMRE2              (MXC_CRM_AP_BASE + 0x2C)
+#define MXC_CRMAP_AMLPMRF               (MXC_CRM_AP_BASE + 0x30)
+#define MXC_CRMAP_AMLPMRG               (MXC_CRM_AP_BASE + 0x34)
+#define MXC_CRMAP_APGCR                 (MXC_CRM_AP_BASE + 0x38)
+#define MXC_CRMAP_ACSR                  (MXC_CRM_AP_BASE + 0x3C)
+#define MXC_CRMAP_ADCR                  (MXC_CRM_AP_BASE + 0x40)
+#define MXC_CRMAP_ACR                   (MXC_CRM_AP_BASE + 0x44)
+#define MXC_CRMAP_AMCR                  (MXC_CRM_AP_BASE + 0x48)
+#define MXC_CRMAP_APCR                  (MXC_CRM_AP_BASE + 0x4C)
+#define MXC_CRMAP_AMORA                 (MXC_CRM_AP_BASE + 0x50)
+#define MXC_CRMAP_AMORB                 (MXC_CRM_AP_BASE + 0x54)
+#define MXC_CRMAP_AGPR                  (MXC_CRM_AP_BASE + 0x58)
+#define MXC_CRMAP_APRA                  (MXC_CRM_AP_BASE + 0x5C)
+#define MXC_CRMAP_APRB                  (MXC_CRM_AP_BASE + 0x60)
+#define MXC_CRMAP_APOR                  (MXC_CRM_AP_BASE + 0x64)
+#define MXC_CRMAP_ADFMR                 (MXC_CRM_AP_BASE + 0x68)
+
+/* CRM AP Register Bit definitions */
+#define MXC_CRMAP_ASCSR_CRS                     0x10000
+#define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET       15
+#define MXC_CRMAP_ASCSR_AP_PATREF_DIV2          0x8000
+#define MXC_CRMAP_ASCSR_USBSEL_OFFSET           13
+#define MXC_CRMAP_ASCSR_USBSEL_MASK             (0x3 << 13)
+#define MXC_CRMAP_ASCSR_CSISEL_OFFSET           11
+#define MXC_CRMAP_ASCSR_CSISEL_MASK             (0x3 << 11)
+#define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET          7
+#define MXC_CRMAP_ASCSR_SSI2SEL_MASK            (0x3 << 7)
+#define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET          5
+#define MXC_CRMAP_ASCSR_SSI1SEL_MASK            (0x3 << 5)
+#define MXC_CRMAP_ASCSR_APSEL_OFFSET            3
+#define MXC_CRMAP_ASCSR_APSEL_MASK              (0x3 << 3)
+#define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET       2
+#define MXC_CRMAP_ASCSR_AP_PATREF_DIV1          0x4
+#define MXC_CRMAP_ASCSR_APISEL                  0x1
+
+#define MXC_CRMAP_ACDR_ARMDIV_OFFSET            8
+#define MXC_CRMAP_ACDR_ARMDIV_MASK              (0xF << 8)
+#define MXC_CRMAP_ACDR_AHBDIV_OFFSET            4
+#define MXC_CRMAP_ACDR_AHBDIV_MASK              (0xF << 4)
+#define MXC_CRMAP_ACDR_IPDIV_OFFSET             0
+#define MXC_CRMAP_ACDR_IPDIV_MASK               0xF
+
+#define MXC_CRMAP_ACDER1_CSIEN_OFFSET           30
+#define MXC_CRMAP_ACDER1_CSIDIV_OFFSET          24
+#define MXC_CRMAP_ACDER1_CSIDIV_MASK            (0x3F << 24)
+#define MXC_CRMAP_ACDER1_SSI2EN_OFFSET          14
+#define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET         8
+#define MXC_CRMAP_ACDER1_SSI2DIV_MASK           (0x3F << 8)
+#define MXC_CRMAP_ACDER1_SSI1EN_OFFSET          6
+#define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET         0
+#define MXC_CRMAP_ACDER1_SSI1DIV_MASK           0x3F
+
+#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET    24
+#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK      (0x7 << 24)
+#define MXC_CRMAP_ACDER2_NFCEN_OFFSET           20
+#define MXC_CRMAP_ACDER2_NFCDIV_OFFSET          16
+#define MXC_CRMAP_ACDER2_NFCDIV_MASK            (0xF << 16)
+#define MXC_CRMAP_ACDER2_USBEN_OFFSET           12
+#define MXC_CRMAP_ACDER2_USBDIV_OFFSET          8
+#define MXC_CRMAP_ACDER2_USBDIV_MASK            (0xF << 8)
+#define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET       5
+#define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK         (0x3 << 5)
+#define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET         0
+#define MXC_CRMAP_ACDER2_BAUDDIV_MASK           0xF
+
+#define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET         22
+#define MXC_CRMAP_AMLPMRA_MLPMA7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET         19
+#define MXC_CRMAP_AMLPMRA_MLPMA6_MASK           (0x7 << 19)
+#define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET         12
+#define MXC_CRMAP_AMLPMRA_MLPMA4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET         9
+#define MXC_CRMAP_AMLPMRA_MLPMA3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET         6
+#define MXC_CRMAP_AMLPMRA_MLPMA2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET         3
+#define MXC_CRMAP_AMLPMRA_MLPMA1_MASK           (0x7 << 3)
+
+#define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET         0
+#define MXC_CRMAP_AMLPMRB_MLPMB0_MASK           0x7
+
+#define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET         28
+#define MXC_CRMAP_AMLPMRC_MLPMC9_MASK           (0x7 << 28)
+#define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET         22
+#define MXC_CRMAP_AMLPMRC_MLPMC7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET         16
+#define MXC_CRMAP_AMLPMRC_MLPMC5_MASK           (0x7 << 16)
+#define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET         12
+#define MXC_CRMAP_AMLPMRC_MLPMC4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET         9
+#define MXC_CRMAP_AMLPMRC_MLPMC3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET         6
+#define MXC_CRMAP_AMLPMRC_MLPMC2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET         3
+#define MXC_CRMAP_AMLPMRC_MLPMC1_MASK           (0x7 << 3)
+#define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET         0
+#define MXC_CRMAP_AMLPMRC_MLPMC0_MASK           0x7
+
+#define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET         22
+#define MXC_CRMAP_AMLPMRD_MLPMD7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET         12
+#define MXC_CRMAP_AMLPMRD_MLPMD4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET         9
+#define MXC_CRMAP_AMLPMRD_MLPMD3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET         6
+#define MXC_CRMAP_AMLPMRD_MLPMD2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET         0
+#define MXC_CRMAP_AMLPMRD_MLPMD0_MASK           0x7
+
+#define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET        28
+#define MXC_CRMAP_AMLPMRE1_MLPME9_MASK          (0x7 << 28)
+#define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET        25
+#define MXC_CRMAP_AMLPMRE1_MLPME8_MASK          (0x7 << 25)
+#define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET        22
+#define MXC_CRMAP_AMLPMRE1_MLPME7_MASK          (0x7 << 22)
+#define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET        19
+#define MXC_CRMAP_AMLPMRE1_MLPME6_MASK          (0x7 << 19)
+#define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET        16
+#define MXC_CRMAP_AMLPMRE1_MLPME5_MASK          (0x7 << 16)
+#define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET        12
+#define MXC_CRMAP_AMLPMRE1_MLPME4_MASK          (0x7 << 12)
+#define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET        9
+#define MXC_CRMAP_AMLPMRE1_MLPME3_MASK          (0x7 << 9)
+#define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET        6
+#define MXC_CRMAP_AMLPMRE1_MLPME2_MASK          (0x7 << 6)
+#define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET        3
+#define MXC_CRMAP_AMLPMRE1_MLPME1_MASK          (0x7 << 3)
+#define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET        0
+#define MXC_CRMAP_AMLPMRE1_MLPME0_MASK          0x7
+
+#define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET        0
+#define MXC_CRMAP_AMLPMRE2_MLPME0_MASK          0x7
+
+#define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET         19
+#define MXC_CRMAP_AMLPMRF_MLPMF6_MASK           (0x7 << 19)
+#define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET         16
+#define MXC_CRMAP_AMLPMRF_MLPMF5_MASK           (0x7 << 16)
+#define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET         9
+#define MXC_CRMAP_AMLPMRF_MLPMF3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET         6
+#define MXC_CRMAP_AMLPMRF_MLPMF2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET         3
+#define MXC_CRMAP_AMLPMRF_MLPMF1_MASK           (0x7 << 3)
+#define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET         0
+#define MXC_CRMAP_AMLPMRF_MLPMF0_MASK           (0x7 << 0)
+
+#define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET         28
+#define MXC_CRMAP_AMLPMRG_MLPMG9_MASK           (0x7 << 28)
+#define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET         22
+#define MXC_CRMAP_AMLPMRG_MLPMG7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET         19
+#define MXC_CRMAP_AMLPMRG_MLPMG6_MASK           (0x7 << 19)
+#define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET         16
+#define MXC_CRMAP_AMLPMRG_MLPMG5_MASK           (0x7 << 16)
+#define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET         12
+#define MXC_CRMAP_AMLPMRG_MLPMG4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET         9
+#define MXC_CRMAP_AMLPMRG_MLPMG3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET         6
+#define MXC_CRMAP_AMLPMRG_MLPMG2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET         3
+#define MXC_CRMAP_AMLPMRG_MLPMG1_MASK           (0x7 << 3)
+#define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET         0
+#define MXC_CRMAP_AMLPMRG_MLPMG0_MASK           0x7
+
+#define MXC_CRMAP_AGPR_IPUPAD_OFFSET            20
+#define MXC_CRMAP_AGPR_IPUPAD_MASK              (0x7 << 20)
+
+#define MXC_CRMAP_APRA_EL1TEN_OFFSET            29
+#define MXC_CRMAP_APRA_SIMEN_OFFSET             24
+#define MXC_CRMAP_APRA_UART3DIV_OFFSET          17
+#define MXC_CRMAP_APRA_UART3DIV_MASK            (0xF << 17)
+#define MXC_CRMAP_APRA_UART3EN_OFFSET           16
+#define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14
+#define MXC_CRMAP_APRA_MQSPIEN_OFFSET           13
+#define MXC_CRMAP_APRA_UART2EN_OFFSET           8
+#define MXC_CRMAP_APRA_UART1EN_OFFSET           0
+
+#define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET        13
+#define MXC_CRMAP_APRB_SDHC2_ISEL_MASK          (0x7 << 13)
+#define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET         9
+#define MXC_CRMAP_APRB_SDHC2_DIV_MASK           (0xF << 9)
+#define MXC_CRMAP_APRB_SDHC2EN_OFFSET           8
+#define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET        5
+#define MXC_CRMAP_APRB_SDHC1_ISEL_MASK          (0x7 << 5)
+#define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET         1
+#define MXC_CRMAP_APRB_SDHC1_DIV_MASK           (0xF << 1)
+#define MXC_CRMAP_APRB_SDHC1EN_OFFSET           0
+
+#define MXC_CRMAP_ACSR_ADS_OFFSET               8
+#define MXC_CRMAP_ACSR_ADS                      (0x1 << 8)
+#define MXC_CRMAP_ACSR_ACS                      0x1
+
+#define MXC_CRMAP_ADCR_LFDF_0                   (0x0 << 8)
+#define MXC_CRMAP_ADCR_LFDF_2                   (0x1 << 8)
+#define MXC_CRMAP_ADCR_LFDF_4                   (0x2 << 8)
+#define MXC_CRMAP_ADCR_LFDF_8                   (0x3 << 8)
+#define MXC_CRMAP_ADCR_LFDF_OFFSET              8
+#define MXC_CRMAP_ADCR_LFDF_MASK                (0x3 << 8)
+#define MXC_CRMAP_ADCR_ALT_PLL                  0x80
+#define MXC_CRMAP_ADCR_DFS_DIVEN                0x20
+#define MXC_CRMAP_ADCR_DIV_BYP                  0x2
+#define MXC_CRMAP_ADCR_VSTAT                    0x8
+#define MXC_CRMAP_ADCR_TSTAT                    0x10
+#define MXC_CRMAP_ADCR_DVFS_VCTRL               0x10
+#define MXC_CRMAP_ADCR_CLK_ON                   0x40
+
+#define MXC_CRMAP_ADFMR_FC_OFFSET               16
+#define MXC_CRMAP_ADFMR_FC_MASK                 (0x1F << 16)
+#define MXC_CRMAP_ADFMR_MF_OFFSET               1
+#define MXC_CRMAP_ADFMR_MF_MASK                 (0x3FF << 1)
+#define MXC_CRMAP_ADFMR_DFM_CLK_READY           0x1
+#define MXC_CRMAP_ADFMR_DFM_PWR_DOWN            0x8000
+
+#define MXC_CRMAP_ACR_CKOHS_HIGH                (1 << 18)
+#define MXC_CRMAP_ACR_CKOS_HIGH                 (1 << 16)
+#define MXC_CRMAP_ACR_CKOHS_MASK                (0x7 << 12)
+#define MXC_CRMAP_ACR_CKOHD                     (1 << 11)
+#define MXC_CRMAP_ACR_CKOHDIV_MASK              (0xF << 8)
+#define MXC_CRMAP_ACR_CKOHDIV_OFFSET            8
+#define MXC_CRMAP_ACR_CKOD                      (1 << 7)
+#define MXC_CRMAP_ACR_CKOS_MASK                 (0x7 << 4)
+
+/* AP Warm reset */
+#define MXC_CRMAP_AMCR_SW_AP                    (1 << 14)
+
+/* Bit definitions of ACGCR in CRM_AP for tree level clock gating */
+#define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT          0x00000001
+#define MXC_CRMAP_ACGCR_ACG0_STOP               0x00000003
+#define MXC_CRMAP_ACGCR_ACG0_RUN                0x00000007
+#define MXC_CRMAP_ACGCR_ACG0_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT          0x00000008
+#define MXC_CRMAP_ACGCR_ACG1_STOP               0x00000018
+#define MXC_CRMAP_ACGCR_ACG1_RUN                0x00000038
+#define MXC_CRMAP_ACGCR_ACG1_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT          0x00000040
+#define MXC_CRMAP_ACGCR_ACG2_STOP               0x000000C0
+#define MXC_CRMAP_ACGCR_ACG2_RUN                0x000001C0
+#define MXC_CRMAP_ACGCR_ACG2_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT          0x00000200
+#define MXC_CRMAP_ACGCR_ACG3_STOP               0x00000600
+#define MXC_CRMAP_ACGCR_ACG3_RUN                0x00000E00
+#define MXC_CRMAP_ACGCR_ACG3_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT          0x00001000
+#define MXC_CRMAP_ACGCR_ACG4_STOP               0x00003000
+#define MXC_CRMAP_ACGCR_ACG4_RUN                0x00007000
+#define MXC_CRMAP_ACGCR_ACG4_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT          0x00010000
+#define MXC_CRMAP_ACGCR_ACG5_STOP               0x00030000
+#define MXC_CRMAP_ACGCR_ACG5_RUN                0x00070000
+#define MXC_CRMAP_ACGCR_ACG5_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT          0x00080000
+#define MXC_CRMAP_ACGCR_ACG6_STOP               0x00180000
+#define MXC_CRMAP_ACGCR_ACG6_RUN                0x00380000
+#define MXC_CRMAP_ACGCR_ACG6_DISABLED           0x00000000
+
+#define NUM_GATE_CTRL                           6
+
+/* CRM COM Register Offsets */
+#define MXC_CRMCOM_CSCR                         (MXC_CRM_COM_BASE + 0x0C)
+#define MXC_CRMCOM_CCCR                         (MXC_CRM_COM_BASE + 0x10)
+
+/* CRM COM Bit Definitions */
+#define MXC_CRMCOM_CSCR_PPD1                    0x08000000
+#define MXC_CRMCOM_CSCR_CKOHSEL                 (1 << 18)
+#define MXC_CRMCOM_CSCR_CKOSEL                  (1 << 17)
+#define MXC_CRMCOM_CCCR_CC_DIV_OFFSET           8
+#define MXC_CRMCOM_CCCR_CC_DIV_MASK             (0x1F << 8)
+#define MXC_CRMCOM_CCCR_CC_SEL_OFFSET           0
+#define MXC_CRMCOM_CCCR_CC_SEL_MASK             0x3
+
+/* DSM Register Offsets */
+#define MXC_DSM_SLEEP_TIME                      (MXC_DSM_BASE + 0x0c)
+#define MXC_DSM_CONTROL0                        (MXC_DSM_BASE + 0x20)
+#define MXC_DSM_CONTROL1                        (MXC_DSM_BASE + 0x24)
+#define MXC_DSM_CTREN                           (MXC_DSM_BASE + 0x28)
+#define MXC_DSM_WARM_PER                        (MXC_DSM_BASE + 0x40)
+#define MXC_DSM_LOCK_PER                        (MXC_DSM_BASE + 0x44)
+#define MXC_DSM_MGPER                           (MXC_DSM_BASE + 0x4c)
+#define MXC_DSM_CRM_CONTROL                     (MXC_DSM_BASE + 0x50)
+
+/* Bit definitions of various registers in DSM */
+#define MXC_DSM_CRM_CTRL_DVFS_BYP               0x00000008
+#define MXC_DSM_CRM_CTRL_DVFS_VCTRL             0x00000004
+#define MXC_DSM_CRM_CTRL_LPMD1                  0x00000002
+#define MXC_DSM_CRM_CTRL_LPMD0                  0x00000001
+#define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE         0x00000000
+#define MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE         0x00000001
+#define MXC_DSM_CRM_CTRL_LPMD_RUN_MODE          0x00000003
+#define MXC_DSM_CONTROL0_STBY_COMMIT_EN         0x00000200
+#define MXC_DSM_CONTROL0_MSTR_EN                0x00000001
+#define MXC_DSM_CONTROL0_RESTART                0x00000010
+/* Counter Block reset */
+#define MXC_DSM_CONTROL1_CB_RST                 0x00000002
+/* State Machine reset */
+#define MXC_DSM_CONTROL1_SM_RST                 0x00000004
+/* Bit needed to reset counter block */
+#define MXC_CONTROL1_RST_CNT32                  0x00000008
+#define MXC_DSM_CONTROL1_RST_CNT32_EN           0x00000800
+#define MXC_DSM_CONTROL1_SLEEP                  0x00000100
+#define MXC_DSM_CONTROL1_WAKEUP_DISABLE         0x00004000
+#define MXC_DSM_CTREN_CNT32                     0x00000001
+
+/* Magic Fix enable bit */
+#define MXC_DSM_MGPER_EN_MGFX                   0x80000000
+#define MXC_DSM_MGPER_PER_MASK                  0x000003FF
+#define MXC_DSM_MGPER_PER(n)                    (MXC_DSM_MGPER_PER_MASK & n)
+
+/* Address offsets of the CLKCTL registers */
+#define MXC_CLKCTL_GP_CTRL      (MXC_CLKCTL_BASE + 0x00)
+#define MXC_CLKCTL_GP_SER       (MXC_CLKCTL_BASE + 0x04)
+#define MXC_CLKCTL_GP_CER       (MXC_CLKCTL_BASE + 0x08)
+
+#endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */
diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c
new file mode 100644
index 000000000000..353bd977b393
--- /dev/null
+++ b/arch/arm/mach-mxc91231/devices.c
@@ -0,0 +1,251 @@
+/*
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <linux/gpio.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/imx-uart.h>
+
+static struct resource uart0[] = {
+        {
+                .start = MXC91231_UART1_BASE_ADDR,
+                .end = MXC91231_UART1_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_UART1_RX,
+                .end = MXC91231_INT_UART1_RX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART1_TX,
+                .end = MXC91231_INT_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART1_MINT,
+                .end = MXC91231_INT_UART1_MINT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device0 = {
+        .name = "imx-uart",
+        .id = 0,
+        .resource = uart0,
+        .num_resources = ARRAY_SIZE(uart0),
+};
+
+static struct resource uart1[] = {
+        {
+                .start = MXC91231_UART2_BASE_ADDR,
+                .end = MXC91231_UART2_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_UART2_RX,
+                .end = MXC91231_INT_UART2_RX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART2_TX,
+                .end = MXC91231_INT_UART2_TX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART2_MINT,
+                .end = MXC91231_INT_UART2_MINT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device1 = {
+        .name = "imx-uart",
+        .id = 1,
+        .resource = uart1,
+        .num_resources = ARRAY_SIZE(uart1),
+};
+
+static struct resource uart2[] = {
+        {
+                .start = MXC91231_UART3_BASE_ADDR,
+                .end = MXC91231_UART3_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_UART3_RX,
+                .end = MXC91231_INT_UART3_RX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART3_TX,
+                .end = MXC91231_INT_UART3_TX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART3_MINT,
+                .end = MXC91231_INT_UART3_MINT,
+                .flags = IORESOURCE_IRQ,
+
+        },
+};
+
+struct platform_device mxc_uart_device2 = {
+        .name = "imx-uart",
+        .id = 2,
+        .resource = uart2,
+        .num_resources = ARRAY_SIZE(uart2),
+};
+
+/* GPIO port description */
+static struct mxc_gpio_port mxc_gpio_ports[] = {
+        [0] = {
+                .chip.label = "gpio-0",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO1_AP_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO1,
+                .virtual_irq_start = MXC_GPIO_IRQ_START,
+        },
+        [1] = {
+                .chip.label = "gpio-1",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO2_AP_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO2,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
+        },
+        [2] = {
+                .chip.label = "gpio-2",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO3_AP_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO3,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
+        },
+        [3] = {
+                .chip.label = "gpio-3",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO4_SH_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO4,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
+        },
+};
+
+int __init mxc_register_gpios(void)
+{
+        return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
+}
+
+static struct resource mxc_nand_resources[] = {
+        {
+                .start  = MXC91231_NFC_BASE_ADDR,
+                .end    = MXC91231_NFC_BASE_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM
+        }, {
+                .start  = MXC91231_INT_NANDFC,
+                .end    = MXC91231_INT_NANDFC,
+                .flags  = IORESOURCE_IRQ
+        },
+};
+
+struct platform_device mxc_nand_device = {
+        .name = "mxc_nand",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_nand_resources),
+        .resource = mxc_nand_resources,
+};
+
+static struct resource mxc_sdhc0_resources[] = {
+        {
+                .start = MXC91231_MMC_SDHC1_BASE_ADDR,
+                .end = MXC91231_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_MMC_SDHC1,
+                .end = MXC91231_INT_MMC_SDHC1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource mxc_sdhc1_resources[] = {
+        {
+                .start = MXC91231_MMC_SDHC2_BASE_ADDR,
+                .end = MXC91231_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_MMC_SDHC2,
+                .end = MXC91231_INT_MMC_SDHC2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_sdhc_device0 = {
+        .name = "mxc-mmc",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_sdhc0_resources),
+        .resource = mxc_sdhc0_resources,
+};
+
+struct platform_device mxc_sdhc_device1 = {
+        .name = "mxc-mmc",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
+        .resource = mxc_sdhc1_resources,
+};
+
+static struct resource mxc_cspi0_resources[] = {
+        {
+                .start = MXC91231_CSPI1_BASE_ADDR,
+                .end = MXC91231_CSPI1_BASE_ADDR + 0x20,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_CSPI1,
+                .end = MXC91231_INT_CSPI1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_cspi_device0 = {
+        .name = "spi_imx",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_cspi0_resources),
+        .resource = mxc_cspi0_resources,
+};
+
+static struct resource mxc_cspi1_resources[] = {
+        {
+                .start = MXC91231_CSPI2_BASE_ADDR,
+                .end = MXC91231_CSPI2_BASE_ADDR + 0x20,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_CSPI2,
+                .end = MXC91231_INT_CSPI2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_cspi_device1 = {
+        .name = "spi_imx",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_cspi1_resources),
+        .resource = mxc_cspi1_resources,
+};
+
+static struct resource mxc_wdog0_resources[] = {
+        {
+                .start = MXC91231_WDOG1_BASE_ADDR,
+                .end = MXC91231_WDOG1_BASE_ADDR + 0x10,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device mxc_wdog_device0 = {
+        .name = "mxc-wdt",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_wdog0_resources),
+        .resource = mxc_wdog0_resources,
+};
diff --git a/arch/arm/mach-mxc91231/devices.h b/arch/arm/mach-mxc91231/devices.h
new file mode 100644
index 000000000000..72a2136ce27d
--- /dev/null
+++ b/arch/arm/mach-mxc91231/devices.h
@@ -0,0 +1,13 @@
+extern struct platform_device mxc_uart_device0;
+extern struct platform_device mxc_uart_device1;
+extern struct platform_device mxc_uart_device2;
+
+extern struct platform_device mxc_nand_device;
+
+extern struct platform_device mxc_sdhc_device0;
+extern struct platform_device mxc_sdhc_device1;
+
+extern struct platform_device mxc_cspi_device0;
+extern struct platform_device mxc_cspi_device1;
+
+extern struct platform_device mxc_wdog_device0;
diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c
new file mode 100644
index 000000000000..405d9b19d891
--- /dev/null
+++ b/arch/arm/mach-mxc91231/iomux.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <mach/iomux-mxc91231.h>
+
+/*
+ * IOMUX register (base) addresses
+ */
+#define IOMUX_AP_BASE           MXC91231_IO_ADDRESS(MXC91231_IOMUX_AP_BASE_ADDR)
+#define IOMUX_COM_BASE          MXC91231_IO_ADDRESS(MXC91231_IOMUX_COM_BASE_ADDR)
+#define IOMUXSW_AP_MUX_CTL      (IOMUX_AP_BASE + 0x000)
+#define IOMUXSW_SP_MUX_CTL      (IOMUX_COM_BASE + 0x000)
+#define IOMUXSW_PAD_CTL         (IOMUX_COM_BASE + 0x200)
+
+#define IOMUXINT_OBS1           (IOMUX_AP_BASE + 0x600)
+#define IOMUXINT_OBS2           (IOMUX_AP_BASE + 0x004)
+
+static DEFINE_SPINLOCK(gpio_mux_lock);
+
+#define NB_PORTS                        ((PIN_MAX + 32) / 32)
+#define PIN_GLOBAL_NUM(pin) \
+        (((pin & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT)*PIN_AP_MAX + \
+         ((pin & MUX_REG_MASK) >> MUX_REG_SHIFT)*4 +            \
+         ((pin & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT))
+
+unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
+/*
+ * set the mode for a IOMUX pin.
+ */
+int mxc_iomux_mode(const unsigned int pin_mode)
+{
+        u32 side, field, l, mode, ret = 0;
+        void __iomem *reg;
+
+        side = (pin_mode & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT;
+        switch (side) {
+        case MUX_SIDE_AP:
+                reg = IOMUXSW_AP_MUX_CTL;
+                break;
+        case MUX_SIDE_SP:
+                reg = IOMUXSW_SP_MUX_CTL;
+                break;
+        default:
+                return -EINVAL;
+        }
+        reg += ((pin_mode & MUX_REG_MASK) >> MUX_REG_SHIFT) * 4;
+        field = (pin_mode & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT;
+        mode = (pin_mode & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+
+        spin_lock(&gpio_mux_lock);
+
+        l = __raw_readl(reg);
+        l &= ~(0xff << (field * 8));
+        l |= mode << (field * 8);
+        __raw_writel(l, reg);
+
+        spin_unlock(&gpio_mux_lock);
+
+        return ret;
+}
+EXPORT_SYMBOL(mxc_iomux_mode);
+
+/*
+ * This function configures the pad value for a IOMUX pin.
+ */
+void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
+{
+        u32 padgrp, field, l;
+        void __iomem *reg;
+
+        padgrp = (pin & MUX_PADGRP_MASK) >> MUX_PADGRP_SHIFT;
+        reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
+        field = (pin + 2) % 3;
+
+        pr_debug("%s: reg offset = 0x%x, field = %d\n",
+                        __func__, (pin + 2) / 3, field);
+
+        spin_lock(&gpio_mux_lock);
+
+        l = __raw_readl(reg);
+        l &= ~(0x1ff << (field * 10));
+        l |= config << (field * 10);
+        __raw_writel(l, reg);
+
+        spin_unlock(&gpio_mux_lock);
+}
+EXPORT_SYMBOL(mxc_iomux_set_pad);
+
+/*
+ * allocs a single pin:
+ *      - reserves the pin so that it is not claimed by another driver
+ *      - setups the iomux according to the configuration
+ */
+int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label)
+{
+        unsigned pad = PIN_GLOBAL_NUM(pin_mode);
+        if (pad >= (PIN_MAX + 1)) {
+                printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
+                        pad, label ? label : "?");
+                return -EINVAL;
+        }
+
+        if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
+                printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
+                        pad, label ? label : "?");
+                return -EBUSY;
+        }
+        mxc_iomux_mode(pin_mode);
+
+        return 0;
+}
+EXPORT_SYMBOL(mxc_iomux_alloc_pin);
+
+int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+                const char *label)
+{
+        unsigned int *p = pin_list;
+        int i;
+        int ret = -EINVAL;
+
+        for (i = 0; i < count; i++) {
+                ret = mxc_iomux_alloc_pin(*p, label);
+                if (ret)
+                        goto setup_error;
+                p++;
+        }
+        return 0;
+
+setup_error:
+        mxc_iomux_release_multiple_pins(pin_list, i);
+        return ret;
+}
+EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
+
+void mxc_iomux_release_pin(const unsigned int pin_mode)
+{
+        unsigned pad = PIN_GLOBAL_NUM(pin_mode);
+
+        if (pad < (PIN_MAX + 1))
+                clear_bit(pad, mxc_pin_alloc_map);
+}
+EXPORT_SYMBOL(mxc_iomux_release_pin);
+
+void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
+{
+        unsigned int *p = pin_list;
+        int i;
+
+        for (i = 0; i < count; i++) {
+                mxc_iomux_release_pin(*p);
+                p++;
+        }
+}
+EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
new file mode 100644
index 000000000000..7dbe4ca12efd
--- /dev/null
+++ b/arch/arm/mach-mxc91231/magx-zn5.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
+ *
+ * This file is released under the GPLv2 or later.
+ */
+
+#include <linux/irq.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/time.h>
+#include <asm/mach/arch.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mxc91231.h>
+#include <mach/mmc.h>
+#include <mach/imx-uart.h>
+
+#include "devices.h"
+
+static struct imxuart_platform_data uart_pdata = {
+};
+
+static struct imxmmc_platform_data sdhc_pdata = {
+};
+
+static void __init zn5_init(void)
+{
+        pm_power_off = mxc91231_power_off;
+
+        mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_DAT_VP__RXD2, "uart2-rx");
+        mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_SE0_VM__TXD2, "uart2-tx");
+
+        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+
+        mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
+
+        mxc_register_device(&mxc_wdog_device0, NULL);
+
+        return;
+}
+
+static void __init zn5_timer_init(void)
+{
+        mxc91231_clocks_init(26000000); /* 26mhz ckih */
+}
+
+struct sys_timer zn5_timer = {
+        .init = zn5_timer_init,
+};
+
+MACHINE_START(MAGX_ZN5, "Motorola Zn5")
+        .phys_io        = MXC91231_AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mxc91231_map_io,
+        .init_irq       = mxc91231_init_irq,
+        .timer          = &zn5_timer,
+        .init_machine   = zn5_init,
+MACHINE_END
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
new file mode 100644
index 000000000000..6becda3ff331
--- /dev/null
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -0,0 +1,94 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2004-2005 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MXC specific definitions
+ *  Copyright 2006 Motorola, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+
+/*
+ * This structure defines the MXC memory map.
+ */
+static struct map_desc mxc_io_desc[] __initdata = {
+        {
+                .virtual        = MXC91231_L2CC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_L2CC_BASE_ADDR),
+                .length         = MXC91231_L2CC_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_X_MEMC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_X_MEMC_BASE_ADDR),
+                .length         = MXC91231_X_MEMC_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_ROMP_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_ROMP_BASE_ADDR),
+                .length         = MXC91231_ROMP_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_AVIC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_AVIC_BASE_ADDR),
+                .length         = MXC91231_AVIC_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_AIPS1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_AIPS1_BASE_ADDR),
+                .length         = MXC91231_AIPS1_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_SPBA0_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_SPBA0_BASE_ADDR),
+                .length         = MXC91231_SPBA0_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_SPBA1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_SPBA1_BASE_ADDR),
+                .length         = MXC91231_SPBA1_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_AIPS2_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_AIPS2_BASE_ADDR),
+                .length         = MXC91231_AIPS2_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory map for
+ * the IO modules.
+ */
+void __init mxc91231_map_io(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MXC91231);
+
+        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
+
+void __init mxc91231_init_irq(void)
+{
+        mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
+}
diff --git a/arch/arm/mach-mxc91231/system.c b/arch/arm/mach-mxc91231/system.c
new file mode 100644
index 000000000000..736f7efd874a
--- /dev/null
+++ b/arch/arm/mach-mxc91231/system.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
+ *
+ * This file is released under the GPLv2 or later.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <asm/proc-fns.h>
+#include <mach/hardware.h>
+
+#include "crm_regs.h"
+
+#define WDOG_WCR                MXC91231_IO_ADDRESS(MXC91231_WDOG1_BASE_ADDR)
+#define WDOG_WCR_OUT_ENABLE     (1 << 6)
+#define WDOG_WCR_ASSERT         (1 << 5)
+
+void mxc91231_power_off(void)
+{
+        u16 wcr;
+
+        wcr = __raw_readw(WDOG_WCR);
+        wcr |= WDOG_WCR_OUT_ENABLE;
+        wcr &= ~WDOG_WCR_ASSERT;
+        __raw_writew(wcr, WDOG_WCR);
+}
+
+void mxc91231_arch_reset(char mode, const char *cmd)
+{
+        u32 amcr;
+
+        /* Reset the AP using CRM */
+        amcr = __raw_readl(MXC_CRMAP_AMCR);
+        amcr &= ~MXC_CRMAP_AMCR_SW_AP;
+        __raw_writel(amcr, MXC_CRMAP_AMCR);
+
+        mdelay(10);
+        cpu_reset(0);
+}
+
+void mxc91231_prepare_idle(void)
+{
+        u32 crm_ctl;
+
+        /* Go to WAIT mode after WFI */
+        crm_ctl = __raw_readl(MXC_DSM_CRM_CONTROL);
+        crm_ctl &= ~(MXC_DSM_CRM_CTRL_LPMD0 | MXC_DSM_CRM_CTRL_LPMD1);
+        crm_ctl |=  MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE;
+        __raw_writel(crm_ctl, MXC_DSM_CRM_CONTROL);
+}
diff --git a/arch/arm/mach-netx/include/mach/entry-macro.S b/arch/arm/mach-netx/include/mach/entry-macro.S
index a1952a0feda6..844f1f9acbdf 100644
--- a/arch/arm/mach-netx/include/mach/entry-macro.S
+++ b/arch/arm/mach-netx/include/mach/entry-macro.S
@@ -24,15 +24,13 @@
                 .endm
 
                 .macro  get_irqnr_preamble, base, tmp
+                ldr     \base, =io_p2v(0x001ff000)
                 .endm
 
                 .macro  arch_ret_to_user, tmp1, tmp2
                 .endm
 
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mov     \base, #io_p2v(0x00100000)
-                add     \base, \base, #0x000ff000
-
                 ldr     \irqstat, [\base, #0]
                 clz     \irqnr, \irqstat
                 rsb     \irqnr, \irqnr, #31
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
new file mode 100644
index 000000000000..2a02b49c40f0
--- /dev/null
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -0,0 +1,21 @@
+if ARCH_NOMADIK
+
+menu "Nomadik boards"
+
+config MACH_NOMADIK_8815NHK
+        bool "ST 8815 Nomadik Hardware Kit (evaluation board)"
+        select NOMADIK_8815
+
+endmenu
+
+config NOMADIK_8815
+        bool
+
+
+config I2C_BITBANG_8815NHK
+        tristate "Driver for bit-bang busses found on the 8815 NHK"
+        depends on I2C && MACH_NOMADIK_8815NHK
+        select I2C_ALGOBIT
+        default y
+
+endif
diff --git a/arch/arm/mach-nomadik/Makefile b/arch/arm/mach-nomadik/Makefile
new file mode 100644
index 000000000000..412040982a40
--- /dev/null
+++ b/arch/arm/mach-nomadik/Makefile
@@ -0,0 +1,19 @@
+#
+# Makefile for the linux kernel.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+
+# Object file lists.
+
+obj-y                   += clock.o timer.o gpio.o
+
+# Cpu revision
+obj-$(CONFIG_NOMADIK_8815) += cpu-8815.o
+
+# Specific board support
+obj-$(CONFIG_MACH_NOMADIK_8815NHK) += board-nhk8815.o
+
+# Nomadik extra devices
+obj-$(CONFIG_I2C_BITBANG_8815NHK) += i2c-8815nhk.o
diff --git a/arch/arm/mach-nomadik/Makefile.boot b/arch/arm/mach-nomadik/Makefile.boot
new file mode 100644
index 000000000000..c7e75acfe6c9
--- /dev/null
+++ b/arch/arm/mach-nomadik/Makefile.boot
@@ -0,0 +1,4 @@
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
+
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
new file mode 100644
index 000000000000..79bdea943eb4
--- /dev/null
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -0,0 +1,111 @@
+/*
+ *  linux/arch/arm/mach-nomadik/board-8815nhk.c
+ *
+ *  Copyright (C) STMicroelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ *  NHK15 board specifc driver definition
+ */
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <mach/setup.h>
+#include "clock.h"
+
+#define __MEM_4K_RESOURCE(x) \
+        .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
+
+static struct amba_device uart0_device = {
+        .dev = { .init_name = "uart0" },
+        __MEM_4K_RESOURCE(NOMADIK_UART0_BASE),
+        .irq = {IRQ_UART0, NO_IRQ},
+};
+
+static struct amba_device uart1_device = {
+        .dev = { .init_name = "uart1" },
+        __MEM_4K_RESOURCE(NOMADIK_UART1_BASE),
+        .irq = {IRQ_UART1, NO_IRQ},
+};
+
+static struct amba_device *amba_devs[] __initdata = {
+        &uart0_device,
+        &uart1_device,
+};
+
+/* We have a fixed clock alone, by now */
+static struct clk nhk8815_clk_48 = {
+        .rate = 48*1000*1000,
+};
+
+static struct resource nhk8815_eth_resources[] = {
+        {
+                .name = "smc91x-regs",
+                .start = 0x34000000 + 0x300,
+                .end = 0x34000000 + SZ_64K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = NOMADIK_GPIO_TO_IRQ(115),
+                .end = NOMADIK_GPIO_TO_IRQ(115),
+                .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING,
+        }
+};
+
+static struct platform_device nhk8815_eth_device = {
+        .name = "smc91x",
+        .resource = nhk8815_eth_resources,
+        .num_resources = ARRAY_SIZE(nhk8815_eth_resources),
+};
+
+static int __init nhk8815_eth_init(void)
+{
+        int gpio_nr = 115; /* hardwired in the board */
+        int err;
+
+        err = gpio_request(gpio_nr, "eth_irq");
+        if (!err) err = nmk_gpio_set_mode(gpio_nr, NMK_GPIO_ALT_GPIO);
+        if (!err) err = gpio_direction_input(gpio_nr);
+        if (err)
+                pr_err("Error %i in %s\n", err, __func__);
+        return err;
+}
+device_initcall(nhk8815_eth_init);
+
+static struct platform_device *nhk8815_platform_devices[] __initdata = {
+        &nhk8815_eth_device,
+        /* will add more devices */
+};
+
+static void __init nhk8815_platform_init(void)
+{
+        int i;
+
+        cpu8815_platform_init();
+        platform_add_devices(nhk8815_platform_devices,
+                             ARRAY_SIZE(nhk8815_platform_devices));
+
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                nmdk_clk_create(&nhk8815_clk_48, amba_devs[i]->dev.init_name);
+                amba_device_register(amba_devs[i], &iomem_resource);
+        }
+}
+
+MACHINE_START(NOMADIK, "NHK8815")
+        /* Maintainer: ST MicroElectronics */
+        .phys_io        = NOMADIK_UART0_BASE,
+        .io_pg_offst    = (IO_ADDRESS(NOMADIK_UART0_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x100,
+        .map_io         = cpu8815_map_io,
+        .init_irq       = cpu8815_init_irq,
+        .timer          = &nomadik_timer,
+        .init_machine   = nhk8815_platform_init,
+MACHINE_END
diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c
new file mode 100644
index 000000000000..9f92502a0083
--- /dev/null
+++ b/arch/arm/mach-nomadik/clock.c
@@ -0,0 +1,45 @@
+/*
+ *  linux/arch/arm/mach-nomadik/clock.c
+ *
+ *  Copyright (C) 2009 Alessandro Rubini
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <asm/clkdev.h>
+#include "clock.h"
+
+/*
+ * The nomadik board uses generic clocks, but the serial pl011 file
+ * calls clk_enable(), clk_disable(), clk_get_rate(), so we provide them
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+/* enable and disable do nothing */
+int clk_enable(struct clk *clk)
+{
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+/* Create a clock structure with the given name */
+int nmdk_clk_create(struct clk *clk, const char *dev_id)
+{
+        struct clk_lookup *clkdev;
+
+        clkdev = clkdev_alloc(clk, NULL, dev_id);
+        if (!clkdev)
+                return -ENOMEM;
+        clkdev_add(clkdev);
+        return 0;
+}
diff --git a/arch/arm/mach-nomadik/clock.h b/arch/arm/mach-nomadik/clock.h
new file mode 100644
index 000000000000..235faec7f627
--- /dev/null
+++ b/arch/arm/mach-nomadik/clock.h
@@ -0,0 +1,14 @@
+
+/*
+ *  linux/arch/arm/mach-nomadik/clock.h
+ *
+ *  Copyright (C) 2009 Alessandro Rubini
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+struct clk {
+        unsigned long           rate;
+};
+extern int nmdk_clk_create(struct clk *clk, const char *dev_id);
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
new file mode 100644
index 000000000000..f93c59634191
--- /dev/null
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright STMicroelectronics, 2007.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/amba/bus.h>
+#include <linux/gpio.h>
+
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/vic.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-l2x0.h>
+
+/* The 8815 has 4 GPIO blocks, let's register them immediately */
+static struct nmk_gpio_platform_data cpu8815_gpio[] = {
+        {
+                .name = "GPIO-0-31",
+                .first_gpio = 0,
+                .first_irq = NOMADIK_GPIO_TO_IRQ(0),
+                .parent_irq = IRQ_GPIO0,
+        }, {
+                .name = "GPIO-32-63",
+                .first_gpio = 32,
+                .first_irq = NOMADIK_GPIO_TO_IRQ(32),
+                .parent_irq = IRQ_GPIO1,
+        }, {
+                .name = "GPIO-64-95",
+                .first_gpio = 64,
+                .first_irq = NOMADIK_GPIO_TO_IRQ(64),
+                .parent_irq = IRQ_GPIO2,
+        }, {
+                .name = "GPIO-96-127", /* 124..127 not routed to pin */
+                .first_gpio = 96,
+                .first_irq = NOMADIK_GPIO_TO_IRQ(96),
+                .parent_irq = IRQ_GPIO3,
+        }
+};
+
+#define __MEM_4K_RESOURCE(x) \
+        .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
+
+static struct amba_device cpu8815_amba_gpio[] = {
+        {
+                .dev = {
+                        .init_name = "gpio0",
+                        .platform_data = cpu8815_gpio + 0,
+                },
+                __MEM_4K_RESOURCE(NOMADIK_GPIO0_BASE),
+        }, {
+                .dev = {
+                        .init_name = "gpio1",
+                        .platform_data = cpu8815_gpio + 1,
+                },
+                __MEM_4K_RESOURCE(NOMADIK_GPIO1_BASE),
+        }, {
+                .dev = {
+                        .init_name = "gpio2",
+                        .platform_data = cpu8815_gpio + 2,
+                },
+                __MEM_4K_RESOURCE(NOMADIK_GPIO2_BASE),
+        }, {
+                .dev = {
+                        .init_name = "gpio3",
+                        .platform_data = cpu8815_gpio + 3,
+                },
+                __MEM_4K_RESOURCE(NOMADIK_GPIO3_BASE),
+        },
+};
+
+static struct amba_device *amba_devs[] __initdata = {
+        cpu8815_amba_gpio + 0,
+        cpu8815_amba_gpio + 1,
+        cpu8815_amba_gpio + 2,
+        cpu8815_amba_gpio + 3,
+};
+
+static int __init cpu8815_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+                amba_device_register(amba_devs[i], &iomem_resource);
+        return 0;
+}
+arch_initcall(cpu8815_init);
+
+/* All SoC devices live in the same area (see hardware.h) */
+static struct map_desc nomadik_io_desc[] __initdata = {
+        {
+                .virtual =      NOMADIK_IO_VIRTUAL,
+                .pfn =          __phys_to_pfn(NOMADIK_IO_PHYSICAL),
+                .length =       NOMADIK_IO_SIZE,
+                .type =         MT_DEVICE,
+        }
+        /* static ram and secured ram may be added later */
+};
+
+void __init cpu8815_map_io(void)
+{
+        iotable_init(nomadik_io_desc, ARRAY_SIZE(nomadik_io_desc));
+}
+
+void __init cpu8815_init_irq(void)
+{
+        /* This modified VIC cell has two register blocks, at 0 and 0x20 */
+        vic_init(io_p2v(NOMADIK_IC_BASE + 0x00), IRQ_VIC_START +  0, ~0, 0);
+        vic_init(io_p2v(NOMADIK_IC_BASE + 0x20), IRQ_VIC_START + 32, ~0, 0);
+}
+
+/*
+ * This function is called from the board init ("init_machine").
+ */
+ void __init cpu8815_platform_init(void)
+{
+#ifdef CONFIG_CACHE_L2X0
+        /* At full speed latency must be >=2, so 0x249 in low bits */
+        l2x0_init(io_p2v(NOMADIK_L2CC_BASE), 0x00730249, 0xfe000fff);
+#endif
+         return;
+}
diff --git a/arch/arm/mach-nomadik/gpio.c b/arch/arm/mach-nomadik/gpio.c
new file mode 100644
index 000000000000..9a09b2791e03
--- /dev/null
+++ b/arch/arm/mach-nomadik/gpio.c
@@ -0,0 +1,396 @@
+/*
+ * Generic GPIO driver for logic cells found in the Nomadik SoC
+ *
+ * Copyright (C) 2008,2009 STMicroelectronics
+ * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
+ *   Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/amba/bus.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+
+/*
+ * The GPIO module in the Nomadik family of Systems-on-Chip is an
+ * AMBA device, managing 32 pins and alternate functions.  The logic block
+ * is currently only used in the Nomadik.
+ *
+ * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
+ */
+
+#define NMK_GPIO_PER_CHIP 32
+struct nmk_gpio_chip {
+        struct gpio_chip chip;
+        void __iomem *addr;
+        unsigned int parent_irq;
+        spinlock_t *lock;
+        /* Keep track of configured edges */
+        u32 edge_rising;
+        u32 edge_falling;
+};
+
+/* Mode functions */
+int nmk_gpio_set_mode(int gpio, int gpio_mode)
+{
+        struct nmk_gpio_chip *nmk_chip;
+        unsigned long flags;
+        u32 afunc, bfunc, bit;
+
+        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        if (!nmk_chip)
+                return -EINVAL;
+
+        bit = 1 << (gpio - nmk_chip->chip.base);
+
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+        afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
+        bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
+        if (gpio_mode & NMK_GPIO_ALT_A)
+                afunc |= bit;
+        if (gpio_mode & NMK_GPIO_ALT_B)
+                bfunc |= bit;
+        writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
+        writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(nmk_gpio_set_mode);
+
+int nmk_gpio_get_mode(int gpio)
+{
+        struct nmk_gpio_chip *nmk_chip;
+        u32 afunc, bfunc, bit;
+
+        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        if (!nmk_chip)
+                return -EINVAL;
+
+        bit = 1 << (gpio - nmk_chip->chip.base);
+
+        afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
+        bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
+
+        return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
+}
+EXPORT_SYMBOL(nmk_gpio_get_mode);
+
+
+/* IRQ functions */
+static inline int nmk_gpio_get_bitmask(int gpio)
+{
+        return 1 << (gpio % 32);
+}
+
+static void nmk_gpio_irq_ack(unsigned int irq)
+{
+        int gpio;
+        struct nmk_gpio_chip *nmk_chip;
+
+        gpio = NOMADIK_IRQ_TO_GPIO(irq);
+        nmk_chip = get_irq_chip_data(irq);
+        if (!nmk_chip)
+                return;
+        writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
+}
+
+static void nmk_gpio_irq_mask(unsigned int irq)
+{
+        int gpio;
+        struct nmk_gpio_chip *nmk_chip;
+        unsigned long flags;
+        u32 bitmask, reg;
+
+        gpio = NOMADIK_IRQ_TO_GPIO(irq);
+        nmk_chip = get_irq_chip_data(irq);
+        bitmask = nmk_gpio_get_bitmask(gpio);
+        if (!nmk_chip)
+                return;
+
+        /* we must individually clear the two edges */
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+        if (nmk_chip->edge_rising & bitmask) {
+                reg = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
+                reg &= ~bitmask;
+                writel(reg, nmk_chip->addr + NMK_GPIO_RWIMSC);
+        }
+        if (nmk_chip->edge_falling & bitmask) {
+                reg = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
+                reg &= ~bitmask;
+                writel(reg, nmk_chip->addr + NMK_GPIO_FWIMSC);
+        }
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+};
+
+static void nmk_gpio_irq_unmask(unsigned int irq)
+{
+        int gpio;
+        struct nmk_gpio_chip *nmk_chip;
+        unsigned long flags;
+        u32 bitmask, reg;
+
+        gpio = NOMADIK_IRQ_TO_GPIO(irq);
+        nmk_chip = get_irq_chip_data(irq);
+        bitmask = nmk_gpio_get_bitmask(gpio);
+        if (!nmk_chip)
+                return;
+
+        /* we must individually set the two edges */
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+        if (nmk_chip->edge_rising & bitmask) {
+                reg = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
+                reg |= bitmask;
+                writel(reg, nmk_chip->addr + NMK_GPIO_RWIMSC);
+        }
+        if (nmk_chip->edge_falling & bitmask) {
+                reg = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
+                reg |= bitmask;
+                writel(reg, nmk_chip->addr + NMK_GPIO_FWIMSC);
+        }
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+}
+
+static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
+{
+        int gpio;
+        struct nmk_gpio_chip *nmk_chip;
+        unsigned long flags;
+        u32 bitmask;
+
+        gpio = NOMADIK_IRQ_TO_GPIO(irq);
+        nmk_chip = get_irq_chip_data(irq);
+        bitmask = nmk_gpio_get_bitmask(gpio);
+        if (!nmk_chip)
+                return -EINVAL;
+
+        if (type & IRQ_TYPE_LEVEL_HIGH)
+                return -EINVAL;
+        if (type & IRQ_TYPE_LEVEL_LOW)
+                return -EINVAL;
+
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+
+        nmk_chip->edge_rising &= ~bitmask;
+        if (type & IRQ_TYPE_EDGE_RISING)
+                nmk_chip->edge_rising |= bitmask;
+        writel(nmk_chip->edge_rising, nmk_chip->addr + NMK_GPIO_RIMSC);
+
+        nmk_chip->edge_falling &= ~bitmask;
+        if (type & IRQ_TYPE_EDGE_FALLING)
+                nmk_chip->edge_falling |= bitmask;
+        writel(nmk_chip->edge_falling, nmk_chip->addr + NMK_GPIO_FIMSC);
+
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+        nmk_gpio_irq_unmask(irq);
+
+        return 0;
+}
+
+static struct irq_chip nmk_gpio_irq_chip = {
+        .name           = "Nomadik-GPIO",
+        .ack            = nmk_gpio_irq_ack,
+        .mask           = nmk_gpio_irq_mask,
+        .unmask         = nmk_gpio_irq_unmask,
+        .set_type       = nmk_gpio_irq_set_type,
+};
+
+static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        struct nmk_gpio_chip *nmk_chip;
+        struct irq_chip *host_chip;
+        unsigned int gpio_irq;
+        u32 pending;
+        unsigned int first_irq;
+
+        nmk_chip = get_irq_data(irq);
+        first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
+        while ( (pending = readl(nmk_chip->addr + NMK_GPIO_IS)) ) {
+                gpio_irq = first_irq + __ffs(pending);
+                generic_handle_irq(gpio_irq);
+        }
+        if (0) {/* don't ack parent irq, as ack == disable */
+                host_chip = get_irq_chip(irq);
+                host_chip->ack(irq);
+        }
+}
+
+static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
+{
+        unsigned int first_irq;
+        int i;
+
+        first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
+        for (i = first_irq; i < first_irq + NMK_GPIO_PER_CHIP; i++) {
+                set_irq_chip(i, &nmk_gpio_irq_chip);
+                set_irq_handler(i, handle_edge_irq);
+                set_irq_flags(i, IRQF_VALID);
+                set_irq_chip_data(i, nmk_chip);
+        }
+        set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
+        set_irq_data(nmk_chip->parent_irq, nmk_chip);
+        return 0;
+}
+
+/* I/O Functions */
+static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct nmk_gpio_chip *nmk_chip =
+                container_of(chip, struct nmk_gpio_chip, chip);
+
+        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
+        return 0;
+}
+
+static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
+                                int val)
+{
+        struct nmk_gpio_chip *nmk_chip =
+                container_of(chip, struct nmk_gpio_chip, chip);
+
+        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
+        return 0;
+}
+
+static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct nmk_gpio_chip *nmk_chip =
+                container_of(chip, struct nmk_gpio_chip, chip);
+        u32 bit = 1 << offset;
+
+        return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
+}
+
+static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
+                                int val)
+{
+        struct nmk_gpio_chip *nmk_chip =
+                container_of(chip, struct nmk_gpio_chip, chip);
+        u32 bit = 1 << offset;
+
+        if (val)
+                writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
+        else
+                writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
+}
+
+/* This structure is replicated for each GPIO block allocated at probe time */
+static struct gpio_chip nmk_gpio_template = {
+        .direction_input        = nmk_gpio_make_input,
+        .get                    = nmk_gpio_get_input,
+        .direction_output       = nmk_gpio_make_output,
+        .set                    = nmk_gpio_set_output,
+        .ngpio                  = NMK_GPIO_PER_CHIP,
+        .can_sleep              = 0,
+};
+
+static int __init nmk_gpio_probe(struct amba_device *dev, struct amba_id *id)
+{
+        struct nmk_gpio_platform_data *pdata;
+        struct nmk_gpio_chip *nmk_chip;
+        struct gpio_chip *chip;
+        int ret;
+
+        pdata = dev->dev.platform_data;
+        ret = amba_request_regions(dev, pdata->name);
+        if (ret)
+                return ret;
+
+        nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
+        if (!nmk_chip) {
+                ret = -ENOMEM;
+                goto out_amba;
+        }
+        /*
+         * The virt address in nmk_chip->addr is in the nomadik register space,
+         * so we can simply convert the resource address, without remapping
+         */
+        nmk_chip->addr = io_p2v(dev->res.start);
+        nmk_chip->chip = nmk_gpio_template;
+        nmk_chip->parent_irq = pdata->parent_irq;
+
+        chip = &nmk_chip->chip;
+        chip->base = pdata->first_gpio;
+        chip->label = pdata->name;
+        chip->dev = &dev->dev;
+        chip->owner = THIS_MODULE;
+
+        ret = gpiochip_add(&nmk_chip->chip);
+        if (ret)
+                goto out_free;
+
+        amba_set_drvdata(dev, nmk_chip);
+
+        nmk_gpio_init_irq(nmk_chip);
+
+        dev_info(&dev->dev, "Bits %i-%i at address %p\n",
+                 nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr);
+        return 0;
+
+ out_free:
+        kfree(nmk_chip);
+ out_amba:
+        amba_release_regions(dev);
+        dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
+                  pdata->first_gpio, pdata->first_gpio+31);
+        return ret;
+}
+
+static int nmk_gpio_remove(struct amba_device *dev)
+{
+        struct nmk_gpio_chip *nmk_chip;
+
+        nmk_chip = amba_get_drvdata(dev);
+        gpiochip_remove(&nmk_chip->chip);
+        kfree(nmk_chip);
+        amba_release_regions(dev);
+        return 0;
+}
+
+
+/* We have 0x1f080060 and 0x1f180060, accept both using the mask */
+static struct amba_id nmk_gpio_ids[] = {
+        {
+                .id     = 0x1f080060,
+                .mask   = 0xffefffff,
+        },
+        {0, 0},
+};
+
+static struct amba_driver nmk_gpio_driver = {
+        .drv = {
+                .owner = THIS_MODULE,
+                .name = "gpio",
+                },
+        .probe = nmk_gpio_probe,
+        .remove = nmk_gpio_remove,
+        .suspend = NULL, /* to be done */
+        .resume = NULL,
+        .id_table = nmk_gpio_ids,
+};
+
+static int __init nmk_gpio_init(void)
+{
+        return amba_driver_register(&nmk_gpio_driver);
+}
+
+arch_initcall(nmk_gpio_init);
+
+MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
+MODULE_DESCRIPTION("Nomadik GPIO Driver");
+MODULE_LICENSE("GPL");
+
+
diff --git a/arch/arm/mach-nomadik/i2c-8815nhk.c b/arch/arm/mach-nomadik/i2c-8815nhk.c
new file mode 100644
index 000000000000..abfe25a08d6b
--- /dev/null
+++ b/arch/arm/mach-nomadik/i2c-8815nhk.c
@@ -0,0 +1,65 @@
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <linux/i2c-gpio.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+/*
+ * There are two busses in the 8815NHK.
+ * They could, in theory, be driven by the hardware component, but we
+ * use bit-bang through GPIO by now, to keep things simple
+ */
+
+static struct i2c_gpio_platform_data nhk8815_i2c_data0 = {
+        /* keep defaults for timeouts; pins are push-pull bidirectional */
+        .scl_pin = 62,
+        .sda_pin = 63,
+};
+
+static struct i2c_gpio_platform_data nhk8815_i2c_data1 = {
+        /* keep defaults for timeouts; pins are push-pull bidirectional */
+        .scl_pin = 53,
+        .sda_pin = 54,
+};
+
+/* first bus: GPIO XX and YY */
+static struct platform_device nhk8815_i2c_dev0 = {
+        .name   = "i2c-gpio",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &nhk8815_i2c_data0,
+        },
+};
+/* second bus: GPIO XX and YY */
+static struct platform_device nhk8815_i2c_dev1 = {
+        .name   = "i2c-gpio",
+        .id     = 1,
+        .dev    = {
+                .platform_data = &nhk8815_i2c_data1,
+        },
+};
+
+static int __init nhk8815_i2c_init(void)
+{
+        nmk_gpio_set_mode(nhk8815_i2c_data0.scl_pin, NMK_GPIO_ALT_GPIO);
+        nmk_gpio_set_mode(nhk8815_i2c_data0.sda_pin, NMK_GPIO_ALT_GPIO);
+        platform_device_register(&nhk8815_i2c_dev0);
+
+        nmk_gpio_set_mode(nhk8815_i2c_data1.scl_pin, NMK_GPIO_ALT_GPIO);
+        nmk_gpio_set_mode(nhk8815_i2c_data1.sda_pin, NMK_GPIO_ALT_GPIO);
+        platform_device_register(&nhk8815_i2c_dev1);
+
+        return 0;
+}
+
+static void __exit nhk8815_i2c_exit(void)
+{
+        platform_device_unregister(&nhk8815_i2c_dev0);
+        platform_device_unregister(&nhk8815_i2c_dev1);
+        return;
+}
+
+module_init(nhk8815_i2c_init);
+module_exit(nhk8815_i2c_exit);
diff --git a/arch/arm/mach-nomadik/include/mach/clkdev.h b/arch/arm/mach-nomadik/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-nomadik/include/mach/debug-macro.S b/arch/arm/mach-nomadik/include/mach/debug-macro.S
new file mode 100644
index 000000000000..e876990e1569
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/debug-macro.S
@@ -0,0 +1,22 @@
+/*
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x10000000        @ physical base address
+                movne   \rx, #0xf0000000        @ virtual base
+                add     \rx, \rx, #0x00100000
+                add     \rx, \rx, #0x000fb000
+                .endm
+
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-nomadik/include/mach/entry-macro.S b/arch/arm/mach-nomadik/include/mach/entry-macro.S
new file mode 100644
index 000000000000..49f1aa3bb420
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/entry-macro.S
@@ -0,0 +1,43 @@
+/*
+ * Low-level IRQ helper macros for Nomadik platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IO_ADDRESS(NOMADIK_IC_BASE)
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+        /* This stanza gets the irq mask from one of two status registers */
+        mov     \irqnr, #0
+        ldr     \irqstat, [\base, #VIC_REG_IRQSR0]      @ get masked status
+        cmp     \irqstat, #0
+        bne     1001f
+        add     \irqnr, \irqnr, #32
+        ldr     \irqstat, [\base, #VIC_REG_IRQSR1]      @ get masked status
+
+1001:   tst     \irqstat, #15
+        bne     1002f
+        add     \irqnr, \irqnr, #4
+        movs    \irqstat, \irqstat, lsr #4
+        bne     1001b
+1002:   tst     \irqstat, #1
+        bne     1003f
+        add     \irqnr, \irqnr, #1
+        movs    \irqstat, \irqstat, lsr #1
+        bne     1002b
+1003:   /* EQ will be set if no irqs pending */
+        .endm
diff --git a/arch/arm/mach-nomadik/include/mach/gpio.h b/arch/arm/mach-nomadik/include/mach/gpio.h
new file mode 100644
index 000000000000..61577c9f9a7d
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/gpio.h
@@ -0,0 +1,71 @@
+/*
+ * Structures and registers for GPIO access in the Nomadik SoC
+ *
+ * Copyright (C) 2008 STMicroelectronics
+ *     Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
+ * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#include <asm-generic/gpio.h>
+
+/*
+ * These currently cause a function call to happen, they may be optimized
+ * if needed by adding cpu-specific defines to identify blocks
+ * (see mach-pxa/include/mach/gpio.h as an example using GPLR etc)
+ */
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+
+/*
+ * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
+ * the "gpio" namespace for generic and cross-machine functions
+ */
+
+/* Register in the logic block */
+#define NMK_GPIO_DAT    0x00
+#define NMK_GPIO_DATS   0x04
+#define NMK_GPIO_DATC   0x08
+#define NMK_GPIO_PDIS   0x0c
+#define NMK_GPIO_DIR    0x10
+#define NMK_GPIO_DIRS   0x14
+#define NMK_GPIO_DIRC   0x18
+#define NMK_GPIO_SLPC   0x1c
+#define NMK_GPIO_AFSLA  0x20
+#define NMK_GPIO_AFSLB  0x24
+
+#define NMK_GPIO_RIMSC  0x40
+#define NMK_GPIO_FIMSC  0x44
+#define NMK_GPIO_IS     0x48
+#define NMK_GPIO_IC     0x4c
+#define NMK_GPIO_RWIMSC 0x50
+#define NMK_GPIO_FWIMSC 0x54
+#define NMK_GPIO_WKS    0x58
+
+/* Alternate functions: function C is set in hw by setting both A and B */
+#define NMK_GPIO_ALT_GPIO       0
+#define NMK_GPIO_ALT_A  1
+#define NMK_GPIO_ALT_B  2
+#define NMK_GPIO_ALT_C  (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
+
+extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
+extern int nmk_gpio_get_mode(int gpio);
+
+/*
+ * Platform data to register a block: only the initial gpio/irq number.
+ */
+struct nmk_gpio_platform_data {
+        char *name;
+        int first_gpio;
+        int first_irq;
+        int parent_irq;
+};
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-nomadik/include/mach/hardware.h b/arch/arm/mach-nomadik/include/mach/hardware.h
new file mode 100644
index 000000000000..6316dba3bfc8
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/hardware.h
@@ -0,0 +1,90 @@
+/*
+ * This file contains the hardware definitions of the Nomadik.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * YOU should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/* Nomadik registers live from 0x1000.0000 to 0x1023.0000 -- currently */
+#define NOMADIK_IO_VIRTUAL      0xF0000000      /* VA of IO  */
+#define NOMADIK_IO_PHYSICAL     0x10000000      /* PA of IO */
+#define NOMADIK_IO_SIZE         0x00300000      /* 3MB for all regs */
+
+/* used in C code, so cast to proper type */
+#define io_p2v(x) ((void __iomem *)(x) \
+                        - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
+#define io_v2p(x) ((unsigned long)(x) \
+                        - NOMADIK_IO_VIRTUAL + NOMADIK_IO_PHYSICAL)
+
+/* used in asm code, so no casts */
+#define IO_ADDRESS(x) ((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
+
+/*
+ *   Base address defination for Nomadik Onchip Logic Block
+ */
+#define NOMADIK_FSMC_BASE       0x10100000      /* FSMC registers */
+#define NOMADIK_SDRAMC_BASE     0x10110000      /* SDRAM Controller */
+#define NOMADIK_CLCDC_BASE      0x10120000      /* CLCD Controller */
+#define NOMADIK_MDIF_BASE       0x10120000      /* MDIF */
+#define NOMADIK_DMA0_BASE       0x10130000      /* DMA0 Controller */
+#define NOMADIK_IC_BASE         0x10140000      /* Vectored Irq Controller */
+#define NOMADIK_DMA1_BASE       0x10150000      /* DMA1 Controller */
+#define NOMADIK_USB_BASE        0x10170000      /* USB-OTG conf reg base */
+#define NOMADIK_CRYP_BASE       0x10180000      /* Crypto processor */
+#define NOMADIK_SHA1_BASE       0x10190000      /* SHA-1 Processor */
+#define NOMADIK_XTI_BASE        0x101A0000      /* XTI */
+#define NOMADIK_RNG_BASE        0x101B0000      /* Random number generator */
+#define NOMADIK_SRC_BASE        0x101E0000      /* SRC base */
+#define NOMADIK_WDOG_BASE       0x101E1000      /* Watchdog */
+#define NOMADIK_MTU0_BASE       0x101E2000      /* Multiple Timer 0 */
+#define NOMADIK_MTU1_BASE       0x101E3000      /* Multiple Timer 1 */
+#define NOMADIK_GPIO0_BASE      0x101E4000      /* GPIO0 */
+#define NOMADIK_GPIO1_BASE      0x101E5000      /* GPIO1 */
+#define NOMADIK_GPIO2_BASE      0x101E6000      /* GPIO2 */
+#define NOMADIK_GPIO3_BASE      0x101E7000      /* GPIO3 */
+#define NOMADIK_RTC_BASE        0x101E8000      /* Real Time Clock base */
+#define NOMADIK_PMU_BASE        0x101E9000      /* Power Management Unit */
+#define NOMADIK_OWM_BASE        0x101EA000      /* One wire master */
+#define NOMADIK_SCR_BASE        0x101EF000      /* Secure Control registers */
+#define NOMADIK_MSP2_BASE       0x101F0000      /* MSP 2 interface */
+#define NOMADIK_MSP1_BASE       0x101F1000      /* MSP 1 interface */
+#define NOMADIK_UART2_BASE      0x101F2000      /* UART 2 interface */
+#define NOMADIK_SSIRx_BASE      0x101F3000      /* SSI 8-ch rx interface */
+#define NOMADIK_SSITx_BASE      0x101F4000      /* SSI 8-ch tx interface */
+#define NOMADIK_MSHC_BASE       0x101F5000      /* Memory Stick(Pro) Host */
+#define NOMADIK_SDI_BASE        0x101F6000      /* SD-card/MM-Card */
+#define NOMADIK_I2C1_BASE       0x101F7000      /* I2C1 interface */
+#define NOMADIK_I2C0_BASE       0x101F8000      /* I2C0 interface */
+#define NOMADIK_MSP0_BASE       0x101F9000      /* MSP 0 interface  */
+#define NOMADIK_FIRDA_BASE      0x101FA000      /* FIrDA interface  */
+#define NOMADIK_UART1_BASE      0x101FB000      /* UART 1 interface */
+#define NOMADIK_SSP_BASE        0x101FC000      /* SSP interface  */
+#define NOMADIK_UART0_BASE      0x101FD000      /* UART 0 interface */
+#define NOMADIK_SGA_BASE        0x101FE000      /* SGA interface */
+#define NOMADIK_L2CC_BASE       0x10210000      /* L2 Cache controller */
+
+/* Other ranges, not for p2v/v2p */
+#define NOMADIK_BACKUP_RAM      0x80010000
+#define NOMADIK_EBROM           0x80000000      /* Embedded boot ROM */
+#define NOMADIK_HAMACV_DMEM_BASE 0xA0100000     /* HAMACV Data Memory Start */
+#define NOMADIK_HAMACV_DMEM_END 0xA01FFFFF      /* HAMACV Data Memory End */
+#define NOMADIK_HAMACA_DMEM     0xA0200000      /* HAMACA Data Memory Space */
+
+#define NOMADIK_FSMC_VA         IO_ADDRESS(NOMADIK_FSMC_BASE)
+#define NOMADIK_MTU0_VA         IO_ADDRESS(NOMADIK_MTU0_BASE)
+#define NOMADIK_MTU1_VA         IO_ADDRESS(NOMADIK_MTU1_BASE)
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-nomadik/include/mach/io.h b/arch/arm/mach-nomadik/include/mach/io.h
new file mode 100644
index 000000000000..2e1eca1b8243
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/io.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-nomadik/include/mach/io.h   (copied from mach-sa1100)
+ *
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Modifications:
+ *  06-12-1997  RMK     Created.
+ *  07-04-1999  RMK     Major cleanup
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+
+#endif
diff --git a/arch/arm/mach-nomadik/include/mach/irqs.h b/arch/arm/mach-nomadik/include/mach/irqs.h
new file mode 100644
index 000000000000..8faabc560398
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/irqs.h
@@ -0,0 +1,82 @@
+/*
+ *  mach-nomadik/include/mach/irqs.h
+ *
+ *  Copyright (C) ST Microelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include <mach/hardware.h>
+
+#define IRQ_VIC_START           0       /* first VIC interrupt is 0 */
+
+/*
+ * Interrupt numbers generic for all Nomadik Chip cuts
+ */
+#define IRQ_WATCHDOG                    0
+#define IRQ_SOFTINT                     1
+#define IRQ_CRYPTO                      2
+#define IRQ_OWM                         3
+#define IRQ_MTU0                        4
+#define IRQ_MTU1                        5
+#define IRQ_GPIO0                       6
+#define IRQ_GPIO1                       7
+#define IRQ_GPIO2                       8
+#define IRQ_GPIO3                       9
+#define IRQ_RTC_RTT                     10
+#define IRQ_SSP                         11
+#define IRQ_UART0                       12
+#define IRQ_DMA1                        13
+#define IRQ_CLCD_MDIF                   14
+#define IRQ_DMA0                        15
+#define IRQ_PWRFAIL                     16
+#define IRQ_UART1                       17
+#define IRQ_FIRDA                       18
+#define IRQ_MSP0                        19
+#define IRQ_I2C0                        20
+#define IRQ_I2C1                        21
+#define IRQ_SDMMC                       22
+#define IRQ_USBOTG                      23
+#define IRQ_SVA_IT0                     24
+#define IRQ_SVA_IT1                     25
+#define IRQ_SAA_IT0                     26
+#define IRQ_SAA_IT1                     27
+#define IRQ_UART2                       28
+#define IRQ_MSP2                        31
+#define IRQ_L2CC                        48
+#define IRQ_HPI                         49
+#define IRQ_SKE                         50
+#define IRQ_KP                          51
+#define IRQ_MEMST                       54
+#define IRQ_SGA_IT                      58
+#define IRQ_USBM                        60
+#define IRQ_MSP1                        62
+
+#define NOMADIK_SOC_NR_IRQS             64
+
+/* After chip-specific IRQ numbers we have the GPIO ones */
+#define NOMADIK_NR_GPIO                 128 /* last 4 not wired to pins */
+#define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + NOMADIK_SOC_NR_IRQS)
+#define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - NOMADIK_SOC_NR_IRQS)
+#define NR_IRQS                         NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
+
+/* Following two are used by entry_macro.S, to access our dual-vic */
+#define VIC_REG_IRQSR0          0
+#define VIC_REG_IRQSR1          0x20
+
+#endif /* __ASM_ARCH_IRQS_H */
+
diff --git a/arch/arm/mach-nomadik/include/mach/memory.h b/arch/arm/mach-nomadik/include/mach/memory.h
new file mode 100644
index 000000000000..1e5689d98ecd
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/memory.h
@@ -0,0 +1,28 @@
+/*
+ *  mach-nomadik/include/mach/memory.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x00000000)
+
+#endif
diff --git a/arch/arm/mach-nomadik/include/mach/mtu.h b/arch/arm/mach-nomadik/include/mach/mtu.h
new file mode 100644
index 000000000000..76da7f085330
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/mtu.h
@@ -0,0 +1,45 @@
+#ifndef __ASM_ARCH_MTU_H
+#define __ASM_ARCH_MTU_H
+
+/*
+ * The MTU device hosts four different counters, with 4 set of
+ * registers. These are register names.
+ */
+
+#define MTU_IMSC        0x00    /* Interrupt mask set/clear */
+#define MTU_RIS         0x04    /* Raw interrupt status */
+#define MTU_MIS         0x08    /* Masked interrupt status */
+#define MTU_ICR         0x0C    /* Interrupt clear register */
+
+/* per-timer registers take 0..3 as argument */
+#define MTU_LR(x)       (0x10 + 0x10 * (x) + 0x00)      /* Load value */
+#define MTU_VAL(x)      (0x10 + 0x10 * (x) + 0x04)      /* Current value */
+#define MTU_CR(x)       (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
+#define MTU_BGLR(x)     (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
+
+/* bits for the control register */
+#define MTU_CRn_ENA             0x80
+#define MTU_CRn_PERIODIC        0x40    /* if 0 = free-running */
+#define MTU_CRn_PRESCALE_MASK   0x0c
+#define MTU_CRn_PRESCALE_1              0x00
+#define MTU_CRn_PRESCALE_16             0x04
+#define MTU_CRn_PRESCALE_256            0x08
+#define MTU_CRn_32BITS          0x02
+#define MTU_CRn_ONESHOT         0x01    /* if 0 = wraps reloading from BGLR*/
+
+/* Other registers are usual amba/primecell registers, currently not used */
+#define MTU_ITCR        0xff0
+#define MTU_ITOP        0xff4
+
+#define MTU_PERIPH_ID0  0xfe0
+#define MTU_PERIPH_ID1  0xfe4
+#define MTU_PERIPH_ID2  0xfe8
+#define MTU_PERIPH_ID3  0xfeC
+
+#define MTU_PCELL0      0xff0
+#define MTU_PCELL1      0xff4
+#define MTU_PCELL2      0xff8
+#define MTU_PCELL3      0xffC
+
+#endif /* __ASM_ARCH_MTU_H */
+
diff --git a/arch/arm/mach-nomadik/include/mach/setup.h b/arch/arm/mach-nomadik/include/mach/setup.h
new file mode 100644
index 000000000000..a4e468cf63da
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/setup.h
@@ -0,0 +1,22 @@
+
+/*
+ * These symbols are needed for board-specific files to call their
+ * own cpu-specific files
+ */
+
+#ifndef __ASM_ARCH_SETUP_H
+#define __ASM_ARCH_SETUP_H
+
+#include <asm/mach/time.h>
+#include <linux/init.h>
+
+#ifdef CONFIG_NOMADIK_8815
+
+extern void cpu8815_map_io(void);
+extern void cpu8815_platform_init(void);
+extern void cpu8815_init_irq(void);
+extern struct sys_timer nomadik_timer;
+
+#endif /* NOMADIK_8815 */
+
+#endif /*  __ASM_ARCH_SETUP_H */
diff --git a/arch/arm/mach-nomadik/include/mach/system.h b/arch/arm/mach-nomadik/include/mach/system.h
new file mode 100644
index 000000000000..7119f688116e
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/system.h
@@ -0,0 +1,45 @@
+/*
+ *  mach-nomadik/include/mach/system.h
+ *
+ *  Copyright (C) 2008 STMicroelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <linux/io.h>
+#include <mach/hardware.h>
+
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+        void __iomem *src_rstsr = io_p2v(NOMADIK_SRC_BASE + 0x18);
+
+        /* FIXME: use egpio when implemented */
+
+        /* Write anything to Reset status register */
+        writel(1, src_rstsr);
+}
+
+#endif
diff --git a/arch/arm/mach-nomadik/include/mach/timex.h b/arch/arm/mach-nomadik/include/mach/timex.h
new file mode 100644
index 000000000000..318b8896ce96
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/timex.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+#define CLOCK_TICK_RATE         2400000
+
+#endif
diff --git a/arch/arm/mach-nomadik/include/mach/uncompress.h b/arch/arm/mach-nomadik/include/mach/uncompress.h
new file mode 100644
index 000000000000..071003bc8456
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/uncompress.h
@@ -0,0 +1,63 @@
+/*
+ *  Copyright (C) 2008 STMicroelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <asm/setup.h>
+#include <asm/io.h>
+#include <mach/hardware.h>
+
+/* we need the constants in amba/serial.h, but it refers to amba_device */
+struct amba_device;
+#include <linux/amba/serial.h>
+
+#define NOMADIK_UART_DR         0x101FB000
+#define NOMADIK_UART_LCRH       0x101FB02c
+#define NOMADIK_UART_CR         0x101FB030
+#define NOMADIK_UART_FR         0x101FB018
+
+static void putc(const char c)
+{
+        /* Do nothing if the UART is not enabled. */
+        if (!(readb(NOMADIK_UART_CR) & UART01x_CR_UARTEN))
+                return;
+
+        if (c == '\n')
+                putc('\r');
+
+        while (readb(NOMADIK_UART_FR) & UART01x_FR_TXFF)
+                barrier();
+        writeb(c, NOMADIK_UART_DR);
+}
+
+static void flush(void)
+{
+        if (!(readb(NOMADIK_UART_CR) & UART01x_CR_UARTEN))
+                return;
+        while (readb(NOMADIK_UART_FR) & UART01x_FR_BUSY)
+                barrier();
+}
+
+static inline void arch_decomp_setup(void)
+{
+}
+
+#define arch_decomp_wdog() /* nothing to do here */
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-nomadik/include/mach/vmalloc.h b/arch/arm/mach-nomadik/include/mach/vmalloc.h
new file mode 100644
index 000000000000..be12e31ea528
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/vmalloc.h
@@ -0,0 +1,2 @@
+
+#define VMALLOC_END       0xe8000000
diff --git a/arch/arm/mach-nomadik/timer.c b/arch/arm/mach-nomadik/timer.c
new file mode 100644
index 000000000000..d1738e7061d4
--- /dev/null
+++ b/arch/arm/mach-nomadik/timer.c
@@ -0,0 +1,164 @@
+/*
+ *  linux/arch/arm/mach-nomadik/timer.c
+ *
+ * Copyright (C) 2008 STMicroelectronics
+ * Copyright (C) 2009 Alessandro Rubini, somewhat based on at91sam926x
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/clockchips.h>
+#include <linux/jiffies.h>
+#include <asm/mach/time.h>
+#include <mach/mtu.h>
+
+#define TIMER_CTRL      0x80    /* No divisor */
+#define TIMER_PERIODIC  0x40
+#define TIMER_SZ32BIT   0x02
+
+/* Initial value for SRC control register: all timers use MXTAL/8 source */
+#define SRC_CR_INIT_MASK        0x00007fff
+#define SRC_CR_INIT_VAL         0x2aaa8000
+
+static u32      nmdk_count;             /* accumulated count */
+static u32      nmdk_cycle;             /* write-once */
+static __iomem void *mtu_base;
+
+/*
+ * clocksource: the MTU device is a decrementing counters, so we negate
+ * the value being read.
+ */
+static cycle_t nmdk_read_timer(struct clocksource *cs)
+{
+        u32 count = readl(mtu_base + MTU_VAL(0));
+        return nmdk_count + nmdk_cycle - count;
+
+}
+
+static struct clocksource nmdk_clksrc = {
+        .name           = "mtu_0",
+        .rating         = 120,
+        .read           = nmdk_read_timer,
+        .shift          = 20,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+/*
+ * Clockevent device: currently only periodic mode is supported
+ */
+static void nmdk_clkevt_mode(enum clock_event_mode mode,
+                             struct clock_event_device *dev)
+{
+        unsigned long flags;
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                /* enable interrupts -- and count current value? */
+                raw_local_irq_save(flags);
+                writel(readl(mtu_base + MTU_IMSC) | 1, mtu_base + MTU_IMSC);
+                raw_local_irq_restore(flags);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                BUG(); /* Not supported, yet */
+                /* FALLTHROUGH */
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+                /* disable irq */
+                raw_local_irq_save(flags);
+                writel(readl(mtu_base + MTU_IMSC) & ~1, mtu_base + MTU_IMSC);
+                raw_local_irq_restore(flags);
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static struct clock_event_device nmdk_clkevt = {
+        .name           = "mtu_0",
+        .features       = CLOCK_EVT_FEAT_PERIODIC,
+        .shift          = 32,
+        .rating         = 100,
+        .set_mode       = nmdk_clkevt_mode,
+};
+
+/*
+ * IRQ Handler for the timer 0 of the MTU block. The irq is not shared
+ * as we are the only users of mtu0 by now.
+ */
+static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
+{
+        /* ack: "interrupt clear register" */
+        writel( 1 << 0, mtu_base + MTU_ICR);
+
+        /* we can't count lost ticks, unfortunately */
+        nmdk_count += nmdk_cycle;
+        nmdk_clkevt.event_handler(&nmdk_clkevt);
+
+        return IRQ_HANDLED;
+}
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+static struct irqaction nmdk_timer_irq = {
+        .name           = "Nomadik Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .handler        = nmdk_timer_interrupt,
+};
+
+static void nmdk_timer_reset(void)
+{
+        u32 cr;
+
+        writel(0, mtu_base + MTU_CR(0)); /* off */
+
+        /* configure load and background-load, and fire it up */
+        writel(nmdk_cycle, mtu_base + MTU_LR(0));
+        writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
+        cr = MTU_CRn_PERIODIC | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS;
+        writel(cr, mtu_base + MTU_CR(0));
+        writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
+}
+
+static void __init nmdk_timer_init(void)
+{
+        u32 src_cr;
+        unsigned long rate;
+        int bits;
+
+        rate = CLOCK_TICK_RATE; /* 2.4MHz */
+        nmdk_cycle = (rate + HZ/2) / HZ;
+
+        /* Configure timer sources in "system reset controller" ctrl reg */
+        src_cr = readl(io_p2v(NOMADIK_SRC_BASE));
+        src_cr &= SRC_CR_INIT_MASK;
+        src_cr |= SRC_CR_INIT_VAL;
+        writel(src_cr, io_p2v(NOMADIK_SRC_BASE));
+
+        /* Save global pointer to mtu, used by functions above */
+        mtu_base = io_p2v(NOMADIK_MTU0_BASE);
+
+        /* Init the timer and register clocksource */
+        nmdk_timer_reset();
+
+        nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
+        bits =  8*sizeof(nmdk_count);
+        nmdk_clksrc.mask = CLOCKSOURCE_MASK(bits);
+
+        clocksource_register(&nmdk_clksrc);
+
+        /* Register irq and clockevents */
+        setup_irq(IRQ_MTU0, &nmdk_timer_irq);
+        nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift);
+        nmdk_clkevt.cpumask = cpumask_of(0);
+        clockevents_register_device(&nmdk_clkevt);
+}
+
+struct sys_timer nomadik_timer = {
+        .init           = nmdk_timer_init,
+};
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 8b40aace9db4..42920f9c1a11 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -15,8 +15,11 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/input.h>
+#include <linux/interrupt.h>
 #include <linux/platform_device.h>
+#include <linux/serial_8250.h>
 
+#include <asm/serial.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -162,10 +165,6 @@ static struct omap_lcd_config ams_delta_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_uart_config ams_delta_uart_config __initdata = {
-        .enabled_uarts = 1,
-};
-
 static struct omap_usb_config ams_delta_usb_config __initdata = {
         .register_host  = 1,
         .hmc_mode       = 16,
@@ -174,7 +173,6 @@ static struct omap_usb_config ams_delta_usb_config __initdata = {
 
 static struct omap_board_config_kernel ams_delta_config[] = {
         { OMAP_TAG_LCD,         &ams_delta_lcd_config },
-        { OMAP_TAG_UART,        &ams_delta_uart_config },
 };
 
 static struct resource ams_delta_kp_resources[] = {
@@ -235,6 +233,41 @@ static void __init ams_delta_init(void)
         platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
 }
 
+static struct plat_serial8250_port ams_delta_modem_ports[] = {
+        {
+                .membase        = (void *) AMS_DELTA_MODEM_VIRT,
+                .mapbase        = AMS_DELTA_MODEM_PHYS,
+                .irq            = -EINVAL, /* changed later */
+                .flags          = UPF_BOOT_AUTOCONF,
+                .irqflags       = IRQF_TRIGGER_RISING,
+                .iotype         = UPIO_MEM,
+                .regshift       = 1,
+                .uartclk        = BASE_BAUD * 16,
+        },
+        { },
+};
+
+static struct platform_device ams_delta_modem_device = {
+        .name   = "serial8250",
+        .id     = PLAT8250_DEV_PLATFORM1,
+        .dev            = {
+                .platform_data = ams_delta_modem_ports,
+        },
+};
+
+static int __init ams_delta_modem_init(void)
+{
+        omap_cfg_reg(M14_1510_GPIO2);
+        ams_delta_modem_ports[0].irq = gpio_to_irq(2);
+
+        ams_delta_latch2_write(
+                AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC,
+                AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC);
+
+        return platform_device_register(&ams_delta_modem_device);
+}
+arch_initcall(ams_delta_modem_init);
+
 static void __init ams_delta_map_io(void)
 {
         omap1_map_common_io();
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 19e0e9232336..a7ead1b93226 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -240,16 +240,11 @@ static int nand_dev_ready(struct omap_nand_platform_data *data)
         return gpio_get_value(P2_NAND_RB_GPIO_PIN);
 }
 
-static struct omap_uart_config fsample_uart_config __initdata = {
-        .enabled_uarts = ((1 << 0) | (1 << 1)),
-};
-
 static struct omap_lcd_config fsample_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
 static struct omap_board_config_kernel fsample_config[] = {
-        { OMAP_TAG_UART,        &fsample_uart_config },
         { OMAP_TAG_LCD,         &fsample_lcd_config },
 };
 
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index e724940e86f2..fb47239da72f 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -57,12 +57,7 @@ static struct omap_usb_config generic1610_usb_config __initdata = {
 };
 #endif
 
-static struct omap_uart_config generic_uart_config __initdata = {
-        .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
-
 static struct omap_board_config_kernel generic_config[] __initdata = {
-        { OMAP_TAG_UART,        &generic_uart_config },
 };
 
 static void __init omap_generic_init(void)
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index f695aa053ac8..aab860307dca 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -360,16 +360,11 @@ static struct omap_usb_config h2_usb_config __initdata = {
         .pins[1]        = 3,
 };
 
-static struct omap_uart_config h2_uart_config __initdata = {
-        .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
-
 static struct omap_lcd_config h2_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
 static struct omap_board_config_kernel h2_config[] __initdata = {
-        { OMAP_TAG_UART,        &h2_uart_config },
         { OMAP_TAG_LCD,         &h2_lcd_config },
 };
 
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index f597968733b4..89586b80b8d5 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -313,16 +313,11 @@ static struct omap_usb_config h3_usb_config __initdata = {
         .pins[1]        = 3,
 };
 
-static struct omap_uart_config h3_uart_config __initdata = {
-        .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
-
 static struct omap_lcd_config h3_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
 static struct omap_board_config_kernel h3_config[] __initdata = {
-        { OMAP_TAG_UART,        &h3_uart_config },
         { OMAP_TAG_LCD,         &h3_lcd_config },
 };
 
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 2fd98260ea49..cc2abbb2d0f4 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -368,13 +368,8 @@ static inline void innovator_mmc_init(void)
 }
 #endif
 
-static struct omap_uart_config innovator_uart_config __initdata = {
-        .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
-
 static struct omap_board_config_kernel innovator_config[] = {
         { OMAP_TAG_LCD,         NULL },
-        { OMAP_TAG_UART,        &innovator_uart_config },
 };
 
 static void __init innovator_init(void)
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index cf3247b15f87..ed891b8a6b15 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -293,10 +293,6 @@ static struct omap_usb_config osk_usb_config __initdata = {
         .pins[0]        = 2,
 };
 
-static struct omap_uart_config osk_uart_config __initdata = {
-        .enabled_uarts = (1 << 0),
-};
-
 #ifdef  CONFIG_OMAP_OSK_MISTRAL
 static struct omap_lcd_config osk_lcd_config __initdata = {
         .ctrl_name      = "internal",
@@ -304,7 +300,6 @@ static struct omap_lcd_config osk_lcd_config __initdata = {
 #endif
 
 static struct omap_board_config_kernel osk_config[] __initdata = {
-        { OMAP_TAG_UART,                &osk_uart_config },
 #ifdef  CONFIG_OMAP_OSK_MISTRAL
         { OMAP_TAG_LCD,                 &osk_lcd_config },
 #endif
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 886b4c0569bd..90dd0431b0dc 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -212,10 +212,6 @@ static struct omap_lcd_config palmte_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_uart_config palmte_uart_config __initdata = {
-        .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2),
-};
-
 #ifdef CONFIG_APM
 /*
  * Values measured in 10 minute intervals averaged over 10 samples.
@@ -302,7 +298,6 @@ static void palmte_get_power_status(struct apm_power_info *info, int *battery)
 
 static struct omap_board_config_kernel palmte_config[] __initdata = {
         { OMAP_TAG_LCD,         &palmte_lcd_config },
-        { OMAP_TAG_UART,        &palmte_uart_config },
 };
 
 static struct spi_board_info palmte_spi_info[] __initdata = {
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 4f1b44831d37..8256139891ff 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -274,13 +274,8 @@ static struct omap_lcd_config palmtt_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_uart_config palmtt_uart_config __initdata = {
-        .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2),
-};
-
 static struct omap_board_config_kernel palmtt_config[] __initdata = {
         { OMAP_TAG_LCD,         &palmtt_lcd_config      },
-        { OMAP_TAG_UART,        &palmtt_uart_config     },
 };
 
 static void __init omap_mpu_wdt_mode(int mode) {
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 9a55c3c58218..81b6bde1c5a3 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -244,13 +244,8 @@ static struct omap_lcd_config palmz71_lcd_config __initdata = {
         .ctrl_name = "internal",
 };
 
-static struct omap_uart_config palmz71_uart_config __initdata = {
-        .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2),
-};
-
 static struct omap_board_config_kernel palmz71_config[] __initdata = {
         {OMAP_TAG_LCD,  &palmz71_lcd_config},
-        {OMAP_TAG_UART, &palmz71_uart_config},
 };
 
 static irqreturn_t
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 3b9f907aa899..83406699f310 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -208,16 +208,11 @@ static int nand_dev_ready(struct omap_nand_platform_data *data)
         return gpio_get_value(P2_NAND_RB_GPIO_PIN);
 }
 
-static struct omap_uart_config perseus2_uart_config __initdata = {
-        .enabled_uarts = ((1 << 0) | (1 << 1)),
-};
-
 static struct omap_lcd_config perseus2_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
 static struct omap_board_config_kernel perseus2_config[] __initdata = {
-        { OMAP_TAG_UART,        &perseus2_uart_config },
         { OMAP_TAG_LCD,         &perseus2_lcd_config },
 };
 
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index c096577695fe..02c85ca2e1df 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -369,13 +369,8 @@ static struct platform_device *sx1_devices[] __initdata = {
 };
 /*-----------------------------------------*/
 
-static struct omap_uart_config sx1_uart_config __initdata = {
-        .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
-
 static struct omap_board_config_kernel sx1_config[] __initdata = {
         { OMAP_TAG_LCD, &sx1_lcd_config },
-        { OMAP_TAG_UART,        &sx1_uart_config },
 };
 
 /*-----------------------------------------*/
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 98275e03dad1..c06e7a553472 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -140,12 +140,7 @@ static struct omap_usb_config voiceblue_usb_config __initdata = {
         .pins[2]        = 6,
 };
 
-static struct omap_uart_config voiceblue_uart_config __initdata = {
-        .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
-
 static struct omap_board_config_kernel voiceblue_config[] = {
-        { OMAP_TAG_UART, &voiceblue_uart_config },
 };
 
 static void __init voiceblue_init_irq(void)
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index bbbaeb0abcd3..06808434ea04 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -71,7 +71,7 @@ static inline void omap_init_rtc(void) {}
 #  define INT_DSP_MAILBOX1      INT_1610_DSP_MAILBOX1
 #endif
 
-#define OMAP1_MBOX_BASE         IO_ADDRESS(OMAP16XX_MAILBOX_BASE)
+#define OMAP1_MBOX_BASE         OMAP1_IO_ADDRESS(OMAP16XX_MAILBOX_BASE)
 
 static struct resource mbox_resources[] = {
         {
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 3afe540149f7..7030f9281ea1 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -29,9 +29,9 @@ extern void omapfb_reserve_sdram(void);
  */
 static struct map_desc omap_io_desc[] __initdata = {
         {
-                .virtual        = IO_VIRT,
-                .pfn            = __phys_to_pfn(IO_PHYS),
-                .length         = IO_SIZE,
+                .virtual        = OMAP1_IO_VIRT,
+                .pfn            = __phys_to_pfn(OMAP1_IO_PHYS),
+                .length         = OMAP1_IO_SIZE,
                 .type           = MT_DEVICE
         }
 };
diff --git a/arch/arm/mach-omap1/pm.h b/arch/arm/mach-omap1/pm.h
index 9ed5e2c1de4d..c4f05bdcf8a6 100644
--- a/arch/arm/mach-omap1/pm.h
+++ b/arch/arm/mach-omap1/pm.h
@@ -39,11 +39,11 @@
  * Register and offset definitions to be used in PM assembler code
  * ----------------------------------------------------------------------------
  */
-#define CLKGEN_REG_ASM_BASE             IO_ADDRESS(0xfffece00)
+#define CLKGEN_REG_ASM_BASE             OMAP1_IO_ADDRESS(0xfffece00)
 #define ARM_IDLECT1_ASM_OFFSET          0x04
 #define ARM_IDLECT2_ASM_OFFSET          0x08
 
-#define TCMIF_ASM_BASE                  IO_ADDRESS(0xfffecc00)
+#define TCMIF_ASM_BASE                  OMAP1_IO_ADDRESS(0xfffecc00)
 #define EMIFS_CONFIG_ASM_OFFSET         0x0c
 #define EMIFF_SDRAM_CONFIG_ASM_OFFSET   0x20
 
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index f754cee4f3c3..d496e50fec40 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -64,7 +64,7 @@ static void __init omap_serial_reset(struct plat_serial8250_port *p)
 
 static struct plat_serial8250_port serial_platform_data[] = {
         {
-                .membase        = IO_ADDRESS(OMAP_UART1_BASE),
+                .membase        = OMAP1_IO_ADDRESS(OMAP_UART1_BASE),
                 .mapbase        = OMAP_UART1_BASE,
                 .irq            = INT_UART1,
                 .flags          = UPF_BOOT_AUTOCONF,
@@ -73,7 +73,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
         },
         {
-                .membase        = IO_ADDRESS(OMAP_UART2_BASE),
+                .membase        = OMAP1_IO_ADDRESS(OMAP_UART2_BASE),
                 .mapbase        = OMAP_UART2_BASE,
                 .irq            = INT_UART2,
                 .flags          = UPF_BOOT_AUTOCONF,
@@ -82,7 +82,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
         },
         {
-                .membase        = IO_ADDRESS(OMAP_UART3_BASE),
+                .membase        = OMAP1_IO_ADDRESS(OMAP_UART3_BASE),
                 .mapbase        = OMAP_UART3_BASE,
                 .irq            = INT_UART3,
                 .flags          = UPF_BOOT_AUTOCONF,
@@ -109,7 +109,6 @@ static struct platform_device serial_device = {
 void __init omap_serial_init(void)
 {
         int i;
-        const struct omap_uart_config *info;
 
         if (cpu_is_omap730()) {
                 serial_platform_data[0].regshift = 0;
@@ -131,19 +130,9 @@ void __init omap_serial_init(void)
                 serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
         }
 
-        info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
-        if (info == NULL)
-                return;
-
         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
                 unsigned char reg;
 
-                if (!((1 << i) & info->enabled_uarts)) {
-                        serial_platform_data[i].membase = NULL;
-                        serial_platform_data[i].mapbase = 0;
-                        continue;
-                }
-
                 switch (i) {
                 case 0:
                         uart1_ck = clk_get(NULL, "uart1_ck");
diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S
index 261cdc48228b..7724e520d07c 100644
--- a/arch/arm/mach-omap1/sram.S
+++ b/arch/arm/mach-omap1/sram.S
@@ -21,13 +21,13 @@
 ENTRY(omap1_sram_reprogram_clock)
         stmfd   sp!, {r0 - r12, lr}             @ save registers on stack
 
-        mov     r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000
-        orr     r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x00ff0000
-        orr     r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x0000ff00
+        mov     r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
+        orr     r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
+        orr     r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
 
-        mov     r3, #IO_ADDRESS(ARM_CKCTL) & 0xff000000
-        orr     r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
-        orr     r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
+        mov     r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
+        orr     r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
+        orr     r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
 
         tst     r0, #1 << 4                     @ want lock mode?
         beq     newck                           @ nope
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 4d56408d3cff..1be6a214d88d 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -62,8 +62,8 @@ typedef struct {
         u32 read_tim;                   /* READ_TIM,   R */
 } omap_mpu_timer_regs_t;
 
-#define omap_mpu_timer_base(n)                                          \
-((volatile omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE +      \
+#define omap_mpu_timer_base(n)                                                  \
+((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE +        \
                                  (n)*OMAP_MPU_TIMER_OFFSET))
 
 static inline unsigned long omap_mpu_timer_read(int nr)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index a755eb5e2361..75b1c7efae7e 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -31,6 +31,11 @@ config MACH_OMAP_GENERIC
         bool "Generic OMAP board"
         depends on ARCH_OMAP2 && ARCH_OMAP24XX
 
+config MACH_OMAP2_TUSB6010
+        bool
+        depends on ARCH_OMAP2 && ARCH_OMAP2420
+        default y if MACH_NOKIA_N8X0
+
 config MACH_OMAP_H4
         bool "OMAP 2420 H4 board"
         depends on ARCH_OMAP2 && ARCH_OMAP24XX
@@ -68,6 +73,10 @@ config MACH_OMAP_3430SDP
         bool "OMAP 3430 SDP board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
 
+config MACH_NOKIA_N8X0
+        bool "Nokia N800/N810"
+        depends on ARCH_OMAP2420
+
 config MACH_NOKIA_RX51
         bool "Nokia RX-51 board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 735bae5b0dec..8cb16777661a 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -5,7 +5,7 @@
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
 
-omap-2-3-common                         = irq.o sdrc.o
+omap-2-3-common                         = irq.o sdrc.o omap_hwmod.o
 prcm-common                             = prcm.o powerdomain.o
 clock-common                            = clock.o clockdomain.o
 
@@ -35,6 +35,11 @@ obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 endif
 
+# PRCM
+obj-$(CONFIG_ARCH_OMAP2)                += cm.o
+obj-$(CONFIG_ARCH_OMAP3)                += cm.o
+obj-$(CONFIG_ARCH_OMAP4)                += cm4xxx.o
+
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)                += clock24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o
@@ -62,7 +67,7 @@ obj-$(CONFIG_MACH_OMAP3_PANDORA)	+= board-omap3pandora.o \
                                            mmc-twl4030.o
 obj-$(CONFIG_MACH_OMAP_3430SDP)         += board-3430sdp.o \
                                            mmc-twl4030.o
-
+obj-$(CONFIG_MACH_NOKIA_N8X0)           += board-n8x0.o
 obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51.o \
                                            board-rx51-peripherals.o \
                                            mmc-twl4030.o
@@ -74,6 +79,7 @@ obj-$(CONFIG_MACH_OMAP_4430SDP)		+= board-4430sdp.o
 
 # Platform specific device init code
 obj-y                                   += usb-musb.o
+obj-$(CONFIG_MACH_OMAP2_TUSB6010)       += usb-tusb6010.o
 
 onenand-$(CONFIG_MTD_ONENAND_OMAP2)     := gpmc-onenand.o
 obj-y                                   += $(onenand-m) $(onenand-y)
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 8ec2a132904d..42217b32f835 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -139,23 +139,19 @@ static inline void board_smc91x_init(void)
 
 #endif
 
+static struct omap_board_config_kernel sdp2430_config[] = {
+        {OMAP_TAG_LCD, &sdp2430_lcd_config},
+};
+
 static void __init omap_2430sdp_init_irq(void)
 {
+        omap_board_config = sdp2430_config;
+        omap_board_config_size = ARRAY_SIZE(sdp2430_config);
         omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
 }
 
-static struct omap_uart_config sdp2430_uart_config __initdata = {
-        .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
-
-static struct omap_board_config_kernel sdp2430_config[] = {
-        {OMAP_TAG_UART, &sdp2430_uart_config},
-        {OMAP_TAG_LCD, &sdp2430_lcd_config},
-};
-
-
 static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
         .gpio_base      = OMAP_MAX_GPIO_LINES,
         .irq_base       = TWL4030_GPIO_IRQ_BASE,
@@ -205,8 +201,6 @@ static void __init omap_2430sdp_init(void)
         omap2430_i2c_init();
 
         platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
-        omap_board_config = sdp2430_config;
-        omap_board_config_size = ARRAY_SIZE(sdp2430_config);
         omap_serial_init();
         twl4030_mmc_init(mmc);
         usb_musb_init();
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index ac262cd74503..bd57ec76dc5e 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -167,26 +167,23 @@ static struct platform_device *sdp3430_devices[] __initdata = {
         &sdp3430_lcd_device,
 };
 
-static void __init omap_3430sdp_init_irq(void)
-{
-        omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
-        omap_init_irq();
-        omap_gpio_init();
-}
-
-static struct omap_uart_config sdp3430_uart_config __initdata = {
-        .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
-
 static struct omap_lcd_config sdp3430_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
 static struct omap_board_config_kernel sdp3430_config[] __initdata = {
-        { OMAP_TAG_UART,        &sdp3430_uart_config },
         { OMAP_TAG_LCD,         &sdp3430_lcd_config },
 };
 
+static void __init omap_3430sdp_init_irq(void)
+{
+        omap_board_config = sdp3430_config;
+        omap_board_config_size = ARRAY_SIZE(sdp3430_config);
+        omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
+        omap_init_irq();
+        omap_gpio_init();
+}
+
 static int sdp3430_batt_table[] = {
 /* 0 C*/
 30800, 29500, 28300, 27100,
@@ -478,12 +475,15 @@ static inline void board_smc91x_init(void)
 
 #endif
 
+static void enable_board_wakeup_source(void)
+{
+        omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
+}
+
 static void __init omap_3430sdp_init(void)
 {
         omap3430_i2c_init();
         platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
-        omap_board_config = sdp3430_config;
-        omap_board_config_size = ARRAY_SIZE(sdp3430_config);
         if (omap_rev() > OMAP3430_REV_ES1_0)
                 ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2;
         else
@@ -495,6 +495,7 @@ static void __init omap_3430sdp_init(void)
         omap_serial_init();
         usb_musb_init();
         board_smc91x_init();
+        enable_board_wakeup_source();
 }
 
 static void __init omap_3430sdp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index b0c7402248f7..eb37c40ea83a 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -39,7 +39,7 @@ static struct platform_device *sdp4430_devices[] __initdata = {
 };
 
 static struct omap_uart_config sdp4430_uart_config __initdata = {
-        .enabled_uarts  = (1 << 0) | (1 << 1) | (1 << 2),
+        .enabled_uarts  = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3),
 };
 
 static struct omap_lcd_config sdp4430_lcd_config __initdata = {
@@ -47,14 +47,13 @@ static struct omap_lcd_config sdp4430_lcd_config __initdata = {
 };
 
 static struct omap_board_config_kernel sdp4430_config[] __initdata = {
-        { OMAP_TAG_UART,        &sdp4430_uart_config },
         { OMAP_TAG_LCD,         &sdp4430_lcd_config },
 };
 
 static void __init gic_init_irq(void)
 {
-        gic_dist_init(0, IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29);
-        gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
+        gic_dist_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29);
+        gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
 }
 
 static void __init omap_4430sdp_init_irq(void)
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index b4d4ef6d90b9..a1132288c701 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -248,18 +248,6 @@ out:
         clk_put(gpmc_fck);
 }
 
-static void __init omap_apollon_init_irq(void)
-{
-        omap2_init_common_hw(NULL, NULL);
-        omap_init_irq();
-        omap_gpio_init();
-        apollon_init_smc91x();
-}
-
-static struct omap_uart_config apollon_uart_config __initdata = {
-        .enabled_uarts = (1 << 0) | (0 << 1) | (0 << 2),
-};
-
 static struct omap_usb_config apollon_usb_config __initdata = {
         .register_dev   = 1,
         .hmc_mode       = 0x14, /* 0:dev 1:host1 2:disable */
@@ -272,10 +260,19 @@ static struct omap_lcd_config apollon_lcd_config __initdata = {
 };
 
 static struct omap_board_config_kernel apollon_config[] = {
-        { OMAP_TAG_UART,        &apollon_uart_config },
         { OMAP_TAG_LCD,         &apollon_lcd_config },
 };
 
+static void __init omap_apollon_init_irq(void)
+{
+        omap_board_config = apollon_config;
+        omap_board_config_size = ARRAY_SIZE(apollon_config);
+        omap2_init_common_hw(NULL, NULL);
+        omap_init_irq();
+        omap_gpio_init();
+        apollon_init_smc91x();
+}
+
 static void __init apollon_led_init(void)
 {
         /* LED0 - AA10 */
@@ -324,8 +321,6 @@ static void __init omap_apollon_init(void)
          * if not needed.
          */
         platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
-        omap_board_config = apollon_config;
-        omap_board_config_size = ARRAY_SIZE(apollon_config);
         omap_serial_init();
 }
 
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index fd00aa03690c..2e09a1c444cb 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -31,24 +31,19 @@
 #include <mach/board.h>
 #include <mach/common.h>
 
+static struct omap_board_config_kernel generic_config[] = {
+};
+
 static void __init omap_generic_init_irq(void)
 {
+        omap_board_config = generic_config;
+        omap_board_config_size = ARRAY_SIZE(generic_config);
         omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
 }
 
-static struct omap_uart_config generic_uart_config __initdata = {
-        .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
-
-static struct omap_board_config_kernel generic_config[] = {
-        { OMAP_TAG_UART,        &generic_uart_config },
-};
-
 static void __init omap_generic_init(void)
 {
-        omap_board_config = generic_config;
-        omap_board_config_size = ARRAY_SIZE(generic_config);
         omap_serial_init();
 }
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 7b1d61d5bb2c..eaa02d012c5c 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -268,18 +268,6 @@ static void __init h4_init_flash(void)
         h4_flash_resource.end   = base + SZ_64M - 1;
 }
 
-static void __init omap_h4_init_irq(void)
-{
-        omap2_init_common_hw(NULL, NULL);
-        omap_init_irq();
-        omap_gpio_init();
-        h4_init_flash();
-}
-
-static struct omap_uart_config h4_uart_config __initdata = {
-        .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
-
 static struct omap_lcd_config h4_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
@@ -318,10 +306,19 @@ static struct omap_usb_config h4_usb_config __initdata = {
 };
 
 static struct omap_board_config_kernel h4_config[] = {
-        { OMAP_TAG_UART,        &h4_uart_config },
         { OMAP_TAG_LCD,         &h4_lcd_config },
 };
 
+static void __init omap_h4_init_irq(void)
+{
+        omap_board_config = h4_config;
+        omap_board_config_size = ARRAY_SIZE(h4_config);
+        omap2_init_common_hw(NULL, NULL);
+        omap_init_irq();
+        omap_gpio_init();
+        h4_init_flash();
+}
+
 static struct at24_platform_data m24c01 = {
         .byte_len       = SZ_1K / 8,
         .page_size      = 16,
@@ -366,8 +363,6 @@ static void __init omap_h4_init(void)
                         ARRAY_SIZE(h4_i2c_board_info));
 
         platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
-        omap_board_config = h4_config;
-        omap_board_config_size = ARRAY_SIZE(h4_config);
         omap_usb_init(&h4_usb_config);
         omap_serial_init();
 }
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index ea383f88cb1b..ec6854cbdd9f 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -268,18 +268,6 @@ static inline void __init ldp_init_smsc911x(void)
         gpio_direction_input(eth_gpio);
 }
 
-static void __init omap_ldp_init_irq(void)
-{
-        omap2_init_common_hw(NULL, NULL);
-        omap_init_irq();
-        omap_gpio_init();
-        ldp_init_smsc911x();
-}
-
-static struct omap_uart_config ldp_uart_config __initdata = {
-        .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
-
 static struct platform_device ldp_lcd_device = {
         .name           = "ldp_lcd",
         .id             = -1,
@@ -290,10 +278,19 @@ static struct omap_lcd_config ldp_lcd_config __initdata = {
 };
 
 static struct omap_board_config_kernel ldp_config[] __initdata = {
-        { OMAP_TAG_UART,        &ldp_uart_config },
         { OMAP_TAG_LCD,         &ldp_lcd_config },
 };
 
+static void __init omap_ldp_init_irq(void)
+{
+        omap_board_config = ldp_config;
+        omap_board_config_size = ARRAY_SIZE(ldp_config);
+        omap2_init_common_hw(NULL, NULL);
+        omap_init_irq();
+        omap_gpio_init();
+        ldp_init_smsc911x();
+}
+
 static struct twl4030_usb_data ldp_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
@@ -377,8 +374,6 @@ static void __init omap_ldp_init(void)
 {
         omap_i2c_init();
         platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
-        omap_board_config = ldp_config;
-        omap_board_config_size = ARRAY_SIZE(ldp_config);
         ts_gpio = 54;
         ldp_spi_board_info[0].irq = gpio_to_irq(ts_gpio);
         spi_register_board_info(ldp_spi_board_info,
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
new file mode 100644
index 000000000000..8341632d260b
--- /dev/null
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -0,0 +1,150 @@
+/*
+ * linux/arch/arm/mach-omap2/board-n8x0.c
+ *
+ * Copyright (C) 2005-2009 Nokia Corporation
+ * Author: Juha Yrjola <juha.yrjola@nokia.com>
+ *
+ * Modified from mach-omap2/board-generic.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/stddef.h>
+#include <linux/spi/spi.h>
+#include <linux/usb/musb.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/board.h>
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <mach/mcspi.h>
+#include <mach/onenand.h>
+#include <mach/serial.h>
+
+static struct omap2_mcspi_device_config p54spi_mcspi_config = {
+        .turbo_mode     = 0,
+        .single_channel = 1,
+};
+
+static struct spi_board_info n800_spi_board_info[] __initdata = {
+        {
+                .modalias       = "p54spi",
+                .bus_num        = 2,
+                .chip_select    = 0,
+                .max_speed_hz   = 48000000,
+                .controller_data = &p54spi_mcspi_config,
+        },
+};
+
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+        defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+
+static struct mtd_partition onenand_partitions[] = {
+        {
+                .name           = "bootloader",
+                .offset         = 0,
+                .size           = 0x20000,
+                .mask_flags     = MTD_WRITEABLE,        /* Force read-only */
+        },
+        {
+                .name           = "config",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 0x60000,
+        },
+        {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 0x200000,
+        },
+        {
+                .name           = "initfs",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 0x400000,
+        },
+        {
+                .name           = "rootfs",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct omap_onenand_platform_data board_onenand_data = {
+        .cs             = 0,
+        .gpio_irq       = 26,
+        .parts          = onenand_partitions,
+        .nr_parts       = ARRAY_SIZE(onenand_partitions),
+        .flags          = ONENAND_SYNC_READ,
+};
+
+static void __init n8x0_onenand_init(void)
+{
+        gpmc_onenand_init(&board_onenand_data);
+}
+
+#else
+
+static void __init n8x0_onenand_init(void) {}
+
+#endif
+
+static void __init n8x0_map_io(void)
+{
+        omap2_set_globals_242x();
+        omap2_map_common_io();
+}
+
+static void __init n8x0_init_irq(void)
+{
+        omap2_init_common_hw(NULL, NULL);
+        omap_init_irq();
+        omap_gpio_init();
+}
+
+static void __init n8x0_init_machine(void)
+{
+        /* FIXME: add n810 spi devices */
+        spi_register_board_info(n800_spi_board_info,
+                                ARRAY_SIZE(n800_spi_board_info));
+
+        omap_serial_init();
+        n8x0_onenand_init();
+}
+
+MACHINE_START(NOKIA_N800, "Nokia N800")
+        .phys_io        = 0x48000000,
+        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
+        .boot_params    = 0x80000100,
+        .map_io         = n8x0_map_io,
+        .init_irq       = n8x0_init_irq,
+        .init_machine   = n8x0_init_machine,
+        .timer          = &omap_timer,
+MACHINE_END
+
+MACHINE_START(NOKIA_N810, "Nokia N810")
+        .phys_io        = 0x48000000,
+        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
+        .boot_params    = 0x80000100,
+        .map_io         = n8x0_map_io,
+        .init_irq       = n8x0_init_irq,
+        .init_machine   = n8x0_init_machine,
+        .timer          = &omap_timer,
+MACHINE_END
+
+MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
+        .phys_io        = 0x48000000,
+        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
+        .boot_params    = 0x80000100,
+        .map_io         = n8x0_map_io,
+        .init_irq       = n8x0_init_irq,
+        .init_machine   = n8x0_init_machine,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index e00ba128cece..500c9956876d 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -108,10 +108,6 @@ static struct platform_device omap3beagle_nand_device = {
 
 #include "sdram-micron-mt46h32m32lf-6.h"
 
-static struct omap_uart_config omap3_beagle_uart_config __initdata = {
-        .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
-
 static struct twl4030_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
@@ -249,11 +245,16 @@ static struct regulator_init_data beagle_vpll2 = {
         .consumer_supplies      = &beagle_vdvi_supply,
 };
 
+static struct twl4030_usb_data beagle_usb_data = {
+        .usb_mode       = T2_USB_MODE_ULPI,
+};
+
 static struct twl4030_platform_data beagle_twldata = {
         .irq_base       = TWL4030_IRQ_BASE,
         .irq_end        = TWL4030_IRQ_END,
 
         /* platform_data for children goes here */
+        .usb            = &beagle_usb_data,
         .gpio           = &beagle_gpio_data,
         .vmmc1          = &beagle_vmmc1,
         .vsim           = &beagle_vsim,
@@ -280,17 +281,6 @@ static int __init omap3_beagle_i2c_init(void)
         return 0;
 }
 
-static void __init omap3_beagle_init_irq(void)
-{
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
-        omap_init_irq();
-#ifdef CONFIG_OMAP_32K_TIMER
-        omap2_gp_clockevent_set_gptimer(12);
-#endif
-        omap_gpio_init();
-}
-
 static struct gpio_led gpio_leds[] = {
         {
                 .name                   = "beagleboard::usr0",
@@ -345,10 +335,22 @@ static struct platform_device keys_gpio = {
 };
 
 static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
-        { OMAP_TAG_UART,        &omap3_beagle_uart_config },
         { OMAP_TAG_LCD,         &omap3_beagle_lcd_config },
 };
 
+static void __init omap3_beagle_init_irq(void)
+{
+        omap_board_config = omap3_beagle_config;
+        omap_board_config_size = ARRAY_SIZE(omap3_beagle_config);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
+        omap_init_irq();
+#ifdef CONFIG_OMAP_32K_TIMER
+        omap2_gp_clockevent_set_gptimer(12);
+#endif
+        omap_gpio_init();
+}
+
 static struct platform_device *omap3_beagle_devices[] __initdata = {
         &omap3_beagle_lcd_device,
         &leds_gpio,
@@ -398,8 +400,6 @@ static void __init omap3_beagle_init(void)
         omap3_beagle_i2c_init();
         platform_add_devices(omap3_beagle_devices,
                         ARRAY_SIZE(omap3_beagle_devices));
-        omap_board_config = omap3_beagle_config;
-        omap_board_config_size = ARRAY_SIZE(omap3_beagle_config);
         omap_serial_init();
 
         omap_cfg_reg(J25_34XX_GPIO170);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c4b144647dc5..d50b9be90580 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -92,10 +92,6 @@ static inline void __init omap3evm_init_smc911x(void)
         gpio_direction_input(OMAP3EVM_ETHR_GPIO_IRQ);
 }
 
-static struct omap_uart_config omap3_evm_uart_config __initdata = {
-        .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
-
 static struct twl4030_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
@@ -278,19 +274,20 @@ struct spi_board_info omap3evm_spi_board_info[] = {
         },
 };
 
+static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
+        { OMAP_TAG_LCD,         &omap3_evm_lcd_config },
+};
+
 static void __init omap3_evm_init_irq(void)
 {
+        omap_board_config = omap3_evm_config;
+        omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
         omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
         omap_init_irq();
         omap_gpio_init();
         omap3evm_init_smc911x();
 }
 
-static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
-        { OMAP_TAG_UART,        &omap3_evm_uart_config },
-        { OMAP_TAG_LCD,         &omap3_evm_lcd_config },
-};
-
 static struct platform_device *omap3_evm_devices[] __initdata = {
         &omap3_evm_lcd_device,
         &omap3evm_smc911x_device,
@@ -301,8 +298,6 @@ static void __init omap3_evm_init(void)
         omap3_evm_i2c_init();
 
         platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices));
-        omap_board_config = omap3_evm_config;
-        omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
 
         spi_register_board_info(omap3evm_spi_board_info,
                                 ARRAY_SIZE(omap3evm_spi_board_info));
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 864ee3d021f7..b43f6e36b6d9 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -213,10 +213,6 @@ static struct twl4030_hsmmc_info omap3pandora_mmc[] = {
         {}      /* Terminator */
 };
 
-static struct omap_uart_config omap3pandora_uart_config __initdata = {
-        .enabled_uarts  = (1 << 2), /* UART3 */
-};
-
 static struct regulator_consumer_supply pandora_vmmc1_supply = {
         .supply                 = "vmmc",
 };
@@ -309,14 +305,6 @@ static int __init omap3pandora_i2c_init(void)
         return 0;
 }
 
-static void __init omap3pandora_init_irq(void)
-{
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
-        omap_init_irq();
-        omap_gpio_init();
-}
-
 static void __init omap3pandora_ads7846_init(void)
 {
         int gpio = OMAP3_PANDORA_TS_GPIO;
@@ -376,10 +364,19 @@ static struct omap_lcd_config omap3pandora_lcd_config __initdata = {
 };
 
 static struct omap_board_config_kernel omap3pandora_config[] __initdata = {
-        { OMAP_TAG_UART,        &omap3pandora_uart_config },
         { OMAP_TAG_LCD,         &omap3pandora_lcd_config },
 };
 
+static void __init omap3pandora_init_irq(void)
+{
+        omap_board_config = omap3pandora_config;
+        omap_board_config_size = ARRAY_SIZE(omap3pandora_config);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
+        omap_init_irq();
+        omap_gpio_init();
+}
+
 static struct platform_device *omap3pandora_devices[] __initdata = {
         &omap3pandora_lcd_device,
         &pandora_leds_gpio,
@@ -391,8 +388,6 @@ static void __init omap3pandora_init(void)
         omap3pandora_i2c_init();
         platform_add_devices(omap3pandora_devices,
                         ARRAY_SIZE(omap3pandora_devices));
-        omap_board_config = omap3pandora_config;
-        omap_board_config_size = ARRAY_SIZE(omap3pandora_config);
         omap_serial_init();
         spi_register_board_info(omap3pandora_spi_board_info,
                         ARRAY_SIZE(omap3pandora_spi_board_info));
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 6bce23004aa4..9917d2fddc2f 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -271,9 +271,6 @@ static void __init overo_flash_init(void)
                         printk(KERN_ERR "Unable to register NAND device\n");
         }
 }
-static struct omap_uart_config overo_uart_config __initdata = {
-        .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
 
 static struct twl4030_hsmmc_info mmc[] = {
         {
@@ -360,14 +357,6 @@ static int __init overo_i2c_init(void)
         return 0;
 }
 
-static void __init overo_init_irq(void)
-{
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
-        omap_init_irq();
-        omap_gpio_init();
-}
-
 static struct platform_device overo_lcd_device = {
         .name           = "overo_lcd",
         .id             = -1,
@@ -378,10 +367,19 @@ static struct omap_lcd_config overo_lcd_config __initdata = {
 };
 
 static struct omap_board_config_kernel overo_config[] __initdata = {
-        { OMAP_TAG_UART,        &overo_uart_config },
         { OMAP_TAG_LCD,         &overo_lcd_config },
 };
 
+static void __init overo_init_irq(void)
+{
+        omap_board_config = overo_config;
+        omap_board_config_size = ARRAY_SIZE(overo_config);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
+        omap_init_irq();
+        omap_gpio_init();
+}
+
 static struct platform_device *overo_devices[] __initdata = {
         &overo_lcd_device,
 };
@@ -390,8 +388,6 @@ static void __init overo_init(void)
 {
         overo_i2c_init();
         platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
-        omap_board_config = overo_config;
-        omap_board_config_size = ARRAY_SIZE(overo_config);
         omap_serial_init();
         overo_flash_init();
         usb_musb_init();
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 56d931a425f7..e70baa799018 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-omap2/board-rx51-flash.c
+ * linux/arch/arm/mach-omap2/board-rx51-peripherals.c
  *
  * Copyright (C) 2008-2009 Nokia
  *
@@ -282,7 +282,124 @@ static struct twl4030_usb_data rx51_usb_data = {
         .usb_mode               = T2_USB_MODE_ULPI,
 };
 
-static struct twl4030_platform_data rx51_twldata = {
+static struct twl4030_ins sleep_on_seq[] __initdata = {
+/*
+ * Turn off VDD1 and VDD2.
+ */
+        {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
+        {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
+/*
+ * And also turn off the OMAP3 PLLs and the sysclk output.
+ */
+        {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3},
+        {MSG_SINGULAR(DEV_GRP_P1, 0x17, RES_STATE_OFF), 3},
+};
+
+static struct twl4030_script sleep_on_script __initdata = {
+        .script = sleep_on_seq,
+        .size   = ARRAY_SIZE(sleep_on_seq),
+        .flags  = TWL4030_SLEEP_SCRIPT,
+};
+
+static struct twl4030_ins wakeup_seq[] __initdata = {
+/*
+ * Reenable the OMAP3 PLLs.
+ * Wakeup VDD1 and VDD2.
+ * Reenable sysclk output.
+ */
+        {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30},
+        {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30},
+        {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37},
+        {MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3},
+};
+
+static struct twl4030_script wakeup_script __initdata = {
+        .script = wakeup_seq,
+        .size   = ARRAY_SIZE(wakeup_seq),
+        .flags  = TWL4030_WAKEUP12_SCRIPT,
+};
+
+static struct twl4030_ins wakeup_p3_seq[] __initdata = {
+/*
+ * Wakeup VDD1 (dummy to be able to insert a delay)
+ * Enable CLKEN
+ */
+        {MSG_SINGULAR(DEV_GRP_P1, 0x17, RES_STATE_ACTIVE), 3},
+};
+
+static struct twl4030_script wakeup_p3_script __initdata = {
+        .script = wakeup_p3_seq,
+        .size   = ARRAY_SIZE(wakeup_p3_seq),
+        .flags  = TWL4030_WAKEUP3_SCRIPT,
+};
+
+static struct twl4030_ins wrst_seq[] __initdata = {
+/*
+ * Reset twl4030.
+ * Reset VDD1 regulator.
+ * Reset VDD2 regulator.
+ * Reset VPLL1 regulator.
+ * Enable sysclk output.
+ * Reenable twl4030.
+ */
+        {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_OFF), 2},
+        {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 0, 1, RES_STATE_ACTIVE),
+                0x13},
+        {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 2, RES_STATE_WRST), 0x13},
+        {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 3, RES_STATE_OFF), 0x13},
+        {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD1, RES_STATE_WRST), 0x13},
+        {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD2, RES_STATE_WRST), 0x13},
+        {MSG_SINGULAR(DEV_GRP_NULL, RES_VPLL1, RES_STATE_WRST), 0x35},
+        {MSG_SINGULAR(DEV_GRP_P1, RES_HFCLKOUT, RES_STATE_ACTIVE), 2},
+        {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_ACTIVE), 2},
+};
+
+static struct twl4030_script wrst_script __initdata = {
+        .script = wrst_seq,
+        .size   = ARRAY_SIZE(wrst_seq),
+        .flags  = TWL4030_WRST_SCRIPT,
+};
+
+static struct twl4030_script *twl4030_scripts[] __initdata = {
+        /* wakeup12 script should be loaded before sleep script, otherwise a
+           board might hit retention before loading of wakeup script is
+           completed. This can cause boot failures depending on timing issues.
+        */
+        &wakeup_script,
+        &sleep_on_script,
+        &wakeup_p3_script,
+        &wrst_script,
+};
+
+static struct twl4030_resconfig twl4030_rconfig[] __initdata = {
+        { .resource = RES_VINTANA1, .devgroup = -1, .type = -1, .type2 = 1 },
+        { .resource = RES_VINTANA2, .devgroup = -1, .type = -1, .type2 = 1 },
+        { .resource = RES_VINTDIG, .devgroup = -1, .type = -1, .type2 = 1 },
+        { .resource = RES_VMMC1, .devgroup = -1, .type = -1, .type2 = 3},
+        { .resource = RES_VMMC2, .devgroup = DEV_GRP_NULL, .type = -1,
+          .type2 = 3},
+        { .resource = RES_VAUX1, .devgroup = -1, .type = -1, .type2 = 3},
+        { .resource = RES_VAUX2, .devgroup = -1, .type = -1, .type2 = 3},
+        { .resource = RES_VAUX3, .devgroup = -1, .type = -1, .type2 = 3},
+        { .resource = RES_VAUX4, .devgroup = -1, .type = -1, .type2 = 3},
+        { .resource = RES_VPLL2, .devgroup = -1, .type = -1, .type2 = 3},
+        { .resource = RES_VDAC, .devgroup = -1, .type = -1, .type2 = 3},
+        { .resource = RES_VSIM, .devgroup = DEV_GRP_NULL, .type = -1,
+          .type2 = 3},
+        { .resource = RES_CLKEN, .devgroup = DEV_GRP_P3, .type = -1,
+                .type2 = 1 },
+        { 0, 0},
+};
+
+static struct twl4030_power_data rx51_t2scripts_data __initdata = {
+        .scripts        = twl4030_scripts,
+        .num = ARRAY_SIZE(twl4030_scripts),
+        .resource_config = twl4030_rconfig,
+};
+
+
+
+static struct twl4030_platform_data rx51_twldata __initdata = {
         .irq_base               = TWL4030_IRQ_BASE,
         .irq_end                = TWL4030_IRQ_END,
 
@@ -291,6 +408,7 @@ static struct twl4030_platform_data rx51_twldata = {
         .keypad                 = &rx51_kp_data,
         .madc                   = &rx51_madc_data,
         .usb                    = &rx51_usb_data,
+        .power                  = &rx51_t2scripts_data,
 
         .vaux1                  = &rx51_vaux1,
         .vaux2                  = &rx51_vaux2,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 1c9e07fe8266..f9196c3b1a7b 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -31,10 +31,6 @@
 #include <mach/gpmc.h>
 #include <mach/usb.h>
 
-static struct omap_uart_config rx51_uart_config = {
-        .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
-};
-
 static struct omap_lcd_config rx51_lcd_config = {
         .ctrl_name      = "internal",
 };
@@ -52,7 +48,6 @@ static struct omap_fbmem_config rx51_fbmem2_config = {
 };
 
 static struct omap_board_config_kernel rx51_config[] = {
-        { OMAP_TAG_UART,        &rx51_uart_config },
         { OMAP_TAG_FBMEM,       &rx51_fbmem0_config },
         { OMAP_TAG_FBMEM,       &rx51_fbmem1_config },
         { OMAP_TAG_FBMEM,       &rx51_fbmem2_config },
@@ -61,6 +56,8 @@ static struct omap_board_config_kernel rx51_config[] = {
 
 static void __init rx51_init_irq(void)
 {
+        omap_board_config = rx51_config;
+        omap_board_config_size = ARRAY_SIZE(rx51_config);
         omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
@@ -70,8 +67,6 @@ extern void __init rx51_peripherals_init(void);
 
 static void __init rx51_init(void)
 {
-        omap_board_config = rx51_config;
-        omap_board_config_size = ARRAY_SIZE(rx51_config);
         omap_serial_init();
         usb_musb_init();
         rx51_peripherals_init();
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index bac5c4321ff7..1f13e2a1f322 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -12,6 +12,7 @@
 #include <linux/gpio.h>
 #include <linux/serial_8250.h>
 #include <linux/smsc911x.h>
+#include <linux/interrupt.h>
 
 #include <mach/gpmc.h>
 
@@ -84,6 +85,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .mapbase        = 0x10000000,
                 .irq            = OMAP_GPIO_IRQ(102),
                 .flags          = UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ,
+                .irqflags       = IRQF_SHARED | IRQF_TRIGGER_RISING,
                 .iotype         = UPIO_MEM,
                 .regshift       = 1,
                 .uartclk        = QUART_CLK,
@@ -94,7 +96,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
 
 static struct platform_device zoom2_debugboard_serial_device = {
         .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM1,
+        .id                     = 3,
         .dev                    = {
                 .platform_data  = serial_platform_data,
         },
@@ -127,6 +129,7 @@ static inline void __init zoom2_init_quaduart(void)
 static inline int omap_zoom2_debugboard_detect(void)
 {
         int debug_board_detect = 0;
+        int ret = 1;
 
         debug_board_detect = ZOOM2_SMSC911X_GPIO;
 
@@ -138,10 +141,10 @@ static inline int omap_zoom2_debugboard_detect(void)
         gpio_direction_input(debug_board_detect);
 
         if (!gpio_get_value(debug_board_detect)) {
-                gpio_free(debug_board_detect);
-                return 0;
+                ret = 0;
         }
-        return 1;
+        gpio_free(debug_board_detect);
+        return ret;
 }
 
 static struct platform_device *zoom2_devices[] __initdata = {
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index 427b7b8b1237..324009edbd53 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -12,36 +12,217 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/i2c/twl4030.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
 #include <mach/common.h>
 #include <mach/usb.h>
+#include <mach/keypad.h>
 
 #include "mmc-twl4030.h"
 
-static void __init omap_zoom2_init_irq(void)
+/* Zoom2 has Qwerty keyboard*/
+static int zoom2_twl4030_keymap[] = {
+        KEY(0, 0, KEY_E),
+        KEY(1, 0, KEY_R),
+        KEY(2, 0, KEY_T),
+        KEY(3, 0, KEY_HOME),
+        KEY(6, 0, KEY_I),
+        KEY(7, 0, KEY_LEFTSHIFT),
+        KEY(0, 1, KEY_D),
+        KEY(1, 1, KEY_F),
+        KEY(2, 1, KEY_G),
+        KEY(3, 1, KEY_SEND),
+        KEY(6, 1, KEY_K),
+        KEY(7, 1, KEY_ENTER),
+        KEY(0, 2, KEY_X),
+        KEY(1, 2, KEY_C),
+        KEY(2, 2, KEY_V),
+        KEY(3, 2, KEY_END),
+        KEY(6, 2, KEY_DOT),
+        KEY(7, 2, KEY_CAPSLOCK),
+        KEY(0, 3, KEY_Z),
+        KEY(1, 3, KEY_KPPLUS),
+        KEY(2, 3, KEY_B),
+        KEY(3, 3, KEY_F1),
+        KEY(6, 3, KEY_O),
+        KEY(7, 3, KEY_SPACE),
+        KEY(0, 4, KEY_W),
+        KEY(1, 4, KEY_Y),
+        KEY(2, 4, KEY_U),
+        KEY(3, 4, KEY_F2),
+        KEY(4, 4, KEY_VOLUMEUP),
+        KEY(6, 4, KEY_L),
+        KEY(7, 4, KEY_LEFT),
+        KEY(0, 5, KEY_S),
+        KEY(1, 5, KEY_H),
+        KEY(2, 5, KEY_J),
+        KEY(3, 5, KEY_F3),
+        KEY(5, 5, KEY_VOLUMEDOWN),
+        KEY(6, 5, KEY_M),
+        KEY(4, 5, KEY_ENTER),
+        KEY(7, 5, KEY_RIGHT),
+        KEY(0, 6, KEY_Q),
+        KEY(1, 6, KEY_A),
+        KEY(2, 6, KEY_N),
+        KEY(3, 6, KEY_BACKSPACE),
+        KEY(6, 6, KEY_P),
+        KEY(7, 6, KEY_UP),
+        KEY(6, 7, KEY_SELECT),
+        KEY(7, 7, KEY_DOWN),
+        KEY(0, 7, KEY_PROG1),   /*MACRO 1 <User defined> */
+        KEY(1, 7, KEY_PROG2),   /*MACRO 2 <User defined> */
+        KEY(2, 7, KEY_PROG3),   /*MACRO 3 <User defined> */
+        KEY(3, 7, KEY_PROG4),   /*MACRO 4 <User defined> */
+        0
+};
+
+static struct twl4030_keypad_data zoom2_kp_twl4030_data = {
+        .rows           = 8,
+        .cols           = 8,
+        .keymap         = zoom2_twl4030_keymap,
+        .keymapsize     = ARRAY_SIZE(zoom2_twl4030_keymap),
+        .rep            = 1,
+};
+
+static struct omap_board_config_kernel zoom2_config[] __initdata = {
+};
+
+static struct regulator_consumer_supply zoom2_vmmc1_supply = {
+        .supply         = "vmmc",
+};
+
+static struct regulator_consumer_supply zoom2_vsim_supply = {
+        .supply         = "vmmc_aux",
+};
+
+static struct regulator_consumer_supply zoom2_vmmc2_supply = {
+        .supply         = "vmmc",
+};
+
+/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
+static struct regulator_init_data zoom2_vmmc1 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &zoom2_vmmc1_supply,
+};
+
+/* VMMC2 for MMC2 card */
+static struct regulator_init_data zoom2_vmmc2 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 1850000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &zoom2_vmmc2_supply,
+};
+
+/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
+static struct regulator_init_data zoom2_vsim = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 3000000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &zoom2_vsim_supply,
+};
+
+static struct twl4030_hsmmc_info mmc[] __initdata = {
+        {
+                .mmc            = 1,
+                .wires          = 4,
+                .gpio_wp        = -EINVAL,
+        },
+        {
+                .mmc            = 2,
+                .wires          = 4,
+                .gpio_wp        = -EINVAL,
+        },
+        {}      /* Terminator */
+};
+
+static int zoom2_twl_gpio_setup(struct device *dev,
+                unsigned gpio, unsigned ngpio)
 {
-        omap2_init_common_hw(NULL, NULL);
-        omap_init_irq();
-        omap_gpio_init();
+        /* gpio + 0 is "mmc0_cd" (input/IRQ),
+         * gpio + 1 is "mmc1_cd" (input/IRQ)
+         */
+        mmc[0].gpio_cd = gpio + 0;
+        mmc[1].gpio_cd = gpio + 1;
+        twl4030_mmc_init(mmc);
+
+        /* link regulators to MMC adapters ... we "know" the
+         * regulators will be set up only *after* we return.
+        */
+        zoom2_vmmc1_supply.dev = mmc[0].dev;
+        zoom2_vsim_supply.dev = mmc[0].dev;
+        zoom2_vmmc2_supply.dev = mmc[1].dev;
+
+        return 0;
 }
 
-static struct omap_uart_config zoom2_uart_config __initdata = {
-        .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
+
+static int zoom2_batt_table[] = {
+/* 0 C*/
+30800, 29500, 28300, 27100,
+26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
+17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
+11600, 11200, 10800, 10400, 10000, 9630,  9280,  8950,  8620,  8310,
+8020,  7730,  7460,  7200,  6950,  6710,  6470,  6250,  6040,  5830,
+5640,  5450,  5260,  5090,  4920,  4760,  4600,  4450,  4310,  4170,
+4040,  3910,  3790,  3670,  3550
 };
 
-static struct omap_board_config_kernel zoom2_config[] __initdata = {
-        { OMAP_TAG_UART,        &zoom2_uart_config },
+static struct twl4030_bci_platform_data zoom2_bci_data = {
+        .battery_tmp_tbl        = zoom2_batt_table,
+        .tblsize                = ARRAY_SIZE(zoom2_batt_table),
 };
 
+static struct twl4030_usb_data zoom2_usb_data = {
+        .usb_mode       = T2_USB_MODE_ULPI,
+};
+
+static void __init omap_zoom2_init_irq(void)
+{
+        omap_board_config = zoom2_config;
+        omap_board_config_size = ARRAY_SIZE(zoom2_config);
+        omap2_init_common_hw(NULL, NULL);
+        omap_init_irq();
+        omap_gpio_init();
+}
+
 static struct twl4030_gpio_platform_data zoom2_gpio_data = {
         .gpio_base      = OMAP_MAX_GPIO_LINES,
         .irq_base       = TWL4030_GPIO_IRQ_BASE,
         .irq_end        = TWL4030_GPIO_IRQ_END,
+        .setup          = zoom2_twl_gpio_setup,
+};
+
+static struct twl4030_madc_platform_data zoom2_madc_data = {
+        .irq_line       = 1,
 };
 
 static struct twl4030_platform_data zoom2_twldata = {
@@ -49,7 +230,15 @@ static struct twl4030_platform_data zoom2_twldata = {
         .irq_end        = TWL4030_IRQ_END,
 
         /* platform_data for children goes here */
+        .bci            = &zoom2_bci_data,
+        .madc           = &zoom2_madc_data,
+        .usb            = &zoom2_usb_data,
         .gpio           = &zoom2_gpio_data,
+        .keypad         = &zoom2_kp_twl4030_data,
+        .vmmc1          = &zoom2_vmmc1,
+        .vmmc2          = &zoom2_vmmc2,
+        .vsim           = &zoom2_vsim,
+
 };
 
 static struct i2c_board_info __initdata zoom2_i2c_boardinfo[] = {
@@ -70,26 +259,13 @@ static int __init omap_i2c_init(void)
         return 0;
 }
 
-static struct twl4030_hsmmc_info mmc[] __initdata = {
-        {
-                .mmc            = 1,
-                .wires          = 4,
-                .gpio_cd        = -EINVAL,
-                .gpio_wp        = -EINVAL,
-        },
-        {}      /* Terminator */
-};
-
 extern int __init omap_zoom2_debugboard_init(void);
 
 static void __init omap_zoom2_init(void)
 {
         omap_i2c_init();
-        omap_board_config = zoom2_config;
-        omap_board_config_size = ARRAY_SIZE(zoom2_config);
         omap_serial_init();
         omap_zoom2_debugboard_init();
-        twl4030_mmc_init(mmc);
         usb_musb_init();
 }
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 456e2ad5f621..f2a92d614f0f 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -1043,5 +1043,7 @@ void omap2_clk_disable_unused(struct clk *clk)
                 omap2_clk_disable(clk);
         } else
                 _omap2_clk_disable(clk);
+        if (clk->clkdm != NULL)
+                pwrdm_clkdm_state_switch(clk->clkdm);
 }
 #endif
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index cd7819cc0c9e..fafcd32e6907 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -27,6 +27,7 @@
 #include <linux/limits.h>
 #include <linux/bitops.h>
 
+#include <mach/cpu.h>
 #include <mach/clock.h>
 #include <mach/sram.h>
 #include <asm/div64.h>
@@ -1067,17 +1068,17 @@ static int __init omap2_clk_arch_init(void)
                 return -EINVAL;
 
         /* REVISIT: not yet ready for 343x */
-#if 0
-        if (clk_set_rate(&virt_prcm_set, mpurate))
-                printk(KERN_ERR "Could not find matching MPU rate\n");
-#endif
+        if (clk_set_rate(&dpll1_ck, mpurate))
+                printk(KERN_ERR "*** Unable to set MPU rate\n");
 
         recalculate_root_clocks();
 
-        printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
+        printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): "
                "%ld.%01ld/%ld/%ld MHz\n",
-               (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
-               (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
+               (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10),
+               (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ;
+
+        calibrate_delay();
 
         return 0;
 }
@@ -1136,7 +1137,7 @@ int __init omap2_clk_init(void)
 
         recalculate_root_clocks();
 
-        printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
+        printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
                "%ld.%01ld/%ld/%ld MHz\n",
                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
                (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 57cc2725b923..c8119781e00a 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1020,6 +1020,7 @@ static struct clk arm_fck = {
         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
         .clksel         = arm_fck_clksel,
+        .clkdm_name     = "mpu_clkdm",
         .recalc         = &omap2_clksel_recalc,
 };
 
@@ -1155,7 +1156,6 @@ static struct clk gfx_cg1_ck = {
         .name           = "gfx_cg1_ck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
         .clkdm_name     = "gfx_3430es1_clkdm",
@@ -1166,7 +1166,6 @@ static struct clk gfx_cg2_ck = {
         .name           = "gfx_cg2_ck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
         .clkdm_name     = "gfx_3430es1_clkdm",
@@ -1210,7 +1209,6 @@ static struct clk sgx_ick = {
         .name           = "sgx_ick",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &l3_ick,
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
         .clkdm_name     = "sgx_clkdm",
@@ -1223,7 +1221,6 @@ static struct clk d2d_26m_fck = {
         .name           = "d2d_26m_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &sys_ck,
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
         .clkdm_name     = "d2d_clkdm",
@@ -1234,7 +1231,6 @@ static struct clk modem_fck = {
         .name           = "modem_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &sys_ck,
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
         .clkdm_name     = "d2d_clkdm",
@@ -1622,7 +1618,6 @@ static struct clk core_l3_ick = {
         .name           = "core_l3_ick",
         .ops            = &clkops_null,
         .parent         = &l3_ick,
-        .init           = &omap2_init_clk_clkdm,
         .clkdm_name     = "core_l3_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -1691,7 +1686,6 @@ static struct clk core_l4_ick = {
         .name           = "core_l4_ick",
         .ops            = &clkops_null,
         .parent         = &l4_ick,
-        .init           = &omap2_init_clk_clkdm,
         .clkdm_name     = "core_l4_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -2089,7 +2083,6 @@ static struct clk dss_tv_fck = {
         .name           = "dss_tv_fck",
         .ops            = &clkops_omap2_dflt,
         .parent         = &omap_54m_fck,
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_TV_SHIFT,
         .clkdm_name     = "dss_clkdm",
@@ -2100,7 +2093,6 @@ static struct clk dss_96m_fck = {
         .name           = "dss_96m_fck",
         .ops            = &clkops_omap2_dflt,
         .parent         = &omap_96m_fck,
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_TV_SHIFT,
         .clkdm_name     = "dss_clkdm",
@@ -2111,7 +2103,6 @@ static struct clk dss2_alwon_fck = {
         .name           = "dss2_alwon_fck",
         .ops            = &clkops_omap2_dflt,
         .parent         = &sys_ck,
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
         .clkdm_name     = "dss_clkdm",
@@ -2123,7 +2114,6 @@ static struct clk dss_ick_3430es1 = {
         .name           = "dss_ick",
         .ops            = &clkops_omap2_dflt,
         .parent         = &l4_ick,
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
         .clkdm_name     = "dss_clkdm",
@@ -2135,7 +2125,6 @@ static struct clk dss_ick_3430es2 = {
         .name           = "dss_ick",
         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
         .parent         = &l4_ick,
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
         .clkdm_name     = "dss_clkdm",
@@ -2159,7 +2148,6 @@ static struct clk cam_ick = {
         .name           = "cam_ick",
         .ops            = &clkops_omap2_dflt,
         .parent         = &l4_ick,
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
         .clkdm_name     = "cam_clkdm",
@@ -2170,7 +2158,6 @@ static struct clk csi2_96m_fck = {
         .name           = "csi2_96m_fck",
         .ops            = &clkops_omap2_dflt,
         .parent         = &core_96m_fck,
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
         .clkdm_name     = "cam_clkdm",
@@ -2183,7 +2170,6 @@ static struct clk usbhost_120m_fck = {
         .name           = "usbhost_120m_fck",
         .ops            = &clkops_omap2_dflt,
         .parent         = &dpll5_m2_ck,
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
         .clkdm_name     = "usbhost_clkdm",
@@ -2194,7 +2180,6 @@ static struct clk usbhost_48m_fck = {
         .name           = "usbhost_48m_fck",
         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
         .parent         = &omap_48m_fck,
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
         .clkdm_name     = "usbhost_clkdm",
@@ -2206,7 +2191,6 @@ static struct clk usbhost_ick = {
         .name           = "usbhost_ick",
         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
         .parent         = &l4_ick,
-        .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
         .clkdm_name     = "usbhost_clkdm",
@@ -2268,7 +2252,6 @@ static struct clk gpt1_fck = {
 static struct clk wkup_32k_fck = {
         .name           = "wkup_32k_fck",
         .ops            = &clkops_null,
-        .init           = &omap2_init_clk_clkdm,
         .parent         = &omap_32k_fck,
         .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
@@ -2383,7 +2366,6 @@ static struct clk per_96m_fck = {
         .name           = "per_96m_fck",
         .ops            = &clkops_null,
         .parent         = &omap_96m_alwon_fck,
-        .init           = &omap2_init_clk_clkdm,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
@@ -2392,7 +2374,6 @@ static struct clk per_48m_fck = {
         .name           = "per_48m_fck",
         .ops            = &clkops_null,
         .parent         = &omap_48m_fck,
-        .init           = &omap2_init_clk_clkdm,
         .clkdm_name     = "per_clkdm",
         .recalc         = &followparent_recalc,
 };
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 0e7d501865b6..4ef7b4f5474e 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -299,7 +299,8 @@ struct clockdomain *clkdm_lookup(const char *name)
  * anything else to indicate failure; or -EINVAL if the function pointer
  * is null.
  */
-int clkdm_for_each(int (*fn)(struct clockdomain *clkdm))
+int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
+                        void *user)
 {
         struct clockdomain *clkdm;
         int ret = 0;
@@ -309,7 +310,7 @@ int clkdm_for_each(int (*fn)(struct clockdomain *clkdm))
 
         mutex_lock(&clkdm_mutex);
         list_for_each_entry(clkdm, &clkdm_list, node) {
-                ret = (*fn)(clkdm);
+                ret = (*fn)(clkdm, user);
                 if (ret)
                         break;
         }
@@ -484,6 +485,8 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
                             v << __ffs(clkdm->clktrctrl_mask),
                             clkdm->pwrdm.ptr->prcm_offs,
                             CM_CLKSTCTRL);
+
+        pwrdm_clkdm_state_switch(clkdm);
 }
 
 /**
@@ -572,6 +575,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
                 omap2_clkdm_wakeup(clkdm);
 
         pwrdm_wait_transition(clkdm->pwrdm.ptr);
+        pwrdm_clkdm_state_switch(clkdm);
 
         return 0;
 }
@@ -624,6 +628,8 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
         else
                 omap2_clkdm_sleep(clkdm);
 
+        pwrdm_clkdm_state_switch(clkdm);
+
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c
new file mode 100644
index 000000000000..8eb2dab8c7db
--- /dev/null
+++ b/arch/arm/mach-omap2/cm.c
@@ -0,0 +1,70 @@
+/*
+ * OMAP2/3 CM module functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <asm/atomic.h>
+
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
+
+/* MAX_MODULE_READY_TIME: max milliseconds for module to leave idle */
+#define MAX_MODULE_READY_TIME           20000
+
+static const u8 cm_idlest_offs[] = {
+        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
+};
+
+/**
+ * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
+ * @prcm_mod: PRCM module offset
+ * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
+ * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
+ *
+ * XXX document
+ */
+int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
+{
+        int ena = 0, i = 0;
+        u8 cm_idlest_reg;
+        u32 mask;
+
+        if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
+                return -EINVAL;
+
+        cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
+
+        if (cpu_is_omap24xx())
+                ena = idlest_shift;
+        else if (cpu_is_omap34xx())
+                ena = 0;
+        else
+                BUG();
+
+        mask = 1 << idlest_shift;
+
+        /* XXX should be OMAP2 CM */
+        while (((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) != ena) &&
+               (i++ < MAX_MODULE_READY_TIME))
+                udelay(1);
+
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index f3c91a1ca391..cfd0b726ba44 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -17,11 +17,11 @@
 #include "prcm-common.h"
 
 #define OMAP2420_CM_REGADDR(module, reg)                                \
-                        IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
+                        OMAP2_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
 #define OMAP2430_CM_REGADDR(module, reg)                                \
-                        IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
+                        OMAP2_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
 #define OMAP34XX_CM_REGADDR(module, reg)                                \
-                        IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+                        OMAP2_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
 
 /*
  * Architecture-specific global CM registers
@@ -98,6 +98,10 @@ extern u32 cm_read_mod_reg(s16 module, u16 idx);
 extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
 extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
 
+extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
+                                      u8 idlest_shift);
+extern int omap4_cm_wait_module_ready(u32 prcm_mod, u8 prcm_dev_offs);
+
 static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
 {
         return cm_rmw_mod_reg_bits(bits, bits, module, idx);
diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c
new file mode 100644
index 000000000000..e4ebd6d53135
--- /dev/null
+++ b/arch/arm/mach-omap2/cm4xxx.c
@@ -0,0 +1,68 @@
+/*
+ * OMAP4 CM module functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <asm/atomic.h>
+
+#include "cm.h"
+#include "cm-regbits-4xxx.h"
+
+/* XXX move this to cm.h */
+/* MAX_MODULE_READY_TIME: max milliseconds for module to leave idle */
+#define MAX_MODULE_READY_TIME                   20000
+
+/*
+ * OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK: isolates the IDLEST field in the
+ * CM_CLKCTRL register.
+ */
+#define OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK       (0x2 << 16)
+
+/*
+ * OMAP4 prcm_mod u32 fields contain packed data: the CM ID in bit 16 and
+ * the PRCM module offset address (from the CM module base) in bits 15-0.
+ */
+#define OMAP4_PRCM_MOD_CM_ID_SHIFT              16
+#define OMAP4_PRCM_MOD_OFFS_MASK                0xffff
+
+/**
+ * omap4_cm_wait_idlest_ready - wait for a module to leave idle or standby
+ * @prcm_mod: PRCM module offset (XXX example)
+ * @prcm_dev_offs: PRCM device offset (e.g. MCASP XXX example)
+ *
+ * XXX document
+ */
+int omap4_cm_wait_idlest_ready(u32 prcm_mod, u8 prcm_dev_offs)
+{
+        int i = 0;
+        u8 cm_id;
+        u16 prcm_mod_offs;
+        u32 mask = OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK;
+
+        cm_id = prcm_mod >> OMAP4_PRCM_MOD_CM_ID_SHIFT;
+        prcm_mod_offs = prcm_mod & OMAP4_PRCM_MOD_OFFS_MASK;
+
+        while (((omap4_cm_read_mod_reg(cm_id, prcm_mod_offs, prcm_dev_offs,
+                                       OMAP4_CM_CLKCTRL_DREG) & mask) != 0) &&
+               (i++ < MAX_MODULE_READY_TIME))
+                udelay(1);
+
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 894cc355818a..a2e915639b72 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -513,6 +513,47 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                         omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
                 }
         }
+
+        if (cpu_is_omap3430()) {
+                if (controller_nr == 0) {
+                        omap_cfg_reg(N28_3430_MMC1_CLK);
+                        omap_cfg_reg(M27_3430_MMC1_CMD);
+                        omap_cfg_reg(N27_3430_MMC1_DAT0);
+                        if (mmc_controller->slots[0].wires == 4 ||
+                                mmc_controller->slots[0].wires == 8) {
+                                omap_cfg_reg(N26_3430_MMC1_DAT1);
+                                omap_cfg_reg(N25_3430_MMC1_DAT2);
+                                omap_cfg_reg(P28_3430_MMC1_DAT3);
+                        }
+                        if (mmc_controller->slots[0].wires == 8) {
+                                omap_cfg_reg(P27_3430_MMC1_DAT4);
+                                omap_cfg_reg(P26_3430_MMC1_DAT5);
+                                omap_cfg_reg(R27_3430_MMC1_DAT6);
+                                omap_cfg_reg(R25_3430_MMC1_DAT7);
+                        }
+                }
+                if (controller_nr == 1) {
+                        /* MMC2 */
+                        omap_cfg_reg(AE2_3430_MMC2_CLK);
+                        omap_cfg_reg(AG5_3430_MMC2_CMD);
+                        omap_cfg_reg(AH5_3430_MMC2_DAT0);
+
+                        /*
+                         * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
+                         * in the board-*.c files
+                         */
+                        if (mmc_controller->slots[0].wires == 4 ||
+                                mmc_controller->slots[0].wires == 8) {
+                                omap_cfg_reg(AH4_3430_MMC2_DAT1);
+                                omap_cfg_reg(AG4_3430_MMC2_DAT2);
+                                omap_cfg_reg(AF4_3430_MMC2_DAT3);
+                        }
+                }
+
+                /*
+                 * For MMC3 the pins need to be muxed in the board-*.c files
+                 */
+        }
 }
 
 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index e9b9bcb19b4e..7574b6f20e8e 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -32,17 +32,23 @@
 #include <mach/sram.h>
 #include <mach/sdrc.h>
 #include <mach/gpmc.h>
+#include <mach/serial.h>
 
 #ifndef CONFIG_ARCH_OMAP4       /* FIXME: Remove this once clkdev is ready */
 #include "clock.h"
 
+#include <mach/omap-pm.h>
 #include <mach/powerdomain.h>
-
 #include "powerdomains.h"
 
 #include <mach/clockdomain.h>
 #include "clockdomains.h"
 #endif
+#include <mach/omap_hwmod.h>
+#include "omap_hwmod_2420.h"
+#include "omap_hwmod_2430.h"
+#include "omap_hwmod_34xx.h"
+
 /*
  * The machine specific code may provide the extra mapping besides the
  * default mapping provided here.
@@ -279,11 +285,26 @@ static int __init _omap2_init_reprogram_sdrc(void)
 void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
                                  struct omap_sdrc_params *sdrc_cs1)
 {
+        struct omap_hwmod **hwmods = NULL;
+
+        if (cpu_is_omap2420())
+                hwmods = omap2420_hwmods;
+        else if (cpu_is_omap2430())
+                hwmods = omap2430_hwmods;
+        else if (cpu_is_omap34xx())
+                hwmods = omap34xx_hwmods;
+
+        omap_hwmod_init(hwmods);
         omap2_mux_init();
 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
+        /* The OPP tables have to be registered before a clk init */
+        omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
         pwrdm_init(powerdomains_omap);
         clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
         omap2_clk_init();
+        omap_serial_early_init();
+        omap_hwmod_late_init();
+        omap_pm_if_init();
         omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
         _omap2_init_reprogram_sdrc();
 #endif
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 015f22a53ead..2d9b5cc981cd 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -217,10 +217,19 @@ static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf)
 }
 
 #define pr_reg(name)                                                    \
-        p += sprintf(p, "%20s: %08x\n",                                 \
-                     __stringify(name), iommu_read_reg(obj, MMU_##name));
-
-static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf)
+        do {                                                            \
+                ssize_t bytes;                                          \
+                const char *str = "%20s: %08x\n";                       \
+                const int maxcol = 32;                                  \
+                bytes = snprintf(p, maxcol, str, __stringify(name),     \
+                                 iommu_read_reg(obj, MMU_##name));      \
+                p += bytes;                                             \
+                len -= bytes;                                           \
+                if (len < maxcol)                                       \
+                        goto out;                                       \
+        } while (0)
+
+static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len)
 {
         char *p = buf;
 
@@ -242,7 +251,7 @@ static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf)
         pr_reg(READ_CAM);
         pr_reg(READ_RAM);
         pr_reg(EMU_FAULT_AD);
-
+out:
         return p - buf;
 }
 
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 99b6e1546311..a846aa1ebb4d 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -128,6 +128,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
+                .buffer_size    = 0x6F,
         },
         {
                 .phys_base      = OMAP34XX_MCBSP2_BASE,
@@ -136,6 +137,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
+                .buffer_size    = 0x3FF,
         },
         {
                 .phys_base      = OMAP34XX_MCBSP3_BASE,
@@ -144,6 +146,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
+                .buffer_size    = 0x6F,
         },
         {
                 .phys_base      = OMAP34XX_MCBSP4_BASE,
@@ -152,6 +155,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
+                .buffer_size    = 0x6F,
         },
         {
                 .phys_base      = OMAP34XX_MCBSP5_BASE,
@@ -160,6 +164,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
                 .ops            = &omap2_mcbsp_ops,
+                .buffer_size    = 0x6F,
         },
 };
 #define OMAP34XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap34xx_mcbsp_pdata)
@@ -168,6 +173,42 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
 #define OMAP34XX_MCBSP_PDATA_SZ         0
 #endif
 
+static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
+        {
+                .phys_base      = OMAP44XX_MCBSP1_BASE,
+                .dma_rx_sync    = OMAP44XX_DMA_MCBSP1_RX,
+                .dma_tx_sync    = OMAP44XX_DMA_MCBSP1_TX,
+                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+        },
+        {
+                .phys_base      = OMAP44XX_MCBSP2_BASE,
+                .dma_rx_sync    = OMAP44XX_DMA_MCBSP2_RX,
+                .dma_tx_sync    = OMAP44XX_DMA_MCBSP2_TX,
+                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+        },
+        {
+                .phys_base      = OMAP44XX_MCBSP3_BASE,
+                .dma_rx_sync    = OMAP44XX_DMA_MCBSP3_RX,
+                .dma_tx_sync    = OMAP44XX_DMA_MCBSP3_TX,
+                .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+        },
+        {
+                .phys_base      = OMAP44XX_MCBSP4_BASE,
+                .dma_rx_sync    = OMAP44XX_DMA_MCBSP4_RX,
+                .dma_tx_sync    = OMAP44XX_DMA_MCBSP4_TX,
+                .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+        },
+};
+#define OMAP44XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap44xx_mcbsp_pdata)
+
 static int __init omap2_mcbsp_init(void)
 {
         if (cpu_is_omap2420())
@@ -176,6 +217,8 @@ static int __init omap2_mcbsp_init(void)
                 omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
         if (cpu_is_omap34xx())
                 omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
+        if (cpu_is_omap44xx())
+                omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
 
         mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
                                                                 GFP_KERNEL);
@@ -191,6 +234,9 @@ static int __init omap2_mcbsp_init(void)
         if (cpu_is_omap34xx())
                 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
                                                 OMAP34XX_MCBSP_PDATA_SZ);
+        if (cpu_is_omap44xx())
+                omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
+                                                OMAP44XX_MCBSP_PDATA_SZ);
 
         return omap_mcbsp_init();
 }
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 43d6b92b65f2..2daa595aaff4 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -492,6 +492,61 @@ MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
                 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
 MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
                 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
+
+/* MMC1 */
+MUX_CFG_34XX("N28_3430_MMC1_CLK", 0x144,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("M27_3430_MMC1_CMD", 0x146,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("N27_3430_MMC1_DAT0", 0x148,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("N26_3430_MMC1_DAT1", 0x14a,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("N25_3430_MMC1_DAT2", 0x14c,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("P28_3430_MMC1_DAT3", 0x14e,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("P27_3430_MMC1_DAT4", 0x150,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("P26_3430_MMC1_DAT5", 0x152,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("R27_3430_MMC1_DAT6", 0x154,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("R25_3430_MMC1_DAT7", 0x156,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+
+/* MMC2 */
+MUX_CFG_34XX("AE2_3430_MMC2_CLK", 0x158,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AG5_3430_MMC2_CMD", 0x15A,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AH5_3430_MMC2_DAT0", 0x15c,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AH4_3430_MMC2_DAT1", 0x15e,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AG4_3430_MMC2_DAT2", 0x160,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AF4_3430_MMC2_DAT3", 0x162,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+
+/* MMC3 */
+MUX_CFG_34XX("AF10_3430_MMC3_CLK", 0x5d8,
+                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AC3_3430_MMC3_CMD", 0x1d0,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AE11_3430_MMC3_DAT0", 0x5e4,
+                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AH9_3430_MMC3_DAT1", 0x5e6,
+                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AF13_3430_MMC3_DAT2", 0x5e8,
+                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AF13_3430_MMC3_DAT3", 0x5e2,
+                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
+
+/* SYS_NIRQ T2 INT1 */
+MUX_CFG_34XX("AF26_34XX_SYS_NIRQ", 0x1E0,
+                OMAP3_WAKEUP_EN | OMAP34XX_PIN_INPUT_PULLUP |
+                OMAP34XX_MUX_MODE0)
 };
 
 #define OMAP34XX_PINS_SZ        ARRAY_SIZE(omap34xx_pins)
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 8fe8d230f21b..48ee295db275 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -54,7 +54,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
          * for us: do so
          */
 
-        gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
+        gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
 
         /*
          * Synchronise with the boot thread.
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
new file mode 100644
index 000000000000..d2e0f1c95961
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -0,0 +1,1554 @@
+/*
+ * omap_hwmod implementation for OMAP2/3/4
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ * With fixes and testing from Kevin Hilman
+ *
+ * Created in collaboration with (alphabetical order): Benoit Cousson,
+ * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
+ * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This code manages "OMAP modules" (on-chip devices) and their
+ * integration with Linux device driver and bus code.
+ *
+ * References:
+ * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
+ * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
+ * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
+ * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
+ * - Open Core Protocol Specification 2.2
+ *
+ * To do:
+ * - pin mux handling
+ * - handle IO mapping
+ * - bus throughput & module latency measurement code
+ *
+ * XXX add tests at the beginning of each function to ensure the hwmod is
+ * in the appropriate state
+ * XXX error return values should be checked to ensure that they are
+ * appropriate
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/bootmem.h>
+
+#include <mach/cpu.h>
+#include <mach/clockdomain.h>
+#include <mach/powerdomain.h>
+#include <mach/clock.h>
+#include <mach/omap_hwmod.h>
+
+#include "cm.h"
+
+/* Maximum microseconds to wait for OMAP module to reset */
+#define MAX_MODULE_RESET_WAIT           10000
+
+/* Name of the OMAP hwmod for the MPU */
+#define MPU_INITIATOR_NAME              "mpu_hwmod"
+
+/* omap_hwmod_list contains all registered struct omap_hwmods */
+static LIST_HEAD(omap_hwmod_list);
+
+static DEFINE_MUTEX(omap_hwmod_mutex);
+
+/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
+static struct omap_hwmod *mpu_oh;
+
+/* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */
+static u8 inited;
+
+
+/* Private functions */
+
+/**
+ * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy
+ * @oh: struct omap_hwmod *
+ *
+ * Load the current value of the hwmod OCP_SYSCONFIG register into the
+ * struct omap_hwmod for later use.  Returns -EINVAL if the hwmod has no
+ * OCP_SYSCONFIG register or 0 upon success.
+ */
+static int _update_sysc_cache(struct omap_hwmod *oh)
+{
+        if (!oh->sysconfig) {
+                WARN(!oh->sysconfig, "omap_hwmod: %s: cannot read "
+                     "OCP_SYSCONFIG: not defined on hwmod\n", oh->name);
+                return -EINVAL;
+        }
+
+        /* XXX ensure module interface clock is up */
+
+        oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs);
+
+        oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
+
+        return 0;
+}
+
+/**
+ * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register
+ * @v: OCP_SYSCONFIG value to write
+ * @oh: struct omap_hwmod *
+ *
+ * Write @v into the module OCP_SYSCONFIG register, if it has one.  No
+ * return value.
+ */
+static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
+{
+        if (!oh->sysconfig) {
+                WARN(!oh->sysconfig, "omap_hwmod: %s: cannot write "
+                     "OCP_SYSCONFIG: not defined on hwmod\n", oh->name);
+                return;
+        }
+
+        /* XXX ensure module interface clock is up */
+
+        if (oh->_sysc_cache != v) {
+                oh->_sysc_cache = v;
+                omap_hwmod_writel(v, oh, oh->sysconfig->sysc_offs);
+        }
+}
+
+/**
+ * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v
+ * @oh: struct omap_hwmod *
+ * @standbymode: MIDLEMODE field bits
+ * @v: pointer to register contents to modify
+ *
+ * Update the master standby mode bits in @v to be @standbymode for
+ * the @oh hwmod.  Does not write to the hardware.  Returns -EINVAL
+ * upon error or 0 upon success.
+ */
+static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode,
+                                   u32 *v)
+{
+        if (!oh->sysconfig ||
+            !(oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE))
+                return -EINVAL;
+
+        *v &= ~SYSC_MIDLEMODE_MASK;
+        *v |= __ffs(standbymode) << SYSC_MIDLEMODE_SHIFT;
+
+        return 0;
+}
+
+/**
+ * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v
+ * @oh: struct omap_hwmod *
+ * @idlemode: SIDLEMODE field bits
+ * @v: pointer to register contents to modify
+ *
+ * Update the slave idle mode bits in @v to be @idlemode for the @oh
+ * hwmod.  Does not write to the hardware.  Returns -EINVAL upon error
+ * or 0 upon success.
+ */
+static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v)
+{
+        if (!oh->sysconfig ||
+            !(oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE))
+                return -EINVAL;
+
+        *v &= ~SYSC_SIDLEMODE_MASK;
+        *v |= __ffs(idlemode) << SYSC_SIDLEMODE_SHIFT;
+
+        return 0;
+}
+
+/**
+ * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v
+ * @oh: struct omap_hwmod *
+ * @clockact: CLOCKACTIVITY field bits
+ * @v: pointer to register contents to modify
+ *
+ * Update the clockactivity mode bits in @v to be @clockact for the
+ * @oh hwmod.  Used for additional powersaving on some modules.  Does
+ * not write to the hardware.  Returns -EINVAL upon error or 0 upon
+ * success.
+ */
+static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v)
+{
+        if (!oh->sysconfig ||
+            !(oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
+                return -EINVAL;
+
+        *v &= ~SYSC_CLOCKACTIVITY_MASK;
+        *v |= clockact << SYSC_CLOCKACTIVITY_SHIFT;
+
+        return 0;
+}
+
+/**
+ * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v
+ * @oh: struct omap_hwmod *
+ * @v: pointer to register contents to modify
+ *
+ * Set the SOFTRESET bit in @v for hwmod @oh.  Returns -EINVAL upon
+ * error or 0 upon success.
+ */
+static int _set_softreset(struct omap_hwmod *oh, u32 *v)
+{
+        if (!oh->sysconfig ||
+            !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET))
+                return -EINVAL;
+
+        *v |= SYSC_SOFTRESET_MASK;
+
+        return 0;
+}
+
+/**
+ * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
+ * @oh: struct omap_hwmod *
+ *
+ * Allow the hardware module @oh to send wakeups.  Returns -EINVAL
+ * upon error or 0 upon success.
+ */
+static int _enable_wakeup(struct omap_hwmod *oh)
+{
+        u32 v;
+
+        if (!oh->sysconfig ||
+            !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP))
+                return -EINVAL;
+
+        v = oh->_sysc_cache;
+        v |= SYSC_ENAWAKEUP_MASK;
+        _write_sysconfig(v, oh);
+
+        /* XXX test pwrdm_get_wken for this hwmod's subsystem */
+
+        oh->_int_flags |= _HWMOD_WAKEUP_ENABLED;
+
+        return 0;
+}
+
+/**
+ * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
+ * @oh: struct omap_hwmod *
+ *
+ * Prevent the hardware module @oh to send wakeups.  Returns -EINVAL
+ * upon error or 0 upon success.
+ */
+static int _disable_wakeup(struct omap_hwmod *oh)
+{
+        u32 v;
+
+        if (!oh->sysconfig ||
+            !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP))
+                return -EINVAL;
+
+        v = oh->_sysc_cache;
+        v &= ~SYSC_ENAWAKEUP_MASK;
+        _write_sysconfig(v, oh);
+
+        /* XXX test pwrdm_get_wken for this hwmod's subsystem */
+
+        oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED;
+
+        return 0;
+}
+
+/**
+ * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active
+ * @oh: struct omap_hwmod *
+ *
+ * Prevent the hardware module @oh from entering idle while the
+ * hardare module initiator @init_oh is active.  Useful when a module
+ * will be accessed by a particular initiator (e.g., if a module will
+ * be accessed by the IVA, there should be a sleepdep between the IVA
+ * initiator and the module).  Only applies to modules in smart-idle
+ * mode.  Returns -EINVAL upon error or passes along
+ * pwrdm_add_sleepdep() value upon success.
+ */
+static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
+{
+        if (!oh->_clk)
+                return -EINVAL;
+
+        return pwrdm_add_sleepdep(oh->_clk->clkdm->pwrdm.ptr,
+                                  init_oh->_clk->clkdm->pwrdm.ptr);
+}
+
+/**
+ * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active
+ * @oh: struct omap_hwmod *
+ *
+ * Allow the hardware module @oh to enter idle while the hardare
+ * module initiator @init_oh is active.  Useful when a module will not
+ * be accessed by a particular initiator (e.g., if a module will not
+ * be accessed by the IVA, there should be no sleepdep between the IVA
+ * initiator and the module).  Only applies to modules in smart-idle
+ * mode.  Returns -EINVAL upon error or passes along
+ * pwrdm_add_sleepdep() value upon success.
+ */
+static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
+{
+        if (!oh->_clk)
+                return -EINVAL;
+
+        return pwrdm_del_sleepdep(oh->_clk->clkdm->pwrdm.ptr,
+                                  init_oh->_clk->clkdm->pwrdm.ptr);
+}
+
+/**
+ * _init_main_clk - get a struct clk * for the the hwmod's main functional clk
+ * @oh: struct omap_hwmod *
+ *
+ * Called from _init_clocks().  Populates the @oh _clk (main
+ * functional clock pointer) if a main_clk is present.  Returns 0 on
+ * success or -EINVAL on error.
+ */
+static int _init_main_clk(struct omap_hwmod *oh)
+{
+        struct clk *c;
+        int ret = 0;
+
+        if (!oh->clkdev_con_id)
+                return 0;
+
+        c = clk_get_sys(oh->clkdev_dev_id, oh->clkdev_con_id);
+        WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get main_clk %s.%s\n",
+             oh->name, oh->clkdev_dev_id, oh->clkdev_con_id);
+        if (IS_ERR(c))
+                ret = -EINVAL;
+        oh->_clk = c;
+
+        return ret;
+}
+
+/**
+ * _init_interface_clk - get a struct clk * for the the hwmod's interface clks
+ * @oh: struct omap_hwmod *
+ *
+ * Called from _init_clocks().  Populates the @oh OCP slave interface
+ * clock pointers.  Returns 0 on success or -EINVAL on error.
+ */
+static int _init_interface_clks(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_ocp_if *os;
+        struct clk *c;
+        int i;
+        int ret = 0;
+
+        if (oh->slaves_cnt == 0)
+                return 0;
+
+        for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) {
+                if (!os->clkdev_con_id)
+                        continue;
+
+                c = clk_get_sys(os->clkdev_dev_id, os->clkdev_con_id);
+                WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get "
+                     "interface_clk %s.%s\n", oh->name,
+                     os->clkdev_dev_id, os->clkdev_con_id);
+                if (IS_ERR(c))
+                        ret = -EINVAL;
+                os->_clk = c;
+        }
+
+        return ret;
+}
+
+/**
+ * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks
+ * @oh: struct omap_hwmod *
+ *
+ * Called from _init_clocks().  Populates the @oh omap_hwmod_opt_clk
+ * clock pointers.  Returns 0 on success or -EINVAL on error.
+ */
+static int _init_opt_clks(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_opt_clk *oc;
+        struct clk *c;
+        int i;
+        int ret = 0;
+
+        for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
+                c = clk_get_sys(oc->clkdev_dev_id, oc->clkdev_con_id);
+                WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get opt_clk "
+                     "%s.%s\n", oh->name, oc->clkdev_dev_id,
+                     oc->clkdev_con_id);
+                if (IS_ERR(c))
+                        ret = -EINVAL;
+                oc->_clk = c;
+        }
+
+        return ret;
+}
+
+/**
+ * _enable_clocks - enable hwmod main clock and interface clocks
+ * @oh: struct omap_hwmod *
+ *
+ * Enables all clocks necessary for register reads and writes to succeed
+ * on the hwmod @oh.  Returns 0.
+ */
+static int _enable_clocks(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_ocp_if *os;
+        int i;
+
+        pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
+
+        if (oh->_clk && !IS_ERR(oh->_clk))
+                clk_enable(oh->_clk);
+
+        if (oh->slaves_cnt > 0) {
+                for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) {
+                        struct clk *c = os->_clk;
+
+                        if (c && !IS_ERR(c) && (os->flags & OCPIF_SWSUP_IDLE))
+                                clk_enable(c);
+                }
+        }
+
+        /* The opt clocks are controlled by the device driver. */
+
+        return 0;
+}
+
+/**
+ * _disable_clocks - disable hwmod main clock and interface clocks
+ * @oh: struct omap_hwmod *
+ *
+ * Disables the hwmod @oh main functional and interface clocks.  Returns 0.
+ */
+static int _disable_clocks(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_ocp_if *os;
+        int i;
+
+        pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
+
+        if (oh->_clk && !IS_ERR(oh->_clk))
+                clk_disable(oh->_clk);
+
+        if (oh->slaves_cnt > 0) {
+                for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) {
+                        struct clk *c = os->_clk;
+
+                        if (c && !IS_ERR(c) && (os->flags & OCPIF_SWSUP_IDLE))
+                                clk_disable(c);
+                }
+        }
+
+        /* The opt clocks are controlled by the device driver. */
+
+        return 0;
+}
+
+/**
+ * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
+ * @oh: struct omap_hwmod *
+ *
+ * Returns the array index of the OCP slave port that the MPU
+ * addresses the device on, or -EINVAL upon error or not found.
+ */
+static int _find_mpu_port_index(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_ocp_if *os;
+        int i;
+        int found = 0;
+
+        if (!oh || oh->slaves_cnt == 0)
+                return -EINVAL;
+
+        for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) {
+                if (os->user & OCP_USER_MPU) {
+                        found = 1;
+                        break;
+                }
+        }
+
+        if (found)
+                pr_debug("omap_hwmod: %s: MPU OCP slave port ID  %d\n",
+                         oh->name, i);
+        else
+                pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n",
+                         oh->name);
+
+        return (found) ? i : -EINVAL;
+}
+
+/**
+ * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU
+ * @oh: struct omap_hwmod *
+ *
+ * Return the virtual address of the base of the register target of
+ * device @oh, or NULL on error.
+ */
+static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
+{
+        struct omap_hwmod_ocp_if *os;
+        struct omap_hwmod_addr_space *mem;
+        int i;
+        int found = 0;
+
+        if (!oh || oh->slaves_cnt == 0)
+                return NULL;
+
+        os = *oh->slaves + index;
+
+        for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) {
+                if (mem->flags & ADDR_TYPE_RT) {
+                        found = 1;
+                        break;
+                }
+        }
+
+        /* XXX use ioremap() instead? */
+
+        if (found)
+                pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
+                         oh->name, OMAP2_IO_ADDRESS(mem->pa_start));
+        else
+                pr_debug("omap_hwmod: %s: no MPU register target found\n",
+                         oh->name);
+
+        return (found) ? OMAP2_IO_ADDRESS(mem->pa_start) : NULL;
+}
+
+/**
+ * _sysc_enable - try to bring a module out of idle via OCP_SYSCONFIG
+ * @oh: struct omap_hwmod *
+ *
+ * If module is marked as SWSUP_SIDLE, force the module out of slave
+ * idle; otherwise, configure it for smart-idle.  If module is marked
+ * as SWSUP_MSUSPEND, force the module out of master standby;
+ * otherwise, configure it for smart-standby.  No return value.
+ */
+static void _sysc_enable(struct omap_hwmod *oh)
+{
+        u8 idlemode;
+        u32 v;
+
+        if (!oh->sysconfig)
+                return;
+
+        v = oh->_sysc_cache;
+
+        if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE) {
+                idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
+                        HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
+                _set_slave_idlemode(oh, idlemode, &v);
+        }
+
+        if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) {
+                idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
+                        HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
+                _set_master_standbymode(oh, idlemode, &v);
+        }
+
+        /* XXX OCP AUTOIDLE bit? */
+
+        if (oh->flags & HWMOD_SET_DEFAULT_CLOCKACT &&
+            oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY)
+                _set_clockactivity(oh, oh->sysconfig->clockact, &v);
+
+        _write_sysconfig(v, oh);
+}
+
+/**
+ * _sysc_idle - try to put a module into idle via OCP_SYSCONFIG
+ * @oh: struct omap_hwmod *
+ *
+ * If module is marked as SWSUP_SIDLE, force the module into slave
+ * idle; otherwise, configure it for smart-idle.  If module is marked
+ * as SWSUP_MSUSPEND, force the module into master standby; otherwise,
+ * configure it for smart-standby.  No return value.
+ */
+static void _sysc_idle(struct omap_hwmod *oh)
+{
+        u8 idlemode;
+        u32 v;
+
+        if (!oh->sysconfig)
+                return;
+
+        v = oh->_sysc_cache;
+
+        if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE) {
+                idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
+                        HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
+                _set_slave_idlemode(oh, idlemode, &v);
+        }
+
+        if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) {
+                idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
+                        HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
+                _set_master_standbymode(oh, idlemode, &v);
+        }
+
+        _write_sysconfig(v, oh);
+}
+
+/**
+ * _sysc_shutdown - force a module into idle via OCP_SYSCONFIG
+ * @oh: struct omap_hwmod *
+ *
+ * Force the module into slave idle and master suspend. No return
+ * value.
+ */
+static void _sysc_shutdown(struct omap_hwmod *oh)
+{
+        u32 v;
+
+        if (!oh->sysconfig)
+                return;
+
+        v = oh->_sysc_cache;
+
+        if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE)
+                _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v);
+
+        if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE)
+                _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v);
+
+        /* XXX clear OCP AUTOIDLE bit? */
+
+        _write_sysconfig(v, oh);
+}
+
+/**
+ * _lookup - find an omap_hwmod by name
+ * @name: find an omap_hwmod by name
+ *
+ * Return a pointer to an omap_hwmod by name, or NULL if not found.
+ * Caller must hold omap_hwmod_mutex.
+ */
+static struct omap_hwmod *_lookup(const char *name)
+{
+        struct omap_hwmod *oh, *temp_oh;
+
+        oh = NULL;
+
+        list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
+                if (!strcmp(name, temp_oh->name)) {
+                        oh = temp_oh;
+                        break;
+                }
+        }
+
+        return oh;
+}
+
+/**
+ * _init_clocks - clk_get() all clocks associated with this hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Called by omap_hwmod_late_init() (after omap2_clk_init()).
+ * Resolves all clock names embedded in the hwmod.  Must be called
+ * with omap_hwmod_mutex held.  Returns -EINVAL if the omap_hwmod
+ * has not yet been registered or if the clocks have already been
+ * initialized, 0 on success, or a non-zero error on failure.
+ */
+static int _init_clocks(struct omap_hwmod *oh)
+{
+        int ret = 0;
+
+        if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED))
+                return -EINVAL;
+
+        pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
+
+        ret |= _init_main_clk(oh);
+        ret |= _init_interface_clks(oh);
+        ret |= _init_opt_clks(oh);
+
+        oh->_state = _HWMOD_STATE_CLKS_INITED;
+
+        return ret;
+}
+
+/**
+ * _wait_target_ready - wait for a module to leave slave idle
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to leave slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully leaves
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm_wait_module_ready() function.
+ */
+static int _wait_target_ready(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_ocp_if *os;
+        int ret;
+
+        if (!oh)
+                return -EINVAL;
+
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+                return 0;
+
+        os = *oh->slaves + oh->_mpu_port_index;
+
+        if (!(os->flags & OCPIF_HAS_IDLEST))
+                return 0;
+
+        /* XXX check module SIDLEMODE */
+
+        /* XXX check clock enable states */
+
+        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
+                                                 oh->prcm.omap2.idlest_reg_id,
+                                                 oh->prcm.omap2.idlest_idle_bit);
+#if 0
+        } else if (cpu_is_omap44xx()) {
+                ret = omap4_cm_wait_module_ready(oh->prcm.omap4.module_offs,
+                                                 oh->prcm.omap4.device_offs);
+#endif
+        } else {
+                BUG();
+        };
+
+        return ret;
+}
+
+/**
+ * _reset - reset an omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit.  hwmod must be
+ * enabled for this to work.  Must be called with omap_hwmod_mutex
+ * held.  Returns -EINVAL if the hwmod cannot be reset this way or if
+ * the hwmod is in the wrong state, -ETIMEDOUT if the module did not
+ * reset in time, or 0 upon success.
+ */
+static int _reset(struct omap_hwmod *oh)
+{
+        u32 r, v;
+        int c;
+
+        if (!oh->sysconfig ||
+            !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET) ||
+            (oh->sysconfig->sysc_flags & SYSS_MISSING))
+                return -EINVAL;
+
+        /* clocks must be on for this operation */
+        if (oh->_state != _HWMOD_STATE_ENABLED) {
+                WARN(1, "omap_hwmod: %s: reset can only be entered from "
+                     "enabled state\n", oh->name);
+                return -EINVAL;
+        }
+
+        pr_debug("omap_hwmod: %s: resetting\n", oh->name);
+
+        v = oh->_sysc_cache;
+        r = _set_softreset(oh, &v);
+        if (r)
+                return r;
+        _write_sysconfig(v, oh);
+
+        c = 0;
+        while (c < MAX_MODULE_RESET_WAIT &&
+               !(omap_hwmod_readl(oh, oh->sysconfig->syss_offs) &
+                 SYSS_RESETDONE_MASK)) {
+                udelay(1);
+                c++;
+        }
+
+        if (c == MAX_MODULE_RESET_WAIT)
+                WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n",
+                     oh->name, MAX_MODULE_RESET_WAIT);
+        else
+                pr_debug("omap_hwmod: %s: reset in %d usec\n", oh->name, c);
+
+        /*
+         * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from
+         * _wait_target_ready() or _reset()
+         */
+
+        return (c == MAX_MODULE_RESET_WAIT) ? -ETIMEDOUT : 0;
+}
+
+/**
+ * _enable - enable an omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Enables an omap_hwmod @oh such that the MPU can access the hwmod's
+ * register target.  Must be called with omap_hwmod_mutex held.
+ * Returns -EINVAL if the hwmod is in the wrong state or passes along
+ * the return value of _wait_target_ready().
+ */
+static int _enable(struct omap_hwmod *oh)
+{
+        int r;
+
+        if (oh->_state != _HWMOD_STATE_INITIALIZED &&
+            oh->_state != _HWMOD_STATE_IDLE &&
+            oh->_state != _HWMOD_STATE_DISABLED) {
+                WARN(1, "omap_hwmod: %s: enabled state can only be entered "
+                     "from initialized, idle, or disabled state\n", oh->name);
+                return -EINVAL;
+        }
+
+        pr_debug("omap_hwmod: %s: enabling\n", oh->name);
+
+        /* XXX mux balls */
+
+        _add_initiator_dep(oh, mpu_oh);
+        _enable_clocks(oh);
+
+        if (oh->sysconfig) {
+                if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
+                        _update_sysc_cache(oh);
+                _sysc_enable(oh);
+        }
+
+        r = _wait_target_ready(oh);
+        if (!r)
+                oh->_state = _HWMOD_STATE_ENABLED;
+
+        return r;
+}
+
+/**
+ * _idle - idle an omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Idles an omap_hwmod @oh.  This should be called once the hwmod has
+ * no further work.  Returns -EINVAL if the hwmod is in the wrong
+ * state or returns 0.
+ */
+static int _idle(struct omap_hwmod *oh)
+{
+        if (oh->_state != _HWMOD_STATE_ENABLED) {
+                WARN(1, "omap_hwmod: %s: idle state can only be entered from "
+                     "enabled state\n", oh->name);
+                return -EINVAL;
+        }
+
+        pr_debug("omap_hwmod: %s: idling\n", oh->name);
+
+        if (oh->sysconfig)
+                _sysc_idle(oh);
+        _del_initiator_dep(oh, mpu_oh);
+        _disable_clocks(oh);
+
+        oh->_state = _HWMOD_STATE_IDLE;
+
+        return 0;
+}
+
+/**
+ * _shutdown - shutdown an omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Shut down an omap_hwmod @oh.  This should be called when the driver
+ * used for the hwmod is removed or unloaded or if the driver is not
+ * used by the system.  Returns -EINVAL if the hwmod is in the wrong
+ * state or returns 0.
+ */
+static int _shutdown(struct omap_hwmod *oh)
+{
+        if (oh->_state != _HWMOD_STATE_IDLE &&
+            oh->_state != _HWMOD_STATE_ENABLED) {
+                WARN(1, "omap_hwmod: %s: disabled state can only be entered "
+                     "from idle, or enabled state\n", oh->name);
+                return -EINVAL;
+        }
+
+        pr_debug("omap_hwmod: %s: disabling\n", oh->name);
+
+        if (oh->sysconfig)
+                _sysc_shutdown(oh);
+        _del_initiator_dep(oh, mpu_oh);
+        /* XXX what about the other system initiators here? DMA, tesla, d2d */
+        _disable_clocks(oh);
+        /* XXX Should this code also force-disable the optional clocks? */
+
+        /* XXX mux any associated balls to safe mode */
+
+        oh->_state = _HWMOD_STATE_DISABLED;
+
+        return 0;
+}
+
+/**
+ * _write_clockact_lock - set the module's clockactivity bits
+ * @oh: struct omap_hwmod *
+ * @clockact: CLOCKACTIVITY field bits
+ *
+ * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
+ * OCP_SYSCONFIG register.  Returns -EINVAL if the hwmod is in the
+ * wrong state or returns 0.
+ */
+static int _write_clockact_lock(struct omap_hwmod *oh, u8 clockact)
+{
+        u32 v;
+
+        if (!oh->sysconfig ||
+            !(oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
+                return -EINVAL;
+
+        mutex_lock(&omap_hwmod_mutex);
+        v = oh->_sysc_cache;
+        _set_clockactivity(oh, clockact, &v);
+        _write_sysconfig(v, oh);
+        mutex_unlock(&omap_hwmod_mutex);
+
+        return 0;
+}
+
+
+/**
+ * _setup - do initial configuration of omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
+ * OCP_SYSCONFIG register.  Must be called with omap_hwmod_mutex
+ * held.  Returns -EINVAL if the hwmod is in the wrong state or returns
+ * 0.
+ */
+static int _setup(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_ocp_if *os;
+        int i;
+
+        if (!oh)
+                return -EINVAL;
+
+        /* Set iclk autoidle mode */
+        if (oh->slaves_cnt > 0) {
+                for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) {
+                        struct clk *c = os->_clk;
+
+                        if (!c || IS_ERR(c))
+                                continue;
+
+                        if (os->flags & OCPIF_SWSUP_IDLE) {
+                                /* XXX omap_iclk_deny_idle(c); */
+                        } else {
+                                /* XXX omap_iclk_allow_idle(c); */
+                                clk_enable(c);
+                        }
+                }
+        }
+
+        oh->_state = _HWMOD_STATE_INITIALIZED;
+
+        _enable(oh);
+
+        if (!(oh->flags & HWMOD_INIT_NO_RESET))
+                _reset(oh);
+
+        /* XXX OCP AUTOIDLE bit? */
+        /* XXX OCP ENAWAKEUP bit? */
+
+        if (!(oh->flags & HWMOD_INIT_NO_IDLE))
+                _idle(oh);
+
+        return 0;
+}
+
+
+
+/* Public functions */
+
+u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs)
+{
+        return __raw_readl(oh->_rt_va + reg_offs);
+}
+
+void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs)
+{
+        __raw_writel(v, oh->_rt_va + reg_offs);
+}
+
+/**
+ * omap_hwmod_register - register a struct omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Registers the omap_hwmod @oh.  Returns -EEXIST if an omap_hwmod already
+ * has been registered by the same name; -EINVAL if the omap_hwmod is in the
+ * wrong state, or 0 on success.
+ *
+ * XXX The data should be copied into bootmem, so the original data
+ * should be marked __initdata and freed after init.  This would allow
+ * unneeded omap_hwmods to be freed on multi-OMAP configurations.  Note
+ * that the copy process would be relatively complex due to the large number
+ * of substructures.
+ */
+int omap_hwmod_register(struct omap_hwmod *oh)
+{
+        int ret, ms_id;
+
+        if (!oh || (oh->_state != _HWMOD_STATE_UNKNOWN))
+                return -EINVAL;
+
+        mutex_lock(&omap_hwmod_mutex);
+
+        pr_debug("omap_hwmod: %s: registering\n", oh->name);
+
+        if (_lookup(oh->name)) {
+                ret = -EEXIST;
+                goto ohr_unlock;
+        }
+
+        ms_id = _find_mpu_port_index(oh);
+        if (!IS_ERR_VALUE(ms_id)) {
+                oh->_mpu_port_index = ms_id;
+                oh->_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
+        } else {
+                oh->_int_flags |= _HWMOD_NO_MPU_PORT;
+        }
+
+        list_add_tail(&oh->node, &omap_hwmod_list);
+
+        oh->_state = _HWMOD_STATE_REGISTERED;
+
+        ret = 0;
+
+ohr_unlock:
+        mutex_unlock(&omap_hwmod_mutex);
+        return ret;
+}
+
+/**
+ * omap_hwmod_lookup - look up a registered omap_hwmod by name
+ * @name: name of the omap_hwmod to look up
+ *
+ * Given a @name of an omap_hwmod, return a pointer to the registered
+ * struct omap_hwmod *, or NULL upon error.
+ */
+struct omap_hwmod *omap_hwmod_lookup(const char *name)
+{
+        struct omap_hwmod *oh;
+
+        if (!name)
+                return NULL;
+
+        mutex_lock(&omap_hwmod_mutex);
+        oh = _lookup(name);
+        mutex_unlock(&omap_hwmod_mutex);
+
+        return oh;
+}
+
+/**
+ * omap_hwmod_for_each - call function for each registered omap_hwmod
+ * @fn: pointer to a callback function
+ *
+ * Call @fn for each registered omap_hwmod, passing @data to each
+ * function.  @fn must return 0 for success or any other value for
+ * failure.  If @fn returns non-zero, the iteration across omap_hwmods
+ * will stop and the non-zero return value will be passed to the
+ * caller of omap_hwmod_for_each().  @fn is called with
+ * omap_hwmod_for_each() held.
+ */
+int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh))
+{
+        struct omap_hwmod *temp_oh;
+        int ret;
+
+        if (!fn)
+                return -EINVAL;
+
+        mutex_lock(&omap_hwmod_mutex);
+        list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
+                ret = (*fn)(temp_oh);
+                if (ret)
+                        break;
+        }
+        mutex_unlock(&omap_hwmod_mutex);
+
+        return ret;
+}
+
+
+/**
+ * omap_hwmod_init - init omap_hwmod code and register hwmods
+ * @ohs: pointer to an array of omap_hwmods to register
+ *
+ * Intended to be called early in boot before the clock framework is
+ * initialized.  If @ohs is not null, will register all omap_hwmods
+ * listed in @ohs that are valid for this chip.  Returns -EINVAL if
+ * omap_hwmod_init() has already been called or 0 otherwise.
+ */
+int omap_hwmod_init(struct omap_hwmod **ohs)
+{
+        struct omap_hwmod *oh;
+        int r;
+
+        if (inited)
+                return -EINVAL;
+
+        inited = 1;
+
+        if (!ohs)
+                return 0;
+
+        oh = *ohs;
+        while (oh) {
+                if (omap_chip_is(oh->omap_chip)) {
+                        r = omap_hwmod_register(oh);
+                        WARN(r, "omap_hwmod: %s: omap_hwmod_register returned "
+                             "%d\n", oh->name, r);
+                }
+                oh = *++ohs;
+        }
+
+        return 0;
+}
+
+/**
+ * omap_hwmod_late_init - do some post-clock framework initialization
+ *
+ * Must be called after omap2_clk_init().  Resolves the struct clk names
+ * to struct clk pointers for each registered omap_hwmod.  Also calls
+ * _setup() on each hwmod.  Returns 0.
+ */
+int omap_hwmod_late_init(void)
+{
+        int r;
+
+        /* XXX check return value */
+        r = omap_hwmod_for_each(_init_clocks);
+        WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n");
+
+        mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME);
+        WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n",
+             MPU_INITIATOR_NAME);
+
+        omap_hwmod_for_each(_setup);
+
+        return 0;
+}
+
+/**
+ * omap_hwmod_unregister - unregister an omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Unregisters a previously-registered omap_hwmod @oh.  There's probably
+ * no use case for this, so it is likely to be removed in a later version.
+ *
+ * XXX Free all of the bootmem-allocated structures here when that is
+ * implemented.  Make it clear that core code is the only code that is
+ * expected to unregister modules.
+ */
+int omap_hwmod_unregister(struct omap_hwmod *oh)
+{
+        if (!oh)
+                return -EINVAL;
+
+        pr_debug("omap_hwmod: %s: unregistering\n", oh->name);
+
+        mutex_lock(&omap_hwmod_mutex);
+        list_del(&oh->node);
+        mutex_unlock(&omap_hwmod_mutex);
+
+        return 0;
+}
+
+/**
+ * omap_hwmod_enable - enable an omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Enable an omap_hwomd @oh.  Intended to be called by omap_device_enable().
+ * Returns -EINVAL on error or passes along the return value from _enable().
+ */
+int omap_hwmod_enable(struct omap_hwmod *oh)
+{
+        int r;
+
+        if (!oh)
+                return -EINVAL;
+
+        mutex_lock(&omap_hwmod_mutex);
+        r = _enable(oh);
+        mutex_unlock(&omap_hwmod_mutex);
+
+        return r;
+}
+
+/**
+ * omap_hwmod_idle - idle an omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Idle an omap_hwomd @oh.  Intended to be called by omap_device_idle().
+ * Returns -EINVAL on error or passes along the return value from _idle().
+ */
+int omap_hwmod_idle(struct omap_hwmod *oh)
+{
+        if (!oh)
+                return -EINVAL;
+
+        mutex_lock(&omap_hwmod_mutex);
+        _idle(oh);
+        mutex_unlock(&omap_hwmod_mutex);
+
+        return 0;
+}
+
+/**
+ * omap_hwmod_shutdown - shutdown an omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Shutdown an omap_hwomd @oh.  Intended to be called by
+ * omap_device_shutdown().  Returns -EINVAL on error or passes along
+ * the return value from _shutdown().
+ */
+int omap_hwmod_shutdown(struct omap_hwmod *oh)
+{
+        if (!oh)
+                return -EINVAL;
+
+        mutex_lock(&omap_hwmod_mutex);
+        _shutdown(oh);
+        mutex_unlock(&omap_hwmod_mutex);
+
+        return 0;
+}
+
+/**
+ * omap_hwmod_enable_clocks - enable main_clk, all interface clocks
+ * @oh: struct omap_hwmod *oh
+ *
+ * Intended to be called by the omap_device code.
+ */
+int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
+{
+        mutex_lock(&omap_hwmod_mutex);
+        _enable_clocks(oh);
+        mutex_unlock(&omap_hwmod_mutex);
+
+        return 0;
+}
+
+/**
+ * omap_hwmod_disable_clocks - disable main_clk, all interface clocks
+ * @oh: struct omap_hwmod *oh
+ *
+ * Intended to be called by the omap_device code.
+ */
+int omap_hwmod_disable_clocks(struct omap_hwmod *oh)
+{
+        mutex_lock(&omap_hwmod_mutex);
+        _disable_clocks(oh);
+        mutex_unlock(&omap_hwmod_mutex);
+
+        return 0;
+}
+
+/**
+ * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete
+ * @oh: struct omap_hwmod *oh
+ *
+ * Intended to be called by drivers and core code when all posted
+ * writes to a device must complete before continuing further
+ * execution (for example, after clearing some device IRQSTATUS
+ * register bits)
+ *
+ * XXX what about targets with multiple OCP threads?
+ */
+void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
+{
+        BUG_ON(!oh);
+
+        if (!oh->sysconfig || !oh->sysconfig->sysc_flags) {
+                WARN(1, "omap_device: %s: OCP barrier impossible due to "
+                      "device configuration\n", oh->name);
+                return;
+        }
+
+        /*
+         * Forces posted writes to complete on the OCP thread handling
+         * register writes
+         */
+        omap_hwmod_readl(oh, oh->sysconfig->sysc_offs);
+}
+
+/**
+ * omap_hwmod_reset - reset the hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Under some conditions, a driver may wish to reset the entire device.
+ * Called from omap_device code.  Returns -EINVAL on error or passes along
+ * the return value from _reset()/_enable().
+ */
+int omap_hwmod_reset(struct omap_hwmod *oh)
+{
+        int r;
+
+        if (!oh || !(oh->_state & _HWMOD_STATE_ENABLED))
+                return -EINVAL;
+
+        mutex_lock(&omap_hwmod_mutex);
+        r = _reset(oh);
+        if (!r)
+                r = _enable(oh);
+        mutex_unlock(&omap_hwmod_mutex);
+
+        return r;
+}
+
+/**
+ * omap_hwmod_count_resources - count number of struct resources needed by hwmod
+ * @oh: struct omap_hwmod *
+ * @res: pointer to the first element of an array of struct resource to fill
+ *
+ * Count the number of struct resource array elements necessary to
+ * contain omap_hwmod @oh resources.  Intended to be called by code
+ * that registers omap_devices.  Intended to be used to determine the
+ * size of a dynamically-allocated struct resource array, before
+ * calling omap_hwmod_fill_resources().  Returns the number of struct
+ * resource array elements needed.
+ *
+ * XXX This code is not optimized.  It could attempt to merge adjacent
+ * resource IDs.
+ *
+ */
+int omap_hwmod_count_resources(struct omap_hwmod *oh)
+{
+        int ret, i;
+
+        ret = oh->mpu_irqs_cnt + oh->sdma_chs_cnt;
+
+        for (i = 0; i < oh->slaves_cnt; i++)
+                ret += (*oh->slaves + i)->addr_cnt;
+
+        return ret;
+}
+
+/**
+ * omap_hwmod_fill_resources - fill struct resource array with hwmod data
+ * @oh: struct omap_hwmod *
+ * @res: pointer to the first element of an array of struct resource to fill
+ *
+ * Fill the struct resource array @res with resource data from the
+ * omap_hwmod @oh.  Intended to be called by code that registers
+ * omap_devices.  See also omap_hwmod_count_resources().  Returns the
+ * number of array elements filled.
+ */
+int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
+{
+        int i, j;
+        int r = 0;
+
+        /* For each IRQ, DMA, memory area, fill in array.*/
+
+        for (i = 0; i < oh->mpu_irqs_cnt; i++) {
+                (res + r)->start = *(oh->mpu_irqs + i);
+                (res + r)->end = *(oh->mpu_irqs + i);
+                (res + r)->flags = IORESOURCE_IRQ;
+                r++;
+        }
+
+        for (i = 0; i < oh->sdma_chs_cnt; i++) {
+                (res + r)->name = (oh->sdma_chs + i)->name;
+                (res + r)->start = (oh->sdma_chs + i)->dma_ch;
+                (res + r)->end = (oh->sdma_chs + i)->dma_ch;
+                (res + r)->flags = IORESOURCE_DMA;
+                r++;
+        }
+
+        for (i = 0; i < oh->slaves_cnt; i++) {
+                struct omap_hwmod_ocp_if *os;
+
+                os = *oh->slaves + i;
+
+                for (j = 0; j < os->addr_cnt; j++) {
+                        (res + r)->start = (os->addr + j)->pa_start;
+                        (res + r)->end = (os->addr + j)->pa_end;
+                        (res + r)->flags = IORESOURCE_MEM;
+                        r++;
+                }
+        }
+
+        return r;
+}
+
+/**
+ * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain
+ * @oh: struct omap_hwmod *
+ *
+ * Return the powerdomain pointer associated with the OMAP module
+ * @oh's main clock.  If @oh does not have a main clk, return the
+ * powerdomain associated with the interface clock associated with the
+ * module's MPU port. (XXX Perhaps this should use the SDMA port
+ * instead?)  Returns NULL on error, or a struct powerdomain * on
+ * success.
+ */
+struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
+{
+        struct clk *c;
+
+        if (!oh)
+                return NULL;
+
+        if (oh->_clk) {
+                c = oh->_clk;
+        } else {
+                if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+                        return NULL;
+                c = oh->slaves[oh->_mpu_port_index]->_clk;
+        }
+
+        return c->clkdm->pwrdm.ptr;
+
+}
+
+/**
+ * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh
+ * @oh: struct omap_hwmod *
+ * @init_oh: struct omap_hwmod * (initiator)
+ *
+ * Add a sleep dependency between the initiator @init_oh and @oh.
+ * Intended to be called by DSP/Bridge code via platform_data for the
+ * DSP case; and by the DMA code in the sDMA case.  DMA code, *Bridge
+ * code needs to add/del initiator dependencies dynamically
+ * before/after accessing a device.  Returns the return value from
+ * _add_initiator_dep().
+ *
+ * XXX Keep a usecount in the clockdomain code
+ */
+int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
+                                 struct omap_hwmod *init_oh)
+{
+        return _add_initiator_dep(oh, init_oh);
+}
+
+/*
+ * XXX what about functions for drivers to save/restore ocp_sysconfig
+ * for context save/restore operations?
+ */
+
+/**
+ * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh
+ * @oh: struct omap_hwmod *
+ * @init_oh: struct omap_hwmod * (initiator)
+ *
+ * Remove a sleep dependency between the initiator @init_oh and @oh.
+ * Intended to be called by DSP/Bridge code via platform_data for the
+ * DSP case; and by the DMA code in the sDMA case.  DMA code, *Bridge
+ * code needs to add/del initiator dependencies dynamically
+ * before/after accessing a device.  Returns the return value from
+ * _del_initiator_dep().
+ *
+ * XXX Keep a usecount in the clockdomain code
+ */
+int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
+                                 struct omap_hwmod *init_oh)
+{
+        return _del_initiator_dep(oh, init_oh);
+}
+
+/**
+ * omap_hwmod_set_clockact_none - set clockactivity test to BOTH
+ * @oh: struct omap_hwmod *
+ *
+ * On some modules, this function can affect the wakeup latency vs.
+ * power consumption balance.  Intended to be called by the
+ * omap_device layer.  Passes along the return value from
+ * _write_clockact_lock().
+ */
+int omap_hwmod_set_clockact_both(struct omap_hwmod *oh)
+{
+        return _write_clockact_lock(oh, CLOCKACT_TEST_BOTH);
+}
+
+/**
+ * omap_hwmod_set_clockact_none - set clockactivity test to MAIN
+ * @oh: struct omap_hwmod *
+ *
+ * On some modules, this function can affect the wakeup latency vs.
+ * power consumption balance.  Intended to be called by the
+ * omap_device layer.  Passes along the return value from
+ * _write_clockact_lock().
+ */
+int omap_hwmod_set_clockact_main(struct omap_hwmod *oh)
+{
+        return _write_clockact_lock(oh, CLOCKACT_TEST_MAIN);
+}
+
+/**
+ * omap_hwmod_set_clockact_none - set clockactivity test to ICLK
+ * @oh: struct omap_hwmod *
+ *
+ * On some modules, this function can affect the wakeup latency vs.
+ * power consumption balance.  Intended to be called by the
+ * omap_device layer.  Passes along the return value from
+ * _write_clockact_lock().
+ */
+int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh)
+{
+        return _write_clockact_lock(oh, CLOCKACT_TEST_ICLK);
+}
+
+/**
+ * omap_hwmod_set_clockact_none - set clockactivity test to NONE
+ * @oh: struct omap_hwmod *
+ *
+ * On some modules, this function can affect the wakeup latency vs.
+ * power consumption balance.  Intended to be called by the
+ * omap_device layer.  Passes along the return value from
+ * _write_clockact_lock().
+ */
+int omap_hwmod_set_clockact_none(struct omap_hwmod *oh)
+{
+        return _write_clockact_lock(oh, CLOCKACT_TEST_NONE);
+}
+
+/**
+ * omap_hwmod_enable_wakeup - allow device to wake up the system
+ * @oh: struct omap_hwmod *
+ *
+ * Sets the module OCP socket ENAWAKEUP bit to allow the module to
+ * send wakeups to the PRCM.  Eventually this should sets PRCM wakeup
+ * registers to cause the PRCM to receive wakeup events from the
+ * module.  Does not set any wakeup routing registers beyond this
+ * point - if the module is to wake up any other module or subsystem,
+ * that must be set separately.  Called by omap_device code.  Returns
+ * -EINVAL on error or 0 upon success.
+ */
+int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
+{
+        if (!oh->sysconfig ||
+            !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP))
+                return -EINVAL;
+
+        mutex_lock(&omap_hwmod_mutex);
+        _enable_wakeup(oh);
+        mutex_unlock(&omap_hwmod_mutex);
+
+        return 0;
+}
+
+/**
+ * omap_hwmod_disable_wakeup - prevent device from waking the system
+ * @oh: struct omap_hwmod *
+ *
+ * Clears the module OCP socket ENAWAKEUP bit to prevent the module
+ * from sending wakeups to the PRCM.  Eventually this should clear
+ * PRCM wakeup registers to cause the PRCM to ignore wakeup events
+ * from the module.  Does not set any wakeup routing registers beyond
+ * this point - if the module is to wake up any other module or
+ * subsystem, that must be set separately.  Called by omap_device
+ * code.  Returns -EINVAL on error or 0 upon success.
+ */
+int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
+{
+        if (!oh->sysconfig ||
+            !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP))
+                return -EINVAL;
+
+        mutex_lock(&omap_hwmod_mutex);
+        _disable_wakeup(oh);
+        mutex_unlock(&omap_hwmod_mutex);
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420.h b/arch/arm/mach-omap2/omap_hwmod_2420.h
new file mode 100644
index 000000000000..767e4965ac4e
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2420.h
@@ -0,0 +1,141 @@
+/*
+ * omap_hwmod_2420.h - hardware modules present on the OMAP2420 chips
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX handle crossbar/shared link difference for L3?
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2420_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2420_H
+
+#ifdef CONFIG_ARCH_OMAP2420
+
+#include <mach/omap_hwmod.h>
+#include <mach/irqs.h>
+#include <mach/cpu.h>
+#include <mach/dma.h>
+
+#include "prm-regbits-24xx.h"
+
+static struct omap_hwmod omap2420_mpu_hwmod;
+static struct omap_hwmod omap2420_l3_hwmod;
+static struct omap_hwmod omap2420_l4_core_hwmod;
+
+/* L3 -> L4_CORE interface */
+static struct omap_hwmod_ocp_if omap2420_l3__l4_core = {
+        .master = &omap2420_l3_hwmod,
+        .slave  = &omap2420_l4_core_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* MPU -> L3 interface */
+static struct omap_hwmod_ocp_if omap2420_mpu__l3 = {
+        .master = &omap2420_mpu_hwmod,
+        .slave  = &omap2420_l3_hwmod,
+        .user   = OCP_USER_MPU,
+};
+
+/* Slave interfaces on the L3 interconnect */
+static struct omap_hwmod_ocp_if *omap2420_l3_slaves[] = {
+        &omap2420_mpu__l3,
+};
+
+/* Master interfaces on the L3 interconnect */
+static struct omap_hwmod_ocp_if *omap2420_l3_masters[] = {
+        &omap2420_l3__l4_core,
+};
+
+/* L3 */
+static struct omap_hwmod omap2420_l3_hwmod = {
+        .name           = "l3_hwmod",
+        .masters        = omap2420_l3_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2420_l3_masters),
+        .slaves         = omap2420_l3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_l3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+static struct omap_hwmod omap2420_l4_wkup_hwmod;
+
+/* L4_CORE -> L4_WKUP interface */
+static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
+        .master = &omap2420_l4_core_hwmod,
+        .slave  = &omap2420_l4_wkup_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* Slave interfaces on the L4_CORE interconnect */
+static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
+        &omap2420_l3__l4_core,
+};
+
+/* Master interfaces on the L4_CORE interconnect */
+static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
+        &omap2420_l4_core__l4_wkup,
+};
+
+/* L4 CORE */
+static struct omap_hwmod omap2420_l4_core_hwmod = {
+        .name           = "l4_core_hwmod",
+        .masters        = omap2420_l4_core_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
+        .slaves         = omap2420_l4_core_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* Slave interfaces on the L4_WKUP interconnect */
+static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
+        &omap2420_l4_core__l4_wkup,
+};
+
+/* Master interfaces on the L4_WKUP interconnect */
+static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
+};
+
+/* L4 WKUP */
+static struct omap_hwmod omap2420_l4_wkup_hwmod = {
+        .name           = "l4_wkup_hwmod",
+        .masters        = omap2420_l4_wkup_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
+        .slaves         = omap2420_l4_wkup_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* Master interfaces on the MPU device */
+static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
+        &omap2420_mpu__l3,
+};
+
+/* MPU */
+static struct omap_hwmod omap2420_mpu_hwmod = {
+        .name           = "mpu_hwmod",
+        .clkdev_dev_id  = NULL,
+        .clkdev_con_id  = "mpu_ck",
+        .masters        = omap2420_mpu_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+static __initdata struct omap_hwmod *omap2420_hwmods[] = {
+        &omap2420_l3_hwmod,
+        &omap2420_l4_core_hwmod,
+        &omap2420_l4_wkup_hwmod,
+        &omap2420_mpu_hwmod,
+        NULL,
+};
+
+#else
+# define omap2420_hwmods                0
+#endif
+
+#endif
+
+
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430.h b/arch/arm/mach-omap2/omap_hwmod_2430.h
new file mode 100644
index 000000000000..a412be6420ec
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2430.h
@@ -0,0 +1,143 @@
+/*
+ * omap_hwmod_2430.h - hardware modules present on the OMAP2430 chips
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX handle crossbar/shared link difference for L3?
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2430_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2430_H
+
+#ifdef CONFIG_ARCH_OMAP2430
+
+#include <mach/omap_hwmod.h>
+#include <mach/irqs.h>
+#include <mach/cpu.h>
+#include <mach/dma.h>
+
+#include "prm-regbits-24xx.h"
+
+static struct omap_hwmod omap2430_mpu_hwmod;
+static struct omap_hwmod omap2430_l3_hwmod;
+static struct omap_hwmod omap2430_l4_core_hwmod;
+
+/* L3 -> L4_CORE interface */
+static struct omap_hwmod_ocp_if omap2430_l3__l4_core = {
+        .master = &omap2430_l3_hwmod,
+        .slave  = &omap2430_l4_core_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* MPU -> L3 interface */
+static struct omap_hwmod_ocp_if omap2430_mpu__l3 = {
+        .master = &omap2430_mpu_hwmod,
+        .slave  = &omap2430_l3_hwmod,
+        .user   = OCP_USER_MPU,
+};
+
+/* Slave interfaces on the L3 interconnect */
+static struct omap_hwmod_ocp_if *omap2430_l3_slaves[] = {
+        &omap2430_mpu__l3,
+};
+
+/* Master interfaces on the L3 interconnect */
+static struct omap_hwmod_ocp_if *omap2430_l3_masters[] = {
+        &omap2430_l3__l4_core,
+};
+
+/* L3 */
+static struct omap_hwmod omap2430_l3_hwmod = {
+        .name           = "l3_hwmod",
+        .masters        = omap2430_l3_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2430_l3_masters),
+        .slaves         = omap2430_l3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_l3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+static struct omap_hwmod omap2430_l4_wkup_hwmod;
+static struct omap_hwmod omap2430_mmc1_hwmod;
+static struct omap_hwmod omap2430_mmc2_hwmod;
+
+/* L4_CORE -> L4_WKUP interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
+        .master = &omap2430_l4_core_hwmod,
+        .slave  = &omap2430_l4_wkup_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* Slave interfaces on the L4_CORE interconnect */
+static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
+        &omap2430_l3__l4_core,
+};
+
+/* Master interfaces on the L4_CORE interconnect */
+static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
+        &omap2430_l4_core__l4_wkup,
+};
+
+/* L4 CORE */
+static struct omap_hwmod omap2430_l4_core_hwmod = {
+        .name           = "l4_core_hwmod",
+        .masters        = omap2430_l4_core_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
+        .slaves         = omap2430_l4_core_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* Slave interfaces on the L4_WKUP interconnect */
+static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
+        &omap2430_l4_core__l4_wkup,
+};
+
+/* Master interfaces on the L4_WKUP interconnect */
+static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
+};
+
+/* L4 WKUP */
+static struct omap_hwmod omap2430_l4_wkup_hwmod = {
+        .name           = "l4_wkup_hwmod",
+        .masters        = omap2430_l4_wkup_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
+        .slaves         = omap2430_l4_wkup_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* Master interfaces on the MPU device */
+static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
+        &omap2430_mpu__l3,
+};
+
+/* MPU */
+static struct omap_hwmod omap2430_mpu_hwmod = {
+        .name           = "mpu_hwmod",
+        .clkdev_dev_id  = NULL,
+        .clkdev_con_id  = "mpu_ck",
+        .masters        = omap2430_mpu_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+        &omap2430_l3_hwmod,
+        &omap2430_l4_core_hwmod,
+        &omap2430_l4_wkup_hwmod,
+        &omap2430_mpu_hwmod,
+        NULL,
+};
+
+#else
+# define omap2430_hwmods                0
+#endif
+
+#endif
+
+
diff --git a/arch/arm/mach-omap2/omap_hwmod_34xx.h b/arch/arm/mach-omap2/omap_hwmod_34xx.h
new file mode 100644
index 000000000000..1e069f831575
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_34xx.h
@@ -0,0 +1,168 @@
+/*
+ * omap_hwmod_34xx.h - hardware modules present on the OMAP34xx chips
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H
+
+#ifdef CONFIG_ARCH_OMAP34XX
+
+#include <mach/omap_hwmod.h>
+#include <mach/irqs.h>
+#include <mach/cpu.h>
+#include <mach/dma.h>
+
+#include "prm-regbits-34xx.h"
+
+static struct omap_hwmod omap34xx_mpu_hwmod;
+static struct omap_hwmod omap34xx_l3_hwmod;
+static struct omap_hwmod omap34xx_l4_core_hwmod;
+static struct omap_hwmod omap34xx_l4_per_hwmod;
+
+/* L3 -> L4_CORE interface */
+static struct omap_hwmod_ocp_if omap34xx_l3__l4_core = {
+        .master = &omap34xx_l3_hwmod,
+        .slave  = &omap34xx_l4_core_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L3 -> L4_PER interface */
+static struct omap_hwmod_ocp_if omap34xx_l3__l4_per = {
+        .master = &omap34xx_l3_hwmod,
+        .slave  = &omap34xx_l4_per_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* MPU -> L3 interface */
+static struct omap_hwmod_ocp_if omap34xx_mpu__l3 = {
+        .master = &omap34xx_mpu_hwmod,
+        .slave  = &omap34xx_l3_hwmod,
+        .user   = OCP_USER_MPU,
+};
+
+/* Slave interfaces on the L3 interconnect */
+static struct omap_hwmod_ocp_if *omap34xx_l3_slaves[] = {
+        &omap34xx_mpu__l3,
+};
+
+/* Master interfaces on the L3 interconnect */
+static struct omap_hwmod_ocp_if *omap34xx_l3_masters[] = {
+        &omap34xx_l3__l4_core,
+        &omap34xx_l3__l4_per,
+};
+
+/* L3 */
+static struct omap_hwmod omap34xx_l3_hwmod = {
+        .name           = "l3_hwmod",
+        .masters        = omap34xx_l3_masters,
+        .masters_cnt    = ARRAY_SIZE(omap34xx_l3_masters),
+        .slaves         = omap34xx_l3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap34xx_l3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+static struct omap_hwmod omap34xx_l4_wkup_hwmod;
+
+/* L4_CORE -> L4_WKUP interface */
+static struct omap_hwmod_ocp_if omap34xx_l4_core__l4_wkup = {
+        .master = &omap34xx_l4_core_hwmod,
+        .slave  = &omap34xx_l4_wkup_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* Slave interfaces on the L4_CORE interconnect */
+static struct omap_hwmod_ocp_if *omap34xx_l4_core_slaves[] = {
+        &omap34xx_l3__l4_core,
+};
+
+/* Master interfaces on the L4_CORE interconnect */
+static struct omap_hwmod_ocp_if *omap34xx_l4_core_masters[] = {
+        &omap34xx_l4_core__l4_wkup,
+};
+
+/* L4 CORE */
+static struct omap_hwmod omap34xx_l4_core_hwmod = {
+        .name           = "l4_core_hwmod",
+        .masters        = omap34xx_l4_core_masters,
+        .masters_cnt    = ARRAY_SIZE(omap34xx_l4_core_masters),
+        .slaves         = omap34xx_l4_core_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap34xx_l4_core_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* Slave interfaces on the L4_PER interconnect */
+static struct omap_hwmod_ocp_if *omap34xx_l4_per_slaves[] = {
+        &omap34xx_l3__l4_per,
+};
+
+/* Master interfaces on the L4_PER interconnect */
+static struct omap_hwmod_ocp_if *omap34xx_l4_per_masters[] = {
+};
+
+/* L4 PER */
+static struct omap_hwmod omap34xx_l4_per_hwmod = {
+        .name           = "l4_per_hwmod",
+        .masters        = omap34xx_l4_per_masters,
+        .masters_cnt    = ARRAY_SIZE(omap34xx_l4_per_masters),
+        .slaves         = omap34xx_l4_per_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap34xx_l4_per_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* Slave interfaces on the L4_WKUP interconnect */
+static struct omap_hwmod_ocp_if *omap34xx_l4_wkup_slaves[] = {
+        &omap34xx_l4_core__l4_wkup,
+};
+
+/* Master interfaces on the L4_WKUP interconnect */
+static struct omap_hwmod_ocp_if *omap34xx_l4_wkup_masters[] = {
+};
+
+/* L4 WKUP */
+static struct omap_hwmod omap34xx_l4_wkup_hwmod = {
+        .name           = "l4_wkup_hwmod",
+        .masters        = omap34xx_l4_wkup_masters,
+        .masters_cnt    = ARRAY_SIZE(omap34xx_l4_wkup_masters),
+        .slaves         = omap34xx_l4_wkup_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap34xx_l4_wkup_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* Master interfaces on the MPU device */
+static struct omap_hwmod_ocp_if *omap34xx_mpu_masters[] = {
+        &omap34xx_mpu__l3,
+};
+
+/* MPU */
+static struct omap_hwmod omap34xx_mpu_hwmod = {
+        .name           = "mpu_hwmod",
+        .clkdev_dev_id  = NULL,
+        .clkdev_con_id  = "arm_fck",
+        .masters        = omap34xx_mpu_masters,
+        .masters_cnt    = ARRAY_SIZE(omap34xx_mpu_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
+        &omap34xx_l3_hwmod,
+        &omap34xx_l4_core_hwmod,
+        &omap34xx_l4_per_hwmod,
+        &omap34xx_l4_wkup_hwmod,
+        &omap34xx_mpu_hwmod,
+        NULL,
+};
+
+#else
+# define omap34xx_hwmods                0
+#endif
+
+#endif
+
+
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 6cc375a275be..1b4c1600f8d8 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -20,13 +20,16 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/timer.h>
+#include <linux/sched.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/module.h>
 
 #include <mach/clock.h>
 #include <mach/board.h>
+#include <mach/powerdomain.h>
+#include <mach/clockdomain.h>
 
 #include "prm.h"
 #include "cm.h"
@@ -48,7 +51,9 @@ int omap2_pm_debug;
         regs[reg_count++].val = __raw_readl(reg)
 #define DUMP_INTC_REG(reg, off) \
         regs[reg_count].name = #reg; \
-        regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
+        regs[reg_count++].val = __raw_readl(OMAP2_IO_ADDRESS(0x480fe000 + (off)))
+
+static int __init pm_dbg_init(void);
 
 void omap2_pm_dump(int mode, int resume, unsigned int us)
 {
@@ -150,3 +155,425 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
         for (i = 0; i < reg_count; i++)
                 printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 }
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+static void pm_dbg_regset_store(u32 *ptr);
+
+struct dentry *pm_dbg_dir;
+
+static int pm_dbg_init_done;
+
+enum {
+        DEBUG_FILE_COUNTERS = 0,
+        DEBUG_FILE_TIMERS,
+};
+
+struct pm_module_def {
+        char name[8]; /* Name of the module */
+        short type; /* CM or PRM */
+        unsigned short offset;
+        int low; /* First register address on this module */
+        int high; /* Last register address on this module */
+};
+
+#define MOD_CM 0
+#define MOD_PRM 1
+
+static const struct pm_module_def *pm_dbg_reg_modules;
+static const struct pm_module_def omap3_pm_reg_modules[] = {
+        { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
+        { "OCP", MOD_CM, OCP_MOD, 0, 0x10 },
+        { "MPU", MOD_CM, MPU_MOD, 4, 0x4c },
+        { "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
+        { "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c },
+        { "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 },
+        { "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
+        { "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c },
+        { "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c },
+        { "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c },
+        { "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 },
+        { "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 },
+        { "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c },
+
+        { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
+        { "OCP", MOD_PRM, OCP_MOD, 4, 0x1c },
+        { "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 },
+        { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
+        { "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 },
+        { "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 },
+        { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
+        { "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 },
+        { "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 },
+        { "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 },
+        { "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 },
+        { "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 },
+        { "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 },
+        { "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 },
+        { "", 0, 0, 0, 0 },
+};
+
+#define PM_DBG_MAX_REG_SETS 4
+
+static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
+
+static int pm_dbg_get_regset_size(void)
+{
+        static int regset_size;
+
+        if (regset_size == 0) {
+                int i = 0;
+
+                while (pm_dbg_reg_modules[i].name[0] != 0) {
+                        regset_size += pm_dbg_reg_modules[i].high +
+                                4 - pm_dbg_reg_modules[i].low;
+                        i++;
+                }
+        }
+        return regset_size;
+}
+
+static int pm_dbg_show_regs(struct seq_file *s, void *unused)
+{
+        int i, j;
+        unsigned long val;
+        int reg_set = (int)s->private;
+        u32 *ptr;
+        void *store = NULL;
+        int regs;
+        int linefeed;
+
+        if (reg_set == 0) {
+                store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
+                ptr = store;
+                pm_dbg_regset_store(ptr);
+        } else {
+                ptr = pm_dbg_reg_set[reg_set - 1];
+        }
+
+        i = 0;
+
+        while (pm_dbg_reg_modules[i].name[0] != 0) {
+                regs = 0;
+                linefeed = 0;
+                if (pm_dbg_reg_modules[i].type == MOD_CM)
+                        seq_printf(s, "MOD: CM_%s (%08x)\n",
+                                pm_dbg_reg_modules[i].name,
+                                (u32)(OMAP3430_CM_BASE +
+                                pm_dbg_reg_modules[i].offset));
+                else
+                        seq_printf(s, "MOD: PRM_%s (%08x)\n",
+                                pm_dbg_reg_modules[i].name,
+                                (u32)(OMAP3430_PRM_BASE +
+                                pm_dbg_reg_modules[i].offset));
+
+                for (j = pm_dbg_reg_modules[i].low;
+                        j <= pm_dbg_reg_modules[i].high; j += 4) {
+                        val = *(ptr++);
+                        if (val != 0) {
+                                regs++;
+                                if (linefeed) {
+                                        seq_printf(s, "\n");
+                                        linefeed = 0;
+                                }
+                                seq_printf(s, "  %02x => %08lx", j, val);
+                                if (regs % 4 == 0)
+                                        linefeed = 1;
+                        }
+                }
+                seq_printf(s, "\n");
+                i++;
+        }
+
+        if (store != NULL)
+                kfree(store);
+
+        return 0;
+}
+
+static void pm_dbg_regset_store(u32 *ptr)
+{
+        int i, j;
+        u32 val;
+
+        i = 0;
+
+        while (pm_dbg_reg_modules[i].name[0] != 0) {
+                for (j = pm_dbg_reg_modules[i].low;
+                        j <= pm_dbg_reg_modules[i].high; j += 4) {
+                        if (pm_dbg_reg_modules[i].type == MOD_CM)
+                                val = cm_read_mod_reg(
+                                        pm_dbg_reg_modules[i].offset, j);
+                        else
+                                val = prm_read_mod_reg(
+                                        pm_dbg_reg_modules[i].offset, j);
+                        *(ptr++) = val;
+                }
+                i++;
+        }
+}
+
+int pm_dbg_regset_save(int reg_set)
+{
+        if (pm_dbg_reg_set[reg_set-1] == NULL)
+                return -EINVAL;
+
+        pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]);
+
+        return 0;
+}
+
+static const char pwrdm_state_names[][4] = {
+        "OFF",
+        "RET",
+        "INA",
+        "ON"
+};
+
+void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
+{
+        s64 t;
+
+        if (!pm_dbg_init_done)
+                return ;
+
+        /* Update timer for previous state */
+        t = sched_clock();
+
+        pwrdm->state_timer[prev] += t - pwrdm->timer;
+
+        pwrdm->timer = t;
+}
+
+static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
+{
+        struct seq_file *s = (struct seq_file *)user;
+
+        if (strcmp(clkdm->name, "emu_clkdm") == 0 ||
+                strcmp(clkdm->name, "wkup_clkdm") == 0 ||
+                strncmp(clkdm->name, "dpll", 4) == 0)
+                return 0;
+
+        seq_printf(s, "%s->%s (%d)", clkdm->name,
+                        clkdm->pwrdm.ptr->name,
+                        atomic_read(&clkdm->usecount));
+        seq_printf(s, "\n");
+
+        return 0;
+}
+
+static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
+{
+        struct seq_file *s = (struct seq_file *)user;
+        int i;
+
+        if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
+                strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
+                strncmp(pwrdm->name, "dpll", 4) == 0)
+                return 0;
+
+        if (pwrdm->state != pwrdm_read_pwrst(pwrdm))
+                printk(KERN_ERR "pwrdm state mismatch(%s) %d != %d\n",
+                        pwrdm->name, pwrdm->state, pwrdm_read_pwrst(pwrdm));
+
+        seq_printf(s, "%s (%s)", pwrdm->name,
+                        pwrdm_state_names[pwrdm->state]);
+        for (i = 0; i < 4; i++)
+                seq_printf(s, ",%s:%d", pwrdm_state_names[i],
+                        pwrdm->state_counter[i]);
+
+        seq_printf(s, "\n");
+
+        return 0;
+}
+
+static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user)
+{
+        struct seq_file *s = (struct seq_file *)user;
+        int i;
+
+        if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
+                strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
+                strncmp(pwrdm->name, "dpll", 4) == 0)
+                return 0;
+
+        pwrdm_state_switch(pwrdm);
+
+        seq_printf(s, "%s (%s)", pwrdm->name,
+                pwrdm_state_names[pwrdm->state]);
+
+        for (i = 0; i < 4; i++)
+                seq_printf(s, ",%s:%lld", pwrdm_state_names[i],
+                        pwrdm->state_timer[i]);
+
+        seq_printf(s, "\n");
+        return 0;
+}
+
+static int pm_dbg_show_counters(struct seq_file *s, void *unused)
+{
+        pwrdm_for_each(pwrdm_dbg_show_counter, s);
+        clkdm_for_each(clkdm_dbg_show_counter, s);
+
+        return 0;
+}
+
+static int pm_dbg_show_timers(struct seq_file *s, void *unused)
+{
+        pwrdm_for_each(pwrdm_dbg_show_timer, s);
+        return 0;
+}
+
+static int pm_dbg_open(struct inode *inode, struct file *file)
+{
+        switch ((int)inode->i_private) {
+        case DEBUG_FILE_COUNTERS:
+                return single_open(file, pm_dbg_show_counters,
+                        &inode->i_private);
+        case DEBUG_FILE_TIMERS:
+        default:
+                return single_open(file, pm_dbg_show_timers,
+                        &inode->i_private);
+        };
+}
+
+static int pm_dbg_reg_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, pm_dbg_show_regs, inode->i_private);
+}
+
+static const struct file_operations debug_fops = {
+        .open           = pm_dbg_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static const struct file_operations debug_reg_fops = {
+        .open           = pm_dbg_reg_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+int pm_dbg_regset_init(int reg_set)
+{
+        char name[2];
+
+        if (!pm_dbg_init_done)
+                pm_dbg_init();
+
+        if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS ||
+                pm_dbg_reg_set[reg_set-1] != NULL)
+                return -EINVAL;
+
+        pm_dbg_reg_set[reg_set-1] =
+                kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
+
+        if (pm_dbg_reg_set[reg_set-1] == NULL)
+                return -ENOMEM;
+
+        if (pm_dbg_dir != NULL) {
+                sprintf(name, "%d", reg_set);
+
+                (void) debugfs_create_file(name, S_IRUGO,
+                        pm_dbg_dir, (void *)reg_set, &debug_reg_fops);
+        }
+
+        return 0;
+}
+
+static int pwrdm_suspend_get(void *data, u64 *val)
+{
+        *val = omap3_pm_get_suspend_state((struct powerdomain *)data);
+
+        if (*val >= 0)
+                return 0;
+        return *val;
+}
+
+static int pwrdm_suspend_set(void *data, u64 val)
+{
+        return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val);
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
+                        pwrdm_suspend_set, "%llu\n");
+
+static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
+{
+        int i;
+        s64 t;
+        struct dentry *d;
+
+        t = sched_clock();
+
+        for (i = 0; i < 4; i++)
+                pwrdm->state_timer[i] = 0;
+
+        pwrdm->timer = t;
+
+        if (strncmp(pwrdm->name, "dpll", 4) == 0)
+                return 0;
+
+        d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir);
+
+        (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
+                        (void *)pwrdm, &pwrdm_suspend_fops);
+
+        return 0;
+}
+
+static int __init pm_dbg_init(void)
+{
+        int i;
+        struct dentry *d;
+        char name[2];
+
+        if (pm_dbg_init_done)
+                return 0;
+
+        if (cpu_is_omap34xx())
+                pm_dbg_reg_modules = omap3_pm_reg_modules;
+        else {
+                printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
+                return -ENODEV;
+        }
+                
+        d = debugfs_create_dir("pm_debug", NULL);
+        if (IS_ERR(d))
+                return PTR_ERR(d);
+
+        (void) debugfs_create_file("count", S_IRUGO,
+                d, (void *)DEBUG_FILE_COUNTERS, &debug_fops);
+        (void) debugfs_create_file("time", S_IRUGO,
+                d, (void *)DEBUG_FILE_TIMERS, &debug_fops);
+
+        pwrdm_for_each(pwrdms_setup, (void *)d);
+
+        pm_dbg_dir = debugfs_create_dir("registers", d);
+        if (IS_ERR(pm_dbg_dir))
+                return PTR_ERR(pm_dbg_dir);
+
+        (void) debugfs_create_file("current", S_IRUGO,
+                pm_dbg_dir, (void *)0, &debug_reg_fops);
+
+        for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
+                if (pm_dbg_reg_set[i] != NULL) {
+                        sprintf(name, "%d", i+1);
+                        (void) debugfs_create_file(name, S_IRUGO,
+                                pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
+
+                }
+
+        pm_dbg_init_done = 1;
+
+        return 0;
+}
+arch_initcall(pm_dbg_init);
+
+#else
+void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) {}
+#endif
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 21201cd4117b..8400f5768923 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -11,12 +11,23 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PM_H
 #define __ARCH_ARM_MACH_OMAP2_PM_H
 
+#include <mach/powerdomain.h>
+
+extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
+extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
+
 #ifdef CONFIG_PM_DEBUG
 extern void omap2_pm_dump(int mode, int resume, unsigned int us);
 extern int omap2_pm_debug;
+extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
+extern int pm_dbg_regset_save(int reg_set);
+extern int pm_dbg_regset_init(int reg_set);
 #else
 #define omap2_pm_dump(mode, resume, us)         do {} while (0);
 #define omap2_pm_debug                          0
+#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
+#define pm_dbg_regset_save(reg_set) do {} while (0);
+#define pm_dbg_regset_init(reg_set) do {} while (0);
 #endif /* CONFIG_PM_DEBUG */
 
 extern void omap24xx_idle_loop_suspend(void);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 528dbdc26e23..bff5c4e89742 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -333,7 +333,7 @@ static struct platform_suspend_ops omap_pm_ops = {
         .valid          = suspend_valid_only_mem,
 };
 
-static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm)
+static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm, void *unused)
 {
         omap2_clkdm_allow_idle(clkdm);
         return 0;
@@ -385,7 +385,7 @@ static void __init prcm_setup_regs(void)
         omap2_clkdm_sleep(gfx_clkdm);
 
         /* Enable clockdomain hardware-supervised control for all clkdms */
-        clkdm_for_each(_pm_clkdm_enable_hwsup);
+        clkdm_for_each(_pm_clkdm_enable_hwsup, NULL);
 
         /* Enable clock autoidle for all domains */
         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 488d595d8e4b..0ff5a6c53aa0 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -170,6 +170,8 @@ static void omap_sram_idle(void)
                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
                 return;
         }
+        pwrdm_pre_transition();
+
         omap2_gpio_prepare_for_retention();
         omap_uart_prepare_idle(0);
         omap_uart_prepare_idle(1);
@@ -182,6 +184,9 @@ static void omap_sram_idle(void)
         omap_uart_resume_idle(1);
         omap_uart_resume_idle(0);
         omap2_gpio_resume_after_retention();
+
+        pwrdm_post_transition();
+
 }
 
 /*
@@ -271,6 +276,7 @@ static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
         if (sleep_switch) {
                 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
                 pwrdm_wait_transition(pwrdm);
+                pwrdm_state_switch(pwrdm);
         }
 
 err:
@@ -658,14 +664,38 @@ static void __init prcm_setup_regs(void)
         omap3_d2d_idle();
 }
 
-static int __init pwrdms_setup(struct powerdomain *pwrdm)
+int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
+{
+        struct power_state *pwrst;
+
+        list_for_each_entry(pwrst, &pwrst_list, node) {
+                if (pwrst->pwrdm == pwrdm)
+                        return pwrst->next_state;
+        }
+        return -EINVAL;
+}
+
+int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
+{
+        struct power_state *pwrst;
+
+        list_for_each_entry(pwrst, &pwrst_list, node) {
+                if (pwrst->pwrdm == pwrdm) {
+                        pwrst->next_state = state;
+                        return 0;
+                }
+        }
+        return -EINVAL;
+}
+
+static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 {
         struct power_state *pwrst;
 
         if (!pwrdm->pwrsts)
                 return 0;
 
-        pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
+        pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
         if (!pwrst)
                 return -ENOMEM;
         pwrst->pwrdm = pwrdm;
@@ -683,7 +713,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm)
  * supported. Initiate sleep transition for other clockdomains, if
  * they are not used
  */
-static int __init clkdms_setup(struct clockdomain *clkdm)
+static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 {
         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
                 omap2_clkdm_allow_idle(clkdm);
@@ -716,13 +746,13 @@ static int __init omap3_pm_init(void)
                 goto err1;
         }
 
-        ret = pwrdm_for_each(pwrdms_setup);
+        ret = pwrdm_for_each(pwrdms_setup, NULL);
         if (ret) {
                 printk(KERN_ERR "Failed to setup powerdomains\n");
                 goto err2;
         }
 
-        (void) clkdm_for_each(clkdms_setup);
+        (void) clkdm_for_each(clkdms_setup, NULL);
 
         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
         if (mpu_pwrdm == NULL) {
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 983f1cb676be..2594cbff3947 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -35,6 +35,13 @@
 #include <mach/powerdomain.h>
 #include <mach/clockdomain.h>
 
+#include "pm.h"
+
+enum {
+        PWRDM_STATE_NOW = 0,
+        PWRDM_STATE_PREV,
+};
+
 /* pwrdm_list contains all registered struct powerdomains */
 static LIST_HEAD(pwrdm_list);
 
@@ -83,7 +90,7 @@ static struct powerdomain *_pwrdm_deps_lookup(struct powerdomain *pwrdm,
         if (!pwrdm || !deps || !omap_chip_is(pwrdm->omap_chip))
                 return ERR_PTR(-EINVAL);
 
-        for (pd = deps; pd; pd++) {
+        for (pd = deps; pd->pwrdm_name; pd++) {
 
                 if (!omap_chip_is(pd->omap_chip))
                         continue;
@@ -96,12 +103,71 @@ static struct powerdomain *_pwrdm_deps_lookup(struct powerdomain *pwrdm,
 
         }
 
-        if (!pd)
+        if (!pd->pwrdm_name)
                 return ERR_PTR(-ENOENT);
 
         return pd->pwrdm;
 }
 
+static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
+{
+
+        int prev;
+        int state;
+
+        if (pwrdm == NULL)
+                return -EINVAL;
+
+        state = pwrdm_read_pwrst(pwrdm);
+
+        switch (flag) {
+        case PWRDM_STATE_NOW:
+                prev = pwrdm->state;
+                break;
+        case PWRDM_STATE_PREV:
+                prev = pwrdm_read_prev_pwrst(pwrdm);
+                if (pwrdm->state != prev)
+                        pwrdm->state_counter[prev]++;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        if (state != prev)
+                pwrdm->state_counter[state]++;
+
+        pm_dbg_update_time(pwrdm, prev);
+
+        pwrdm->state = state;
+
+        return 0;
+}
+
+static int _pwrdm_pre_transition_cb(struct powerdomain *pwrdm, void *unused)
+{
+        pwrdm_clear_all_prev_pwrst(pwrdm);
+        _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
+        return 0;
+}
+
+static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
+{
+        _pwrdm_state_switch(pwrdm, PWRDM_STATE_PREV);
+        return 0;
+}
+
+static __init void _pwrdm_setup(struct powerdomain *pwrdm)
+{
+        int i;
+
+        for (i = 0; i < 4; i++)
+                pwrdm->state_counter[i] = 0;
+
+        pwrdm_wait_transition(pwrdm);
+        pwrdm->state = pwrdm_read_pwrst(pwrdm);
+        pwrdm->state_counter[pwrdm->state] = 1;
+
+}
 
 /* Public functions */
 
@@ -117,9 +183,12 @@ void pwrdm_init(struct powerdomain **pwrdm_list)
 {
         struct powerdomain **p = NULL;
 
-        if (pwrdm_list)
-                for (p = pwrdm_list; *p; p++)
+        if (pwrdm_list) {
+                for (p = pwrdm_list; *p; p++) {
                         pwrdm_register(*p);
+                        _pwrdm_setup(*p);
+                }
+        }
 }
 
 /**
@@ -217,7 +286,8 @@ struct powerdomain *pwrdm_lookup(const char *name)
  * anything else to indicate failure; or -EINVAL if the function
  * pointer is null.
  */
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm))
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+                        void *user)
 {
         struct powerdomain *temp_pwrdm;
         unsigned long flags;
@@ -228,7 +298,7 @@ int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm))
 
         read_lock_irqsave(&pwrdm_rwlock, flags);
         list_for_each_entry(temp_pwrdm, &pwrdm_list, node) {
-                ret = (*fn)(temp_pwrdm);
+                ret = (*fn)(temp_pwrdm, user);
                 if (ret)
                         break;
         }
@@ -1110,4 +1180,36 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
         return 0;
 }
 
+int pwrdm_state_switch(struct powerdomain *pwrdm)
+{
+        return _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
+}
+
+int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
+{
+        if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) {
+                pwrdm_wait_transition(clkdm->pwrdm.ptr);
+                return pwrdm_state_switch(clkdm->pwrdm.ptr);
+        }
+
+        return -EINVAL;
+}
+int pwrdm_clk_state_switch(struct clk *clk)
+{
+        if (clk != NULL && clk->clkdm != NULL)
+                return pwrdm_clkdm_state_switch(clk->clkdm);
+        return -EINVAL;
+}
+
+int pwrdm_pre_transition(void)
+{
+        pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
+        return 0;
+}
+
+int pwrdm_post_transition(void)
+{
+        pwrdm_for_each(_pwrdm_post_transition_cb, NULL);
+        return 0;
+}
 
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 9937e2814696..03c467c35f54 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -17,11 +17,11 @@
 #include "prcm-common.h"
 
 #define OMAP2420_PRM_REGADDR(module, reg)                               \
-                        IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
+                        OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
 #define OMAP2430_PRM_REGADDR(module, reg)                               \
-                        IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
+                        OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
 #define OMAP34XX_PRM_REGADDR(module, reg)                               \
-                        IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
+                        OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
 
 /*
  * Architecture-specific global PRM registers
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 1a8bbd094066..0837eda5f2b6 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -48,9 +48,9 @@ static inline u32 sms_read_reg(u16 reg)
         return __raw_readl(OMAP_SMS_REGADDR(reg));
 }
 #else
-#define OMAP242X_SDRC_REGADDR(reg)      IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
-#define OMAP243X_SDRC_REGADDR(reg)      IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
-#define OMAP34XX_SDRC_REGADDR(reg)      IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
+#define OMAP242X_SDRC_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
+#define OMAP243X_SDRC_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
+#define OMAP34XX_SDRC_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
 #endif  /* __ASSEMBLER__ */
 
 #endif
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index a7421a50410b..3a529c77daa8 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -73,7 +73,7 @@ static LIST_HEAD(uart_list);
 
 static struct plat_serial8250_port serial_platform_data0[] = {
         {
-                .membase        = IO_ADDRESS(OMAP_UART1_BASE),
+                .membase        = OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
                 .mapbase        = OMAP_UART1_BASE,
                 .irq            = 72,
                 .flags          = UPF_BOOT_AUTOCONF,
@@ -87,7 +87,7 @@ static struct plat_serial8250_port serial_platform_data0[] = {
 
 static struct plat_serial8250_port serial_platform_data1[] = {
         {
-                .membase        = IO_ADDRESS(OMAP_UART2_BASE),
+                .membase        = OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
                 .mapbase        = OMAP_UART2_BASE,
                 .irq            = 73,
                 .flags          = UPF_BOOT_AUTOCONF,
@@ -101,7 +101,7 @@ static struct plat_serial8250_port serial_platform_data1[] = {
 
 static struct plat_serial8250_port serial_platform_data2[] = {
         {
-                .membase        = IO_ADDRESS(OMAP_UART3_BASE),
+                .membase        = OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
                 .mapbase        = OMAP_UART3_BASE,
                 .irq            = 74,
                 .flags          = UPF_BOOT_AUTOCONF,
@@ -109,10 +109,35 @@ static struct plat_serial8250_port serial_platform_data2[] = {
                 .regshift       = 2,
                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
         }, {
+#ifdef CONFIG_ARCH_OMAP4
+                .membase        = IO_ADDRESS(OMAP_UART4_BASE),
+                .mapbase        = OMAP_UART4_BASE,
+                .irq            = 70,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = OMAP24XX_BASE_BAUD * 16,
+        }, {
+#endif
                 .flags          = 0
         }
 };
 
+#ifdef CONFIG_ARCH_OMAP4
+static struct plat_serial8250_port serial_platform_data3[] = {
+        {
+                .membase        = IO_ADDRESS(OMAP_UART4_BASE),
+                .mapbase        = OMAP_UART4_BASE,
+                .irq            = 70,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = OMAP24XX_BASE_BAUD * 16,
+        }, {
+                .flags          = 0
+        }
+};
+#endif
 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
                                            int offset)
 {
@@ -460,7 +485,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                 uart->padconf = 0;
         }
 
-        p->flags |= UPF_SHARE_IRQ;
+        p->irqflags |= IRQF_SHARED;
         ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
                           "serial idle", (void *)uart);
         WARN_ON(ret);
@@ -550,12 +575,22 @@ static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
                         },
                 },
         },
+#ifdef CONFIG_ARCH_OMAP4
+        {
+                .pdev = {
+                        .name                   = "serial8250",
+                        .id                     = 3
+                        .dev                    = {
+                                .platform_data  = serial_platform_data3,
+                        },
+                },
+        },
+#endif
 };
 
-void __init omap_serial_init(void)
+void __init omap_serial_early_init(void)
 {
         int i;
-        const struct omap_uart_config *info;
         char name[16];
 
         /*
@@ -564,23 +599,12 @@ void __init omap_serial_init(void)
          * if not needed.
          */
 
-        info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
-
-        if (info == NULL)
-                return;
-
         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
                 struct omap_uart_state *uart = &omap_uart[i];
                 struct platform_device *pdev = &uart->pdev;
                 struct device *dev = &pdev->dev;
                 struct plat_serial8250_port *p = dev->platform_data;
 
-                if (!(info->enabled_uarts & (1 << i))) {
-                        p->membase = NULL;
-                        p->mapbase = 0;
-                        continue;
-                }
-
                 sprintf(name, "uart%d_ick", i+1);
                 uart->ick = clk_get(NULL, name);
                 if (IS_ERR(uart->ick)) {
@@ -595,8 +619,11 @@ void __init omap_serial_init(void)
                         uart->fck = NULL;
                 }
 
-                if (!uart->ick || !uart->fck)
-                        continue;
+                /* FIXME: Remove this once the clkdev is ready */
+                if (!cpu_is_omap44xx()) {
+                        if (!uart->ick || !uart->fck)
+                                continue;
+                }
 
                 uart->num = i;
                 p->private_data = uart;
@@ -607,6 +634,18 @@ void __init omap_serial_init(void)
                         p->irq += 32;
 
                 omap_uart_enable_clocks(uart);
+        }
+}
+
+void __init omap_serial_init(void)
+{
+        int i;
+
+        for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+                struct omap_uart_state *uart = &omap_uart[i];
+                struct platform_device *pdev = &uart->pdev;
+                struct device *dev = &pdev->dev;
+
                 omap_uart_reset(uart);
                 omap_uart_idle_init(uart);
 
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index bb299851116d..9b62208658bc 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -128,7 +128,7 @@ omap242x_sdi_prcm_voltctrl:
 prcm_mask_val:
         .word 0xFFFF3FFC
 omap242x_sdi_timer_32ksynct_cr:
-        .word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
+        .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
 ENTRY(omap242x_sram_ddr_init_sz)
         .word   . - omap242x_sram_ddr_init
 
@@ -224,7 +224,7 @@ omap242x_srs_prcm_voltctrl:
 ddr_prcm_mask_val:
         .word 0xFFFF3FFC
 omap242x_srs_timer_32ksynct:
-        .word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
+        .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
 
 ENTRY(omap242x_sram_reprogram_sdrc_sz)
         .word   . - omap242x_sram_reprogram_sdrc
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index 9955abcaeb31..df2cd9277c00 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -128,7 +128,7 @@ omap243x_sdi_prcm_voltctrl:
 prcm_mask_val:
         .word 0xFFFF3FFC
 omap243x_sdi_timer_32ksynct_cr:
-        .word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
+        .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
 ENTRY(omap243x_sram_ddr_init_sz)
         .word   . - omap243x_sram_ddr_init
 
@@ -224,7 +224,7 @@ omap243x_srs_prcm_voltctrl:
 ddr_prcm_mask_val:
         .word 0xFFFF3FFC
 omap243x_srs_timer_32ksynct:
-        .word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
+        .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
 
 ENTRY(omap243x_sram_reprogram_sdrc_sz)
         .word   . - omap243x_sram_reprogram_sdrc
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 97eeeebcb066..e2338c0aebcf 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -231,7 +231,7 @@ static void __init omap2_gp_clocksource_init(void)
 static void __init omap2_gp_timer_init(void)
 {
 #ifdef CONFIG_LOCAL_TIMERS
-        twd_base = IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE);
+        twd_base = OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE);
 #endif
         omap_dm_timer_init();
 
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 739e59e8025c..1145a2562b0f 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -31,15 +31,6 @@
 #include <mach/mux.h>
 #include <mach/usb.h>
 
-#define OTG_SYSCONFIG   (OMAP34XX_HSUSB_OTG_BASE + 0x404)
-
-static void __init usb_musb_pm_init(void)
-{
-        /* Ensure force-idle mode for OTG controller */
-        if (cpu_is_omap34xx())
-                omap_writel(0, OTG_SYSCONFIG);
-}
-
 #ifdef CONFIG_USB_MUSB_SOC
 
 static struct resource musb_resources[] = {
@@ -173,13 +164,10 @@ void __init usb_musb_init(void)
                 printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n");
                 return;
         }
-
-        usb_musb_pm_init();
 }
 
 #else
 void __init usb_musb_init(void)
 {
-        usb_musb_pm_init();
 }
 #endif /* CONFIG_USB_MUSB_SOC */
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 2c7035d8dcbf..c3d513cad5ac 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -89,6 +89,27 @@ config MACH_EDMINI_V2
           Say 'Y' here if you want your kernel to support the
           LaCie Ethernet Disk mini V2.
 
+config MACH_D2NET
+        bool "LaCie d2 Network"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie d2 Network NAS.
+
+config MACH_BIGDISK
+        bool "LaCie Big Disk Network"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie Big Disk Network NAS.
+
+config MACH_NET2BIG
+        bool "LaCie 2Big Network"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie 2Big Network NAS.
+
 config MACH_MSS2
         bool "Maxtor Shared Storage II"
         help
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index edc38e2c856f..89772fcd65c7 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -12,6 +12,9 @@ obj-$(CONFIG_MACH_WRT350N_V2)	+= wrt350n-v2-setup.o
 obj-$(CONFIG_MACH_TS78XX)       += ts78xx-setup.o
 obj-$(CONFIG_MACH_MV2120)       += mv2120-setup.o
 obj-$(CONFIG_MACH_EDMINI_V2)    += edmini_v2-setup.o
+obj-$(CONFIG_MACH_D2NET)        += d2net-setup.o
+obj-$(CONFIG_MACH_BIGDISK)      += d2net-setup.o
+obj-$(CONFIG_MACH_NET2BIG)      += net2big-setup.o
 obj-$(CONFIG_MACH_MSS2)         += mss2-setup.o
 obj-$(CONFIG_MACH_WNR854T)      += wnr854t-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_GE)        += rd88f5181l-ge-setup.o
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index d78731edebb6..1a5d6a0e2602 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -84,7 +84,8 @@ static int __init orion5x_cpu_win_can_remap(int win)
         orion5x_pcie_id(&dev, &rev);
         if ((dev == MV88F5281_DEV_ID && win < 4)
             || (dev == MV88F5182_DEV_ID && win < 2)
-            || (dev == MV88F5181_DEV_ID && win < 2))
+            || (dev == MV88F5181_DEV_ID && win < 2)
+            || (dev == MV88F6183_DEV_ID && win < 4))
                 return 1;
 
         return 0;
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
new file mode 100644
index 000000000000..9d4bf763f25b
--- /dev/null
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -0,0 +1,365 @@
+/*
+ * arch/arm/mach-orion5x/d2net-setup.c
+ *
+ * LaCie d2Network and Big Disk Network NAS setup
+ *
+ * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <mach/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * LaCie d2 Network Info
+ ****************************************************************************/
+
+/*
+ * 512KB NOR flash Device bus boot chip select
+ */
+
+#define D2NET_NOR_BOOT_BASE             0xfff80000
+#define D2NET_NOR_BOOT_SIZE             SZ_512K
+
+/*****************************************************************************
+ * 512KB NOR Flash on Boot Device
+ ****************************************************************************/
+
+/*
+ * TODO: Check write support on flash MX29LV400CBTC-70G
+ */
+
+static struct mtd_partition d2net_partitions[] = {
+        {
+                .name           = "Full512kb",
+                .size           = MTDPART_SIZ_FULL,
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+};
+
+static struct physmap_flash_data d2net_nor_flash_data = {
+        .width          = 1,
+        .parts          = d2net_partitions,
+        .nr_parts       = ARRAY_SIZE(d2net_partitions),
+};
+
+static struct resource d2net_nor_flash_resource = {
+        .flags                  = IORESOURCE_MEM,
+        .start                  = D2NET_NOR_BOOT_BASE,
+        .end                    = D2NET_NOR_BOOT_BASE
+                                        + D2NET_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device d2net_nor_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &d2net_nor_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &d2net_nor_flash_resource,
+};
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data d2net_eth_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+/*****************************************************************************
+ * I2C devices
+ ****************************************************************************/
+
+/*
+ * i2c addr | chip         | description
+ * 0x32     | Ricoh 5C372b | RTC
+ * 0x3e     | GMT G762     | PWM fan controller
+ * 0x50     | HT24LC08     | eeprom (1kB)
+ *
+ * TODO: Add G762 support to the g760a driver.
+ */
+static struct i2c_board_info __initdata d2net_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("rs5c372b", 0x32),
+        }, {
+                I2C_BOARD_INFO("24c08", 0x50),
+        },
+};
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+
+static struct mv_sata_platform_data d2net_sata_data = {
+        .n_ports        = 2,
+};
+
+#define D2NET_GPIO_SATA0_POWER  3
+#define D2NET_GPIO_SATA1_POWER  12
+
+static void __init d2net_sata_power_init(void)
+{
+        int err;
+
+        err = gpio_request(D2NET_GPIO_SATA0_POWER, "SATA0 power");
+        if (err == 0) {
+                err = gpio_direction_output(D2NET_GPIO_SATA0_POWER, 1);
+                if (err)
+                        gpio_free(D2NET_GPIO_SATA0_POWER);
+        }
+        if (err)
+                pr_err("d2net: failed to configure SATA0 power GPIO\n");
+
+        err = gpio_request(D2NET_GPIO_SATA1_POWER, "SATA1 power");
+        if (err == 0) {
+                err = gpio_direction_output(D2NET_GPIO_SATA1_POWER, 1);
+                if (err)
+                        gpio_free(D2NET_GPIO_SATA1_POWER);
+        }
+        if (err)
+                pr_err("d2net: failed to configure SATA1 power GPIO\n");
+}
+
+/*****************************************************************************
+ * GPIO LED's
+ ****************************************************************************/
+
+/*
+ * The blue front LED is wired to the CPLD and can blink in relation with the
+ * SATA activity. This feature is disabled to make this LED compatible with
+ * the leds-gpio driver: MPP14 and MPP15 are configured to act like output
+ * GPIO's and have to stay in an active state. This is needed to set the blue
+ * LED in a "fix on" state regardless of the SATA activity.
+ *
+ * The following array detail the different LED registers and the combination
+ * of their possible values:
+ *
+ * led_off   | blink_ctrl | SATA active | LED state
+ *           |            |             |
+ *    1      |     x      |      x      |  off
+ *    0      |     0      |      0      |  off
+ *    0      |     1      |      0      |  blink (rate 300ms)
+ *    0      |     x      |      1      |  on
+ *
+ * Notes: The blue and the red front LED's can't be on at the same time.
+ *        Red LED have priority.
+ */
+
+#define D2NET_GPIO_RED_LED              6
+#define D2NET_GPIO_BLUE_LED_BLINK_CTRL  16
+#define D2NET_GPIO_BLUE_LED_OFF         23
+#define D2NET_GPIO_SATA0_ACT            14
+#define D2NET_GPIO_SATA1_ACT            15
+
+static struct gpio_led d2net_leds[] = {
+        {
+                .name = "d2net:blue:power",
+                .gpio = D2NET_GPIO_BLUE_LED_OFF,
+                .active_low = 1,
+        },
+        {
+                .name = "d2net:red:fail",
+                .gpio = D2NET_GPIO_RED_LED,
+        },
+};
+
+static struct gpio_led_platform_data d2net_led_data = {
+        .num_leds = ARRAY_SIZE(d2net_leds),
+        .leds = d2net_leds,
+};
+
+static struct platform_device d2net_gpio_leds = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_led_data,
+        },
+};
+
+static void __init d2net_gpio_leds_init(void)
+{
+        /* Configure GPIO over MPP max number. */
+        orion_gpio_set_valid(D2NET_GPIO_BLUE_LED_OFF, 1);
+
+        if (gpio_request(D2NET_GPIO_SATA0_ACT, "LED SATA0 activity") != 0)
+                return;
+        if (gpio_direction_output(D2NET_GPIO_SATA0_ACT, 1) != 0)
+                goto err_free_1;
+        if (gpio_request(D2NET_GPIO_SATA1_ACT, "LED SATA1 activity") != 0)
+                goto err_free_1;
+        if (gpio_direction_output(D2NET_GPIO_SATA1_ACT, 1) != 0)
+                goto err_free_2;
+        platform_device_register(&d2net_gpio_leds);
+        return;
+
+err_free_2:
+        gpio_free(D2NET_GPIO_SATA1_ACT);
+err_free_1:
+        gpio_free(D2NET_GPIO_SATA0_ACT);
+        return;
+}
+
+/****************************************************************************
+ * GPIO keys
+ ****************************************************************************/
+
+#define D2NET_GPIO_PUSH_BUTTON          18
+#define D2NET_GPIO_POWER_SWITCH_ON      8
+#define D2NET_GPIO_POWER_SWITCH_OFF     9
+
+#define D2NET_SWITCH_POWER_ON           0x1
+#define D2NET_SWITCH_POWER_OFF          0x2
+
+static struct gpio_keys_button d2net_buttons[] = {
+        {
+                .type           = EV_SW,
+                .code           = D2NET_SWITCH_POWER_OFF,
+                .gpio           = D2NET_GPIO_POWER_SWITCH_OFF,
+                .desc           = "Power rocker switch (auto|off)",
+                .active_low     = 0,
+        },
+        {
+                .type           = EV_SW,
+                .code           = D2NET_SWITCH_POWER_ON,
+                .gpio           = D2NET_GPIO_POWER_SWITCH_ON,
+                .desc           = "Power rocker switch (on|auto)",
+                .active_low     = 0,
+        },
+        {
+                .type           = EV_KEY,
+                .code           = KEY_POWER,
+                .gpio           = D2NET_GPIO_PUSH_BUTTON,
+                .desc           = "Front Push Button",
+                .active_low     = 0,
+        },
+};
+
+static struct gpio_keys_platform_data d2net_button_data = {
+        .buttons        = d2net_buttons,
+        .nbuttons       = ARRAY_SIZE(d2net_buttons),
+};
+
+static struct platform_device d2net_gpio_buttons = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_button_data,
+        },
+};
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+
+static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },       /* Board ID (bit 0) */
+        {  1, MPP_GPIO },       /* Board ID (bit 1) */
+        {  2, MPP_GPIO },       /* Board ID (bit 2) */
+        {  3, MPP_GPIO },       /* SATA 0 power */
+        {  4, MPP_UNUSED },
+        {  5, MPP_GPIO },       /* Fan fail detection */
+        {  6, MPP_GPIO },       /* Red front LED */
+        {  7, MPP_UNUSED },
+        {  8, MPP_GPIO },       /* Rear power switch (on|auto) */
+        {  9, MPP_GPIO },       /* Rear power switch (auto|off) */
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED },
+        { 12, MPP_GPIO },       /* SATA 1 power */
+        { 13, MPP_UNUSED },
+        { 14, MPP_GPIO },       /* SATA 0 active */
+        { 15, MPP_GPIO },       /* SATA 1 active */
+        { 16, MPP_GPIO },       /* Blue front LED blink control */
+        { 17, MPP_UNUSED },
+        { 18, MPP_GPIO },       /* Front button (0 = Released, 1 = Pushed ) */
+        { 19, MPP_UNUSED },
+        { -1 }
+        /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
+        /* 23: Blue front LED off */
+        /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */
+};
+
+static void __init d2net_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(d2net_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&d2net_eth_data);
+        orion5x_i2c_init();
+        orion5x_uart0_init();
+
+        d2net_sata_power_init();
+        orion5x_sata_init(&d2net_sata_data);
+
+        orion5x_setup_dev_boot_win(D2NET_NOR_BOOT_BASE,
+                                D2NET_NOR_BOOT_SIZE);
+        platform_device_register(&d2net_nor_flash);
+
+        platform_device_register(&d2net_gpio_buttons);
+
+        d2net_gpio_leds_init();
+
+        pr_notice("d2net: Flash write are not yet supported.\n");
+
+        i2c_register_board_info(0, d2net_i2c_devices,
+                                ARRAY_SIZE(d2net_i2c_devices));
+}
+
+/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
+
+#ifdef CONFIG_MACH_D2NET
+MACHINE_START(D2NET, "LaCie d2 Network")
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = d2net_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_BIGDISK
+MACHINE_START(BIGDISK, "LaCie Big Disk Network")
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = d2net_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
+#endif
+
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
new file mode 100644
index 000000000000..7bd6283476f9
--- /dev/null
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -0,0 +1,431 @@
+/*
+ * arch/arm/mach-orion5x/net2big-setup.c
+ *
+ * LaCie 2Big Network NAS setup
+ *
+ * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * LaCie 2Big Network Info
+ ****************************************************************************/
+
+/*
+ * 512KB NOR flash Device bus boot chip select
+ */
+
+#define NET2BIG_NOR_BOOT_BASE           0xfff80000
+#define NET2BIG_NOR_BOOT_SIZE           SZ_512K
+
+/*****************************************************************************
+ * 512KB NOR Flash on Boot Device
+ ****************************************************************************/
+
+/*
+ * TODO: Check write support on flash MX29LV400CBTC-70G
+ */
+
+static struct mtd_partition net2big_partitions[] = {
+        {
+                .name           = "Full512kb",
+                .size           = MTDPART_SIZ_FULL,
+                .offset         = 0x00000000,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+};
+
+static struct physmap_flash_data net2big_nor_flash_data = {
+        .width          = 1,
+        .parts          = net2big_partitions,
+        .nr_parts       = ARRAY_SIZE(net2big_partitions),
+};
+
+static struct resource net2big_nor_flash_resource = {
+        .flags                  = IORESOURCE_MEM,
+        .start                  = NET2BIG_NOR_BOOT_BASE,
+        .end                    = NET2BIG_NOR_BOOT_BASE
+                                        + NET2BIG_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device net2big_nor_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &net2big_nor_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &net2big_nor_flash_resource,
+};
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data net2big_eth_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+/*****************************************************************************
+ * I2C devices
+ ****************************************************************************/
+
+/*
+ * i2c addr | chip         | description
+ * 0x32     | Ricoh 5C372b | RTC
+ * 0x50     | HT24LC08     | eeprom (1kB)
+ */
+static struct i2c_board_info __initdata net2big_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("rs5c372b", 0x32),
+        }, {
+                I2C_BOARD_INFO("24c08", 0x50),
+        },
+};
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+
+static struct mv_sata_platform_data net2big_sata_data = {
+        .n_ports        = 2,
+};
+
+#define NET2BIG_GPIO_SATA_POWER_REQ     19
+#define NET2BIG_GPIO_SATA0_POWER        23
+#define NET2BIG_GPIO_SATA1_POWER        25
+
+static void __init net2big_sata_power_init(void)
+{
+        int err;
+
+        /* Configure GPIOs over MPP max number. */
+        orion_gpio_set_valid(NET2BIG_GPIO_SATA0_POWER, 1);
+        orion_gpio_set_valid(NET2BIG_GPIO_SATA1_POWER, 1);
+
+        err = gpio_request(NET2BIG_GPIO_SATA0_POWER, "SATA0 power status");
+        if (err == 0) {
+                err = gpio_direction_input(NET2BIG_GPIO_SATA0_POWER);
+                if (err)
+                        gpio_free(NET2BIG_GPIO_SATA0_POWER);
+        }
+        if (err) {
+                pr_err("net2big: failed to setup SATA0 power GPIO\n");
+                return;
+        }
+
+        err = gpio_request(NET2BIG_GPIO_SATA1_POWER, "SATA1 power status");
+        if (err == 0) {
+                err = gpio_direction_input(NET2BIG_GPIO_SATA1_POWER);
+                if (err)
+                        gpio_free(NET2BIG_GPIO_SATA1_POWER);
+        }
+        if (err) {
+                pr_err("net2big: failed to setup SATA1 power GPIO\n");
+                goto err_free_1;
+        }
+
+        err = gpio_request(NET2BIG_GPIO_SATA_POWER_REQ, "SATA power request");
+        if (err == 0) {
+                err = gpio_direction_output(NET2BIG_GPIO_SATA_POWER_REQ, 0);
+                if (err)
+                        gpio_free(NET2BIG_GPIO_SATA_POWER_REQ);
+        }
+        if (err) {
+                pr_err("net2big: failed to setup SATA power request GPIO\n");
+                goto err_free_2;
+        }
+
+        if (gpio_get_value(NET2BIG_GPIO_SATA0_POWER) &&
+                gpio_get_value(NET2BIG_GPIO_SATA1_POWER)) {
+                return;
+        }
+
+        /*
+         * SATA power up on both disk is done by pulling high the CPLD power
+         * request line. The 300ms delay is related to the CPLD clock and is
+         * needed to be sure that the CPLD has take into account the low line
+         * status.
+         */
+        msleep(300);
+        gpio_set_value(NET2BIG_GPIO_SATA_POWER_REQ, 1);
+        pr_info("net2big: power up SATA hard disks\n");
+
+        return;
+
+err_free_2:
+        gpio_free(NET2BIG_GPIO_SATA1_POWER);
+err_free_1:
+        gpio_free(NET2BIG_GPIO_SATA0_POWER);
+
+        return;
+}
+
+/*****************************************************************************
+ * GPIO LEDs
+ ****************************************************************************/
+
+/*
+ * The power front LEDs (blue and red) and SATA red LEDs are controlled via a
+ * single GPIO line and are compatible with the leds-gpio driver.
+ *
+ * The SATA blue LEDs have some hardware blink capabilities which are detailled
+ * in the following array:
+ *
+ * SATAx blue LED | SATAx activity | LED state
+ *                |                |
+ *       0        |       0        |  blink (rate 300ms)
+ *       1        |       0        |  off
+ *       ?        |       1        |  on
+ *
+ * Notes: The blue and the red front LED's can't be on at the same time.
+ *        Blue LED have priority.
+ */
+
+#define NET2BIG_GPIO_PWR_RED_LED        6
+#define NET2BIG_GPIO_PWR_BLUE_LED       16
+#define NET2BIG_GPIO_PWR_LED_BLINK_STOP 7
+
+#define NET2BIG_GPIO_SATA0_RED_LED      11
+#define NET2BIG_GPIO_SATA1_RED_LED      10
+
+#define NET2BIG_GPIO_SATA0_BLUE_LED     17
+#define NET2BIG_GPIO_SATA1_BLUE_LED     13
+
+static struct gpio_led net2big_leds[] = {
+        {
+                .name = "net2big:red:power",
+                .gpio = NET2BIG_GPIO_PWR_RED_LED,
+        },
+        {
+                .name = "net2big:blue:power",
+                .gpio = NET2BIG_GPIO_PWR_BLUE_LED,
+        },
+        {
+                .name = "net2big:red:sata0",
+                .gpio = NET2BIG_GPIO_SATA0_RED_LED,
+        },
+        {
+                .name = "net2big:red:sata1",
+                .gpio = NET2BIG_GPIO_SATA1_RED_LED,
+        },
+};
+
+static struct gpio_led_platform_data net2big_led_data = {
+        .num_leds = ARRAY_SIZE(net2big_leds),
+        .leds = net2big_leds,
+};
+
+static struct platform_device net2big_gpio_leds = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &net2big_led_data,
+        },
+};
+
+static void __init net2big_gpio_leds_init(void)
+{
+        int err;
+
+        /* Stop initial CPLD slow red/blue blinking on power LED. */
+        err = gpio_request(NET2BIG_GPIO_PWR_LED_BLINK_STOP,
+                           "Power LED blink stop");
+        if (err == 0) {
+                err = gpio_direction_output(NET2BIG_GPIO_PWR_LED_BLINK_STOP, 1);
+                if (err)
+                        gpio_free(NET2BIG_GPIO_PWR_LED_BLINK_STOP);
+        }
+        if (err)
+                pr_err("net2big: failed to setup power LED blink GPIO\n");
+
+        /*
+         * Configure SATA0 and SATA1 blue LEDs to blink in relation with the
+         * hard disk activity.
+         */
+        err = gpio_request(NET2BIG_GPIO_SATA0_BLUE_LED,
+                           "SATA0 blue LED control");
+        if (err == 0) {
+                err = gpio_direction_output(NET2BIG_GPIO_SATA0_BLUE_LED, 1);
+                if (err)
+                        gpio_free(NET2BIG_GPIO_SATA0_BLUE_LED);
+        }
+        if (err)
+                pr_err("net2big: failed to setup SATA0 blue LED GPIO\n");
+
+        err = gpio_request(NET2BIG_GPIO_SATA1_BLUE_LED,
+                           "SATA1 blue LED control");
+        if (err == 0) {
+                err = gpio_direction_output(NET2BIG_GPIO_SATA1_BLUE_LED, 1);
+                if (err)
+                        gpio_free(NET2BIG_GPIO_SATA1_BLUE_LED);
+        }
+        if (err)
+                pr_err("net2big: failed to setup SATA1 blue LED GPIO\n");
+
+        platform_device_register(&net2big_gpio_leds);
+}
+
+/****************************************************************************
+ * GPIO keys
+ ****************************************************************************/
+
+#define NET2BIG_GPIO_PUSH_BUTTON        18
+#define NET2BIG_GPIO_POWER_SWITCH_ON    8
+#define NET2BIG_GPIO_POWER_SWITCH_OFF   9
+
+#define NET2BIG_SWITCH_POWER_ON         0x1
+#define NET2BIG_SWITCH_POWER_OFF        0x2
+
+static struct gpio_keys_button net2big_buttons[] = {
+        {
+                .type           = EV_SW,
+                .code           = NET2BIG_SWITCH_POWER_OFF,
+                .gpio           = NET2BIG_GPIO_POWER_SWITCH_OFF,
+                .desc           = "Power rocker switch (auto|off)",
+                .active_low     = 0,
+        },
+        {
+                .type           = EV_SW,
+                .code           = NET2BIG_SWITCH_POWER_ON,
+                .gpio           = NET2BIG_GPIO_POWER_SWITCH_ON,
+                .desc           = "Power rocker switch (on|auto)",
+                .active_low     = 0,
+        },
+        {
+                .type           = EV_KEY,
+                .code           = KEY_POWER,
+                .gpio           = NET2BIG_GPIO_PUSH_BUTTON,
+                .desc           = "Front Push Button",
+                .active_low     = 0,
+        },
+};
+
+static struct gpio_keys_platform_data net2big_button_data = {
+        .buttons        = net2big_buttons,
+        .nbuttons       = ARRAY_SIZE(net2big_buttons),
+};
+
+static struct platform_device net2big_gpio_buttons = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &net2big_button_data,
+        },
+};
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+
+static struct orion5x_mpp_mode net2big_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },       /* Raid mode (bit 0) */
+        {  1, MPP_GPIO },       /* USB port 2 fuse (0 = Fail, 1 = Ok) */
+        {  2, MPP_GPIO },       /* Raid mode (bit 1) */
+        {  3, MPP_GPIO },       /* Board ID (bit 0) */
+        {  4, MPP_GPIO },       /* Fan activity (0 = Off, 1 = On) */
+        {  5, MPP_GPIO },       /* Fan fail detection */
+        {  6, MPP_GPIO },       /* Red front LED (0 = Off, 1 = On) */
+        {  7, MPP_GPIO },       /* Disable initial blinking on front LED */
+        {  8, MPP_GPIO },       /* Rear power switch (on|auto) */
+        {  9, MPP_GPIO },       /* Rear power switch (auto|off) */
+        { 10, MPP_GPIO },       /* SATA 1 red LED (0 = Off, 1 = On) */
+        { 11, MPP_GPIO },       /* SATA 0 red LED (0 = Off, 1 = On) */
+        { 12, MPP_GPIO },       /* Board ID (bit 1) */
+        { 13, MPP_GPIO },       /* SATA 1 blue LED blink control */
+        { 14, MPP_SATA_LED },
+        { 15, MPP_SATA_LED },
+        { 16, MPP_GPIO },       /* Blue front LED control */
+        { 17, MPP_GPIO },       /* SATA 0 blue LED blink control */
+        { 18, MPP_GPIO },       /* Front button (0 = Released, 1 = Pushed ) */
+        { 19, MPP_GPIO },       /* SATA{0,1} power On/Off request */
+        { -1 }
+        /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
+        /* 23: SATA 0 power status */
+        /* 24: Board power off */
+        /* 25: SATA 1 power status */
+};
+
+#define NET2BIG_GPIO_POWER_OFF          24
+
+static void net2big_power_off(void)
+{
+        gpio_set_value(NET2BIG_GPIO_POWER_OFF, 1);
+}
+
+static void __init net2big_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(net2big_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&net2big_eth_data);
+        orion5x_i2c_init();
+        orion5x_uart0_init();
+        orion5x_xor_init();
+
+        net2big_sata_power_init();
+        orion5x_sata_init(&net2big_sata_data);
+
+        orion5x_setup_dev_boot_win(NET2BIG_NOR_BOOT_BASE,
+                                   NET2BIG_NOR_BOOT_SIZE);
+        platform_device_register(&net2big_nor_flash);
+
+        platform_device_register(&net2big_gpio_buttons);
+        net2big_gpio_leds_init();
+
+        i2c_register_board_info(0, net2big_i2c_devices,
+                                ARRAY_SIZE(net2big_i2c_devices));
+
+        orion_gpio_set_valid(NET2BIG_GPIO_POWER_OFF, 1);
+
+        if (gpio_request(NET2BIG_GPIO_POWER_OFF, "power-off") == 0 &&
+            gpio_direction_output(NET2BIG_GPIO_POWER_OFF, 0) == 0)
+                pm_power_off = net2big_power_off;
+        else
+                pr_err("net2big: failed to configure power-off GPIO\n");
+
+        pr_notice("net2big: Flash writing is not yet supported.\n");
+}
+
+/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
+MACHINE_START(NET2BIG, "LaCie 2Big Network")
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = net2big_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
+
diff --git a/arch/arm/mach-pxa/include/mach/audio.h b/arch/arm/mach-pxa/include/mach/audio.h
index 16eb02552d5d..a3449e35a6f5 100644
--- a/arch/arm/mach-pxa/include/mach/audio.h
+++ b/arch/arm/mach-pxa/include/mach/audio.h
@@ -3,10 +3,12 @@
 
 #include <sound/core.h>
 #include <sound/pcm.h>
+#include <sound/ac97_codec.h>
 
 /*
  * @reset_gpio: AC97 reset gpio (normally gpio113 or gpio95)
  *              a -1 value means no gpio will be used for reset
+ * @codec_pdata: AC97 codec platform_data
 
  * reset_gpio should only be specified for pxa27x CPUs where a silicon
  * bug prevents correct operation of the reset line. If not specified,
@@ -20,6 +22,7 @@ typedef struct {
         void (*resume)(void *);
         void *priv;
         int reset_gpio;
+        void *codec_pdata[AC97_BUS_MAX_DEVICES];
 } pxa2xx_audio_ops_t;
 
 extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops);
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h b/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h
index d5a48a96dea7..7b4eadc6df3a 100644
--- a/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h
+++ b/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h
@@ -2,9 +2,12 @@
 #define __ASM_ARCH_PXA27x_KEYPAD_H
 
 #include <linux/input.h>
+#include <linux/input/matrix_keypad.h>
 
 #define MAX_MATRIX_KEY_ROWS     (8)
 #define MAX_MATRIX_KEY_COLS     (8)
+#define MATRIX_ROW_SHIFT        (3)
+#define MAX_DIRECT_KEY_NUM      (8)
 
 /* pxa3xx keypad platform specific parameters
  *
@@ -33,7 +36,7 @@ struct pxa27x_keypad_platform_data {
 
         /* direct keys */
         int             direct_key_num;
-        unsigned int    direct_key_map[8];
+        unsigned int    direct_key_map[MAX_DIRECT_KEY_NUM];
 
         /* rotary encoders 0 */
         int             enable_rotary0;
@@ -51,8 +54,6 @@ struct pxa27x_keypad_platform_data {
         unsigned int    debounce_interval;
 };
 
-#define KEY(row, col, val)      (((row) << 28) | ((col) << 24) | (val))
-
 extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
 
 #endif /* __ASM_ARCH_PXA27x_KEYPAD_H */
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 2546c066cd6e..629e05d1196e 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -678,8 +678,8 @@ static int corgi_enter_suspend(unsigned long alarm_time, unsigned int alarm_enab
                 dev_dbg(sharpsl_pm.dev, "User triggered wakeup in offline charger.\n");
         }
 
-        if ((!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_LOCK)) || (sharpsl_fatal_check() < 0) )
-        {
+        if ((!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_LOCK)) ||
+            (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_FATAL))) {
                 dev_err(sharpsl_pm.dev, "Fatal condition. Suspend.\n");
                 corgi_goto_sleep(alarm_time, alarm_enable, state);
                 return 1;
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index d4cfa2145386..dfc9b0bc6eb2 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -75,7 +75,7 @@ config MACH_REALVIEW_PBX
 
 config REALVIEW_HIGH_PHYS_OFFSET
         bool "High physical base address for the RealView platform"
-        depends on !MACH_REALVIEW_PB1176
+        depends on MMU && !MACH_REALVIEW_PB1176
         default y
         help
           RealView boards other than PB1176 have the RAM available at
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index facbd49eec67..dc3519c50ab2 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -221,6 +221,9 @@ arch_initcall(realview_i2c_init);
 
 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 
+/*
+ * This is only used if GPIOLIB support is disabled
+ */
 static unsigned int realview_mmc_status(struct device *dev)
 {
         struct amba_device *adev = container_of(dev, struct amba_device, dev);
@@ -237,11 +240,15 @@ static unsigned int realview_mmc_status(struct device *dev)
 struct mmc_platform_data realview_mmc0_plat_data = {
         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
         .status         = realview_mmc_status,
+        .gpio_wp        = 17,
+        .gpio_cd        = 16,
 };
 
 struct mmc_platform_data realview_mmc1_plat_data = {
         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
         .status         = realview_mmc_status,
+        .gpio_wp        = 19,
+        .gpio_cd        = 18,
 };
 
 /*
diff --git a/arch/arm/mach-realview/include/mach/gpio.h b/arch/arm/mach-realview/include/mach/gpio.h
new file mode 100644
index 000000000000..94ff27678a46
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/gpio.h
@@ -0,0 +1,6 @@
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
diff --git a/arch/arm/mach-realview/include/mach/hardware.h b/arch/arm/mach-realview/include/mach/hardware.h
index b42c14f89acb..8a638d15797f 100644
--- a/arch/arm/mach-realview/include/mach/hardware.h
+++ b/arch/arm/mach-realview/include/mach/hardware.h
@@ -25,6 +25,7 @@
 #include <asm/sizes.h>
 
 /* macro to get at IO space when running virtually */
+#ifdef CONFIG_MMU
 /*
  * Statically mapped addresses:
  *
@@ -33,6 +34,9 @@
  * 1fxx xxxx -> fexx xxxx
  */
 #define IO_ADDRESS(x)           (((x) & 0x03ffffff) + 0xfb000000)
+#else
+#define IO_ADDRESS(x)           (x)
+#endif
 #define __io_address(n)         __io(IO_ADDRESS(n))
 
 #endif
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index ac0e83f1cc3a..a88458b4799d 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -20,6 +20,7 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/localtimer.h>
+#include <asm/unified.h>
 
 #include <mach/board-eb.h>
 #include <mach/board-pb11mp.h>
@@ -137,26 +138,19 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 static void __init poke_milo(void)
 {
-        extern void secondary_startup(void);
-
         /* nobody is to be released from the pen yet */
         pen_release = -1;
 
         /*
-         * write the address of secondary startup into the system-wide
-         * flags register, then clear the bottom two bits, which is what
-         * BootMonitor is waiting for
+         * Write the address of secondary startup into the system-wide flags
+         * register. The BootMonitor waits for this register to become
+         * non-zero.
          */
-#if 1
 #define REALVIEW_SYS_FLAGSS_OFFSET 0x30
-        __raw_writel(virt_to_phys(realview_secondary_startup),
-                     __io_address(REALVIEW_SYS_BASE) +
-                     REALVIEW_SYS_FLAGSS_OFFSET);
 #define REALVIEW_SYS_FLAGSC_OFFSET 0x34
-        __raw_writel(3,
+        __raw_writel(BSYM(virt_to_phys(realview_secondary_startup)),
                      __io_address(REALVIEW_SYS_BASE) +
-                     REALVIEW_SYS_FLAGSC_OFFSET);
-#endif
+                     REALVIEW_SYS_FLAGSS_OFFSET);
 
         mb();
 }
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 8dfa44e08a94..abd13b448671 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -23,6 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl061.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -113,6 +114,21 @@ static void __init realview_eb_map_io(void)
                 iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc));
 }
 
+static struct pl061_platform_data gpio0_plat_data = {
+        .gpio_base      = 0,
+        .irq_base       = -1,
+};
+
+static struct pl061_platform_data gpio1_plat_data = {
+        .gpio_base      = 8,
+        .irq_base       = -1,
+};
+
+static struct pl061_platform_data gpio2_plat_data = {
+        .gpio_base      = 16,
+        .irq_base       = -1,
+};
+
 /*
  * RealView EB AMBA devices
  */
@@ -189,9 +205,9 @@ AMBA_DEVICE(clcd,  "dev:20",  EB_CLCD,  &clcd_plat_data);
 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 AMBA_DEVICE(wdog,  "dev:e1",  EB_WATCHDOG, NULL);
-AMBA_DEVICE(gpio0, "dev:e4",  EB_GPIO0, NULL);
-AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
-AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    NULL);
+AMBA_DEVICE(gpio0, "dev:e4",  EB_GPIO0, &gpio0_plat_data);
+AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
+AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    &gpio2_plat_data);
 AMBA_DEVICE(rtc,   "dev:e8",  EB_RTC,   NULL);
 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 AMBA_DEVICE(uart0, "dev:f1",  EB_UART0, NULL);
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 25efe71a67c7..17fbb0e889b6 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -23,6 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl061.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -107,6 +108,21 @@ static void __init realview_pb1176_map_io(void)
         iotable_init(realview_pb1176_io_desc, ARRAY_SIZE(realview_pb1176_io_desc));
 }
 
+static struct pl061_platform_data gpio0_plat_data = {
+        .gpio_base      = 0,
+        .irq_base       = -1,
+};
+
+static struct pl061_platform_data gpio1_plat_data = {
+        .gpio_base      = 8,
+        .irq_base       = -1,
+};
+
+static struct pl061_platform_data gpio2_plat_data = {
+        .gpio_base      = 16,
+        .irq_base       = -1,
+};
+
 /*
  * RealView PB1176 AMBA devices
  */
@@ -164,9 +180,9 @@ AMBA_DEVICE(uart3,	"fpga:09",	PB1176_UART3,	NULL);
 AMBA_DEVICE(smc,        "dev:00",       PB1176_SMC,     NULL);
 AMBA_DEVICE(sctl,       "dev:e0",       SCTL,           NULL);
 AMBA_DEVICE(wdog,       "dev:e1",       PB1176_WATCHDOG,        NULL);
-AMBA_DEVICE(gpio0,      "dev:e4",       PB1176_GPIO0,   NULL);
-AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          NULL);
-AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          NULL);
+AMBA_DEVICE(gpio0,      "dev:e4",       PB1176_GPIO0,   &gpio0_plat_data);
+AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          &gpio1_plat_data);
+AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          &gpio2_plat_data);
 AMBA_DEVICE(rtc,        "dev:e8",       PB1176_RTC,     NULL);
 AMBA_DEVICE(sci0,       "dev:f0",       SCI,            NULL);
 AMBA_DEVICE(uart0,      "dev:f1",       PB1176_UART0,   NULL);
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index dc4b16943907..fdd042b85f40 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -23,6 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl061.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -108,6 +109,21 @@ static void __init realview_pb11mp_map_io(void)
         iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc));
 }
 
+static struct pl061_platform_data gpio0_plat_data = {
+        .gpio_base      = 0,
+        .irq_base       = -1,
+};
+
+static struct pl061_platform_data gpio1_plat_data = {
+        .gpio_base      = 8,
+        .irq_base       = -1,
+};
+
+static struct pl061_platform_data gpio2_plat_data = {
+        .gpio_base      = 16,
+        .irq_base       = -1,
+};
+
 /*
  * RealView PB11MPCore AMBA devices
  */
@@ -166,9 +182,9 @@ AMBA_DEVICE(uart3,	"fpga:09",	PB11MP_UART3,	NULL);
 AMBA_DEVICE(smc,        "dev:00",       PB11MP_SMC,     NULL);
 AMBA_DEVICE(sctl,       "dev:e0",       SCTL,           NULL);
 AMBA_DEVICE(wdog,       "dev:e1",       PB11MP_WATCHDOG, NULL);
-AMBA_DEVICE(gpio0,      "dev:e4",       PB11MP_GPIO0,   NULL);
-AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          NULL);
-AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          NULL);
+AMBA_DEVICE(gpio0,      "dev:e4",       PB11MP_GPIO0,   &gpio0_plat_data);
+AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          &gpio1_plat_data);
+AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          &gpio2_plat_data);
 AMBA_DEVICE(rtc,        "dev:e8",       PB11MP_RTC,     NULL);
 AMBA_DEVICE(sci0,       "dev:f0",       SCI,            NULL);
 AMBA_DEVICE(uart0,      "dev:f1",       PB11MP_UART0,   NULL);
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index d6ac1eb86576..70bba9900d97 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -23,6 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl061.h>
 #include <linux/io.h>
 
 #include <asm/irq.h>
@@ -98,6 +99,21 @@ static void __init realview_pba8_map_io(void)
         iotable_init(realview_pba8_io_desc, ARRAY_SIZE(realview_pba8_io_desc));
 }
 
+static struct pl061_platform_data gpio0_plat_data = {
+        .gpio_base      = 0,
+        .irq_base       = -1,
+};
+
+static struct pl061_platform_data gpio1_plat_data = {
+        .gpio_base      = 8,
+        .irq_base       = -1,
+};
+
+static struct pl061_platform_data gpio2_plat_data = {
+        .gpio_base      = 16,
+        .irq_base       = -1,
+};
+
 /*
  * RealView PBA8Core AMBA devices
  */
@@ -156,9 +172,9 @@ AMBA_DEVICE(uart3,	"fpga:09",	PBA8_UART3,	NULL);
 AMBA_DEVICE(smc,        "dev:00",       PBA8_SMC,       NULL);
 AMBA_DEVICE(sctl,       "dev:e0",       SCTL,           NULL);
 AMBA_DEVICE(wdog,       "dev:e1",       PBA8_WATCHDOG, NULL);
-AMBA_DEVICE(gpio0,      "dev:e4",       PBA8_GPIO0,     NULL);
-AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          NULL);
-AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          NULL);
+AMBA_DEVICE(gpio0,      "dev:e4",       PBA8_GPIO0,     &gpio0_plat_data);
+AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          &gpio1_plat_data);
+AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          &gpio2_plat_data);
 AMBA_DEVICE(rtc,        "dev:e8",       PBA8_RTC,       NULL);
 AMBA_DEVICE(sci0,       "dev:f0",       SCI,            NULL);
 AMBA_DEVICE(uart0,      "dev:f1",       PBA8_UART0,     NULL);
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index ede2a57240a3..ce6c5d25fbef 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -22,6 +22,7 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl061.h>
 #include <linux/io.h>
 
 #include <asm/irq.h>
@@ -118,6 +119,21 @@ static void __init realview_pbx_map_io(void)
                 iotable_init(realview_local_io_desc, ARRAY_SIZE(realview_local_io_desc));
 }
 
+static struct pl061_platform_data gpio0_plat_data = {
+        .gpio_base      = 0,
+        .irq_base       = -1,
+};
+
+static struct pl061_platform_data gpio1_plat_data = {
+        .gpio_base      = 8,
+        .irq_base       = -1,
+};
+
+static struct pl061_platform_data gpio2_plat_data = {
+        .gpio_base      = 16,
+        .irq_base       = -1,
+};
+
 /*
  * RealView PBXCore AMBA devices
  */
@@ -176,9 +192,9 @@ AMBA_DEVICE(uart3,	"fpga:09",	PBX_UART3,	NULL);
 AMBA_DEVICE(smc,        "dev:00",       PBX_SMC,        NULL);
 AMBA_DEVICE(sctl,       "dev:e0",       SCTL,           NULL);
 AMBA_DEVICE(wdog,       "dev:e1",       PBX_WATCHDOG,   NULL);
-AMBA_DEVICE(gpio0,      "dev:e4",       PBX_GPIO0,      NULL);
-AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          NULL);
-AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          NULL);
+AMBA_DEVICE(gpio0,      "dev:e4",       PBX_GPIO0,      &gpio0_plat_data);
+AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          &gpio1_plat_data);
+AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          &gpio2_plat_data);
 AMBA_DEVICE(rtc,        "dev:e8",       PBX_RTC,        NULL);
 AMBA_DEVICE(sci0,       "dev:f0",       SCI,            NULL);
 AMBA_DEVICE(uart0,      "dev:f1",       PBX_UART0,      NULL);
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 41bb65d5b91f..d8c023d4df30 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -12,6 +12,7 @@ config CPU_S3C2410
         select S3C2410_GPIO
         select CPU_LLSERIAL_S3C2410
         select S3C2410_PM if PM
+        select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
         help
           Support for S3C2410 and S3C2410A family from the S3C24XX line
           of Samsung Mobile CPUs.
@@ -45,6 +46,22 @@ config MACH_BAST_IDE
           Internal node for machines with an BAST style IDE
           interface
 
+# cpu frequency scaling support
+
+config S3C2410_CPUFREQ
+        bool
+        depends on CPU_FREQ_S3C24XX && CPU_S3C2410
+        select S3C2410_CPUFREQ_UTILS
+        help
+          CPU Frequency scaling support for S3C2410
+
+config S3C2410_PLLTABLE
+        bool
+        depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL
+        default y
+        help
+          Select the PLL table for the S3C2410
+
 menu "S3C2410 Machines"
 
 config ARCH_SMDK2410
@@ -79,6 +96,7 @@ config MACH_N30
 config ARCH_BAST
         bool "Simtec Electronics BAST (EB2410ITX)"
         select CPU_S3C2410
+        select S3C2410_IOTIMING if S3C2410_CPUFREQ
         select PM_SIMTEC if PM
         select SIMTEC_NOR
         select MACH_BAST_IDE
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index fca02f82711c..2ab5ba4b266f 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -15,6 +15,8 @@ obj-$(CONFIG_CPU_S3C2410_DMA)	+= dma.o
 obj-$(CONFIG_CPU_S3C2410_DMA)   += dma.o
 obj-$(CONFIG_S3C2410_PM)        += pm.o sleep.o
 obj-$(CONFIG_S3C2410_GPIO)      += gpio.o
+obj-$(CONFIG_S3C2410_CPUFREQ)   += cpu-freq.o
+obj-$(CONFIG_S3C2410_PLLTABLE)  += pll.o
 
 # Machine support
 
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c
new file mode 100644
index 000000000000..9d1186877d08
--- /dev/null
+++ b/arch/arm/mach-s3c2410/cpu-freq.c
@@ -0,0 +1,159 @@
+/* linux/arch/arm/mach-s3c2410/cpu-freq.c
+ *
+ * Copyright (c) 2006,2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 CPU Frequency scaling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/sysdev.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/regs-clock.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/cpu-freq-core.h>
+
+/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
+
+static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        u32 clkdiv = 0;
+
+        if (cfg->divs.h_divisor == 2)
+                clkdiv |= S3C2410_CLKDIVN_HDIVN;
+
+        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
+                clkdiv |= S3C2410_CLKDIVN_PDIVN;
+
+        __raw_writel(clkdiv, S3C2410_CLKDIVN);
+}
+
+static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long hclk, fclk, pclk;
+        unsigned int hdiv, pdiv;
+        unsigned long hclk_max;
+
+        fclk = cfg->freq.fclk;
+        hclk_max = cfg->max.hclk;
+
+        cfg->freq.armclk = fclk;
+
+        s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
+                      __func__, fclk, hclk_max);
+
+        hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
+        hclk = fclk / hdiv;
+
+        if (hclk > cfg->max.hclk) {
+                s3c_freq_dbg("%s: hclk too big\n", __func__);
+                return -EINVAL;
+        }
+
+        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
+        pclk = hclk / pdiv;
+
+        if (pclk > cfg->max.pclk) {
+                s3c_freq_dbg("%s: pclk too big\n", __func__);
+                return -EINVAL;
+        }
+
+        pdiv *= hdiv;
+
+        /* record the result */
+        cfg->divs.p_divisor = pdiv;
+        cfg->divs.h_divisor = hdiv;
+
+        return 0      ;
+}
+
+static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
+        .max            = {
+                .fclk   = 200000000,
+                .hclk   = 100000000,
+                .pclk   =  50000000,
+        },
+
+        /* transition latency is about 5ms worst-case, so
+         * set 10ms to be sure */
+        .latency        = 10000000,
+
+        .locktime_m     = 150,
+        .locktime_u     = 150,
+        .locktime_bits  = 12,
+
+        .need_pll       = 1,
+
+        .name           = "s3c2410",
+        .calc_iotiming  = s3c2410_iotiming_calc,
+        .set_iotiming   = s3c2410_iotiming_set,
+        .get_iotiming   = s3c2410_iotiming_get,
+        .resume_clocks  = s3c2410_setup_clocks,
+
+        .set_fvco       = s3c2410_set_fvco,
+        .set_refresh    = s3c2410_cpufreq_setrefresh,
+        .set_divs       = s3c2410_cpufreq_setdivs,
+        .calc_divs      = s3c2410_cpufreq_calcdivs,
+
+        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
+};
+
+static int s3c2410_cpufreq_add(struct sys_device *sysdev)
+{
+        return s3c_cpufreq_register(&s3c2410_cpufreq_info);
+}
+
+static struct sysdev_driver s3c2410_cpufreq_driver = {
+        .add            = s3c2410_cpufreq_add,
+};
+
+static int __init s3c2410_cpufreq_init(void)
+{
+        return sysdev_driver_register(&s3c2410_sysclass,
+                                      &s3c2410_cpufreq_driver);
+}
+
+arch_initcall(s3c2410_cpufreq_init);
+
+static int s3c2410a_cpufreq_add(struct sys_device *sysdev)
+{
+        /* alter the maximum freq settings for S3C2410A. If a board knows
+         * it only has a maximum of 200, then it should register its own
+         * limits. */
+
+        s3c2410_cpufreq_info.max.fclk = 266000000;
+        s3c2410_cpufreq_info.max.hclk = 133000000;
+        s3c2410_cpufreq_info.max.pclk =  66500000;
+        s3c2410_cpufreq_info.name = "s3c2410a";
+
+        return s3c2410_cpufreq_add(sysdev);
+}
+
+static struct sysdev_driver s3c2410a_cpufreq_driver = {
+        .add            = s3c2410a_cpufreq_add,
+};
+
+static int __init s3c2410a_cpufreq_init(void)
+{
+        return sysdev_driver_register(&s3c2410a_sysclass,
+                                      &s3c2410a_cpufreq_driver);
+}
+
+arch_initcall(s3c2410a_cpufreq_init);
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index dbf96e60d992..63b753f56c64 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -164,6 +164,17 @@ static int __init s3c2410_dma_drvinit(void)
 }
 
 arch_initcall(s3c2410_dma_drvinit);
+
+static struct sysdev_driver s3c2410a_dma_driver = {
+        .add    = s3c2410_dma_add,
+};
+
+static int __init s3c2410a_dma_drvinit(void)
+{
+        return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_dma_driver);
+}
+
+arch_initcall(s3c2410a_dma_drvinit);
 #endif
 
 #if defined(CONFIG_CPU_S3C2442)
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
index 2a2384ffa7b1..6c12c6312ad8 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -164,6 +164,12 @@
 #define IRQ_S3CUART_TX3         IRQ_S3C2443_TX3
 #define IRQ_S3CUART_ERR3        IRQ_S3C2443_ERR3
 
+#ifdef CONFIG_CPU_S3C2440
+#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97
+#else
+#define IRQ_S3C244x_AC97 IRQ_S3C2443_AC97
+#endif
+
 /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
 #define FIQ_START               IRQ_EINT0
 
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index e99b212cb1ca..b049e61460b6 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -67,6 +67,13 @@
 #define S3C2443_PA_HSMMC   (0x4A800000)
 #define S3C2443_SZ_HSMMC   (256)
 
+/* S3C2412 memory and IO controls */
+#define S3C2412_PA_SSMC (0x4F000000)
+#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
+
+#define S3C2412_PA_EBI  (0x48800000)
+#define S3C2412_VA_EBI  S3C_ADDR_CPU(0x00010000)
+
 /* physical addresses of all the chip-select areas */
 
 #define S3C2410_CS0 (0x00000000)
@@ -103,5 +110,6 @@
 #define S3C_PA_UART         S3C24XX_PA_UART
 #define S3C_PA_USBHOST  S3C2410_PA_USBHOST
 #define S3C_PA_HSMMC0       S3C2443_PA_HSMMC
+#define S3C_PA_NAND         S3C24XX_PA_NAND
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index b278d0c45ccf..f6e8eec879c8 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -328,13 +328,15 @@
 
 #define S3C2410_GPD8_VD16       (0x02 << 16)
 #define S3C2400_GPD8_TOUT3      (0x02 << 16)
+#define S3C2440_GPD8_SPIMISO1   (0x03 << 16)
 
 #define S3C2410_GPD9_VD17       (0x02 << 18)
 #define S3C2400_GPD9_TCLK0      (0x02 << 18)
-#define S3C2410_GPD9_MASK       (0x03 << 18)
+#define S3C2440_GPD9_SPIMOSI1   (0x03 << 18)
 
 #define S3C2410_GPD10_VD18      (0x02 << 20)
 #define S3C2400_GPD10_nWAIT     (0x02 << 20)
+#define S3C2440_GPD10_SPICLK1   (0x03 << 20)
 
 #define S3C2410_GPD11_VD19      (0x02 << 22)
 
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
index 57759804e2fa..7f7c52947963 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
@@ -73,6 +73,16 @@
 #define S3C2410_BWSCON_WS7              (1<<30)
 #define S3C2410_BWSCON_ST7              (1<<31)
 
+/* accesor functions for getting BANK(n) configuration. (n != 0) */
+
+#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
+
+#define S3C2410_BWSCON_DW8              (0)
+#define S3C2410_BWSCON_DW16             (1)
+#define S3C2410_BWSCON_DW32             (2)
+#define S3C2410_BWSCON_WS               (1 << 2)
+#define S3C2410_BWSCON_ST               (1 << 3)
+
 /* memory set (rom, ram) */
 #define S3C2410_BANKCON0                S3C2410_MEMREG(0x0004)
 #define S3C2410_BANKCON1                S3C2410_MEMREG(0x0008)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
index a4bf27123170..fb6352515090 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
@@ -14,9 +14,11 @@
 #ifndef __ASM_ARM_REGS_S3C2412_MEM
 #define __ASM_ARM_REGS_S3C2412_MEM
 
-#ifndef S3C2412_MEMREG
 #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
-#endif
+#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
+
+#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
+#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
 
 #define S3C2412_BANKCFG                 S3C2412_MEMREG(0x00)
 #define S3C2412_BANKCON1                S3C2412_MEMREG(0x04)
@@ -26,4 +28,21 @@
 #define S3C2412_REFRESH                 S3C2412_MEMREG(0x10)
 #define S3C2412_TIMEOUT                 S3C2412_MEMREG(0x14)
 
+/* EBI control registers */
+
+#define S3C2412_EBI_PR                  S3C2412_EBIREG(0x00)
+#define S3C2412_EBI_BANKCFG             S3C2412_EBIREG(0x04)
+
+/* SSMC control registers */
+
+#define S3C2412_SSMC_BANK(x)            S3C2412_SSMC(x, 0x00)
+#define S3C2412_SMIDCYR(x)              S3C2412_SSMC(x, 0x00)
+#define S3C2412_SMBWSTRD(x)             S3C2412_SSMC(x, 0x04)
+#define S3C2412_SMBWSTWRR(x)            S3C2412_SSMC(x, 0x08)
+#define S3C2412_SMBWSTOENR(x)           S3C2412_SSMC(x, 0x0C)
+#define S3C2412_SMBWSTWENR(x)           S3C2412_SSMC(x, 0x10)
+#define S3C2412_SMBCR(x)                S3C2412_SSMC(x, 0x14)
+#define S3C2412_SMBSR(x)                S3C2412_SSMC(x, 0x18)
+#define S3C2412_SMBWSTBRDR(x)           S3C2412_SSMC(x, 0x1C)
+
 #endif /*  __ASM_ARM_REGS_S3C2412_MEM */
diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h
index 1d300fb112b1..193b39d654ed 100644
--- a/arch/arm/mach-s3c2410/include/mach/spi.h
+++ b/arch/arm/mach-s3c2410/include/mach/spi.h
@@ -30,4 +30,7 @@ extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
 extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
                                               int enable);
 
+extern void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
+                                               int enable);
+
 #endif /* __ASM_ARCH_SPI_H */
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index 92150399563b..5e2f35332056 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -39,9 +39,22 @@ static struct sysdev_driver s3c2410_irq_driver = {
         .resume         = s3c24xx_irq_resume,
 };
 
-static int s3c2410_irq_init(void)
+static int __init s3c2410_irq_init(void)
 {
         return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver);
 }
 
 arch_initcall(s3c2410_irq_init);
+
+static struct sysdev_driver s3c2410a_irq_driver = {
+        .add            = s3c2410_irq_add,
+        .suspend        = s3c24xx_irq_suspend,
+        .resume         = s3c24xx_irq_resume,
+};
+
+static int __init s3c2410a_irq_init(void)
+{
+        return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_irq_driver);
+}
+
+arch_initcall(s3c2410a_irq_init);
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index ce3baba2cd7f..647c9adb018f 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -45,6 +45,7 @@
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 
+#include <plat/hwmon.h>
 #include <plat/nand.h>
 #include <plat/iic.h>
 #include <mach/fb.h>
@@ -59,6 +60,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/cpu-freq.h>
 
 #include "usb-simtec.h"
 #include "nor-simtec.h"
@@ -547,7 +549,35 @@ static struct i2c_board_info bast_i2c_devs[] __initdata = {
         },
 };
 
+static struct s3c_hwmon_pdata bast_hwmon_info = {
+        /* LCD contrast (0-6.6V) */
+        .in[0] = &(struct s3c_hwmon_chcfg) {
+                .name           = "lcd-contrast",
+                .mult           = 3300,
+                .div            = 512,
+        },
+        /* LED current feedback */
+        .in[1] = &(struct s3c_hwmon_chcfg) {
+                .name           = "led-feedback",
+                .mult           = 3300,
+                .div            = 1024,
+        },
+        /* LCD feedback (0-6.6V) */
+        .in[2] = &(struct s3c_hwmon_chcfg) {
+                .name           = "lcd-feedback",
+                .mult           = 3300,
+                .div            = 512,
+        },
+        /* Vcore (1.8-2.0V), Vref 3.3V  */
+        .in[3] = &(struct s3c_hwmon_chcfg) {
+                .name           = "vcore",
+                .mult           = 3300,
+                .div            = 1024,
+        },
+};
+
 /* Standard BAST devices */
+// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
 
 static struct platform_device *bast_devices[] __initdata = {
         &s3c_device_usb,
@@ -556,6 +586,8 @@ static struct platform_device *bast_devices[] __initdata = {
         &s3c_device_i2c0,
         &s3c_device_rtc,
         &s3c_device_nand,
+        &s3c_device_adc,
+        &s3c_device_hwmon,
         &bast_device_dm9k,
         &bast_device_asix,
         &bast_device_axpp,
@@ -570,6 +602,12 @@ static struct clk *bast_clocks[] __initdata = {
         &s3c24xx_uclk,
 };
 
+static struct s3c_cpufreq_board __initdata bast_cpufreq = {
+        .refresh        = 7800, /* 7.8usec */
+        .auto_io        = 1,
+        .need_io        = 1,
+};
+
 static void __init bast_map_io(void)
 {
         /* initialise the clocks */
@@ -588,6 +626,7 @@ static void __init bast_map_io(void)
         s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
 
         s3c_device_nand.dev.platform_data = &bast_nand_info;
+        s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
 
         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
         s3c24xx_init_clocks(0);
@@ -608,6 +647,8 @@ static void __init bast_init(void)
 
         usb_simtec_init();
         nor_simtec_init();
+
+        s3c_cpufreq_setboard(&bast_cpufreq);
 }
 
 MACHINE_START(BAST, "Simtec-BAST")
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c
new file mode 100644
index 000000000000..f178c2fd9d85
--- /dev/null
+++ b/arch/arm/mach-s3c2410/pll.c
@@ -0,0 +1,95 @@
+/* arch/arm/mach-s3c2410/pll.c
+ *
+ * Copyright (c) 2006,2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@arm.linux.org.uk>
+ *
+ * S3C2410 CPU PLL tables
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sysdev.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+
+static struct cpufreq_frequency_table pll_vals_12MHz[] = {
+    { .frequency = 34000000,  .index = PLLVAL(82, 2, 3),   },
+    { .frequency = 45000000,  .index = PLLVAL(82, 1, 3),   },
+    { .frequency = 51000000,  .index = PLLVAL(161, 3, 3),  },
+    { .frequency = 48000000,  .index = PLLVAL(120, 2, 3),  },
+    { .frequency = 56000000,  .index = PLLVAL(142, 2, 3),  },
+    { .frequency = 68000000,  .index = PLLVAL(82, 2, 2),   },
+    { .frequency = 79000000,  .index = PLLVAL(71, 1, 2),   },
+    { .frequency = 85000000,  .index = PLLVAL(105, 2, 2),  },
+    { .frequency = 90000000,  .index = PLLVAL(112, 2, 2),  },
+    { .frequency = 101000000, .index = PLLVAL(127, 2, 2),  },
+    { .frequency = 113000000, .index = PLLVAL(105, 1, 2),  },
+    { .frequency = 118000000, .index = PLLVAL(150, 2, 2),  },
+    { .frequency = 124000000, .index = PLLVAL(116, 1, 2),  },
+    { .frequency = 135000000, .index = PLLVAL(82, 2, 1),   },
+    { .frequency = 147000000, .index = PLLVAL(90, 2, 1),   },
+    { .frequency = 152000000, .index = PLLVAL(68, 1, 1),   },
+    { .frequency = 158000000, .index = PLLVAL(71, 1, 1),   },
+    { .frequency = 170000000, .index = PLLVAL(77, 1, 1),   },
+    { .frequency = 180000000, .index = PLLVAL(82, 1, 1),   },
+    { .frequency = 186000000, .index = PLLVAL(85, 1, 1),   },
+    { .frequency = 192000000, .index = PLLVAL(88, 1, 1),   },
+    { .frequency = 203000000, .index = PLLVAL(161, 3, 1),  },
+
+    /* 2410A extras */
+
+    { .frequency = 210000000, .index = PLLVAL(132, 2, 1),  },
+    { .frequency = 226000000, .index = PLLVAL(105, 1, 1),  },
+    { .frequency = 266000000, .index = PLLVAL(125, 1, 1),  },
+    { .frequency = 268000000, .index = PLLVAL(126, 1, 1),  },
+    { .frequency = 270000000, .index = PLLVAL(127, 1, 1),  },
+};
+
+static int s3c2410_plls_add(struct sys_device *dev)
+{
+        return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
+}
+
+static struct sysdev_driver s3c2410_plls_drv = {
+        .add    = s3c2410_plls_add,
+};
+
+static int __init s3c2410_pll_init(void)
+{
+        return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_plls_drv);
+
+}
+
+arch_initcall(s3c2410_pll_init);
+
+static struct sysdev_driver s3c2410a_plls_drv = {
+        .add    = s3c2410_plls_add,
+};
+
+static int __init s3c2410a_pll_init(void)
+{
+        return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_plls_drv);
+}
+
+arch_initcall(s3c2410a_pll_init);
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index 143e08a599d4..966119c8efee 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -119,6 +119,18 @@ static int __init s3c2410_pm_drvinit(void)
 }
 
 arch_initcall(s3c2410_pm_drvinit);
+
+static struct sysdev_driver s3c2410a_pm_driver = {
+        .add            = s3c2410_pm_add,
+        .resume         = s3c2410_pm_resume,
+};
+
+static int __init s3c2410a_pm_drvinit(void)
+{
+        return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_pm_driver);
+}
+
+arch_initcall(s3c2410a_pm_drvinit);
 #endif
 
 #if defined(CONFIG_CPU_S3C2440)
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index feb141b1f915..91ba42f688ac 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -105,17 +105,33 @@ void __init_or_cpufreq s3c2410_setup_clocks(void)
         s3c24xx_setup_clocks(fclk, hclk, pclk);
 }
 
+/* fake ARMCLK for use with cpufreq, etc. */
+
+static struct clk s3c2410_armclk = {
+        .name   = "armclk",
+        .parent = &clk_f,
+        .id     = -1,
+};
+
 void __init s3c2410_init_clocks(int xtal)
 {
         s3c24xx_register_baseclocks(xtal);
         s3c2410_setup_clocks();
         s3c2410_baseclk_add();
+        s3c24xx_register_clock(&s3c2410_armclk);
 }
 
 struct sysdev_class s3c2410_sysclass = {
         .name = "s3c2410-core",
 };
 
+/* Note, we would have liked to name this s3c2410-core, but we cannot
+ * register two sysdev_class with the same name.
+ */
+struct sysdev_class s3c2410a_sysclass = {
+        .name = "s3c2410a-core",
+};
+
 static struct sys_device s3c2410_sysdev = {
         .cls            = &s3c2410_sysclass,
 };
@@ -133,9 +149,22 @@ static int __init s3c2410_core_init(void)
 
 core_initcall(s3c2410_core_init);
 
+static int __init s3c2410a_core_init(void)
+{
+        return sysdev_class_register(&s3c2410a_sysclass);
+}
+
+core_initcall(s3c2410a_core_init);
+
 int __init s3c2410_init(void)
 {
         printk("S3C2410: Initialising architecture\n");
 
         return sysdev_register(&s3c2410_sysdev);
 }
+
+int __init s3c2410a_init(void)
+{
+        s3c2410_sysdev.cls = &s3c2410a_sysclass;
+        return s3c2410_init();
+}
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index 63586ffd0ae7..35c1bde89cf2 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -32,6 +32,15 @@ config S3C2412_PM
         help
           Internal config node to apply S3C2412 power management
 
+# Note, the S3C2412 IOtiming support is in plat-s3c24xx
+
+config S3C2412_CPUFREQ
+        bool
+        depends on CPU_FREQ_S3C24XX && CPU_S3C2412
+        select S3C2412_IOTIMING
+        default y
+        help
+          CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
 
 menu "S3C2412 Machines"
 
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 20918d5dc6a9..530ec46cbaea 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CPU_S3C2412)	+= clock.o
 obj-$(CONFIG_CPU_S3C2412)       += gpio.o
 obj-$(CONFIG_S3C2412_DMA)       += dma.o
 obj-$(CONFIG_S3C2412_PM)        += pm.o sleep.o
+obj-$(CONFIG_S3C2412_CPUFREQ)   += cpu-freq.o
 
 # Machine support
 
diff --git a/arch/arm/mach-s3c2412/cpu-freq.c b/arch/arm/mach-s3c2412/cpu-freq.c
new file mode 100644
index 000000000000..eb3ea1721335
--- /dev/null
+++ b/arch/arm/mach-s3c2412/cpu-freq.c
@@ -0,0 +1,257 @@
+/* linux/arch/arm/mach-s3c2412/cpu-freq.c
+ *
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2412 CPU Frequency scalling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/sysdev.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-s3c2412-mem.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/cpu-freq-core.h>
+
+/* our clock resources. */
+static struct clk *xtal;
+static struct clk *fclk;
+static struct clk *hclk;
+static struct clk *armclk;
+
+/* HDIV: 1, 2, 3, 4, 6, 8 */
+
+static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned int hdiv, pdiv, armdiv, dvs;
+        unsigned long hclk, fclk, armclk, armdiv_clk;
+        unsigned long hclk_max;
+
+        fclk = cfg->freq.fclk;
+        armclk = cfg->freq.armclk;
+        hclk_max = cfg->max.hclk;
+
+        /* We can't run hclk above armclk as at the best we have to
+         * have armclk and hclk in dvs mode. */
+
+        if (hclk_max > armclk)
+                hclk_max = armclk;
+
+        s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n",
+                     __func__, fclk, armclk, hclk_max);
+        s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n",
+                     __func__, cfg->freq.fclk, cfg->freq.armclk,
+                     cfg->freq.hclk, cfg->freq.pclk);
+
+        armdiv = fclk / armclk;
+
+        if (armdiv < 1)
+                armdiv = 1;
+        if (armdiv > 2)
+                armdiv = 2;
+
+        cfg->divs.arm_divisor = armdiv;
+        armdiv_clk = fclk / armdiv;
+
+        hdiv = armdiv_clk / hclk_max;
+        if (hdiv < 1)
+                hdiv = 1;
+
+        cfg->freq.hclk = hclk = armdiv_clk / hdiv;
+
+        /* set dvs depending on whether we reached armclk or not. */
+        cfg->divs.dvs = dvs = armclk < armdiv_clk;
+
+        /* update the actual armclk we achieved. */
+        cfg->freq.armclk = dvs ? hclk : armdiv_clk;
+
+        s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n",
+                     __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs);
+
+        if (hdiv > 4)
+                goto invalid;
+
+        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
+
+        if ((hclk / pdiv) > cfg->max.pclk)
+                pdiv++;
+
+        cfg->freq.pclk = hclk / pdiv;
+
+        s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
+
+        if (pdiv > 2)
+                goto invalid;
+
+        pdiv *= hdiv;
+
+        /* store the result, and then return */
+
+        cfg->divs.h_divisor = hdiv * armdiv;
+        cfg->divs.p_divisor = pdiv * armdiv;
+
+        return 0;
+
+ invalid:
+        return -EINVAL;
+}
+
+static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long clkdiv;
+        unsigned long olddiv;
+
+        olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN);
+
+        /* clear off current clock info */
+
+        clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN;
+        clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK;
+        clkdiv &= ~S3C2412_CLKDIVN_PDIVN;
+
+        if (cfg->divs.arm_divisor == 2)
+                clkdiv |= S3C2412_CLKDIVN_ARMDIVN;
+
+        clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1);
+
+        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
+                clkdiv |= S3C2412_CLKDIVN_PDIVN;
+
+        s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
+        __raw_writel(clkdiv, S3C2410_CLKDIVN);
+
+        clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
+}
+
+static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
+{
+        struct s3c_cpufreq_board *board = cfg->board;
+        unsigned long refresh;
+
+        s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__,
+                     board->refresh, cfg->freq.hclk);
+
+        /* Reduce both the refresh time (in ns) and the frequency (in MHz)
+         * by 10 each to ensure that we do not overflow 32 bit numbers. This
+         * should work for HCLK up to 133MHz and refresh period up to 30usec.
+         */
+
+        refresh = (board->refresh / 10);
+        refresh *= (cfg->freq.hclk / 100);
+        refresh /= (1 * 1000 * 1000);   /* 10^6 */
+
+        s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh);
+        __raw_writel(refresh, S3C2412_REFRESH);
+}
+
+/* set the default cpu frequency information, based on an 200MHz part
+ * as we have no other way of detecting the speed rating in software.
+ */
+
+static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
+        .max            = {
+                .fclk   = 200000000,
+                .hclk   = 100000000,
+                .pclk   =  50000000,
+        },
+
+        .latency        = 5000000, /* 5ms */
+
+        .locktime_m     = 150,
+        .locktime_u     = 150,
+        .locktime_bits  = 16,
+
+        .name           = "s3c2412",
+        .set_refresh    = s3c2412_cpufreq_setrefresh,
+        .set_divs       = s3c2412_cpufreq_setdivs,
+        .calc_divs      = s3c2412_cpufreq_calcdivs,
+
+        .calc_iotiming  = s3c2412_iotiming_calc,
+        .set_iotiming   = s3c2412_iotiming_set,
+        .get_iotiming   = s3c2412_iotiming_get,
+
+        .resume_clocks  = s3c2412_setup_clocks,
+
+        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
+};
+
+static int s3c2412_cpufreq_add(struct sys_device *sysdev)
+{
+        unsigned long fclk_rate;
+
+        hclk = clk_get(NULL, "hclk");
+        if (IS_ERR(hclk)) {
+                printk(KERN_ERR "%s: cannot find hclk clock\n", __func__);
+                return -ENOENT;
+        }
+
+        fclk = clk_get(NULL, "fclk");
+        if (IS_ERR(fclk)) {
+                printk(KERN_ERR "%s: cannot find fclk clock\n", __func__);
+                goto err_fclk;
+        }
+
+        fclk_rate = clk_get_rate(fclk);
+        if (fclk_rate > 200000000) {
+                printk(KERN_INFO
+                       "%s: fclk %ld MHz, assuming 266MHz capable part\n",
+                       __func__, fclk_rate / 1000000);
+                s3c2412_cpufreq_info.max.fclk = 266000000;
+                s3c2412_cpufreq_info.max.hclk = 133000000;
+                s3c2412_cpufreq_info.max.pclk =  66000000;
+        }
+
+        armclk = clk_get(NULL, "armclk");
+        if (IS_ERR(armclk)) {
+                printk(KERN_ERR "%s: cannot find arm clock\n", __func__);
+                goto err_armclk;
+        }
+
+        xtal = clk_get(NULL, "xtal");
+        if (IS_ERR(xtal)) {
+                printk(KERN_ERR "%s: cannot find xtal clock\n", __func__);
+                goto err_xtal;
+        }
+
+        return s3c_cpufreq_register(&s3c2412_cpufreq_info);
+
+err_xtal:
+        clk_put(armclk);
+err_armclk:
+        clk_put(fclk);
+err_fclk:
+        clk_put(hclk);
+
+        return -ENOENT;
+}
+
+static struct sysdev_driver s3c2412_cpufreq_driver = {
+        .add            = s3c2412_cpufreq_add,
+};
+
+static int s3c2412_cpufreq_init(void)
+{
+        return sysdev_driver_register(&s3c2412_sysclass,
+                                      &s3c2412_cpufreq_driver);
+}
+
+arch_initcall(s3c2412_cpufreq_init);
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index 5b5aba69ec3f..bef39f77729d 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -69,6 +69,18 @@ static struct map_desc s3c2412_iodesc[] __initdata = {
         IODESC_ENT(CLKPWR),
         IODESC_ENT(TIMER),
         IODESC_ENT(WATCHDOG),
+        {
+                .virtual = (unsigned long)S3C2412_VA_SSMC,
+                .pfn     = __phys_to_pfn(S3C2412_PA_SSMC),
+                .length  = SZ_1M,
+                .type    = MT_DEVICE,
+        },
+        {
+                .virtual = (unsigned long)S3C2412_VA_EBI,
+                .pfn     = __phys_to_pfn(S3C2412_PA_EBI),
+                .length  = SZ_1M,
+                .type    = MT_DEVICE,
+        },
 };
 
 /* uart registration process */
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 8cfeaec37306..8ae1b288f7fa 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -33,6 +33,7 @@ config MACH_ANUBIS
         select PM_SIMTEC if PM
         select HAVE_PATA_PLATFORM
         select S3C24XX_GPIO_EXTRA64
+        select S3C2440_XTAL_12000000
         select S3C_DEV_USB_HOST
         help
           Say Y here if you are using the Simtec Electronics ANUBIS
@@ -44,6 +45,8 @@ config MACH_OSIRIS
         select S3C24XX_DCLK
         select PM_SIMTEC if PM
         select S3C24XX_GPIO_EXTRA128
+        select S3C2440_XTAL_12000000
+        select S3C2410_IOTIMING if S3C2440_CPUFREQ
         select S3C_DEV_USB_HOST
         help
           Say Y here if you are using the Simtec IM2440D20 module, also
@@ -52,6 +55,7 @@ config MACH_OSIRIS
 config MACH_RX3715
         bool "HP iPAQ rx3715"
         select CPU_S3C2440
+        select S3C2440_XTAL_16934400
         select PM_H1940 if PM
         help
           Say Y here if you are using the HP iPAQ rx3715.
@@ -59,6 +63,7 @@ config MACH_RX3715
 config ARCH_S3C2440
         bool "SMDK2440"
         select CPU_S3C2440
+        select S3C2440_XTAL_16934400
         select MACH_SMDK
         select S3C_DEV_USB_HOST
         help
@@ -67,6 +72,7 @@ config ARCH_S3C2440
 config MACH_NEXCODER_2440
         bool "NexVision NEXCODER 2440 Light Board"
         select CPU_S3C2440
+        select S3C2440_XTAL_12000000
         select S3C_DEV_USB_HOST
         help
           Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
@@ -75,6 +81,7 @@ config SMDK2440_CPU2440
         bool "SMDK2440 with S3C2440 CPU module"
         depends on ARCH_S3C2440
         default y if ARCH_S3C2440
+        select S3C2440_XTAL_16934400
         select CPU_S3C2440
 
 config MACH_AT2440EVB
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index cba064b49a64..2105a41281a4 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -34,6 +34,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
+#include <plat/cpu-freq.h>
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-mem.h>
@@ -351,6 +352,12 @@ static struct clk *osiris_clocks[] __initdata = {
         &s3c24xx_uclk,
 };
 
+static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
+        .refresh        = 7800, /* refresh period is 7.8usec */
+        .auto_io        = 1,
+        .need_io        = 1,
+};
+
 static void __init osiris_map_io(void)
 {
         unsigned long flags;
@@ -402,6 +409,8 @@ static void __init osiris_init(void)
 
         s3c_i2c0_set_platdata(NULL);
 
+        s3c_cpufreq_setboard(&osiris_cpufreq);
+
         i2c_register_board_info(0, osiris_i2c_devs,
                                 ARRAY_SIZE(osiris_i2c_devs));
 
diff --git a/arch/arm/mach-s3c24a0/include/mach/map.h b/arch/arm/mach-s3c24a0/include/mach/map.h
index a01132717e34..79e4d93ea2b6 100644
--- a/arch/arm/mach-s3c24a0/include/mach/map.h
+++ b/arch/arm/mach-s3c24a0/include/mach/map.h
@@ -81,5 +81,6 @@
 
 #define S3C_PA_UART             S3C24A0_PA_UART
 #define S3C_PA_IIC              S3C24A0_PA_IIC
+#define S3C_PA_NAND             S3C24XX_PA_NAND
 
 #endif /* __ASM_ARCH_24A0_MAP_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h
index 5057d9948d35..fc8b223bad4f 100644
--- a/arch/arm/mach-s3c6400/include/mach/map.h
+++ b/arch/arm/mach-s3c6400/include/mach/map.h
@@ -38,18 +38,21 @@
 #define S3C_VA_UART2            S3C_VA_UARTx(2)
 #define S3C_VA_UART3            S3C_VA_UARTx(3)
 
+#define S3C64XX_PA_NAND         (0x70200000)
 #define S3C64XX_PA_FB           (0x77100000)
 #define S3C64XX_PA_USB_HSOTG    (0x7C000000)
 #define S3C64XX_PA_WATCHDOG     (0x7E004000)
 #define S3C64XX_PA_SYSCON       (0x7E00F000)
+#define S3C64XX_PA_AC97         (0x7F001000)
 #define S3C64XX_PA_IIS0         (0x7F002000)
 #define S3C64XX_PA_IIS1         (0x7F003000)
 #define S3C64XX_PA_TIMER        (0x7F006000)
 #define S3C64XX_PA_IIC0         (0x7F004000)
+#define S3C64XX_PA_IISV4        (0x7F00D000)
 #define S3C64XX_PA_IIC1         (0x7F00F000)
 
 #define S3C64XX_PA_GPIO         (0x7F008000)
-#define S3C64XX_VA_GPIO         S3C_ADDR(0x00500000)
+#define S3C64XX_VA_GPIO         S3C_ADDR_CPU(0x00000000)
 #define S3C64XX_SZ_GPIO         SZ_4K
 
 #define S3C64XX_PA_SDRAM        (0x50000000)
@@ -57,7 +60,7 @@
 #define S3C64XX_PA_VIC1         (0x71300000)
 
 #define S3C64XX_PA_MODEM        (0x74108000)
-#define S3C64XX_VA_MODEM        S3C_ADDR(0x00600000)
+#define S3C64XX_VA_MODEM        S3C_ADDR_CPU(0x00100000)
 
 #define S3C64XX_PA_USBHOST      (0x74300000)
 
@@ -72,6 +75,7 @@
 #define S3C_PA_HSMMC2           S3C64XX_PA_HSMMC2
 #define S3C_PA_IIC              S3C64XX_PA_IIC0
 #define S3C_PA_IIC1             S3C64XX_PA_IIC1
+#define S3C_PA_NAND             S3C64XX_PA_NAND
 #define S3C_PA_FB               S3C64XX_PA_FB
 #define S3C_PA_USBHOST          S3C64XX_PA_USBHOST
 #define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c6400/s3c6400.c
index 1ece887d90bb..b42bdd0f2138 100644
--- a/arch/arm/mach-s3c6400/s3c6400.c
+++ b/arch/arm/mach-s3c6400/s3c6400.c
@@ -48,6 +48,8 @@ void __init s3c6400_map_io(void)
 
         /* the i2c devices are directly compatible with s3c2440 */
         s3c_i2c0_setname("s3c2440-i2c");
+
+        s3c_device_nand.name = "s3c6400-nand";
 }
 
 void __init s3c6400_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c6410/Kconfig b/arch/arm/mach-s3c6410/Kconfig
index e63aac7f4e5a..f9d0f09f9761 100644
--- a/arch/arm/mach-s3c6410/Kconfig
+++ b/arch/arm/mach-s3c6410/Kconfig
@@ -97,3 +97,13 @@ config MACH_NCP
         select S3C64XX_SETUP_I2C1
         help
           Machine support for the Samsung NCP
+
+config MACH_HMT
+        bool "Airgoo HMT"
+        select CPU_S3C6410
+        select S3C_DEV_FB
+        select S3C_DEV_USB_HOST
+        select S3C64XX_SETUP_FB_24BPP
+        select HAVE_PWM
+        help
+          Machine support for the Airgoo HMT
diff --git a/arch/arm/mach-s3c6410/Makefile b/arch/arm/mach-s3c6410/Makefile
index 6f9deac88612..3e48c3dbf973 100644
--- a/arch/arm/mach-s3c6410/Makefile
+++ b/arch/arm/mach-s3c6410/Makefile
@@ -23,5 +23,4 @@ obj-$(CONFIG_S3C6410_SETUP_SDHCI)	+= setup-sdhci.o
 obj-$(CONFIG_MACH_ANW6410)      += mach-anw6410.o
 obj-$(CONFIG_MACH_SMDK6410)     += mach-smdk6410.o
 obj-$(CONFIG_MACH_NCP)          += mach-ncp.o
-
-
+obj-$(CONFIG_MACH_HMT)          += mach-hmt.o
diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c
index ade904de8895..9b67c663d9d8 100644
--- a/arch/arm/mach-s3c6410/cpu.c
+++ b/arch/arm/mach-s3c6410/cpu.c
@@ -62,6 +62,8 @@ void __init s3c6410_map_io(void)
         /* the i2c devices are directly compatible with s3c2440 */
         s3c_i2c0_setname("s3c2440-i2c");
         s3c_i2c1_setname("s3c2440-i2c");
+
+        s3c_device_nand.name = "s3c6400-nand";
 }
 
 void __init s3c6410_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c6410/mach-hmt.c b/arch/arm/mach-s3c6410/mach-hmt.c
new file mode 100644
index 000000000000..c5741056193f
--- /dev/null
+++ b/arch/arm/mach-s3c6410/mach-hmt.c
@@ -0,0 +1,276 @@
+/* mach-hmt.c - Platform code for Airgoo HMT
+ *
+ * Copyright 2009 Peter Korsgaard <jacmet@sunsite.dk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/leds.h>
+#include <linux/pwm_backlight.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-fb.h>
+#include <mach/map.h>
+
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <plat/iic.h>
+#include <plat/fb.h>
+#include <plat/nand.h>
+
+#include <plat/s3c6410.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
+#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+
+static struct s3c2410_uartcfg hmt_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+};
+
+static int hmt_bl_init(struct device *dev)
+{
+        int ret;
+
+        ret = gpio_request(S3C64XX_GPB(4), "lcd backlight enable");
+        if (!ret)
+                ret = gpio_direction_output(S3C64XX_GPB(4), 0);
+
+        return ret;
+}
+
+static int hmt_bl_notify(int brightness)
+{
+        /*
+         * translate from CIELUV/CIELAB L*->brightness, E.G. from
+         * perceived luminance to light output. Assumes range 0..25600
+         */
+        if (brightness < 0x800) {
+                /* Y = Yn * L / 903.3 */
+                brightness = (100*256 * brightness + 231245/2) / 231245;
+        } else {
+                /* Y = Yn * ((L + 16) / 116 )^3 */
+                int t = (brightness*4 + 16*1024 + 58)/116;
+                brightness = 25 * ((t * t * t + 0x100000/2) / 0x100000);
+        }
+
+        gpio_set_value(S3C64XX_GPB(4), brightness);
+
+        return brightness;
+}
+
+static void hmt_bl_exit(struct device *dev)
+{
+        gpio_free(S3C64XX_GPB(4));
+}
+
+static struct platform_pwm_backlight_data hmt_backlight_data = {
+        .pwm_id         = 1,
+        .max_brightness = 100 * 256,
+        .dft_brightness = 40 * 256,
+        .pwm_period_ns  = 1000000000 / (100 * 256 * 20),
+        .init           = hmt_bl_init,
+        .notify         = hmt_bl_notify,
+        .exit           = hmt_bl_exit,
+
+};
+
+static struct platform_device hmt_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent = &s3c_device_timer[1].dev,
+                .platform_data = &hmt_backlight_data,
+        },
+};
+
+static struct s3c_fb_pd_win hmt_fb_win0 = {
+        .win_mode       = {
+                .pixclock       = 41094,
+                .left_margin    = 8,
+                .right_margin   = 13,
+                .upper_margin   = 7,
+                .lower_margin   = 5,
+                .hsync_len      = 3,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp        = 32,
+        .default_bpp    = 16,
+};
+
+/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
+static struct s3c_fb_platdata hmt_lcd_pdata __initdata = {
+        .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
+        .win[0]         = &hmt_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+};
+
+static struct mtd_partition hmt_nand_part[] = {
+        [0] = {
+                .name   = "uboot",
+                .size   = SZ_512K,
+                .offset = 0,
+        },
+        [1] = {
+                .name   = "uboot-env1",
+                .size   = SZ_256K,
+                .offset = SZ_512K,
+        },
+        [2] = {
+                .name   = "uboot-env2",
+                .size   = SZ_256K,
+                .offset = SZ_512K + SZ_256K,
+        },
+        [3] = {
+                .name   = "kernel",
+                .size   = SZ_2M,
+                .offset = SZ_1M,
+        },
+        [4] = {
+                .name   = "rootfs",
+                .size   = MTDPART_SIZ_FULL,
+                .offset = SZ_1M + SZ_2M,
+        },
+};
+
+static struct s3c2410_nand_set hmt_nand_sets[] = {
+        [0] = {
+                .name           = "nand",
+                .nr_chips       = 1,
+                .nr_partitions  = ARRAY_SIZE(hmt_nand_part),
+                .partitions     = hmt_nand_part,
+        },
+};
+
+static struct s3c2410_platform_nand hmt_nand_info = {
+        .tacls          = 25,
+        .twrph0         = 55,
+        .twrph1         = 40,
+        .nr_sets        = ARRAY_SIZE(hmt_nand_sets),
+        .sets           = hmt_nand_sets,
+};
+
+static struct gpio_led hmt_leds[] = {
+        { /* left function keys */
+                .name                   = "left:blue",
+                .gpio                   = S3C64XX_GPO(12),
+                .default_trigger        = "default-on",
+        },
+        { /* right function keys - red */
+                .name                   = "right:red",
+                .gpio                   = S3C64XX_GPO(13),
+        },
+        { /* right function keys - green */
+                .name                   = "right:green",
+                .gpio                   = S3C64XX_GPO(14),
+        },
+        { /* right function keys - blue */
+                .name                   = "right:blue",
+                .gpio                   = S3C64XX_GPO(15),
+                .default_trigger        = "default-on",
+        },
+};
+
+static struct gpio_led_platform_data hmt_led_data = {
+        .num_leds = ARRAY_SIZE(hmt_leds),
+        .leds = hmt_leds,
+};
+
+static struct platform_device hmt_leds_device = {
+        .name                   = "leds-gpio",
+        .id                     = -1,
+        .dev.platform_data      = &hmt_led_data,
+};
+
+static struct map_desc hmt_iodesc[] = {};
+
+static struct platform_device *hmt_devices[] __initdata = {
+        &s3c_device_i2c0,
+        &s3c_device_nand,
+        &s3c_device_fb,
+        &s3c_device_usb,
+        &s3c_device_timer[1],
+        &hmt_backlight_device,
+        &hmt_leds_device,
+};
+
+static void __init hmt_map_io(void)
+{
+        s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
+}
+
+static void __init hmt_machine_init(void)
+{
+        s3c_i2c0_set_platdata(NULL);
+        s3c_fb_set_platdata(&hmt_lcd_pdata);
+        s3c_device_nand.dev.platform_data = &hmt_nand_info;
+
+        gpio_request(S3C64XX_GPC(7), "usb power");
+        gpio_direction_output(S3C64XX_GPC(7), 0);
+        gpio_request(S3C64XX_GPM(0), "usb power");
+        gpio_direction_output(S3C64XX_GPM(0), 1);
+        gpio_request(S3C64XX_GPK(7), "usb power");
+        gpio_direction_output(S3C64XX_GPK(7), 1);
+        gpio_request(S3C64XX_GPF(13), "usb power");
+        gpio_direction_output(S3C64XX_GPF(13), 1);
+
+        platform_add_devices(hmt_devices, ARRAY_SIZE(hmt_devices));
+}
+
+MACHINE_START(HMT, "Airgoo-HMT")
+        /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
+        .phys_io        = S3C_PA_UART & 0xfff00000,
+        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .init_irq       = s3c6410_init_irq,
+        .map_io         = hmt_map_io,
+        .init_machine   = hmt_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c6410/mach-ncp.c b/arch/arm/mach-s3c6410/mach-ncp.c
index 6030636f8548..55e9bbfaf68b 100644
--- a/arch/arm/mach-s3c6410/mach-ncp.c
+++ b/arch/arm/mach-s3c6410/mach-ncp.c
@@ -79,7 +79,7 @@ static struct platform_device *ncp_devices[] __initdata = {
         &s3c_device_i2c0,
 };
 
-struct map_desc ncp_iodesc[] = {};
+static struct map_desc ncp_iodesc[] __initdata = {};
 
 static void __init ncp_map_io(void)
 {
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
index bc9a7dea567f..ea51dbe76e3e 100644
--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
+++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
@@ -65,16 +65,30 @@ static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
         [0] = {
                 .hwport      = 0,
                 .flags       = 0,
-                .ucon        = 0x3c5,
-                .ulcon       = 0x03,
-                .ufcon       = 0x51,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
         },
         [1] = {
                 .hwport      = 1,
                 .flags       = 0,
-                .ucon        = 0x3c5,
-                .ulcon       = 0x03,
-                .ufcon       = 0x51,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [3] = {
+                .hwport      = 3,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
         },
 };
 
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
new file mode 100644
index 000000000000..b1a4ba504416
--- /dev/null
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -0,0 +1,22 @@
+# arch/arm/mach-s5pc100/Kconfig
+#
+# Copyright 2009 Samsung Electronics Co.
+#       Byungho Min <bhmin@samsung.com>
+#
+# Licensed under GPLv2
+
+# Configuration options for the S5PC100 CPU
+
+config CPU_S5PC100
+        bool
+        select CPU_S5PC100_INIT
+        select CPU_S5PC100_CLOCK
+        help
+          Enable S5PC100 CPU support
+
+config MACH_SMDKC100
+        bool "SMDKC100"
+        select CPU_S5PC100
+        select S5PC1XX_SETUP_I2C1
+        help
+          Machine support for the Samsung SMDKC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
new file mode 100644
index 000000000000..afc89b381d7a
--- /dev/null
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -0,0 +1,17 @@
+# arch/arm/mach-s5pc100/Makefile
+#
+# Copyright 2009 Samsung Electronics Co.
+#
+# Licensed under GPLv2
+
+obj-y                           :=
+obj-m                           :=
+obj-n                           :=
+obj-                            :=
+
+# Core support for S5PC100 system
+
+obj-$(CONFIG_CPU_S5PC100)       += cpu.o
+
+# machine support
+obj-$(CONFIG_MACH_SMDKC100)     += mach-smdkc100.o
diff --git a/arch/arm/mach-s5pc100/Makefile.boot b/arch/arm/mach-s5pc100/Makefile.boot
new file mode 100644
index 000000000000..ff90aa13bd67
--- /dev/null
+++ b/arch/arm/mach-s5pc100/Makefile.boot
@@ -0,0 +1,2 @@
+   zreladdr-y   := 0x20008000
+params_phys-y   := 0x20000100
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
new file mode 100644
index 000000000000..0e718890da32
--- /dev/null
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -0,0 +1,97 @@
+/* linux/arch/arm/mach-s5pc100/cpu.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Based on mach-s3c6410/cpu.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <asm/irq.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/regs-serial.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/sdhci.h>
+#include <plat/iic-core.h>
+#include <plat/s5pc100.h>
+
+/* Initial IO mappings */
+
+static struct map_desc s5pc100_iodesc[] __initdata = {
+};
+
+/* s5pc100_map_io
+ *
+ * register the standard cpu IO areas
+*/
+
+void __init s5pc100_map_io(void)
+{
+        iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
+
+        /* initialise device information early */
+}
+
+void __init s5pc100_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
+        s3c24xx_register_baseclocks(xtal);
+        s5pc1xx_register_clocks();
+        s5pc100_register_clocks();
+        s5pc100_setup_clocks();
+}
+
+void __init s5pc100_init_irq(void)
+{
+        u32 vic_valid[] = {~0, ~0, ~0};
+
+        /* VIC0, VIC1, and VIC2 are fully populated. */
+        s5pc1xx_init_irq(vic_valid, ARRAY_SIZE(vic_valid));
+}
+
+struct sysdev_class s5pc100_sysclass = {
+        .name   = "s5pc100-core",
+};
+
+static struct sys_device s5pc100_sysdev = {
+        .cls    = &s5pc100_sysclass,
+};
+
+static int __init s5pc100_core_init(void)
+{
+        return sysdev_class_register(&s5pc100_sysclass);
+}
+
+core_initcall(s5pc100_core_init);
+
+int __init s5pc100_init(void)
+{
+        printk(KERN_DEBUG "S5PC100: Initialising architecture\n");
+
+        return sysdev_register(&s5pc100_sysdev);
+}
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
new file mode 100644
index 000000000000..9d142ccf654b
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
@@ -0,0 +1,38 @@
+/* arch/arm/mach-s5pc100/include/mach/debug-macro.S
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ *
+ * Based on mach-s3c6400/include/mach/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* pull in the relevant register and map files. */
+
+#include <mach/map.h>
+#include <plat/regs-serial.h>
+
+        /* note, for the boot process to work we have to keep the UART
+         * virtual address aligned to an 1MiB boundary for the L1
+         * mapping the head code makes. We keep the UART virtual address
+         * aligned and add in the offset when we load the value here.
+         */
+
+        .macro addruart, rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1
+                ldreq   \rx, = S3C_PA_UART
+                ldrne   \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
+                add     \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
+        .endm
+
+/* include the reset of the code which will do the work, we're only
+ * compiling for a single cpu processor type so the default of s3c2440
+ * will be fine with us.
+ */
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
new file mode 100644
index 000000000000..67131939e626
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
@@ -0,0 +1,50 @@
+/* arch/arm/mach-s5pc100/include/mach/entry-macro.S
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Based on mach-s3c6400/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for the Samsung S5PC1XX series
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+#include <asm/hardware/vic.h>
+#include <mach/map.h>
+#include <plat/irqs.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =S3C_VA_VIC0
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+        @ check the vic0
+        mov     \irqnr, # S3C_IRQ_OFFSET + 31
+        ldr     \irqstat, [ \base, # VIC_IRQ_STATUS ]
+        teq     \irqstat, #0
+
+        @ otherwise try vic1
+        addeq   \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0)
+        addeq   \irqnr, \irqnr, #32
+        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
+        teqeq   \irqstat, #0
+
+        @ otherwise try vic2
+        addeq   \tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0)
+        addeq   \irqnr, \irqnr, #32
+        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
+        teqeq   \irqstat, #0
+
+        clzne   \irqstat, \irqstat
+        subne   \irqnr, \irqnr, \irqstat
+        .endm
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio-core.h b/arch/arm/mach-s5pc100/include/mach/gpio-core.h
new file mode 100644
index 000000000000..ad28d8ec8a78
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/gpio-core.h
@@ -0,0 +1,21 @@
+/* arch/arm/mach-s5pc100/include/mach/gpio-core.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - GPIO core support
+ *
+ * Based on mach-s3c6400/include/mach/gpio-core.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_CORE_H
+#define __ASM_ARCH_GPIO_CORE_H __FILE__
+
+/* currently we just include the platform support */
+#include <plat/gpio-core.h>
+
+#endif /* __ASM_ARCH_GPIO_CORE_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
new file mode 100644
index 000000000000..c74fc93d7d15
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -0,0 +1,146 @@
+/* arch/arm/mach-s5pc100/include/mach/gpio.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - GPIO lib support
+ *
+ * Base on mach-s3c6400/include/mach/gpio.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+
+/* GPIO bank sizes */
+#define S5PC1XX_GPIO_A0_NR      (8)
+#define S5PC1XX_GPIO_A1_NR      (5)
+#define S5PC1XX_GPIO_B_NR       (8)
+#define S5PC1XX_GPIO_C_NR       (5)
+#define S5PC1XX_GPIO_D_NR       (7)
+#define S5PC1XX_GPIO_E0_NR      (8)
+#define S5PC1XX_GPIO_E1_NR      (6)
+#define S5PC1XX_GPIO_F0_NR      (8)
+#define S5PC1XX_GPIO_F1_NR      (8)
+#define S5PC1XX_GPIO_F2_NR      (8)
+#define S5PC1XX_GPIO_F3_NR      (4)
+#define S5PC1XX_GPIO_G0_NR      (8)
+#define S5PC1XX_GPIO_G1_NR      (3)
+#define S5PC1XX_GPIO_G2_NR      (7)
+#define S5PC1XX_GPIO_G3_NR      (7)
+#define S5PC1XX_GPIO_H0_NR      (8)
+#define S5PC1XX_GPIO_H1_NR      (8)
+#define S5PC1XX_GPIO_H2_NR      (8)
+#define S5PC1XX_GPIO_H3_NR      (8)
+#define S5PC1XX_GPIO_I_NR       (8)
+#define S5PC1XX_GPIO_J0_NR      (8)
+#define S5PC1XX_GPIO_J1_NR      (5)
+#define S5PC1XX_GPIO_J2_NR      (8)
+#define S5PC1XX_GPIO_J3_NR      (8)
+#define S5PC1XX_GPIO_J4_NR      (4)
+#define S5PC1XX_GPIO_K0_NR      (8)
+#define S5PC1XX_GPIO_K1_NR      (6)
+#define S5PC1XX_GPIO_K2_NR      (8)
+#define S5PC1XX_GPIO_K3_NR      (8)
+#define S5PC1XX_GPIO_MP00_NR    (8)
+#define S5PC1XX_GPIO_MP01_NR    (8)
+#define S5PC1XX_GPIO_MP02_NR    (8)
+#define S5PC1XX_GPIO_MP03_NR    (8)
+#define S5PC1XX_GPIO_MP04_NR    (5)
+
+/* GPIO bank numbes */
+
+/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
+ * space for debugging purposes so that any accidental
+ * change from one gpio bank to another can be caught.
+*/
+
+#define S5PC1XX_GPIO_NEXT(__gpio) \
+        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+enum s3c_gpio_number {
+        S5PC1XX_GPIO_A0_START   = 0,
+        S5PC1XX_GPIO_A1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0),
+        S5PC1XX_GPIO_B_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1),
+        S5PC1XX_GPIO_C_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_B),
+        S5PC1XX_GPIO_D_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_C),
+        S5PC1XX_GPIO_E0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_D),
+        S5PC1XX_GPIO_E1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E0),
+        S5PC1XX_GPIO_F0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E1),
+        S5PC1XX_GPIO_F1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F0),
+        S5PC1XX_GPIO_F2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F1),
+        S5PC1XX_GPIO_F3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F2),
+        S5PC1XX_GPIO_G0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F3),
+        S5PC1XX_GPIO_G1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G0),
+        S5PC1XX_GPIO_G2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G1),
+        S5PC1XX_GPIO_G3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G2),
+        S5PC1XX_GPIO_H0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G3),
+        S5PC1XX_GPIO_H1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H0),
+        S5PC1XX_GPIO_H2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H1),
+        S5PC1XX_GPIO_H3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H2),
+        S5PC1XX_GPIO_I_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H3),
+        S5PC1XX_GPIO_J0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_I),
+        S5PC1XX_GPIO_J1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J0),
+        S5PC1XX_GPIO_J2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J1),
+        S5PC1XX_GPIO_J3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J2),
+        S5PC1XX_GPIO_J4_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J3),
+        S5PC1XX_GPIO_K0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J4),
+        S5PC1XX_GPIO_K1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K0),
+        S5PC1XX_GPIO_K2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K1),
+        S5PC1XX_GPIO_K3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K2),
+        S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3),
+        S5PC1XX_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP00),
+        S5PC1XX_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP01),
+        S5PC1XX_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP02),
+        S5PC1XX_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP03),
+};
+
+/* S5PC1XX GPIO number definitions. */
+#define S5PC1XX_GPA0(_nr)       (S5PC1XX_GPIO_A0_START + (_nr))
+#define S5PC1XX_GPA1(_nr)       (S5PC1XX_GPIO_A1_START + (_nr))
+#define S5PC1XX_GPB(_nr)        (S5PC1XX_GPIO_B_START + (_nr))
+#define S5PC1XX_GPC(_nr)        (S5PC1XX_GPIO_C_START + (_nr))
+#define S5PC1XX_GPD(_nr)        (S5PC1XX_GPIO_D_START + (_nr))
+#define S5PC1XX_GPE0(_nr)       (S5PC1XX_GPIO_E0_START + (_nr))
+#define S5PC1XX_GPE1(_nr)       (S5PC1XX_GPIO_E1_START + (_nr))
+#define S5PC1XX_GPF0(_nr)       (S5PC1XX_GPIO_F0_START + (_nr))
+#define S5PC1XX_GPF1(_nr)       (S5PC1XX_GPIO_F1_START + (_nr))
+#define S5PC1XX_GPF2(_nr)       (S5PC1XX_GPIO_F2_START + (_nr))
+#define S5PC1XX_GPF3(_nr)       (S5PC1XX_GPIO_F3_START + (_nr))
+#define S5PC1XX_GPG0(_nr)       (S5PC1XX_GPIO_G0_START + (_nr))
+#define S5PC1XX_GPG1(_nr)       (S5PC1XX_GPIO_G1_START + (_nr))
+#define S5PC1XX_GPG2(_nr)       (S5PC1XX_GPIO_G2_START + (_nr))
+#define S5PC1XX_GPG3(_nr)       (S5PC1XX_GPIO_G3_START + (_nr))
+#define S5PC1XX_GPH0(_nr)       (S5PC1XX_GPIO_H0_START + (_nr))
+#define S5PC1XX_GPH1(_nr)       (S5PC1XX_GPIO_H1_START + (_nr))
+#define S5PC1XX_GPH2(_nr)       (S5PC1XX_GPIO_H2_START + (_nr))
+#define S5PC1XX_GPH3(_nr)       (S5PC1XX_GPIO_H3_START + (_nr))
+#define S5PC1XX_GPI(_nr)        (S5PC1XX_GPIO_I_START + (_nr))
+#define S5PC1XX_GPJ0(_nr)       (S5PC1XX_GPIO_J0_START + (_nr))
+#define S5PC1XX_GPJ1(_nr)       (S5PC1XX_GPIO_J1_START + (_nr))
+#define S5PC1XX_GPJ2(_nr)       (S5PC1XX_GPIO_J2_START + (_nr))
+#define S5PC1XX_GPJ3(_nr)       (S5PC1XX_GPIO_J3_START + (_nr))
+#define S5PC1XX_GPJ4(_nr)       (S5PC1XX_GPIO_J4_START + (_nr))
+#define S5PC1XX_GPK0(_nr)       (S5PC1XX_GPIO_K0_START + (_nr))
+#define S5PC1XX_GPK1(_nr)       (S5PC1XX_GPIO_K1_START + (_nr))
+#define S5PC1XX_GPK2(_nr)       (S5PC1XX_GPIO_K2_START + (_nr))
+#define S5PC1XX_GPK3(_nr)       (S5PC1XX_GPIO_K3_START + (_nr))
+#define S5PC1XX_MP00(_nr)       (S5PC1XX_GPIO_MP00_START + (_nr))
+#define S5PC1XX_MP01(_nr)       (S5PC1XX_GPIO_MP01_START + (_nr))
+#define S5PC1XX_MP02(_nr)       (S5PC1XX_GPIO_MP02_START + (_nr))
+#define S5PC1XX_MP03(_nr)       (S5PC1XX_GPIO_MP03_START + (_nr))
+#define S5PC1XX_MP04(_nr)       (S5PC1XX_GPIO_MP04_START + (_nr))
+
+/* the end of the S5PC1XX specific gpios */
+#define S5PC1XX_GPIO_END        (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1)
+#define S3C_GPIO_END            S5PC1XX_GPIO_END
+
+/* define the number of gpios we need to the one after the MP04() range */
+#define ARCH_NR_GPIOS   (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1)
+
+#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s5pc100/include/mach/hardware.h b/arch/arm/mach-s5pc100/include/mach/hardware.h
new file mode 100644
index 000000000000..6b38618c2fd9
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/hardware.h
@@ -0,0 +1,14 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/hardware.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - Hardware support
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H __FILE__
+
+/* currently nothing here, placeholder */
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
new file mode 100644
index 000000000000..622720dba289
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -0,0 +1,14 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/irqs.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - IRQ definitions
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
+
+#include <plat/irqs.h>
+
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
new file mode 100644
index 000000000000..9e9f39130b2c
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -0,0 +1,75 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/map.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Based on mach-s3c6400/include/mach/map.h
+ *
+ * S5PC1XX - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H __FILE__
+
+#include <plat/map-base.h>
+
+
+/* Chip ID */
+#define S5PC100_PA_CHIPID       (0xE0000000)
+#define S5PC1XX_PA_CHIPID       S5PC100_PA_CHIPID
+#define S5PC1XX_VA_CHIPID       S3C_VA_SYS
+
+/* System */
+#define S5PC100_PA_SYS          (0xE0100000)
+#define S5PC100_PA_CLK          (S5PC100_PA_SYS + 0x0)
+#define S5PC100_PA_PWR          (S5PC100_PA_SYS + 0x8000)
+#define S5PC1XX_PA_CLK          S5PC100_PA_CLK
+#define S5PC1XX_PA_PWR          S5PC100_PA_PWR
+#define S5PC1XX_VA_CLK          (S3C_VA_SYS + 0x10000)
+#define S5PC1XX_VA_PWR          (S3C_VA_SYS + 0x20000)
+
+/* Interrupt */
+#define S5PC100_PA_VIC          (0xE4000000)
+#define S5PC100_VA_VIC          S3C_VA_IRQ
+#define S5PC100_PA_VIC_OFFSET   0x100000
+#define S5PC100_VA_VIC_OFFSET   0x10000
+#define S5PC1XX_PA_VIC(x)       (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
+#define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
+
+/* Timer */
+#define S5PC100_PA_TIMER        (0xEA000000)
+#define S5PC1XX_PA_TIMER        S5PC100_PA_TIMER
+#define S5PC1XX_VA_TIMER        S3C_VA_TIMER
+
+/* UART */
+#define S5PC100_PA_UART         (0xEC000000)
+#define S5PC1XX_PA_UART         S5PC100_PA_UART
+#define S5PC1XX_VA_UART         S3C_VA_UART
+
+/* IIC */
+#define S5PC100_PA_IIC          (0xEC100000)
+
+/* ETC */
+#define S5PC100_PA_SDRAM        (0x20000000)
+
+/* compatibility defines. */
+#define S3C_PA_UART             S5PC100_PA_UART
+#define S3C_PA_UART0            (S5PC100_PA_UART + 0x0)
+#define S3C_PA_UART1            (S5PC100_PA_UART + 0x400)
+#define S3C_PA_UART2            (S5PC100_PA_UART + 0x800)
+#define S3C_PA_UART3            (S5PC100_PA_UART + 0xC00)
+#define S3C_VA_UART0            (S3C_VA_UART + 0x0)
+#define S3C_VA_UART1            (S3C_VA_UART + 0x400)
+#define S3C_VA_UART2            (S3C_VA_UART + 0x800)
+#define S3C_VA_UART3            (S3C_VA_UART + 0xC00)
+#define S3C_UART_OFFSET         0x400
+#define S3C_VA_VIC0             (S3C_VA_IRQ + 0x0)
+#define S3C_VA_VIC1             (S3C_VA_IRQ + 0x10000)
+#define S3C_VA_VIC2             (S3C_VA_IRQ + 0x20000)
+#define S3C_PA_IIC              S5PC100_PA_IIC
+
+#endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/memory.h b/arch/arm/mach-s5pc100/include/mach/memory.h
new file mode 100644
index 000000000000..4b60d18179f7
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/memory.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-s5pc100/include/mach/memory.h
+ *
+ * Copyright 2008 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Based on mach-s3c6400/include/mach/memory.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET             UL(0x20000000)
+
+#endif
diff --git a/arch/arm/mach-s5pc100/include/mach/pwm-clock.h b/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
new file mode 100644
index 000000000000..b34d2f7aae52
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
@@ -0,0 +1,56 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - pwm clock and timer support
+ *
+ * Based on mach-s3c6400/include/mach/pwm-clock.h
+ */
+
+/**
+ * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
+ * @tcfg: The timer TCFG1 register bits shifted down to 0.
+ *
+ * Return true if the given configuration from TCFG1 is a TCLK instead
+ * any of the TDIV clocks.
+ */
+static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
+{
+        return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
+}
+
+/**
+ * tcfg_to_divisor() - convert tcfg1 setting to a divisor
+ * @tcfg1: The tcfg1 setting, shifted down.
+ *
+ * Get the divisor value for the given tcfg1 setting. We assume the
+ * caller has already checked to see if this is not a TCLK source.
+ */
+static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
+{
+        return 1 << tcfg1;
+}
+
+/**
+ * pwm_tdiv_has_div1() - does the tdiv setting have a /1
+ *
+ * Return true if we have a /1 in the tdiv setting.
+ */
+static inline unsigned int pwm_tdiv_has_div1(void)
+{
+        return 1;
+}
+
+/**
+ * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
+ * @div: The divisor to calculate the bit information for.
+ *
+ * Turn a divisor into the necessary bit field for TCFG1.
+ */
+static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
+{
+        return ilog2(div);
+}
+
+#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
new file mode 100644
index 000000000000..751ac15438c8
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
@@ -0,0 +1,24 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/regs-irq.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX - IRQ register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_IRQ_H
+#define __ASM_ARCH_REGS_IRQ_H __FILE__
+
+#include <mach/map.h>
+#include <asm/hardware/vic.h>
+
+/* interrupt controller */
+#define S5PC1XX_VIC0REG(x)                      ((x) + S5PC1XX_VA_VIC(0))
+#define S5PC1XX_VIC1REG(x)                      ((x) + S5PC1XX_VA_VIC(1))
+#define S5PC1XX_VIC2REG(x)                      ((x) + S5PC1XX_VA_VIC(2))
+
+#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
new file mode 100644
index 000000000000..e39014375470
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/system.h
@@ -0,0 +1,24 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/system.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX - system implementation
+ *
+ * Based on mach-s3c6400/include/mach/system.h
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H __FILE__
+
+static void arch_idle(void)
+{
+        /* nothing here yet */
+}
+
+static void arch_reset(char mode, const char *cmd)
+{
+        /* nothing here yet */
+}
+
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h
new file mode 100644
index 000000000000..d3de0f3591ae
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/tick.h
@@ -0,0 +1,29 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/tick.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S3C64XX - Timer tick support definitions
+ *
+ * Based on mach-s3c6400/include/mach/tick.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TICK_H
+#define __ASM_ARCH_TICK_H __FILE__
+
+/* note, the timer interrutps turn up in 2 places, the vic and then
+ * the timer block. We take the VIC as the base at the moment.
+ */
+static inline u32 s3c24xx_ostimer_pending(void)
+{
+        u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS);
+        return pend & 1 << (IRQ_TIMER4 - S5PC1XX_IRQ_VIC0(0));
+}
+
+#define TICK_MAX        (0xffffffff)
+
+#endif /* __ASM_ARCH_TICK_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/uncompress.h b/arch/arm/mach-s5pc100/include/mach/uncompress.h
new file mode 100644
index 000000000000..01ccf535e76c
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/uncompress.h
@@ -0,0 +1,28 @@
+/* arch/arm/mach-s5pc100/include/mach/uncompress.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - uncompress code
+ *
+ * Based on mach-s3c6400/include/mach/uncompress.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <mach/map.h>
+#include <plat/uncompress.h>
+
+static void arch_detect_cpu(void)
+{
+        /* we do not need to do any cpu detection here at the moment. */
+        fifo_mask = S3C2440_UFSTAT_TXMASK;
+        fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
+}
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
new file mode 100644
index 000000000000..214093cd7632
--- /dev/null
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -0,0 +1,103 @@
+/* linux/arch/arm/mach-s5pc100/mach-smdkc100.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ * Author: Byungho Min <bhmin@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/map.h>
+
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/s5pc100.h>
+
+#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
+#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+
+static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        [3] = {
+                .hwport      = 3,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+};
+
+static struct map_desc smdkc100_iodesc[] = {};
+
+static struct platform_device *smdkc100_devices[] __initdata = {
+};
+
+static void __init smdkc100_map_io(void)
+{
+        s5pc1xx_init_io(smdkc100_iodesc, ARRAY_SIZE(smdkc100_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
+}
+
+static void __init smdkc100_machine_init(void)
+{
+        platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
+}
+
+MACHINE_START(SMDKC100, "SMDKC100")
+        /* Maintainer: Byungho Min <bhmin@samsung.com> */
+        .phys_io        = S5PC1XX_PA_UART & 0xfff00000,
+        .io_pg_offst    = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S5PC100_PA_SDRAM + 0x100,
+
+        .init_irq       = s5pc100_init_irq,
+        .map_io         = smdkc100_map_io,
+        .init_machine   = smdkc100_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h
index 3959b20d5d1c..28c2cf50c259 100644
--- a/arch/arm/mach-sa1100/include/mach/assabet.h
+++ b/arch/arm/mach-sa1100/include/mach/assabet.h
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-sa1100/include/mach/assabet.h
  *
- * Created 2000/06/05 by Nicolas Pitre <nico@cam.org>
+ * Created 2000/06/05 by Nicolas Pitre <nico@fluxnic.net>
  *
  * This file contains the hardware specific definitions for Assabet
  * Only include this file from SA1100-specific files.
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index 60711822b125..99f5856d8de4 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-sa1100/include/mach/hardware.h
  *
- * Copyright (C) 1998 Nicolas Pitre <nico@cam.org>
+ * Copyright (C) 1998 Nicolas Pitre <nico@fluxnic.net>
  *
  * This file contains the hardware definitions for SA1100 architecture
  *
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
index e9f8eed900f5..d5277f9bee77 100644
--- a/arch/arm/mach-sa1100/include/mach/memory.h
+++ b/arch/arm/mach-sa1100/include/mach/memory.h
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-sa1100/include/mach/memory.h
  *
- * Copyright (C) 1999-2000 Nicolas Pitre <nico@cam.org>
+ * Copyright (C) 1999-2000 Nicolas Pitre <nico@fluxnic.net>
  */
 
 #ifndef __ASM_ARCH_MEMORY_H
diff --git a/arch/arm/mach-sa1100/include/mach/neponset.h b/arch/arm/mach-sa1100/include/mach/neponset.h
index d3f044f92c00..ffe2bc45eed0 100644
--- a/arch/arm/mach-sa1100/include/mach/neponset.h
+++ b/arch/arm/mach-sa1100/include/mach/neponset.h
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-sa1100/include/mach/neponset.h
  *
- * Created 2000/06/05 by Nicolas Pitre <nico@cam.org>
+ * Created 2000/06/05 by Nicolas Pitre <nico@fluxnic.net>
  *
  * This file contains the hardware specific definitions for Assabet
  * Only include this file from SA1100-specific files.
diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h
index 942b153e251d..ba9da9f7f183 100644
--- a/arch/arm/mach-sa1100/include/mach/system.h
+++ b/arch/arm/mach-sa1100/include/mach/system.h
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-sa1100/include/mach/system.h
  *
- * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
+ * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
  */
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-sa1100/include/mach/uncompress.h b/arch/arm/mach-sa1100/include/mach/uncompress.h
index 714160b03d7a..6cb39ddde656 100644
--- a/arch/arm/mach-sa1100/include/mach/uncompress.h
+++ b/arch/arm/mach-sa1100/include/mach/uncompress.h
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-sa1100/include/mach/uncompress.h
  *
- * (C) 1999 Nicolas Pitre <nico@cam.org>
+ * (C) 1999 Nicolas Pitre <nico@fluxnic.net>
  *
  * Reorganised to be machine independent.
  */
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 111cce67ad2f..c83fdc80edfd 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -15,7 +15,7 @@
  *                      Save more value for the resume function! Support
  *                      Bitsy/Assabet/Freebird board
  *
- * 2001-08-29:  Nicolas Pitre <nico@cam.org>
+ * 2001-08-29:  Nicolas Pitre <nico@fluxnic.net>
  *                      Cleaned up, pushed platform dependent stuff
  *                      in the platform specific files.
  *
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 711c0295c66f..95d92e8e56a8 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -4,7 +4,7 @@
  * Copyright (C) 1998 Deborah Wallach.
  * Twiddles  (C) 1999 Hugo Fiennes <hugo@empeg.com>
  *
- * 2000/03/29 (C) Nicolas Pitre <nico@cam.org>
+ * 2000/03/29 (C) Nicolas Pitre <nico@fluxnic.net>
  *      Rewritten: big cleanup, much simpler, better HZ accuracy.
  *
  */
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
index 3138d3955c9e..585cc013639d 100644
--- a/arch/arm/mach-u300/mmc.c
+++ b/arch/arm/mach-u300/mmc.c
@@ -156,6 +156,8 @@ int __devinit mmc_init(struct amba_device *adev)
         mmci_card->mmc0_plat_data.ocr_mask = MMC_VDD_28_29;
         mmci_card->mmc0_plat_data.translate_vdd = mmc_translate_vdd;
         mmci_card->mmc0_plat_data.status = mmc_status;
+        mmci_card->mmc0_plat_data.gpio_wp = -1;
+        mmci_card->mmc0_plat_data.gpio_cd = -1;
 
         mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data;
 
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 31093af7d052..975eae41ee66 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -26,6 +26,7 @@
 #include <linux/interrupt.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
+#include <linux/amba/pl061.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/cnt32_to_63.h>
@@ -371,6 +372,8 @@ unsigned int mmc_status(struct device *dev)
 static struct mmc_platform_data mmc0_plat_data = {
         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
         .status         = mmc_status,
+        .gpio_wp        = -1,
+        .gpio_cd        = -1,
 };
 
 /*
@@ -705,6 +708,16 @@ static struct clcd_board clcd_plat_data = {
         .remove         = versatile_clcd_remove,
 };
 
+static struct pl061_platform_data gpio0_plat_data = {
+        .gpio_base      = 0,
+        .irq_base       = IRQ_GPIO0_START,
+};
+
+static struct pl061_platform_data gpio1_plat_data = {
+        .gpio_base      = 8,
+        .irq_base       = IRQ_GPIO1_START,
+};
+
 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 #define AACI_DMA        { 0x80, 0x81 }
 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
@@ -767,8 +780,8 @@ AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
-AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
-AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
+AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
+AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
diff --git a/arch/arm/mach-versatile/include/mach/gpio.h b/arch/arm/mach-versatile/include/mach/gpio.h
new file mode 100644
index 000000000000..94ff27678a46
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/gpio.h
@@ -0,0 +1,6 @@
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
diff --git a/arch/arm/mach-versatile/include/mach/irqs.h b/arch/arm/mach-versatile/include/mach/irqs.h
index 9bfdb30e1f3f..bf44c61bd1f6 100644
--- a/arch/arm/mach-versatile/include/mach/irqs.h
+++ b/arch/arm/mach-versatile/include/mach/irqs.h
@@ -122,4 +122,13 @@
 #define IRQ_SIC_PCI3            (IRQ_SIC_START + SIC_INT_PCI3)
 #define IRQ_SIC_END             63
 
-#define NR_IRQS                 64
+#define IRQ_GPIO0_START         (IRQ_SIC_END + 1)
+#define IRQ_GPIO0_END           (IRQ_GPIO0_START + 31)
+#define IRQ_GPIO1_START         (IRQ_GPIO0_END + 1)
+#define IRQ_GPIO1_END           (IRQ_GPIO1_START + 31)
+#define IRQ_GPIO2_START         (IRQ_GPIO1_END + 1)
+#define IRQ_GPIO2_END           (IRQ_GPIO2_START + 31)
+#define IRQ_GPIO3_START         (IRQ_GPIO2_END + 1)
+#define IRQ_GPIO3_END           (IRQ_GPIO3_START + 31)
+
+#define NR_IRQS                 (IRQ_GPIO3_END + 1)
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index aa051c0884f8..9af8d8154df5 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -23,6 +23,7 @@
 #include <linux/device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl061.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -43,6 +44,18 @@
 static struct mmc_platform_data mmc1_plat_data = {
         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
         .status         = mmc_status,
+        .gpio_wp        = -1,
+        .gpio_cd        = -1,
+};
+
+static struct pl061_platform_data gpio2_plat_data = {
+        .gpio_base      = 16,
+        .irq_base       = IRQ_GPIO2_START,
+};
+
+static struct pl061_platform_data gpio3_plat_data = {
+        .gpio_base      = 24,
+        .irq_base       = IRQ_GPIO3_START,
 };
 
 #define UART3_IRQ       { IRQ_SIC_UART3, NO_IRQ }
@@ -70,8 +83,8 @@ AMBA_DEVICE(sci1,  "fpga:0a", SCI1,     NULL);
 AMBA_DEVICE(mmc1,  "fpga:0b", MMCI1,    &mmc1_plat_data);
 
 /* DevChip Primecells */
-AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    NULL);
-AMBA_DEVICE(gpio3, "dev:e7",  GPIO3,    NULL);
+AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    &gpio2_plat_data);
+AMBA_DEVICE(gpio3, "dev:e7",  GPIO3,    &gpio3_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &uart3_device,
diff --git a/arch/arm/mach-w90x900/Kconfig b/arch/arm/mach-w90x900/Kconfig
index 8e4178fe5ec2..69bab32a8bc2 100644
--- a/arch/arm/mach-w90x900/Kconfig
+++ b/arch/arm/mach-w90x900/Kconfig
@@ -5,6 +5,16 @@ config CPU_W90P910
         help
           Support for W90P910 of Nuvoton W90X900 CPUs.
 
+config CPU_NUC950
+        bool
+        help
+          Support for NUCP950 of Nuvoton NUC900 CPUs.
+
+config CPU_NUC960
+        bool
+        help
+          Support for NUCP960 of Nuvoton NUC900 CPUs.
+
 menu "W90P910 Machines"
 
 config MACH_W90P910EVB
@@ -16,4 +26,24 @@ config MACH_W90P910EVB
 
 endmenu
 
+menu "NUC950 Machines"
+
+config MACH_W90P950EVB
+        bool "Nuvoton NUC950 Evaluation Board"
+        select CPU_NUC950
+        help
+           Say Y here if you are using the Nuvoton NUC950EVB
+
+endmenu
+
+menu "NUC960 Machines"
+
+config MACH_W90N960EVB
+        bool "Nuvoton NUC960 Evaluation Board"
+        select CPU_NUC960
+        help
+           Say Y here if you are using the Nuvoton NUC960EVB
+
+endmenu
+
 endif
diff --git a/arch/arm/mach-w90x900/Makefile b/arch/arm/mach-w90x900/Makefile
index d50c94f4dbdf..828c0326441e 100644
--- a/arch/arm/mach-w90x900/Makefile
+++ b/arch/arm/mach-w90x900/Makefile
@@ -4,12 +4,16 @@
 
 # Object file lists.
 
-obj-y                           := irq.o time.o mfp-w90p910.o gpio.o clock.o
-
+obj-y                           := irq.o time.o mfp.o gpio.o clock.o
+obj-y                           += clksel.o dev.o cpu.o
 # W90X900 CPU support files
 
-obj-$(CONFIG_CPU_W90P910)       += w90p910.o
+obj-$(CONFIG_CPU_W90P910)       += nuc910.o
+obj-$(CONFIG_CPU_NUC950)        += nuc950.o
+obj-$(CONFIG_CPU_NUC960)        += nuc960.o
 
 # machine support
 
-obj-$(CONFIG_MACH_W90P910EVB)   += mach-w90p910evb.o
+obj-$(CONFIG_MACH_W90P910EVB)   += mach-nuc910evb.o
+obj-$(CONFIG_MACH_W90P950EVB)   += mach-nuc950evb.o
+obj-$(CONFIG_MACH_W90N960EVB)   += mach-nuc960evb.o
diff --git a/arch/arm/mach-w90x900/clksel.c b/arch/arm/mach-w90x900/clksel.c
new file mode 100644
index 000000000000..3de4a5211c3b
--- /dev/null
+++ b/arch/arm/mach-w90x900/clksel.c
@@ -0,0 +1,91 @@
+/*
+ * linux/arch/arm/mach-w90x900/clksel.c
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-clock.h>
+
+#define PLL0            0x00
+#define PLL1            0x01
+#define OTHER           0x02
+#define EXT             0x03
+#define MSOFFSET        0x0C
+#define ATAOFFSET       0x0a
+#define LCDOFFSET       0x06
+#define AUDOFFSET       0x04
+#define CPUOFFSET       0x00
+
+static DEFINE_MUTEX(clksel_sem);
+
+static void clock_source_select(const char *dev_id, unsigned int clkval)
+{
+        unsigned int clksel, offset;
+
+        clksel = __raw_readl(REG_CLKSEL);
+
+        if (strcmp(dev_id, "nuc900-ms") == 0)
+                offset = MSOFFSET;
+        else if (strcmp(dev_id, "nuc900-atapi") == 0)
+                offset = ATAOFFSET;
+        else if (strcmp(dev_id, "nuc900-lcd") == 0)
+                offset = LCDOFFSET;
+        else if (strcmp(dev_id, "nuc900-audio") == 0)
+                offset = AUDOFFSET;
+        else
+                offset = CPUOFFSET;
+
+        clksel &= ~(0x03 << offset);
+        clksel |= (clkval << offset);
+
+        __raw_writel(clksel, REG_CLKSEL);
+}
+
+void nuc900_clock_source(struct device *dev, unsigned char *src)
+{
+        unsigned int clkval;
+        const char *dev_id;
+
+        BUG_ON(!src);
+        clkval = 0;
+
+        mutex_lock(&clksel_sem);
+
+        if (dev)
+                dev_id = dev_name(dev);
+        else
+                dev_id = "cpufreq";
+
+        if (strcmp(src, "pll0") == 0)
+                clkval = PLL0;
+        else if (strcmp(src, "pll1") == 0)
+                clkval = PLL1;
+        else if (strcmp(src, "ext") == 0)
+                clkval = EXT;
+        else if (strcmp(src, "oth") == 0)
+                clkval = OTHER;
+
+        clock_source_select(dev_id, clkval);
+
+        mutex_unlock(&clksel_sem);
+}
+EXPORT_SYMBOL(nuc900_clock_source);
+
diff --git a/arch/arm/mach-w90x900/clock.c b/arch/arm/mach-w90x900/clock.c
index f420613cd395..b785994bab0a 100644
--- a/arch/arm/mach-w90x900/clock.c
+++ b/arch/arm/mach-w90x900/clock.c
@@ -25,6 +25,8 @@
 
 #include "clock.h"
 
+#define SUBCLK 0x24
+
 static DEFINE_SPINLOCK(clocks_lock);
 
 int clk_enable(struct clk *clk)
@@ -53,7 +55,13 @@ void clk_disable(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_disable);
 
-void w90x900_clk_enable(struct clk *clk, int enable)
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return 15000000;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+void nuc900_clk_enable(struct clk *clk, int enable)
 {
         unsigned int clocks = clk->cken;
         unsigned long clken;
@@ -68,6 +76,22 @@ void w90x900_clk_enable(struct clk *clk, int enable)
         __raw_writel(clken, W90X900_VA_CLKPWR);
 }
 
+void nuc900_subclk_enable(struct clk *clk, int enable)
+{
+        unsigned int clocks = clk->cken;
+        unsigned long clken;
+
+        clken = __raw_readl(W90X900_VA_CLKPWR + SUBCLK);
+
+        if (enable)
+                clken |= clocks;
+        else
+                clken &= ~clocks;
+
+        __raw_writel(clken, W90X900_VA_CLKPWR + SUBCLK);
+}
+
+
 void clks_register(struct clk_lookup *clks, size_t num)
 {
         int i;
diff --git a/arch/arm/mach-w90x900/clock.h b/arch/arm/mach-w90x900/clock.h
index 4f27bda76d56..f5816a06eed6 100644
--- a/arch/arm/mach-w90x900/clock.h
+++ b/arch/arm/mach-w90x900/clock.h
@@ -12,7 +12,8 @@
 
 #include <asm/clkdev.h>
 
-void w90x900_clk_enable(struct clk *clk, int enable);
+void nuc900_clk_enable(struct clk *clk, int enable);
+void nuc900_subclk_enable(struct clk *clk, int enable);
 void clks_register(struct clk_lookup *clks, size_t num);
 
 struct clk {
@@ -23,10 +24,17 @@ struct clk {
 
 #define DEFINE_CLK(_name, _ctrlbit)                     \
 struct clk clk_##_name = {                              \
-                .enable = w90x900_clk_enable,           \
+                .enable = nuc900_clk_enable,            \
                 .cken   = (1 << _ctrlbit),              \
         }
 
+#define DEFINE_SUBCLK(_name, _ctrlbit)                  \
+struct clk clk_##_name = {                              \
+                .enable = nuc900_subclk_enable, \
+                .cken   = (1 << _ctrlbit),              \
+        }
+
+
 #define DEF_CLKLOOK(_clk, _devname, _conname)           \
         {                                               \
                 .clk            = _clk,                 \
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
new file mode 100644
index 000000000000..921cef991bf0
--- /dev/null
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -0,0 +1,212 @@
+/*
+ * linux/arch/arm/mach-w90x900/cpu.c
+ *
+ * Copyright (c) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * NUC900 series cpu common support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/serial_8250.h>
+#include <linux/delay.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-serial.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-ebi.h>
+
+#include "cpu.h"
+#include "clock.h"
+
+/* Initial IO mappings */
+
+static struct map_desc nuc900_iodesc[] __initdata = {
+        IODESC_ENT(IRQ),
+        IODESC_ENT(GCR),
+        IODESC_ENT(UART),
+        IODESC_ENT(TIMER),
+        IODESC_ENT(EBI),
+};
+
+/* Initial clock declarations. */
+static DEFINE_CLK(lcd, 0);
+static DEFINE_CLK(audio, 1);
+static DEFINE_CLK(fmi, 4);
+static DEFINE_SUBCLK(ms, 0);
+static DEFINE_SUBCLK(sd, 1);
+static DEFINE_CLK(dmac, 5);
+static DEFINE_CLK(atapi, 6);
+static DEFINE_CLK(emc, 7);
+static DEFINE_SUBCLK(rmii, 2);
+static DEFINE_CLK(usbd, 8);
+static DEFINE_CLK(usbh, 9);
+static DEFINE_CLK(g2d, 10);;
+static DEFINE_CLK(pwm, 18);
+static DEFINE_CLK(ps2, 24);
+static DEFINE_CLK(kpi, 25);
+static DEFINE_CLK(wdt, 26);
+static DEFINE_CLK(gdma, 27);
+static DEFINE_CLK(adc, 28);
+static DEFINE_CLK(usi, 29);
+static DEFINE_CLK(ext, 0);
+
+static struct clk_lookup nuc900_clkregs[] = {
+        DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL),
+        DEF_CLKLOOK(&clk_audio, "nuc900-audio", NULL),
+        DEF_CLKLOOK(&clk_fmi, "nuc900-fmi", NULL),
+        DEF_CLKLOOK(&clk_ms, "nuc900-fmi", "MS"),
+        DEF_CLKLOOK(&clk_sd, "nuc900-fmi", "SD"),
+        DEF_CLKLOOK(&clk_dmac, "nuc900-dmac", NULL),
+        DEF_CLKLOOK(&clk_atapi, "nuc900-atapi", NULL),
+        DEF_CLKLOOK(&clk_emc, "nuc900-emc", NULL),
+        DEF_CLKLOOK(&clk_rmii, "nuc900-emc", "RMII"),
+        DEF_CLKLOOK(&clk_usbd, "nuc900-usbd", NULL),
+        DEF_CLKLOOK(&clk_usbh, "nuc900-usbh", NULL),
+        DEF_CLKLOOK(&clk_g2d, "nuc900-g2d", NULL),
+        DEF_CLKLOOK(&clk_pwm, "nuc900-pwm", NULL),
+        DEF_CLKLOOK(&clk_ps2, "nuc900-ps2", NULL),
+        DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL),
+        DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL),
+        DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL),
+        DEF_CLKLOOK(&clk_adc, "nuc900-adc", NULL),
+        DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL),
+        DEF_CLKLOOK(&clk_ext, NULL, "ext"),
+};
+
+/* Initial serial platform data */
+
+struct plat_serial8250_port nuc900_uart_data[] = {
+        NUC900_8250PORT(UART0),
+};
+
+struct platform_device nuc900_serial_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev                    = {
+                .platform_data  = nuc900_uart_data,
+        },
+};
+
+/*Set NUC900 series cpu frequence*/
+static int __init nuc900_set_clkval(unsigned int cpufreq)
+{
+        unsigned int pllclk, ahbclk, apbclk, val;
+
+        pllclk = 0;
+        ahbclk = 0;
+        apbclk = 0;
+
+        switch (cpufreq) {
+        case 66:
+                pllclk = PLL_66MHZ;
+                ahbclk = AHB_CPUCLK_1_1;
+                apbclk = APB_AHB_1_2;
+                break;
+
+        case 100:
+                pllclk = PLL_100MHZ;
+                ahbclk = AHB_CPUCLK_1_1;
+                apbclk = APB_AHB_1_2;
+                break;
+
+        case 120:
+                pllclk = PLL_120MHZ;
+                ahbclk = AHB_CPUCLK_1_2;
+                apbclk = APB_AHB_1_2;
+                break;
+
+        case 166:
+                pllclk = PLL_166MHZ;
+                ahbclk = AHB_CPUCLK_1_2;
+                apbclk = APB_AHB_1_2;
+                break;
+
+        case 200:
+                pllclk = PLL_200MHZ;
+                ahbclk = AHB_CPUCLK_1_2;
+                apbclk = APB_AHB_1_2;
+                break;
+        }
+
+        __raw_writel(pllclk, REG_PLLCON0);
+
+        val = __raw_readl(REG_CLKDIV);
+        val &= ~(0x03 << 24 | 0x03 << 26);
+        val |= (ahbclk << 24 | apbclk << 26);
+        __raw_writel(val, REG_CLKDIV);
+
+        return  0;
+}
+static int __init nuc900_set_cpufreq(char *str)
+{
+        unsigned long cpufreq, val;
+
+        if (!*str)
+                return 0;
+
+        strict_strtoul(str, 0, &cpufreq);
+
+        nuc900_clock_source(NULL, "ext");
+
+        nuc900_set_clkval(cpufreq);
+
+        mdelay(1);
+
+        val = __raw_readl(REG_CKSKEW);
+        val &= ~0xff;
+        val |= DEFAULTSKEW;
+        __raw_writel(val, REG_CKSKEW);
+
+        nuc900_clock_source(NULL, "pll0");
+
+        return 1;
+}
+
+__setup("cpufreq=", nuc900_set_cpufreq);
+
+/*Init NUC900 evb io*/
+
+void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size)
+{
+        unsigned long idcode = 0x0;
+
+        iotable_init(mach_desc, mach_size);
+        iotable_init(nuc900_iodesc, ARRAY_SIZE(nuc900_iodesc));
+
+        idcode = __raw_readl(NUC900PDID);
+        if (idcode == NUC910_CPUID)
+                printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode);
+        else if (idcode == NUC920_CPUID)
+                printk(KERN_INFO "CPU type 0x%08lx is NUC920\n", idcode);
+        else if (idcode == NUC950_CPUID)
+                printk(KERN_INFO "CPU type 0x%08lx is NUC950\n", idcode);
+        else if (idcode == NUC960_CPUID)
+                printk(KERN_INFO "CPU type 0x%08lx is NUC960\n", idcode);
+}
+
+/*Init NUC900 clock*/
+
+void __init nuc900_init_clocks(void)
+{
+        clks_register(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs));
+}
+
diff --git a/arch/arm/mach-w90x900/cpu.h b/arch/arm/mach-w90x900/cpu.h
index 57b5dbabeb41..4d58ba164e25 100644
--- a/arch/arm/mach-w90x900/cpu.h
+++ b/arch/arm/mach-w90x900/cpu.h
@@ -6,7 +6,7 @@
  * Copyright (c) 2008 Nuvoton technology corporation
  * All rights reserved.
  *
- * Header file for W90X900 CPU support
+ * Header file for NUC900 CPU support
  *
  * Wan ZongShun <mcuos.com@gmail.com>
  *
@@ -24,29 +24,7 @@
        .type    = MT_DEVICE,                           \
 }
 
-/*Cpu identifier register*/
-
-#define W90X900PDID     W90X900_VA_GCR
-#define W90P910_CPUID   0x02900910
-#define W90P920_CPUID   0x02900920
-#define W90P950_CPUID   0x02900950
-#define W90N960_CPUID   0x02900960
-
-struct w90x900_uartcfg;
-struct map_desc;
-struct sys_timer;
-
-/* core initialisation functions */
-
-extern void w90x900_init_irq(void);
-extern void w90p910_init_io(struct map_desc *mach_desc, int size);
-extern void w90p910_init_uarts(struct w90x900_uartcfg *cfg, int no);
-extern void w90p910_init_clocks(void);
-extern void w90p910_map_io(struct map_desc *mach_desc, int size);
-extern struct platform_device w90p910_serial_device;
-extern struct sys_timer w90x900_timer;
-
-#define W90X900_8250PORT(name)                                  \
+#define NUC900_8250PORT(name)                                   \
 {                                                               \
         .membase        = name##_BA,                            \
         .mapbase        = name##_PA,                            \
@@ -56,3 +34,26 @@ extern struct sys_timer w90x900_timer;
         .iotype         = UPIO_MEM,                             \
         .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,    \
 }
+
+/*Cpu identifier register*/
+
+#define NUC900PDID      W90X900_VA_GCR
+#define NUC910_CPUID    0x02900910
+#define NUC920_CPUID    0x02900920
+#define NUC950_CPUID    0x02900950
+#define NUC960_CPUID    0x02900960
+
+/* extern file from cpu.c */
+
+extern void nuc900_clock_source(struct device *dev, unsigned char *src);
+extern void nuc900_init_clocks(void);
+extern void nuc900_map_io(struct map_desc *mach_desc, int mach_size);
+extern void nuc900_board_init(struct platform_device **device, int size);
+
+/* for either public between 910 and 920, or between 920 and 950 */
+
+extern struct platform_device nuc900_serial_device;
+extern struct platform_device nuc900_device_fmi;
+extern struct platform_device nuc900_device_kpi;
+extern struct platform_device nuc900_device_rtc;
+extern struct platform_device nuc900_device_ts;
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
new file mode 100644
index 000000000000..2a6f98de48d2
--- /dev/null
+++ b/arch/arm/mach-w90x900/dev.c
@@ -0,0 +1,389 @@
+/*
+ * linux/arch/arm/mach-w90x900/dev.c
+ *
+ * Copyright (C) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach-types.h>
+
+#include <mach/regs-serial.h>
+#include <mach/map.h>
+
+#include "cpu.h"
+
+/*NUC900 evb norflash driver data */
+
+#define NUC900_FLASH_BASE       0xA0000000
+#define NUC900_FLASH_SIZE       0x400000
+#define SPIOFFSET               0x200
+#define SPIOREG_SIZE            0x100
+
+static struct mtd_partition nuc900_flash_partitions[] = {
+        {
+                .name   =       "NOR Partition 1 for kernel (960K)",
+                .size   =       0xF0000,
+                .offset =       0x10000,
+        },
+        {
+                .name   =       "NOR Partition 2 for image (1M)",
+                .size   =       0x100000,
+                .offset =       0x100000,
+        },
+        {
+                .name   =       "NOR Partition 3 for user (2M)",
+                .size   =       0x200000,
+                .offset =       0x00200000,
+        }
+};
+
+static struct physmap_flash_data nuc900_flash_data = {
+        .width          =       2,
+        .parts          =       nuc900_flash_partitions,
+        .nr_parts       =       ARRAY_SIZE(nuc900_flash_partitions),
+};
+
+static struct resource nuc900_flash_resources[] = {
+        {
+                .start  =       NUC900_FLASH_BASE,
+                .end    =       NUC900_FLASH_BASE + NUC900_FLASH_SIZE - 1,
+                .flags  =       IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device nuc900_flash_device = {
+        .name           =       "physmap-flash",
+        .id             =       0,
+        .dev            = {
+                                .platform_data = &nuc900_flash_data,
+                        },
+        .resource       =       nuc900_flash_resources,
+        .num_resources  =       ARRAY_SIZE(nuc900_flash_resources),
+};
+
+/* USB EHCI Host Controller */
+
+static struct resource nuc900_usb_ehci_resource[] = {
+        [0] = {
+                .start = W90X900_PA_USBEHCIHOST,
+                .end   = W90X900_PA_USBEHCIHOST + W90X900_SZ_USBEHCIHOST - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_USBH,
+                .end   = IRQ_USBH,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static u64 nuc900_device_usb_ehci_dmamask = 0xffffffffUL;
+
+static struct platform_device nuc900_device_usb_ehci = {
+        .name             = "nuc900-ehci",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(nuc900_usb_ehci_resource),
+        .resource         = nuc900_usb_ehci_resource,
+        .dev              = {
+                .dma_mask = &nuc900_device_usb_ehci_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+
+/* USB OHCI Host Controller */
+
+static struct resource nuc900_usb_ohci_resource[] = {
+        [0] = {
+                .start = W90X900_PA_USBOHCIHOST,
+                .end   = W90X900_PA_USBOHCIHOST + W90X900_SZ_USBOHCIHOST - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_USBH,
+                .end   = IRQ_USBH,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static u64 nuc900_device_usb_ohci_dmamask = 0xffffffffUL;
+static struct platform_device nuc900_device_usb_ohci = {
+        .name             = "nuc900-ohci",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(nuc900_usb_ohci_resource),
+        .resource         = nuc900_usb_ohci_resource,
+        .dev              = {
+                .dma_mask = &nuc900_device_usb_ohci_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+
+/* USB Device (Gadget)*/
+
+static struct resource nuc900_usbgadget_resource[] = {
+        [0] = {
+                .start = W90X900_PA_USBDEV,
+                .end   = W90X900_PA_USBDEV + W90X900_SZ_USBDEV - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_USBD,
+                .end   = IRQ_USBD,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device nuc900_device_usbgadget = {
+        .name           = "nuc900-usbgadget",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(nuc900_usbgadget_resource),
+        .resource       = nuc900_usbgadget_resource,
+};
+
+/* MAC device */
+
+static struct resource nuc900_emc_resource[] = {
+        [0] = {
+                .start = W90X900_PA_EMC,
+                .end   = W90X900_PA_EMC + W90X900_SZ_EMC - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_EMCTX,
+                .end   = IRQ_EMCTX,
+                .flags = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start = IRQ_EMCRX,
+                .end   = IRQ_EMCRX,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static u64 nuc900_device_emc_dmamask = 0xffffffffUL;
+static struct platform_device nuc900_device_emc = {
+        .name           = "nuc900-emc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(nuc900_emc_resource),
+        .resource       = nuc900_emc_resource,
+        .dev              = {
+                .dma_mask = &nuc900_device_emc_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+
+/* SPI device */
+
+static struct resource nuc900_spi_resource[] = {
+        [0] = {
+                .start = W90X900_PA_I2C + SPIOFFSET,
+                .end   = W90X900_PA_I2C + SPIOFFSET + SPIOREG_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_SSP,
+                .end   = IRQ_SSP,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device nuc900_device_spi = {
+        .name           = "nuc900-spi",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(nuc900_spi_resource),
+        .resource       = nuc900_spi_resource,
+};
+
+/* spi device, spi flash info */
+
+static struct mtd_partition nuc900_spi_flash_partitions[] = {
+        {
+                .name = "bootloader(spi)",
+                .size = 0x0100000,
+                .offset = 0,
+        },
+};
+
+static struct flash_platform_data nuc900_spi_flash_data = {
+        .name = "m25p80",
+        .parts =  nuc900_spi_flash_partitions,
+        .nr_parts = ARRAY_SIZE(nuc900_spi_flash_partitions),
+        .type = "w25x16",
+};
+
+static struct spi_board_info nuc900_spi_board_info[] __initdata = {
+        {
+                .modalias = "m25p80",
+                .max_speed_hz = 20000000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .platform_data = &nuc900_spi_flash_data,
+                .mode = SPI_MODE_0,
+        },
+};
+
+/* WDT Device */
+
+static struct resource nuc900_wdt_resource[] = {
+        [0] = {
+                .start = W90X900_PA_TIMER,
+                .end   = W90X900_PA_TIMER + W90X900_SZ_TIMER - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_WDT,
+                .end   = IRQ_WDT,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device nuc900_device_wdt = {
+        .name           = "nuc900-wdt",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(nuc900_wdt_resource),
+        .resource       = nuc900_wdt_resource,
+};
+
+/*
+ * public device definition between 910 and 920, or 910
+ * and 950 or 950 and 960...,their dev platform register
+ * should be in specific file such as nuc950, nuc960 c
+ * files rather than the public dev.c file here. so the
+ * corresponding platform_device definition should not be
+ * static.
+*/
+
+/* RTC controller*/
+
+static struct resource nuc900_rtc_resource[] = {
+        [0] = {
+                .start = W90X900_PA_RTC,
+                .end   = W90X900_PA_RTC + 0xff,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_RTC,
+                .end   = IRQ_RTC,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device nuc900_device_rtc = {
+        .name           = "nuc900-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(nuc900_rtc_resource),
+        .resource       = nuc900_rtc_resource,
+};
+
+/*TouchScreen controller*/
+
+static struct resource nuc900_ts_resource[] = {
+        [0] = {
+                .start = W90X900_PA_ADC,
+                .end   = W90X900_PA_ADC + W90X900_SZ_ADC-1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_ADC,
+                .end   = IRQ_ADC,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device nuc900_device_ts = {
+        .name           = "nuc900-ts",
+        .id             = -1,
+        .resource       = nuc900_ts_resource,
+        .num_resources  = ARRAY_SIZE(nuc900_ts_resource),
+};
+
+/* FMI Device */
+
+static struct resource nuc900_fmi_resource[] = {
+        [0] = {
+                .start = W90X900_PA_FMI,
+                .end   = W90X900_PA_FMI + W90X900_SZ_FMI - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_FMI,
+                .end   = IRQ_FMI,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device nuc900_device_fmi = {
+        .name           = "nuc900-fmi",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(nuc900_fmi_resource),
+        .resource       = nuc900_fmi_resource,
+};
+
+/* KPI controller*/
+
+static struct resource nuc900_kpi_resource[] = {
+        [0] = {
+                .start = W90X900_PA_KPI,
+                .end   = W90X900_PA_KPI + W90X900_SZ_KPI - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_KPI,
+                .end   = IRQ_KPI,
+                .flags = IORESOURCE_IRQ,
+        }
+
+};
+
+struct platform_device nuc900_device_kpi = {
+        .name           = "nuc900-kpi",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(nuc900_kpi_resource),
+        .resource       = nuc900_kpi_resource,
+};
+
+/*Here should be your evb resourse,such as LCD*/
+
+static struct platform_device *nuc900_public_dev[] __initdata = {
+        &nuc900_serial_device,
+        &nuc900_flash_device,
+        &nuc900_device_usb_ehci,
+        &nuc900_device_usb_ohci,
+        &nuc900_device_usbgadget,
+        &nuc900_device_emc,
+        &nuc900_device_spi,
+        &nuc900_device_wdt,
+};
+
+/* Provide adding specific CPU platform devices API */
+
+void __init nuc900_board_init(struct platform_device **device, int size)
+{
+        platform_add_devices(device, size);
+        platform_add_devices(nuc900_public_dev, ARRAY_SIZE(nuc900_public_dev));
+        spi_register_board_info(nuc900_spi_board_info,
+                                        ARRAY_SIZE(nuc900_spi_board_info));
+}
+
diff --git a/arch/arm/mach-w90x900/gpio.c b/arch/arm/mach-w90x900/gpio.c
index c72e0dfa1825..ba05aec7ea4b 100644
--- a/arch/arm/mach-w90x900/gpio.c
+++ b/arch/arm/mach-w90x900/gpio.c
@@ -1,7 +1,7 @@
 /*
- * linux/arch/arm/mach-w90p910/gpio.c
+ * linux/arch/arm/mach-w90x900/gpio.c
  *
- * Generic w90p910 GPIO handling
+ * Generic nuc900 GPIO handling
  *
  *  Wan ZongShun <mcuos.com@gmail.com>
  *
@@ -30,31 +30,31 @@
 #define GPIO_IN                 (0x0C)
 #define GROUPINERV              (0x10)
 #define GPIO_GPIO(Nb)           (0x00000001 << (Nb))
-#define to_w90p910_gpio_chip(c) container_of(c, struct w90p910_gpio_chip, chip)
+#define to_nuc900_gpio_chip(c) container_of(c, struct nuc900_gpio_chip, chip)
 
-#define W90P910_GPIO_CHIP(name, base_gpio, nr_gpio)                     \
+#define NUC900_GPIO_CHIP(name, base_gpio, nr_gpio)                      \
         {                                                               \
                 .chip = {                                               \
                         .label            = name,                       \
-                        .direction_input  = w90p910_dir_input,          \
-                        .direction_output = w90p910_dir_output,         \
-                        .get              = w90p910_gpio_get,           \
-                        .set              = w90p910_gpio_set,           \
+                        .direction_input  = nuc900_dir_input,           \
+                        .direction_output = nuc900_dir_output,          \
+                        .get              = nuc900_gpio_get,            \
+                        .set              = nuc900_gpio_set,            \
                         .base             = base_gpio,                  \
                         .ngpio            = nr_gpio,                    \
                 }                                                       \
         }
 
-struct w90p910_gpio_chip {
+struct nuc900_gpio_chip {
         struct gpio_chip        chip;
         void __iomem            *regbase;       /* Base of group register*/
         spinlock_t              gpio_lock;
 };
 
-static int w90p910_gpio_get(struct gpio_chip *chip, unsigned offset)
+static int nuc900_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip);
-        void __iomem *pio = w90p910_gpio->regbase + GPIO_IN;
+        struct nuc900_gpio_chip *nuc900_gpio = to_nuc900_gpio_chip(chip);
+        void __iomem *pio = nuc900_gpio->regbase + GPIO_IN;
         unsigned int regval;
 
         regval = __raw_readl(pio);
@@ -63,14 +63,14 @@ static int w90p910_gpio_get(struct gpio_chip *chip, unsigned offset)
         return (regval != 0);
 }
 
-static void w90p910_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
+static void nuc900_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
 {
-        struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip);
-        void __iomem *pio = w90p910_gpio->regbase + GPIO_OUT;
+        struct nuc900_gpio_chip *nuc900_gpio = to_nuc900_gpio_chip(chip);
+        void __iomem *pio = nuc900_gpio->regbase + GPIO_OUT;
         unsigned int regval;
         unsigned long flags;
 
-        spin_lock_irqsave(&w90p910_gpio->gpio_lock, flags);
+        spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags);
 
         regval = __raw_readl(pio);
 
@@ -81,36 +81,36 @@ static void w90p910_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
 
         __raw_writel(regval, pio);
 
-        spin_unlock_irqrestore(&w90p910_gpio->gpio_lock, flags);
+        spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags);
 }
 
-static int w90p910_dir_input(struct gpio_chip *chip, unsigned offset)
+static int nuc900_dir_input(struct gpio_chip *chip, unsigned offset)
 {
-        struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip);
-        void __iomem *pio = w90p910_gpio->regbase + GPIO_DIR;
+        struct nuc900_gpio_chip *nuc900_gpio = to_nuc900_gpio_chip(chip);
+        void __iomem *pio = nuc900_gpio->regbase + GPIO_DIR;
         unsigned int regval;
         unsigned long flags;
 
-        spin_lock_irqsave(&w90p910_gpio->gpio_lock, flags);
+        spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags);
 
         regval = __raw_readl(pio);
         regval &= ~GPIO_GPIO(offset);
         __raw_writel(regval, pio);
 
-        spin_unlock_irqrestore(&w90p910_gpio->gpio_lock, flags);
+        spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags);
 
         return 0;
 }
 
-static int w90p910_dir_output(struct gpio_chip *chip, unsigned offset, int val)
+static int nuc900_dir_output(struct gpio_chip *chip, unsigned offset, int val)
 {
-        struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip);
-        void __iomem *outreg = w90p910_gpio->regbase + GPIO_OUT;
-        void __iomem *pio = w90p910_gpio->regbase + GPIO_DIR;
+        struct nuc900_gpio_chip *nuc900_gpio = to_nuc900_gpio_chip(chip);
+        void __iomem *outreg = nuc900_gpio->regbase + GPIO_OUT;
+        void __iomem *pio = nuc900_gpio->regbase + GPIO_DIR;
         unsigned int regval;
         unsigned long flags;
 
-        spin_lock_irqsave(&w90p910_gpio->gpio_lock, flags);
+        spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags);
 
         regval = __raw_readl(pio);
         regval |= GPIO_GPIO(offset);
@@ -125,28 +125,28 @@ static int w90p910_dir_output(struct gpio_chip *chip, unsigned offset, int val)
 
         __raw_writel(regval, outreg);
 
-        spin_unlock_irqrestore(&w90p910_gpio->gpio_lock, flags);
+        spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags);
 
         return 0;
 }
 
-static struct w90p910_gpio_chip w90p910_gpio[] = {
-        W90P910_GPIO_CHIP("GROUPC", 0, 16),
-        W90P910_GPIO_CHIP("GROUPD", 16, 10),
-        W90P910_GPIO_CHIP("GROUPE", 26, 14),
-        W90P910_GPIO_CHIP("GROUPF", 40, 10),
-        W90P910_GPIO_CHIP("GROUPG", 50, 17),
-        W90P910_GPIO_CHIP("GROUPH", 67, 8),
-        W90P910_GPIO_CHIP("GROUPI", 75, 17),
+static struct nuc900_gpio_chip nuc900_gpio[] = {
+        NUC900_GPIO_CHIP("GROUPC", 0, 16),
+        NUC900_GPIO_CHIP("GROUPD", 16, 10),
+        NUC900_GPIO_CHIP("GROUPE", 26, 14),
+        NUC900_GPIO_CHIP("GROUPF", 40, 10),
+        NUC900_GPIO_CHIP("GROUPG", 50, 17),
+        NUC900_GPIO_CHIP("GROUPH", 67, 8),
+        NUC900_GPIO_CHIP("GROUPI", 75, 17),
 };
 
-void __init w90p910_init_gpio(int nr_group)
+void __init nuc900_init_gpio(int nr_group)
 {
         unsigned        i;
-        struct w90p910_gpio_chip *gpio_chip;
+        struct nuc900_gpio_chip *gpio_chip;
 
         for (i = 0; i < nr_group; i++) {
-                gpio_chip = &w90p910_gpio[i];
+                gpio_chip = &nuc900_gpio[i];
                 spin_lock_init(&gpio_chip->gpio_lock);
                 gpio_chip->regbase = GPIO_BASE + i * GROUPINERV;
                 gpiochip_add(&gpio_chip->chip);
diff --git a/arch/arm/mach-w90x900/include/mach/regs-clock.h b/arch/arm/mach-w90x900/include/mach/regs-clock.h
index f10b6a8dc069..516d6b477b61 100644
--- a/arch/arm/mach-w90x900/include/mach/regs-clock.h
+++ b/arch/arm/mach-w90x900/include/mach/regs-clock.h
@@ -28,4 +28,26 @@
 #define REG_CLKEN1      (CLK_BA + 0x24)
 #define REG_CLKDIV1     (CLK_BA + 0x28)
 
+/* Define PLL freq setting */
+#define PLL_DISABLE             0x12B63
+#define PLL_66MHZ               0x2B63
+#define PLL_100MHZ              0x4F64
+#define PLL_120MHZ              0x4F63
+#define PLL_166MHZ              0x4124
+#define PLL_200MHZ              0x4F24
+
+/* Define AHB:CPUFREQ ratio */
+#define AHB_CPUCLK_1_1          0x00
+#define AHB_CPUCLK_1_2          0x01
+#define AHB_CPUCLK_1_4          0x02
+#define AHB_CPUCLK_1_8          0x03
+
+/* Define APB:AHB ratio */
+#define APB_AHB_1_2             0x01
+#define APB_AHB_1_4             0x02
+#define APB_AHB_1_8             0x03
+
+/* Define clock skew */
+#define DEFAULTSKEW             0x48
+
 #endif /*  __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-w90x900/include/mach/regs-ebi.h b/arch/arm/mach-w90x900/include/mach/regs-ebi.h
new file mode 100644
index 000000000000..b68455e7f88b
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/regs-ebi.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-w90x900/include/mach/regs-ebi.h
+ *
+ * Copyright (c) 2009 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_REGS_EBI_H
+#define __ASM_ARCH_REGS_EBI_H
+
+/* EBI Control Registers */
+
+#define EBI_BA          W90X900_VA_EBI
+#define REG_EBICON      (EBI_BA + 0x00)
+#define REG_ROMCON      (EBI_BA + 0x04)
+#define REG_SDCONF0     (EBI_BA + 0x08)
+#define REG_SDCONF1     (EBI_BA + 0x0C)
+#define REG_SDTIME0     (EBI_BA + 0x10)
+#define REG_SDTIME1     (EBI_BA + 0x14)
+#define REG_EXT0CON     (EBI_BA + 0x18)
+#define REG_EXT1CON     (EBI_BA + 0x1C)
+#define REG_EXT2CON     (EBI_BA + 0x20)
+#define REG_EXT3CON     (EBI_BA + 0x24)
+#define REG_EXT4CON     (EBI_BA + 0x28)
+#define REG_CKSKEW      (EBI_BA + 0x2C)
+
+#endif /*  __ASM_ARCH_REGS_EBI_H */
diff --git a/arch/arm/mach-w90x900/include/mach/w90p910_keypad.h b/arch/arm/mach-w90x900/include/mach/w90p910_keypad.h
new file mode 100644
index 000000000000..556778e8ddaa
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/w90p910_keypad.h
@@ -0,0 +1,15 @@
+#ifndef __ASM_ARCH_W90P910_KEYPAD_H
+#define __ASM_ARCH_W90P910_KEYPAD_H
+
+#include <linux/input/matrix_keypad.h>
+
+extern void mfp_set_groupi(struct device *dev);
+
+struct w90p910_keypad_platform_data {
+        const struct matrix_keymap_data *keymap_data;
+
+        unsigned int    prescale;
+        unsigned int    debounce;
+};
+
+#endif /* __ASM_ARCH_W90P910_KEYPAD_H */
diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c
index 0b4fc194729c..0ce9d8e867eb 100644
--- a/arch/arm/mach-w90x900/irq.c
+++ b/arch/arm/mach-w90x900/irq.c
@@ -10,8 +10,7 @@
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * the Free Software Foundation;version 2 of the License.
  *
  */
 
@@ -29,9 +28,114 @@
 #include <mach/hardware.h>
 #include <mach/regs-irq.h>
 
-static void w90x900_irq_mask(unsigned int irq)
+struct group_irq {
+        unsigned long           gpen;
+        unsigned int            enabled;
+        void                    (*enable)(struct group_irq *, int enable);
+};
+
+static DEFINE_SPINLOCK(groupirq_lock);
+
+#define DEFINE_GROUP(_name, _ctrlbit, _num)                             \
+struct group_irq group_##_name = {                                      \
+                .enable         = nuc900_group_enable,                  \
+                .gpen           = ((1 << _num) - 1) << _ctrlbit,        \
+        }
+
+static void nuc900_group_enable(struct group_irq *gpirq, int enable);
+
+static DEFINE_GROUP(nirq0, 0, 4);
+static DEFINE_GROUP(nirq1, 4, 4);
+static DEFINE_GROUP(usbh, 8, 2);
+static DEFINE_GROUP(ottimer, 16, 3);
+static DEFINE_GROUP(gdma, 20, 2);
+static DEFINE_GROUP(sc, 24, 2);
+static DEFINE_GROUP(i2c, 26, 2);
+static DEFINE_GROUP(ps2, 28, 2);
+
+static int group_irq_enable(struct group_irq *group_irq)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&groupirq_lock, flags);
+        if (group_irq->enabled++ == 0)
+                (group_irq->enable)(group_irq, 1);
+        spin_unlock_irqrestore(&groupirq_lock, flags);
+
+        return 0;
+}
+
+static void group_irq_disable(struct group_irq *group_irq)
 {
+        unsigned long flags;
+
+        WARN_ON(group_irq->enabled == 0);
+
+        spin_lock_irqsave(&groupirq_lock, flags);
+        if (--group_irq->enabled == 0)
+                (group_irq->enable)(group_irq, 0);
+        spin_unlock_irqrestore(&groupirq_lock, flags);
+}
+
+static void nuc900_group_enable(struct group_irq *gpirq, int enable)
+{
+        unsigned int groupen = gpirq->gpen;
+        unsigned long regval;
+
+        regval = __raw_readl(REG_AIC_GEN);
+
+        if (enable)
+                regval |= groupen;
+        else
+                regval &= ~groupen;
+
+        __raw_writel(regval, REG_AIC_GEN);
+}
+
+static void nuc900_irq_mask(unsigned int irq)
+{
+        struct group_irq *group_irq;
+
+        group_irq = NULL;
+
         __raw_writel(1 << irq, REG_AIC_MDCR);
+
+        switch (irq) {
+        case IRQ_GROUP0:
+                group_irq = &group_nirq0;
+                break;
+
+        case IRQ_GROUP1:
+                group_irq = &group_nirq1;
+                break;
+
+        case IRQ_USBH:
+                group_irq = &group_usbh;
+                break;
+
+        case IRQ_T_INT_GROUP:
+                group_irq = &group_ottimer;
+                break;
+
+        case IRQ_GDMAGROUP:
+                group_irq = &group_gdma;
+                break;
+
+        case IRQ_SCGROUP:
+                group_irq = &group_sc;
+                break;
+
+        case IRQ_I2CGROUP:
+                group_irq = &group_i2c;
+                break;
+
+        case IRQ_P2SGROUP:
+                group_irq = &group_ps2;
+                break;
+        }
+
+        if (group_irq)
+                group_irq_disable(group_irq);
 }
 
 /*
@@ -39,37 +143,71 @@ static void w90x900_irq_mask(unsigned int irq)
  * to REG_AIC_EOSCR for ACK
  */
 
-static void w90x900_irq_ack(unsigned int irq)
+static void nuc900_irq_ack(unsigned int irq)
 {
         __raw_writel(0x01, REG_AIC_EOSCR);
 }
 
-static void w90x900_irq_unmask(unsigned int irq)
+static void nuc900_irq_unmask(unsigned int irq)
 {
-        unsigned long mask;
+        struct group_irq *group_irq;
+
+        group_irq = NULL;
 
-        if (irq == IRQ_T_INT_GROUP) {
-                mask = __raw_readl(REG_AIC_GEN);
-                __raw_writel(TIME_GROUP_IRQ | mask, REG_AIC_GEN);
-                __raw_writel(1 << IRQ_T_INT_GROUP, REG_AIC_MECR);
-        }
         __raw_writel(1 << irq, REG_AIC_MECR);
+
+        switch (irq) {
+        case IRQ_GROUP0:
+                group_irq = &group_nirq0;
+                break;
+
+        case IRQ_GROUP1:
+                group_irq = &group_nirq1;
+                break;
+
+        case IRQ_USBH:
+                group_irq = &group_usbh;
+                break;
+
+        case IRQ_T_INT_GROUP:
+                group_irq = &group_ottimer;
+                break;
+
+        case IRQ_GDMAGROUP:
+                group_irq = &group_gdma;
+                break;
+
+        case IRQ_SCGROUP:
+                group_irq = &group_sc;
+                break;
+
+        case IRQ_I2CGROUP:
+                group_irq = &group_i2c;
+                break;
+
+        case IRQ_P2SGROUP:
+                group_irq = &group_ps2;
+                break;
+        }
+
+        if (group_irq)
+                group_irq_enable(group_irq);
 }
 
-static struct irq_chip w90x900_irq_chip = {
-        .ack       = w90x900_irq_ack,
-        .mask      = w90x900_irq_mask,
-        .unmask    = w90x900_irq_unmask,
+static struct irq_chip nuc900_irq_chip = {
+        .ack       = nuc900_irq_ack,
+        .mask      = nuc900_irq_mask,
+        .unmask    = nuc900_irq_unmask,
 };
 
-void __init w90x900_init_irq(void)
+void __init nuc900_init_irq(void)
 {
         int irqno;
 
         __raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
 
         for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) {
-                set_irq_chip(irqno, &w90x900_irq_chip);
+                set_irq_chip(irqno, &nuc900_irq_chip);
                 set_irq_handler(irqno, handle_level_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
diff --git a/arch/arm/mach-w90x900/mach-nuc910evb.c b/arch/arm/mach-w90x900/mach-nuc910evb.c
new file mode 100644
index 000000000000..ec05bda946f3
--- /dev/null
+++ b/arch/arm/mach-w90x900/mach-nuc910evb.c
@@ -0,0 +1,44 @@
+/*
+ * linux/arch/arm/mach-w90x900/mach-nuc910evb.c
+ *
+ * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche
+ *
+ * Copyright (C) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+#include <mach/map.h>
+
+#include "nuc910.h"
+
+static void __init nuc910evb_map_io(void)
+{
+        nuc910_map_io();
+        nuc910_init_clocks();
+}
+
+static void __init nuc910evb_init(void)
+{
+        nuc910_board_init();
+}
+
+MACHINE_START(W90P910EVB, "W90P910EVB")
+        /* Maintainer: Wan ZongShun */
+        .phys_io        = W90X900_PA_UART,
+        .io_pg_offst    = (((u32)W90X900_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = 0,
+        .map_io         = nuc910evb_map_io,
+        .init_irq       = nuc900_init_irq,
+        .init_machine   = nuc910evb_init,
+        .timer          = &nuc900_timer,
+MACHINE_END
diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c
new file mode 100644
index 000000000000..cef903bcccd1
--- /dev/null
+++ b/arch/arm/mach-w90x900/mach-nuc950evb.c
@@ -0,0 +1,44 @@
+/*
+ * linux/arch/arm/mach-w90x900/mach-nuc950evb.c
+ *
+ * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche
+ *
+ * Copyright (C) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+#include <mach/map.h>
+
+#include "nuc950.h"
+
+static void __init nuc950evb_map_io(void)
+{
+        nuc950_map_io();
+        nuc950_init_clocks();
+}
+
+static void __init nuc950evb_init(void)
+{
+        nuc950_board_init();
+}
+
+MACHINE_START(W90P950EVB, "W90P950EVB")
+        /* Maintainer: Wan ZongShun */
+        .phys_io        = W90X900_PA_UART,
+        .io_pg_offst    = (((u32)W90X900_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = 0,
+        .map_io         = nuc950evb_map_io,
+        .init_irq       = nuc900_init_irq,
+        .init_machine   = nuc950evb_init,
+        .timer          = &nuc900_timer,
+MACHINE_END
diff --git a/arch/arm/mach-w90x900/mach-nuc960evb.c b/arch/arm/mach-w90x900/mach-nuc960evb.c
new file mode 100644
index 000000000000..e3a46f19f2bc
--- /dev/null
+++ b/arch/arm/mach-w90x900/mach-nuc960evb.c
@@ -0,0 +1,44 @@
+/*
+ * linux/arch/arm/mach-w90x900/mach-nuc960evb.c
+ *
+ * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche
+ *
+ * Copyright (C) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+#include <mach/map.h>
+
+#include "nuc960.h"
+
+static void __init nuc960evb_map_io(void)
+{
+        nuc960_map_io();
+        nuc960_init_clocks();
+}
+
+static void __init nuc960evb_init(void)
+{
+        nuc960_board_init();
+}
+
+MACHINE_START(W90N960EVB, "W90N960EVB")
+        /* Maintainer: Wan ZongShun */
+        .phys_io        = W90X900_PA_UART,
+        .io_pg_offst    = (((u32)W90X900_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = 0,
+        .map_io         = nuc960evb_map_io,
+        .init_irq       = nuc900_init_irq,
+        .init_machine   = nuc960evb_init,
+        .timer          = &nuc900_timer,
+MACHINE_END
diff --git a/arch/arm/mach-w90x900/mach-w90p910evb.c b/arch/arm/mach-w90x900/mach-w90p910evb.c
deleted file mode 100644
index 7a62bd348e80..000000000000
--- a/arch/arm/mach-w90x900/mach-w90p910evb.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * linux/arch/arm/mach-w90x900/mach-w90p910evb.c
- *
- * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche
- *
- * Copyright (C) 2008 Nuvoton technology corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation;version 2 of the License.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach-types.h>
-
-#include <mach/regs-serial.h>
-#include <mach/map.h>
-
-#include "cpu.h"
-/*w90p910 evb norflash driver data */
-
-#define W90P910_FLASH_BASE      0xA0000000
-#define W90P910_FLASH_SIZE      0x400000
-
-static struct mtd_partition w90p910_flash_partitions[] = {
-        {
-                .name   =       "NOR Partition 1 for kernel (960K)",
-                .size   =       0xF0000,
-                .offset =       0x10000,
-        },
-        {
-                .name   =       "NOR Partition 2 for image (1M)",
-                .size   =       0x100000,
-                .offset =       0x100000,
-        },
-        {
-                .name   =       "NOR Partition 3 for user (2M)",
-                .size   =       0x200000,
-                .offset =       0x00200000,
-        }
-};
-
-static struct physmap_flash_data w90p910_flash_data = {
-        .width          =       2,
-        .parts          =       w90p910_flash_partitions,
-        .nr_parts       =       ARRAY_SIZE(w90p910_flash_partitions),
-};
-
-static struct resource w90p910_flash_resources[] = {
-        {
-                .start  =       W90P910_FLASH_BASE,
-                .end    =       W90P910_FLASH_BASE + W90P910_FLASH_SIZE - 1,
-                .flags  =       IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device w90p910_flash_device = {
-        .name           =       "physmap-flash",
-        .id             =       0,
-        .dev            = {
-                                .platform_data = &w90p910_flash_data,
-                        },
-        .resource       =       w90p910_flash_resources,
-        .num_resources  =       ARRAY_SIZE(w90p910_flash_resources),
-};
-
-/* USB EHCI Host Controller */
-
-static struct resource w90x900_usb_ehci_resource[] = {
-        [0] = {
-                .start = W90X900_PA_USBEHCIHOST,
-                .end   = W90X900_PA_USBEHCIHOST + W90X900_SZ_USBEHCIHOST - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_USBH,
-                .end   = IRQ_USBH,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-
-static u64 w90x900_device_usb_ehci_dmamask = 0xffffffffUL;
-
-struct platform_device w90x900_device_usb_ehci = {
-        .name             = "w90x900-ehci",
-        .id               = -1,
-        .num_resources    = ARRAY_SIZE(w90x900_usb_ehci_resource),
-        .resource         = w90x900_usb_ehci_resource,
-        .dev              = {
-                .dma_mask = &w90x900_device_usb_ehci_dmamask,
-                .coherent_dma_mask = 0xffffffffUL
-        }
-};
-EXPORT_SYMBOL(w90x900_device_usb_ehci);
-
-/* USB OHCI Host Controller */
-
-static struct resource w90x900_usb_ohci_resource[] = {
-        [0] = {
-                .start = W90X900_PA_USBOHCIHOST,
-                .end   = W90X900_PA_USBOHCIHOST + W90X900_SZ_USBOHCIHOST - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_USBH,
-                .end   = IRQ_USBH,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-
-static u64 w90x900_device_usb_ohci_dmamask = 0xffffffffUL;
-struct platform_device w90x900_device_usb_ohci = {
-        .name             = "w90x900-ohci",
-        .id               = -1,
-        .num_resources    = ARRAY_SIZE(w90x900_usb_ohci_resource),
-        .resource         = w90x900_usb_ohci_resource,
-        .dev              = {
-                .dma_mask = &w90x900_device_usb_ohci_dmamask,
-                .coherent_dma_mask = 0xffffffffUL
-        }
-};
-EXPORT_SYMBOL(w90x900_device_usb_ohci);
-
-/*TouchScreen controller*/
-
-static struct resource w90x900_ts_resource[] = {
-        [0] = {
-                .start = W90X900_PA_ADC,
-                .end   = W90X900_PA_ADC + W90X900_SZ_ADC-1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_ADC,
-                .end   = IRQ_ADC,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device w90x900_device_ts = {
-        .name           = "w90x900-ts",
-        .id             = -1,
-        .resource       = w90x900_ts_resource,
-        .num_resources  = ARRAY_SIZE(w90x900_ts_resource),
-};
-EXPORT_SYMBOL(w90x900_device_ts);
-
-/* RTC controller*/
-
-static struct resource w90x900_rtc_resource[] = {
-        [0] = {
-                .start = W90X900_PA_RTC,
-                .end   = W90X900_PA_RTC + 0xff,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_RTC,
-                .end   = IRQ_RTC,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device w90x900_device_rtc = {
-        .name           = "w90x900-rtc",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(w90x900_rtc_resource),
-        .resource       = w90x900_rtc_resource,
-};
-EXPORT_SYMBOL(w90x900_device_rtc);
-
-/* KPI controller*/
-
-static struct resource w90x900_kpi_resource[] = {
-        [0] = {
-                .start = W90X900_PA_KPI,
-                .end   = W90X900_PA_KPI + W90X900_SZ_KPI - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_KPI,
-                .end   = IRQ_KPI,
-                .flags = IORESOURCE_IRQ,
-        }
-
-};
-
-struct platform_device w90x900_device_kpi = {
-        .name           = "w90x900-kpi",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(w90x900_kpi_resource),
-        .resource       = w90x900_kpi_resource,
-};
-EXPORT_SYMBOL(w90x900_device_kpi);
-
-/* USB Device (Gadget)*/
-
-static struct resource w90x900_usbgadget_resource[] = {
-        [0] = {
-                .start = W90X900_PA_USBDEV,
-                .end   = W90X900_PA_USBDEV + W90X900_SZ_USBDEV - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_USBD,
-                .end   = IRQ_USBD,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device w90x900_device_usbgadget = {
-        .name           = "w90x900-usbgadget",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(w90x900_usbgadget_resource),
-        .resource       = w90x900_usbgadget_resource,
-};
-EXPORT_SYMBOL(w90x900_device_usbgadget);
-
-static struct map_desc w90p910_iodesc[] __initdata = {
-};
-
-/*Here should be your evb resourse,such as LCD*/
-
-static struct platform_device *w90p910evb_dev[] __initdata = {
-        &w90p910_serial_device,
-        &w90p910_flash_device,
-        &w90x900_device_usb_ehci,
-        &w90x900_device_usb_ohci,
-        &w90x900_device_ts,
-        &w90x900_device_rtc,
-        &w90x900_device_kpi,
-        &w90x900_device_usbgadget,
-};
-
-static void __init w90p910evb_map_io(void)
-{
-        w90p910_map_io(w90p910_iodesc, ARRAY_SIZE(w90p910_iodesc));
-        w90p910_init_clocks();
-}
-
-static void __init w90p910evb_init(void)
-{
-        platform_add_devices(w90p910evb_dev, ARRAY_SIZE(w90p910evb_dev));
-}
-
-MACHINE_START(W90P910EVB, "W90P910EVB")
-        /* Maintainer: Wan ZongShun */
-        .phys_io        = W90X900_PA_UART,
-        .io_pg_offst    = (((u32)W90X900_VA_UART) >> 18) & 0xfffc,
-        .boot_params    = 0,
-        .map_io         = w90p910evb_map_io,
-        .init_irq       = w90x900_init_irq,
-        .init_machine   = w90p910evb_init,
-        .timer          = &w90x900_timer,
-MACHINE_END
diff --git a/arch/arm/mach-w90x900/mfp-w90p910.c b/arch/arm/mach-w90x900/mfp-w90p910.c
deleted file mode 100644
index a3520fefb5e7..000000000000
--- a/arch/arm/mach-w90x900/mfp-w90p910.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * linux/arch/arm/mach-w90x900/mfp-w90p910.c
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation;version 2 of the License.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-
-#define REG_MFSEL       (W90X900_VA_GCR + 0xC)
-
-#define GPSELF          (0x01 << 1)
-
-#define GPSELC          (0x03 << 2)
-#define ENKPI           (0x02 << 2)
-#define ENNAND          (0x01 << 2)
-
-#define GPSELEI0        (0x01 << 26)
-#define GPSELEI1        (0x01 << 27)
-
-static DECLARE_MUTEX(mfp_sem);
-
-void mfp_set_groupf(struct device *dev)
-{
-        unsigned long mfpen;
-        const char *dev_id;
-
-        BUG_ON(!dev);
-
-        down(&mfp_sem);
-
-        dev_id = dev_name(dev);
-
-        mfpen = __raw_readl(REG_MFSEL);
-
-        if (strcmp(dev_id, "w90p910-emc") == 0)
-                mfpen |= GPSELF;/*enable mac*/
-        else
-                mfpen &= ~GPSELF;/*GPIOF[9:0]*/
-
-        __raw_writel(mfpen, REG_MFSEL);
-
-        up(&mfp_sem);
-}
-EXPORT_SYMBOL(mfp_set_groupf);
-
-void mfp_set_groupc(struct device *dev)
-{
-        unsigned long mfpen;
-        const char *dev_id;
-
-        BUG_ON(!dev);
-
-        down(&mfp_sem);
-
-        dev_id = dev_name(dev);
-
-        mfpen = __raw_readl(REG_MFSEL);
-
-        if (strcmp(dev_id, "w90p910-lcd") == 0)
-                mfpen |= GPSELC;/*enable lcd*/
-        else if (strcmp(dev_id, "w90p910-kpi") == 0) {
-                        mfpen &= (~GPSELC);/*enable kpi*/
-                        mfpen |= ENKPI;
-                } else if (strcmp(dev_id, "w90p910-nand") == 0) {
-                                mfpen &= (~GPSELC);/*enable nand*/
-                                mfpen |= ENNAND;
-                        } else
-                                mfpen &= (~GPSELC);/*GPIOC[14:0]*/
-
-        __raw_writel(mfpen, REG_MFSEL);
-
-        up(&mfp_sem);
-}
-EXPORT_SYMBOL(mfp_set_groupc);
-
-void mfp_set_groupi(struct device *dev, int gpio)
-{
-        unsigned long mfpen;
-        const char *dev_id;
-
-        BUG_ON(!dev);
-
-        down(&mfp_sem);
-
-        dev_id = dev_name(dev);
-
-        mfpen = __raw_readl(REG_MFSEL);
-
-        if (strcmp(dev_id, "w90p910-wdog") == 0)
-                mfpen |= GPSELEI1;/*enable wdog*/
-                else if (strcmp(dev_id, "w90p910-atapi") == 0)
-                        mfpen |= GPSELEI0;/*enable atapi*/
-
-        __raw_writel(mfpen, REG_MFSEL);
-
-        up(&mfp_sem);
-}
-EXPORT_SYMBOL(mfp_set_groupi);
-
diff --git a/arch/arm/mach-w90x900/mfp.c b/arch/arm/mach-w90x900/mfp.c
new file mode 100644
index 000000000000..a47dc9a708ee
--- /dev/null
+++ b/arch/arm/mach-w90x900/mfp.c
@@ -0,0 +1,158 @@
+/*
+ * linux/arch/arm/mach-w90x900/mfp.c
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+
+#define REG_MFSEL       (W90X900_VA_GCR + 0xC)
+
+#define GPSELF          (0x01 << 1)
+
+#define GPSELC          (0x03 << 2)
+#define ENKPI           (0x02 << 2)
+#define ENNAND          (0x01 << 2)
+
+#define GPSELEI0        (0x01 << 26)
+#define GPSELEI1        (0x01 << 27)
+
+#define GPIOG0TO1       (0x03 << 14)
+#define GPIOG2TO3       (0x03 << 16)
+#define ENSPI           (0x0a << 14)
+#define ENI2C0          (0x01 << 14)
+#define ENI2C1          (0x01 << 16)
+
+static DEFINE_MUTEX(mfp_mutex);
+
+void mfp_set_groupf(struct device *dev)
+{
+        unsigned long mfpen;
+        const char *dev_id;
+
+        BUG_ON(!dev);
+
+        mutex_lock(&mfp_mutex);
+
+        dev_id = dev_name(dev);
+
+        mfpen = __raw_readl(REG_MFSEL);
+
+        if (strcmp(dev_id, "nuc900-emc") == 0)
+                mfpen |= GPSELF;/*enable mac*/
+        else
+                mfpen &= ~GPSELF;/*GPIOF[9:0]*/
+
+        __raw_writel(mfpen, REG_MFSEL);
+
+        mutex_unlock(&mfp_mutex);
+}
+EXPORT_SYMBOL(mfp_set_groupf);
+
+void mfp_set_groupc(struct device *dev)
+{
+        unsigned long mfpen;
+        const char *dev_id;
+
+        BUG_ON(!dev);
+
+        mutex_lock(&mfp_mutex);
+
+        dev_id = dev_name(dev);
+
+        mfpen = __raw_readl(REG_MFSEL);
+
+        if (strcmp(dev_id, "nuc900-lcd") == 0)
+                mfpen |= GPSELC;/*enable lcd*/
+        else if (strcmp(dev_id, "nuc900-kpi") == 0) {
+                mfpen &= (~GPSELC);/*enable kpi*/
+                mfpen |= ENKPI;
+        } else if (strcmp(dev_id, "nuc900-nand") == 0) {
+                mfpen &= (~GPSELC);/*enable nand*/
+                mfpen |= ENNAND;
+        } else
+                mfpen &= (~GPSELC);/*GPIOC[14:0]*/
+
+        __raw_writel(mfpen, REG_MFSEL);
+
+        mutex_unlock(&mfp_mutex);
+}
+EXPORT_SYMBOL(mfp_set_groupc);
+
+void mfp_set_groupi(struct device *dev)
+{
+        unsigned long mfpen;
+        const char *dev_id;
+
+        BUG_ON(!dev);
+
+        mutex_lock(&mfp_mutex);
+
+        dev_id = dev_name(dev);
+
+        mfpen = __raw_readl(REG_MFSEL);
+
+        mfpen &= ~GPSELEI1;/*default gpio16*/
+
+        if (strcmp(dev_id, "nuc900-wdog") == 0)
+                mfpen |= GPSELEI1;/*enable wdog*/
+        else if (strcmp(dev_id, "nuc900-atapi") == 0)
+                mfpen |= GPSELEI0;/*enable atapi*/
+        else if (strcmp(dev_id, "nuc900-keypad") == 0)
+                mfpen &= ~GPSELEI0;/*enable keypad*/
+
+        __raw_writel(mfpen, REG_MFSEL);
+
+        mutex_unlock(&mfp_mutex);
+}
+EXPORT_SYMBOL(mfp_set_groupi);
+
+void mfp_set_groupg(struct device *dev)
+{
+        unsigned long mfpen;
+        const char *dev_id;
+
+        BUG_ON(!dev);
+
+        mutex_lock(&mfp_mutex);
+
+        dev_id = dev_name(dev);
+
+        mfpen = __raw_readl(REG_MFSEL);
+
+        if (strcmp(dev_id, "nuc900-spi") == 0) {
+                mfpen &= ~(GPIOG0TO1 | GPIOG2TO3);
+                mfpen |= ENSPI;/*enable spi*/
+        } else if (strcmp(dev_id, "nuc900-i2c0") == 0) {
+                mfpen &= ~(GPIOG0TO1);
+                mfpen |= ENI2C0;/*enable i2c0*/
+        } else if (strcmp(dev_id, "nuc900-i2c1") == 0) {
+                mfpen &= ~(GPIOG2TO3);
+                mfpen |= ENI2C1;/*enable i2c1*/
+        } else {
+                mfpen &= ~(GPIOG0TO1 | GPIOG2TO3);/*GPIOG[3:0]*/
+        }
+
+        __raw_writel(mfpen, REG_MFSEL);
+
+        mutex_unlock(&mfp_mutex);
+}
+EXPORT_SYMBOL(mfp_set_groupg);
+
diff --git a/arch/arm/mach-w90x900/nuc910.c b/arch/arm/mach-w90x900/nuc910.c
new file mode 100644
index 000000000000..656f03b3b629
--- /dev/null
+++ b/arch/arm/mach-w90x900/nuc910.c
@@ -0,0 +1,60 @@
+/*
+ * linux/arch/arm/mach-w90x900/nuc910.c
+ *
+ * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks
+ *
+ * Copyright (c) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * NUC910 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include "cpu.h"
+#include "clock.h"
+
+/* define specific CPU platform device */
+
+static struct platform_device *nuc910_dev[] __initdata = {
+        &nuc900_device_ts,
+        &nuc900_device_rtc,
+};
+
+/* define specific CPU platform io map */
+
+static struct map_desc nuc910evb_iodesc[] __initdata = {
+        IODESC_ENT(USBEHCIHOST),
+        IODESC_ENT(USBOHCIHOST),
+        IODESC_ENT(KPI),
+        IODESC_ENT(USBDEV),
+        IODESC_ENT(ADC),
+};
+
+/*Init NUC910 evb io*/
+
+void __init nuc910_map_io(void)
+{
+        nuc900_map_io(nuc910evb_iodesc, ARRAY_SIZE(nuc910evb_iodesc));
+}
+
+/*Init NUC910 clock*/
+
+void __init nuc910_init_clocks(void)
+{
+        nuc900_init_clocks();
+}
+
+/*Init NUC910 board info*/
+
+void __init nuc910_board_init(void)
+{
+        nuc900_board_init(nuc910_dev, ARRAY_SIZE(nuc910_dev));
+}
diff --git a/arch/arm/mach-w90x900/nuc910.h b/arch/arm/mach-w90x900/nuc910.h
new file mode 100644
index 000000000000..83e9ba5fc26c
--- /dev/null
+++ b/arch/arm/mach-w90x900/nuc910.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-w90x900/nuc910.h
+ *
+ * Copyright (c) 2008 Nuvoton corporation
+ *
+ * Header file for NUC900 CPU support
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+struct map_desc;
+struct sys_timer;
+
+/* core initialisation functions */
+
+extern void nuc900_init_irq(void);
+extern struct sys_timer nuc900_timer;
+
+/* extern file from nuc910.c */
+
+extern void nuc910_board_init(void);
+extern void nuc910_init_clocks(void);
+extern void nuc910_map_io(void);
diff --git a/arch/arm/mach-w90x900/nuc950.c b/arch/arm/mach-w90x900/nuc950.c
new file mode 100644
index 000000000000..149508116d18
--- /dev/null
+++ b/arch/arm/mach-w90x900/nuc950.c
@@ -0,0 +1,54 @@
+/*
+ * linux/arch/arm/mach-w90x900/nuc950.c
+ *
+ * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * NUC950 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include "cpu.h"
+
+/* define specific CPU platform device */
+
+static struct platform_device *nuc950_dev[] __initdata = {
+        &nuc900_device_kpi,
+        &nuc900_device_fmi,
+};
+
+/* define specific CPU platform io map */
+
+static struct map_desc nuc950evb_iodesc[] __initdata = {
+};
+
+/*Init NUC950 evb io*/
+
+void __init nuc950_map_io(void)
+{
+        nuc900_map_io(nuc950evb_iodesc, ARRAY_SIZE(nuc950evb_iodesc));
+}
+
+/*Init NUC950 clock*/
+
+void __init nuc950_init_clocks(void)
+{
+        nuc900_init_clocks();
+}
+
+/*Init NUC950 board info*/
+
+void __init nuc950_board_init(void)
+{
+        nuc900_board_init(nuc950_dev, ARRAY_SIZE(nuc950_dev));
+}
diff --git a/arch/arm/mach-w90x900/nuc950.h b/arch/arm/mach-w90x900/nuc950.h
new file mode 100644
index 000000000000..98a1148bc5ae
--- /dev/null
+++ b/arch/arm/mach-w90x900/nuc950.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-w90x900/nuc950.h
+ *
+ * Copyright (c) 2008 Nuvoton corporation
+ *
+ * Header file for NUC900 CPU support
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+struct map_desc;
+struct sys_timer;
+
+/* core initialisation functions */
+
+extern void nuc900_init_irq(void);
+extern struct sys_timer nuc900_timer;
+
+/* extern file from nuc950.c */
+
+extern void nuc950_board_init(void);
+extern void nuc950_init_clocks(void);
+extern void nuc950_map_io(void);
diff --git a/arch/arm/mach-w90x900/nuc960.c b/arch/arm/mach-w90x900/nuc960.c
new file mode 100644
index 000000000000..8851a3a27ce2
--- /dev/null
+++ b/arch/arm/mach-w90x900/nuc960.c
@@ -0,0 +1,54 @@
+/*
+ * linux/arch/arm/mach-w90x900/nuc960.c
+ *
+ * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * NUC960 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include "cpu.h"
+
+/* define specific CPU platform device */
+
+static struct platform_device *nuc960_dev[] __initdata = {
+        &nuc900_device_kpi,
+        &nuc900_device_fmi,
+};
+
+/* define specific CPU platform io map */
+
+static struct map_desc nuc960evb_iodesc[] __initdata = {
+};
+
+/*Init NUC960 evb io*/
+
+void __init nuc960_map_io(void)
+{
+        nuc900_map_io(nuc960evb_iodesc, ARRAY_SIZE(nuc960evb_iodesc));
+}
+
+/*Init NUC960 clock*/
+
+void __init nuc960_init_clocks(void)
+{
+        nuc900_init_clocks();
+}
+
+/*Init NUC960 board info*/
+
+void __init nuc960_board_init(void)
+{
+        nuc900_board_init(nuc960_dev, ARRAY_SIZE(nuc960_dev));
+}
diff --git a/arch/arm/mach-w90x900/nuc960.h b/arch/arm/mach-w90x900/nuc960.h
new file mode 100644
index 000000000000..f0c07cbe3a82
--- /dev/null
+++ b/arch/arm/mach-w90x900/nuc960.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-w90x900/nuc960.h
+ *
+ * Copyright (c) 2008 Nuvoton corporation
+ *
+ * Header file for NUC900 CPU support
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+struct map_desc;
+struct sys_timer;
+
+/* core initialisation functions */
+
+extern void nuc900_init_irq(void);
+extern struct sys_timer nuc900_timer;
+
+/* extern file from nuc960.c */
+
+extern void nuc960_board_init(void);
+extern void nuc960_init_clocks(void);
+extern void nuc960_map_io(void);
diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c
index bcc838f6b393..4128af870b41 100644
--- a/arch/arm/mach-w90x900/time.c
+++ b/arch/arm/mach-w90x900/time.c
@@ -3,7 +3,7 @@
  *
  * Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks
  *
- * Copyright (c) 2008 Nuvoton technology corporation
+ * Copyright (c) 2009 Nuvoton technology corporation
  * All rights reserved.
  *
  * Wan ZongShun <mcuos.com@gmail.com>
@@ -23,6 +23,8 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/leds.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/irq.h>
@@ -31,49 +33,150 @@
 #include <mach/map.h>
 #include <mach/regs-timer.h>
 
-static unsigned long w90x900_gettimeoffset(void)
+#define RESETINT        0x1f
+#define PERIOD          (0x01 << 27)
+#define ONESHOT         (0x00 << 27)
+#define COUNTEN         (0x01 << 30)
+#define INTEN           (0x01 << 29)
+
+#define TICKS_PER_SEC   100
+#define PRESCALE        0x63 /* Divider = prescale + 1 */
+
+unsigned int timer0_load;
+
+static void nuc900_clockevent_setmode(enum clock_event_mode mode,
+                struct clock_event_device *clk)
 {
+        unsigned int val;
+
+        val = __raw_readl(REG_TCSR0);
+        val &= ~(0x03 << 27);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                __raw_writel(timer0_load, REG_TICR0);
+                val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
+                break;
+
+        case CLOCK_EVT_MODE_ONESHOT:
+                val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
+                break;
+
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+
+        __raw_writel(val, REG_TCSR0);
+}
+
+static int nuc900_clockevent_setnextevent(unsigned long evt,
+                struct clock_event_device *clk)
+{
+        unsigned int val;
+
+        __raw_writel(evt, REG_TICR0);
+
+        val = __raw_readl(REG_TCSR0);
+        val |= (COUNTEN | INTEN | PRESCALE);
+        __raw_writel(val, REG_TCSR0);
+
         return 0;
 }
 
+static struct clock_event_device nuc900_clockevent_device = {
+        .name           = "nuc900-timer0",
+        .shift          = 32,
+        .features       = CLOCK_EVT_MODE_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .set_mode       = nuc900_clockevent_setmode,
+        .set_next_event = nuc900_clockevent_setnextevent,
+        .rating         = 300,
+};
+
 /*IRQ handler for the timer*/
 
-static irqreturn_t
-w90x900_timer_interrupt(int irq, void *dev_id)
+static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id)
 {
-        timer_tick();
+        struct clock_event_device *evt = &nuc900_clockevent_device;
+
         __raw_writel(0x01, REG_TISR); /* clear TIF0 */
+
+        evt->event_handler(evt);
         return IRQ_HANDLED;
 }
 
-static struct irqaction w90x900_timer_irq = {
-        .name           = "w90x900 Timer Tick",
+static struct irqaction nuc900_timer0_irq = {
+        .name           = "nuc900-timer0",
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = w90x900_timer_interrupt,
+        .handler        = nuc900_timer0_interrupt,
 };
 
-/*Set up timer reg.*/
+static void __init nuc900_clockevents_init(unsigned int rate)
+{
+        nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
+                                        nuc900_clockevent_device.shift);
+        nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
+                                        &nuc900_clockevent_device);
+        nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf,
+                                        &nuc900_clockevent_device);
+        nuc900_clockevent_device.cpumask = cpumask_of(0);
 
-static void w90x900_timer_setup(void)
+        clockevents_register_device(&nuc900_clockevent_device);
+}
+
+static cycle_t nuc900_get_cycles(struct clocksource *cs)
 {
-        __raw_writel(0, REG_TCSR0);
-        __raw_writel(0, REG_TCSR1);
-        __raw_writel(0, REG_TCSR2);
-        __raw_writel(0, REG_TCSR3);
-        __raw_writel(0, REG_TCSR4);
-        __raw_writel(0x1F, REG_TISR);
-        __raw_writel(15000000/(100 * 100), REG_TICR0);
-        __raw_writel(0x68000063, REG_TCSR0);
+        return ~__raw_readl(REG_TDR1);
 }
 
-static void __init w90x900_timer_init(void)
+static struct clocksource clocksource_nuc900 = {
+        .name   = "nuc900-timer1",
+        .rating = 200,
+        .read   = nuc900_get_cycles,
+        .mask   = CLOCKSOURCE_MASK(32),
+        .shift  = 20,
+        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init nuc900_clocksource_init(unsigned int rate)
 {
-        w90x900_timer_setup();
-        setup_irq(IRQ_TIMER0, &w90x900_timer_irq);
+        unsigned int val;
+
+        __raw_writel(0xffffffff, REG_TICR1);
+
+        val = __raw_readl(REG_TCSR1);
+        val |= (COUNTEN | PERIOD);
+        __raw_writel(val, REG_TCSR1);
+
+        clocksource_nuc900.mult =
+                clocksource_khz2mult((rate / 1000), clocksource_nuc900.shift);
+        clocksource_register(&clocksource_nuc900);
+}
+
+static void __init nuc900_timer_init(void)
+{
+        struct clk *ck_ext = clk_get(NULL, "ext");
+        unsigned int    rate;
+
+        BUG_ON(IS_ERR(ck_ext));
+
+        rate = clk_get_rate(ck_ext);
+        clk_put(ck_ext);
+        rate = rate / (PRESCALE + 0x01);
+
+         /* set a known state */
+        __raw_writel(0x00, REG_TCSR0);
+        __raw_writel(0x00, REG_TCSR1);
+        __raw_writel(RESETINT, REG_TISR);
+        timer0_load = (rate / TICKS_PER_SEC);
+
+        setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
+
+        nuc900_clocksource_init(rate);
+        nuc900_clockevents_init(rate);
 }
 
-struct sys_timer w90x900_timer = {
-        .init           = w90x900_timer_init,
-        .offset         = w90x900_gettimeoffset,
-        .resume         = w90x900_timer_setup
+struct sys_timer nuc900_timer = {
+        .init           = nuc900_timer_init,
 };
diff --git a/arch/arm/mach-w90x900/w90p910.c b/arch/arm/mach-w90x900/w90p910.c
deleted file mode 100644
index 1c97e4930b7a..000000000000
--- a/arch/arm/mach-w90x900/w90p910.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * linux/arch/arm/mach-w90x900/w90p910.c
- *
- * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks
- *
- * Copyright (c) 2008 Nuvoton technology corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * W90P910 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation;version 2 of the License.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/serial_8250.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/irq.h>
-
-#include <mach/hardware.h>
-#include <mach/regs-serial.h>
-
-#include "cpu.h"
-#include "clock.h"
-
-/* Initial IO mappings */
-
-static struct map_desc w90p910_iodesc[] __initdata = {
-        IODESC_ENT(IRQ),
-        IODESC_ENT(GCR),
-        IODESC_ENT(UART),
-        IODESC_ENT(TIMER),
-        IODESC_ENT(EBI),
-        IODESC_ENT(USBEHCIHOST),
-        IODESC_ENT(USBOHCIHOST),
-        IODESC_ENT(ADC),
-        IODESC_ENT(RTC),
-        IODESC_ENT(KPI),
-        IODESC_ENT(USBDEV),
-        /*IODESC_ENT(LCD),*/
-};
-
-/* Initial clock declarations. */
-static DEFINE_CLK(lcd, 0);
-static DEFINE_CLK(audio, 1);
-static DEFINE_CLK(fmi, 4);
-static DEFINE_CLK(dmac, 5);
-static DEFINE_CLK(atapi, 6);
-static DEFINE_CLK(emc, 7);
-static DEFINE_CLK(usbd, 8);
-static DEFINE_CLK(usbh, 9);
-static DEFINE_CLK(g2d, 10);;
-static DEFINE_CLK(pwm, 18);
-static DEFINE_CLK(ps2, 24);
-static DEFINE_CLK(kpi, 25);
-static DEFINE_CLK(wdt, 26);
-static DEFINE_CLK(gdma, 27);
-static DEFINE_CLK(adc, 28);
-static DEFINE_CLK(usi, 29);
-
-static struct clk_lookup w90p910_clkregs[] = {
-        DEF_CLKLOOK(&clk_lcd, "w90p910-lcd", NULL),
-        DEF_CLKLOOK(&clk_audio, "w90p910-audio", NULL),
-        DEF_CLKLOOK(&clk_fmi, "w90p910-fmi", NULL),
-        DEF_CLKLOOK(&clk_dmac, "w90p910-dmac", NULL),
-        DEF_CLKLOOK(&clk_atapi, "w90p910-atapi", NULL),
-        DEF_CLKLOOK(&clk_emc, "w90p910-emc", NULL),
-        DEF_CLKLOOK(&clk_usbd, "w90p910-usbd", NULL),
-        DEF_CLKLOOK(&clk_usbh, "w90p910-usbh", NULL),
-        DEF_CLKLOOK(&clk_g2d, "w90p910-g2d", NULL),
-        DEF_CLKLOOK(&clk_pwm, "w90p910-pwm", NULL),
-        DEF_CLKLOOK(&clk_ps2, "w90p910-ps2", NULL),
-        DEF_CLKLOOK(&clk_kpi, "w90p910-kpi", NULL),
-        DEF_CLKLOOK(&clk_wdt, "w90p910-wdt", NULL),
-        DEF_CLKLOOK(&clk_gdma, "w90p910-gdma", NULL),
-        DEF_CLKLOOK(&clk_adc, "w90p910-adc", NULL),
-        DEF_CLKLOOK(&clk_usi, "w90p910-usi", NULL),
-};
-
-/* Initial serial platform data */
-
-struct plat_serial8250_port w90p910_uart_data[] = {
-        W90X900_8250PORT(UART0),
-};
-
-struct platform_device w90p910_serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = w90p910_uart_data,
-        },
-};
-
-/*Init W90P910 evb io*/
-
-void __init w90p910_map_io(struct map_desc *mach_desc, int mach_size)
-{
-        unsigned long idcode = 0x0;
-
-        iotable_init(w90p910_iodesc, ARRAY_SIZE(w90p910_iodesc));
-
-        idcode = __raw_readl(W90X900PDID);
-        if (idcode != W90P910_CPUID)
-                printk(KERN_ERR "CPU type 0x%08lx is not W90P910\n", idcode);
-}
-
-/*Init W90P910 clock*/
-
-void __init w90p910_init_clocks(void)
-{
-        clks_register(w90p910_clkregs, ARRAY_SIZE(w90p910_clkregs));
-}
-
-static int __init w90p910_init_cpu(void)
-{
-        return 0;
-}
-
-static int __init w90x900_arch_init(void)
-{
-        return w90p910_init_cpu();
-}
-arch_initcall(w90x900_arch_init);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 83c025e72ceb..5fe595aeba69 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -758,7 +758,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 config CACHE_L2X0
         bool "Enable the L2x0 outer cache controller"
         depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX
+                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK
         default y
         select OUTER_CACHE
         help
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 03cd27d917b9..b270d6228fe2 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -159,7 +159,9 @@ union offset_union {
 
 #define __get8_unaligned_check(ins,val,addr,err)        \
         __asm__(                                        \
-        "1:     "ins"   %1, [%2], #1\n"                 \
+ ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
+ THUMB( "1:     "ins"   %1, [%2]\n"     )               \
+ THUMB( "       add     %2, %2, #1\n"   )               \
         "2:\n"                                          \
         "       .section .fixup,\"ax\"\n"               \
         "       .align  2\n"                            \
@@ -215,7 +217,9 @@ union offset_union {
         do {                                                    \
                 unsigned int err = 0, v = val, a = addr;        \
                 __asm__( FIRST_BYTE_16                          \
-                "1:     "ins"   %1, [%2], #1\n"                 \
+         ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
+         THUMB( "1:     "ins"   %1, [%2]\n"     )               \
+         THUMB( "       add     %2, %2, #1\n"   )               \
                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
                 "2:     "ins"   %1, [%2]\n"                     \
                 "3:\n"                                          \
@@ -245,11 +249,17 @@ union offset_union {
         do {                                                    \
                 unsigned int err = 0, v = val, a = addr;        \
                 __asm__( FIRST_BYTE_32                          \
-                "1:     "ins"   %1, [%2], #1\n"                 \
+         ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
+         THUMB( "1:     "ins"   %1, [%2]\n"     )               \
+         THUMB( "       add     %2, %2, #1\n"   )               \
                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
-                "2:     "ins"   %1, [%2], #1\n"                 \
+         ARM(   "2:     "ins"   %1, [%2], #1\n" )               \
+         THUMB( "2:     "ins"   %1, [%2]\n"     )               \
+         THUMB( "       add     %2, %2, #1\n"   )               \
                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
-                "3:     "ins"   %1, [%2], #1\n"                 \
+         ARM(   "3:     "ins"   %1, [%2], #1\n" )               \
+         THUMB( "3:     "ins"   %1, [%2]\n"     )               \
+         THUMB( "       add     %2, %2, #1\n"   )               \
                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
                 "4:     "ins"   %1, [%2]\n"                     \
                 "5:\n"                                          \
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index be93ff02a98d..bda0ec31a4e2 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -21,7 +21,7 @@
  *
  *      Flush the whole D-cache.
  *
- *      Corrupted registers: r0-r5, r7, r9-r11
+ *      Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
  *
  *      - mm    - mm_struct describing address space
  */
@@ -51,8 +51,12 @@ loop1:
 loop2:
         mov     r9, r4                          @ create working copy of max way size
 loop3:
-        orr     r11, r10, r9, lsl r5            @ factor way and cache number into r11
-        orr     r11, r11, r7, lsl r2            @ factor index number into r11
+ ARM(   orr     r11, r10, r9, lsl r5    )       @ factor way and cache number into r11
+ THUMB( lsl     r6, r9, r5              )
+ THUMB( orr     r11, r10, r6            )       @ factor way and cache number into r11
+ ARM(   orr     r11, r11, r7, lsl r2    )       @ factor index number into r11
+ THUMB( lsl     r6, r7, r2              )
+ THUMB( orr     r11, r11, r6            )       @ factor index number into r11
         mcr     p15, 0, r11, c7, c14, 2         @ clean & invalidate by set/way
         subs    r9, r9, #1                      @ decrement the way
         bge     loop3
@@ -82,11 +86,13 @@ ENDPROC(v7_flush_dcache_all)
  *
  */
 ENTRY(v7_flush_kern_cache_all)
-        stmfd   sp!, {r4-r5, r7, r9-r11, lr}
+ ARM(   stmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
+ THUMB( stmfd   sp!, {r4-r7, r9-r11, lr}        )
         bl      v7_flush_dcache_all
         mov     r0, #0
         mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
-        ldmfd   sp!, {r4-r5, r7, r9-r11, lr}
+ ARM(   ldmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
+ THUMB( ldmfd   sp!, {r4-r7, r9-r11, lr}        )
         mov     pc, lr
 ENDPROC(v7_flush_kern_cache_all)
 
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 510c179b0ac8..b30925fcbcdc 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -36,7 +36,34 @@
 #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
 #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
 
+static u64 get_coherent_dma_mask(struct device *dev)
+{
+        u64 mask = ISA_DMA_THRESHOLD;
+
+        if (dev) {
+                mask = dev->coherent_dma_mask;
+
+                /*
+                 * Sanity check the DMA mask - it must be non-zero, and
+                 * must be able to be satisfied by a DMA allocation.
+                 */
+                if (mask == 0) {
+                        dev_warn(dev, "coherent DMA mask is unset\n");
+                        return 0;
+                }
+
+                if ((~mask) & ISA_DMA_THRESHOLD) {
+                        dev_warn(dev, "coherent DMA mask %#llx is smaller "
+                                 "than system GFP_DMA mask %#llx\n",
+                                 mask, (unsigned long long)ISA_DMA_THRESHOLD);
+                        return 0;
+                }
+        }
 
+        return mask;
+}
+
+#ifdef CONFIG_MMU
 /*
  * These are the page tables (2MB each) covering uncached, DMA consistent allocations
  */
@@ -152,7 +179,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
         struct page *page;
         struct arm_vm_region *c;
         unsigned long order;
-        u64 mask = ISA_DMA_THRESHOLD, limit;
+        u64 mask = get_coherent_dma_mask(dev);
+        u64 limit;
 
         if (!consistent_pte[0]) {
                 printk(KERN_ERR "%s: not initialised\n", __func__);
@@ -160,25 +188,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
                 return NULL;
         }
 
-        if (dev) {
-                mask = dev->coherent_dma_mask;
-
-                /*
-                 * Sanity check the DMA mask - it must be non-zero, and
-                 * must be able to be satisfied by a DMA allocation.
-                 */
-                if (mask == 0) {
-                        dev_warn(dev, "coherent DMA mask is unset\n");
-                        goto no_page;
-                }
-
-                if ((~mask) & ISA_DMA_THRESHOLD) {
-                        dev_warn(dev, "coherent DMA mask %#llx is smaller "
-                                 "than system GFP_DMA mask %#llx\n",
-                                 mask, (unsigned long long)ISA_DMA_THRESHOLD);
-                        goto no_page;
-                }
-        }
+        if (!mask)
+                goto no_page;
 
         /*
          * Sanity check the allocation size.
@@ -267,6 +278,31 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
         *handle = ~0;
         return NULL;
 }
+#else   /* !CONFIG_MMU */
+static void *
+__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
+            pgprot_t prot)
+{
+        void *virt;
+        u64 mask = get_coherent_dma_mask(dev);
+
+        if (!mask)
+                goto error;
+
+        if (mask != 0xffffffff)
+                gfp |= GFP_DMA;
+        virt = kmalloc(size, gfp);
+        if (!virt)
+                goto error;
+
+        *handle =  virt_to_dma(dev, virt);
+        return virt;
+
+error:
+        *handle = ~0;
+        return NULL;
+}
+#endif  /* CONFIG_MMU */
 
 /*
  * Allocate DMA-coherent memory space and return both the kernel remapped
@@ -311,9 +347,10 @@ EXPORT_SYMBOL(dma_alloc_writecombine);
 static int dma_mmap(struct device *dev, struct vm_area_struct *vma,
                     void *cpu_addr, dma_addr_t dma_addr, size_t size)
 {
+        int ret = -ENXIO;
+#ifdef CONFIG_MMU
         unsigned long flags, user_size, kern_size;
         struct arm_vm_region *c;
-        int ret = -ENXIO;
 
         user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
 
@@ -334,6 +371,7 @@ static int dma_mmap(struct device *dev, struct vm_area_struct *vma,
                                               vma->vm_page_prot);
                 }
         }
+#endif  /* CONFIG_MMU */
 
         return ret;
 }
@@ -358,6 +396,7 @@ EXPORT_SYMBOL(dma_mmap_writecombine);
  * free a page as defined by the above mapping.
  * Must not be called with IRQs disabled.
  */
+#ifdef CONFIG_MMU
 void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle)
 {
         struct arm_vm_region *c;
@@ -444,6 +483,14 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr
                __func__, cpu_addr);
         dump_stack();
 }
+#else   /* !CONFIG_MMU */
+void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle)
+{
+        if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
+                return;
+        kfree(cpu_addr);
+}
+#endif  /* CONFIG_MMU */
 EXPORT_SYMBOL(dma_free_coherent);
 
 /*
@@ -451,10 +498,12 @@ EXPORT_SYMBOL(dma_free_coherent);
  */
 static int __init consistent_init(void)
 {
+        int ret = 0;
+#ifdef CONFIG_MMU
         pgd_t *pgd;
         pmd_t *pmd;
         pte_t *pte;
-        int ret = 0, i = 0;
+        int i = 0;
         u32 base = CONSISTENT_BASE;
 
         do {
@@ -477,6 +526,7 @@ static int __init consistent_init(void)
                 consistent_pte[i++] = pte;
                 base += (1 << PGDIR_SHIFT);
         } while (base < CONSISTENT_END);
+#endif  /* !CONFIG_MMU */
 
         return ret;
 }
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 6fdcbb709827..cc8829d7e116 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -16,6 +16,8 @@
 #include <linux/kprobes.h>
 #include <linux/uaccess.h>
 #include <linux/page-flags.h>
+#include <linux/sched.h>
+#include <linux/highmem.h>
 
 #include <asm/system.h>
 #include <asm/pgtable.h>
@@ -23,6 +25,7 @@
 
 #include "fault.h"
 
+#ifdef CONFIG_MMU
 
 #ifdef CONFIG_KPROBES
 static inline int notify_page_fault(struct pt_regs *regs, unsigned int fsr)
@@ -97,6 +100,10 @@ void show_pte(struct mm_struct *mm, unsigned long addr)
 
         printk("\n");
 }
+#else                                   /* CONFIG_MMU */
+void show_pte(struct mm_struct *mm, unsigned long addr)
+{ }
+#endif                                  /* CONFIG_MMU */
 
 /*
  * Oops.  The kernel tried to access some page that wasn't present.
@@ -171,6 +178,7 @@ void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
                 __do_kernel_fault(mm, addr, fsr, regs);
 }
 
+#ifdef CONFIG_MMU
 #define VM_FAULT_BADMAP         0x010000
 #define VM_FAULT_BADACCESS      0x020000
 
@@ -322,6 +330,13 @@ no_context:
         __do_kernel_fault(mm, addr, fsr, regs);
         return 0;
 }
+#else                                   /* CONFIG_MMU */
+static int
+do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
+{
+        return 0;
+}
+#endif                                  /* CONFIG_MMU */
 
 /*
  * First Level Translation Fault Handler
@@ -340,6 +355,7 @@ no_context:
  * interrupt or a critical region, and should only copy the information
  * from the master page table, nothing more.
  */
+#ifdef CONFIG_MMU
 static int __kprobes
 do_translation_fault(unsigned long addr, unsigned int fsr,
                      struct pt_regs *regs)
@@ -378,6 +394,14 @@ bad_area:
         do_bad_area(addr, fsr, regs);
         return 0;
 }
+#else                                   /* CONFIG_MMU */
+static int
+do_translation_fault(unsigned long addr, unsigned int fsr,
+                     struct pt_regs *regs)
+{
+        return 0;
+}
+#endif                                  /* CONFIG_MMU */
 
 /*
  * Some section permission faults need to be handled gracefully.
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index c07222eb5ce0..575f3ad722e7 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -144,7 +144,14 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
          * page.  This ensures that data in the physical page is mutually
          * coherent with the kernels mapping.
          */
-        __cpuc_flush_dcache_page(page_address(page));
+#ifdef CONFIG_HIGHMEM
+        /*
+         * kmap_atomic() doesn't set the page virtual address, and
+         * kunmap_atomic() takes care of cache flushing already.
+         */
+        if (page_address(page))
+#endif
+                __cpuc_flush_dcache_page(page_address(page));
 
         /*
          * If this is a page cache page, and we have an aliasing VIPT cache,
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index a34954d9df7d..73cae57fa707 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -40,11 +40,16 @@ void *kmap_atomic(struct page *page, enum km_type type)
 {
         unsigned int idx;
         unsigned long vaddr;
+        void *kmap;
 
         pagefault_disable();
         if (!PageHighMem(page))
                 return page_address(page);
 
+        kmap = kmap_high_get(page);
+        if (kmap)
+                return kmap;
+
         idx = type + KM_TYPE_NR * smp_processor_id();
         vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
 #ifdef CONFIG_DEBUG_HIGHMEM
@@ -80,6 +85,9 @@ void kunmap_atomic(void *kvaddr, enum km_type type)
 #else
                 (void) idx;  /* to kill a warning */
 #endif
+        } else if (vaddr >= PKMAP_ADDR(0) && vaddr < PKMAP_ADDR(LAST_PKMAP)) {
+                /* this address was obtained through kmap_high_get() */
+                kunmap_high(pte_page(pkmap_page_table[PKMAP_NR(vaddr)]));
         }
         pagefault_enable();
 }
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 3a7279c1ce5e..ea36186f32c3 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -15,6 +15,7 @@
 #include <linux/mman.h>
 #include <linux/nodemask.h>
 #include <linux/initrd.h>
+#include <linux/sort.h>
 #include <linux/highmem.h>
 
 #include <asm/mach-types.h>
@@ -349,12 +350,43 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
         free_area_init_node(node, zone_size, min, zhole_size);
 }
 
+#ifndef CONFIG_SPARSEMEM
+int pfn_valid(unsigned long pfn)
+{
+        struct meminfo *mi = &meminfo;
+        unsigned int left = 0, right = mi->nr_banks;
+
+        do {
+                unsigned int mid = (right + left) / 2;
+                struct membank *bank = &mi->bank[mid];
+
+                if (pfn < bank_pfn_start(bank))
+                        right = mid;
+                else if (pfn >= bank_pfn_end(bank))
+                        left = mid + 1;
+                else
+                        return 1;
+        } while (left < right);
+        return 0;
+}
+EXPORT_SYMBOL(pfn_valid);
+#endif
+
+static int __init meminfo_cmp(const void *_a, const void *_b)
+{
+        const struct membank *a = _a, *b = _b;
+        long cmp = bank_pfn_start(a) - bank_pfn_start(b);
+        return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
+}
+
 void __init bootmem_init(void)
 {
         struct meminfo *mi = &meminfo;
         unsigned long min, max_low, max_high;
         int node, initrd_node;
 
+        sort(&mi->bank, mi->nr_banks, sizeof(mi->bank[0]), meminfo_cmp, NULL);
+
         /*
          * Locate which node contains the ramdisk image, if any.
          */
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index ad7bacc693b2..900811cc9130 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -12,6 +12,7 @@
 #include <asm/cacheflush.h>
 #include <asm/sections.h>
 #include <asm/page.h>
+#include <asm/setup.h>
 #include <asm/mach/arch.h>
 
 #include "mm.h"
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 54b1f721dec8..7d63beaf9745 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -77,19 +77,15 @@
  * Sanity check the PTE configuration for the code below - which makes
  * certain assumptions about how these bits are layed out.
  */
+#ifdef CONFIG_MMU
 #if L_PTE_SHARED != PTE_EXT_SHARED
 #error PTE shared bit mismatch
 #endif
-#if L_PTE_BUFFERABLE != PTE_BUFFERABLE
-#error PTE bufferable bit mismatch
-#endif
-#if L_PTE_CACHEABLE != PTE_CACHEABLE
-#error PTE cacheable bit mismatch
-#endif
 #if (L_PTE_EXEC+L_PTE_USER+L_PTE_WRITE+L_PTE_DIRTY+L_PTE_YOUNG+\
      L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
 #error Invalid Linux PTE bit settings
 #endif
+#endif  /* CONFIG_MMU */
 
 /*
  * The ARMv6 and ARMv7 set_pte_ext translation function.
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 180a08d03a03..f3fa1c32fe92 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -127,7 +127,9 @@ ENDPROC(cpu_v7_switch_mm)
  */
 ENTRY(cpu_v7_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
+ ARM(   str     r1, [r0], #-2048        )       @ linux version
+ THUMB( str     r1, [r0]                )       @ linux version
+ THUMB( sub     r0, r0, #2048           )
 
         bic     r3, r1, #0x000003f0
         bic     r3, r3, #PTE_TYPE_MASK
@@ -232,7 +234,6 @@ __v7_setup:
         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
         mov     r10, #0x1f                      @ domains 0, 1 = manager
         mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
-#endif
         /*
          * Memory region attributes with SCTLR.TRE=1
          *
@@ -265,6 +266,7 @@ __v7_setup:
         ldr     r6, =0x40e040e0                 @ NMRR
         mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
         mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
+#endif
         adr     r5, v7_crval
         ldmia   r5, {r5, r6}
 #ifdef CONFIG_CPU_ENDIAN_BE8
@@ -273,6 +275,7 @@ __v7_setup:
         mrc     p15, 0, r0, c1, c0, 0           @ read control register
         bic     r0, r0, r5                      @ clear bits them
         orr     r0, r0, r6                      @ set them
+ THUMB( orr     r0, r0, #1 << 30        )       @ Thumb exceptions
         mov     pc, lr                          @ return to head.S:__ret
 ENDPROC(__v7_setup)
 
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 0cce37b93937..423394260bcb 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -17,7 +17,7 @@
  *
  * 2001 Sep 08:
  *      Completely revisited, many important fixes
- *      Nicolas Pitre <nico@cam.org>
+ *      Nicolas Pitre <nico@fluxnic.net>
  */
 
 #include <linux/linkage.h>
diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/plat-iop/setup.c
index 9e573e78176a..bade586fed0f 100644
--- a/arch/arm/plat-iop/setup.c
+++ b/arch/arm/plat-iop/setup.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/plat-iop/setup.c
  *
- * Author: Nicolas Pitre <nico@cam.org>
+ * Author: Nicolas Pitre <nico@fluxnic.net>
  * Copyright (C) 2001 MontaVista Software, Inc.
  * Copyright (C) 2004 Intel Corporation.
  *
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 8986b7412235..ca5c7c226341 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -9,6 +9,7 @@ choice
 config ARCH_MX1
         bool "MX1-based"
         select CPU_ARM920T
+        select COMMON_CLKDEV
         help
           This enables support for systems based on the Freescale i.MX1 family
 
@@ -19,6 +20,13 @@ config ARCH_MX2
         help
           This enables support for systems based on the Freescale i.MX2 family
 
+config ARCH_MX25
+        bool "MX25-based"
+        select CPU_ARM926T
+        select COMMON_CLKDEV
+        help
+          This enables support for systems based on the Freescale i.MX25 family
+
 config ARCH_MX3
         bool "MX3-based"
         select CPU_V6
@@ -26,11 +34,20 @@ config ARCH_MX3
         help
           This enables support for systems based on the Freescale i.MX3 family
 
+config ARCH_MXC91231
+        bool "MXC91231-based"
+        select CPU_V6
+        select COMMON_CLKDEV
+        help
+          This enables support for systems based on the Freescale MXC91231 family
+
 endchoice
 
 source "arch/arm/mach-mx1/Kconfig"
 source "arch/arm/mach-mx2/Kconfig"
 source "arch/arm/mach-mx3/Kconfig"
+source "arch/arm/mach-mx25/Kconfig"
+source "arch/arm/mach-mxc91231/Kconfig"
 
 endmenu
 
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 92e13566cd4f..9e8fbd57495c 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -39,6 +39,7 @@
 #include <linux/string.h>
 
 #include <mach/clock.h>
+#include <mach/hardware.h>
 
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
@@ -47,76 +48,6 @@ static DEFINE_MUTEX(clocks_mutex);
  * Standard clock functions defined in include/linux/clk.h
  *-------------------------------------------------------------------------*/
 
-/*
- * All the code inside #ifndef CONFIG_COMMON_CLKDEV can be removed once all
- * MXC architectures have switched to using clkdev.
- */
-#ifndef CONFIG_COMMON_CLKDEV
-/*
- * Retrieve a clock by name.
- *
- * Note that we first try to use device id on the bus
- * and clock name. If this fails, we try to use "<name>.<id>". If this fails,
- * we try to use clock name only.
- * The reference count to the clock's module owner ref count is incremented.
- */
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        struct clk *p, *clk = ERR_PTR(-ENOENT);
-        int idno;
-        const char *str;
-
-        if (id == NULL)
-                return clk;
-
-        if (dev == NULL || dev->bus != &platform_bus_type)
-                idno = -1;
-        else
-                idno = to_platform_device(dev)->id;
-
-        mutex_lock(&clocks_mutex);
-
-        list_for_each_entry(p, &clocks, node) {
-                if (p->id == idno &&
-                    strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                        clk = p;
-                        goto found;
-                }
-        }
-
-        str = strrchr(id, '.');
-        if (str) {
-                int cnt = str - id;
-                str++;
-                idno = simple_strtol(str, NULL, 10);
-                list_for_each_entry(p, &clocks, node) {
-                        if (p->id == idno &&
-                            strlen(p->name) == cnt &&
-                            strncmp(id, p->name, cnt) == 0 &&
-                            try_module_get(p->owner)) {
-                                clk = p;
-                                goto found;
-                        }
-                }
-        }
-
-        list_for_each_entry(p, &clocks, node) {
-                if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                        clk = p;
-                        goto found;
-                }
-        }
-
-        printk(KERN_WARNING "clk: Unable to get requested clock: %s\n", id);
-
-found:
-        mutex_unlock(&clocks_mutex);
-
-        return clk;
-}
-EXPORT_SYMBOL(clk_get);
-#endif
-
 static void __clk_disable(struct clk *clk)
 {
         if (clk == NULL || IS_ERR(clk))
@@ -193,16 +124,6 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
 
-#ifndef CONFIG_COMMON_CLKDEV
-/* Decrement the clock's module reference count */
-void clk_put(struct clk *clk)
-{
-        if (clk && !IS_ERR(clk))
-                module_put(clk->owner);
-}
-EXPORT_SYMBOL(clk_put);
-#endif
-
 /* Round the requested clock rate to the nearest supported
  * rate that is less than or equal to the requested rate.
  * This is dependent on the clock's current parent.
@@ -265,80 +186,6 @@ struct clk *clk_get_parent(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_parent);
 
-#ifndef CONFIG_COMMON_CLKDEV
-/*
- * Add a new clock to the clock tree.
- */
-int clk_register(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-
-        mutex_lock(&clocks_mutex);
-        list_add(&clk->node, &clocks);
-        mutex_unlock(&clocks_mutex);
-
-        return 0;
-}
-EXPORT_SYMBOL(clk_register);
-
-/* Remove a clock from the clock tree */
-void clk_unregister(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return;
-
-        mutex_lock(&clocks_mutex);
-        list_del(&clk->node);
-        mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clk_unregister);
-
-#ifdef CONFIG_PROC_FS
-static int mxc_clock_read_proc(char *page, char **start, off_t off,
-                                int count, int *eof, void *data)
-{
-        struct clk *clkp;
-        char *p = page;
-        int len;
-
-        list_for_each_entry(clkp, &clocks, node) {
-                p += sprintf(p, "%s-%d:\t\t%lu, %d", clkp->name, clkp->id,
-                                clk_get_rate(clkp), clkp->usecount);
-                if (clkp->parent)
-                        p += sprintf(p, ", %s-%d\n", clkp->parent->name,
-                                     clkp->parent->id);
-                else
-                        p += sprintf(p, "\n");
-        }
-
-        len = (p - page) - off;
-        if (len < 0)
-                len = 0;
-
-        *eof = (len <= count) ? 1 : 0;
-        *start = page + off;
-
-        return len;
-}
-
-static int __init mxc_setup_proc_entry(void)
-{
-        struct proc_dir_entry *res;
-
-        res = create_proc_read_entry("cpu/clocks", 0, NULL,
-                                     mxc_clock_read_proc, NULL);
-        if (!res) {
-                printk(KERN_ERR "Failed to create proc/cpu/clocks\n");
-                return -ENOMEM;
-        }
-        return 0;
-}
-
-late_initcall(mxc_setup_proc_entry);
-#endif /* CONFIG_PROC_FS */
-#endif
-
 /*
  * Get the resulting clock rate from a PLL register value and the input
  * frequency. PLLs with this register layout can at least be found on
@@ -363,12 +210,11 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
 
         mfn_abs = mfn;
 
-#if !defined CONFIG_ARCH_MX1 && !defined CONFIG_ARCH_MX21
-        if (mfn >= 0x200) {
-                mfn |= 0xFFFFFE00;
-                mfn_abs = -mfn;
-        }
-#endif
+        /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
+         * 2's complements number
+         */
+        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+                mfn_abs = 0x400 - mfn;
 
         freq *= 2;
         freq /= pd + 1;
@@ -376,8 +222,10 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
         ll = (unsigned long long)freq * mfn_abs;
 
         do_div(ll, mfd + 1);
-        if (mfn < 0)
+
+        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
                 ll = -ll;
+
         ll = (freq * mfi) + ll;
 
         return ll;
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 7506d963be4b..cfc4a8b43e6a 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -29,6 +29,23 @@
 static struct mxc_gpio_port *mxc_gpio_ports;
 static int gpio_table_size;
 
+#define cpu_is_mx1_mx2()        (cpu_is_mx1() || cpu_is_mx2())
+
+#define GPIO_DR         (cpu_is_mx1_mx2() ? 0x1c : 0x00)
+#define GPIO_GDIR       (cpu_is_mx1_mx2() ? 0x00 : 0x04)
+#define GPIO_PSR        (cpu_is_mx1_mx2() ? 0x24 : 0x08)
+#define GPIO_ICR1       (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
+#define GPIO_ICR2       (cpu_is_mx1_mx2() ? 0x2C : 0x10)
+#define GPIO_IMR        (cpu_is_mx1_mx2() ? 0x30 : 0x14)
+#define GPIO_ISR        (cpu_is_mx1_mx2() ? 0x34 : 0x18)
+#define GPIO_ISR        (cpu_is_mx1_mx2() ? 0x34 : 0x18)
+
+#define GPIO_INT_LOW_LEV        (cpu_is_mx1_mx2() ? 0x3 : 0x0)
+#define GPIO_INT_HIGH_LEV       (cpu_is_mx1_mx2() ? 0x2 : 0x1)
+#define GPIO_INT_RISE_EDGE      (cpu_is_mx1_mx2() ? 0x0 : 0x2)
+#define GPIO_INT_FALL_EDGE      (cpu_is_mx1_mx2() ? 0x1 : 0x3)
+#define GPIO_INT_NONE           0x4
+
 /* Note: This driver assumes 32 GPIOs are handled in one register */
 
 static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
@@ -162,7 +179,6 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
         }
 }
 
-#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
 /* MX1 and MX3 has one interrupt *per* gpio port */
 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
@@ -174,9 +190,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 
         mxc_gpio_irq_handler(port, irq_stat);
 }
-#endif
 
-#ifdef CONFIG_ARCH_MX2
 /* MX2 has one interrupt *for all* gpio ports */
 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
@@ -195,7 +209,6 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
                         mxc_gpio_irq_handler(&port[i], irq_stat);
         }
 }
-#endif
 
 static struct irq_chip gpio_irq_chip = {
         .ack = gpio_ack_irq,
@@ -284,17 +297,18 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                 /* its a serious configuration bug when it fails */
                 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
 
-#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
-                /* setup one handler for each entry */
-                set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
-                set_irq_data(port[i].irq, &port[i]);
-#endif
+                if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) {
+                        /* setup one handler for each entry */
+                        set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
+                        set_irq_data(port[i].irq, &port[i]);
+                }
+        }
+
+        if (cpu_is_mx2()) {
+                /* setup one handler for all GPIO interrupts */
+                set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
+                set_irq_data(port[0].irq, port);
         }
 
-#ifdef CONFIG_ARCH_MX2
-        /* setup one handler for all GPIO interrupts */
-        set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
-        set_irq_data(port[0].irq, port);
-#endif
         return 0;
 }
diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
index 8769e910e559..0376c133c9f4 100644
--- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
+++ b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
@@ -12,11 +12,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
 #define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
 
-#include <mach/hardware.h>
-
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
new file mode 100644
index 000000000000..a1fd5830af48
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * Based on board-pcm038.h which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
+#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
+
+#ifndef __ASSEMBLY__
+/*
+ * This CPU module needs a baseboard to work. After basic initializing
+ * its own devices, it calls baseboard's init function.
+ * TODO: Add your own baseboard init function and call it from
+ * inside eukrea_cpuimx27_init().
+ *
+ * This example here is for the development board. Refer
+ * eukrea_mbimx27-baseboard.c
+ */
+
+extern void eukrea_mbimx27_baseboard_init(void);
+
+#endif
+
+#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
index 06701df74c42..0cf4fa29510c 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
@@ -15,12 +15,6 @@
 #define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
 
 /*
- * MXC UART EVB board level configurations
- */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPI_IO_ADDRESS(UART1_BASE_ADDR)
-
-/*
  * Memory-mapped I/O on MX21ADS base board
  */
 #define MX21ADS_MMIO_BASE_ADDR   0xF5000000
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
index d42f4e6116f8..7776d230327f 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
@@ -26,12 +26,6 @@
                                 MXC_MAX_VIRTUAL_INTS)
 
 /*
- * MXC UART EVB board level configurations
- */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPI_IO_ADDRESS(UART1_BASE_ADDR)
-
-/*
  * @name Memory Size parameters
  */
 
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
index a870f8ea2443..ea87551d2736 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
@@ -11,9 +11,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__
 #define __ASM_ARCH_MXC_BOARD_MX27LITE_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
index 552b55d714d8..fec1bcfa9164 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
@@ -11,9 +11,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__
 #define __ASM_ARCH_MXC_BOARD_MX27PDK_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 06e6895f7f65..2cbfa35e82ff 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -114,9 +114,4 @@
 
 #define MXC_MAX_EXP_IO_LINES    16
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
index 78cf31e22e4d..eb5a5024622e 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
@@ -22,11 +22,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
 #define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
 
-/* mandatory for CONFIG_LL_DEBUG */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
-
 #ifndef __ASSEMBLY__
 
 enum mx31lilly_boards {
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 52fbdf2d6f26..8e64325d6905 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -11,8 +11,5 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
 #define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
 
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
 
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index 303fd2434a21..d5be6b5a6acf 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -19,11 +19,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
 #define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
-
 #ifndef __ASSEMBLY__
 
 enum mx31moboard_boards {
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
index 519bab3eb28b..2bbd6ed17f50 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
@@ -11,11 +11,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__
 #define __ASM_ARCH_MXC_BOARD_MX31PDK_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 /* Definitions for components on the Debug board */
 
 /* Base address of CPLD controller on the Debug board */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
index 1111037d6d9d..383f1c04df06 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
@@ -19,9 +19,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__
 #define __ASM_ARCH_MXC_BOARD_MX35PDK_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/plat-mxc/include/mach/board-pcm037.h
index f0a1fa1938a2..13411709b13a 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm037.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm037.h
@@ -19,9 +19,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
 #define __ASM_ARCH_MXC_BOARD_PCM037_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h
index 4fcd7499e092..410f9786ed22 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm038.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h
@@ -19,11 +19,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
 #define __ASM_ARCH_MXC_BOARD_PCM038_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
-
 #ifndef __ASSEMBLY__
 /*
  * This CPU module needs a baseboard to work. After basic initializing
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/plat-mxc/include/mach/board-pcm043.h
index 15fbdf16abcd..1ac4e1682e5c 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm043.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm043.h
@@ -19,9 +19,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__
 #define __ASM_ARCH_MXC_BOARD_PCM043_H__
 
-/* mandatory for CONFIG_LL_DEBUG */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
index 04033ec637d2..6d88c7af4b23 100644
--- a/arch/arm/plat-mxc/include/mach/board-qong.h
+++ b/arch/arm/plat-mxc/include/mach/board-qong.h
@@ -11,11 +11,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
 #define __ASM_ARCH_MXC_BOARD_QONG_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 /* NOR FLASH */
 #define QONG_NOR_SIZE           (128*1024*1024)
 
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 02c3cd004db3..286cb9b0a25b 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -16,18 +16,33 @@ struct clk;
 
 extern void mx1_map_io(void);
 extern void mx21_map_io(void);
+extern void mx25_map_io(void);
 extern void mx27_map_io(void);
 extern void mx31_map_io(void);
 extern void mx35_map_io(void);
-extern void mxc_init_irq(void);
-extern void mxc_timer_init(struct clk *timer_clk);
+extern void mxc91231_map_io(void);
+extern void mxc_init_irq(void __iomem *);
+extern void mx1_init_irq(void);
+extern void mx21_init_irq(void);
+extern void mx25_init_irq(void);
+extern void mx27_init_irq(void);
+extern void mx31_init_irq(void);
+extern void mx35_init_irq(void);
+extern void mxc91231_init_irq(void);
+extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
 extern int mx1_clocks_init(unsigned long fref);
 extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
+extern int mx25_clocks_init(unsigned long fref);
 extern int mx27_clocks_init(unsigned long fref);
 extern int mx31_clocks_init(unsigned long fref);
 extern int mx35_clocks_init(void);
+extern int mxc91231_clocks_init(unsigned long fref);
 extern int mxc_register_gpios(void);
 extern int mxc_register_device(struct platform_device *pdev, void *data);
 extern void mxc_set_cpu_type(unsigned int type);
+extern void mxc_arch_reset_init(void __iomem *);
+extern void mxc91231_power_off(void);
+extern void mxc91231_arch_reset(int, const char *);
+extern void mxc91231_prepare_idle(void);
 
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index bbc5f6753cfb..15b2b148a105 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -11,52 +11,52 @@
  *
  */
 
-#include <mach/hardware.h>
-
-#ifdef CONFIG_MACH_MX31ADS
-#include <mach/board-mx31ads.h>
-#endif
-#ifdef CONFIG_MACH_PCM037
-#include <mach/board-pcm037.h>
-#endif
-#ifdef CONFIG_MACH_MX31LITE
-#include <mach/board-mx31lite.h>
-#endif
-#ifdef CONFIG_MACH_MX27ADS
-#include <mach/board-mx27ads.h>
-#endif
-#ifdef CONFIG_MACH_MX21ADS
-#include <mach/board-mx21ads.h>
+#ifdef CONFIG_ARCH_MX1
+#include <mach/mx1.h>
+#define UART_PADDR      UART1_BASE_ADDR
+#define UART_VADDR      IO_ADDRESS(UART1_BASE_ADDR)
 #endif
-#ifdef CONFIG_MACH_PCM038
-#include <mach/board-pcm038.h>
+
+#ifdef CONFIG_ARCH_MX25
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#ifdef CONFIG_MACH_MX31_3DS
-#include <mach/board-mx31pdk.h>
+#include <mach/mx25.h>
+#define UART_PADDR      UART1_BASE_ADDR
+#define UART_VADDR      MX25_AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif
-#ifdef CONFIG_MACH_QONG
-#include <mach/board-qong.h>
+
+#ifdef CONFIG_ARCH_MX2
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#ifdef CONFIG_MACH_PCM043
-#include <mach/board-pcm043.h>
+#include <mach/mx2x.h>
+#define UART_PADDR      UART1_BASE_ADDR
+#define UART_VADDR      AIPI_IO_ADDRESS(UART1_BASE_ADDR)
 #endif
-#ifdef CONFIG_MACH_MX27_3DS
-#include <mach/board-mx27pdk.h>
+
+#ifdef CONFIG_ARCH_MX3
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#ifdef CONFIG_MACH_ARMADILLO5X0
-#include <mach/board-armadillo5x0.h>
+#include <mach/mx3x.h>
+#define UART_PADDR      UART1_BASE_ADDR
+#define UART_VADDR      AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif
-#ifdef CONFIG_MACH_MX35_3DS
-#include <mach/board-mx35pdk.h>
+
+#ifdef CONFIG_ARCH_MXC91231
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#ifdef CONFIG_MACH_MX27LITE
-#include <mach/board-mx27lite.h>
+#include <mach/mxc91231.h>
+#define UART_PADDR      MXC91231_UART2_BASE_ADDR
+#define UART_VADDR      MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
 #endif
                 .macro  addruart,rx
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
-                ldreq   \rx, =MXC_LL_UART_PADDR @ physical
-                ldrne   \rx, =MXC_LL_UART_VADDR @ virtual
+                ldreq   \rx, =UART_PADDR        @ physical
+                ldrne   \rx, =UART_VADDR        @ virtual
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 5f01d60da845..7cf290efe768 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -18,7 +18,8 @@
         .endm
 
         .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
+        ldr     \base, =avic_base
+        ldr     \base, [\base]
 #ifdef CONFIG_MXC_IRQ_PRIOR
         ldr     r4, [\base, #AVIC_NIMASK]
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 42e4ee37ca1f..78db75475f69 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -42,6 +42,14 @@
 # include <mach/mx1.h>
 #endif
 
+#ifdef CONFIG_ARCH_MX25
+# include <mach/mx25.h>
+#endif
+
+#ifdef CONFIG_ARCH_MXC91231
+# include <mach/mxc91231.h>
+#endif
+
 #include <mach/mxc.h>
 
 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h
index 9f0101157ec1..5263506b7ddf 100644
--- a/arch/arm/plat-mxc/include/mach/imxfb.h
+++ b/arch/arm/plat-mxc/include/mach/imxfb.h
@@ -2,6 +2,8 @@
  * This structure describes the machine which we are running on.
  */
 
+#include <linux/fb.h>
+
 #define PCR_TFT         (1 << 31)
 #define PCR_COLOR       (1 << 30)
 #define PCR_PBSIZ_1     (0 << 28)
@@ -13,7 +15,8 @@
 #define PCR_BPIX_4      (2 << 25)
 #define PCR_BPIX_8      (3 << 25)
 #define PCR_BPIX_12     (4 << 25)
-#define PCR_BPIX_16     (4 << 25)
+#define PCR_BPIX_16     (5 << 25)
+#define PCR_BPIX_18     (6 << 25)
 #define PCR_PIXPOL      (1 << 24)
 #define PCR_FLMPOL      (1 << 23)
 #define PCR_LPPOL       (1 << 22)
@@ -46,29 +49,21 @@
 #define DMACR_HM(x)     (((x) & 0xf) << 16)
 #define DMACR_TM(x)     ((x) & 0xf)
 
-struct imx_fb_platform_data {
-        u_long          pixclock;
-
-        u_short         xres;
-        u_short         yres;
-
-        u_int           nonstd;
-        u_char          bpp;
-        u_char          hsync_len;
-        u_char          left_margin;
-        u_char          right_margin;
+struct imx_fb_videomode {
+        struct fb_videomode mode;
+        u32 pcr;
+        unsigned char   bpp;
+};
 
-        u_char          vsync_len;
-        u_char          upper_margin;
-        u_char          lower_margin;
-        u_char          sync;
+struct imx_fb_platform_data {
+        struct imx_fb_videomode *mode;
+        int             num_modes;
 
         u_int           cmap_greyscale:1,
                         cmap_inverse:1,
                         cmap_static:1,
                         unused:29;
 
-        u_int           pcr;
         u_int           pwmr;
         u_int           lscr1;
         u_int           dmacr;
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
new file mode 100644
index 000000000000..810c47f56e77
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -0,0 +1,517 @@
+/*
+ * arch/arm/plat-mxc/include/mach/iomux-mx25.h
+ *
+ * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
+ *
+ * based on arch/arm/mach-mx25/mx25_pins.h
+ *    Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * and
+ * arch/arm/plat-mxc/include/mach/iomux-mx35.h
+ *    Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __IOMUX_MX25_H__
+#define __IOMUX_MX25_H__
+
+#include <mach/iomux-v3.h>
+
+#ifndef GPIO_PORTA
+#error Please include mach/iomux.h
+#endif
+
+/*
+ *
+ * @brief MX25 I/O Pin List
+ *
+ * @ingroup GPIO_MX25
+ */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * IOMUX/PAD Bit field definitions
+ */
+
+#define MX25_PAD_A10__A10               IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A10__GPIO_4_0          IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A13__A13               IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A13__GPIO_4_1          IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A14__A14               IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A14__GPIO_2_0          IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A15__A15               IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A15__GPIO_2_1          IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A16__A16               IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A16__GPIO_2_2          IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A17__A17               IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A17__GPIO_2_3          IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A18__A18               IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A18__GPIO_2_4          IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A18__FEC_COL           IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTL)
+
+#define MX25_PAD_A19__A19               IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A19__FEC_RX_ER         IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTL)
+#define MX25_PAD_A19__GPIO_2_5          IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A20__A20               IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A20__GPIO_2_6          IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A20__FEC_RDATA2        IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTL)
+
+#define MX25_PAD_A21__A21               IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A21__GPIO_2_7          IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A21__FEC_RDATA3        IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTL)
+
+#define MX25_PAD_A22__A22               IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A22__GPIO_2_8          IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A23__A23               IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A23__GPIO_2_9          IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A24__A24               IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A24__GPIO_2_10         IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A24__FEC_RX_CLK        IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTL)
+
+#define MX25_PAD_A25__A25               IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A25__GPIO_2_11         IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A25__FEC_CRS           IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTL)
+
+#define MX25_PAD_EB0__EB0               IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_EB0__AUD4_TXD          IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL)
+#define MX25_PAD_EB0__GPIO_2_12         IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_EB1__EB1               IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_EB1__AUD4_RXD          IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL)
+#define MX25_PAD_EB1__GPIO_2_13         IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_OE__OE                 IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_OE__AUD4_TXC           IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_OE__GPIO_2_14          IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CS0__CS0               IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS0__GPIO_4_2          IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CS1__CS1               IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS1__GPIO_4_3          IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CS4__CS4               IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS4__UART5_CTS         IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS4__GPIO_3_20         IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CS5__CS5               IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS5__UART5_RTS         IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS5__GPIO_3_21         IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_NF_CE0__NF_CE0         IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_NF_CE0__GPIO_3_22      IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_ECB__ECB               IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_ECB__UART5_TXD_MUX     IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_ECB__GPIO_3_23         IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LBA__LBA               IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LBA__UART5_RXD_MUX     IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL)
+#define MX25_PAD_LBA__GPIO_3_24         IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_BCLK__BCLK             IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_BCLK__GPIO_4_4         IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_RW__RW                 IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_RW__AUD4_TXFS          IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL)
+#define MX25_PAD_RW__GPIO_3_25          IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_NFWE_B__NFWE_B         IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFWE_B__GPIO_3_26      IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_NFRE_B__NFRE_B         IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFRE_B__GPIO_3_27      IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_NFALE__NFALE           IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFALE__GPIO_3_28       IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_NFCLE__NFCLE           IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFCLE__GPIO_3_29       IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_NFWP_B__NFWP_B         IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFWP_B__GPIO_3_30      IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_NFRB__NFRB             IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_NFRB__GPIO_3_31        IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D15__D15               IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D15__LD16              IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D15__GPIO_4_5          IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D14__D14               IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D14__LD17              IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D14__GPIO_4_6          IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D13__D13               IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D13__LD18              IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D13__GPIO_4_7          IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D12__D12               IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D12__GPIO_4_8          IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D11__D11               IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D11__GPIO_4_9          IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D10__D10               IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D10__GPIO_4_10         IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D10__USBOTG_OC         IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP)
+
+#define MX25_PAD_D9__D9                 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D9__GPIO_4_11          IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D9__USBH2_PWR          IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE)
+
+#define MX25_PAD_D8__D8                 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D8__GPIO_4_12          IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D8__USBH2_OC           IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP)
+
+#define MX25_PAD_D7__D7                 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D7__GPIO_4_13          IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D6__D6                 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D6__GPIO_4_14          IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D5__D5                 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D5__GPIO_4_15          IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D4__D4                 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D4__GPIO_4_16          IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D3__D3                 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D3__GPIO_4_17          IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D2__D2                 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D2__GPIO_4_18          IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D1__D1                 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D1__GPIO_4_19          IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D0__D0                 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D0__GPIO_4_20          IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD0__LD0               IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD0__CSI_D0            IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD0__GPIO_2_15         IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD1__LD1               IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD1__CSI_D1            IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD1__GPIO_2_16         IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD2__LD2               IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD2__GPIO_2_17         IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD3__LD3               IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD3__GPIO_2_18         IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD4__LD4               IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD4__GPIO_2_19         IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD5__LD5               IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD5__GPIO_1_19         IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD6__LD6               IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD6__GPIO_1_20         IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD7__LD7               IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD7__GPIO_1_21         IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD8__LD8               IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD8__FEC_TX_ERR        IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTL)
+
+#define MX25_PAD_LD9__LD9               IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD9__FEC_COL           IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTL)
+
+#define MX25_PAD_LD10__LD10             IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD10__FEC_RX_ER        IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTL)
+
+#define MX25_PAD_LD11__LD11             IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD11__FEC_RDATA2       IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTL)
+
+#define MX25_PAD_LD12__LD12             IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD12__FEC_RDATA3       IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTL)
+
+#define MX25_PAD_LD13__LD13             IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD13__FEC_TDATA2       IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTL)
+
+#define MX25_PAD_LD14__LD14             IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD14__FEC_TDATA3       IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTL)
+
+#define MX25_PAD_LD15__LD15             IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD15__FEC_RX_CLK       IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTL)
+
+#define MX25_PAD_HSYNC__HSYNC           IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_HSYNC__GPIO_1_22       IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_VSYNC__VSYNC           IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSYNC__GPIO_1_23       IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LSCLK__LSCLK           IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LSCLK__GPIO_1_24       IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_OE_ACD__OE_ACD         IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_OE_ACD__GPIO_1_25      IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CONTRAST__CONTRAST     IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CONTRAST__FEC_CRS      IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTL)
+
+#define MX25_PAD_PWM__PWM               IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_PWM__GPIO_1_26         IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_PWM__USBH2_OC          IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP)
+
+#define MX25_PAD_CSI_D2__CSI_D2         IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D2__UART5_RXD_MUX  IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D2__GPIO_1_27      IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_D3__CSI_D3         IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D3__GPIO_1_28      IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_D4__CSI_D4         IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D4__UART5_RTS      IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D4__GPIO_1_29      IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_D5__CSI_D5         IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D5__GPIO_1_30      IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_D6__CSI_D6         IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D6__GPIO_1_31      IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_D7__CSI_D7         IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D7__GPIO_1_6       IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_D8__CSI_D8         IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D8__GPIO_1_7       IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_D9__CSI_D9         IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D9__GPIO_4_21      IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_MCLK__CSI_MCLK     IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_MCLK__GPIO_1_8     IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_VSYNC__CSI_VSYNC   IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_VSYNC__GPIO_1_9    IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_HSYNC__CSI_HSYNC   IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_HSYNC__GPIO_1_10   IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_PIXCLK__GPIO_1_11  IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_I2C1_CLK__I2C1_CLK     IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_I2C1_CLK__GPIO_1_12    IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_I2C1_DAT__I2C1_DAT     IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_I2C1_DAT__GPIO_1_13    IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_MOSI__GPIO_1_14  IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_MISO__GPIO_1_15  IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSPI1_SS0__CSPI1_SS0   IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_SS0__GPIO_1_16   IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSPI1_SS1__CSPI1_SS1   IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_SS1__GPIO_1_17   IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_SCLK__GPIO_1_18  IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSPI1_RDY__CSPI1_RDY   IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_CSPI1_RDY__GPIO_2_22   IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN)
+#define MX25_PAD_UART1_RXD__GPIO_4_22   IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART1_TXD__GPIO_4_23   IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
+#define MX25_PAD_UART1_RTS__CSI_D0      IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL)
+#define MX25_PAD_UART1_RTS__GPIO_4_24   IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
+#define MX25_PAD_UART1_CTS__CSI_D1      IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL)
+#define MX25_PAD_UART1_CTS__GPIO_4_25   IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART2_RXD__UART2_RXD   IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_RXD__GPIO_4_26   IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_TXD__GPIO_4_27   IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART2_RTS__UART2_RTS   IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_RTS__FEC_COL     IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTL)
+#define MX25_PAD_UART2_RTS__GPIO_4_28   IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART2_CTS__FEC_RX_ER   IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTL)
+#define MX25_PAD_UART2_CTS__UART2_CTS   IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_CTS__GPIO_4_29   IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_SD1_CMD__SD1_CMD       IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_CMD__FEC_RDATA2    IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_CMD__GPIO_2_23     IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_SD1_CLK__SD1_CLK       IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_CLK__FEC_RDATA3    IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_CLK__GPIO_2_24     IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_SD1_DATA0__SD1_DATA0   IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA0__GPIO_2_25   IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_SD1_DATA1__SD1_DATA1   IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA1__AUD7_RXD    IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA1__GPIO_2_26   IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_SD1_DATA2__SD1_DATA2   IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA2__FEC_RX_CLK  IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_DATA2__GPIO_2_27   IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_SD1_DATA3__SD1_DATA3   IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA3__FEC_CRS     IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_DATA3__GPIO_2_28   IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_ROW0__KPP_ROW0     IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW0__GPIO_2_29    IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_ROW1__KPP_ROW1     IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW1__GPIO_2_30    IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_ROW2__KPP_ROW2     IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW2__CSI_D0       IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
+#define MX25_PAD_KPP_ROW2__GPIO_2_31    IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_ROW3__KPP_ROW3     IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW3__CSI_LD1      IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
+#define MX25_PAD_KPP_ROW3__GPIO_3_0     IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_COL0__KPP_COL0     IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL0__GPIO_3_1     IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_COL1__KPP_COL1     IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL1__GPIO_3_2     IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_COL2__KPP_COL2     IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL2__GPIO_3_3     IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_COL3__KPP_COL3     IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL3__GPIO_3_4     IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_MDC__FEC_MDC       IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_MDC__AUD4_TXD      IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL)
+#define MX25_PAD_FEC_MDC__GPIO_3_5      IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_MDIO__FEC_MDIO     IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP)
+#define MX25_PAD_FEC_MDIO__AUD4_RXD     IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL)
+#define MX25_PAD_FEC_MDIO__GPIO_3_6     IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_TDATA0__GPIO_3_7   IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_TDATA1__AUD4_TXFS  IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL)
+#define MX25_PAD_FEC_TDATA1__GPIO_3_8   IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_TX_EN__FEC_TX_EN   IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_TX_EN__GPIO_3_9    IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
+#define MX25_PAD_FEC_RDATA0__GPIO_3_10  IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
+#define MX25_PAD_FEC_RDATA1__GPIO_3_11  IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_RX_DV__FEC_RX_DV   IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
+#define MX25_PAD_FEC_RX_DV__CAN2_RX     IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP)
+#define MX25_PAD_FEC_RX_DV__GPIO_3_12   IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN)
+#define MX25_PAD_FEC_TX_CLK__GPIO_3_13  IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_RTCK__RTCK             IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_RTCK__OWIRE            IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_RTCK__GPIO_3_14        IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_DE_B__DE_B             IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_DE_B__GPIO_2_20        IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_TDO__TDO               IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_GPIO_A__GPIO_A         IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_A__CAN1_TX        IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
+#define MX25_PAD_GPIO_A__USBOTG_PWR     IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE)
+
+#define MX25_PAD_GPIO_B__GPIO_B         IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_B__CAN1_RX        IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K)
+#define MX25_PAD_GPIO_B__USBOTG_OC      IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP)
+
+#define MX25_PAD_GPIO_C__GPIO_C         IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_C__CAN2_TX        IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
+
+#define MX25_PAD_GPIO_D__GPIO_D         IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_D__CAN2_RX        IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
+
+#define MX25_PAD_GPIO_E__GPIO_E         IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_E__AUD7_TXD       IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_GPIO_F__GPIO_F         IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_F__AUD7_TXC       IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_EXT_ARMCLK__GPIO_3_15  IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_VSTBY_REQ__VSTBY_REQ   IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSTBY_REQ__AUD7_TXFS   IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSTBY_REQ__GPIO_3_17   IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSTBY_ACK__VSTBY_ACK   IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSTBY_ACK__GPIO_3_18   IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_POWER_FAIL__AUD7_RXD   IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL)
+#define MX25_PAD_POWER_FAIL__GPIO_3_19  IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CLKO__CLKO             IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CLKO__GPIO_2_21        IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_BOOT_MODE0__GPIO_4_30  IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_BOOT_MODE1__GPIO_4_31  IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CTL_GRP_DVS_MISC       IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_FEC        IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_JTAG       IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_NFC        IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_CSI        IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_WEIM       IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_DDR        IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_CRM        IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_KPP        IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_SDHC1      IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_LCD        IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_UART       IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_NFC        IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_CSI        IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_CSPI1      IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DDRTYPE        IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_SDHC1      IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_LCD        IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+
+#endif // __ASSEMBLY__
+#endif // __IOMUX_MX25_H__
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 2eb182f73876..446f86763816 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -635,6 +635,19 @@ enum iomux_pins {
 #define MX31_PIN_USBOTG_DIR__USBOTG_DIR        IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBOTG_NXT__USBOTG_NXT        IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBOTG_STP__USBOTG_STP        IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM        IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_MISO__USBH1_RXDP        IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SS0__USBH1_TXDM         IOMUX_MODE(MX31_PIN_CSPI1_SS0,  IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SS1__USBH1_TXDP         IOMUX_MODE(MX31_PIN_CSPI1_SS1,  IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SS2__USBH1_RCV          IOMUX_MODE(MX31_PIN_CSPI1_SS2,  IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SCLK__USBH1_OEB         IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS       IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_USBH2_DATA0__USBH2_DATA0      IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_DATA1__USBH2_DATA1      IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_CLK__USBH2_CLK          IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_DIR__USBH2_DIR          IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_NXT__USBH2_NXT          IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_STP__USBH2_STP          IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USB_OC__GPIO1_30       IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_I2C_DAT__I2C1_SDA      IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_I2C_CLK__I2C1_SCL      IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
@@ -669,6 +682,18 @@ enum iomux_pins {
 #define MX31_PIN_GPIO3_0__GPIO3_0       IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_GPIO3_1__GPIO3_1       IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_TXD2__GPIO1_28         IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_GPIO1_0__GPIO1_0       IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SVEN0__GPIO2_0         IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_STX0__GPIO2_1          IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SRX0__GPIO2_2          IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SIMPD0__GPIO2_3        IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_DTR_DCE1__GPIO2_8      IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_DSR_DCE1__GPIO2_9      IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_RI_DCE1__GPIO2_10      IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_DCD_DCE1__GPIO2_11     IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_STXD5__GPIO1_21       IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SRXD5__GPIO1_22       IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
+
 
 /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
  * cspi1_ss1*/
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
new file mode 100644
index 000000000000..9f13061192c8
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Dmitriy Taychenachev <dimichxp@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __MACH_IOMUX_MXC91231_H__
+#define __MACH_IOMUX_MXC91231_H__
+
+/*
+ * various IOMUX output functions
+ */
+
+#define IOMUX_OCONFIG_GPIO (0 << 4)     /* used as GPIO */
+#define IOMUX_OCONFIG_FUNC (1 << 4)     /* used as function */
+#define IOMUX_OCONFIG_ALT1 (2 << 4)     /* used as alternate function 1 */
+#define IOMUX_OCONFIG_ALT2 (3 << 4)     /* used as alternate function 2 */
+#define IOMUX_OCONFIG_ALT3 (4 << 4)     /* used as alternate function 3 */
+#define IOMUX_OCONFIG_ALT4 (5 << 4)     /* used as alternate function 4 */
+#define IOMUX_OCONFIG_ALT5 (6 << 4)     /* used as alternate function 5 */
+#define IOMUX_OCONFIG_ALT6 (7 << 4)     /* used as alternate function 6 */
+#define IOMUX_ICONFIG_NONE  0           /* not configured for input */
+#define IOMUX_ICONFIG_GPIO  1           /* used as GPIO */
+#define IOMUX_ICONFIG_FUNC  2           /* used as function */
+#define IOMUX_ICONFIG_ALT1  4           /* used as alternate function 1 */
+#define IOMUX_ICONFIG_ALT2  8           /* used as alternate function 2 */
+
+#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
+#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
+#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
+#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
+
+/*
+ * setups a single pin:
+ *      - reserves the pin so that it is not claimed by another driver
+ *      - setups the iomux according to the configuration
+ *      - if the pin is configured as a GPIO, we claim it throug kernel gpiolib
+ */
+int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label);
+/*
+ * setups mutliple pins
+ * convenient way to call the above function with tables
+ */
+int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+                const char *label);
+
+/*
+ * releases a single pin:
+ *      - make it available for a future use by another driver
+ *      - frees the GPIO if the pin was configured as GPIO
+ *      - DOES NOT reconfigure the IOMUX in its reset state
+ */
+void mxc_iomux_release_pin(const unsigned int pin_mode);
+/*
+ * releases multiple pins
+ * convenvient way to call the above function with tables
+ */
+void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count);
+
+#define MUX_SIDE_AP             (0)
+#define MUX_SIDE_SP             (1)
+
+#define MUX_SIDE_SHIFT          (26)
+#define MUX_SIDE_MASK           (0x1 << MUX_SIDE_SHIFT)
+
+#define MUX_GPIO_PORT_SHIFT     (23)
+#define MUX_GPIO_PORT_MASK      (0x7 << MUX_GPIO_PORT_SHIFT)
+
+#define MUX_GPIO_PIN_SHIFT      (20)
+#define MUX_GPIO_PIN_MASK       (0x1f << MUX_GPIO_PIN_SHIFT)
+
+#define MUX_REG_SHIFT           (15)
+#define MUX_REG_MASK            (0x1f << MUX_REG_SHIFT)
+
+#define MUX_FIELD_SHIFT         (13)
+#define MUX_FIELD_MASK          (0x3 << MUX_FIELD_SHIFT)
+
+#define MUX_PADGRP_SHIFT        (8)
+#define MUX_PADGRP_MASK         (0x1f << MUX_PADGRP_SHIFT)
+
+#define MUX_PIN_MASK            (0xffffff << 8)
+
+#define GPIO_PORT_MAX           (3)
+
+#define IOMUX_PIN(side, gport, gpin, ctlreg, ctlfield, padgrp) \
+        (((side) << MUX_SIDE_SHIFT) |             \
+         (gport << MUX_GPIO_PORT_SHIFT) |               \
+         ((gpin) << MUX_GPIO_PIN_SHIFT) |               \
+         ((ctlreg) << MUX_REG_SHIFT) |          \
+         ((ctlfield) << MUX_FIELD_SHIFT) |              \
+         ((padgrp) << MUX_PADGRP_SHIFT))
+
+#define MUX_MODE_OUT_SHIFT      (4)
+#define MUX_MODE_IN_SHIFT       (0)
+#define MUX_MODE_SHIFT          (0)
+#define MUX_MODE_MASK           (0xff << MUX_MODE_SHIFT)
+
+#define IOMUX_MODE(pin, mode) \
+        (pin | (mode << MUX_MODE_SHIFT))
+
+enum iomux_pins {
+        /* AP Side pins */
+        MXC91231_PIN_AP_CLE             = IOMUX_PIN(0, 0,  0,  0, 0, 24),
+        MXC91231_PIN_AP_ALE             = IOMUX_PIN(0, 0,  1,  0, 1, 24),
+        MXC91231_PIN_AP_CE_B            = IOMUX_PIN(0, 0,  2,  0, 2, 24),
+        MXC91231_PIN_AP_RE_B            = IOMUX_PIN(0, 0,  3,  0, 3, 24),
+        MXC91231_PIN_AP_WE_B            = IOMUX_PIN(0, 0,  4,  1, 0, 24),
+        MXC91231_PIN_AP_WP_B            = IOMUX_PIN(0, 0,  5,  1, 1, 24),
+        MXC91231_PIN_AP_BSY_B           = IOMUX_PIN(0, 0,  6,  1, 2, 24),
+        MXC91231_PIN_AP_U1_TXD          = IOMUX_PIN(0, 0,  7,  1, 3, 28),
+        MXC91231_PIN_AP_U1_RXD          = IOMUX_PIN(0, 0,  8,  2, 0, 28),
+        MXC91231_PIN_AP_U1_RTS_B        = IOMUX_PIN(0, 0,  9,  2, 1, 28),
+        MXC91231_PIN_AP_U1_CTS_B        = IOMUX_PIN(0, 0, 10,  2, 2, 28),
+        MXC91231_PIN_AP_AD1_TXD         = IOMUX_PIN(0, 0, 11,  2, 3,  9),
+        MXC91231_PIN_AP_AD1_RXD         = IOMUX_PIN(0, 0, 12,  3, 0,  9),
+        MXC91231_PIN_AP_AD1_TXC         = IOMUX_PIN(0, 0, 13,  3, 1,  9),
+        MXC91231_PIN_AP_AD1_TXFS        = IOMUX_PIN(0, 0, 14,  3, 2,  9),
+        MXC91231_PIN_AP_AD2_TXD         = IOMUX_PIN(0, 0, 15,  3, 3,  9),
+        MXC91231_PIN_AP_AD2_RXD         = IOMUX_PIN(0, 0, 16,  4, 0,  9),
+        MXC91231_PIN_AP_AD2_TXC         = IOMUX_PIN(0, 0, 17,  4, 1,  9),
+        MXC91231_PIN_AP_AD2_TXFS        = IOMUX_PIN(0, 0, 18,  4, 2,  9),
+        MXC91231_PIN_AP_OWDAT           = IOMUX_PIN(0, 0, 19,  4, 3, 28),
+        MXC91231_PIN_AP_IPU_LD17        = IOMUX_PIN(0, 0, 20,  5, 0, 28),
+        MXC91231_PIN_AP_IPU_D3_VSYNC    = IOMUX_PIN(0, 0, 21,  5, 1, 28),
+        MXC91231_PIN_AP_IPU_D3_HSYNC    = IOMUX_PIN(0, 0, 22,  5, 2, 28),
+        MXC91231_PIN_AP_IPU_D3_CLK      = IOMUX_PIN(0, 0, 23,  5, 3, 28),
+        MXC91231_PIN_AP_IPU_D3_DRDY     = IOMUX_PIN(0, 0, 24,  6, 0, 28),
+        MXC91231_PIN_AP_IPU_D3_CONTR    = IOMUX_PIN(0, 0, 25,  6, 1, 28),
+        MXC91231_PIN_AP_IPU_D0_CS       = IOMUX_PIN(0, 0, 26,  6, 2, 28),
+        MXC91231_PIN_AP_IPU_LD16        = IOMUX_PIN(0, 0, 27,  6, 3, 28),
+        MXC91231_PIN_AP_IPU_D2_CS       = IOMUX_PIN(0, 0, 28,  7, 0, 28),
+        MXC91231_PIN_AP_IPU_PAR_RS      = IOMUX_PIN(0, 0, 29,  7, 1, 28),
+        MXC91231_PIN_AP_IPU_D3_PS       = IOMUX_PIN(0, 0, 30,  7, 2, 28),
+        MXC91231_PIN_AP_IPU_D3_CLS      = IOMUX_PIN(0, 0, 31,  7, 3, 28),
+        MXC91231_PIN_AP_IPU_RD          = IOMUX_PIN(0, 1,  0,  8, 0, 28),
+        MXC91231_PIN_AP_IPU_WR          = IOMUX_PIN(0, 1,  1,  8, 1, 28),
+        MXC91231_PIN_AP_IPU_LD0         = IOMUX_PIN(0, 7,  0,  8, 2, 28),
+        MXC91231_PIN_AP_IPU_LD1         = IOMUX_PIN(0, 7,  0,  8, 3, 28),
+        MXC91231_PIN_AP_IPU_LD2         = IOMUX_PIN(0, 7,  0,  9, 0, 28),
+        MXC91231_PIN_AP_IPU_LD3         = IOMUX_PIN(0, 1,  2,  9, 1, 28),
+        MXC91231_PIN_AP_IPU_LD4         = IOMUX_PIN(0, 1,  3,  9, 2, 28),
+        MXC91231_PIN_AP_IPU_LD5         = IOMUX_PIN(0, 1,  4,  9, 3, 28),
+        MXC91231_PIN_AP_IPU_LD6         = IOMUX_PIN(0, 1,  5, 10, 0, 28),
+        MXC91231_PIN_AP_IPU_LD7         = IOMUX_PIN(0, 1,  6, 10, 1, 28),
+        MXC91231_PIN_AP_IPU_LD8         = IOMUX_PIN(0, 1,  7, 10, 2, 28),
+        MXC91231_PIN_AP_IPU_LD9         = IOMUX_PIN(0, 1,  8, 10, 3, 28),
+        MXC91231_PIN_AP_IPU_LD10        = IOMUX_PIN(0, 1,  9, 11, 0, 28),
+        MXC91231_PIN_AP_IPU_LD11        = IOMUX_PIN(0, 1, 10, 11, 1, 28),
+        MXC91231_PIN_AP_IPU_LD12        = IOMUX_PIN(0, 1, 11, 11, 2, 28),
+        MXC91231_PIN_AP_IPU_LD13        = IOMUX_PIN(0, 1, 12, 11, 3, 28),
+        MXC91231_PIN_AP_IPU_LD14        = IOMUX_PIN(0, 1, 13, 12, 0, 28),
+        MXC91231_PIN_AP_IPU_LD15        = IOMUX_PIN(0, 1, 14, 12, 1, 28),
+        MXC91231_PIN_AP_KPROW4          = IOMUX_PIN(0, 7,  0, 12, 2, 10),
+        MXC91231_PIN_AP_KPROW5          = IOMUX_PIN(0, 1, 16, 12, 3, 10),
+        MXC91231_PIN_AP_GPIO_AP_B17     = IOMUX_PIN(0, 1, 17, 13, 0, 10),
+        MXC91231_PIN_AP_GPIO_AP_B18     = IOMUX_PIN(0, 1, 18, 13, 1, 10),
+        MXC91231_PIN_AP_KPCOL3          = IOMUX_PIN(0, 1, 19, 13, 2, 11),
+        MXC91231_PIN_AP_KPCOL4          = IOMUX_PIN(0, 1, 20, 13, 3, 11),
+        MXC91231_PIN_AP_KPCOL5          = IOMUX_PIN(0, 1, 21, 14, 0, 11),
+        MXC91231_PIN_AP_GPIO_AP_B22     = IOMUX_PIN(0, 1, 22, 14, 1, 11),
+        MXC91231_PIN_AP_GPIO_AP_B23     = IOMUX_PIN(0, 1, 23, 14, 2, 11),
+        MXC91231_PIN_AP_CSI_D0          = IOMUX_PIN(0, 1, 24, 14, 3, 21),
+        MXC91231_PIN_AP_CSI_D1          = IOMUX_PIN(0, 1, 25, 15, 0, 21),
+        MXC91231_PIN_AP_CSI_D2          = IOMUX_PIN(0, 1, 26, 15, 1, 21),
+        MXC91231_PIN_AP_CSI_D3          = IOMUX_PIN(0, 1, 27, 15, 2, 21),
+        MXC91231_PIN_AP_CSI_D4          = IOMUX_PIN(0, 1, 28, 15, 3, 21),
+        MXC91231_PIN_AP_CSI_D5          = IOMUX_PIN(0, 1, 29, 16, 0, 21),
+        MXC91231_PIN_AP_CSI_D6          = IOMUX_PIN(0, 1, 30, 16, 1, 21),
+        MXC91231_PIN_AP_CSI_D7          = IOMUX_PIN(0, 1, 31, 16, 2, 21),
+        MXC91231_PIN_AP_CSI_D8          = IOMUX_PIN(0, 2,  0, 16, 3, 21),
+        MXC91231_PIN_AP_CSI_D9          = IOMUX_PIN(0, 2,  1, 17, 0, 21),
+        MXC91231_PIN_AP_CSI_MCLK        = IOMUX_PIN(0, 2,  2, 17, 1, 21),
+        MXC91231_PIN_AP_CSI_VSYNC       = IOMUX_PIN(0, 2,  3, 17, 2, 21),
+        MXC91231_PIN_AP_CSI_HSYNC       = IOMUX_PIN(0, 2,  4, 17, 3, 21),
+        MXC91231_PIN_AP_CSI_PIXCLK      = IOMUX_PIN(0, 2,  5, 18, 0, 21),
+        MXC91231_PIN_AP_I2CLK           = IOMUX_PIN(0, 2,  6, 18, 1, 12),
+        MXC91231_PIN_AP_I2DAT           = IOMUX_PIN(0, 2,  7, 18, 2, 12),
+        MXC91231_PIN_AP_GPIO_AP_C8      = IOMUX_PIN(0, 2,  8, 18, 3,  9),
+        MXC91231_PIN_AP_GPIO_AP_C9      = IOMUX_PIN(0, 2,  9, 19, 0,  9),
+        MXC91231_PIN_AP_GPIO_AP_C10     = IOMUX_PIN(0, 2, 10, 19, 1,  9),
+        MXC91231_PIN_AP_GPIO_AP_C11     = IOMUX_PIN(0, 2, 11, 19, 2,  9),
+        MXC91231_PIN_AP_GPIO_AP_C12     = IOMUX_PIN(0, 2, 12, 19, 3,  9),
+        MXC91231_PIN_AP_GPIO_AP_C13     = IOMUX_PIN(0, 2, 13, 20, 0, 28),
+        MXC91231_PIN_AP_GPIO_AP_C14     = IOMUX_PIN(0, 2, 14, 20, 1, 28),
+        MXC91231_PIN_AP_GPIO_AP_C15     = IOMUX_PIN(0, 2, 15, 20, 2,  9),
+        MXC91231_PIN_AP_GPIO_AP_C16     = IOMUX_PIN(0, 2, 16, 20, 3,  9),
+        MXC91231_PIN_AP_GPIO_AP_C17     = IOMUX_PIN(0, 2, 17, 21, 0,  9),
+        MXC91231_PIN_AP_ED_INT0         = IOMUX_PIN(0, 2, 18, 21, 1, 22),
+        MXC91231_PIN_AP_ED_INT1         = IOMUX_PIN(0, 2, 19, 21, 2, 22),
+        MXC91231_PIN_AP_ED_INT2         = IOMUX_PIN(0, 2, 20, 21, 3, 22),
+        MXC91231_PIN_AP_ED_INT3         = IOMUX_PIN(0, 2, 21, 22, 0, 22),
+        MXC91231_PIN_AP_ED_INT4         = IOMUX_PIN(0, 2, 22, 22, 1, 23),
+        MXC91231_PIN_AP_ED_INT5         = IOMUX_PIN(0, 2, 23, 22, 2, 23),
+        MXC91231_PIN_AP_ED_INT6         = IOMUX_PIN(0, 2, 24, 22, 3, 23),
+        MXC91231_PIN_AP_ED_INT7         = IOMUX_PIN(0, 2, 25, 23, 0, 23),
+        MXC91231_PIN_AP_U2_DSR_B        = IOMUX_PIN(0, 2, 26, 23, 1, 28),
+        MXC91231_PIN_AP_U2_RI_B         = IOMUX_PIN(0, 2, 27, 23, 2, 28),
+        MXC91231_PIN_AP_U2_CTS_B        = IOMUX_PIN(0, 2, 28, 23, 3, 28),
+        MXC91231_PIN_AP_U2_DTR_B        = IOMUX_PIN(0, 2, 29, 24, 0, 28),
+        MXC91231_PIN_AP_KPROW0          = IOMUX_PIN(0, 7,  0, 24, 1, 10),
+        MXC91231_PIN_AP_KPROW1          = IOMUX_PIN(0, 1, 15, 24, 2, 10),
+        MXC91231_PIN_AP_KPROW2          = IOMUX_PIN(0, 7,  0, 24, 3, 10),
+        MXC91231_PIN_AP_KPROW3          = IOMUX_PIN(0, 7,  0, 25, 0, 10),
+        MXC91231_PIN_AP_KPCOL0          = IOMUX_PIN(0, 7,  0, 25, 1, 11),
+        MXC91231_PIN_AP_KPCOL1          = IOMUX_PIN(0, 7,  0, 25, 2, 11),
+        MXC91231_PIN_AP_KPCOL2          = IOMUX_PIN(0, 7,  0, 25, 3, 11),
+
+        /* Shared pins */
+        MXC91231_PIN_SP_U3_TXD          = IOMUX_PIN(1, 3,  0,  0, 0, 28),
+        MXC91231_PIN_SP_U3_RXD          = IOMUX_PIN(1, 3,  1,  0, 1, 28),
+        MXC91231_PIN_SP_U3_RTS_B        = IOMUX_PIN(1, 3,  2,  0, 2, 28),
+        MXC91231_PIN_SP_U3_CTS_B        = IOMUX_PIN(1, 3,  3,  0, 3, 28),
+        MXC91231_PIN_SP_USB_TXOE_B      = IOMUX_PIN(1, 3,  4,  1, 0, 28),
+        MXC91231_PIN_SP_USB_DAT_VP      = IOMUX_PIN(1, 3,  5,  1, 1, 28),
+        MXC91231_PIN_SP_USB_SE0_VM      = IOMUX_PIN(1, 3,  6,  1, 2, 28),
+        MXC91231_PIN_SP_USB_RXD         = IOMUX_PIN(1, 3,  7,  1, 3, 28),
+        MXC91231_PIN_SP_UH2_TXOE_B      = IOMUX_PIN(1, 3,  8,  2, 0, 28),
+        MXC91231_PIN_SP_UH2_SPEED       = IOMUX_PIN(1, 3,  9,  2, 1, 28),
+        MXC91231_PIN_SP_UH2_SUSPEN      = IOMUX_PIN(1, 3, 10,  2, 2, 28),
+        MXC91231_PIN_SP_UH2_TXDP        = IOMUX_PIN(1, 3, 11,  2, 3, 28),
+        MXC91231_PIN_SP_UH2_RXDP        = IOMUX_PIN(1, 3, 12,  3, 0, 28),
+        MXC91231_PIN_SP_UH2_RXDM        = IOMUX_PIN(1, 3, 13,  3, 1, 28),
+        MXC91231_PIN_SP_UH2_OVR         = IOMUX_PIN(1, 3, 14,  3, 2, 28),
+        MXC91231_PIN_SP_UH2_PWR         = IOMUX_PIN(1, 3, 15,  3, 3, 28),
+        MXC91231_PIN_SP_SD1_DAT0        = IOMUX_PIN(1, 3, 16,  4, 0, 25),
+        MXC91231_PIN_SP_SD1_DAT1        = IOMUX_PIN(1, 3, 17,  4, 1, 25),
+        MXC91231_PIN_SP_SD1_DAT2        = IOMUX_PIN(1, 3, 18,  4, 2, 25),
+        MXC91231_PIN_SP_SD1_DAT3        = IOMUX_PIN(1, 3, 19,  4, 3, 25),
+        MXC91231_PIN_SP_SD1_CMD         = IOMUX_PIN(1, 3, 20,  5, 0, 25),
+        MXC91231_PIN_SP_SD1_CLK         = IOMUX_PIN(1, 3, 21,  5, 1, 25),
+        MXC91231_PIN_SP_SD2_DAT0        = IOMUX_PIN(1, 3, 22,  5, 2, 26),
+        MXC91231_PIN_SP_SD2_DAT1        = IOMUX_PIN(1, 3, 23,  5, 3, 26),
+        MXC91231_PIN_SP_SD2_DAT2        = IOMUX_PIN(1, 3, 24,  6, 0, 26),
+        MXC91231_PIN_SP_SD2_DAT3        = IOMUX_PIN(1, 3, 25,  6, 1, 26),
+        MXC91231_PIN_SP_GPIO_SP_A26     = IOMUX_PIN(1, 3, 26,  6, 2, 28),
+        MXC91231_PIN_SP_SPI1_CLK        = IOMUX_PIN(1, 3, 27,  6, 3, 13),
+        MXC91231_PIN_SP_SPI1_MOSI       = IOMUX_PIN(1, 3, 28,  7, 0, 13),
+        MXC91231_PIN_SP_SPI1_MISO       = IOMUX_PIN(1, 3, 29,  7, 1, 13),
+        MXC91231_PIN_SP_SPI1_SS0        = IOMUX_PIN(1, 3, 30,  7, 2, 13),
+        MXC91231_PIN_SP_SPI1_SS1        = IOMUX_PIN(1, 3, 31,  7, 3, 13),
+        MXC91231_PIN_SP_SD2_CMD         = IOMUX_PIN(1, 7,  0,  8, 0, 26),
+        MXC91231_PIN_SP_SD2_CLK         = IOMUX_PIN(1, 7,  0,  8, 1, 26),
+        MXC91231_PIN_SP_SIM1_RST_B      = IOMUX_PIN(1, 2, 30,  8, 2, 28),
+        MXC91231_PIN_SP_SIM1_SVEN       = IOMUX_PIN(1, 7,  0,  8, 3, 28),
+        MXC91231_PIN_SP_SIM1_CLK        = IOMUX_PIN(1, 7,  0,  9, 0, 28),
+        MXC91231_PIN_SP_SIM1_TRXD       = IOMUX_PIN(1, 7,  0,  9, 1, 28),
+        MXC91231_PIN_SP_SIM1_PD         = IOMUX_PIN(1, 2, 31,  9, 2, 28),
+        MXC91231_PIN_SP_UH2_TXDM        = IOMUX_PIN(1, 7,  0,  9, 3, 28),
+        MXC91231_PIN_SP_UH2_RXD         = IOMUX_PIN(1, 7,  0, 10, 0, 28),
+};
+
+#define PIN_AP_MAX      (104)
+#define PIN_SP_MAX      (41)
+
+#define PIN_MAX         (PIN_AP_MAX + PIN_SP_MAX)
+
+/*
+ * Convenience values for use with mxc_iomux_mode()
+ *
+ * Format here is MXC91231_PIN_(pin name)__(function)
+ */
+
+#define MXC91231_PIN_SP_USB_DAT_VP__USB_DAT_VP \
+        IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_FUNC)
+#define MXC91231_PIN_SP_USB_SE0_VM__USB_SE0_VM \
+        IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_FUNC)
+#define MXC91231_PIN_SP_USB_DAT_VP__RXD2 \
+        IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_ALT1)
+#define MXC91231_PIN_SP_USB_SE0_VM__TXD2 \
+        IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_ALT1)
+
+
+#endif /* __MACH_IOMUX_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 7cd84547658f..a0fa40265468 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -68,28 +68,24 @@ struct pad_desc {
 /*
  * Use to set PAD control
  */
-#define PAD_CTL_DRIVE_VOLTAGE_3_3_V     0
-#define PAD_CTL_DRIVE_VOLTAGE_1_8_V     1
 
-#define PAD_CTL_NO_HYSTERESIS           0
-#define PAD_CTL_HYSTERESIS              1
+#define PAD_CTL_DVS                     (1 << 13)
+#define PAD_CTL_HYS                     (1 << 8)
 
-#define PAD_CTL_PULL_DISABLED           0x0
-#define PAD_CTL_PULL_KEEPER             0xa
-#define PAD_CTL_PULL_DOWN_100K          0xc
-#define PAD_CTL_PULL_UP_47K             0xd
-#define PAD_CTL_PULL_UP_100K            0xe
-#define PAD_CTL_PULL_UP_22K             0xf
+#define PAD_CTL_PKE                     (1 << 7)
+#define PAD_CTL_PUE                     (1 << 6)
+#define PAD_CTL_PUS_100K_DOWN           (0 << 4)
+#define PAD_CTL_PUS_47K_UP              (1 << 4)
+#define PAD_CTL_PUS_100K_UP             (2 << 4)
+#define PAD_CTL_PUS_22K_UP              (3 << 4)
 
-#define PAD_CTL_OUTPUT_CMOS             0
-#define PAD_CTL_OUTPUT_OPEN_DRAIN       1
+#define PAD_CTL_ODE                     (1 << 3)
 
-#define PAD_CTL_DRIVE_STRENGTH_NORM     0
-#define PAD_CTL_DRIVE_STRENGTH_HIGH     1
-#define PAD_CTL_DRIVE_STRENGTH_MAX      2
+#define PAD_CTL_DSE_STANDARD            (0 << 1)
+#define PAD_CTL_DSE_HIGH                (1 << 1)
+#define PAD_CTL_DSE_MAX                 (2 << 1)
 
-#define PAD_CTL_SLEW_RATE_SLOW          0
-#define PAD_CTL_SLEW_RATE_FAST          1
+#define PAD_CTL_SRE_FAST                (1 << 0)
 
 /*
  * setups a single pad:
@@ -117,5 +113,10 @@ void mxc_iomux_v3_release_pad(struct pad_desc *pad);
  */
 void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
 
+/*
+ * Initialise the iomux controller
+ */
+void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
+
 #endif /* __MACH_IOMUX_V3_H__*/
 
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h
index 171f8adc1109..6d49f8ae3259 100644
--- a/arch/arm/plat-mxc/include/mach/iomux.h
+++ b/arch/arm/plat-mxc/include/mach/iomux.h
@@ -49,6 +49,9 @@
 #ifdef CONFIG_ARCH_MX2
 # define GPIO_PORT_MAX  5
 #endif
+#ifdef CONFIG_ARCH_MX25
+# define GPIO_PORT_MAX  3
+#endif
 
 #ifndef GPIO_PORT_MAX
 # error "GPIO config port count unknown!"
@@ -107,6 +110,9 @@
 #include <mach/iomux-mx27.h>
 #endif
 #endif
+#ifdef CONFIG_ARCH_MX25
+#include <mach/iomux-mx25.h>
+#endif
 
 
 /* decode irq number to use with IMR(x), ISR(x) and friends */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 518a36504b88..ead9d592168d 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -24,6 +24,10 @@
 #define MXC_GPIO_IRQS           (32 * 6)
 #elif defined CONFIG_ARCH_MX3
 #define MXC_GPIO_IRQS           (32 * 3)
+#elif defined CONFIG_ARCH_MX25
+#define MXC_GPIO_IRQS           (32 * 4)
+#elif defined CONFIG_ARCH_MXC91231
+#define MXC_GPIO_IRQS           (32 * 4)
 #endif
 
 /*
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 6065e00176ed..d3afafdcc0e5 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -22,6 +22,10 @@
 #endif
 #elif defined CONFIG_ARCH_MX3
 #define PHYS_OFFSET             UL(0x80000000)
+#elif defined CONFIG_ARCH_MX25
+#define PHYS_OFFSET             UL(0x80000000)
+#elif defined CONFIG_ARCH_MXC91231
+#define PHYS_OFFSET             UL(0x90000000)
 #endif
 
 #if defined(CONFIG_MX1_VIDEO)
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 1000bf330bcd..1b2890a5c452 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -12,10 +12,6 @@
 #ifndef __ASM_ARCH_MXC_MX1_H__
 #define __ASM_ARCH_MXC_MX1_H__
 
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
-
 #include <mach/vmalloc.h>
 
 /*
@@ -138,20 +134,6 @@
 #define GPIO_INT_PORTD          62
 #define WDT_INT                 63
 
-/* gpio and gpio based interrupt handling */
-#define GPIO_DR                 0x1C
-#define GPIO_GDIR               0x00
-#define GPIO_PSR                0x24
-#define GPIO_ICR1               0x28
-#define GPIO_ICR2               0x2C
-#define GPIO_IMR                0x30
-#define GPIO_ISR                0x34
-#define GPIO_INT_LOW_LEV        0x3
-#define GPIO_INT_HIGH_LEV       0x2
-#define GPIO_INT_RISE_EDGE      0x0
-#define GPIO_INT_FALL_EDGE      0x1
-#define GPIO_INT_NONE           0x4
-
 /* DMA */
 #define DMA_REQ_UART3_T         2
 #define DMA_REQ_UART3_R         3
@@ -179,8 +161,4 @@
 #define DMA_REQ_UART1_T         30
 #define DMA_REQ_UART1_R         31
 
-/* mandatory for CONFIG_DEBUG_LL */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /*  __ASM_ARCH_MXC_MX1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 8b070a041a99..21112c695ec5 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -25,11 +25,6 @@
 #ifndef __ASM_ARCH_MXC_MX21_H__
 #define __ASM_ARCH_MXC_MX21_H__
 
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
-
-
 /* Memory regions and CS */
 #define SDRAM_BASE_ADDR         0xC0000000
 #define CSD1_BASE_ADDR          0xC4000000
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
new file mode 100644
index 000000000000..ec64bd9a8ab1
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -0,0 +1,44 @@
+#ifndef __MACH_MX25_H__
+#define __MACH_MX25_H__
+
+#define MX25_AIPS1_BASE_ADDR            0x43F00000
+#define MX25_AIPS1_BASE_ADDR_VIRT       0xFC000000
+#define MX25_AIPS1_SIZE                 SZ_1M
+#define MX25_AIPS2_BASE_ADDR            0x53F00000
+#define MX25_AIPS2_BASE_ADDR_VIRT       0xFC200000
+#define MX25_AIPS2_SIZE                 SZ_1M
+#define MX25_AVIC_BASE_ADDR             0x68000000
+#define MX25_AVIC_BASE_ADDR_VIRT        0xFC400000
+#define MX25_AVIC_SIZE                  SZ_1M
+
+#define MX25_IOMUXC_BASE_ADDR           (MX25_AIPS1_BASE_ADDR + 0xac000)
+
+#define MX25_CRM_BASE_ADDR              (MX25_AIPS2_BASE_ADDR + 0x80000)
+#define MX25_GPT1_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0x90000)
+#define MX25_WDOG_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xdc000)
+
+#define MX25_GPIO1_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000)
+#define MX25_GPIO2_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000)
+#define MX25_GPIO3_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
+#define MX25_GPIO4_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
+
+#define MX25_AIPS1_IO_ADDRESS(x)  \
+        (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
+#define MX25_AIPS2_IO_ADDRESS(x)  \
+        (((x) - MX25_AIPS2_BASE_ADDR) + MX25_AIPS2_BASE_ADDR_VIRT)
+#define MX25_AVIC_IO_ADDRESS(x)  \
+        (((x) - MX25_AVIC_BASE_ADDR) + MX25_AVIC_BASE_ADDR_VIRT)
+
+#define __in_range(addr, name)  ((addr) >= name##_BASE_ADDR && (addr) < name##_BASE_ADDR + name##_SIZE)
+
+#define MX25_IO_ADDRESS(x)                                      \
+        (void __force __iomem *)                                \
+        (__in_range(x, MX25_AIPS1) ? MX25_AIPS1_IO_ADDRESS(x) : \
+        __in_range(x, MX25_AIPS2) ? MX25_AIPS2_IO_ADDRESS(x) :  \
+        __in_range(x, MX25_AVIC) ? MX25_AVIC_IO_ADDRESS(x) :    \
+        0xDEADBEEF)
+
+#define UART1_BASE_ADDR                 0x43f90000
+#define UART2_BASE_ADDR                 0x43f94000
+
+#endif /* __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 6e93f2c0b7bb..dc3ad9aa952a 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -24,10 +24,6 @@
 #ifndef __ASM_ARCH_MXC_MX27_H__
 #define __ASM_ARCH_MXC_MX27_H__
 
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
-
 /* IRAM */
 #define IRAM_BASE_ADDR          0xFFFF4C00      /* internal ram */
 
@@ -120,7 +116,4 @@ extern int mx27_revision(void);
 
 /* Mandatory defines used globally */
 
-/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
-#define ARCH_NR_GPIOS           (192 + 16)
-
 #endif /* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index fc40d3ab8c5b..db5d921e0fe6 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -23,10 +23,6 @@
 #ifndef __ASM_ARCH_MXC_MX2x_H__
 #define __ASM_ARCH_MXC_MX2x_H__
 
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
-
 /* The following addresses are common between i.MX21 and i.MX27 */
 
 /* Register offests */
@@ -154,20 +150,6 @@
 #define MXC_INT_GPIO            8
 #define MXC_INT_CSPI3           6
 
-/* gpio and gpio based interrupt handling */
-#define GPIO_DR                 0x1C
-#define GPIO_GDIR               0x00
-#define GPIO_PSR                0x24
-#define GPIO_ICR1               0x28
-#define GPIO_ICR2               0x2C
-#define GPIO_IMR                0x30
-#define GPIO_ISR                0x34
-#define GPIO_INT_LOW_LEV        0x3
-#define GPIO_INT_HIGH_LEV       0x2
-#define GPIO_INT_RISE_EDGE      0x0
-#define GPIO_INT_FALL_EDGE      0x1
-#define GPIO_INT_NONE           0x4
-
 /* fixed DMA request numbers */
 #define DMA_REQ_CSI_RX          31
 #define DMA_REQ_CSI_STAT        30
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 0b06941b6139..14ac0dcc82f4 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -4,7 +4,7 @@
 #define MX31_IRAM_BASE_ADDR             0x1FFC0000      /* internal ram */
 #define MX31_IRAM_SIZE                  SZ_16K
 
-#define OTG_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00088000)
+#define MX31_OTG_BASE_ADDR      (AIPS1_BASE_ADDR + 0x00088000)
 #define ATA_BASE_ADDR           (AIPS1_BASE_ADDR + 0x0008C000)
 #define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B0000)
 #define UART5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B4000)
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 6465fefb42e3..ab4cfec6c8ab 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -5,6 +5,7 @@
 #define MX35_IRAM_SIZE          SZ_128K
 
 #define MXC_FEC_BASE_ADDR       0x50038000
+#define MX35_OTG_BASE_ADDR      0x53ff4000
 #define MX35_NFC_BASE_ADDR      0xBB000000
 
 /*
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index b559a4bb5769..009f4440276b 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -11,10 +11,6 @@
 #ifndef __ASM_ARCH_MXC_MX31_H__
 #define __ASM_ARCH_MXC_MX31_H__
 
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
-
 /*
  * MX31 memory map:
  *
@@ -263,25 +259,8 @@
 #define SYSTEM_REV_MIN          CHIP_REV_1_0
 #define SYSTEM_REV_NUM          3
 
-/* gpio and gpio based interrupt handling */
-#define GPIO_DR                 0x00
-#define GPIO_GDIR               0x04
-#define GPIO_PSR                0x08
-#define GPIO_ICR1               0x0C
-#define GPIO_ICR2               0x10
-#define GPIO_IMR                0x14
-#define GPIO_ISR                0x18
-#define GPIO_INT_LOW_LEV        0x0
-#define GPIO_INT_HIGH_LEV       0x1
-#define GPIO_INT_RISE_EDGE      0x2
-#define GPIO_INT_FALL_EDGE      0x3
-#define GPIO_INT_NONE           0x4
-
 /* Mandatory defines used globally */
 
-/* this CPU supports up to 96 GPIOs */
-#define ARCH_NR_GPIOS           96
-
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 
 extern unsigned int system_rev;
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 5fa2a07f4eaf..51990536b845 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -26,9 +26,11 @@
 
 #define MXC_CPU_MX1             1
 #define MXC_CPU_MX21            21
+#define MXC_CPU_MX25            25
 #define MXC_CPU_MX27            27
 #define MXC_CPU_MX31            31
 #define MXC_CPU_MX35            35
+#define MXC_CPU_MXC91231        91231
 
 #ifndef __ASSEMBLY__
 extern unsigned int __mxc_cpu_type;
@@ -58,6 +60,18 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx21()          (0)
 #endif
 
+#ifdef CONFIG_ARCH_MX25
+# ifdef mxc_cpu_type
+#  undef mxc_cpu_type
+#  define mxc_cpu_type __mxc_cpu_type
+# else
+#  define mxc_cpu_type MXC_CPU_MX25
+# endif
+# define cpu_is_mx25()          (mxc_cpu_type == MXC_CPU_MX25)
+#else
+# define cpu_is_mx25()          (0)
+#endif
+
 #ifdef CONFIG_MACH_MX27
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
@@ -94,13 +108,25 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx35()          (0)
 #endif
 
+#ifdef CONFIG_ARCH_MXC91231
+# ifdef mxc_cpu_type
+#  undef mxc_cpu_type
+#  define mxc_cpu_type __mxc_cpu_type
+# else
+#  define mxc_cpu_type MXC_CPU_MXC91231
+# endif
+# define cpu_is_mxc91231()      (mxc_cpu_type == MXC_CPU_MXC91231)
+#else
+# define cpu_is_mxc91231()      (0)
+#endif
+
 #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
 #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10)
 #define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4)
 #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8)
 #endif
 
-#define cpu_is_mx3()    (cpu_is_mx31() || cpu_is_mx35())
+#define cpu_is_mx3()    (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
 #define cpu_is_mx2()    (cpu_is_mx21() || cpu_is_mx27())
 
 #endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
new file mode 100644
index 000000000000..81484d1ef232
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -0,0 +1,315 @@
+/*
+ *  Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - Platform specific register memory map
+ *
+ *  Copyright 2005-2007 Motorola, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __MACH_MXC91231_H__
+#define __MACH_MXC91231_H__
+
+/*
+ * L2CC
+ */
+#define MXC91231_L2CC_BASE_ADDR         0x30000000
+#define MXC91231_L2CC_BASE_ADDR_VIRT    0xF9000000
+#define MXC91231_L2CC_SIZE              SZ_64K
+
+/*
+ * AIPS 1
+ */
+#define MXC91231_AIPS1_BASE_ADDR        0x43F00000
+#define MXC91231_AIPS1_BASE_ADDR_VIRT   0xFC000000
+#define MXC91231_AIPS1_SIZE             SZ_1M
+
+#define MXC91231_AIPS1_CTRL_BASE_ADDR   MXC91231_AIPS1_BASE_ADDR
+#define MXC91231_MAX_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x04000)
+#define MXC91231_EVTMON_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0x08000)
+#define MXC91231_CLKCTL_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0x0C000)
+#define MXC91231_ETB_SLOT4_BASE_ADDR    (MXC91231_AIPS1_BASE_ADDR + 0x10000)
+#define MXC91231_ETB_SLOT5_BASE_ADDR    (MXC91231_AIPS1_BASE_ADDR + 0x14000)
+#define MXC91231_ECT_CTIO_BASE_ADDR     (MXC91231_AIPS1_BASE_ADDR + 0x18000)
+#define MXC91231_I2C_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x80000)
+#define MXC91231_MU_BASE_ADDR           (MXC91231_AIPS1_BASE_ADDR + 0x88000)
+#define MXC91231_UART1_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x90000)
+#define MXC91231_UART2_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x94000)
+#define MXC91231_DSM_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x98000)
+#define MXC91231_OWIRE_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x9C000)
+#define MXC91231_SSI1_BASE_ADDR         (MXC91231_AIPS1_BASE_ADDR + 0xA0000)
+#define MXC91231_KPP_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0xA8000)
+#define MXC91231_IOMUX_AP_BASE_ADDR     (MXC91231_AIPS1_BASE_ADDR + 0xAC000)
+#define MXC91231_CTI_AP_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0xB8000)
+
+/*
+ * AIPS 2
+ */
+#define MXC91231_AIPS2_BASE_ADDR        0x53F00000
+#define MXC91231_AIPS2_BASE_ADDR_VIRT   0xFC100000
+#define MXC91231_AIPS2_SIZE             SZ_1M
+
+#define MXC91231_GEMK_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
+#define MXC91231_GPT1_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0x90000)
+#define MXC91231_EPIT1_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0x94000)
+#define MXC91231_SCC_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xAC000)
+#define MXC91231_RNGA_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xB0000)
+#define MXC91231_IPU_CTRL_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xC0000)
+#define MXC91231_AUDMUX_BASE_ADDR       (MXC91231_AIPS2_BASE_ADDR + 0xC4000)
+#define MXC91231_EDIO_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xC8000)
+#define MXC91231_GPIO1_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xCC000)
+#define MXC91231_GPIO2_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xD0000)
+#define MXC91231_SDMA_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xD4000)
+#define MXC91231_RTC_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xD8000)
+#define MXC91231_WDOG1_BASE_ADDR        (MXC91231_AIPS2_BASE_ADDR + 0xDC000)
+#define MXC91231_PWM_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xE0000)
+#define MXC91231_GPIO3_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xE4000)
+#define MXC91231_WDOG2_BASE_ADDR        (MXC91231_AIPS2_BASE_ADDR + 0xE8000)
+#define MXC91231_RTIC_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xEC000)
+#define MXC91231_LPMC_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xF0000)
+
+/*
+ * SPBA global module 0
+ */
+#define MXC91231_SPBA0_BASE_ADDR        0x50000000
+#define MXC91231_SPBA0_BASE_ADDR_VIRT   0xFC200000
+#define MXC91231_SPBA0_SIZE             SZ_1M
+
+#define MXC91231_MMC_SDHC1_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x04000)
+#define MXC91231_MMC_SDHC2_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x08000)
+#define MXC91231_UART3_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x0C000)
+#define MXC91231_CSPI2_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x10000)
+#define MXC91231_SSI2_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x14000)
+#define MXC91231_SIM_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x18000)
+#define MXC91231_IIM_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x1C000)
+#define MXC91231_CTI_SDMA_BASE_ADDR     (MXC91231_SPBA0_BASE_ADDR + 0x20000)
+#define MXC91231_USBOTG_CTRL_BASE_ADDR  (MXC91231_SPBA0_BASE_ADDR + 0x24000)
+#define MXC91231_USBOTG_DATA_BASE_ADDR  (MXC91231_SPBA0_BASE_ADDR + 0x28000)
+#define MXC91231_CSPI1_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x30000)
+#define MXC91231_SPBA_CTRL_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x3C000)
+#define MXC91231_IOMUX_COM_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x40000)
+#define MXC91231_CRM_COM_BASE_ADDR      (MXC91231_SPBA0_BASE_ADDR + 0x44000)
+#define MXC91231_CRM_AP_BASE_ADDR       (MXC91231_SPBA0_BASE_ADDR + 0x48000)
+#define MXC91231_PLL0_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x4C000)
+#define MXC91231_PLL1_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x50000)
+#define MXC91231_PLL2_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x54000)
+#define MXC91231_GPIO4_SH_BASE_ADDR     (MXC91231_SPBA0_BASE_ADDR + 0x58000)
+#define MXC91231_HAC_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
+#define MXC91231_SAHARA_BASE_ADDR       (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
+#define MXC91231_PLL3_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x60000)
+
+/*
+ * SPBA global module 1
+ */
+#define MXC91231_SPBA1_BASE_ADDR        0x52000000
+#define MXC91231_SPBA1_BASE_ADDR_VIRT   0xFC300000
+#define MXC91231_SPBA1_SIZE             SZ_1M
+
+#define MXC91231_MQSPI_BASE_ADDR        (MXC91231_SPBA1_BASE_ADDR + 0x34000)
+#define MXC91231_EL1T_BASE_ADDR         (MXC91231_SPBA1_BASE_ADDR + 0x38000)
+
+/*!
+ * Defines for SPBA modules
+ */
+#define MXC91231_SPBA_SDHC1             0x04
+#define MXC91231_SPBA_SDHC2             0x08
+#define MXC91231_SPBA_UART3             0x0C
+#define MXC91231_SPBA_CSPI2             0x10
+#define MXC91231_SPBA_SSI2              0x14
+#define MXC91231_SPBA_SIM               0x18
+#define MXC91231_SPBA_IIM               0x1C
+#define MXC91231_SPBA_CTI_SDMA          0x20
+#define MXC91231_SPBA_USBOTG_CTRL_REGS  0x24
+#define MXC91231_SPBA_USBOTG_DATA_REGS  0x28
+#define MXC91231_SPBA_CSPI1             0x30
+#define MXC91231_SPBA_MQSPI             0x34
+#define MXC91231_SPBA_EL1T              0x38
+#define MXC91231_SPBA_IOMUX             0x40
+#define MXC91231_SPBA_CRM_COM           0x44
+#define MXC91231_SPBA_CRM_AP            0x48
+#define MXC91231_SPBA_PLL0              0x4C
+#define MXC91231_SPBA_PLL1              0x50
+#define MXC91231_SPBA_PLL2              0x54
+#define MXC91231_SPBA_GPIO4             0x58
+#define MXC91231_SPBA_SAHARA            0x5C
+
+/*
+ * ROMP and AVIC
+ */
+#define MXC91231_ROMP_BASE_ADDR         0x60000000
+#define MXC91231_ROMP_BASE_ADDR_VIRT    0xFC400000
+#define MXC91231_ROMP_SIZE              SZ_64K
+
+#define MXC91231_AVIC_BASE_ADDR         0x68000000
+#define MXC91231_AVIC_BASE_ADDR_VIRT    0xFC410000
+#define MXC91231_AVIC_SIZE              SZ_64K
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define MXC91231_X_MEMC_BASE_ADDR       0xB8000000
+#define MXC91231_X_MEMC_BASE_ADDR_VIRT  0xFC420000
+#define MXC91231_X_MEMC_SIZE            SZ_64K
+
+#define MXC91231_NFC_BASE_ADDR          (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
+#define MXC91231_ESDCTL_BASE_ADDR       (MXC91231_X_MEMC_BASE_ADDR + 0x1000)
+#define MXC91231_WEIM_BASE_ADDR         (MXC91231_X_MEMC_BASE_ADDR + 0x2000)
+#define MXC91231_M3IF_BASE_ADDR         (MXC91231_X_MEMC_BASE_ADDR + 0x3000)
+#define MXC91231_EMI_CTL_BASE_ADDR      (MXC91231_X_MEMC_BASE_ADDR + 0x4000)
+
+/*
+ * Memory regions and CS
+ * CPLD is connected on CS4
+ * CS5 is TP1021 or it is not connected
+ * */
+#define MXC91231_FB_RAM_BASE_ADDR       0x78000000
+#define MXC91231_FB_RAM_SIZE            SZ_256K
+#define MXC91231_CSD0_BASE_ADDR         0x80000000
+#define MXC91231_CSD1_BASE_ADDR         0x90000000
+#define MXC91231_CS0_BASE_ADDR          0xA0000000
+#define MXC91231_CS1_BASE_ADDR          0xA8000000
+#define MXC91231_CS2_BASE_ADDR          0xB0000000
+#define MXC91231_CS3_BASE_ADDR          0xB2000000
+#define MXC91231_CS4_BASE_ADDR          0xB4000000
+#define MXC91231_CS5_BASE_ADDR          0xB6000000
+
+/* Is given address belongs to the specified memory region? */
+#define ADDRESS_IN_REGION(addr, start, size) \
+        (((addr) >= (start)) && ((addr) < (start)+(size)))
+
+/* Is given address belongs to the specified named `module'? */
+#define MXC91231_IS_MODULE(addr, module) \
+        ADDRESS_IN_REGION(addr, MXC91231_ ## module ## _BASE_ADDR, \
+                                MXC91231_ ## module ## _SIZE)
+/*
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+
+#define MXC91231_IO_ADDRESS(x) \
+        (void __iomem *) \
+        (MXC91231_IS_MODULE(x, L2CC) ? MXC91231_L2CC_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, AIPS1) ? MXC91231_AIPS1_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, AIPS2) ? MXC91231_AIPS2_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, SPBA0) ? MXC91231_SPBA0_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, SPBA1) ? MXC91231_SPBA1_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, ROMP) ? MXC91231_ROMP_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, AVIC) ? MXC91231_AVIC_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, X_MEMC) ? MXC91231_X_MEMC_IO_ADDRESS(x) : \
+         0xDEADBEEF)
+
+
+/*
+ * define the address mapping macros: in physical address order
+ */
+#define MXC91231_L2CC_IO_ADDRESS(x)  \
+        (((x) - MXC91231_L2CC_BASE_ADDR) + MXC91231_L2CC_BASE_ADDR_VIRT)
+
+#define MXC91231_AIPS1_IO_ADDRESS(x)  \
+        (((x) - MXC91231_AIPS1_BASE_ADDR) + MXC91231_AIPS1_BASE_ADDR_VIRT)
+
+#define MXC91231_SPBA0_IO_ADDRESS(x)  \
+        (((x) - MXC91231_SPBA0_BASE_ADDR) + MXC91231_SPBA0_BASE_ADDR_VIRT)
+
+#define MXC91231_SPBA1_IO_ADDRESS(x)  \
+        (((x) - MXC91231_SPBA1_BASE_ADDR) + MXC91231_SPBA1_BASE_ADDR_VIRT)
+
+#define MXC91231_AIPS2_IO_ADDRESS(x)  \
+        (((x) - MXC91231_AIPS2_BASE_ADDR) + MXC91231_AIPS2_BASE_ADDR_VIRT)
+
+#define MXC91231_ROMP_IO_ADDRESS(x)  \
+        (((x) - MXC91231_ROMP_BASE_ADDR) + MXC91231_ROMP_BASE_ADDR_VIRT)
+
+#define MXC91231_AVIC_IO_ADDRESS(x)  \
+        (((x) - MXC91231_AVIC_BASE_ADDR) + MXC91231_AVIC_BASE_ADDR_VIRT)
+
+#define MXC91231_X_MEMC_IO_ADDRESS(x)  \
+        (((x) - MXC91231_X_MEMC_BASE_ADDR) + MXC91231_X_MEMC_BASE_ADDR_VIRT)
+
+/*
+ * Interrupt numbers
+ */
+#define MXC91231_INT_GPIO3              0
+#define MXC91231_INT_EL1T_CI            1
+#define MXC91231_INT_EL1T_RFCI          2
+#define MXC91231_INT_EL1T_RFI           3
+#define MXC91231_INT_EL1T_MCU           4
+#define MXC91231_INT_EL1T_IPI           5
+#define MXC91231_INT_MU_GEN             6
+#define MXC91231_INT_GPIO4              7
+#define MXC91231_INT_MMC_SDHC2          8
+#define MXC91231_INT_MMC_SDHC1          9
+#define MXC91231_INT_I2C                10
+#define MXC91231_INT_SSI2               11
+#define MXC91231_INT_SSI1               12
+#define MXC91231_INT_CSPI2              13
+#define MXC91231_INT_CSPI1              14
+#define MXC91231_INT_RTIC               15
+#define MXC91231_INT_SAHARA             15
+#define MXC91231_INT_HAC                15
+#define MXC91231_INT_UART3_RX           16
+#define MXC91231_INT_UART3_TX           17
+#define MXC91231_INT_UART3_MINT         18
+#define MXC91231_INT_ECT                19
+#define MXC91231_INT_SIM_IPB            20
+#define MXC91231_INT_SIM_DATA           21
+#define MXC91231_INT_RNGA               22
+#define MXC91231_INT_DSM_AP             23
+#define MXC91231_INT_KPP                24
+#define MXC91231_INT_RTC                25
+#define MXC91231_INT_PWM                26
+#define MXC91231_INT_GEMK_AP            27
+#define MXC91231_INT_EPIT               28
+#define MXC91231_INT_GPT                29
+#define MXC91231_INT_UART2_RX           30
+#define MXC91231_INT_UART2_TX           31
+#define MXC91231_INT_UART2_MINT         32
+#define MXC91231_INT_NANDFC             33
+#define MXC91231_INT_SDMA               34
+#define MXC91231_INT_USB_WAKEUP         35
+#define MXC91231_INT_USB_SOF            36
+#define MXC91231_INT_PMU_EVTMON         37
+#define MXC91231_INT_USB_FUNC           38
+#define MXC91231_INT_USB_DMA            39
+#define MXC91231_INT_USB_CTRL           40
+#define MXC91231_INT_IPU_ERR            41
+#define MXC91231_INT_IPU_SYN            42
+#define MXC91231_INT_UART1_RX           43
+#define MXC91231_INT_UART1_TX           44
+#define MXC91231_INT_UART1_MINT         45
+#define MXC91231_INT_IIM                46
+#define MXC91231_INT_MU_RX_OR           47
+#define MXC91231_INT_MU_TX_OR           48
+#define MXC91231_INT_SCC_SCM            49
+#define MXC91231_INT_SCC_SMN            50
+#define MXC91231_INT_GPIO2              51
+#define MXC91231_INT_GPIO1              52
+#define MXC91231_INT_MQSPI1             53
+#define MXC91231_INT_MQSPI2             54
+#define MXC91231_INT_WDOG2              55
+#define MXC91231_INT_EXT_INT7           56
+#define MXC91231_INT_EXT_INT6           57
+#define MXC91231_INT_EXT_INT5           58
+#define MXC91231_INT_EXT_INT4           59
+#define MXC91231_INT_EXT_INT3           60
+#define MXC91231_INT_EXT_INT2           61
+#define MXC91231_INT_EXT_INT1           62
+#define MXC91231_INT_EXT_INT0           63
+
+#define MXC91231_MAX_INT_LINES          63
+#define MXC91231_MAX_EXT_LINES          8
+
+#endif /* __MACH_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index e56241af870e..ef00199568de 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -21,8 +21,18 @@
 #ifndef __ASM_ARCH_MXC_SYSTEM_H__
 #define __ASM_ARCH_MXC_SYSTEM_H__
 
+#include <mach/hardware.h>
+#include <mach/common.h>
+
 static inline void arch_idle(void)
 {
+#ifdef CONFIG_ARCH_MXC91231
+        if (cpu_is_mxc91231()) {
+                /* Need this to set DSM low-power mode */
+                mxc91231_prepare_idle();
+        }
+#endif
+
         cpu_do_idle();
 }
 
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 07b4a73c9d2f..527a6c24788e 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -26,6 +26,10 @@
 #define CLOCK_TICK_RATE         13300000
 #elif defined CONFIG_ARCH_MX3
 #define CLOCK_TICK_RATE         16625000
+#elif defined CONFIG_ARCH_MX25
+#define CLOCK_TICK_RATE         16000000
+#elif defined CONFIG_ARCH_MXC91231
+#define CLOCK_TICK_RATE         13000000
 #endif
 
 #endif                          /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index de6fe0365982..082a3908256b 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -26,8 +26,11 @@
 #define __MXC_BOOT_UNCOMPRESS
 
 #include <mach/hardware.h>
+#include <asm/mach-types.h>
 
-#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
+static unsigned long uart_base;
+
+#define UART(x) (*(volatile unsigned long *)(uart_base + (x)))
 
 #define USR2 0x98
 #define USR2_TXFE (1<<14)
@@ -46,19 +49,10 @@
 
 static void putc(int ch)
 {
-        static unsigned long serial_port = 0;
-
-        if (unlikely(serial_port == 0)) {
-                do {
-                        serial_port = UART1_BASE_ADDR;
-                        if (UART(UCR1) & UCR1_UARTEN)
-                                break;
-                        serial_port = UART2_BASE_ADDR;
-                        if (UART(UCR1) & UCR1_UARTEN)
-                                break;
-                        return;
-                } while (0);
-        }
+        if (!uart_base)
+                return;
+        if (!(UART(UCR1) & UCR1_UARTEN))
+                return;
 
         while (!(UART(USR2) & USR2_TXFE))
                 barrier();
@@ -68,11 +62,49 @@ static void putc(int ch)
 
 #define flush() do { } while (0)
 
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
+#define MX1_UART1_BASE_ADDR     0x00206000
+#define MX25_UART1_BASE_ADDR    0x43f90000
+#define MX2X_UART1_BASE_ADDR    0x1000a000
+#define MX3X_UART1_BASE_ADDR    0x43F90000
+#define MX3X_UART2_BASE_ADDR    0x43F94000
+
+static __inline__ void __arch_decomp_setup(unsigned long arch_id)
+{
+        switch (arch_id) {
+        case MACH_TYPE_MX1ADS:
+        case MACH_TYPE_SCB9328:
+                uart_base = MX1_UART1_BASE_ADDR;
+                break;
+        case MACH_TYPE_MX25_3DS:
+                uart_base = MX25_UART1_BASE_ADDR;
+                break;
+        case MACH_TYPE_IMX27LITE:
+        case MACH_TYPE_MX27_3DS:
+        case MACH_TYPE_MX27ADS:
+        case MACH_TYPE_PCM038:
+        case MACH_TYPE_MX21ADS:
+                uart_base = MX2X_UART1_BASE_ADDR;
+                break;
+        case MACH_TYPE_MX31LITE:
+        case MACH_TYPE_ARMADILLO5X0:
+        case MACH_TYPE_MX31MOBOARD:
+        case MACH_TYPE_QONG:
+        case MACH_TYPE_MX31_3DS:
+        case MACH_TYPE_PCM037:
+        case MACH_TYPE_MX31ADS:
+        case MACH_TYPE_MX35_3DS:
+        case MACH_TYPE_PCM043:
+                uart_base = MX3X_UART1_BASE_ADDR;
+                break;
+        case MACH_TYPE_MAGX_ZN5:
+                uart_base = MX3X_UART2_BASE_ADDR;
+                break;
+        default:
+                break;
+        }
+}
 
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
 #define arch_decomp_wdog()
 
 #endif                          /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index 77a078f9513f..851ca99bf1b1 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -29,7 +29,7 @@
 #include <asm/mach/map.h>
 #include <mach/iomux-v3.h>
 
-#define IOMUX_BASE      IO_ADDRESS(IOMUXC_BASE_ADDR)
+static void __iomem *base;
 
 static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG];
 
@@ -45,14 +45,14 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
         if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map))
                 return -EBUSY;
         if (pad->mux_ctrl_ofs)
-                __raw_writel(pad->mux_mode, IOMUX_BASE + pad->mux_ctrl_ofs);
+                __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs);
 
         if (pad->select_input_ofs)
                 __raw_writel(pad->select_input,
-                                IOMUX_BASE + pad->select_input_ofs);
+                                base + pad->select_input_ofs);
 
-        if (!(pad->pad_ctrl & NO_PAD_CTRL))
-                __raw_writel(pad->pad_ctrl, IOMUX_BASE + pad->pad_ctrl_ofs);
+        if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs)
+                __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs);
         return 0;
 }
 EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
@@ -96,3 +96,8 @@ void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count)
         }
 }
 EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads);
+
+void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
+{
+        base = iomux_v3_base;
+}
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 8aee76304f8f..778ddfe57d89 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -44,7 +44,7 @@
 #define AVIC_FIPNDH             0x60    /* fast int pending high */
 #define AVIC_FIPNDL             0x64    /* fast int pending low */
 
-static void __iomem *avic_base;
+void __iomem *avic_base;
 
 int imx_irq_set_priority(unsigned char irq, unsigned char prio)
 {
@@ -113,11 +113,11 @@ static struct irq_chip mxc_avic_chip = {
  * interrupts. It registers the interrupt enable and disable functions
  * to the kernel for each interrupt source.
  */
-void __init mxc_init_irq(void)
+void __init mxc_init_irq(void __iomem *irqbase)
 {
         int i;
 
-        avic_base = IO_ADDRESS(AVIC_BASE_ADDR);
+        avic_base = irqbase;
 
         /* put the AVIC into the reset value with
          * all interrupts disabled
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index ae34198a79dd..5cdbd605ac05 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -32,6 +32,7 @@
 #define MX3_PWMPR                 0x10    /* PWM Period Register */
 #define MX3_PWMCR_PRESCALER(x)    (((x - 1) & 0xFFF) << 4)
 #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define MX3_PWMCR_CLKSRC_IPG      (1 << 16)
 #define MX3_PWMCR_EN              (1 << 0)
 
 
@@ -55,9 +56,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
         if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
                 return -EINVAL;
 
-        if (cpu_is_mx27() || cpu_is_mx3()) {
+        if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25()) {
                 unsigned long long c;
                 unsigned long period_cycles, duty_cycles, prescale;
+                u32 cr;
+
                 c = clk_get_rate(pwm->clk);
                 c = c * period_ns;
                 do_div(c, 1000000000);
@@ -72,9 +75,15 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 
                 writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR);
                 writel(period_cycles, pwm->mmio_base + MX3_PWMPR);
-                writel(MX3_PWMCR_PRESCALER(prescale - 1) |
-                        MX3_PWMCR_CLKSRC_IPG_HIGH | MX3_PWMCR_EN,
-                        pwm->mmio_base + MX3_PWMCR);
+
+                cr = MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_EN;
+
+                if (cpu_is_mx25())
+                        cr |= MX3_PWMCR_CLKSRC_IPG;
+                else
+                        cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
+
+                writel(cr, pwm->mmio_base + MX3_PWMCR);
         } else if (cpu_is_mx1() || cpu_is_mx21()) {
                 /* The PWM subsystem allows for exact frequencies. However,
                  * I cannot connect a scope on my device to the PWM line and
@@ -118,6 +127,8 @@ EXPORT_SYMBOL(pwm_enable);
 
 void pwm_disable(struct pwm_device *pwm)
 {
+        writel(0, pwm->mmio_base + MX3_PWMCR);
+
         if (pwm->clk_enabled) {
                 clk_disable(pwm->clk);
                 pwm->clk_enabled = 0;
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 79c37577c916..97f42799fa58 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -27,32 +27,38 @@
 #include <linux/delay.h>
 
 #include <mach/hardware.h>
+#include <mach/common.h>
 #include <asm/proc-fns.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_ARCH_MX1
-#define WDOG_WCR_REG            IO_ADDRESS(WDT_BASE_ADDR)
-#define WDOG_WCR_ENABLE         (1 << 0)
-#else
-#define WDOG_WCR_REG            IO_ADDRESS(WDOG_BASE_ADDR)
-#define WDOG_WCR_ENABLE         (1 << 2)
-#endif
+static void __iomem *wdog_base;
 
 /*
  * Reset the system. It is called by machine_restart().
  */
 void arch_reset(char mode, const char *cmd)
 {
-        if (!cpu_is_mx1()) {
+        unsigned int wcr_enable;
+
+#ifdef CONFIG_ARCH_MXC91231
+        if (cpu_is_mxc91231()) {
+                mxc91231_arch_reset(mode, cmd);
+                return;
+        }
+#endif
+        if (cpu_is_mx1()) {
+                wcr_enable = (1 << 0);
+        } else {
                 struct clk *clk;
 
                 clk = clk_get_sys("imx-wdt.0", NULL);
                 if (!IS_ERR(clk))
                         clk_enable(clk);
+                wcr_enable = (1 << 2);
         }
 
         /* Assert SRS signal */
-        __raw_writew(WDOG_WCR_ENABLE, WDOG_WCR_REG);
+        __raw_writew(wcr_enable, wdog_base);
 
         /* wait for reset to assert... */
         mdelay(500);
@@ -65,3 +71,8 @@ void arch_reset(char mode, const char *cmd)
         /* we'll take a jump through zero as a poor second */
         cpu_reset(0);
 }
+
+void mxc_arch_reset_init(void __iomem *base)
+{
+        wdog_base = base;
+}
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 88fb3a57e029..844567ee35fe 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -47,7 +47,7 @@
 #define MX2_TSTAT_CAPT          (1 << 1)
 #define MX2_TSTAT_COMP          (1 << 0)
 
-/* MX31, MX35 */
+/* MX31, MX35, MX25, MXC91231 */
 #define MX3_TCTL_WAITEN         (1 << 3)
 #define MX3_TCTL_CLK_IPG        (1 << 6)
 #define MX3_TCTL_FRR            (1 << 9)
@@ -66,7 +66,7 @@ static inline void gpt_irq_disable(void)
 {
         unsigned int tmp;
 
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                 __raw_writel(0, timer_base + MX3_IR);
         else {
                 tmp = __raw_readl(timer_base + MXC_TCTL);
@@ -76,7 +76,7 @@ static inline void gpt_irq_disable(void)
 
 static inline void gpt_irq_enable(void)
 {
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                 __raw_writel(1<<0, timer_base + MX3_IR);
         else {
                 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
@@ -90,7 +90,7 @@ static void gpt_irq_acknowledge(void)
                 __raw_writel(0, timer_base + MX1_2_TSTAT);
         if (cpu_is_mx2())
                 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT);
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                 __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);
 }
 
@@ -117,7 +117,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
 {
         unsigned int c = clk_get_rate(timer_clk);
 
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                 clocksource_mxc.read = mx3_get_cycles;
 
         clocksource_mxc.mult = clocksource_hz2mult(c,
@@ -180,7 +180,7 @@ static void mxc_set_mode(enum clock_event_mode mode,
 
         if (mode != clockevent_mode) {
                 /* Set event time into far-far future */
-                if (cpu_is_mx3())
+                if (cpu_is_mx3() || cpu_is_mx25())
                         __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3,
                                         timer_base + MX3_TCMP);
                 else
@@ -233,7 +233,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
         struct clock_event_device *evt = &clockevent_mxc;
         uint32_t tstat;
 
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                 tstat = __raw_readl(timer_base + MX3_TSTAT);
         else
                 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
@@ -264,7 +264,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
 {
         unsigned int c = clk_get_rate(timer_clk);
 
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                 clockevent_mxc.set_next_event = mx3_set_next_event;
 
         clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
@@ -281,30 +281,13 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
         return 0;
 }
 
-void __init mxc_timer_init(struct clk *timer_clk)
+void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 {
         uint32_t tctl_val;
-        int irq;
 
         clk_enable(timer_clk);
 
-        if (cpu_is_mx1()) {
-#ifdef CONFIG_ARCH_MX1
-                timer_base = IO_ADDRESS(TIM1_BASE_ADDR);
-                irq = TIM1_INT;
-#endif
-        } else if (cpu_is_mx2()) {
-#ifdef CONFIG_ARCH_MX2
-                timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
-                irq = MXC_INT_GPT1;
-#endif
-        } else if (cpu_is_mx3()) {
-#ifdef CONFIG_ARCH_MX3
-                timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
-                irq = MXC_INT_GPT;
-#endif
-        } else
-                BUG();
+        timer_base = base;
 
         /*
          * Initialise to a known state (all timers off, and timing reset)
@@ -313,7 +296,7 @@ void __init mxc_timer_init(struct clk *timer_clk)
         __raw_writel(0, timer_base + MXC_TCTL);
         __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
 
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                 tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;
         else
                 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index efe85d095190..64b3f52bd9b2 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -120,6 +120,10 @@ config OMAP_MBOX_FWK
 config OMAP_IOMMU
         tristate
 
+config OMAP_IOMMU_DEBUG
+        depends on OMAP_IOMMU
+        tristate
+
 choice
         prompt "System timer"
         default OMAP_MPU_TIMER
@@ -183,6 +187,19 @@ config OMAP_SERIAL_WAKE
           to data on the serial RX line. This allows you to wake the
           system from serial console.
 
+choice
+        prompt "OMAP PM layer selection"
+        depends on ARCH_OMAP
+        default OMAP_PM_NOOP
+
+config OMAP_PM_NONE
+        bool "No PM layer"
+
+config OMAP_PM_NOOP
+        bool "No-op/debug PM layer"
+
+endchoice
+
 endmenu
 
 endif
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index a83279523958..98f01910c2cf 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -12,8 +12,13 @@ obj-  :=
 # OCPI interconnect support for 1710, 1610 and 5912
 obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
 
+# omap_device support (OMAP2+ only at the moment)
+obj-$(CONFIG_ARCH_OMAP2) += omap_device.o
+obj-$(CONFIG_ARCH_OMAP3) += omap_device.o
+
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o
+obj-$(CONFIG_OMAP_IOMMU_DEBUG) += iommu-debug.o
 
 obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
@@ -25,3 +30,4 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
 # OMAP mailbox framework
 obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
 
+obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
\ No newline at end of file
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index e8c327a45a55..bf880e966d3b 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -488,7 +488,7 @@ static int __init clk_debugfs_init(void)
         }
         return 0;
 err_out:
-        debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */
+        debugfs_remove_recursive(clk_debugfs_root);
         return err;
 }
 late_initcall(clk_debugfs_init);
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index ebcf006406f9..3a4768d55895 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -54,50 +54,6 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
         struct omap_board_config_kernel *kinfo = NULL;
         int i;
 
-#ifdef CONFIG_OMAP_BOOT_TAG
-        struct omap_board_config_entry *info = NULL;
-
-        if (omap_bootloader_tag_len > 4)
-                info = (struct omap_board_config_entry *) omap_bootloader_tag;
-        while (info != NULL) {
-                u8 *next;
-
-                if (info->tag == tag) {
-                        if (skip == 0)
-                                break;
-                        skip--;
-                }
-
-                if ((info->len & 0x03) != 0) {
-                        /* We bail out to avoid an alignment fault */
-                        printk(KERN_ERR "OMAP peripheral config: Length (%d) not word-aligned (tag %04x)\n",
-                               info->len, info->tag);
-                        return NULL;
-                }
-                next = (u8 *) info + sizeof(*info) + info->len;
-                if (next >= omap_bootloader_tag + omap_bootloader_tag_len)
-                        info = NULL;
-                else
-                        info = (struct omap_board_config_entry *) next;
-        }
-        if (info != NULL) {
-                /* Check the length as a lame attempt to check for
-                 * binary inconsistency. */
-                if (len != NO_LENGTH_CHECK) {
-                        /* Word-align len */
-                        if (len & 0x03)
-                                len = (len + 3) & ~0x03;
-                        if (info->len != len) {
-                                printk(KERN_ERR "OMAP peripheral config: Length mismatch with tag %x (want %d, got %d)\n",
-                                       tag, len, info->len);
-                                return NULL;
-                        }
-                }
-                if (len_out != NULL)
-                        *len_out = info->len;
-                return info->data;
-        }
-#endif
         /* Try to find the config from the board-specific structures
          * in the kernel. */
         for (i = 0; i < omap_board_config_size; i++) {
@@ -127,50 +83,6 @@ const void *omap_get_var_config(u16 tag, size_t *len)
 }
 EXPORT_SYMBOL(omap_get_var_config);
 
-static int __init omap_add_serial_console(void)
-{
-        const struct omap_serial_console_config *con_info;
-        const struct omap_uart_config *uart_info;
-        static char speed[11], *opt = NULL;
-        int line, i, uart_idx;
-
-        uart_info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
-        con_info = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
-                                        struct omap_serial_console_config);
-        if (uart_info == NULL || con_info == NULL)
-                return 0;
-
-        if (con_info->console_uart == 0)
-                return 0;
-
-        if (con_info->console_speed) {
-                snprintf(speed, sizeof(speed), "%u", con_info->console_speed);
-                opt = speed;
-        }
-
-        uart_idx = con_info->console_uart - 1;
-        if (uart_idx >= OMAP_MAX_NR_PORTS) {
-                printk(KERN_INFO "Console: external UART#%d. "
-                        "Not adding it as console this time.\n",
-                        uart_idx + 1);
-                return 0;
-        }
-        if (!(uart_info->enabled_uarts & (1 << uart_idx))) {
-                printk(KERN_ERR "Console: Selected UART#%d is "
-                        "not enabled for this platform\n",
-                        uart_idx + 1);
-                return -1;
-        }
-        line = 0;
-        for (i = 0; i < uart_idx; i++) {
-                if (uart_info->enabled_uarts & (1 << i))
-                        line++;
-        }
-        return add_preferred_console("ttyS", line, opt);
-}
-console_initcall(omap_add_serial_console);
-
-
 /*
  * 32KHz clocksource ... always available, on pretty most chips except
  * OMAP 730 and 1510.  Other timers could be used as clocksources, with
@@ -253,11 +165,8 @@ static struct clocksource clocksource_32k = {
  */
 unsigned long long sched_clock(void)
 {
-        unsigned long long ret;
-
-        ret = (unsigned long long)clocksource_32k.read(&clocksource_32k);
-        ret = (ret * clocksource_32k.mult_orig) >> clocksource_32k.shift;
-        return ret;
+        return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k),
+                                  clocksource_32k.mult, clocksource_32k.shift);
 }
 
 static int __init omap_init_clocksource_32k(void)
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index be4eefda4767..9395898dd49a 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -281,24 +281,27 @@ static int /* __init */ fpga_probe(struct platform_device *pdev)
         return 0;
 }
 
-static int fpga_suspend_late(struct platform_device *pdev, pm_message_t mesg)
+static int fpga_suspend_noirq(struct device *dev)
 {
         __raw_writew(~0, &fpga->leds);
         return 0;
 }
 
-static int fpga_resume_early(struct platform_device *pdev)
+static int fpga_resume_noirq(struct device *dev)
 {
         __raw_writew(~hw_led_state, &fpga->leds);
         return 0;
 }
 
+static struct dev_pm_ops fpga_dev_pm_ops = {
+        .suspend_noirq = fpga_suspend_noirq,
+        .resume_noirq = fpga_resume_noirq,
+};
 
 static struct platform_driver led_driver = {
         .driver.name    = "omap_dbg_led",
+        .driver.pm      = &fpga_dev_pm_ops,
         .probe          = fpga_probe,
-        .suspend_late   = fpga_suspend_late,
-        .resume_early   = fpga_resume_early,
 };
 
 static int __init fpga_init(void)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index e3ac94f09006..fd3154ae69b1 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1127,6 +1127,11 @@ int omap_dma_running(void)
 void omap_dma_link_lch(int lch_head, int lch_queue)
 {
         if (omap_dma_in_1510_mode()) {
+                if (lch_head == lch_queue) {
+                        dma_write(dma_read(CCR(lch_head)) | (3 << 8),
+                                                                CCR(lch_head));
+                        return;
+                }
                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
                 BUG();
                 return;
@@ -1149,6 +1154,11 @@ EXPORT_SYMBOL(omap_dma_link_lch);
 void omap_dma_unlink_lch(int lch_head, int lch_queue)
 {
         if (omap_dma_in_1510_mode()) {
+                if (lch_head == lch_queue) {
+                        dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
+                                                                CCR(lch_head));
+                        return;
+                }
                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
                 BUG();
                 return;
@@ -2337,16 +2347,16 @@ static int __init omap_init_dma(void)
         int ch, r;
 
         if (cpu_class_is_omap1()) {
-                omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
+                omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
         } else if (cpu_is_omap24xx()) {
-                omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
+                omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
         } else if (cpu_is_omap34xx()) {
-                omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
+                omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
         } else if (cpu_is_omap44xx()) {
-                omap_dma_base = IO_ADDRESS(OMAP44XX_DMA4_BASE);
+                omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
         } else {
                 pr_err("DMA init failed for unsupported omap\n");
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 7f50b6103dee..d325b54daeb5 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -774,7 +774,10 @@ int __init omap_dm_timer_init(void)
 
         for (i = 0; i < dm_timer_count; i++) {
                 timer = &dm_timers[i];
-                timer->io_base = IO_ADDRESS(timer->phys_base);
+                if (cpu_class_is_omap1())
+                        timer->io_base = OMAP1_IO_ADDRESS(timer->phys_base);
+                else
+                        timer->io_base = OMAP2_IO_ADDRESS(timer->phys_base);
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
                                         defined(CONFIG_ARCH_OMAP4)
                 if (cpu_class_is_omap2()) {
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 9298bc0ab171..693839c89ad0 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -31,7 +31,7 @@
 /*
  * OMAP1510 GPIO registers
  */
-#define OMAP1510_GPIO_BASE              IO_ADDRESS(0xfffce000)
+#define OMAP1510_GPIO_BASE              OMAP1_IO_ADDRESS(0xfffce000)
 #define OMAP1510_GPIO_DATA_INPUT        0x00
 #define OMAP1510_GPIO_DATA_OUTPUT       0x04
 #define OMAP1510_GPIO_DIR_CONTROL       0x08
@@ -45,10 +45,10 @@
 /*
  * OMAP1610 specific GPIO registers
  */
-#define OMAP1610_GPIO1_BASE             IO_ADDRESS(0xfffbe400)
-#define OMAP1610_GPIO2_BASE             IO_ADDRESS(0xfffbec00)
-#define OMAP1610_GPIO3_BASE             IO_ADDRESS(0xfffbb400)
-#define OMAP1610_GPIO4_BASE             IO_ADDRESS(0xfffbbc00)
+#define OMAP1610_GPIO1_BASE             OMAP1_IO_ADDRESS(0xfffbe400)
+#define OMAP1610_GPIO2_BASE             OMAP1_IO_ADDRESS(0xfffbec00)
+#define OMAP1610_GPIO3_BASE             OMAP1_IO_ADDRESS(0xfffbb400)
+#define OMAP1610_GPIO4_BASE             OMAP1_IO_ADDRESS(0xfffbbc00)
 #define OMAP1610_GPIO_REVISION          0x0000
 #define OMAP1610_GPIO_SYSCONFIG         0x0010
 #define OMAP1610_GPIO_SYSSTATUS         0x0014
@@ -70,12 +70,12 @@
 /*
  * OMAP730 specific GPIO registers
  */
-#define OMAP730_GPIO1_BASE              IO_ADDRESS(0xfffbc000)
-#define OMAP730_GPIO2_BASE              IO_ADDRESS(0xfffbc800)
-#define OMAP730_GPIO3_BASE              IO_ADDRESS(0xfffbd000)
-#define OMAP730_GPIO4_BASE              IO_ADDRESS(0xfffbd800)
-#define OMAP730_GPIO5_BASE              IO_ADDRESS(0xfffbe000)
-#define OMAP730_GPIO6_BASE              IO_ADDRESS(0xfffbe800)
+#define OMAP730_GPIO1_BASE              OMAP1_IO_ADDRESS(0xfffbc000)
+#define OMAP730_GPIO2_BASE              OMAP1_IO_ADDRESS(0xfffbc800)
+#define OMAP730_GPIO3_BASE              OMAP1_IO_ADDRESS(0xfffbd000)
+#define OMAP730_GPIO4_BASE              OMAP1_IO_ADDRESS(0xfffbd800)
+#define OMAP730_GPIO5_BASE              OMAP1_IO_ADDRESS(0xfffbe000)
+#define OMAP730_GPIO6_BASE              OMAP1_IO_ADDRESS(0xfffbe800)
 #define OMAP730_GPIO_DATA_INPUT         0x00
 #define OMAP730_GPIO_DATA_OUTPUT        0x04
 #define OMAP730_GPIO_DIR_CONTROL        0x08
@@ -86,12 +86,12 @@
 /*
  * OMAP850 specific GPIO registers
  */
-#define OMAP850_GPIO1_BASE              IO_ADDRESS(0xfffbc000)
-#define OMAP850_GPIO2_BASE              IO_ADDRESS(0xfffbc800)
-#define OMAP850_GPIO3_BASE              IO_ADDRESS(0xfffbd000)
-#define OMAP850_GPIO4_BASE              IO_ADDRESS(0xfffbd800)
-#define OMAP850_GPIO5_BASE              IO_ADDRESS(0xfffbe000)
-#define OMAP850_GPIO6_BASE              IO_ADDRESS(0xfffbe800)
+#define OMAP850_GPIO1_BASE              OMAP1_IO_ADDRESS(0xfffbc000)
+#define OMAP850_GPIO2_BASE              OMAP1_IO_ADDRESS(0xfffbc800)
+#define OMAP850_GPIO3_BASE              OMAP1_IO_ADDRESS(0xfffbd000)
+#define OMAP850_GPIO4_BASE              OMAP1_IO_ADDRESS(0xfffbd800)
+#define OMAP850_GPIO5_BASE              OMAP1_IO_ADDRESS(0xfffbe000)
+#define OMAP850_GPIO6_BASE              OMAP1_IO_ADDRESS(0xfffbe800)
 #define OMAP850_GPIO_DATA_INPUT         0x00
 #define OMAP850_GPIO_DATA_OUTPUT        0x04
 #define OMAP850_GPIO_DIR_CONTROL        0x08
@@ -99,19 +99,21 @@
 #define OMAP850_GPIO_INT_MASK           0x10
 #define OMAP850_GPIO_INT_STATUS         0x14
 
+#define OMAP1_MPUIO_VBASE               OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
+
 /*
  * omap24xx specific GPIO registers
  */
-#define OMAP242X_GPIO1_BASE             IO_ADDRESS(0x48018000)
-#define OMAP242X_GPIO2_BASE             IO_ADDRESS(0x4801a000)
-#define OMAP242X_GPIO3_BASE             IO_ADDRESS(0x4801c000)
-#define OMAP242X_GPIO4_BASE             IO_ADDRESS(0x4801e000)
+#define OMAP242X_GPIO1_BASE             OMAP2_IO_ADDRESS(0x48018000)
+#define OMAP242X_GPIO2_BASE             OMAP2_IO_ADDRESS(0x4801a000)
+#define OMAP242X_GPIO3_BASE             OMAP2_IO_ADDRESS(0x4801c000)
+#define OMAP242X_GPIO4_BASE             OMAP2_IO_ADDRESS(0x4801e000)
 
-#define OMAP243X_GPIO1_BASE             IO_ADDRESS(0x4900C000)
-#define OMAP243X_GPIO2_BASE             IO_ADDRESS(0x4900E000)
-#define OMAP243X_GPIO3_BASE             IO_ADDRESS(0x49010000)
-#define OMAP243X_GPIO4_BASE             IO_ADDRESS(0x49012000)
-#define OMAP243X_GPIO5_BASE             IO_ADDRESS(0x480B6000)
+#define OMAP243X_GPIO1_BASE             OMAP2_IO_ADDRESS(0x4900C000)
+#define OMAP243X_GPIO2_BASE             OMAP2_IO_ADDRESS(0x4900E000)
+#define OMAP243X_GPIO3_BASE             OMAP2_IO_ADDRESS(0x49010000)
+#define OMAP243X_GPIO4_BASE             OMAP2_IO_ADDRESS(0x49012000)
+#define OMAP243X_GPIO5_BASE             OMAP2_IO_ADDRESS(0x480B6000)
 
 #define OMAP24XX_GPIO_REVISION          0x0000
 #define OMAP24XX_GPIO_SYSCONFIG         0x0010
@@ -138,28 +140,52 @@
 #define OMAP24XX_GPIO_CLEARDATAOUT      0x0090
 #define OMAP24XX_GPIO_SETDATAOUT        0x0094
 
+#define OMAP4_GPIO_REVISION             0x0000
+#define OMAP4_GPIO_SYSCONFIG            0x0010
+#define OMAP4_GPIO_EOI                  0x0020
+#define OMAP4_GPIO_IRQSTATUSRAW0        0x0024
+#define OMAP4_GPIO_IRQSTATUSRAW1        0x0028
+#define OMAP4_GPIO_IRQSTATUS0           0x002c
+#define OMAP4_GPIO_IRQSTATUS1           0x0030
+#define OMAP4_GPIO_IRQSTATUSSET0        0x0034
+#define OMAP4_GPIO_IRQSTATUSSET1        0x0038
+#define OMAP4_GPIO_IRQSTATUSCLR0        0x003c
+#define OMAP4_GPIO_IRQSTATUSCLR1        0x0040
+#define OMAP4_GPIO_IRQWAKEN0            0x0044
+#define OMAP4_GPIO_IRQWAKEN1            0x0048
+#define OMAP4_GPIO_SYSSTATUS            0x0104
+#define OMAP4_GPIO_CTRL                 0x0130
+#define OMAP4_GPIO_OE                   0x0134
+#define OMAP4_GPIO_DATAIN               0x0138
+#define OMAP4_GPIO_DATAOUT              0x013c
+#define OMAP4_GPIO_LEVELDETECT0         0x0140
+#define OMAP4_GPIO_LEVELDETECT1         0x0144
+#define OMAP4_GPIO_RISINGDETECT         0x0148
+#define OMAP4_GPIO_FALLINGDETECT        0x014c
+#define OMAP4_GPIO_DEBOUNCENABLE        0x0150
+#define OMAP4_GPIO_DEBOUNCINGTIME       0x0154
+#define OMAP4_GPIO_CLEARDATAOUT         0x0190
+#define OMAP4_GPIO_SETDATAOUT           0x0194
 /*
  * omap34xx specific GPIO registers
  */
 
-#define OMAP34XX_GPIO1_BASE             IO_ADDRESS(0x48310000)
-#define OMAP34XX_GPIO2_BASE             IO_ADDRESS(0x49050000)
-#define OMAP34XX_GPIO3_BASE             IO_ADDRESS(0x49052000)
-#define OMAP34XX_GPIO4_BASE             IO_ADDRESS(0x49054000)
-#define OMAP34XX_GPIO5_BASE             IO_ADDRESS(0x49056000)
-#define OMAP34XX_GPIO6_BASE             IO_ADDRESS(0x49058000)
+#define OMAP34XX_GPIO1_BASE             OMAP2_IO_ADDRESS(0x48310000)
+#define OMAP34XX_GPIO2_BASE             OMAP2_IO_ADDRESS(0x49050000)
+#define OMAP34XX_GPIO3_BASE             OMAP2_IO_ADDRESS(0x49052000)
+#define OMAP34XX_GPIO4_BASE             OMAP2_IO_ADDRESS(0x49054000)
+#define OMAP34XX_GPIO5_BASE             OMAP2_IO_ADDRESS(0x49056000)
+#define OMAP34XX_GPIO6_BASE             OMAP2_IO_ADDRESS(0x49058000)
 
 /*
  * OMAP44XX  specific GPIO registers
  */
-#define OMAP44XX_GPIO1_BASE             IO_ADDRESS(0x4a310000)
-#define OMAP44XX_GPIO2_BASE             IO_ADDRESS(0x48055000)
-#define OMAP44XX_GPIO3_BASE             IO_ADDRESS(0x48057000)
-#define OMAP44XX_GPIO4_BASE             IO_ADDRESS(0x48059000)
-#define OMAP44XX_GPIO5_BASE             IO_ADDRESS(0x4805B000)
-#define OMAP44XX_GPIO6_BASE             IO_ADDRESS(0x4805D000)
-
-#define OMAP_MPUIO_VBASE                IO_ADDRESS(OMAP_MPUIO_BASE)
+#define OMAP44XX_GPIO1_BASE             OMAP2_IO_ADDRESS(0x4a310000)
+#define OMAP44XX_GPIO2_BASE             OMAP2_IO_ADDRESS(0x48055000)
+#define OMAP44XX_GPIO3_BASE             OMAP2_IO_ADDRESS(0x48057000)
+#define OMAP44XX_GPIO4_BASE             OMAP2_IO_ADDRESS(0x48059000)
+#define OMAP44XX_GPIO5_BASE             OMAP2_IO_ADDRESS(0x4805B000)
+#define OMAP44XX_GPIO6_BASE             OMAP2_IO_ADDRESS(0x4805D000)
 
 struct gpio_bank {
         void __iomem *base;
@@ -195,7 +221,7 @@ struct gpio_bank {
 
 #ifdef CONFIG_ARCH_OMAP16XX
 static struct gpio_bank gpio_bank_1610[5] = {
-        { OMAP_MPUIO_VBASE,    INT_MPUIO,           IH_MPUIO_BASE,     METHOD_MPUIO},
+        { OMAP1_MPUIO_VBASE,    INT_MPUIO,          IH_MPUIO_BASE,     METHOD_MPUIO},
         { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1,      IH_GPIO_BASE,      METHOD_GPIO_1610 },
         { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
         { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
@@ -205,14 +231,14 @@ static struct gpio_bank gpio_bank_1610[5] = {
 
 #ifdef CONFIG_ARCH_OMAP15XX
 static struct gpio_bank gpio_bank_1510[2] = {
-        { OMAP_MPUIO_VBASE,   INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
+        { OMAP1_MPUIO_VBASE,   INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
         { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE,  METHOD_GPIO_1510 }
 };
 #endif
 
 #ifdef CONFIG_ARCH_OMAP730
 static struct gpio_bank gpio_bank_730[7] = {
-        { OMAP_MPUIO_VBASE,    INT_730_MPUIO,       IH_MPUIO_BASE,      METHOD_MPUIO },
+        { OMAP1_MPUIO_VBASE,    INT_730_MPUIO,      IH_MPUIO_BASE,      METHOD_MPUIO },
         { OMAP730_GPIO1_BASE,  INT_730_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_730 },
         { OMAP730_GPIO2_BASE,  INT_730_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_730 },
         { OMAP730_GPIO3_BASE,  INT_730_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_730 },
@@ -224,7 +250,7 @@ static struct gpio_bank gpio_bank_730[7] = {
 
 #ifdef CONFIG_ARCH_OMAP850
 static struct gpio_bank gpio_bank_850[7] = {
-        { OMAP_MPUIO_BASE,     INT_850_MPUIO,       IH_MPUIO_BASE,      METHOD_MPUIO },
+        { OMAP1_MPUIO_BASE,     INT_850_MPUIO,      IH_MPUIO_BASE,      METHOD_MPUIO },
         { OMAP850_GPIO1_BASE,  INT_850_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_850 },
         { OMAP850_GPIO2_BASE,  INT_850_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_850 },
         { OMAP850_GPIO3_BASE,  INT_850_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_850 },
@@ -386,12 +412,16 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
                 reg += OMAP850_GPIO_DIR_CONTROL;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_OE;
                 break;
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
+        case METHOD_GPIO_24XX:
+                reg += OMAP4_GPIO_OE;
+                break;
+#endif
         default:
                 WARN_ON(1);
                 return;
@@ -459,8 +489,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                         l &= ~(1 << gpio);
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 if (enable)
                         reg += OMAP24XX_GPIO_SETDATAOUT;
@@ -469,6 +498,15 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                 l = 1 << gpio;
                 break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+        case METHOD_GPIO_24XX:
+                if (enable)
+                        reg += OMAP4_GPIO_SETDATAOUT;
+                else
+                        reg += OMAP4_GPIO_CLEARDATAOUT;
+                l = 1 << gpio;
+                break;
+#endif
         default:
                 WARN_ON(1);
                 return;
@@ -509,12 +547,16 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
                 reg += OMAP850_GPIO_DATA_INPUT;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_DATAIN;
                 break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+        case METHOD_GPIO_24XX:
+                reg += OMAP4_GPIO_DATAIN;
+                break;
+#endif
         default:
                 return -EINVAL;
         }
@@ -589,7 +631,11 @@ void omap_set_gpio_debounce(int gpio, int enable)
 
         bank = get_gpio_bank(gpio);
         reg = bank->base;
+#ifdef CONFIG_ARCH_OMAP4
+        reg += OMAP4_GPIO_DEBOUNCENABLE;
+#else
         reg += OMAP24XX_GPIO_DEBOUNCE_EN;
+#endif
 
         spin_lock_irqsave(&bank->lock, flags);
         val = __raw_readl(reg);
@@ -626,7 +672,11 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time)
         reg = bank->base;
 
         enc_time &= 0xff;
+#ifdef CONFIG_ARCH_OMAP4
+        reg += OMAP4_GPIO_DEBOUNCINGTIME;
+#else
         reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
+#endif
         __raw_writel(enc_time, reg);
 }
 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
@@ -638,23 +688,46 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
 {
         void __iomem *base = bank->base;
         u32 gpio_bit = 1 << gpio;
+        u32 val;
 
-        MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
-                trigger & IRQ_TYPE_LEVEL_LOW);
-        MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
-                trigger & IRQ_TYPE_LEVEL_HIGH);
-        MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
-                trigger & IRQ_TYPE_EDGE_RISING);
-        MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
-                trigger & IRQ_TYPE_EDGE_FALLING);
-
+        if (cpu_is_omap44xx()) {
+                MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_LOW);
+                MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_HIGH);
+                MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_RISING);
+                MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_FALLING);
+        } else {
+                MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_LOW);
+                MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_HIGH);
+                MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_RISING);
+                MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_FALLING);
+        }
         if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
-                if (trigger != 0)
-                        __raw_writel(1 << gpio, bank->base
+                if (cpu_is_omap44xx()) {
+                        if (trigger != 0)
+                                __raw_writel(1 << gpio, bank->base+
+                                                OMAP4_GPIO_IRQWAKEN0);
+                        else {
+                                val = __raw_readl(bank->base +
+                                                        OMAP4_GPIO_IRQWAKEN0);
+                                __raw_writel(val & (~(1 << gpio)), bank->base +
+                                                         OMAP4_GPIO_IRQWAKEN0);
+                        }
+                } else {
+                        if (trigger != 0)
+                                __raw_writel(1 << gpio, bank->base
                                         + OMAP24XX_GPIO_SETWKUENA);
-                else
-                        __raw_writel(1 << gpio, bank->base
+                        else
+                                __raw_writel(1 << gpio, bank->base
                                         + OMAP24XX_GPIO_CLEARWKUENA);
+                }
         } else {
                 if (trigger != 0)
                         bank->enabled_non_wakeup_gpios |= gpio_bit;
@@ -662,9 +735,15 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
                         bank->enabled_non_wakeup_gpios &= ~gpio_bit;
         }
 
-        bank->level_mask =
-                __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
-                __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+        if (cpu_is_omap44xx()) {
+                bank->level_mask =
+                        __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
+                        __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
+        } else {
+                bank->level_mask =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
+                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+        }
 }
 #endif
 
@@ -828,12 +907,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
                 reg += OMAP850_GPIO_INT_STATUS;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_IRQSTATUS1;
                 break;
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
+        case METHOD_GPIO_24XX:
+                reg += OMAP4_GPIO_IRQSTATUS0;
+                break;
+#endif
         default:
                 WARN_ON(1);
                 return;
@@ -843,12 +926,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
         /* Workaround for clearing DSP GPIO interrupts to allow retention */
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+#endif
+#if defined(CONFIG_ARCH_OMAP4)
+        reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
+#endif
+        if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
                 __raw_writel(gpio_mask, reg);
 
         /* Flush posted write for the irq status to avoid spurious interrupts */
         __raw_readl(reg);
-#endif
+        }
 }
 
 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
@@ -898,13 +985,18 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
                 inv = 1;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_IRQENABLE1;
                 mask = 0xffffffff;
                 break;
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
+        case METHOD_GPIO_24XX:
+                reg += OMAP4_GPIO_IRQSTATUSSET0;
+                mask = 0xffffffff;
+                break;
+#endif
         default:
                 WARN_ON(1);
                 return 0;
@@ -972,8 +1064,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                         l |= gpio_mask;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 if (enable)
                         reg += OMAP24XX_GPIO_SETIRQENABLE1;
@@ -982,6 +1073,15 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                 l = gpio_mask;
                 break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+        case METHOD_GPIO_24XX:
+                if (enable)
+                        reg += OMAP4_GPIO_IRQSTATUSSET0;
+                else
+                        reg += OMAP4_GPIO_IRQSTATUSCLR0;
+                l = gpio_mask;
+                break;
+#endif
         default:
                 WARN_ON(1);
                 return;
@@ -1157,11 +1257,14 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         if (bank->method == METHOD_GPIO_850)
                 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         if (bank->method == METHOD_GPIO_24XX)
                 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
+        if (bank->method == METHOD_GPIO_24XX)
+                isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
+#endif
         while(1) {
                 u32 isr_saved, level_mask = 0;
                 u32 enabled;
@@ -1315,8 +1418,9 @@ static struct irq_chip mpuio_irq_chip = {
 
 #include <linux/platform_device.h>
 
-static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
+static int omap_mpuio_suspend_noirq(struct device *dev)
 {
+        struct platform_device *pdev = to_platform_device(dev);
         struct gpio_bank        *bank = platform_get_drvdata(pdev);
         void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
         unsigned long           flags;
@@ -1329,8 +1433,9 @@ static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t me
         return 0;
 }
 
-static int omap_mpuio_resume_early(struct platform_device *pdev)
+static int omap_mpuio_resume_noirq(struct device *dev)
 {
+        struct platform_device *pdev = to_platform_device(dev);
         struct gpio_bank        *bank = platform_get_drvdata(pdev);
         void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
         unsigned long           flags;
@@ -1342,14 +1447,18 @@ static int omap_mpuio_resume_early(struct platform_device *pdev)
         return 0;
 }
 
+static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
+        .suspend_noirq = omap_mpuio_suspend_noirq,
+        .resume_noirq = omap_mpuio_resume_noirq,
+};
+
 /* use platform_driver for this, now that there's no longer any
  * point to sys_device (other than not disturbing old code).
  */
 static struct platform_driver omap_mpuio_driver = {
-        .suspend_late   = omap_mpuio_suspend_late,
-        .resume_early   = omap_mpuio_resume_early,
         .driver         = {
                 .name   = "mpuio",
+                .pm     = &omap_mpuio_dev_pm_ops,
         },
 };
 
@@ -1638,7 +1747,7 @@ static int __init _omap_gpio_init(void)
 
                 gpio_bank_count = OMAP34XX_NR_GPIOS;
                 gpio_bank = gpio_bank_44xx;
-                rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
+                rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
                 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
                         (rev >> 4) & 0x0f, rev & 0x0f);
         }
@@ -1672,7 +1781,16 @@ static int __init _omap_gpio_init(void)
                         static const u32 non_wakeup_gpios[] = {
                                 0xe203ffc0, 0x08700040
                         };
-
+                if (cpu_is_omap44xx()) {
+                        __raw_writel(0xffffffff, bank->base +
+                                                OMAP4_GPIO_IRQSTATUSCLR0);
+                        __raw_writew(0x0015, bank->base +
+                                                OMAP4_GPIO_SYSCONFIG);
+                        __raw_writel(0x00000000, bank->base +
+                                                 OMAP4_GPIO_DEBOUNCENABLE);
+                        /* Initialize interface clock ungated, module enabled */
+                        __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
+                } else {
                         __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
                         __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
                         __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
@@ -1680,12 +1798,12 @@ static int __init _omap_gpio_init(void)
 
                         /* Initialize interface clock ungated, module enabled */
                         __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
+                }
                         if (i < ARRAY_SIZE(non_wakeup_gpios))
                                 bank->non_wakeup_gpios = non_wakeup_gpios[i];
                         gpio_count = 32;
                 }
 #endif
-
                 /* REVISIT eventually switch from OMAP-specific gpio structs
                  * over to the generic ones
                  */
@@ -1771,14 +1889,20 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
                         wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
                         break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                 case METHOD_GPIO_24XX:
                         wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
                         wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
                         wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
                         break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                case METHOD_GPIO_24XX:
+                        wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        break;
+#endif
                 default:
                         continue;
                 }
@@ -1813,13 +1937,18 @@ static int omap_gpio_resume(struct sys_device *dev)
                         wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
                         break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                 case METHOD_GPIO_24XX:
                         wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
                         wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
                         break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                case METHOD_GPIO_24XX:
+                        wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        break;
+#endif
                 default:
                         continue;
                 }
@@ -1863,21 +1992,29 @@ void omap2_gpio_prepare_for_retention(void)
 
                 if (!(bank->enabled_non_wakeup_gpios))
                         continue;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
                 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                bank->saved_datain = __raw_readl(bank->base +
+                                                        OMAP4_GPIO_DATAIN);
+                l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
+                l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
+#endif
                 bank->saved_fallingdetect = l1;
                 bank->saved_risingdetect = l2;
                 l1 &= ~bank->enabled_non_wakeup_gpios;
                 l2 &= ~bank->enabled_non_wakeup_gpios;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
+                __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
+#endif
                 c++;
         }
         if (!c) {
@@ -1895,38 +2032,73 @@ void omap2_gpio_resume_after_retention(void)
                 return;
         for (i = 0; i < gpio_bank_count; i++) {
                 struct gpio_bank *bank = &gpio_bank[i];
-                u32 l;
+                u32 l, gen, gen0, gen1;
 
                 if (!(bank->enabled_non_wakeup_gpios))
                         continue;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                 __raw_writel(bank->saved_fallingdetect,
                                  bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                 __raw_writel(bank->saved_risingdetect,
                                  bank->base + OMAP24XX_GPIO_RISINGDETECT);
+                l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+                __raw_writel(bank->saved_fallingdetect,
+                                 bank->base + OMAP4_GPIO_FALLINGDETECT);
+                __raw_writel(bank->saved_risingdetect,
+                                 bank->base + OMAP4_GPIO_RISINGDETECT);
+                l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
 #endif
                 /* Check if any of the non-wakeup interrupt GPIOs have changed
                  * state.  If so, generate an IRQ by software.  This is
                  * horribly racy, but it's the best we can do to work around
                  * this silicon bug. */
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
-                l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
-#endif
                 l ^= bank->saved_datain;
                 l &= bank->non_wakeup_gpios;
-                if (l) {
+
+                /*
+                 * No need to generate IRQs for the rising edge for gpio IRQs
+                 * configured with falling edge only; and vice versa.
+                 */
+                gen0 = l & bank->saved_fallingdetect;
+                gen0 &= bank->saved_datain;
+
+                gen1 = l & bank->saved_risingdetect;
+                gen1 &= ~(bank->saved_datain);
+
+                /* FIXME: Consider GPIO IRQs with level detections properly! */
+                gen = l & (~(bank->saved_fallingdetect) &
+                                ~(bank->saved_risingdetect));
+                /* Consider all GPIO IRQs needed to be updated */
+                gen |= gen0 | gen1;
+
+                if (gen) {
                         u32 old0, old1;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                         old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
                         old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-                        __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
-                        __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+                        __raw_writel(old0 | gen, bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT0);
+                        __raw_writel(old1 | gen, bank->base +
+                                        OMAP24XX_GPIO_LEVELDETECT1);
                         __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
                         __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                        old0 = __raw_readl(bank->base +
+                                                OMAP4_GPIO_LEVELDETECT0);
+                        old1 = __raw_readl(bank->base +
+                                                OMAP4_GPIO_LEVELDETECT1);
+                        __raw_writel(old0 | l, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT0);
+                        __raw_writel(old1 | l, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT1);
+                        __raw_writel(old0, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT0);
+                        __raw_writel(old1, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT1);
+#endif
                 }
         }
 
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/mach/board.h
index 50ea79a0efa2..8e913c322810 100644
--- a/arch/arm/plat-omap/include/mach/board.h
+++ b/arch/arm/plat-omap/include/mach/board.h
@@ -16,10 +16,8 @@
 
 /* Different peripheral ids */
 #define OMAP_TAG_CLOCK          0x4f01
-#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
 #define OMAP_TAG_LCD            0x4f05
 #define OMAP_TAG_GPIO_SWITCH    0x4f06
-#define OMAP_TAG_UART           0x4f07
 #define OMAP_TAG_FBMEM          0x4f08
 #define OMAP_TAG_STI_CONSOLE    0x4f09
 #define OMAP_TAG_CAMERA_SENSOR  0x4f0a
diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/mach/clockdomain.h
index b9d0dd2da89b..99ebd886f134 100644
--- a/arch/arm/plat-omap/include/mach/clockdomain.h
+++ b/arch/arm/plat-omap/include/mach/clockdomain.h
@@ -95,7 +95,8 @@ int clkdm_register(struct clockdomain *clkdm);
 int clkdm_unregister(struct clockdomain *clkdm);
 struct clockdomain *clkdm_lookup(const char *name);
 
-int clkdm_for_each(int (*fn)(struct clockdomain *clkdm));
+int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
+                        void *user);
 struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
 
 void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
index 8140dbccb7bc..826d317cdbec 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/mach/control.h
@@ -20,15 +20,15 @@
 
 #ifndef __ASSEMBLY__
 #define OMAP242X_CTRL_REGADDR(reg)                                      \
-        IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+        OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
 #define OMAP243X_CTRL_REGADDR(reg)                                      \
-        IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+        OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)                                      \
-        IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+        OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
 #else
-#define OMAP242X_CTRL_REGADDR(reg)      IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
-#define OMAP243X_CTRL_REGADDR(reg)      IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
-#define OMAP343X_CTRL_REGADDR(reg)      IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define OMAP242X_CTRL_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+#define OMAP243X_CTRL_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+#define OMAP343X_CTRL_REGADDR(reg)      OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
 #endif /* __ASSEMBLY__ */
 
 /*
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
index 7b939cc01962..72f680b7180d 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -122,6 +122,11 @@
 #define OMAP_DMA4_CCFN(n)               (0x60 * (n) + 0xc0)
 #define OMAP_DMA4_COLOR(n)              (0x60 * (n) + 0xc4)
 
+/* Additional registers available on OMAP4 */
+#define OMAP_DMA4_CDP(n)                (0x60 * (n) + 0xd0)
+#define OMAP_DMA4_CNDP(n)               (0x60 * (n) + 0xd4)
+#define OMAP_DMA4_CCDN(n)               (0x60 * (n) + 0xd8)
+
 /* Dummy defines to keep multi-omap compiles happy */
 #define OMAP1_DMA_REVISION              0
 #define OMAP1_DMA_IRQSTATUS_L0          0
@@ -311,6 +316,89 @@
 #define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
 #define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
 
+/* DMA request lines for 44xx */
+#define OMAP44XX_DMA_DSS_DISPC_REQ      6       /* S_DMA_5 */
+#define OMAP44XX_DMA_SYS_REQ2           7       /* S_DMA_6 */
+#define OMAP44XX_DMA_ISS_REQ1           9       /* S_DMA_8 */
+#define OMAP44XX_DMA_ISS_REQ2           10      /* S_DMA_9 */
+#define OMAP44XX_DMA_ISS_REQ3           12      /* S_DMA_11 */
+#define OMAP44XX_DMA_ISS_REQ4           13      /* S_DMA_12 */
+#define OMAP44XX_DMA_DSS_RFBI_REQ       14      /* S_DMA_13 */
+#define OMAP44XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
+#define OMAP44XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
+#define OMAP44XX_DMA_MCBSP2_TX          17      /* S_DMA_16 */
+#define OMAP44XX_DMA_MCBSP2_RX          18      /* S_DMA_17 */
+#define OMAP44XX_DMA_MCBSP3_TX          19      /* S_DMA_18 */
+#define OMAP44XX_DMA_MCBSP3_RX          20      /* S_DMA_19 */
+#define OMAP44XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
+#define OMAP44XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
+#define OMAP44XX_DMA_I2C3_TX            25      /* S_DMA_24 */
+#define OMAP44XX_DMA_I2C3_RX            26      /* S_DMA_25 */
+#define OMAP44XX_DMA_I2C1_TX            27      /* S_DMA_26 */
+#define OMAP44XX_DMA_I2C1_RX            28      /* S_DMA_27 */
+#define OMAP44XX_DMA_I2C2_TX            29      /* S_DMA_28 */
+#define OMAP44XX_DMA_I2C2_RX            30      /* S_DMA_29 */
+#define OMAP44XX_DMA_MCBSP4_TX          31      /* S_DMA_30 */
+#define OMAP44XX_DMA_MCBSP4_RX          32      /* S_DMA_31 */
+#define OMAP44XX_DMA_MCBSP1_TX          33      /* S_DMA_32 */
+#define OMAP44XX_DMA_MCBSP1_RX          34      /* S_DMA_33 */
+#define OMAP44XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
+#define OMAP44XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
+#define OMAP44XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
+#define OMAP44XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
+#define OMAP44XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
+#define OMAP44XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
+#define OMAP44XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
+#define OMAP44XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
+#define OMAP44XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
+#define OMAP44XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
+#define OMAP44XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
+#define OMAP44XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
+#define OMAP44XX_DMA_MMC2_TX            47      /* S_DMA_46 */
+#define OMAP44XX_DMA_MMC2_RX            48      /* S_DMA_47 */
+#define OMAP44XX_DMA_UART1_TX           49      /* S_DMA_48 */
+#define OMAP44XX_DMA_UART1_RX           50      /* S_DMA_49 */
+#define OMAP44XX_DMA_UART2_TX           51      /* S_DMA_50 */
+#define OMAP44XX_DMA_UART2_RX           52      /* S_DMA_51 */
+#define OMAP44XX_DMA_UART3_TX           53      /* S_DMA_52 */
+#define OMAP44XX_DMA_UART3_RX           54      /* S_DMA_53 */
+#define OMAP44XX_DMA_UART4_TX           55      /* S_DMA_54 */
+#define OMAP44XX_DMA_UART4_RX           56      /* S_DMA_55 */
+#define OMAP44XX_DMA_MMC4_TX            57      /* S_DMA_56 */
+#define OMAP44XX_DMA_MMC4_RX            58      /* S_DMA_57 */
+#define OMAP44XX_DMA_MMC5_TX            59      /* S_DMA_58 */
+#define OMAP44XX_DMA_MMC5_RX            60      /* S_DMA_59 */
+#define OMAP44XX_DMA_MMC1_TX            61      /* S_DMA_60 */
+#define OMAP44XX_DMA_MMC1_RX            62      /* S_DMA_61 */
+#define OMAP44XX_DMA_SYS_REQ3           64      /* S_DMA_63 */
+#define OMAP44XX_DMA_MCPDM_UP           65      /* S_DMA_64 */
+#define OMAP44XX_DMA_MCPDM_DL           66      /* S_DMA_65 */
+#define OMAP44XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
+#define OMAP44XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ0      72      /* S_DMA_71 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ1      73      /* S_DMA_72 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ2      74      /* S_DMA_73 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ3      75      /* S_DMA_74 */
+#define OMAP44XX_DMA_DSS_HDMI_REQ       76      /* S_DMA_75 */
+#define OMAP44XX_DMA_MMC3_TX            77      /* S_DMA_76 */
+#define OMAP44XX_DMA_MMC3_RX            78      /* S_DMA_77 */
+#define OMAP44XX_DMA_USIM_TX            79      /* S_DMA_78 */
+#define OMAP44XX_DMA_USIM_RX            80      /* S_DMA_79 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ0      81      /* S_DMA_80 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ1      82      /* S_DMA_81 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ2      83      /* S_DMA_82 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ3      84      /* S_DMA_83 */
+#define OMAP44XX_DMA_ABE_REQ0           101     /* S_DMA_100 */
+#define OMAP44XX_DMA_ABE_REQ1           102     /* S_DMA_101 */
+#define OMAP44XX_DMA_ABE_REQ2           103     /* S_DMA_102 */
+#define OMAP44XX_DMA_ABE_REQ3           104     /* S_DMA_103 */
+#define OMAP44XX_DMA_ABE_REQ4           105     /* S_DMA_104 */
+#define OMAP44XX_DMA_ABE_REQ5           106     /* S_DMA_105 */
+#define OMAP44XX_DMA_ABE_REQ6           107     /* S_DMA_106 */
+#define OMAP44XX_DMA_ABE_REQ7           108     /* S_DMA_107 */
+#define OMAP44XX_DMA_I2C4_TX            124     /* S_DMA_123 */
+#define OMAP44XX_DMA_I2C4_RX            125     /* S_DMA_124 */
+
 /*----------------------------------------------------------------------------*/
 
 /* Hardware registers for LCD DMA */
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
index 56426ed45ef4..a5592991634d 100644
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ b/arch/arm/plat-omap/include/mach/entry-macro.S
@@ -41,7 +41,7 @@
                 .endm
 
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =IO_ADDRESS(OMAP_IH1_BASE)
+                ldr     \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
                 ldr     \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
                 ldr     \tmp, [\base, #IRQ_MIR_REG_OFFSET]
                 mov     \irqstat, #0xffffffff
@@ -53,7 +53,7 @@
                 cmp     \irqnr, #0
                 ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
                 cmpeq   \irqnr, #INT_IH2_IRQ
-                ldreq   \base, =IO_ADDRESS(OMAP_IH2_BASE)
+                ldreq   \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
                 ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
                 addeqs  \irqnr, \irqnr, #32
 1510:
@@ -68,9 +68,9 @@
 
 /* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
 #if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
-#define OMAP2_VA_IC_BASE                IO_ADDRESS(OMAP24XX_IC_BASE)
+#define OMAP2_VA_IC_BASE                OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE)
 #elif defined(CONFIG_ARCH_OMAP34XX)
-#define OMAP2_VA_IC_BASE                IO_ADDRESS(OMAP34XX_IC_BASE)
+#define OMAP2_VA_IC_BASE                OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE)
 #endif
 #if defined(CONFIG_ARCH_OMAP4)
 #include <mach/omap44xx.h>
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h
index 2b22a8799bc6..633ff688b928 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/mach/gpio.h
@@ -29,7 +29,7 @@
 #include <linux/io.h>
 #include <mach/irqs.h>
 
-#define OMAP_MPUIO_BASE                 0xfffb5000
+#define OMAP1_MPUIO_BASE                        0xfffb5000
 
 #if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
 
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index 21fb0efdda86..8d32df32b0b1 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -54,17 +54,33 @@
  * ----------------------------------------------------------------------------
  */
 
-#if defined(CONFIG_ARCH_OMAP1)
+#ifdef __ASSEMBLER__
+#define IOMEM(x)                (x)
+#else
+#define IOMEM(x)                ((void __force __iomem *)(x))
+#endif
+
+#define OMAP1_IO_OFFSET         0x01000000      /* Virtual IO = 0xfefb0000 */
+#define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
+
+#define OMAP2_IO_OFFSET         0x90000000
+#define OMAP2_IO_ADDRESS(pa)    IOMEM((pa) + OMAP2_IO_OFFSET) /* L3 and L4 */
+
+/*
+ * ----------------------------------------------------------------------------
+ * Omap1 specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
 
-#define IO_PHYS                 0xFFFB0000
-#define IO_OFFSET               0x01000000      /* Virtual IO = 0xfefb0000 */
-#define IO_SIZE                 0x40000
-#define IO_VIRT                 (IO_PHYS - IO_OFFSET)
-#define __IO_ADDRESS(pa)        ((pa) - IO_OFFSET)
-#define __OMAP1_IO_ADDRESS(pa)  ((pa) - IO_OFFSET)
-#define io_v2p(va)              ((va) + IO_OFFSET)
+#define OMAP1_IO_PHYS           0xFFFB0000
+#define OMAP1_IO_SIZE           0x40000
+#define OMAP1_IO_VIRT           (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
 
-#elif defined(CONFIG_ARCH_OMAP2)
+/*
+ * ----------------------------------------------------------------------------
+ * Omap2 specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
 
 /* We map both L3 and L4 on OMAP2 */
 #define L3_24XX_PHYS    L3_24XX_BASE    /* 0x68000000 */
@@ -87,11 +103,6 @@
 #define OMAP243X_SMS_VIRT       0xFC000000
 #define OMAP243X_SMS_SIZE       SZ_1M
 
-#define IO_OFFSET               0x90000000
-#define __IO_ADDRESS(pa)        ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
-#define __OMAP2_IO_ADDRESS(pa)  ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
-#define io_v2p(va)              ((va) - IO_OFFSET)      /* Works for L3 and L4 */
-
 /* DSP */
 #define DSP_MEM_24XX_PHYS       OMAP2420_DSP_MEM_BASE   /* 0x58000000 */
 #define DSP_MEM_24XX_VIRT       0xe0000000
@@ -103,7 +114,11 @@
 #define DSP_MMU_24XX_VIRT       0xe2000000
 #define DSP_MMU_24XX_SIZE       SZ_4K
 
-#elif defined(CONFIG_ARCH_OMAP3)
+/*
+ * ----------------------------------------------------------------------------
+ * Omap3 specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
 
 /* We map both L3 and L4 on OMAP3 */
 #define L3_34XX_PHYS            L3_34XX_BASE    /* 0x68000000 */
@@ -143,12 +158,6 @@
 #define OMAP343X_SDRC_VIRT      0xFD000000
 #define OMAP343X_SDRC_SIZE      SZ_1M
 
-
-#define IO_OFFSET               0x90000000
-#define __IO_ADDRESS(pa)        ((pa) + IO_OFFSET)/* Works for L3 and L4 */
-#define __OMAP2_IO_ADDRESS(pa)  ((pa) + IO_OFFSET)/* Works for L3 and L4 */
-#define io_v2p(va)              ((va) - IO_OFFSET)/* Works for L3 and L4 */
-
 /* DSP */
 #define DSP_MEM_34XX_PHYS       OMAP34XX_DSP_MEM_BASE   /* 0x58000000 */
 #define DSP_MEM_34XX_VIRT       0xe0000000
@@ -160,8 +169,12 @@
 #define DSP_MMU_34XX_VIRT       0xe2000000
 #define DSP_MMU_34XX_SIZE       SZ_4K
 
+/*
+ * ----------------------------------------------------------------------------
+ * Omap4 specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
 
-#elif defined(CONFIG_ARCH_OMAP4)
 /* We map both L3 and L4 on OMAP4 */
 #define L3_44XX_PHYS            L3_44XX_BASE
 #define L3_44XX_VIRT            0xd4000000
@@ -189,38 +202,24 @@
 #define OMAP44XX_GPMC_SIZE      SZ_1M
 
 
-#define IO_OFFSET               0x90000000
-#define __IO_ADDRESS(pa)        ((pa) + IO_OFFSET)/* Works for L3 and L4 */
-#define __OMAP2_IO_ADDRESS(pa)  ((pa) + IO_OFFSET)/* Works for L3 and L4 */
-#define io_v2p(va)              ((va) - IO_OFFSET)/* Works for L3 and L4 */
-
-#endif
-
-#define IO_ADDRESS(pa)          IOMEM(__IO_ADDRESS(pa))
-#define OMAP1_IO_ADDRESS(pa)    IOMEM(__OMAP1_IO_ADDRESS(pa))
-#define OMAP2_IO_ADDRESS(pa)    IOMEM(__OMAP2_IO_ADDRESS(pa))
+/*
+ * ----------------------------------------------------------------------------
+ * Omap specific register access
+ * ----------------------------------------------------------------------------
+ */
 
-#ifdef __ASSEMBLER__
-#define IOMEM(x)                (x)
-#else
-#define IOMEM(x)                ((void __force __iomem *)(x))
+#ifndef __ASSEMBLER__
 
 /*
- * Functions to access the OMAP IO region
- *
- * NOTE: - Use omap_read/write[bwl] for physical register addresses
- *       - Use __raw_read/write[bwl]() for virtual register addresses
- *       - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
- *       - DO NOT use hardcoded virtual addresses to allow changing the
- *         IO address space again if needed
+ * NOTE: Please use ioremap + __raw_read/write where possible instead of these
  */
-#define omap_readb(a)           __raw_readb(IO_ADDRESS(a))
-#define omap_readw(a)           __raw_readw(IO_ADDRESS(a))
-#define omap_readl(a)           __raw_readl(IO_ADDRESS(a))
 
-#define omap_writeb(v,a)        __raw_writeb(v, IO_ADDRESS(a))
-#define omap_writew(v,a)        __raw_writew(v, IO_ADDRESS(a))
-#define omap_writel(v,a)        __raw_writel(v, IO_ADDRESS(a))
+extern u8 omap_readb(u32 pa);
+extern u16 omap_readw(u32 pa);
+extern u32 omap_readl(u32 pa);
+extern void omap_writeb(u8 v, u32 pa);
+extern void omap_writew(u16 v, u32 pa);
+extern void omap_writel(u32 v, u32 pa);
 
 struct omap_sdrc_params;
 
diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/mach/iommu.h
index 769b00b4c34a..46d41ac83dbf 100644
--- a/arch/arm/plat-omap/include/mach/iommu.h
+++ b/arch/arm/plat-omap/include/mach/iommu.h
@@ -95,7 +95,7 @@ struct iommu_functions {
 
         void (*save_ctx)(struct iommu *obj);
         void (*restore_ctx)(struct iommu *obj);
-        ssize_t (*dump_ctx)(struct iommu *obj, char *buf);
+        ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len);
 };
 
 struct iommu_platform_data {
@@ -162,7 +162,7 @@ extern void uninstall_iommu_arch(const struct iommu_functions *ops);
 extern int foreach_iommu_device(void *data,
                                 int (*fn)(struct device *, void *));
 
-extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf);
-extern size_t dump_tlb_entries(struct iommu *obj, char *buf);
+extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len);
+extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len);
 
 #endif /* __MACH_IOMMU_H */
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index bb154ea76769..e0d6eca222cc 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -53,6 +53,11 @@
 #define OMAP34XX_MCBSP4_BASE    0x49026000
 #define OMAP34XX_MCBSP5_BASE    0x48096000
 
+#define OMAP44XX_MCBSP1_BASE    0x49022000
+#define OMAP44XX_MCBSP2_BASE    0x49024000
+#define OMAP44XX_MCBSP3_BASE    0x49026000
+#define OMAP44XX_MCBSP4_BASE    0x48074000
+
 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
 
 #define OMAP_MCBSP_REG_DRR2     0x00
@@ -98,7 +103,8 @@
 #define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
 #define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
 
-#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+        defined(CONFIG_ARCH_OMAP4)
 
 #define OMAP_MCBSP_REG_DRR2     0x00
 #define OMAP_MCBSP_REG_DRR1     0x04
@@ -134,6 +140,11 @@
 #define OMAP_MCBSP_REG_XCERG    0x74
 #define OMAP_MCBSP_REG_XCERH    0x78
 #define OMAP_MCBSP_REG_SYSCON   0x8C
+#define OMAP_MCBSP_REG_THRSH2   0x90
+#define OMAP_MCBSP_REG_THRSH1   0x94
+#define OMAP_MCBSP_REG_IRQST    0xA0
+#define OMAP_MCBSP_REG_IRQEN    0xA4
+#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
 #define OMAP_MCBSP_REG_XCCR     0xAC
 #define OMAP_MCBSP_REG_RCCR     0xB0
 
@@ -249,8 +260,27 @@
 #define RDISABLE                0x0001
 
 /********************** McBSP SYSCONFIG bit definitions ********************/
+#define CLOCKACTIVITY(value)    ((value)<<8)
+#define SIDLEMODE(value)        ((value)<<3)
+#define ENAWAKEUP               0x0004
 #define SOFTRST                 0x0002
 
+/********************** McBSP DMA operating modes **************************/
+#define MCBSP_DMA_MODE_ELEMENT          0
+#define MCBSP_DMA_MODE_THRESHOLD        1
+#define MCBSP_DMA_MODE_FRAME            2
+
+/********************** McBSP WAKEUPEN bit definitions *********************/
+#define XEMPTYEOFEN             0x4000
+#define XRDYEN                  0x0400
+#define XEOFEN                  0x0200
+#define XFSXEN                  0x0100
+#define XSYNCERREN              0x0080
+#define RRDYEN                  0x0008
+#define REOFEN                  0x0004
+#define RFSREN                  0x0002
+#define RSYNCERREN              0x0001
+
 /* we don't do multichannel for now */
 struct omap_mcbsp_reg_cfg {
         u16 spcr2;
@@ -344,6 +374,9 @@ struct omap_mcbsp_platform_data {
         u8 dma_rx_sync, dma_tx_sync;
         u16 rx_irq, tx_irq;
         struct omap_mcbsp_ops *ops;
+#ifdef CONFIG_ARCH_OMAP34XX
+        u16 buffer_size;
+#endif
 };
 
 struct omap_mcbsp {
@@ -377,6 +410,11 @@ struct omap_mcbsp {
         struct omap_mcbsp_platform_data *pdata;
         struct clk *iclk;
         struct clk *fclk;
+#ifdef CONFIG_ARCH_OMAP34XX
+        int dma_op_mode;
+        u16 max_tx_thres;
+        u16 max_rx_thres;
+#endif
 };
 extern struct omap_mcbsp **mcbsp_ptr;
 extern int omap_mcbsp_count;
@@ -385,10 +423,25 @@ int omap_mcbsp_init(void);
 void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
                                         int size);
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
+#ifdef CONFIG_ARCH_OMAP34XX
+void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
+void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
+u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
+u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
+int omap_mcbsp_get_dma_op_mode(unsigned int id);
+#else
+static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
+{ }
+static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
+{ }
+static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
+static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
+static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
+#endif
 int omap_mcbsp_request(unsigned int id);
 void omap_mcbsp_free(unsigned int id);
-void omap_mcbsp_start(unsigned int id);
-void omap_mcbsp_stop(unsigned int id);
+void omap_mcbsp_start(unsigned int id, int tx, int rx);
+void omap_mcbsp_stop(unsigned int id, int tx, int rx);
 void omap_mcbsp_xmit_word(unsigned int id, u32 word);
 u32 omap_mcbsp_recv_word(unsigned int id);
 
diff --git a/arch/arm/plat-omap/include/mach/mtd-xip.h b/arch/arm/plat-omap/include/mach/mtd-xip.h
index 39b591ff54bb..f82a8dcaad94 100644
--- a/arch/arm/plat-omap/include/mach/mtd-xip.h
+++ b/arch/arm/plat-omap/include/mach/mtd-xip.h
@@ -25,7 +25,7 @@ typedef struct {
 } xip_omap_mpu_timer_regs_t;
 
 #define xip_omap_mpu_timer_base(n)                                      \
-((volatile xip_omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE +  \
+((volatile xip_omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE +    \
         (n)*OMAP_MPU_TIMER_OFFSET))
 
 static inline unsigned long xip_omap_mpu_timer_read(int nr)
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 80281c458baf..98dfab651dfc 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -857,6 +857,37 @@ enum omap34xx_index {
         /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
         H16_34XX_SDRC_CKE0,
         H17_34XX_SDRC_CKE1,
+
+        /* MMC1 */
+        N28_3430_MMC1_CLK,
+        M27_3430_MMC1_CMD,
+        N27_3430_MMC1_DAT0,
+        N26_3430_MMC1_DAT1,
+        N25_3430_MMC1_DAT2,
+        P28_3430_MMC1_DAT3,
+        P27_3430_MMC1_DAT4,
+        P26_3430_MMC1_DAT5,
+        R27_3430_MMC1_DAT6,
+        R25_3430_MMC1_DAT7,
+
+        /* MMC2 */
+        AE2_3430_MMC2_CLK,
+        AG5_3430_MMC2_CMD,
+        AH5_3430_MMC2_DAT0,
+        AH4_3430_MMC2_DAT1,
+        AG4_3430_MMC2_DAT2,
+        AF4_3430_MMC2_DAT3,
+
+        /* MMC3 */
+        AF10_3430_MMC3_CLK,
+        AC3_3430_MMC3_CMD,
+        AE11_3430_MMC3_DAT0,
+        AH9_3430_MMC3_DAT1,
+        AF13_3430_MMC3_DAT2,
+        AF13_3430_MMC3_DAT3,
+
+        /* SYS_NIRQ T2 INT1 */
+        AF26_34XX_SYS_NIRQ,
 };
 
 struct omap_mux_cfg {
diff --git a/arch/arm/plat-omap/include/mach/omap-pm.h b/arch/arm/plat-omap/include/mach/omap-pm.h
new file mode 100644
index 000000000000..3ee41d711492
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap-pm.h
@@ -0,0 +1,301 @@
+/*
+ * omap-pm.h - OMAP power management interface
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
+ * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa,
+ * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley,
+ * Richard Woodruff
+ */
+
+#ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H
+#define ASM_ARM_ARCH_OMAP_OMAP_PM_H
+
+#include <linux/device.h>
+#include <linux/cpufreq.h>
+
+#include "powerdomain.h"
+
+/**
+ * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
+ * @rate: target clock rate
+ * @opp_id: OPP ID
+ * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
+ *
+ * Operating performance point data.  Can vary by OMAP chip and board.
+ */
+struct omap_opp {
+        unsigned long rate;
+        u8 opp_id;
+        u16 min_vdd;
+};
+
+extern struct omap_opp *mpu_opps;
+extern struct omap_opp *dsp_opps;
+extern struct omap_opp *l3_opps;
+
+/*
+ * agent_id values for use with omap_pm_set_min_bus_tput():
+ *
+ * OCP_INITIATOR_AGENT is only valid for devices that can act as
+ * initiators -- it represents the device's L3 interconnect
+ * connection.  OCP_TARGET_AGENT represents the device's L4
+ * interconnect connection.
+ */
+#define OCP_TARGET_AGENT                1
+#define OCP_INITIATOR_AGENT             2
+
+/**
+ * omap_pm_if_early_init - OMAP PM init code called before clock fw init
+ * @mpu_opp_table: array ptr to struct omap_opp for MPU
+ * @dsp_opp_table: array ptr to struct omap_opp for DSP
+ * @l3_opp_table : array ptr to struct omap_opp for CORE
+ *
+ * Initialize anything that must be configured before the clock
+ * framework starts.  The "_if_" is to avoid name collisions with the
+ * PM idle-loop code.
+ */
+int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
+                                 struct omap_opp *dsp_opp_table,
+                                 struct omap_opp *l3_opp_table);
+
+/**
+ * omap_pm_if_init - OMAP PM init code called after clock fw init
+ *
+ * The main initialization code.  OPP tables are passed in here.  The
+ * "_if_" is to avoid name collisions with the PM idle-loop code.
+ */
+int __init omap_pm_if_init(void);
+
+/**
+ * omap_pm_if_exit - OMAP PM exit code
+ *
+ * Exit code; currently unused.  The "_if_" is to avoid name
+ * collisions with the PM idle-loop code.
+ */
+void omap_pm_if_exit(void);
+
+/*
+ * Device-driver-originated constraints (via board-*.c files, platform_data)
+ */
+
+
+/**
+ * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency
+ * @dev: struct device * requesting the constraint
+ * @t: maximum MPU wakeup latency in microseconds
+ *
+ * Request that the maximum interrupt latency for the MPU to be no
+ * greater than 't' microseconds. "Interrupt latency" in this case is
+ * defined as the elapsed time from the occurrence of a hardware or
+ * timer interrupt to the time when the device driver's interrupt
+ * service routine has been entered by the MPU.
+ *
+ * It is intended that underlying PM code will use this information to
+ * determine what power state to put the MPU powerdomain into, and
+ * possibly the CORE powerdomain as well, since interrupt handling
+ * code currently runs from SDRAM.  Advanced PM or board*.c code may
+ * also configure interrupt controller priorities, OCP bus priorities,
+ * CPU speed(s), etc.
+ *
+ * This function will not affect device wakeup latency, e.g., time
+ * elapsed from when a device driver enables a hardware device with
+ * clk_enable(), to when the device is ready for register access or
+ * other use.  To control this device wakeup latency, use
+ * set_max_dev_wakeup_lat()
+ *
+ * Multiple calls to set_max_mpu_wakeup_lat() will replace the
+ * previous t value.  To remove the latency target for the MPU, call
+ * with t = -1.
+ *
+ * No return value.
+ */
+void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
+
+
+/**
+ * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device
+ * @dev: struct device * requesting the constraint
+ * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT)
+ * @r: minimum throughput (in KiB/s)
+ *
+ * Request that the minimum data throughput on the OCP interconnect
+ * attached to device 'dev' interconnect agent 'tbus_id' be no less
+ * than 'r' KiB/s.
+ *
+ * It is expected that the OMAP PM or bus code will use this
+ * information to set the interconnect clock to run at the lowest
+ * possible speed that satisfies all current system users.  The PM or
+ * bus code will adjust the estimate based on its model of the bus, so
+ * device driver authors should attempt to specify an accurate
+ * quantity for their device use case, and let the PM or bus code
+ * overestimate the numbers as necessary to handle request/response
+ * latency, other competing users on the system, etc.  On OMAP2/3, if
+ * a driver requests a minimum L4 interconnect speed constraint, the
+ * code will also need to add an minimum L3 interconnect speed
+ * constraint,
+ *
+ * Multiple calls to set_min_bus_tput() will replace the previous rate
+ * value for this device.  To remove the interconnect throughput
+ * restriction for this device, call with r = 0.
+ *
+ * No return value.
+ */
+void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
+
+
+/**
+ * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
+ * @dev: struct device *
+ * @t: maximum device wakeup latency in microseconds
+ *
+ * Request that the maximum amount of time necessary for a device to
+ * become accessible after its clocks are enabled should be no greater
+ * than 't' microseconds.  Specifically, this represents the time from
+ * when a device driver enables device clocks with clk_enable(), to
+ * when the register reads and writes on the device will succeed.
+ * This function should be called before clk_disable() is called,
+ * since the power state transition decision may be made during
+ * clk_disable().
+ *
+ * It is intended that underlying PM code will use this information to
+ * determine what power state to put the powerdomain enclosing this
+ * device into.
+ *
+ * Multiple calls to set_max_dev_wakeup_lat() will replace the
+ * previous wakeup latency values for this device.  To remove the wakeup
+ * latency restriction for this device, call with t = -1.
+ *
+ * No return value.
+ */
+void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t);
+
+
+/**
+ * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
+ * @dev: struct device *
+ * @t: maximum DMA transfer start latency in microseconds
+ *
+ * Request that the maximum system DMA transfer start latency for this
+ * device 'dev' should be no greater than 't' microseconds.  "DMA
+ * transfer start latency" here is defined as the elapsed time from
+ * when a device (e.g., McBSP) requests that a system DMA transfer
+ * start or continue, to the time at which data starts to flow into
+ * that device from the system DMA controller.
+ *
+ * It is intended that underlying PM code will use this information to
+ * determine what power state to put the CORE powerdomain into.
+ *
+ * Since system DMA transfers may not involve the MPU, this function
+ * will not affect MPU wakeup latency.  Use set_max_cpu_lat() to do
+ * so.  Similarly, this function will not affect device wakeup latency
+ * -- use set_max_dev_wakeup_lat() to affect that.
+ *
+ * Multiple calls to set_max_sdma_lat() will replace the previous t
+ * value for this device.  To remove the maximum DMA latency for this
+ * device, call with t = -1.
+ *
+ * No return value.
+ */
+void omap_pm_set_max_sdma_lat(struct device *dev, long t);
+
+
+/*
+ * DSP Bridge-specific constraints
+ */
+
+/**
+ * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
+ *
+ * Intended for use by DSPBridge.  Returns an array of OPP->DSP clock
+ * frequency entries.  The final item in the array should have .rate =
+ * .opp_id = 0.
+ */
+const struct omap_opp *omap_pm_dsp_get_opp_table(void);
+
+/**
+ * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
+ * @opp_id: target DSP OPP ID
+ *
+ * Set a minimum OPP ID for the DSP.  This is intended to be called
+ * only from the DSP Bridge MPU-side driver.  Unfortunately, the only
+ * information that code receives from the DSP/BIOS load estimator is the
+ * target OPP ID; hence, this interface.  No return value.
+ */
+void omap_pm_dsp_set_min_opp(u8 opp_id);
+
+/**
+ * omap_pm_dsp_get_opp - report the current DSP OPP ID
+ *
+ * Report the current OPP for the DSP.  Since on OMAP3, the DSP and
+ * MPU share a single voltage domain, the OPP ID returned back may
+ * represent a higher DSP speed than the OPP requested via
+ * omap_pm_dsp_set_min_opp().
+ *
+ * Returns the current VDD1 OPP ID, or 0 upon error.
+ */
+u8 omap_pm_dsp_get_opp(void);
+
+
+/*
+ * CPUFreq-originated constraint
+ *
+ * In the future, this should be handled by custom OPP clocktype
+ * functions.
+ */
+
+/**
+ * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
+ *
+ * Provide a frequency table usable by CPUFreq for the current chip/board.
+ * Returns a pointer to a struct cpufreq_frequency_table array or NULL
+ * upon error.
+ */
+struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
+
+/**
+ * omap_pm_cpu_set_freq - set the current minimum MPU frequency
+ * @f: MPU frequency in Hz
+ *
+ * Set the current minimum CPU frequency.  The actual CPU frequency
+ * used could end up higher if the DSP requested a higher OPP.
+ * Intended to be called by plat-omap/cpu_omap.c:omap_target().  No
+ * return value.
+ */
+void omap_pm_cpu_set_freq(unsigned long f);
+
+/**
+ * omap_pm_cpu_get_freq - report the current CPU frequency
+ *
+ * Returns the current MPU frequency, or 0 upon error.
+ */
+unsigned long omap_pm_cpu_get_freq(void);
+
+
+/*
+ * Device context loss tracking
+ */
+
+/**
+ * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx
+ * @dev: struct device *
+ *
+ * This function returns the number of times that the device @dev has
+ * lost its internal context.  This generally occurs on a powerdomain
+ * transition to OFF.  Drivers use this as an optimization to avoid restoring
+ * context if the device hasn't lost it.  To use, drivers should initially
+ * call this in their context save functions and store the result.  Early in
+ * the driver's context restore function, the driver should call this function
+ * again, and compare the result to the stored counter.  If they differ, the
+ * driver must restore device context.   If the number of context losses
+ * exceeds the maximum positive integer, the function will wrap to 0 and
+ * continue counting.  Returns the number of context losses for this device,
+ * or -EINVAL upon error.
+ */
+int omap_pm_get_dev_context_loss_count(struct device *dev);
+
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/mach/omap44xx.h
index 15dec7f1c7c0..b3ba5ac7b4a4 100644
--- a/arch/arm/plat-omap/include/mach/omap44xx.h
+++ b/arch/arm/plat-omap/include/mach/omap44xx.h
@@ -33,14 +33,14 @@
 #define IRQ_SIR_IRQ                     0x0040
 #define OMAP44XX_GIC_DIST_BASE          0x48241000
 #define OMAP44XX_GIC_CPU_BASE           0x48240100
-#define OMAP44XX_VA_GIC_CPU_BASE        IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
+#define OMAP44XX_VA_GIC_CPU_BASE        OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
 #define OMAP44XX_SCU_BASE               0x48240000
-#define OMAP44XX_VA_SCU_BASE            IO_ADDRESS(OMAP44XX_SCU_BASE)
+#define OMAP44XX_VA_SCU_BASE            OMAP2_IO_ADDRESS(OMAP44XX_SCU_BASE)
 #define OMAP44XX_LOCAL_TWD_BASE         0x48240600
-#define OMAP44XX_VA_LOCAL_TWD_BASE      IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
+#define OMAP44XX_VA_LOCAL_TWD_BASE      OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
 #define OMAP44XX_LOCAL_TWD_SIZE         0x00000100
 #define OMAP44XX_WKUPGEN_BASE           0x48281000
-#define OMAP44XX_VA_WKUPGEN_BASE        IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
+#define OMAP44XX_VA_WKUPGEN_BASE        OMAP2_IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
 
 #endif /* __ASM_ARCH_OMAP44XX_H */
 
diff --git a/arch/arm/plat-omap/include/mach/omap_device.h b/arch/arm/plat-omap/include/mach/omap_device.h
new file mode 100644
index 000000000000..bd0e136db337
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap_device.h
@@ -0,0 +1,141 @@
+/*
+ * omap_device headers
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * Developed in collaboration with (alphabetical order): Benoit
+ * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
+ * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
+ * Woodruff
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Eventually this type of functionality should either be
+ * a) implemented via arch-specific pointers in platform_device
+ * or
+ * b) implemented as a proper omap_bus/omap_device in Linux, no more
+ *    platform_device
+ *
+ * omap_device differs from omap_hwmod in that it includes external
+ * (e.g., board- and system-level) integration details.  omap_hwmod
+ * stores hardware data that is invariant for a given OMAP chip.
+ *
+ * To do:
+ * - GPIO integration
+ * - regulator integration
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <mach/omap_hwmod.h>
+
+/* omap_device._state values */
+#define OMAP_DEVICE_STATE_UNKNOWN       0
+#define OMAP_DEVICE_STATE_ENABLED       1
+#define OMAP_DEVICE_STATE_IDLE          2
+#define OMAP_DEVICE_STATE_SHUTDOWN      3
+
+/**
+ * struct omap_device - omap_device wrapper for platform_devices
+ * @pdev: platform_device
+ * @hwmods: (one .. many per omap_device)
+ * @hwmods_cnt: ARRAY_SIZE() of @hwmods
+ * @pm_lats: ptr to an omap_device_pm_latency table
+ * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
+ * @pm_lat_level: array index of the last odpl entry executed - -1 if never
+ * @dev_wakeup_lat: dev wakeup latency in microseconds
+ * @_dev_wakeup_lat_limit: dev wakeup latency limit in usec - set by OMAP PM
+ * @_state: one of OMAP_DEVICE_STATE_* (see above)
+ * @flags: device flags
+ *
+ * Integrates omap_hwmod data into Linux platform_device.
+ *
+ * Field names beginning with underscores are for the internal use of
+ * the omap_device code.
+ *
+ */
+struct omap_device {
+        struct platform_device          pdev;
+        struct omap_hwmod               **hwmods;
+        struct omap_device_pm_latency   *pm_lats;
+        u32                             dev_wakeup_lat;
+        u32                             _dev_wakeup_lat_limit;
+        u8                              pm_lats_cnt;
+        s8                              pm_lat_level;
+        u8                              hwmods_cnt;
+        u8                              _state;
+};
+
+/* Device driver interface (call via platform_data fn ptrs) */
+
+int omap_device_enable(struct platform_device *pdev);
+int omap_device_idle(struct platform_device *pdev);
+int omap_device_shutdown(struct platform_device *pdev);
+
+/* Core code interface */
+
+int omap_device_count_resources(struct omap_device *od);
+int omap_device_fill_resources(struct omap_device *od, struct resource *res);
+
+struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
+                                      struct omap_hwmod *oh, void *pdata,
+                                      int pdata_len,
+                                      struct omap_device_pm_latency *pm_lats,
+                                      int pm_lats_cnt);
+
+struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
+                                         struct omap_hwmod **oh, int oh_cnt,
+                                         void *pdata, int pdata_len,
+                                         struct omap_device_pm_latency *pm_lats,
+                                         int pm_lats_cnt);
+
+int omap_device_register(struct omap_device *od);
+
+/* OMAP PM interface */
+int omap_device_align_pm_lat(struct platform_device *pdev,
+                             u32 new_wakeup_lat_limit);
+struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
+
+/* Other */
+
+int omap_device_idle_hwmods(struct omap_device *od);
+int omap_device_enable_hwmods(struct omap_device *od);
+
+int omap_device_disable_clocks(struct omap_device *od);
+int omap_device_enable_clocks(struct omap_device *od);
+
+
+/*
+ * Entries should be kept in latency order ascending
+ *
+ * deact_lat is the maximum number of microseconds required to complete
+ * deactivate_func() at the device's slowest OPP.
+ *
+ * act_lat is the maximum number of microseconds required to complete
+ * activate_func() at the device's slowest OPP.
+ *
+ * This will result in some suboptimal power management decisions at fast
+ * OPPs, but avoids having to recompute all device power management decisions
+ * if the system shifts from a fast OPP to a slow OPP (in order to meet
+ * latency requirements).
+ *
+ * XXX should deactivate_func/activate_func() take platform_device pointers
+ * rather than omap_device pointers?
+ */
+struct omap_device_pm_latency {
+        u32 deactivate_lat;
+        int (*deactivate_func)(struct omap_device *od);
+        u32 activate_lat;
+        int (*activate_func)(struct omap_device *od);
+};
+
+
+#endif
+
diff --git a/arch/arm/plat-omap/include/mach/omap_hwmod.h b/arch/arm/plat-omap/include/mach/omap_hwmod.h
new file mode 100644
index 000000000000..1f79c20e2929
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap_hwmod.h
@@ -0,0 +1,447 @@
+/*
+ * omap_hwmod macros, structures
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * Created in collaboration with (alphabetical order): Benoit Cousson,
+ * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
+ * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * These headers and macros are used to define OMAP on-chip module
+ * data and their integration with other OMAP modules and Linux.
+ *
+ * References:
+ * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
+ * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
+ * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
+ * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
+ * - Open Core Protocol Specification 2.2
+ *
+ * To do:
+ * - add interconnect error log structures
+ * - add pinmuxing
+ * - init_conn_id_bit (CONNID_BIT_VECTOR)
+ * - implement default hwmod SMS/SDRC flags?
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
+
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+
+#include <mach/cpu.h>
+
+struct omap_device;
+
+/* OCP SYSCONFIG bit shifts/masks */
+#define SYSC_MIDLEMODE_SHIFT            12
+#define SYSC_MIDLEMODE_MASK             (0x3 << SYSC_MIDLEMODE_SHIFT)
+#define SYSC_CLOCKACTIVITY_SHIFT        8
+#define SYSC_CLOCKACTIVITY_MASK         (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
+#define SYSC_SIDLEMODE_SHIFT            3
+#define SYSC_SIDLEMODE_MASK             (0x3 << SYSC_SIDLEMODE_SHIFT)
+#define SYSC_ENAWAKEUP_SHIFT            2
+#define SYSC_ENAWAKEUP_MASK             (1 << SYSC_ENAWAKEUP_SHIFT)
+#define SYSC_SOFTRESET_SHIFT            1
+#define SYSC_SOFTRESET_MASK             (1 << SYSC_SOFTRESET_SHIFT)
+
+/* OCP SYSSTATUS bit shifts/masks */
+#define SYSS_RESETDONE_SHIFT            0
+#define SYSS_RESETDONE_MASK             (1 << SYSS_RESETDONE_SHIFT)
+
+/* Master standby/slave idle mode flags */
+#define HWMOD_IDLEMODE_FORCE            (1 << 0)
+#define HWMOD_IDLEMODE_NO               (1 << 1)
+#define HWMOD_IDLEMODE_SMART            (1 << 2)
+
+
+/**
+ * struct omap_hwmod_dma_info - MPU address space handled by the hwmod
+ * @name: name of the DMA channel (module local name)
+ * @dma_ch: DMA channel ID
+ *
+ * @name should be something short, e.g., "tx" or "rx".  It is for use
+ * by platform_get_resource_byname().  It is defined locally to the
+ * hwmod.
+ */
+struct omap_hwmod_dma_info {
+        const char      *name;
+        u16             dma_ch;
+};
+
+/**
+ * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
+ * @role: "sys", "32k", "tv", etc -- for use in clk_get()
+ * @clkdev_dev_id: opt clock: clkdev dev_id string
+ * @clkdev_con_id: opt clock: clkdev con_id string
+ * @_clk: pointer to the struct clk (filled in at runtime)
+ *
+ * The module's interface clock and main functional clock should not
+ * be added as optional clocks.
+ */
+struct omap_hwmod_opt_clk {
+        const char      *role;
+        const char      *clkdev_dev_id;
+        const char      *clkdev_con_id;
+        struct clk      *_clk;
+};
+
+
+/* omap_hwmod_omap2_firewall.flags bits */
+#define OMAP_FIREWALL_L3                (1 << 0)
+#define OMAP_FIREWALL_L4                (1 << 1)
+
+/**
+ * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
+ * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
+ * @l4_fw_region: L4 firewall region ID
+ * @l4_prot_group: L4 protection group ID
+ * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
+ */
+struct omap_hwmod_omap2_firewall {
+        u8 l3_perm_bit;
+        u8 l4_fw_region;
+        u8 l4_prot_group;
+        u8 flags;
+};
+
+
+/*
+ * omap_hwmod_addr_space.flags bits
+ *
+ * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
+ * ADDR_TYPE_RT: Address space contains module register target data.
+ */
+#define ADDR_MAP_ON_INIT        (1 << 0)
+#define ADDR_TYPE_RT            (1 << 1)
+
+/**
+ * struct omap_hwmod_addr_space - MPU address space handled by the hwmod
+ * @pa_start: starting physical address
+ * @pa_end: ending physical address
+ * @flags: (see omap_hwmod_addr_space.flags macros above)
+ *
+ * Address space doesn't necessarily follow physical interconnect
+ * structure.  GPMC is one example.
+ */
+struct omap_hwmod_addr_space {
+        u32 pa_start;
+        u32 pa_end;
+        u8 flags;
+};
+
+
+/*
+ * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
+ * interface to interact with the hwmod.  Used to add sleep dependencies
+ * when the module is enabled or disabled.
+ */
+#define OCP_USER_MPU                    (1 << 0)
+#define OCP_USER_SDMA                   (1 << 1)
+
+/* omap_hwmod_ocp_if.flags bits */
+#define OCPIF_HAS_IDLEST                (1 << 0)
+#define OCPIF_SWSUP_IDLE                (1 << 1)
+#define OCPIF_CAN_BURST                 (1 << 2)
+
+/**
+ * struct omap_hwmod_ocp_if - OCP interface data
+ * @master: struct omap_hwmod that initiates OCP transactions on this link
+ * @slave: struct omap_hwmod that responds to OCP transactions on this link
+ * @addr: address space associated with this link
+ * @clkdev_dev_id: interface clock: clkdev dev_id string
+ * @clkdev_con_id: interface clock: clkdev con_id string
+ * @_clk: pointer to the interface struct clk (filled in at runtime)
+ * @fw: interface firewall data
+ * @addr_cnt: ARRAY_SIZE(@addr)
+ * @width: OCP data width
+ * @thread_cnt: number of threads
+ * @max_burst_len: maximum burst length in @width sized words (0 if unlimited)
+ * @user: initiators using this interface (see OCP_USER_* macros above)
+ * @flags: OCP interface flags (see OCPIF_* macros above)
+ *
+ * It may also be useful to add a tag_cnt field for OCP2.x devices.
+ *
+ * Parameter names beginning with an underscore are managed internally by
+ * the omap_hwmod code and should not be set during initialization.
+ */
+struct omap_hwmod_ocp_if {
+        struct omap_hwmod               *master;
+        struct omap_hwmod               *slave;
+        struct omap_hwmod_addr_space    *addr;
+        const char                      *clkdev_dev_id;
+        const char                      *clkdev_con_id;
+        struct clk                      *_clk;
+        union {
+                struct omap_hwmod_omap2_firewall omap2;
+        }                               fw;
+        u8                              addr_cnt;
+        u8                              width;
+        u8                              thread_cnt;
+        u8                              max_burst_len;
+        u8                              user;
+        u8                              flags;
+};
+
+
+/* Macros for use in struct omap_hwmod_sysconfig */
+
+/* Flags for use in omap_hwmod_sysconfig.idlemodes */
+#define MASTER_STANDBY_SHIFT    2
+#define SLAVE_IDLE_SHIFT        0
+#define SIDLE_FORCE             (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
+#define SIDLE_NO                (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
+#define SIDLE_SMART             (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
+#define MSTANDBY_FORCE          (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
+#define MSTANDBY_NO             (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
+#define MSTANDBY_SMART          (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
+
+/* omap_hwmod_sysconfig.sysc_flags capability flags */
+#define SYSC_HAS_AUTOIDLE       (1 << 0)
+#define SYSC_HAS_SOFTRESET      (1 << 1)
+#define SYSC_HAS_ENAWAKEUP      (1 << 2)
+#define SYSC_HAS_EMUFREE        (1 << 3)
+#define SYSC_HAS_CLOCKACTIVITY  (1 << 4)
+#define SYSC_HAS_SIDLEMODE      (1 << 5)
+#define SYSC_HAS_MIDLEMODE      (1 << 6)
+#define SYSS_MISSING            (1 << 7)
+
+/* omap_hwmod_sysconfig.clockact flags */
+#define CLOCKACT_TEST_BOTH      0x0
+#define CLOCKACT_TEST_MAIN      0x1
+#define CLOCKACT_TEST_ICLK      0x2
+#define CLOCKACT_TEST_NONE      0x3
+
+/**
+ * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data
+ * @rev_offs: IP block revision register offset (from module base addr)
+ * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
+ * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
+ * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
+ * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
+ * @clockact: the default value of the module CLOCKACTIVITY bits
+ *
+ * @clockact describes to the module which clocks are likely to be
+ * disabled when the PRCM issues its idle request to the module.  Some
+ * modules have separate clockdomains for the interface clock and main
+ * functional clock, and can check whether they should acknowledge the
+ * idle request based on the internal module functionality that has
+ * been associated with the clocks marked in @clockact.  This field is
+ * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
+ *
+ */
+struct omap_hwmod_sysconfig {
+        u16 rev_offs;
+        u16 sysc_offs;
+        u16 syss_offs;
+        u8 idlemodes;
+        u8 sysc_flags;
+        u8 clockact;
+};
+
+/**
+ * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
+ * @module_offs: PRCM submodule offset from the start of the PRM/CM
+ * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
+ * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
+ * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
+ * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
+ * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
+ *
+ * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
+ * WKEN, GRPSEL registers.  In an ideal world, no extra information
+ * would be needed for IDLEST information, but alas, there are some
+ * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
+ * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
+ */
+struct omap_hwmod_omap2_prcm {
+        s16 module_offs;
+        u8 prcm_reg_id;
+        u8 module_bit;
+        u8 idlest_reg_id;
+        u8 idlest_idle_bit;
+        u8 idlest_stdby_bit;
+};
+
+
+/**
+ * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
+ * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2
+ * @device_offs: device register offset from @module_offs
+ * @submodule_wkdep_bit: bit shift of the WKDEP range
+ */
+struct omap_hwmod_omap4_prcm {
+        u32 module_offs;
+        u16 device_offs;
+        u8 submodule_wkdep_bit;
+};
+
+
+/*
+ * omap_hwmod.flags definitions
+ *
+ * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
+ *     of idle, rather than relying on module smart-idle
+ * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
+ *     of standby, rather than relying on module smart-standby
+ * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
+ *     SDRAM controller, etc.
+ * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
+ *     controller, etc.
+ * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
+ */
+#define HWMOD_SWSUP_SIDLE                       (1 << 0)
+#define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
+#define HWMOD_INIT_NO_RESET                     (1 << 2)
+#define HWMOD_INIT_NO_IDLE                      (1 << 3)
+#define HWMOD_SET_DEFAULT_CLOCKACT              (1 << 4)
+
+/*
+ * omap_hwmod._int_flags definitions
+ * These are for internal use only and are managed by the omap_hwmod code.
+ *
+ * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
+ * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
+ * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
+ */
+#define _HWMOD_NO_MPU_PORT                      (1 << 0)
+#define _HWMOD_WAKEUP_ENABLED                   (1 << 1)
+#define _HWMOD_SYSCONFIG_LOADED                 (1 << 2)
+
+/*
+ * omap_hwmod._state definitions
+ *
+ * INITIALIZED: reset (optionally), initialized, enabled, disabled
+ *              (optionally)
+ *
+ *
+ */
+#define _HWMOD_STATE_UNKNOWN                    0
+#define _HWMOD_STATE_REGISTERED                 1
+#define _HWMOD_STATE_CLKS_INITED                2
+#define _HWMOD_STATE_INITIALIZED                3
+#define _HWMOD_STATE_ENABLED                    4
+#define _HWMOD_STATE_IDLE                       5
+#define _HWMOD_STATE_DISABLED                   6
+
+/**
+ * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
+ * @name: name of the hwmod
+ * @od: struct omap_device currently associated with this hwmod (internal use)
+ * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
+ * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
+ * @prcm: PRCM data pertaining to this hwmod
+ * @clkdev_dev_id: main clock: clkdev dev_id string
+ * @clkdev_con_id: main clock: clkdev con_id string
+ * @_clk: pointer to the main struct clk (filled in at runtime)
+ * @opt_clks: other device clocks that drivers can request (0..*)
+ * @masters: ptr to array of OCP ifs that this hwmod can initiate on
+ * @slaves: ptr to array of OCP ifs that this hwmod can respond on
+ * @sysconfig: device SYSCONFIG/SYSSTATUS register data
+ * @dev_attr: arbitrary device attributes that can be passed to the driver
+ * @_sysc_cache: internal-use hwmod flags
+ * @_rt_va: cached register target start address (internal use)
+ * @_mpu_port_index: cached MPU register target slave ID (internal use)
+ * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
+ * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
+ * @mpu_irqs_cnt: number of @mpu_irqs
+ * @sdma_chs_cnt: number of @sdma_chs
+ * @opt_clks_cnt: number of @opt_clks
+ * @master_cnt: number of @master entries
+ * @slaves_cnt: number of @slave entries
+ * @response_lat: device OCP response latency (in interface clock cycles)
+ * @_int_flags: internal-use hwmod flags
+ * @_state: internal-use hwmod state
+ * @flags: hwmod flags (documented below)
+ * @omap_chip: OMAP chips this hwmod is present on
+ * @node: list node for hwmod list (internal use)
+ *
+ * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main
+ * clock," which for our purposes is defined as "the functional clock needed
+ * for register accesses to complete."  Modules may not have a main clock if
+ * the interface clock also serves as a main clock.
+ *
+ * Parameter names beginning with an underscore are managed internally by
+ * the omap_hwmod code and should not be set during initialization.
+ */
+struct omap_hwmod {
+        const char                      *name;
+        struct omap_device              *od;
+        u8                              *mpu_irqs;
+        struct omap_hwmod_dma_info      *sdma_chs;
+        union {
+                struct omap_hwmod_omap2_prcm omap2;
+                struct omap_hwmod_omap4_prcm omap4;
+        }                               prcm;
+        const char                      *clkdev_dev_id;
+        const char                      *clkdev_con_id;
+        struct clk                      *_clk;
+        struct omap_hwmod_opt_clk       *opt_clks;
+        struct omap_hwmod_ocp_if        **masters; /* connect to *_IA */
+        struct omap_hwmod_ocp_if        **slaves;  /* connect to *_TA */
+        struct omap_hwmod_sysconfig     *sysconfig;
+        void                            *dev_attr;
+        u32                             _sysc_cache;
+        void __iomem                    *_rt_va;
+        struct list_head                node;
+        u16                             flags;
+        u8                              _mpu_port_index;
+        u8                              msuspendmux_reg_id;
+        u8                              msuspendmux_shift;
+        u8                              response_lat;
+        u8                              mpu_irqs_cnt;
+        u8                              sdma_chs_cnt;
+        u8                              opt_clks_cnt;
+        u8                              masters_cnt;
+        u8                              slaves_cnt;
+        u8                              hwmods_cnt;
+        u8                              _int_flags;
+        u8                              _state;
+        const struct omap_chip_id       omap_chip;
+};
+
+int omap_hwmod_init(struct omap_hwmod **ohs);
+int omap_hwmod_register(struct omap_hwmod *oh);
+int omap_hwmod_unregister(struct omap_hwmod *oh);
+struct omap_hwmod *omap_hwmod_lookup(const char *name);
+int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh));
+int omap_hwmod_late_init(void);
+
+int omap_hwmod_enable(struct omap_hwmod *oh);
+int omap_hwmod_idle(struct omap_hwmod *oh);
+int omap_hwmod_shutdown(struct omap_hwmod *oh);
+
+int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
+int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
+
+int omap_hwmod_reset(struct omap_hwmod *oh);
+void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
+
+void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs);
+u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs);
+
+int omap_hwmod_count_resources(struct omap_hwmod *oh);
+int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
+
+struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
+
+int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
+                                 struct omap_hwmod *init_oh);
+int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
+                                 struct omap_hwmod *init_oh);
+
+int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
+int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
+int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
+int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
+
+int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
+int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h
index 69c9e675d8ee..6271d8556a40 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -117,6 +117,13 @@ struct powerdomain {
 
         struct list_head node;
 
+        int state;
+        unsigned state_counter[4];
+
+#ifdef CONFIG_PM_DEBUG
+        s64 timer;
+        s64 state_timer[4];
+#endif
 };
 
 
@@ -126,7 +133,8 @@ int pwrdm_register(struct powerdomain *pwrdm);
 int pwrdm_unregister(struct powerdomain *pwrdm);
 struct powerdomain *pwrdm_lookup(const char *name);
 
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm));
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+                        void *user);
 
 int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
 int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
@@ -164,4 +172,9 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
 
 int pwrdm_wait_transition(struct powerdomain *pwrdm);
 
+int pwrdm_state_switch(struct powerdomain *pwrdm);
+int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
+int pwrdm_pre_transition(void);
+int pwrdm_post_transition(void);
+
 #endif
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index 0be18e4ff182..1c09c78a48f2 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -21,19 +21,28 @@
 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
 
 #define SDRC_SYSCONFIG          0x010
+#define SDRC_CS_CFG             0x040
+#define SDRC_SHARING            0x044
+#define SDRC_ERR_TYPE           0x04C
 #define SDRC_DLLA_CTRL          0x060
 #define SDRC_DLLA_STATUS        0x064
 #define SDRC_DLLB_CTRL          0x068
 #define SDRC_DLLB_STATUS        0x06C
 #define SDRC_POWER              0x070
+#define SDRC_MCFG_0             0x080
 #define SDRC_MR_0               0x084
+#define SDRC_EMR2_0             0x08c
 #define SDRC_ACTIM_CTRL_A_0     0x09c
 #define SDRC_ACTIM_CTRL_B_0     0x0a0
 #define SDRC_RFR_CTRL_0         0x0a4
+#define SDRC_MANUAL_0           0x0a8
+#define SDRC_MCFG_1             0x0B0
 #define SDRC_MR_1               0x0B4
+#define SDRC_EMR2_1             0x0BC
 #define SDRC_ACTIM_CTRL_A_1     0x0C4
 #define SDRC_ACTIM_CTRL_B_1     0x0C8
 #define SDRC_RFR_CTRL_1         0x0D4
+#define SDRC_MANUAL_1           0x0D8
 
 /*
  * These values represent the number of memory clock cycles between
@@ -71,11 +80,11 @@
  */
 
 #define OMAP242X_SMS_REGADDR(reg)                                       \
-                        (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
+                        (void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
 #define OMAP243X_SMS_REGADDR(reg)                                       \
-                        (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
+                        (void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
 #define OMAP343X_SMS_REGADDR(reg)                                       \
-                        (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
+                        (void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
 
 /* SMS register offsets - read/write with sms_{read,write}_reg() */
 
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
index def0529c75eb..e249186d26e2 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARCH_SERIAL_H
 #define __ASM_ARCH_SERIAL_H
 
+#include <linux/init.h>
+
 #if defined(CONFIG_ARCH_OMAP1)
 /* OMAP1 serial ports */
 #define OMAP_UART1_BASE         0xfffb0000
@@ -53,6 +55,7 @@
                         })
 
 #ifndef __ASSEMBLER__
+extern void __init omap_serial_early_init(void);
 extern void omap_serial_init(void);
 extern int omap_uart_can_sleep(void);
 extern void omap_uart_check_wakeup(void);
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/mach/system.h
index 1060e345423b..ed8ec7477261 100644
--- a/arch/arm/plat-omap/include/mach/system.h
+++ b/arch/arm/plat-omap/include/mach/system.h
@@ -1,6 +1,6 @@
 /*
  * Copied from arch/arm/mach-sa1100/include/mach/system.h
- * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
+ * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
  */
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index 9b42d72d96cf..b6defa23e77e 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -30,8 +30,8 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
 {
 #ifdef CONFIG_ARCH_OMAP1
         if (cpu_class_is_omap1()) {
-                if (BETWEEN(p, IO_PHYS, IO_SIZE))
-                        return XLATE(p, IO_PHYS, IO_VIRT);
+                if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
+                        return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
         }
         if (cpu_is_omap730()) {
                 if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE))
@@ -132,3 +132,61 @@ void omap_iounmap(volatile void __iomem *addr)
                 __iounmap(addr);
 }
 EXPORT_SYMBOL(omap_iounmap);
+
+/*
+ * NOTE: Please use ioremap + __raw_read/write where possible instead of these
+ */
+
+u8 omap_readb(u32 pa)
+{
+        if (cpu_class_is_omap1())
+                return __raw_readb(OMAP1_IO_ADDRESS(pa));
+        else
+                return __raw_readb(OMAP2_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readb);
+
+u16 omap_readw(u32 pa)
+{
+        if (cpu_class_is_omap1())
+                return __raw_readw(OMAP1_IO_ADDRESS(pa));
+        else
+                return __raw_readw(OMAP2_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readw);
+
+u32 omap_readl(u32 pa)
+{
+        if (cpu_class_is_omap1())
+                return __raw_readl(OMAP1_IO_ADDRESS(pa));
+        else
+                return __raw_readl(OMAP2_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readl);
+
+void omap_writeb(u8 v, u32 pa)
+{
+        if (cpu_class_is_omap1())
+                __raw_writeb(v, OMAP1_IO_ADDRESS(pa));
+        else
+                __raw_writeb(v, OMAP2_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writeb);
+
+void omap_writew(u16 v, u32 pa)
+{
+        if (cpu_class_is_omap1())
+                __raw_writew(v, OMAP1_IO_ADDRESS(pa));
+        else
+                __raw_writew(v, OMAP2_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writew);
+
+void omap_writel(u32 v, u32 pa)
+{
+        if (cpu_class_is_omap1())
+                __raw_writel(v, OMAP1_IO_ADDRESS(pa));
+        else
+                __raw_writel(v, OMAP2_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writel);
diff --git a/arch/arm/plat-omap/iommu-debug.c b/arch/arm/plat-omap/iommu-debug.c
new file mode 100644
index 000000000000..c799b3b0d709
--- /dev/null
+++ b/arch/arm/plat-omap/iommu-debug.c
@@ -0,0 +1,415 @@
+/*
+ * omap iommu: debugfs interface
+ *
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/uaccess.h>
+#include <linux/platform_device.h>
+#include <linux/debugfs.h>
+
+#include <mach/iommu.h>
+#include <mach/iovmm.h>
+
+#include "iopgtable.h"
+
+#define MAXCOLUMN 100 /* for short messages */
+
+static DEFINE_MUTEX(iommu_debug_lock);
+
+static struct dentry *iommu_debug_root;
+
+static ssize_t debug_read_ver(struct file *file, char __user *userbuf,
+                              size_t count, loff_t *ppos)
+{
+        u32 ver = iommu_arch_version();
+        char buf[MAXCOLUMN], *p = buf;
+
+        p += sprintf(p, "H/W version: %d.%d\n", (ver >> 4) & 0xf , ver & 0xf);
+
+        return simple_read_from_buffer(userbuf, count, ppos, buf, p - buf);
+}
+
+static ssize_t debug_read_regs(struct file *file, char __user *userbuf,
+                               size_t count, loff_t *ppos)
+{
+        struct iommu *obj = file->private_data;
+        char *p, *buf;
+        ssize_t bytes;
+
+        buf = kmalloc(count, GFP_KERNEL);
+        if (!buf)
+                return -ENOMEM;
+        p = buf;
+
+        mutex_lock(&iommu_debug_lock);
+
+        bytes = iommu_dump_ctx(obj, p, count);
+        bytes = simple_read_from_buffer(userbuf, count, ppos, buf, bytes);
+
+        mutex_unlock(&iommu_debug_lock);
+        kfree(buf);
+
+        return bytes;
+}
+
+static ssize_t debug_read_tlb(struct file *file, char __user *userbuf,
+                              size_t count, loff_t *ppos)
+{
+        struct iommu *obj = file->private_data;
+        char *p, *buf;
+        ssize_t bytes, rest;
+
+        buf = kmalloc(count, GFP_KERNEL);
+        if (!buf)
+                return -ENOMEM;
+        p = buf;
+
+        mutex_lock(&iommu_debug_lock);
+
+        p += sprintf(p, "%8s %8s\n", "cam:", "ram:");
+        p += sprintf(p, "-----------------------------------------\n");
+        rest = count - (p - buf);
+        p += dump_tlb_entries(obj, p, rest);
+
+        bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf);
+
+        mutex_unlock(&iommu_debug_lock);
+        kfree(buf);
+
+        return bytes;
+}
+
+static ssize_t debug_write_pagetable(struct file *file,
+                     const char __user *userbuf, size_t count, loff_t *ppos)
+{
+        struct iotlb_entry e;
+        struct cr_regs cr;
+        int err;
+        struct iommu *obj = file->private_data;
+        char buf[MAXCOLUMN], *p = buf;
+
+        count = min(count, sizeof(buf));
+
+        mutex_lock(&iommu_debug_lock);
+        if (copy_from_user(p, userbuf, count)) {
+                mutex_unlock(&iommu_debug_lock);
+                return -EFAULT;
+        }
+
+        sscanf(p, "%x %x", &cr.cam, &cr.ram);
+        if (!cr.cam || !cr.ram) {
+                mutex_unlock(&iommu_debug_lock);
+                return -EINVAL;
+        }
+
+        iotlb_cr_to_e(&cr, &e);
+        err = iopgtable_store_entry(obj, &e);
+        if (err)
+                dev_err(obj->dev, "%s: fail to store cr\n", __func__);
+
+        mutex_unlock(&iommu_debug_lock);
+        return count;
+}
+
+#define dump_ioptable_entry_one(lv, da, val)                    \
+        ({                                                      \
+                int __err = 0;                                  \
+                ssize_t bytes;                                  \
+                const int maxcol = 22;                          \
+                const char *str = "%d: %08x %08x\n";            \
+                bytes = snprintf(p, maxcol, str, lv, da, val);  \
+                p += bytes;                                     \
+                len -= bytes;                                   \
+                if (len < maxcol)                               \
+                        __err = -ENOMEM;                        \
+                __err;                                          \
+        })
+
+static ssize_t dump_ioptable(struct iommu *obj, char *buf, ssize_t len)
+{
+        int i;
+        u32 *iopgd;
+        char *p = buf;
+
+        spin_lock(&obj->page_table_lock);
+
+        iopgd = iopgd_offset(obj, 0);
+        for (i = 0; i < PTRS_PER_IOPGD; i++, iopgd++) {
+                int j, err;
+                u32 *iopte;
+                u32 da;
+
+                if (!*iopgd)
+                        continue;
+
+                if (!(*iopgd & IOPGD_TABLE)) {
+                        da = i << IOPGD_SHIFT;
+
+                        err = dump_ioptable_entry_one(1, da, *iopgd);
+                        if (err)
+                                goto out;
+                        continue;
+                }
+
+                iopte = iopte_offset(iopgd, 0);
+
+                for (j = 0; j < PTRS_PER_IOPTE; j++, iopte++) {
+                        if (!*iopte)
+                                continue;
+
+                        da = (i << IOPGD_SHIFT) + (j << IOPTE_SHIFT);
+                        err = dump_ioptable_entry_one(2, da, *iopgd);
+                        if (err)
+                                goto out;
+                }
+        }
+out:
+        spin_unlock(&obj->page_table_lock);
+
+        return p - buf;
+}
+
+static ssize_t debug_read_pagetable(struct file *file, char __user *userbuf,
+                                    size_t count, loff_t *ppos)
+{
+        struct iommu *obj = file->private_data;
+        char *p, *buf;
+        size_t bytes;
+
+        buf = (char *)__get_free_page(GFP_KERNEL);
+        if (!buf)
+                return -ENOMEM;
+        p = buf;
+
+        p += sprintf(p, "L: %8s %8s\n", "da:", "pa:");
+        p += sprintf(p, "-----------------------------------------\n");
+
+        mutex_lock(&iommu_debug_lock);
+
+        bytes = PAGE_SIZE - (p - buf);
+        p += dump_ioptable(obj, p, bytes);
+
+        bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf);
+
+        mutex_unlock(&iommu_debug_lock);
+        free_page((unsigned long)buf);
+
+        return bytes;
+}
+
+static ssize_t debug_read_mmap(struct file *file, char __user *userbuf,
+                               size_t count, loff_t *ppos)
+{
+        struct iommu *obj = file->private_data;
+        char *p, *buf;
+        struct iovm_struct *tmp;
+        int uninitialized_var(i);
+        ssize_t bytes;
+
+        buf = (char *)__get_free_page(GFP_KERNEL);
+        if (!buf)
+                return -ENOMEM;
+        p = buf;
+
+        p += sprintf(p, "%-3s %-8s %-8s %6s %8s\n",
+                     "No", "start", "end", "size", "flags");
+        p += sprintf(p, "-------------------------------------------------\n");
+
+        mutex_lock(&iommu_debug_lock);
+
+        list_for_each_entry(tmp, &obj->mmap, list) {
+                size_t len;
+                const char *str = "%3d %08x-%08x %6x %8x\n";
+                const int maxcol = 39;
+
+                len = tmp->da_end - tmp->da_start;
+                p += snprintf(p, maxcol, str,
+                              i, tmp->da_start, tmp->da_end, len, tmp->flags);
+
+                if (PAGE_SIZE - (p - buf) < maxcol)
+                        break;
+                i++;
+        }
+
+        bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf);
+
+        mutex_unlock(&iommu_debug_lock);
+        free_page((unsigned long)buf);
+
+        return bytes;
+}
+
+static ssize_t debug_read_mem(struct file *file, char __user *userbuf,
+                              size_t count, loff_t *ppos)
+{
+        struct iommu *obj = file->private_data;
+        char *p, *buf;
+        struct iovm_struct *area;
+        ssize_t bytes;
+
+        count = min_t(ssize_t, count, PAGE_SIZE);
+
+        buf = (char *)__get_free_page(GFP_KERNEL);
+        if (!buf)
+                return -ENOMEM;
+        p = buf;
+
+        mutex_lock(&iommu_debug_lock);
+
+        area = find_iovm_area(obj, (u32)ppos);
+        if (IS_ERR(area)) {
+                bytes = -EINVAL;
+                goto err_out;
+        }
+        memcpy(p, area->va, count);
+        p += count;
+
+        bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf);
+err_out:
+        mutex_unlock(&iommu_debug_lock);
+        free_page((unsigned long)buf);
+
+        return bytes;
+}
+
+static ssize_t debug_write_mem(struct file *file, const char __user *userbuf,
+                               size_t count, loff_t *ppos)
+{
+        struct iommu *obj = file->private_data;
+        struct iovm_struct *area;
+        char *p, *buf;
+
+        count = min_t(size_t, count, PAGE_SIZE);
+
+        buf = (char *)__get_free_page(GFP_KERNEL);
+        if (!buf)
+                return -ENOMEM;
+        p = buf;
+
+        mutex_lock(&iommu_debug_lock);
+
+        if (copy_from_user(p, userbuf, count)) {
+                count =  -EFAULT;
+                goto err_out;
+        }
+
+        area = find_iovm_area(obj, (u32)ppos);
+        if (IS_ERR(area)) {
+                count = -EINVAL;
+                goto err_out;
+        }
+        memcpy(area->va, p, count);
+err_out:
+        mutex_unlock(&iommu_debug_lock);
+        free_page((unsigned long)buf);
+
+        return count;
+}
+
+static int debug_open_generic(struct inode *inode, struct file *file)
+{
+        file->private_data = inode->i_private;
+        return 0;
+}
+
+#define DEBUG_FOPS(name)                                                \
+        static const struct file_operations debug_##name##_fops = {     \
+                .open = debug_open_generic,                             \
+                .read = debug_read_##name,                              \
+                .write = debug_write_##name,                            \
+        };
+
+#define DEBUG_FOPS_RO(name)                                             \
+        static const struct file_operations debug_##name##_fops = {     \
+                .open = debug_open_generic,                             \
+                .read = debug_read_##name,                              \
+        };
+
+DEBUG_FOPS_RO(ver);
+DEBUG_FOPS_RO(regs);
+DEBUG_FOPS_RO(tlb);
+DEBUG_FOPS(pagetable);
+DEBUG_FOPS_RO(mmap);
+DEBUG_FOPS(mem);
+
+#define __DEBUG_ADD_FILE(attr, mode)                                    \
+        {                                                               \
+                struct dentry *dent;                                    \
+                dent = debugfs_create_file(#attr, mode, parent,         \
+                                           obj, &debug_##attr##_fops);  \
+                if (!dent)                                              \
+                        return -ENOMEM;                                 \
+        }
+
+#define DEBUG_ADD_FILE(name) __DEBUG_ADD_FILE(name, 600)
+#define DEBUG_ADD_FILE_RO(name) __DEBUG_ADD_FILE(name, 400)
+
+static int iommu_debug_register(struct device *dev, void *data)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct iommu *obj = platform_get_drvdata(pdev);
+        struct dentry *d, *parent;
+
+        if (!obj || !obj->dev)
+                return -EINVAL;
+
+        d = debugfs_create_dir(obj->name, iommu_debug_root);
+        if (!d)
+                return -ENOMEM;
+        parent = d;
+
+        d = debugfs_create_u8("nr_tlb_entries", 400, parent,
+                              (u8 *)&obj->nr_tlb_entries);
+        if (!d)
+                return -ENOMEM;
+
+        DEBUG_ADD_FILE_RO(ver);
+        DEBUG_ADD_FILE_RO(regs);
+        DEBUG_ADD_FILE_RO(tlb);
+        DEBUG_ADD_FILE(pagetable);
+        DEBUG_ADD_FILE_RO(mmap);
+        DEBUG_ADD_FILE(mem);
+
+        return 0;
+}
+
+static int __init iommu_debug_init(void)
+{
+        struct dentry *d;
+        int err;
+
+        d = debugfs_create_dir("iommu", NULL);
+        if (!d)
+                return -ENOMEM;
+        iommu_debug_root = d;
+
+        err = foreach_iommu_device(d, iommu_debug_register);
+        if (err)
+                goto err_out;
+        return 0;
+
+err_out:
+        debugfs_remove_recursive(iommu_debug_root);
+        return err;
+}
+module_init(iommu_debug_init)
+
+static void __exit iommu_debugfs_exit(void)
+{
+        debugfs_remove_recursive(iommu_debug_root);
+}
+module_exit(iommu_debugfs_exit)
+
+MODULE_DESCRIPTION("omap iommu: debugfs interface");
+MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 4a0301399013..4b6012707307 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -351,16 +351,14 @@ EXPORT_SYMBOL_GPL(flush_iotlb_all);
 
 #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
 
-ssize_t iommu_dump_ctx(struct iommu *obj, char *buf)
+ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)
 {
-        ssize_t bytes;
-
         if (!obj || !buf)
                 return -EINVAL;
 
         clk_enable(obj->clk);
 
-        bytes = arch_iommu->dump_ctx(obj, buf);
+        bytes = arch_iommu->dump_ctx(obj, buf, bytes);
 
         clk_disable(obj->clk);
 
@@ -368,7 +366,7 @@ ssize_t iommu_dump_ctx(struct iommu *obj, char *buf)
 }
 EXPORT_SYMBOL_GPL(iommu_dump_ctx);
 
-static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs)
+static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num)
 {
         int i;
         struct iotlb_lock saved, l;
@@ -379,7 +377,7 @@ static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs)
         iotlb_lock_get(obj, &saved);
         memcpy(&l, &saved, sizeof(saved));
 
-        for (i = 0; i < obj->nr_tlb_entries; i++) {
+        for (i = 0; i < num; i++) {
                 struct cr_regs tmp;
 
                 iotlb_lock_get(obj, &l);
@@ -402,18 +400,21 @@ static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs)
  * @obj:        target iommu
  * @buf:        output buffer
  **/
-size_t dump_tlb_entries(struct iommu *obj, char *buf)
+size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t bytes)
 {
-        int i, n;
+        int i, num;
         struct cr_regs *cr;
         char *p = buf;
 
-        cr = kcalloc(obj->nr_tlb_entries, sizeof(*cr), GFP_KERNEL);
+        num = bytes / sizeof(*cr);
+        num = min(obj->nr_tlb_entries, num);
+
+        cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
         if (!cr)
                 return 0;
 
-        n = __dump_tlb_entries(obj, cr);
-        for (i = 0; i < n; i++)
+        num = __dump_tlb_entries(obj, cr, num);
+        for (i = 0; i < num; i++)
                 p += iotlb_dump_cr(obj, cr + i, p);
         kfree(cr);
 
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
index 2fce2c151a95..6fc52fcbdc03 100644
--- a/arch/arm/plat-omap/iovmm.c
+++ b/arch/arm/plat-omap/iovmm.c
@@ -199,7 +199,7 @@ static void *vmap_sg(const struct sg_table *sgt)
                 va += bytes;
         }
 
-        flush_cache_vmap(new->addr, total);
+        flush_cache_vmap(new->addr, new->addr + total);
         return new->addr;
 
 err_out:
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index efa0e0111f38..88ac9768f1c1 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -191,13 +191,177 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
-        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
                 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
                 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
         }
 }
 EXPORT_SYMBOL(omap_mcbsp_config);
 
+#ifdef CONFIG_ARCH_OMAP34XX
+/*
+ * omap_mcbsp_set_tx_threshold configures how to deal
+ * with transmit threshold. the threshold value and handler can be
+ * configure in here.
+ */
+void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
+{
+        struct omap_mcbsp *mcbsp;
+        void __iomem *io_base;
+
+        if (!cpu_is_omap34xx())
+                return;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+        io_base = mcbsp->io_base;
+
+        OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
+}
+EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
+
+/*
+ * omap_mcbsp_set_rx_threshold configures how to deal
+ * with receive threshold. the threshold value and handler can be
+ * configure in here.
+ */
+void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
+{
+        struct omap_mcbsp *mcbsp;
+        void __iomem *io_base;
+
+        if (!cpu_is_omap34xx())
+                return;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+        io_base = mcbsp->io_base;
+
+        OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
+}
+EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
+
+/*
+ * omap_mcbsp_get_max_tx_thres just return the current configured
+ * maximum threshold for transmission
+ */
+u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
+{
+        struct omap_mcbsp *mcbsp;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+
+        return mcbsp->max_tx_thres;
+}
+EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
+
+/*
+ * omap_mcbsp_get_max_rx_thres just return the current configured
+ * maximum threshold for reception
+ */
+u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
+{
+        struct omap_mcbsp *mcbsp;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+
+        return mcbsp->max_rx_thres;
+}
+EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
+
+/*
+ * omap_mcbsp_get_dma_op_mode just return the current configured
+ * operating mode for the mcbsp channel
+ */
+int omap_mcbsp_get_dma_op_mode(unsigned int id)
+{
+        struct omap_mcbsp *mcbsp;
+        int dma_op_mode;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+
+        spin_lock_irq(&mcbsp->lock);
+        dma_op_mode = mcbsp->dma_op_mode;
+        spin_unlock_irq(&mcbsp->lock);
+
+        return dma_op_mode;
+}
+EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
+
+static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
+{
+        /*
+         * Enable wakup behavior, smart idle and all wakeups
+         * REVISIT: some wakeups may be unnecessary
+         */
+        if (cpu_is_omap34xx()) {
+                u16 syscon;
+
+                syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
+                syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
+
+                spin_lock_irq(&mcbsp->lock);
+                if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
+                        syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
+                                        CLOCKACTIVITY(0x02));
+                        OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN,
+                                        XRDYEN | RRDYEN);
+                } else {
+                        syscon |= SIDLEMODE(0x01);
+                }
+                spin_unlock_irq(&mcbsp->lock);
+
+                OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
+        }
+}
+
+static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
+{
+        /*
+         * Disable wakup behavior, smart idle and all wakeups
+         */
+        if (cpu_is_omap34xx()) {
+                u16 syscon;
+
+                syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
+                syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
+                /*
+                 * HW bug workaround - If no_idle mode is taken, we need to
+                 * go to smart_idle before going to always_idle, or the
+                 * device will not hit retention anymore.
+                 */
+                syscon |= SIDLEMODE(0x02);
+                OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
+
+                syscon &= ~(SIDLEMODE(0x03));
+                OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
+
+                OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0);
+        }
+}
+#else
+static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
+static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
+#endif
+
 /*
  * We can choose between IRQ based or polled IO.
  * This needs to be called before omap_mcbsp_request().
@@ -257,6 +421,9 @@ int omap_mcbsp_request(unsigned int id)
         clk_enable(mcbsp->iclk);
         clk_enable(mcbsp->fclk);
 
+        /* Do procedure specific to omap34xx arch, if applicable */
+        omap34xx_mcbsp_request(mcbsp);
+
         /*
          * Make sure that transmitter, receiver and sample-rate generator are
          * not running before activating IRQs.
@@ -305,6 +472,9 @@ void omap_mcbsp_free(unsigned int id)
         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
                 mcbsp->pdata->ops->free(id);
 
+        /* Do procedure specific to omap34xx arch, if applicable */
+        omap34xx_mcbsp_free(mcbsp);
+
         clk_disable(mcbsp->fclk);
         clk_disable(mcbsp->iclk);
 
@@ -328,14 +498,15 @@ void omap_mcbsp_free(unsigned int id)
 EXPORT_SYMBOL(omap_mcbsp_free);
 
 /*
- * Here we start the McBSP, by enabling the sample
- * generator, both transmitter and receivers,
- * and the frame sync.
+ * Here we start the McBSP, by enabling transmitter, receiver or both.
+ * If no transmitter or receiver is active prior calling, then sample-rate
+ * generator and frame sync are started.
  */
-void omap_mcbsp_start(unsigned int id)
+void omap_mcbsp_start(unsigned int id, int tx, int rx)
 {
         struct omap_mcbsp *mcbsp;
         void __iomem *io_base;
+        int idle;
         u16 w;
 
         if (!omap_mcbsp_check_valid_id(id)) {
@@ -348,32 +519,58 @@ void omap_mcbsp_start(unsigned int id)
         mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
         mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
 
-        /* Start the sample generator */
-        w = OMAP_MCBSP_READ(io_base, SPCR2);
-        OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
+        idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
+                  OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
+
+        if (idle) {
+                /* Start the sample generator */
+                w = OMAP_MCBSP_READ(io_base, SPCR2);
+                OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
+        }
 
         /* Enable transmitter and receiver */
+        tx &= 1;
         w = OMAP_MCBSP_READ(io_base, SPCR2);
-        OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
+        OMAP_MCBSP_WRITE(io_base, SPCR2, w | tx);
 
+        rx &= 1;
         w = OMAP_MCBSP_READ(io_base, SPCR1);
-        OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
+        OMAP_MCBSP_WRITE(io_base, SPCR1, w | rx);
 
-        udelay(100);
+        /*
+         * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
+         * REVISIT: 100us may give enough time for two CLKSRG, however
+         * due to some unknown PM related, clock gating etc. reason it
+         * is now at 500us.
+         */
+        udelay(500);
 
-        /* Start frame sync */
-        w = OMAP_MCBSP_READ(io_base, SPCR2);
-        OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
+        if (idle) {
+                /* Start frame sync */
+                w = OMAP_MCBSP_READ(io_base, SPCR2);
+                OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
+        }
+
+        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+                /* Release the transmitter and receiver */
+                w = OMAP_MCBSP_READ(io_base, XCCR);
+                w &= ~(tx ? XDISABLE : 0);
+                OMAP_MCBSP_WRITE(io_base, XCCR, w);
+                w = OMAP_MCBSP_READ(io_base, RCCR);
+                w &= ~(rx ? RDISABLE : 0);
+                OMAP_MCBSP_WRITE(io_base, RCCR, w);
+        }
 
         /* Dump McBSP Regs */
         omap_mcbsp_dump_reg(id);
 }
 EXPORT_SYMBOL(omap_mcbsp_start);
 
-void omap_mcbsp_stop(unsigned int id)
+void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 {
         struct omap_mcbsp *mcbsp;
         void __iomem *io_base;
+        int idle;
         u16 w;
 
         if (!omap_mcbsp_check_valid_id(id)) {
@@ -385,16 +582,33 @@ void omap_mcbsp_stop(unsigned int id)
         io_base = mcbsp->io_base;
 
         /* Reset transmitter */
+        tx &= 1;
+        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+                w = OMAP_MCBSP_READ(io_base, XCCR);
+                w |= (tx ? XDISABLE : 0);
+                OMAP_MCBSP_WRITE(io_base, XCCR, w);
+        }
         w = OMAP_MCBSP_READ(io_base, SPCR2);
-        OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
+        OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~tx);
 
         /* Reset receiver */
+        rx &= 1;
+        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+                w = OMAP_MCBSP_READ(io_base, RCCR);
+                w |= (tx ? RDISABLE : 0);
+                OMAP_MCBSP_WRITE(io_base, RCCR, w);
+        }
         w = OMAP_MCBSP_READ(io_base, SPCR1);
-        OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
+        OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~rx);
 
-        /* Reset the sample rate generator */
-        w = OMAP_MCBSP_READ(io_base, SPCR2);
-        OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
+        idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
+                  OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
+
+        if (idle) {
+                /* Reset the sample rate generator */
+                w = OMAP_MCBSP_READ(io_base, SPCR2);
+                OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
+        }
 }
 EXPORT_SYMBOL(omap_mcbsp_stop);
 
@@ -883,6 +1097,149 @@ void omap_mcbsp_set_spi_mode(unsigned int id,
 }
 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
 
+#ifdef CONFIG_ARCH_OMAP34XX
+#define max_thres(m)                    (mcbsp->pdata->buffer_size)
+#define valid_threshold(m, val)         ((val) <= max_thres(m))
+#define THRESHOLD_PROP_BUILDER(prop)                                    \
+static ssize_t prop##_show(struct device *dev,                          \
+                        struct device_attribute *attr, char *buf)       \
+{                                                                       \
+        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
+                                                                        \
+        return sprintf(buf, "%u\n", mcbsp->prop);                       \
+}                                                                       \
+                                                                        \
+static ssize_t prop##_store(struct device *dev,                         \
+                                struct device_attribute *attr,          \
+                                const char *buf, size_t size)           \
+{                                                                       \
+        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
+        unsigned long val;                                              \
+        int status;                                                     \
+                                                                        \
+        status = strict_strtoul(buf, 0, &val);                          \
+        if (status)                                                     \
+                return status;                                          \
+                                                                        \
+        if (!valid_threshold(mcbsp, val))                               \
+                return -EDOM;                                           \
+                                                                        \
+        mcbsp->prop = val;                                              \
+        return size;                                                    \
+}                                                                       \
+                                                                        \
+static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
+
+THRESHOLD_PROP_BUILDER(max_tx_thres);
+THRESHOLD_PROP_BUILDER(max_rx_thres);
+
+static const char *dma_op_modes[] = {
+        "element", "threshold", "frame",
+};
+
+static ssize_t dma_op_mode_show(struct device *dev,
+                        struct device_attribute *attr, char *buf)
+{
+        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
+        int dma_op_mode, i = 0;
+        ssize_t len = 0;
+        const char * const *s;
+
+        spin_lock_irq(&mcbsp->lock);
+        dma_op_mode = mcbsp->dma_op_mode;
+        spin_unlock_irq(&mcbsp->lock);
+
+        for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
+                if (dma_op_mode == i)
+                        len += sprintf(buf + len, "[%s] ", *s);
+                else
+                        len += sprintf(buf + len, "%s ", *s);
+        }
+        len += sprintf(buf + len, "\n");
+
+        return len;
+}
+
+static ssize_t dma_op_mode_store(struct device *dev,
+                                struct device_attribute *attr,
+                                const char *buf, size_t size)
+{
+        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
+        const char * const *s;
+        int i = 0;
+
+        for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
+                if (sysfs_streq(buf, *s))
+                        break;
+
+        if (i == ARRAY_SIZE(dma_op_modes))
+                return -EINVAL;
+
+        spin_lock_irq(&mcbsp->lock);
+        if (!mcbsp->free) {
+                size = -EBUSY;
+                goto unlock;
+        }
+        mcbsp->dma_op_mode = i;
+
+unlock:
+        spin_unlock_irq(&mcbsp->lock);
+
+        return size;
+}
+
+static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
+
+static const struct attribute *additional_attrs[] = {
+        &dev_attr_max_tx_thres.attr,
+        &dev_attr_max_rx_thres.attr,
+        &dev_attr_dma_op_mode.attr,
+        NULL,
+};
+
+static const struct attribute_group additional_attr_group = {
+        .attrs = (struct attribute **)additional_attrs,
+};
+
+static inline int __devinit omap_additional_add(struct device *dev)
+{
+        return sysfs_create_group(&dev->kobj, &additional_attr_group);
+}
+
+static inline void __devexit omap_additional_remove(struct device *dev)
+{
+        sysfs_remove_group(&dev->kobj, &additional_attr_group);
+}
+
+static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
+{
+        mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
+        if (cpu_is_omap34xx()) {
+                mcbsp->max_tx_thres = max_thres(mcbsp);
+                mcbsp->max_rx_thres = max_thres(mcbsp);
+                /*
+                 * REVISIT: Set dmap_op_mode to THRESHOLD as default
+                 * for mcbsp2 instances.
+                 */
+                if (omap_additional_add(mcbsp->dev))
+                        dev_warn(mcbsp->dev,
+                                "Unable to create additional controls\n");
+        } else {
+                mcbsp->max_tx_thres = -EINVAL;
+                mcbsp->max_rx_thres = -EINVAL;
+        }
+}
+
+static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
+{
+        if (cpu_is_omap34xx())
+                omap_additional_remove(mcbsp->dev);
+}
+#else
+static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
+static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
+#endif /* CONFIG_ARCH_OMAP34XX */
+
 /*
  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
  * 730 has only 2 McBSP, and both of them are MPU peripherals.
@@ -953,6 +1310,10 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
         mcbsp->dev = &pdev->dev;
         mcbsp_ptr[id] = mcbsp;
         platform_set_drvdata(pdev, mcbsp);
+
+        /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
+        omap34xx_device_init(mcbsp);
+
         return 0;
 
 err_fclk:
@@ -976,6 +1337,8 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
                                 mcbsp->pdata->ops->free)
                         mcbsp->pdata->ops->free(mcbsp->id);
 
+                omap34xx_device_exit(mcbsp);
+
                 clk_disable(mcbsp->fclk);
                 clk_disable(mcbsp->iclk);
                 clk_put(mcbsp->fclk);
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
new file mode 100644
index 000000000000..e98f0a2a6c26
--- /dev/null
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -0,0 +1,296 @@
+/*
+ * omap-pm-noop.c - OMAP power management interface - dummy version
+ *
+ * This code implements the OMAP power management interface to
+ * drivers, CPUIdle, CPUFreq, and DSP Bridge.  It is strictly for
+ * debug/demonstration use, as it does nothing but printk() whenever a
+ * function is called (when DEBUG is defined, below)
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * Interface developed by (in alphabetical order):
+ * Karthik Dasu, Tony Lindgren, Rajendra Nayak, Sakari Poussa, Veeramanikandan
+ * Raju, Anand Sawant, Igor Stoppa, Paul Walmsley, Richard Woodruff
+ */
+
+#undef DEBUG
+
+#include <linux/init.h>
+#include <linux/cpufreq.h>
+#include <linux/device.h>
+
+/* Interface documentation is in mach/omap-pm.h */
+#include <mach/omap-pm.h>
+
+#include <mach/powerdomain.h>
+
+struct omap_opp *dsp_opps;
+struct omap_opp *mpu_opps;
+struct omap_opp *l3_opps;
+
+/*
+ * Device-driver-originated constraints (via board-*.c files)
+ */
+
+void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
+{
+        if (!dev || t < -1) {
+                WARN_ON(1);
+                return;
+        };
+
+        if (t == -1)
+                pr_debug("OMAP PM: remove max MPU wakeup latency constraint: "
+                         "dev %s\n", dev_name(dev));
+        else
+                pr_debug("OMAP PM: add max MPU wakeup latency constraint: "
+                         "dev %s, t = %ld usec\n", dev_name(dev), t);
+
+        /*
+         * For current Linux, this needs to map the MPU to a
+         * powerdomain, then go through the list of current max lat
+         * constraints on the MPU and find the smallest.  If
+         * the latency constraint has changed, the code should
+         * recompute the state to enter for the next powerdomain
+         * state.
+         *
+         * TI CDP code can call constraint_set here.
+         */
+}
+
+void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
+{
+        if (!dev || (agent_id != OCP_INITIATOR_AGENT &&
+            agent_id != OCP_TARGET_AGENT)) {
+                WARN_ON(1);
+                return;
+        };
+
+        if (r == 0)
+                pr_debug("OMAP PM: remove min bus tput constraint: "
+                         "dev %s for agent_id %d\n", dev_name(dev), agent_id);
+        else
+                pr_debug("OMAP PM: add min bus tput constraint: "
+                         "dev %s for agent_id %d: rate %ld KiB\n",
+                         dev_name(dev), agent_id, r);
+
+        /*
+         * This code should model the interconnect and compute the
+         * required clock frequency, convert that to a VDD2 OPP ID, then
+         * set the VDD2 OPP appropriately.
+         *
+         * TI CDP code can call constraint_set here on the VDD2 OPP.
+         */
+}
+
+void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t)
+{
+        if (!dev || t < -1) {
+                WARN_ON(1);
+                return;
+        };
+
+        if (t == -1)
+                pr_debug("OMAP PM: remove max device latency constraint: "
+                         "dev %s\n", dev_name(dev));
+        else
+                pr_debug("OMAP PM: add max device latency constraint: "
+                         "dev %s, t = %ld usec\n", dev_name(dev), t);
+
+        /*
+         * For current Linux, this needs to map the device to a
+         * powerdomain, then go through the list of current max lat
+         * constraints on that powerdomain and find the smallest.  If
+         * the latency constraint has changed, the code should
+         * recompute the state to enter for the next powerdomain
+         * state.  Conceivably, this code should also determine
+         * whether to actually disable the device clocks or not,
+         * depending on how long it takes to re-enable the clocks.
+         *
+         * TI CDP code can call constraint_set here.
+         */
+}
+
+void omap_pm_set_max_sdma_lat(struct device *dev, long t)
+{
+        if (!dev || t < -1) {
+                WARN_ON(1);
+                return;
+        };
+
+        if (t == -1)
+                pr_debug("OMAP PM: remove max DMA latency constraint: "
+                         "dev %s\n", dev_name(dev));
+        else
+                pr_debug("OMAP PM: add max DMA latency constraint: "
+                         "dev %s, t = %ld usec\n", dev_name(dev), t);
+
+        /*
+         * For current Linux PM QOS params, this code should scan the
+         * list of maximum CPU and DMA latencies and select the
+         * smallest, then set cpu_dma_latency pm_qos_param
+         * accordingly.
+         *
+         * For future Linux PM QOS params, with separate CPU and DMA
+         * latency params, this code should just set the dma_latency param.
+         *
+         * TI CDP code can call constraint_set here.
+         */
+
+}
+
+
+/*
+ * DSP Bridge-specific constraints
+ */
+
+const struct omap_opp *omap_pm_dsp_get_opp_table(void)
+{
+        pr_debug("OMAP PM: DSP request for OPP table\n");
+
+        /*
+         * Return DSP frequency table here:  The final item in the
+         * array should have .rate = .opp_id = 0.
+         */
+
+        return NULL;
+}
+
+void omap_pm_dsp_set_min_opp(u8 opp_id)
+{
+        if (opp_id == 0) {
+                WARN_ON(1);
+                return;
+        }
+
+        pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id);
+
+        /*
+         *
+         * For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we
+         * can just test to see which is higher, the CPU's desired OPP
+         * ID or the DSP's desired OPP ID, and use whichever is
+         * highest.
+         *
+         * In CDP12.14+, the VDD1 OPP custom clock that controls the DSP
+         * rate is keyed on MPU speed, not the OPP ID.  So we need to
+         * map the OPP ID to the MPU speed for use with clk_set_rate()
+         * if it is higher than the current OPP clock rate.
+         *
+         */
+}
+
+
+u8 omap_pm_dsp_get_opp(void)
+{
+        pr_debug("OMAP PM: DSP requests current DSP OPP ID\n");
+
+        /*
+         * For l-o dev tree, call clk_get_rate() on VDD1 OPP clock
+         *
+         * CDP12.14+:
+         * Call clk_get_rate() on the OPP custom clock, map that to an
+         * OPP ID using the tables defined in board-*.c/chip-*.c files.
+         */
+
+        return 0;
+}
+
+/*
+ * CPUFreq-originated constraint
+ *
+ * In the future, this should be handled by custom OPP clocktype
+ * functions.
+ */
+
+struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void)
+{
+        pr_debug("OMAP PM: CPUFreq request for frequency table\n");
+
+        /*
+         * Return CPUFreq frequency table here: loop over
+         * all VDD1 clkrates, pull out the mpu_ck frequencies, build
+         * table
+         */
+
+        return NULL;
+}
+
+void omap_pm_cpu_set_freq(unsigned long f)
+{
+        if (f == 0) {
+                WARN_ON(1);
+                return;
+        }
+
+        pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n",
+                 f);
+
+        /*
+         * For l-o dev tree, determine whether MPU freq or DSP OPP id
+         * freq is higher.  Find the OPP ID corresponding to the
+         * higher frequency.  Call clk_round_rate() and clk_set_rate()
+         * on the OPP custom clock.
+         *
+         * CDP should just be able to set the VDD1 OPP clock rate here.
+         */
+}
+
+unsigned long omap_pm_cpu_get_freq(void)
+{
+        pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n");
+
+        /*
+         * Call clk_get_rate() on the mpu_ck.
+         */
+
+        return 0;
+}
+
+/*
+ * Device context loss tracking
+ */
+
+int omap_pm_get_dev_context_loss_count(struct device *dev)
+{
+        if (!dev) {
+                WARN_ON(1);
+                return -EINVAL;
+        };
+
+        pr_debug("OMAP PM: returning context loss count for dev %s\n",
+                 dev_name(dev));
+
+        /*
+         * Map the device to the powerdomain.  Return the powerdomain
+         * off counter.
+         */
+
+        return 0;
+}
+
+
+/* Should be called before clk framework init */
+int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
+                                 struct omap_opp *dsp_opp_table,
+                                 struct omap_opp *l3_opp_table)
+{
+        mpu_opps = mpu_opp_table;
+        dsp_opps = dsp_opp_table;
+        l3_opps = l3_opp_table;
+        return 0;
+}
+
+/* Must be called after clock framework is initialized */
+int __init omap_pm_if_init(void)
+{
+        return 0;
+}
+
+void omap_pm_if_exit(void)
+{
+        /* Deallocate CPUFreq frequency table here */
+}
+
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
new file mode 100644
index 000000000000..2c409fc6dd21
--- /dev/null
+++ b/arch/arm/plat-omap/omap_device.c
@@ -0,0 +1,687 @@
+/*
+ * omap_device implementation
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * Developed in collaboration with (alphabetical order): Benoit
+ * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
+ * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
+ * Woodruff
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This code provides a consistent interface for OMAP device drivers
+ * to control power management and interconnect properties of their
+ * devices.
+ *
+ * In the medium- to long-term, this code should either be
+ * a) implemented via arch-specific pointers in platform_data
+ * or
+ * b) implemented as a proper omap_bus/omap_device in Linux, no more
+ *    platform_data func pointers
+ *
+ *
+ * Guidelines for usage by driver authors:
+ *
+ * 1. These functions are intended to be used by device drivers via
+ * function pointers in struct platform_data.  As an example,
+ * omap_device_enable() should be passed to the driver as
+ *
+ * struct foo_driver_platform_data {
+ * ...
+ *      int (*device_enable)(struct platform_device *pdev);
+ * ...
+ * }
+ *
+ * Note that the generic "device_enable" name is used, rather than
+ * "omap_device_enable".  This is so other architectures can pass in their
+ * own enable/disable functions here.
+ *
+ * This should be populated during device setup:
+ *
+ * ...
+ * pdata->device_enable = omap_device_enable;
+ * ...
+ *
+ * 2. Drivers should first check to ensure the function pointer is not null
+ * before calling it, as in:
+ *
+ * if (pdata->device_enable)
+ *     pdata->device_enable(pdev);
+ *
+ * This allows other architectures that don't use similar device_enable()/
+ * device_shutdown() functions to execute normally.
+ *
+ * ...
+ *
+ * Suggested usage by device drivers:
+ *
+ * During device initialization:
+ * device_enable()
+ *
+ * During device idle:
+ * (save remaining device context if necessary)
+ * device_idle();
+ *
+ * During device resume:
+ * device_enable();
+ * (restore context if necessary)
+ *
+ * During device shutdown:
+ * device_shutdown()
+ * (device must be reinitialized at this point to use it again)
+ *
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <mach/omap_device.h>
+#include <mach/omap_hwmod.h>
+
+/* These parameters are passed to _omap_device_{de,}activate() */
+#define USE_WAKEUP_LAT                  0
+#define IGNORE_WAKEUP_LAT               1
+
+/* XXX this should be moved into a separate file */
+#if defined(CONFIG_ARCH_OMAP2420)
+# define OMAP_32KSYNCT_BASE             0x48004000
+#elif defined(CONFIG_ARCH_OMAP2430)
+# define OMAP_32KSYNCT_BASE             0x49020000
+#elif defined(CONFIG_ARCH_OMAP3430)
+# define OMAP_32KSYNCT_BASE             0x48320000
+#else
+# error Unknown OMAP device
+#endif
+
+/* Private functions */
+
+/**
+ * _read_32ksynct - read the OMAP 32K sync timer
+ *
+ * Returns the current value of the 32KiHz synchronization counter.
+ * XXX this should be generalized to simply read the system clocksource.
+ * XXX this should be moved to a separate synctimer32k.c file
+ */
+static u32 _read_32ksynct(void)
+{
+        if (!cpu_class_is_omap2())
+                BUG();
+
+        return __raw_readl(OMAP2_IO_ADDRESS(OMAP_32KSYNCT_BASE + 0x010));
+}
+
+/**
+ * _omap_device_activate - increase device readiness
+ * @od: struct omap_device *
+ * @ignore_lat: increase to latency target (0) or full readiness (1)?
+ *
+ * Increase readiness of omap_device @od (thus decreasing device
+ * wakeup latency, but consuming more power).  If @ignore_lat is
+ * IGNORE_WAKEUP_LAT, make the omap_device fully active.  Otherwise,
+ * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup
+ * latency is greater than the requested maximum wakeup latency, step
+ * backwards in the omap_device_pm_latency table to ensure the
+ * device's maximum wakeup latency is less than or equal to the
+ * requested maximum wakeup latency.  Returns 0.
+ */
+static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
+{
+        u32 a, b;
+
+        pr_debug("omap_device: %s: activating\n", od->pdev.name);
+
+        while (od->pm_lat_level > 0) {
+                struct omap_device_pm_latency *odpl;
+                int act_lat = 0;
+
+                od->pm_lat_level--;
+
+                odpl = od->pm_lats + od->pm_lat_level;
+
+                if (!ignore_lat &&
+                    (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit))
+                        break;
+
+                a = _read_32ksynct();
+
+                /* XXX check return code */
+                odpl->activate_func(od);
+
+                b = _read_32ksynct();
+
+                act_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */
+
+                pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time "
+                         "%d usec\n", od->pdev.name, od->pm_lat_level, act_lat);
+
+                WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: "
+                     "activate step %d took longer than expected (%d > %d)\n",
+                     od->pdev.name, od->pdev.id, od->pm_lat_level,
+                     act_lat, odpl->activate_lat);
+
+                od->dev_wakeup_lat -= odpl->activate_lat;
+        }
+
+        return 0;
+}
+
+/**
+ * _omap_device_deactivate - decrease device readiness
+ * @od: struct omap_device *
+ * @ignore_lat: decrease to latency target (0) or full inactivity (1)?
+ *
+ * Decrease readiness of omap_device @od (thus increasing device
+ * wakeup latency, but conserving power).  If @ignore_lat is
+ * IGNORE_WAKEUP_LAT, make the omap_device fully inactive.  Otherwise,
+ * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup
+ * latency is less than the requested maximum wakeup latency, step
+ * forwards in the omap_device_pm_latency table to ensure the device's
+ * maximum wakeup latency is less than or equal to the requested
+ * maximum wakeup latency.  Returns 0.
+ */
+static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
+{
+        u32 a, b;
+
+        pr_debug("omap_device: %s: deactivating\n", od->pdev.name);
+
+        while (od->pm_lat_level < od->pm_lats_cnt) {
+                struct omap_device_pm_latency *odpl;
+                int deact_lat = 0;
+
+                odpl = od->pm_lats + od->pm_lat_level;
+
+                if (!ignore_lat &&
+                    ((od->dev_wakeup_lat + odpl->activate_lat) >
+                     od->_dev_wakeup_lat_limit))
+                        break;
+
+                a = _read_32ksynct();
+
+                /* XXX check return code */
+                odpl->deactivate_func(od);
+
+                b = _read_32ksynct();
+
+                deact_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */
+
+                pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time "
+                         "%d usec\n", od->pdev.name, od->pm_lat_level,
+                         deact_lat);
+
+                WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: "
+                     "deactivate step %d took longer than expected (%d > %d)\n",
+                     od->pdev.name, od->pdev.id, od->pm_lat_level,
+                     deact_lat, odpl->deactivate_lat);
+
+                od->dev_wakeup_lat += odpl->activate_lat;
+
+                od->pm_lat_level++;
+        }
+
+        return 0;
+}
+
+static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
+{
+        return container_of(pdev, struct omap_device, pdev);
+}
+
+
+/* Public functions for use by core code */
+
+/**
+ * omap_device_count_resources - count number of struct resource entries needed
+ * @od: struct omap_device *
+ *
+ * Count the number of struct resource entries needed for this
+ * omap_device @od.  Used by omap_device_build_ss() to determine how
+ * much memory to allocate before calling
+ * omap_device_fill_resources().  Returns the count.
+ */
+int omap_device_count_resources(struct omap_device *od)
+{
+        struct omap_hwmod *oh;
+        int c = 0;
+        int i;
+
+        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
+                c += omap_hwmod_count_resources(oh);
+
+        pr_debug("omap_device: %s: counted %d total resources across %d "
+                 "hwmods\n", od->pdev.name, c, od->hwmods_cnt);
+
+        return c;
+}
+
+/**
+ * omap_device_fill_resources - fill in array of struct resource
+ * @od: struct omap_device *
+ * @res: pointer to an array of struct resource to be filled in
+ *
+ * Populate one or more empty struct resource pointed to by @res with
+ * the resource data for this omap_device @od.  Used by
+ * omap_device_build_ss() after calling omap_device_count_resources().
+ * Ideally this function would not be needed at all.  If omap_device
+ * replaces platform_device, then we can specify our own
+ * get_resource()/ get_irq()/etc functions that use the underlying
+ * omap_hwmod information.  Or if platform_device is extended to use
+ * subarchitecture-specific function pointers, the various
+ * platform_device functions can simply call omap_device internal
+ * functions to get device resources.  Hacking around the existing
+ * platform_device code wastes memory.  Returns 0.
+ */
+int omap_device_fill_resources(struct omap_device *od, struct resource *res)
+{
+        struct omap_hwmod *oh;
+        int c = 0;
+        int i, r;
+
+        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) {
+                r = omap_hwmod_fill_resources(oh, res);
+                res += r;
+                c += r;
+        }
+
+        return 0;
+}
+
+/**
+ * omap_device_build - build and register an omap_device with one omap_hwmod
+ * @pdev_name: name of the platform_device driver to use
+ * @pdev_id: this platform_device's connection ID
+ * @oh: ptr to the single omap_hwmod that backs this omap_device
+ * @pdata: platform_data ptr to associate with the platform_device
+ * @pdata_len: amount of memory pointed to by @pdata
+ * @pm_lats: pointer to a omap_device_pm_latency array for this device
+ * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
+ *
+ * Convenience function for building and registering a single
+ * omap_device record, which in turn builds and registers a
+ * platform_device record.  See omap_device_build_ss() for more
+ * information.  Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
+ * passes along the return value of omap_device_build_ss().
+ */
+struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
+                                      struct omap_hwmod *oh, void *pdata,
+                                      int pdata_len,
+                                      struct omap_device_pm_latency *pm_lats,
+                                      int pm_lats_cnt)
+{
+        struct omap_hwmod *ohs[] = { oh };
+
+        if (!oh)
+                return ERR_PTR(-EINVAL);
+
+        return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata,
+                                    pdata_len, pm_lats, pm_lats_cnt);
+}
+
+/**
+ * omap_device_build_ss - build and register an omap_device with multiple hwmods
+ * @pdev_name: name of the platform_device driver to use
+ * @pdev_id: this platform_device's connection ID
+ * @oh: ptr to the single omap_hwmod that backs this omap_device
+ * @pdata: platform_data ptr to associate with the platform_device
+ * @pdata_len: amount of memory pointed to by @pdata
+ * @pm_lats: pointer to a omap_device_pm_latency array for this device
+ * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
+ *
+ * Convenience function for building and registering an omap_device
+ * subsystem record.  Subsystem records consist of multiple
+ * omap_hwmods.  This function in turn builds and registers a
+ * platform_device record.  Returns an ERR_PTR() on error, or passes
+ * along the return value of omap_device_register().
+ */
+struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
+                                         struct omap_hwmod **ohs, int oh_cnt,
+                                         void *pdata, int pdata_len,
+                                         struct omap_device_pm_latency *pm_lats,
+                                         int pm_lats_cnt)
+{
+        int ret = -ENOMEM;
+        struct omap_device *od;
+        char *pdev_name2;
+        struct resource *res = NULL;
+        int res_count;
+        struct omap_hwmod **hwmods;
+
+        if (!ohs || oh_cnt == 0 || !pdev_name)
+                return ERR_PTR(-EINVAL);
+
+        if (!pdata && pdata_len > 0)
+                return ERR_PTR(-EINVAL);
+
+        pr_debug("omap_device: %s: building with %d hwmods\n", pdev_name,
+                 oh_cnt);
+
+        od = kzalloc(sizeof(struct omap_device), GFP_KERNEL);
+        if (!od)
+                return ERR_PTR(-ENOMEM);
+
+        od->hwmods_cnt = oh_cnt;
+
+        hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt,
+                         GFP_KERNEL);
+        if (!hwmods)
+                goto odbs_exit1;
+
+        memcpy(hwmods, ohs, sizeof(struct omap_hwmod *) * oh_cnt);
+        od->hwmods = hwmods;
+
+        pdev_name2 = kzalloc(strlen(pdev_name) + 1, GFP_KERNEL);
+        if (!pdev_name2)
+                goto odbs_exit2;
+        strcpy(pdev_name2, pdev_name);
+
+        od->pdev.name = pdev_name2;
+        od->pdev.id = pdev_id;
+
+        res_count = omap_device_count_resources(od);
+        if (res_count > 0) {
+                res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
+                if (!res)
+                        goto odbs_exit3;
+        }
+        omap_device_fill_resources(od, res);
+
+        od->pdev.num_resources = res_count;
+        od->pdev.resource = res;
+
+        platform_device_add_data(&od->pdev, pdata, pdata_len);
+
+        od->pm_lats = pm_lats;
+        od->pm_lats_cnt = pm_lats_cnt;
+
+        ret = omap_device_register(od);
+        if (ret)
+                goto odbs_exit4;
+
+        return od;
+
+odbs_exit4:
+        kfree(res);
+odbs_exit3:
+        kfree(pdev_name2);
+odbs_exit2:
+        kfree(hwmods);
+odbs_exit1:
+        kfree(od);
+
+        pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret);
+
+        return ERR_PTR(ret);
+}
+
+/**
+ * omap_device_register - register an omap_device with one omap_hwmod
+ * @od: struct omap_device * to register
+ *
+ * Register the omap_device structure.  This currently just calls
+ * platform_device_register() on the underlying platform_device.
+ * Returns the return value of platform_device_register().
+ */
+int omap_device_register(struct omap_device *od)
+{
+        pr_debug("omap_device: %s: registering\n", od->pdev.name);
+
+        return platform_device_register(&od->pdev);
+}
+
+
+/* Public functions for use by device drivers through struct platform_data */
+
+/**
+ * omap_device_enable - fully activate an omap_device
+ * @od: struct omap_device * to activate
+ *
+ * Do whatever is necessary for the hwmods underlying omap_device @od
+ * to be accessible and ready to operate.  This generally involves
+ * enabling clocks, setting SYSCONFIG registers; and in the future may
+ * involve remuxing pins.  Device drivers should call this function
+ * (through platform_data function pointers) where they would normally
+ * enable clocks, etc.  Returns -EINVAL if called when the omap_device
+ * is already enabled, or passes along the return value of
+ * _omap_device_activate().
+ */
+int omap_device_enable(struct platform_device *pdev)
+{
+        int ret;
+        struct omap_device *od;
+
+        od = _find_by_pdev(pdev);
+
+        if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
+                WARN(1, "omap_device: %s.%d: omap_device_enable() called from "
+                     "invalid state\n", od->pdev.name, od->pdev.id);
+                return -EINVAL;
+        }
+
+        /* Enable everything if we're enabling this device from scratch */
+        if (od->_state == OMAP_DEVICE_STATE_UNKNOWN)
+                od->pm_lat_level = od->pm_lats_cnt;
+
+        ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT);
+
+        od->dev_wakeup_lat = 0;
+        od->_dev_wakeup_lat_limit = INT_MAX;
+        od->_state = OMAP_DEVICE_STATE_ENABLED;
+
+        return ret;
+}
+
+/**
+ * omap_device_idle - idle an omap_device
+ * @od: struct omap_device * to idle
+ *
+ * Idle omap_device @od by calling as many .deactivate_func() entries
+ * in the omap_device's pm_lats table as is possible without exceeding
+ * the device's maximum wakeup latency limit, pm_lat_limit.  Device
+ * drivers should call this function (through platform_data function
+ * pointers) where they would normally disable clocks after operations
+ * complete, etc..  Returns -EINVAL if the omap_device is not
+ * currently enabled, or passes along the return value of
+ * _omap_device_deactivate().
+ */
+int omap_device_idle(struct platform_device *pdev)
+{
+        int ret;
+        struct omap_device *od;
+
+        od = _find_by_pdev(pdev);
+
+        if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
+                WARN(1, "omap_device: %s.%d: omap_device_idle() called from "
+                     "invalid state\n", od->pdev.name, od->pdev.id);
+                return -EINVAL;
+        }
+
+        ret = _omap_device_deactivate(od, USE_WAKEUP_LAT);
+
+        od->_state = OMAP_DEVICE_STATE_IDLE;
+
+        return ret;
+}
+
+/**
+ * omap_device_shutdown - shut down an omap_device
+ * @od: struct omap_device * to shut down
+ *
+ * Shut down omap_device @od by calling all .deactivate_func() entries
+ * in the omap_device's pm_lats table and then shutting down all of
+ * the underlying omap_hwmods.  Used when a device is being "removed"
+ * or a device driver is being unloaded.  Returns -EINVAL if the
+ * omap_device is not currently enabled or idle, or passes along the
+ * return value of _omap_device_deactivate().
+ */
+int omap_device_shutdown(struct platform_device *pdev)
+{
+        int ret, i;
+        struct omap_device *od;
+        struct omap_hwmod *oh;
+
+        od = _find_by_pdev(pdev);
+
+        if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
+            od->_state != OMAP_DEVICE_STATE_IDLE) {
+                WARN(1, "omap_device: %s.%d: omap_device_shutdown() called "
+                     "from invalid state\n", od->pdev.name, od->pdev.id);
+                return -EINVAL;
+        }
+
+        ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT);
+
+        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
+                omap_hwmod_shutdown(oh);
+
+        od->_state = OMAP_DEVICE_STATE_SHUTDOWN;
+
+        return ret;
+}
+
+/**
+ * omap_device_align_pm_lat - activate/deactivate device to match wakeup lat lim
+ * @od: struct omap_device *
+ *
+ * When a device's maximum wakeup latency limit changes, call some of
+ * the .activate_func or .deactivate_func function pointers in the
+ * omap_device's pm_lats array to ensure that the device's maximum
+ * wakeup latency is less than or equal to the new latency limit.
+ * Intended to be called by OMAP PM code whenever a device's maximum
+ * wakeup latency limit changes (e.g., via
+ * omap_pm_set_dev_wakeup_lat()).  Returns 0 if nothing needs to be
+ * done (e.g., if the omap_device is not currently idle, or if the
+ * wakeup latency is already current with the new limit) or passes
+ * along the return value of _omap_device_deactivate() or
+ * _omap_device_activate().
+ */
+int omap_device_align_pm_lat(struct platform_device *pdev,
+                             u32 new_wakeup_lat_limit)
+{
+        int ret = -EINVAL;
+        struct omap_device *od;
+
+        od = _find_by_pdev(pdev);
+
+        if (new_wakeup_lat_limit == od->dev_wakeup_lat)
+                return 0;
+
+        od->_dev_wakeup_lat_limit = new_wakeup_lat_limit;
+
+        if (od->_state != OMAP_DEVICE_STATE_IDLE)
+                return 0;
+        else if (new_wakeup_lat_limit > od->dev_wakeup_lat)
+                ret = _omap_device_deactivate(od, USE_WAKEUP_LAT);
+        else if (new_wakeup_lat_limit < od->dev_wakeup_lat)
+                ret = _omap_device_activate(od, USE_WAKEUP_LAT);
+
+        return ret;
+}
+
+/**
+ * omap_device_get_pwrdm - return the powerdomain * associated with @od
+ * @od: struct omap_device *
+ *
+ * Return the powerdomain associated with the first underlying
+ * omap_hwmod for this omap_device.  Intended for use by core OMAP PM
+ * code.  Returns NULL on error or a struct powerdomain * upon
+ * success.
+ */
+struct powerdomain *omap_device_get_pwrdm(struct omap_device *od)
+{
+        /*
+         * XXX Assumes that all omap_hwmod powerdomains are identical.
+         * This may not necessarily be true.  There should be a sanity
+         * check in here to WARN() if any difference appears.
+         */
+        if (!od->hwmods_cnt)
+                return NULL;
+
+        return omap_hwmod_get_pwrdm(od->hwmods[0]);
+}
+
+/*
+ * Public functions intended for use in omap_device_pm_latency
+ * .activate_func and .deactivate_func function pointers
+ */
+
+/**
+ * omap_device_enable_hwmods - call omap_hwmod_enable() on all hwmods
+ * @od: struct omap_device *od
+ *
+ * Enable all underlying hwmods.  Returns 0.
+ */
+int omap_device_enable_hwmods(struct omap_device *od)
+{
+        struct omap_hwmod *oh;
+        int i;
+
+        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
+                omap_hwmod_enable(oh);
+
+        /* XXX pass along return value here? */
+        return 0;
+}
+
+/**
+ * omap_device_idle_hwmods - call omap_hwmod_idle() on all hwmods
+ * @od: struct omap_device *od
+ *
+ * Idle all underlying hwmods.  Returns 0.
+ */
+int omap_device_idle_hwmods(struct omap_device *od)
+{
+        struct omap_hwmod *oh;
+        int i;
+
+        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
+                omap_hwmod_idle(oh);
+
+        /* XXX pass along return value here? */
+        return 0;
+}
+
+/**
+ * omap_device_disable_clocks - disable all main and interface clocks
+ * @od: struct omap_device *od
+ *
+ * Disable the main functional clock and interface clock for all of the
+ * omap_hwmods associated with the omap_device.  Returns 0.
+ */
+int omap_device_disable_clocks(struct omap_device *od)
+{
+        struct omap_hwmod *oh;
+        int i;
+
+        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
+                omap_hwmod_disable_clocks(oh);
+
+        /* XXX pass along return value here? */
+        return 0;
+}
+
+/**
+ * omap_device_enable_clocks - enable all main and interface clocks
+ * @od: struct omap_device *od
+ *
+ * Enable the main functional clock and interface clock for all of the
+ * omap_hwmods associated with the omap_device.  Returns 0.
+ */
+int omap_device_enable_clocks(struct omap_device *od)
+{
+        struct omap_hwmod *oh;
+        int i;
+
+        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
+                omap_hwmod_enable_clocks(oh);
+
+        /* XXX pass along return value here? */
+        return 0;
+}
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 5eae7876979c..925f64711c37 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -56,16 +56,16 @@
 #define SRAM_BOOTLOADER_SZ      0x80
 #endif
 
-#define OMAP24XX_VA_REQINFOPERM0        IO_ADDRESS(0x68005048)
-#define OMAP24XX_VA_READPERM0           IO_ADDRESS(0x68005050)
-#define OMAP24XX_VA_WRITEPERM0          IO_ADDRESS(0x68005058)
-
-#define OMAP34XX_VA_REQINFOPERM0        IO_ADDRESS(0x68012848)
-#define OMAP34XX_VA_READPERM0           IO_ADDRESS(0x68012850)
-#define OMAP34XX_VA_WRITEPERM0          IO_ADDRESS(0x68012858)
-#define OMAP34XX_VA_ADDR_MATCH2         IO_ADDRESS(0x68012880)
-#define OMAP34XX_VA_SMS_RG_ATT0         IO_ADDRESS(0x6C000048)
-#define OMAP34XX_VA_CONTROL_STAT        IO_ADDRESS(0x480022F0)
+#define OMAP24XX_VA_REQINFOPERM0        OMAP2_IO_ADDRESS(0x68005048)
+#define OMAP24XX_VA_READPERM0           OMAP2_IO_ADDRESS(0x68005050)
+#define OMAP24XX_VA_WRITEPERM0          OMAP2_IO_ADDRESS(0x68005058)
+
+#define OMAP34XX_VA_REQINFOPERM0        OMAP2_IO_ADDRESS(0x68012848)
+#define OMAP34XX_VA_READPERM0           OMAP2_IO_ADDRESS(0x68012850)
+#define OMAP34XX_VA_WRITEPERM0          OMAP2_IO_ADDRESS(0x68012858)
+#define OMAP34XX_VA_ADDR_MATCH2         OMAP2_IO_ADDRESS(0x68012880)
+#define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_IO_ADDRESS(0x6C000048)
+#define OMAP34XX_VA_CONTROL_STAT        OMAP2_IO_ADDRESS(0x480022F0)
 
 #define GP_DEVICE               0x300
 
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig
index 935c7558469b..8931c5f0e46b 100644
--- a/arch/arm/plat-s3c/Kconfig
+++ b/arch/arm/plat-s3c/Kconfig
@@ -198,4 +198,9 @@ config S3C_DEV_USB_HSOTG
         help
           Compile in platform device definition for USB high-speed OtG
 
+config S3C_DEV_NAND
+        bool
+        help
+          Compile in platform device definition for NAND controller
+
 endif
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index 0761766b1833..3c09109e9e84 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -28,13 +28,17 @@ obj-$(CONFIG_PM)		+= pm.o
 obj-$(CONFIG_PM)                += pm-gpio.o
 obj-$(CONFIG_S3C2410_PM_CHECK)  += pm-check.o
 
+# PWM support
+
+obj-$(CONFIG_HAVE_PWM)          += pwm.o
+
 # devices
 
 obj-$(CONFIG_S3C_DEV_HSMMC)     += dev-hsmmc.o
 obj-$(CONFIG_S3C_DEV_HSMMC1)    += dev-hsmmc1.o
 obj-y                           += dev-i2c0.o
 obj-$(CONFIG_S3C_DEV_I2C1)      += dev-i2c1.o
-obj-$(CONFIG_SND_S3C64XX_SOC_I2S)       += dev-audio.o
 obj-$(CONFIG_S3C_DEV_FB)        += dev-fb.o
 obj-$(CONFIG_S3C_DEV_USB_HOST)  += dev-usb.o
 obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o
+obj-$(CONFIG_S3C_DEV_NAND)      += dev-nand.o
diff --git a/arch/arm/plat-s3c/dev-nand.c b/arch/arm/plat-s3c/dev-nand.c
new file mode 100644
index 000000000000..4e5323732434
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-nand.c
@@ -0,0 +1,30 @@
+/*
+ * S3C series device definition for nand device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <mach/map.h>
+#include <plat/devs.h>
+
+static struct resource s3c_nand_resource[] = {
+        [0] = {
+                .start = S3C_PA_NAND,
+                .end   = S3C_PA_NAND + SZ_1M,
+                .flags = IORESOURCE_MEM,
+        }
+};
+
+struct platform_device s3c_device_nand = {
+        .name             = "s3c2410-nand",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s3c_nand_resource),
+        .resource         = s3c_nand_resource,
+};
+
+EXPORT_SYMBOL(s3c_device_nand);
diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-s3c/include/plat/adc.h
index d847bd476b6c..5f3b1cd53b90 100644
--- a/arch/arm/plat-s3c/include/plat/adc.h
+++ b/arch/arm/plat-s3c/include/plat/adc.h
@@ -19,10 +19,14 @@ struct s3c_adc_client;
 extern int s3c_adc_start(struct s3c_adc_client *client,
                          unsigned int channel, unsigned int nr_samples);
 
+extern int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch);
+
 extern struct s3c_adc_client *
         s3c_adc_register(struct platform_device *pdev,
-                         void (*select)(unsigned selected),
-                         void (*conv)(unsigned d0, unsigned d1,
+                         void (*select)(struct s3c_adc_client *client,
+                                        unsigned selected),
+                         void (*conv)(struct s3c_adc_client *client,
+                                      unsigned d0, unsigned d1,
                                       unsigned *samples_left),
                          unsigned int is_ts);
 
diff --git a/arch/arm/plat-s3c/include/plat/audio-simtec.h b/arch/arm/plat-s3c/include/plat/audio-simtec.h
new file mode 100644
index 000000000000..0f440b9168db
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/audio-simtec.h
@@ -0,0 +1,37 @@
+/* arch/arm/plat-s3c/include/plat/audio-simtec.h
+ *
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Simtec Audio support.
+*/
+
+/**
+ * struct s3c24xx_audio_simtec_pdata - platform data for simtec audio
+ * @use_mpllin: Select codec clock from MPLLin
+ * @output_cdclk: Need to output CDCLK to the codec
+ * @have_mic: Set if we have a MIC socket
+ * @have_lout: Set if we have a LineOut socket
+ * @amp_gpio: GPIO pin to enable the AMP
+ * @amp_gain: Option GPIO to control AMP gain
+ */
+struct s3c24xx_audio_simtec_pdata {
+        unsigned int    use_mpllin:1;
+        unsigned int    output_cdclk:1;
+
+        unsigned int    have_mic:1;
+        unsigned int    have_lout:1;
+
+        int             amp_gpio;
+        int             amp_gain[2];
+
+        void    (*startup)(void);
+};
+
+extern int simtec_audio_add(const char *codec_name,
+                            struct s3c24xx_audio_simtec_pdata *pdata);
diff --git a/arch/arm/plat-s3c/include/plat/cpu-freq.h b/arch/arm/plat-s3c/include/plat/cpu-freq.h
index c86a13307e90..7b982b7f28cd 100644
--- a/arch/arm/plat-s3c/include/plat/cpu-freq.h
+++ b/arch/arm/plat-s3c/include/plat/cpu-freq.h
@@ -17,6 +17,21 @@ struct s3c_cpufreq_info;
 struct s3c_cpufreq_board;
 struct s3c_iotimings;
 
+/**
+ * struct s3c_freq - frequency information (mainly for core drivers)
+ * @fclk: The FCLK frequency in Hz.
+ * @armclk: The ARMCLK frequency in Hz.
+ * @hclk_tns: HCLK cycle time in 10ths of nano-seconds.
+ * @hclk: The HCLK frequency in Hz.
+ * @pclk: The PCLK frequency in Hz.
+ *
+ * This contains the frequency information about the current configuration
+ * mainly for the core drivers to ensure we do not end up passing about
+ * a large number of parameters.
+ *
+ * The @hclk_tns field is a useful cache for the parts of the drivers that
+ * need to calculate IO timings and suchlike.
+ */
 struct s3c_freq {
         unsigned long   fclk;
         unsigned long   armclk;
@@ -25,48 +40,84 @@ struct s3c_freq {
         unsigned long   pclk;
 };
 
-/* wrapper 'struct cpufreq_freqs' so that any drivers receiving the
+/**
+ * struct s3c_cpufreq_freqs - s3c cpufreq notification information.
+ * @freqs: The cpufreq setting information.
+ * @old: The old clock settings.
+ * @new: The new clock settings.
+ * @pll_changing: Set if the PLL is changing.
+ *
+ * Wrapper 'struct cpufreq_freqs' so that any drivers receiving the
  * notification can use this information that is not provided by just
  * having the core frequency alone.
+ *
+ * The pll_changing flag is used to indicate if the PLL itself is
+ * being set during this change. This is important as the clocks
+ * will temporarily be set to the XTAL clock during this time, so
+ * drivers may want to close down their output during this time.
+ *
+ * Note, this is not being used by any current drivers and therefore
+ * may be removed in the future.
  */
-
 struct s3c_cpufreq_freqs {
         struct cpufreq_freqs    freqs;
         struct s3c_freq         old;
         struct s3c_freq         new;
+
+        unsigned int            pll_changing:1;
 };
 
 #define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
 
+/**
+ * struct s3c_clkdivs - clock divisor information
+ * @p_divisor: Divisor from FCLK to PCLK.
+ * @h_divisor: Divisor from FCLK to HCLK.
+ * @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs).
+ * @dvs: Non-zero if using DVS mode for ARMCLK.
+ *
+ * Divisor settings for the core clocks.
+ */
 struct s3c_clkdivs {
-        int             p_divisor;      /* fclk / pclk */
-        int             h_divisor;      /* fclk / hclk */
-        int             arm_divisor;    /* not all cpus have this. */
-        unsigned char   dvs;            /* using dvs mode to arm. */
+        int             p_divisor;
+        int             h_divisor;
+        int             arm_divisor;
+        unsigned char   dvs;
 };
 
 #define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
 
+/**
+ * struct s3c_pllval - PLL value entry.
+ * @freq: The frequency for this entry in Hz.
+ * @pll_reg: The PLL register setting for this PLL value.
+ */
 struct s3c_pllval {
         unsigned long           freq;
         unsigned long           pll_reg;
 };
 
-struct s3c_cpufreq_config {
-        struct s3c_freq         freq;
-        struct s3c_pllval       pll;
-        struct s3c_clkdivs      divs;
-        struct s3c_cpufreq_info *info;  /* for core, not drivers */
-        struct s3c_cpufreq_board *board;
-};
-
-/* s3c_cpufreq_board
+/**
+ * struct s3c_cpufreq_board - per-board cpu frequency informatin
+ * @refresh: The SDRAM refresh period in nanoseconds.
+ * @auto_io: Set if the IO timing settings should be generated from the
+ *      initialisation time hardware registers.
+ * @need_io: Set if the board has external IO on any of the chipselect
+ *      lines that will require the hardware timing registers to be
+ *      updated on a clock change.
+ * @max: The maxium frequency limits for the system. Any field that
+ *      is left at zero will use the CPU's settings.
+ *
+ * This contains the board specific settings that affect how the CPU
+ * drivers chose settings. These include the memory refresh and IO
+ * timing information.
  *
- * per-board configuraton information, such as memory refresh and
- * how to initialise IO timings.
+ * Registration depends on the driver being used, the ARMCLK only
+ * implementation does not currently need this but the older style
+ * driver requires this to be available.
  */
 struct s3c_cpufreq_board {
-        unsigned int    refresh;        /* refresh period in ns */
+        unsigned int    refresh;
         unsigned int    auto_io:1;      /* automatically init io timings. */
         unsigned int    need_io:1;      /* set if needs io timing support. */
 
diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h
index be541cbba070..fbc3d498e02e 100644
--- a/arch/arm/plat-s3c/include/plat/cpu.h
+++ b/arch/arm/plat-s3c/include/plat/cpu.h
@@ -65,6 +65,7 @@ extern struct sys_timer s3c24xx_timer;
 /* system device classes */
 
 extern struct sysdev_class s3c2410_sysclass;
+extern struct sysdev_class s3c2410a_sysclass;
 extern struct sysdev_class s3c2412_sysclass;
 extern struct sysdev_class s3c2440_sysclass;
 extern struct sysdev_class s3c2442_sysclass;
diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h
index 2e170827e0b0..0f540ea1e999 100644
--- a/arch/arm/plat-s3c/include/plat/devs.h
+++ b/arch/arm/plat-s3c/include/plat/devs.h
@@ -46,6 +46,8 @@ extern struct platform_device s3c_device_hsmmc2;
 extern struct platform_device s3c_device_spi0;
 extern struct platform_device s3c_device_spi1;
 
+extern struct platform_device s3c_device_hwmon;
+
 extern struct platform_device s3c_device_nand;
 
 extern struct platform_device s3c_device_usbgadget;
@@ -56,5 +58,6 @@ extern struct platform_device s3c_device_usb_hsotg;
 #ifdef CONFIG_CPU_S3C2440
 
 extern struct platform_device s3c_device_camif;
+extern struct platform_device s3c_device_ac97;
 
 #endif
diff --git a/arch/arm/plat-s3c/include/plat/hwmon.h b/arch/arm/plat-s3c/include/plat/hwmon.h
new file mode 100644
index 000000000000..1ba88ea0aa31
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/hwmon.h
@@ -0,0 +1,41 @@
+/* linux/arch/arm/plat-s3c/include/plat/hwmon.h
+ *
+ * Copyright 2005 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C - HWMon interface for ADC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_ADC_HWMON_H
+#define __ASM_ARCH_ADC_HWMON_H __FILE__
+
+/**
+ * s3c_hwmon_chcfg - channel configuration
+ * @name: The name to give this channel.
+ * @mult: Multiply the ADC value read by this.
+ * @div: Divide the value from the ADC by this.
+ *
+ * The value read from the ADC is converted to a value that
+ * hwmon expects (mV) by result = (value_read * @mult) / @div.
+ */
+struct s3c_hwmon_chcfg {
+        const char      *name;
+        unsigned int    mult;
+        unsigned int    div;
+};
+
+/**
+ * s3c_hwmon_pdata - HWMON platform data
+ * @in: One configuration for each possible channel used.
+ */
+struct s3c_hwmon_pdata {
+        struct s3c_hwmon_chcfg  *in[8];
+};
+
+#endif /* __ASM_ARCH_ADC_HWMON_H */
+
diff --git a/arch/arm/plat-s3c/include/plat/map-base.h b/arch/arm/plat-s3c/include/plat/map-base.h
index b84289d32a54..250be311c85b 100644
--- a/arch/arm/plat-s3c/include/plat/map-base.h
+++ b/arch/arm/plat-s3c/include/plat/map-base.h
@@ -32,9 +32,15 @@
 
 #define S3C_VA_IRQ      S3C_ADDR(0x00000000)    /* irq controller(s) */
 #define S3C_VA_SYS      S3C_ADDR(0x00100000)    /* system control */
-#define S3C_VA_MEM      S3C_ADDR(0x00200000)    /* system control */
+#define S3C_VA_MEM      S3C_ADDR(0x00200000)    /* memory control */
 #define S3C_VA_TIMER    S3C_ADDR(0x00300000)    /* timer block */
 #define S3C_VA_WATCHDOG S3C_ADDR(0x00400000)    /* watchdog */
 #define S3C_VA_UART     S3C_ADDR(0x01000000)    /* UART */
 
+/* This is used for the CPU specific mappings that may be needed, so that
+ * they do not need to directly used S3C_ADDR() and thus make it easier to
+ * modify the space for mapping.
+ */
+#define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x))
+
 #endif /* __ASM_PLAT_MAP_H */
diff --git a/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h b/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h
index 0fad7571030e..07659dad1748 100644
--- a/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h
+++ b/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h
@@ -33,6 +33,11 @@
 #define S3C2412_IISCON_RXDMA_ACTIVE     (1 << 1)
 #define S3C2412_IISCON_IIS_ACTIVE       (1 << 0)
 
+#define S3C64XX_IISMOD_BLC_16BIT        (0 << 13)
+#define S3C64XX_IISMOD_BLC_8BIT         (1 << 13)
+#define S3C64XX_IISMOD_BLC_24BIT        (2 << 13)
+#define S3C64XX_IISMOD_BLC_MASK         (3 << 13)
+
 #define S3C64XX_IISMOD_IMS_PCLK         (0 << 10)
 #define S3C64XX_IISMOD_IMS_SYSMUX       (1 << 10)
 
diff --git a/arch/arm/plat-s3c24xx/pwm.c b/arch/arm/plat-s3c/pwm.c
index 82a6d4de02a3..4fdc5b307fd2 100644
--- a/arch/arm/plat-s3c24xx/pwm.c
+++ b/arch/arm/plat-s3c/pwm.c
@@ -1,10 +1,10 @@
-/* arch/arm/plat-s3c24xx/pwm.c
+/* arch/arm/plat-s3c/pwm.c
  *
  * Copyright (c) 2007 Ben Dooks
  * Copyright (c) 2008 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
  *
- * S3C24XX PWM device core
+ * S3C series PWM device core
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -20,6 +20,7 @@
 #include <linux/pwm.h>
 
 #include <mach/irqs.h>
+#include <mach/map.h>
 
 #include <plat/devs.h>
 #include <plat/regs-timer.h>
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 5b0bc914f58e..9c7aca489643 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -10,6 +10,7 @@ config PLAT_S3C24XX
         default y
         select NO_IOPORT
         select ARCH_REQUIRE_GPIOLIB
+        select S3C_DEVICE_NAND
         help
           Base platform code for any Samsung S3C24XX device
 
@@ -34,6 +35,40 @@ config CPU_S3C244X
         help
           Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
 
+config S3C2440_CPUFREQ
+        bool "S3C2440/S3C2442 CPU Frequency scaling support"
+        depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
+        select S3C2410_CPUFREQ_UTILS
+        default y
+        help
+          CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
+
+config S3C2440_XTAL_12000000
+        bool
+        help
+          Indicate that the build needs to support 12MHz system
+          crystal.
+
+config S3C2440_XTAL_16934400
+        bool
+        help
+          Indicate that the build needs to support 16.9344MHz system
+          crystal.
+
+config S3C2440_PLL_12000000
+        bool
+        depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000
+        default y if CPU_FREQ_S3C24XX_PLL
+        help
+          PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
+
+config S3C2440_PLL_16934400
+        bool
+        depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400
+        default y if CPU_FREQ_S3C24XX_PLL
+        help
+          PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
+
 config S3C24XX_PWM
         bool "PWM device support"
         select HAVE_PWM
@@ -105,8 +140,39 @@ config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7
           SPI GPIO configuration code for BUS 1 when connected to
           GPG5, GPG6 and GPG7.
 
+config S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10
+        bool
+        help
+          SPI GPIO configuration code for BUS 1 when connected to
+          GPD8, GPD9 and GPD10.
+
 # common code for s3c24xx based machines, such as the SMDKs.
 
+# cpu frequency items common between s3c2410 and s3c2440/s3c2442
+
+config S3C2410_IOTIMING
+        bool
+        depends on CPU_FREQ_S3C24XX
+        help
+          Internal node to select io timing code that is common to the s3c2410
+          and s3c2440/s3c2442 cpu frequency support.
+
+config S3C2410_CPUFREQ_UTILS
+        bool
+        depends on CPU_FREQ_S3C24XX
+        help
+          Internal node to select timing code that is common to the s3c2410
+          and s3c2440/s3c244 cpu frequency support.
+
+# cpu frequency support common to s3c2412, s3c2413 and s3c2442
+
+config S3C2412_IOTIMING
+        bool
+        depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
+        help
+          Intel node to select io timing code that is common to the s3c2412
+          and the s3c2443.
+
 config MACH_SMDK
         bool
         help
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 579a165c2827..7780d2dd833a 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -20,19 +20,28 @@ obj-y				+= gpiolib.o
 obj-y                           += clock.o
 obj-$(CONFIG_S3C24XX_DCLK)      += clock-dclk.o
 
+obj-$(CONFIG_CPU_FREQ_S3C24XX)  += cpu-freq.o
+obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
+
 # Architecture dependant builds
 
 obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o
 obj-$(CONFIG_CPU_S3C244X)       += s3c244x-irq.o
 obj-$(CONFIG_CPU_S3C244X)       += s3c244x-clock.o
+obj-$(CONFIG_S3C2440_CPUFREQ)   += s3c2440-cpufreq.o
+obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o
+obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o
+
 obj-$(CONFIG_PM_SIMTEC)         += pm-simtec.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM)                += irq-pm.o
 obj-$(CONFIG_PM)                += sleep.o
-obj-$(CONFIG_S3C24XX_PWM)       += pwm.o
 obj-$(CONFIG_S3C2410_CLOCK)     += s3c2410-clock.o
 obj-$(CONFIG_S3C2410_DMA)       += dma.o
 obj-$(CONFIG_S3C24XX_ADC)       += adc.o
+obj-$(CONFIG_S3C2410_IOTIMING)  += s3c2410-iotiming.o
+obj-$(CONFIG_S3C2412_IOTIMING)  += s3c2412-iotiming.o
+obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o
 
 # device specific setup and/or initialisation
 obj-$(CONFIG_ARCH_S3C2410)      += setup-i2c.o
@@ -41,6 +50,7 @@ obj-$(CONFIG_ARCH_S3C2410)	+= setup-i2c.o
 
 obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o
 obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7)    += spi-bus1-gpg5_6_7.o
+obj-$(CONFIG_S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10)   += spi-bus1-gpd8_9_10.o
 
 # machine common support
 
diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-s3c24xx/adc.c
index ee1baf11ad9e..11117a7ba911 100644
--- a/arch/arm/plat-s3c24xx/adc.c
+++ b/arch/arm/plat-s3c24xx/adc.c
@@ -39,13 +39,16 @@
 struct s3c_adc_client {
         struct platform_device  *pdev;
         struct list_head         pend;
+        wait_queue_head_t       *wait;
 
         unsigned int             nr_samples;
+        int                      result;
         unsigned char            is_ts;
         unsigned char            channel;
 
-        void    (*select_cb)(unsigned selected);
-        void    (*convert_cb)(unsigned val1, unsigned val2,
+        void    (*select_cb)(struct s3c_adc_client *c, unsigned selected);
+        void    (*convert_cb)(struct s3c_adc_client *c,
+                              unsigned val1, unsigned val2,
                               unsigned *samples_left);
 };
 
@@ -81,7 +84,7 @@ static inline void s3c_adc_select(struct adc_device *adc,
 {
         unsigned con = readl(adc->regs + S3C2410_ADCCON);
 
-        client->select_cb(1);
+        client->select_cb(client, 1);
 
         con &= ~S3C2410_ADCCON_MUXMASK;
         con &= ~S3C2410_ADCCON_STDBM;
@@ -153,25 +156,61 @@ int s3c_adc_start(struct s3c_adc_client *client,
 }
 EXPORT_SYMBOL_GPL(s3c_adc_start);
 
-static void s3c_adc_default_select(unsigned select)
+static void s3c_convert_done(struct s3c_adc_client *client,
+                             unsigned v, unsigned u, unsigned *left)
+{
+        client->result = v;
+        wake_up(client->wait);
+}
+
+int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch)
+{
+        DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake);
+        int ret;
+
+        client->convert_cb = s3c_convert_done;
+        client->wait = &wake;
+        client->result = -1;
+
+        ret = s3c_adc_start(client, ch, 1);
+        if (ret < 0)
+                goto err;
+
+        ret = wait_event_timeout(wake, client->result >= 0, HZ / 2);
+        if (client->result < 0) {
+                ret = -ETIMEDOUT;
+                goto err;
+        }
+
+        client->convert_cb = NULL;
+        return client->result;
+
+err:
+        return ret;
+}
+EXPORT_SYMBOL_GPL(s3c_adc_convert);
+
+static void s3c_adc_default_select(struct s3c_adc_client *client,
+                                   unsigned select)
 {
 }
 
 struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
-                                        void (*select)(unsigned int selected),
-                                        void (*conv)(unsigned d0, unsigned d1,
+                                        void (*select)(struct s3c_adc_client *client,
+                                                       unsigned int selected),
+                                        void (*conv)(struct s3c_adc_client *client,
+                                                     unsigned d0, unsigned d1,
                                                      unsigned *samples_left),
                                         unsigned int is_ts)
 {
         struct s3c_adc_client *client;
 
         WARN_ON(!pdev);
-        WARN_ON(!conv);
 
         if (!select)
                 select = s3c_adc_default_select;
 
-        if (!conv || !pdev)
+        if (!pdev)
                 return ERR_PTR(-EINVAL);
 
         client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL);
@@ -230,16 +269,19 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
         adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
 
         client->nr_samples--;
-        (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff, &client->nr_samples);
+
+        if (client->convert_cb)
+                (client->convert_cb)(client, data0 & 0x3ff, data1 & 0x3ff,
+                                     &client->nr_samples);
 
         if (client->nr_samples > 0) {
                 /* fire another conversion for this */
 
-                client->select_cb(1);
+                client->select_cb(client, 1);
                 s3c_adc_convert(adc);
         } else {
                 local_irq_save(flags);
-                (client->select_cb)(0);
+                (client->select_cb)(client, 0);
                 adc->cur = NULL;
 
                 s3c_adc_try(adc);
diff --git a/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c b/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
new file mode 100644
index 000000000000..a9276667c2fb
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
@@ -0,0 +1,199 @@
+/* linux/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
+ *
+ * Copyright (c) 2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX CPU Frequency scaling - debugfs status support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/err.h>
+
+#include <plat/cpu-freq-core.h>
+
+static struct dentry *dbgfs_root;
+static struct dentry *dbgfs_file_io;
+static struct dentry *dbgfs_file_info;
+static struct dentry *dbgfs_file_board;
+
+#define print_ns(x) ((x) / 10), ((x) % 10)
+
+static void show_max(struct seq_file *seq, struct s3c_freq *f)
+{
+        seq_printf(seq, "MAX: F=%lu, H=%lu, P=%lu, A=%lu\n",
+                   f->fclk, f->hclk, f->pclk, f->armclk);
+}
+
+static int board_show(struct seq_file *seq, void *p)
+{
+        struct s3c_cpufreq_config *cfg;
+        struct s3c_cpufreq_board *brd;
+
+        cfg = s3c_cpufreq_getconfig();
+        if (!cfg) {
+                seq_printf(seq, "no configuration registered\n");
+                return 0;
+        }
+
+        brd = cfg->board;
+        if (!brd) {
+                seq_printf(seq, "no board definition set?\n");
+                return 0;
+        }
+
+        seq_printf(seq, "SDRAM refresh %u ns\n", brd->refresh);
+        seq_printf(seq, "auto_io=%u\n", brd->auto_io);
+        seq_printf(seq, "need_io=%u\n", brd->need_io);
+
+        show_max(seq, &brd->max);
+
+
+        return 0;
+}
+
+static int fops_board_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, board_show, NULL);
+}
+
+static const struct file_operations fops_board = {
+        .open           = fops_board_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .owner          = THIS_MODULE,
+};
+
+static int info_show(struct seq_file *seq, void *p)
+{
+        struct s3c_cpufreq_config *cfg;
+
+        cfg = s3c_cpufreq_getconfig();
+        if (!cfg) {
+                seq_printf(seq, "no configuration registered\n");
+                return 0;
+        }
+
+        seq_printf(seq, "  FCLK %ld Hz\n", cfg->freq.fclk);
+        seq_printf(seq, "  HCLK %ld Hz (%lu.%lu ns)\n",
+                   cfg->freq.hclk, print_ns(cfg->freq.hclk_tns));
+        seq_printf(seq, "  PCLK %ld Hz\n", cfg->freq.hclk);
+        seq_printf(seq, "ARMCLK %ld Hz\n", cfg->freq.armclk);
+        seq_printf(seq, "\n");
+
+        show_max(seq, &cfg->max);
+
+        seq_printf(seq, "Divisors: P=%d, H=%d, A=%d, dvs=%s\n",
+                   cfg->divs.h_divisor, cfg->divs.p_divisor,
+                   cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off");
+        seq_printf(seq, "\n");
+
+        seq_printf(seq, "lock_pll=%u\n", cfg->lock_pll);
+
+        return 0;
+}
+
+static int fops_info_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, info_show, NULL);
+}
+
+static const struct file_operations fops_info = {
+        .open           = fops_info_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .owner          = THIS_MODULE,
+};
+
+static int io_show(struct seq_file *seq, void *p)
+{
+        void (*show_bank)(struct seq_file *, struct s3c_cpufreq_config *, union s3c_iobank *);
+        struct s3c_cpufreq_config *cfg;
+        struct s3c_iotimings *iot;
+        union s3c_iobank *iob;
+        int bank;
+
+        cfg = s3c_cpufreq_getconfig();
+        if (!cfg) {
+                seq_printf(seq, "no configuration registered\n");
+                return 0;
+        }
+
+        show_bank = cfg->info->debug_io_show;
+        if (!show_bank) {
+                seq_printf(seq, "no code to show bank timing\n");
+                return 0;
+        }
+
+        iot = s3c_cpufreq_getiotimings();
+        if (!iot) {
+                seq_printf(seq, "no io timings registered\n");
+                return 0;
+        }
+
+        seq_printf(seq, "hclk period is %lu.%lu ns\n", print_ns(cfg->freq.hclk_tns));
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                iob = &iot->bank[bank];
+
+                seq_printf(seq, "bank %d: ", bank);
+
+                if (!iob->io_2410) {
+                        seq_printf(seq, "nothing set\n");
+                        continue;
+                }
+
+                show_bank(seq, cfg, iob);
+        }
+
+        return 0;
+}
+
+static int fops_io_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, io_show, NULL);
+}
+
+static const struct file_operations fops_io = {
+        .open           = fops_io_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .owner          = THIS_MODULE,
+};
+
+
+static int __init s3c_freq_debugfs_init(void)
+{
+        dbgfs_root = debugfs_create_dir("s3c-cpufreq", NULL);
+        if (IS_ERR(dbgfs_root)) {
+                printk(KERN_ERR "%s: error creating debugfs root\n", __func__);
+                return PTR_ERR(dbgfs_root);
+        }
+
+        dbgfs_file_io = debugfs_create_file("io-timing", S_IRUGO, dbgfs_root,
+                                            NULL, &fops_io);
+
+        dbgfs_file_info = debugfs_create_file("info", S_IRUGO, dbgfs_root,
+                                              NULL, &fops_info);
+
+        dbgfs_file_board = debugfs_create_file("board", S_IRUGO, dbgfs_root,
+                                               NULL, &fops_board);
+
+        return 0;
+}
+
+late_initcall(s3c_freq_debugfs_init);
+
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c
new file mode 100644
index 000000000000..4f1b789a1173
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/cpu-freq.c
@@ -0,0 +1,716 @@
+/* linux/arch/arm/plat-s3c24xx/cpu-freq.c
+ *
+ * Copyright (c) 2006,2007,2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX CPU Frequency scaling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/cpu.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/cpu-freq-core.h>
+
+#include <mach/regs-clock.h>
+
+/* note, cpufreq support deals in kHz, no Hz */
+
+static struct cpufreq_driver s3c24xx_driver;
+static struct s3c_cpufreq_config cpu_cur;
+static struct s3c_iotimings s3c24xx_iotiming;
+static struct cpufreq_frequency_table *pll_reg;
+static unsigned int last_target = ~0;
+static unsigned int ftab_size;
+static struct cpufreq_frequency_table *ftab;
+
+static struct clk *_clk_mpll;
+static struct clk *_clk_xtal;
+static struct clk *clk_fclk;
+static struct clk *clk_hclk;
+static struct clk *clk_pclk;
+static struct clk *clk_arm;
+
+#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
+struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void)
+{
+        return &cpu_cur;
+}
+
+struct s3c_iotimings *s3c_cpufreq_getiotimings(void)
+{
+        return &s3c24xx_iotiming;
+}
+#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUGFS */
+
+static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long fclk, pclk, hclk, armclk;
+
+        cfg->freq.fclk = fclk = clk_get_rate(clk_fclk);
+        cfg->freq.hclk = hclk = clk_get_rate(clk_hclk);
+        cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
+        cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
+
+        cfg->pll.index = __raw_readl(S3C2410_MPLLCON);
+        cfg->pll.frequency = fclk;
+
+        cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
+
+        cfg->divs.h_divisor = fclk / hclk;
+        cfg->divs.p_divisor = fclk / pclk;
+}
+
+static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long pll = cfg->pll.frequency;
+
+        cfg->freq.fclk = pll;
+        cfg->freq.hclk = pll / cfg->divs.h_divisor;
+        cfg->freq.pclk = pll / cfg->divs.p_divisor;
+
+        /* convert hclk into 10ths of nanoseconds for io calcs */
+        cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
+}
+
+static inline int closer(unsigned int target, unsigned int n, unsigned int c)
+{
+        int diff_cur = abs(target - c);
+        int diff_new = abs(target - n);
+
+        return (diff_new < diff_cur);
+}
+
+static void s3c_cpufreq_show(const char *pfx,
+                                 struct s3c_cpufreq_config *cfg)
+{
+        s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n",
+                     pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk,
+                     cfg->freq.hclk, cfg->divs.h_divisor,
+                     cfg->freq.pclk, cfg->divs.p_divisor);
+}
+
+/* functions to wrapper the driver info calls to do the cpu specific work */
+
+static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg)
+{
+        if (cfg->info->set_iotiming)
+                (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming);
+}
+
+static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg)
+{
+        if (cfg->info->calc_iotiming)
+                return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming);
+
+        return 0;
+}
+
+static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
+{
+        (cfg->info->set_refresh)(cfg);
+}
+
+static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        (cfg->info->set_divs)(cfg);
+}
+
+static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        return (cfg->info->calc_divs)(cfg);
+}
+
+static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
+{
+        (cfg->info->set_fvco)(cfg);
+}
+
+static inline void s3c_cpufreq_resume_clocks(void)
+{
+        cpu_cur.info->resume_clocks();
+}
+
+static inline void s3c_cpufreq_updateclk(struct clk *clk,
+                                         unsigned int freq)
+{
+        clk_set_rate(clk, freq);
+}
+
+static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
+                                 unsigned int target_freq,
+                                 struct cpufreq_frequency_table *pll)
+{
+        struct s3c_cpufreq_freqs freqs;
+        struct s3c_cpufreq_config cpu_new;
+        unsigned long flags;
+
+        cpu_new = cpu_cur;  /* copy new from current */
+
+        s3c_cpufreq_show("cur", &cpu_cur);
+
+        /* TODO - check for DMA currently outstanding */
+
+        cpu_new.pll = pll ? *pll : cpu_cur.pll;
+
+        if (pll)
+                freqs.pll_changing = 1;
+
+        /* update our frequencies */
+
+        cpu_new.freq.armclk = target_freq;
+        cpu_new.freq.fclk = cpu_new.pll.frequency;
+
+        if (s3c_cpufreq_calcdivs(&cpu_new) < 0) {
+                printk(KERN_ERR "no divisors for %d\n", target_freq);
+                goto err_notpossible;
+        }
+
+        s3c_freq_dbg("%s: got divs\n", __func__);
+
+        s3c_cpufreq_calc(&cpu_new);
+
+        s3c_freq_dbg("%s: calculated frequencies for new\n", __func__);
+
+        if (cpu_new.freq.hclk != cpu_cur.freq.hclk) {
+                if (s3c_cpufreq_calcio(&cpu_new) < 0) {
+                        printk(KERN_ERR "%s: no IO timings\n", __func__);
+                        goto err_notpossible;
+                }
+        }
+
+        s3c_cpufreq_show("new", &cpu_new);
+
+        /* setup our cpufreq parameters */
+
+        freqs.old = cpu_cur.freq;
+        freqs.new = cpu_new.freq;
+
+        freqs.freqs.cpu = 0;
+        freqs.freqs.old = cpu_cur.freq.armclk / 1000;
+        freqs.freqs.new = cpu_new.freq.armclk / 1000;
+
+        /* update f/h/p clock settings before we issue the change
+         * notification, so that drivers do not need to do anything
+         * special if they want to recalculate on CPUFREQ_PRECHANGE. */
+
+        s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency);
+        s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk);
+        s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk);
+        s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk);
+
+        /* start the frequency change */
+
+        if (policy)
+                cpufreq_notify_transition(&freqs.freqs, CPUFREQ_PRECHANGE);
+
+        /* If hclk is staying the same, then we do not need to
+         * re-write the IO or the refresh timings whilst we are changing
+         * speed. */
+
+        local_irq_save(flags);
+
+        /* is our memory clock slowing down? */
+        if (cpu_new.freq.hclk < cpu_cur.freq.hclk) {
+                s3c_cpufreq_setrefresh(&cpu_new);
+                s3c_cpufreq_setio(&cpu_new);
+        }
+
+        if (cpu_new.freq.fclk == cpu_cur.freq.fclk) {
+                /* not changing PLL, just set the divisors */
+
+                s3c_cpufreq_setdivs(&cpu_new);
+        } else {
+                if (cpu_new.freq.fclk < cpu_cur.freq.fclk) {
+                        /* slow the cpu down, then set divisors */
+
+                        s3c_cpufreq_setfvco(&cpu_new);
+                        s3c_cpufreq_setdivs(&cpu_new);
+                } else {
+                        /* set the divisors, then speed up */
+
+                        s3c_cpufreq_setdivs(&cpu_new);
+                        s3c_cpufreq_setfvco(&cpu_new);
+                }
+        }
+
+        /* did our memory clock speed up */
+        if (cpu_new.freq.hclk > cpu_cur.freq.hclk) {
+                s3c_cpufreq_setrefresh(&cpu_new);
+                s3c_cpufreq_setio(&cpu_new);
+        }
+
+        /* update our current settings */
+        cpu_cur = cpu_new;
+
+        local_irq_restore(flags);
+
+        /* notify everyone we've done this */
+        if (policy)
+                cpufreq_notify_transition(&freqs.freqs, CPUFREQ_POSTCHANGE);
+
+        s3c_freq_dbg("%s: finished\n", __func__);
+        return 0;
+
+ err_notpossible:
+        printk(KERN_ERR "no compatible settings for %d\n", target_freq);
+        return -EINVAL;
+}
+
+/* s3c_cpufreq_target
+ *
+ * called by the cpufreq core to adjust the frequency that the CPU
+ * is currently running at.
+ */
+
+static int s3c_cpufreq_target(struct cpufreq_policy *policy,
+                              unsigned int target_freq,
+                              unsigned int relation)
+{
+        struct cpufreq_frequency_table *pll;
+        unsigned int index;
+
+        /* avoid repeated calls which cause a needless amout of duplicated
+         * logging output (and CPU time as the calculation process is
+         * done) */
+        if (target_freq == last_target)
+                return 0;
+
+        last_target = target_freq;
+
+        s3c_freq_dbg("%s: policy %p, target %u, relation %u\n",
+                     __func__, policy, target_freq, relation);
+
+        if (ftab) {
+                if (cpufreq_frequency_table_target(policy, ftab,
+                                                   target_freq, relation,
+                                                   &index)) {
+                        s3c_freq_dbg("%s: table failed\n", __func__);
+                        return -EINVAL;
+                }
+
+                s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__,
+                             target_freq, index, ftab[index].frequency);
+                target_freq = ftab[index].frequency;
+        }
+
+        target_freq *= 1000;  /* convert target to Hz */
+
+        /* find the settings for our new frequency */
+
+        if (!pll_reg || cpu_cur.lock_pll) {
+                /* either we've not got any PLL values, or we've locked
+                 * to the current one. */
+                pll = NULL;
+        } else {
+                struct cpufreq_policy tmp_policy;
+                int ret;
+
+                /* we keep the cpu pll table in Hz, to ensure we get an
+                 * accurate value for the PLL output. */
+
+                tmp_policy.min = policy->min * 1000;
+                tmp_policy.max = policy->max * 1000;
+                tmp_policy.cpu = policy->cpu;
+
+                /* cpufreq_frequency_table_target uses a pointer to 'index'
+                 * which is the number of the table entry, not the value of
+                 * the table entry's index field. */
+
+                ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg,
+                                                     target_freq, relation,
+                                                     &index);
+
+                if (ret < 0) {
+                        printk(KERN_ERR "%s: no PLL available\n", __func__);
+                        goto err_notpossible;
+                }
+
+                pll = pll_reg + index;
+
+                s3c_freq_dbg("%s: target %u => %u\n",
+                             __func__, target_freq, pll->frequency);
+
+                target_freq = pll->frequency;
+        }
+
+        return s3c_cpufreq_settarget(policy, target_freq, pll);
+
+ err_notpossible:
+        printk(KERN_ERR "no compatible settings for %d\n", target_freq);
+        return -EINVAL;
+}
+
+static unsigned int s3c_cpufreq_get(unsigned int cpu)
+{
+        return clk_get_rate(clk_arm) / 1000;
+}
+
+struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name)
+{
+        struct clk *clk;
+
+        clk = clk_get(dev, name);
+        if (IS_ERR(clk))
+                printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name);
+
+        return clk;
+}
+
+static int s3c_cpufreq_init(struct cpufreq_policy *policy)
+{
+        printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy);
+
+        if (policy->cpu != 0)
+                return -EINVAL;
+
+        policy->cur = s3c_cpufreq_get(0);
+        policy->min = policy->cpuinfo.min_freq = 0;
+        policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000;
+        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+
+        /* feed the latency information from the cpu driver */
+        policy->cpuinfo.transition_latency = cpu_cur.info->latency;
+
+        if (ftab)
+                cpufreq_frequency_table_cpuinfo(policy, ftab);
+
+        return 0;
+}
+
+static __init int s3c_cpufreq_initclks(void)
+{
+        _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll");
+        _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal");
+        clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk");
+        clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk");
+        clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk");
+        clk_arm = s3c_cpufreq_clk_get(NULL, "armclk");
+
+        if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) ||
+            IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) {
+                printk(KERN_ERR "%s: could not get clock(s)\n", __func__);
+                return -ENOENT;
+        }
+
+        printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__,
+               clk_get_rate(clk_fclk) / 1000,
+               clk_get_rate(clk_hclk) / 1000,
+               clk_get_rate(clk_pclk) / 1000,
+               clk_get_rate(clk_arm) / 1000);
+
+        return 0;
+}
+
+static int s3c_cpufreq_verify(struct cpufreq_policy *policy)
+{
+        if (policy->cpu != 0)
+                return -EINVAL;
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static struct cpufreq_frequency_table suspend_pll;
+static unsigned int suspend_freq;
+
+static int s3c_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg)
+{
+        suspend_pll.frequency = clk_get_rate(_clk_mpll);
+        suspend_pll.index = __raw_readl(S3C2410_MPLLCON);
+        suspend_freq = s3c_cpufreq_get(0) * 1000;
+
+        return 0;
+}
+
+static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
+{
+        int ret;
+
+        s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy);
+
+        last_target = ~0;       /* invalidate last_target setting */
+
+        /* first, find out what speed we resumed at. */
+        s3c_cpufreq_resume_clocks();
+
+        /* whilst we will be called later on, we try and re-set the
+         * cpu frequencies as soon as possible so that we do not end
+         * up resuming devices and then immediatley having to re-set
+         * a number of settings once these devices have restarted.
+         *
+         * as a note, it is expected devices are not used until they
+         * have been un-suspended and at that time they should have
+         * used the updated clock settings.
+         */
+
+        ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll);
+        if (ret) {
+                printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__);
+                return ret;
+        }
+
+        return 0;
+}
+#else
+#define s3c_cpufreq_resume NULL
+#define s3c_cpufreq_suspend NULL
+#endif
+
+static struct cpufreq_driver s3c24xx_driver = {
+        .flags          = CPUFREQ_STICKY,
+        .verify         = s3c_cpufreq_verify,
+        .target         = s3c_cpufreq_target,
+        .get            = s3c_cpufreq_get,
+        .init           = s3c_cpufreq_init,
+        .suspend        = s3c_cpufreq_suspend,
+        .resume         = s3c_cpufreq_resume,
+        .name           = "s3c24xx",
+};
+
+
+int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info)
+{
+        if (!info || !info->name) {
+                printk(KERN_ERR "%s: failed to pass valid information\n",
+                       __func__);
+                return -EINVAL;
+        }
+
+        printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n",
+               info->name);
+
+        /* check our driver info has valid data */
+
+        BUG_ON(info->set_refresh == NULL);
+        BUG_ON(info->set_divs == NULL);
+        BUG_ON(info->calc_divs == NULL);
+
+        /* info->set_fvco is optional, depending on whether there
+         * is a need to set the clock code. */
+
+        cpu_cur.info = info;
+
+        /* Note, driver registering should probably update locktime */
+
+        return 0;
+}
+
+int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
+{
+        struct s3c_cpufreq_board *ours;
+
+        if (!board) {
+                printk(KERN_INFO "%s: no board data\n", __func__);
+                return -EINVAL;
+        }
+
+        /* Copy the board information so that each board can make this
+         * initdata. */
+
+        ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL);
+        if (ours == NULL) {
+                printk(KERN_ERR "%s: no memory\n", __func__);
+                return -ENOMEM;
+        }
+
+        *ours = *board;
+        cpu_cur.board = ours;
+
+        return 0;
+}
+
+int __init s3c_cpufreq_auto_io(void)
+{
+        int ret;
+
+        if (!cpu_cur.info->get_iotiming) {
+                printk(KERN_ERR "%s: get_iotiming undefined\n", __func__);
+                return -ENOENT;
+        }
+
+        printk(KERN_INFO "%s: working out IO settings\n", __func__);
+
+        ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming);
+        if (ret)
+                printk(KERN_ERR "%s: failed to get timings\n", __func__);
+
+        return ret;
+}
+
+/* if one or is zero, then return the other, otherwise return the min */
+#define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b))
+
+/**
+ * s3c_cpufreq_freq_min - find the minimum settings for the given freq.
+ * @dst: The destination structure
+ * @a: One argument.
+ * @b: The other argument.
+ *
+ * Create a minimum of each frequency entry in the 'struct s3c_freq',
+ * unless the entry is zero when it is ignored and the non-zero argument
+ * used.
+ */
+static void s3c_cpufreq_freq_min(struct s3c_freq *dst,
+                                 struct s3c_freq *a, struct s3c_freq *b)
+{
+        dst->fclk = do_min(a->fclk, b->fclk);
+        dst->hclk = do_min(a->hclk, b->hclk);
+        dst->pclk = do_min(a->pclk, b->pclk);
+        dst->armclk = do_min(a->armclk, b->armclk);
+}
+
+static inline u32 calc_locktime(u32 freq, u32 time_us)
+{
+        u32 result;
+
+        result = freq * time_us;
+        result = DIV_ROUND_UP(result, 1000 * 1000);
+
+        return result;
+}
+
+static void s3c_cpufreq_update_loctkime(void)
+{
+        unsigned int bits = cpu_cur.info->locktime_bits;
+        u32 rate = (u32)clk_get_rate(_clk_xtal);
+        u32 val;
+
+        if (bits == 0) {
+                WARN_ON(1);
+                return;
+        }
+
+        val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits;
+        val |= calc_locktime(rate, cpu_cur.info->locktime_m);
+
+        printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val);
+        __raw_writel(val, S3C2410_LOCKTIME);
+}
+
+static int s3c_cpufreq_build_freq(void)
+{
+        int size, ret;
+
+        if (!cpu_cur.info->calc_freqtable)
+                return -EINVAL;
+
+        kfree(ftab);
+        ftab = NULL;
+
+        size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0);
+        size++;
+
+        ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL);
+        if (!ftab) {
+                printk(KERN_ERR "%s: no memory for tables\n", __func__);
+                return -ENOMEM;
+        }
+
+        ftab_size = size;
+
+        ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size);
+        s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END);
+
+        return 0;
+}
+
+static int __init s3c_cpufreq_initcall(void)
+{
+        int ret = 0;
+
+        if (cpu_cur.info && cpu_cur.board) {
+                ret = s3c_cpufreq_initclks();
+                if (ret)
+                        goto out;
+
+                /* get current settings */
+                s3c_cpufreq_getcur(&cpu_cur);
+                s3c_cpufreq_show("cur", &cpu_cur);
+
+                if (cpu_cur.board->auto_io) {
+                        ret = s3c_cpufreq_auto_io();
+                        if (ret) {
+                                printk(KERN_ERR "%s: failed to get io timing\n",
+                                       __func__);
+                                goto out;
+                        }
+                }
+
+                if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) {
+                        printk(KERN_ERR "%s: no IO support registered\n",
+                               __func__);
+                        ret = -EINVAL;
+                        goto out;
+                }
+
+                if (!cpu_cur.info->need_pll)
+                        cpu_cur.lock_pll = 1;
+
+                s3c_cpufreq_update_loctkime();
+
+                s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max,
+                                     &cpu_cur.info->max);
+
+                if (cpu_cur.info->calc_freqtable)
+                        s3c_cpufreq_build_freq();
+
+                ret = cpufreq_register_driver(&s3c24xx_driver);
+        }
+
+ out:
+        return ret;
+}
+
+late_initcall(s3c_cpufreq_initcall);
+
+/**
+ * s3c_plltab_register - register CPU PLL table.
+ * @plls: The list of PLL entries.
+ * @plls_no: The size of the PLL entries @plls.
+ *
+ * Register the given set of PLLs with the system.
+ */
+int __init s3c_plltab_register(struct cpufreq_frequency_table *plls,
+                               unsigned int plls_no)
+{
+        struct cpufreq_frequency_table *vals;
+        unsigned int size;
+
+        size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1);
+
+        vals = kmalloc(size, GFP_KERNEL);
+        if (vals) {
+                memcpy(vals, plls, size);
+                pll_reg = vals;
+
+                /* write a terminating entry, we don't store it in the
+                 * table that is stored in the kernel */
+                vals += plls_no;
+                vals->frequency = CPUFREQ_TABLE_END;
+
+                printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no);
+        } else
+                printk(KERN_ERR "cpufreq: no memory for PLL tables\n");
+
+        return vals ? 0 : -ENOMEM;
+}
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 1932b7e0da15..5447e60f3936 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -81,7 +81,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .map_io         = s3c2410_map_io,
                 .init_clocks    = s3c2410_init_clocks,
                 .init_uarts     = s3c2410_init_uarts,
-                .init           = s3c2410_init,
+                .init           = s3c2410a_init,
                 .name           = name_s3c2410a
         },
         {
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 4eb378c89a39..f52a92ce8dda 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -26,6 +26,8 @@
 #include <asm/mach/irq.h>
 #include <mach/fb.h>
 #include <mach/hardware.h>
+#include <mach/dma.h>
+#include <mach/irqs.h>
 #include <asm/irq.h>
 
 #include <plat/regs-serial.h>
@@ -180,25 +182,6 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
         }
 }
 
-/* NAND Controller */
-
-static struct resource s3c_nand_resource[] = {
-        [0] = {
-                .start = S3C24XX_PA_NAND,
-                .end   = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1,
-                .flags = IORESOURCE_MEM,
-        }
-};
-
-struct platform_device s3c_device_nand = {
-        .name             = "s3c2410-nand",
-        .id               = -1,
-        .num_resources    = ARRAY_SIZE(s3c_nand_resource),
-        .resource         = s3c_nand_resource,
-};
-
-EXPORT_SYMBOL(s3c_device_nand);
-
 /* USB Device (Gadget)*/
 
 static struct resource s3c_usbgadget_resource[] = {
@@ -348,7 +331,7 @@ struct platform_device s3c_device_adc = {
 /* HWMON */
 
 struct platform_device s3c_device_hwmon = {
-        .name           = "s3c24xx-hwmon",
+        .name           = "s3c-hwmon",
         .id             = -1,
         .dev.parent     = &s3c_device_adc.dev,
 };
@@ -473,4 +456,52 @@ struct platform_device s3c_device_camif = {
 
 EXPORT_SYMBOL(s3c_device_camif);
 
+/* AC97 */
+
+static struct resource s3c_ac97_resource[] = {
+        [0] = {
+                .start = S3C2440_PA_AC97,
+                .end   = S3C2440_PA_AC97 + S3C2440_SZ_AC97 -1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_S3C244x_AC97,
+                .end   = IRQ_S3C244x_AC97,
+                .flags = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .name  = "PCM out",
+                .start = DMACH_PCM_OUT,
+                .end   = DMACH_PCM_OUT,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .name  = "PCM in",
+                .start = DMACH_PCM_IN,
+                .end   = DMACH_PCM_IN,
+                .flags = IORESOURCE_DMA,
+        },
+        [4] = {
+                .name  = "Mic in",
+                .start = DMACH_MIC_IN,
+                .end   = DMACH_MIC_IN,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static u64 s3c_device_ac97_dmamask = 0xffffffffUL;
+
+struct platform_device s3c_device_ac97 = {
+        .name             = "s3c-ac97",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s3c_ac97_resource),
+        .resource         = s3c_ac97_resource,
+        .dev              = {
+                .dma_mask = &s3c_device_ac97_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+
+EXPORT_SYMBOL(s3c_device_ac97);
+
 #endif // CONFIG_CPU_S32440
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
new file mode 100644
index 000000000000..efeb025affc7
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
@@ -0,0 +1,282 @@
+/* arch/arm/plat-s3c/include/plat/cpu-freq.h
+ *
+ * Copyright (c) 2006,2007,2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C CPU frequency scaling support - core support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <plat/cpu-freq.h>
+
+struct seq_file;
+
+#define MAX_BANKS (8)
+#define S3C2412_MAX_IO  (8)
+
+/**
+ * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
+ * @bankcon: The cached version of settings in this structure.
+ * @tacp:
+ * @tacs: Time from address valid to nCS asserted.
+ * @tcos: Time from nCS asserted to nOE or nWE asserted.
+ * @tacc: Time that nOE or nWE is asserted.
+ * @tcoh: Time nCS is held after nOE or nWE are released.
+ * @tcah: Time address is held for after
+ * @nwait_en: Whether nWAIT is enabled for this bank.
+ *
+ * This structure represents the IO timings for a S3C2410 style IO bank
+ * used by the CPU frequency support if it needs to change the settings
+ * of the IO.
+ */
+struct s3c2410_iobank_timing {
+        unsigned long   bankcon;
+        unsigned int    tacp;
+        unsigned int    tacs;
+        unsigned int    tcos;
+        unsigned int    tacc;
+        unsigned int    tcoh;           /* nCS hold afrer nOE/nWE */
+        unsigned int    tcah;           /* Address hold after nCS */
+        unsigned char   nwait_en;       /* nWait enabled for bank. */
+};
+
+/**
+ * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO
+ * @idcy: The idle cycle time between transactions.
+ * @wstrd: nCS release to end of read cycle.
+ * @wstwr: nCS release to end of write cycle.
+ * @wstoen: nCS assertion to nOE assertion time.
+ * @wstwen: nCS assertion to nWE assertion time.
+ * @wstbrd: Burst ready delay.
+ * @smbidcyr: Register cache for smbidcyr value.
+ * @smbwstrd: Register cache for smbwstrd value.
+ * @smbwstwr: Register cache for smbwstwr value.
+ * @smbwstoen: Register cache for smbwstoen value.
+ * @smbwstwen: Register cache for smbwstwen value.
+ * @smbwstbrd: Register cache for smbwstbrd value.
+ *
+ * Timing information for a IO bank on an S3C2412 or similar system which
+ * uses a PL093 block.
+ */
+struct s3c2412_iobank_timing {
+        unsigned int    idcy;
+        unsigned int    wstrd;
+        unsigned int    wstwr;
+        unsigned int    wstoen;
+        unsigned int    wstwen;
+        unsigned int    wstbrd;
+
+        /* register cache */
+        unsigned char   smbidcyr;
+        unsigned char   smbwstrd;
+        unsigned char   smbwstwr;
+        unsigned char   smbwstoen;
+        unsigned char   smbwstwen;
+        unsigned char   smbwstbrd;
+};
+
+union s3c_iobank {
+        struct s3c2410_iobank_timing    *io_2410;
+        struct s3c2412_iobank_timing    *io_2412;
+};
+
+/**
+ * struct s3c_iotimings - Chip IO timings holder
+ * @bank: The timings for each IO bank.
+ */
+struct s3c_iotimings {
+        union s3c_iobank        bank[MAX_BANKS];
+};
+
+/**
+ * struct s3c_plltab - PLL table information.
+ * @vals: List of PLL values.
+ * @size: Size of the PLL table @vals.
+ */
+struct s3c_plltab {
+        struct s3c_pllval       *vals;
+        int                      size;
+};
+
+/**
+ * struct s3c_cpufreq_config - current cpu frequency configuration
+ * @freq: The current settings for the core clocks.
+ * @max: Maxium settings, derived from core, board and user settings.
+ * @pll: The PLL table entry for the current PLL settings.
+ * @divs: The divisor settings for the core clocks.
+ * @info: The current core driver information.
+ * @board: The information for the board we are running on.
+ * @lock_pll: Set if the PLL settings cannot be changed.
+ *
+ * This is for the core drivers that need to know information about
+ * the current settings and values. It should not be needed by any
+ * device drivers.
+*/
+struct s3c_cpufreq_config {
+        struct s3c_freq         freq;
+        struct s3c_freq         max;
+        struct cpufreq_frequency_table pll;
+        struct s3c_clkdivs      divs;
+        struct s3c_cpufreq_info *info;  /* for core, not drivers */
+        struct s3c_cpufreq_board *board;
+
+        unsigned int    lock_pll:1;
+};
+
+/**
+ * struct s3c_cpufreq_info - Information for the CPU frequency driver.
+ * @name: The name of this implementation.
+ * @max: The maximum frequencies for the system.
+ * @latency: Transition latency to give to cpufreq.
+ * @locktime_m: The lock-time in uS for the MPLL.
+ * @locktime_u: The lock-time in uS for the UPLL.
+ * @locttime_bits: The number of bits each LOCKTIME field.
+ * @need_pll: Set if this driver needs to change the PLL values to acheive
+ *      any frequency changes. This is really only need by devices like the
+ *      S3C2410 where there is no or limited divider between the PLL and the
+ *      ARMCLK.
+ * @resume_clocks: Update the clocks on resume.
+ * @get_iotiming: Get the current IO timing data, mainly for use at start.
+ * @set_iotiming: Update the IO timings from the cached copies calculated
+ *      from the @calc_iotiming entry when changing the frequency.
+ * @calc_iotiming: Calculate and update the cached copies of the IO timings
+ *      from the newly calculated frequencies.
+ * @calc_freqtable: Calculate (fill in) the given frequency table from the
+ *      current frequency configuration. If the table passed in is NULL,
+ *      then the return is the number of elements to be filled for allocation
+ *      of the table.
+ * @set_refresh: Set the memory refresh configuration.
+ * @set_fvco: Set the PLL frequencies.
+ * @set_divs: Update the clock divisors.
+ * @calc_divs: Calculate the clock divisors.
+ */
+struct s3c_cpufreq_info {
+        const char              *name;
+        struct s3c_freq         max;
+
+        unsigned int            latency;
+
+        unsigned int            locktime_m;
+        unsigned int            locktime_u;
+        unsigned char           locktime_bits;
+
+        unsigned int            need_pll:1;
+
+        /* driver routines */
+
+        void            (*resume_clocks)(void);
+
+        int             (*get_iotiming)(struct s3c_cpufreq_config *cfg,
+                                        struct s3c_iotimings *timings);
+
+        void            (*set_iotiming)(struct s3c_cpufreq_config *cfg,
+                                        struct s3c_iotimings *timings);
+
+        int             (*calc_iotiming)(struct s3c_cpufreq_config *cfg,
+                                         struct s3c_iotimings *timings);
+
+        int             (*calc_freqtable)(struct s3c_cpufreq_config *cfg,
+                                          struct cpufreq_frequency_table *t,
+                                          size_t table_size);
+
+        void            (*debug_io_show)(struct seq_file *seq,
+                                         struct s3c_cpufreq_config *cfg,
+                                         union s3c_iobank *iob);
+
+        void            (*set_refresh)(struct s3c_cpufreq_config *cfg);
+        void            (*set_fvco)(struct s3c_cpufreq_config *cfg);
+        void            (*set_divs)(struct s3c_cpufreq_config *cfg);
+        int             (*calc_divs)(struct s3c_cpufreq_config *cfg);
+};
+
+extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
+
+extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, unsigned int plls_no);
+
+/* exports and utilities for debugfs */
+extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
+extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
+
+extern void s3c2410_iotiming_debugfs(struct seq_file *seq,
+                                     struct s3c_cpufreq_config *cfg,
+                                     union s3c_iobank *iob);
+
+extern void s3c2412_iotiming_debugfs(struct seq_file *seq,
+                                     struct s3c_cpufreq_config *cfg,
+                                     union s3c_iobank *iob);
+
+#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
+#define s3c_cpufreq_debugfs_call(x) x
+#else
+#define s3c_cpufreq_debugfs_call(x) NULL
+#endif
+
+/* Useful utility functions. */
+
+extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *);
+
+/* S3C2410 and compatible exported functions */
+
+extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
+
+extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
+                                 struct s3c_iotimings *iot);
+
+extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
+                                struct s3c_iotimings *timings);
+
+extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
+                                 struct s3c_iotimings *iot);
+
+extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);
+
+/* S3C2412 compatible routines */
+
+extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
+                                struct s3c_iotimings *timings);
+
+extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
+                                struct s3c_iotimings *timings);
+
+extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
+                                 struct s3c_iotimings *iot);
+
+extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
+                                 struct s3c_iotimings *iot);
+
+#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG
+#define s3c_freq_dbg(x...) printk(KERN_INFO x)
+#else
+#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
+#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */
+
+#ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG
+#define s3c_freq_iodbg(x...) printk(KERN_INFO x)
+#else
+#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
+#endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */
+
+static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
+                                      int index, size_t table_size,
+                                      unsigned int freq)
+{
+        if (index < 0)
+                return index;
+
+        if (table) {
+                if (index >= table_size)
+                        return -ENOMEM;
+
+                s3c_freq_dbg("%s: { %d = %u kHz }\n",
+                             __func__, index, freq);
+
+                table[index].index = index;
+                table[index].frequency = freq;
+        }
+
+        return index + 1;
+}
diff --git a/arch/arm/plat-s3c24xx/include/plat/fiq.h b/arch/arm/plat-s3c24xx/include/plat/fiq.h
new file mode 100644
index 000000000000..8521b8372c5f
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/fiq.h
@@ -0,0 +1,13 @@
+/* linux/include/asm-arm/plat-s3c24xx/fiq.h
+ *
+ * Copyright (c) 2009 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Header file for S3C24XX CPU FIQ support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+extern int s3c24xx_set_fiq(unsigned int irq, bool on);
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
index a9ac9e29759e..b6deeef8f663 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
@@ -14,6 +14,7 @@
 #ifdef CONFIG_CPU_S3C2410
 
 extern  int s3c2410_init(void);
+extern  int s3c2410a_init(void);
 
 extern void s3c2410_map_io(void);
 
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index 958737775ad2..d02f5f02045e 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -493,6 +493,38 @@ s3c_irq_demux_extint4t7(unsigned int irq,
         }
 }
 
+#ifdef CONFIG_FIQ
+/**
+ * s3c24xx_set_fiq - set the FIQ routing
+ * @irq: IRQ number to route to FIQ on processor.
+ * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
+ *
+ * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
+ * @on is true, the @irq is checked to see if it can be routed and the
+ * interrupt controller updated to route the IRQ. If @on is false, the FIQ
+ * routing is cleared, regardless of which @irq is specified.
+ */
+int s3c24xx_set_fiq(unsigned int irq, bool on)
+{
+        u32 intmod;
+        unsigned offs;
+
+        if (on) {
+                offs = irq - FIQ_START;
+                if (offs > 31)
+                        return -EINVAL;
+
+                intmod = 1 << offs;
+        } else {
+                intmod = 0;
+        }
+
+        __raw_writel(intmod, S3C2410_INTMOD);
+        return 0;
+}
+#endif
+
+
 /* s3c24xx_init_irq
  *
  * Initialise S3C2410 IRQ system
@@ -505,6 +537,10 @@ void __init s3c24xx_init_irq(void)
         int irqno;
         int i;
 
+#ifdef CONFIG_FIQ
+        init_FIQ();
+#endif
+
         irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
 
         /* first, clear all interrupts pending... */
diff --git a/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c b/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
new file mode 100644
index 000000000000..43ea80190d87
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
@@ -0,0 +1,64 @@
+/* linux/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
+ *
+ * Copyright (c) 2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX CPU Frequency scaling - utils for S3C2410/S3C2440/S3C2442
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/cpufreq.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-clock.h>
+
+#include <plat/cpu-freq-core.h>
+
+/**
+ * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
+ * @cfg: The frequency configuration
+ *
+ * Set the SDRAM refresh value appropriately for the configured
+ * frequency.
+ */
+void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
+{
+        struct s3c_cpufreq_board *board = cfg->board;
+        unsigned long refresh;
+        unsigned long refval;
+
+        /* Reduce both the refresh time (in ns) and the frequency (in MHz)
+         * down to ensure that we do not overflow 32 bit numbers.
+         *
+         * This should work for HCLK up to 133MHz and refresh period up
+         * to 30usec.
+         */
+
+        refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
+        refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale  */
+        refresh = (1 << 11) + 1 - refresh;
+
+        s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh);
+
+        refval = __raw_readl(S3C2410_REFRESH);
+        refval &= ~((1 << 12) - 1);
+        refval |= refresh;
+        __raw_writel(refval, S3C2410_REFRESH);
+}
+
+/**
+ * s3c2410_set_fvco - set the PLL value
+ * @cfg: The frequency configuration
+ */
+void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
+{
+        __raw_writel(cfg->pll.index, S3C2410_MPLLCON);
+}
diff --git a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
new file mode 100644
index 000000000000..d0a3a145cd4d
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
@@ -0,0 +1,477 @@
+/* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
+ *
+ * Copyright (c) 2006,2008,2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX CPU Frequency scaling - IO timing for S3C2410/S3C2440/S3C2442
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/cpufreq.h>
+#include <linux/seq_file.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-clock.h>
+
+#include <plat/cpu-freq-core.h>
+
+#define print_ns(x) ((x) / 10), ((x) % 10)
+
+/**
+ * s3c2410_print_timing - print bank timing data for debug purposes
+ * @pfx: The prefix to put on the output
+ * @timings: The timing inforamtion to print.
+*/
+static void s3c2410_print_timing(const char *pfx,
+                                 struct s3c_iotimings *timings)
+{
+        struct s3c2410_iobank_timing *bt;
+        int bank;
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = timings->bank[bank].io_2410;
+                if (!bt)
+                        continue;
+
+                printk(KERN_DEBUG "%s %d: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, "
+                       "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank,
+                       print_ns(bt->tacs),
+                       print_ns(bt->tcos),
+                       print_ns(bt->tacc),
+                       print_ns(bt->tcoh),
+                       print_ns(bt->tcah));
+        }
+}
+
+/**
+ * bank_reg - convert bank number to pointer to the control register.
+ * @bank: The IO bank number.
+ */
+static inline void __iomem *bank_reg(unsigned int bank)
+{
+        return S3C2410_BANKCON0 + (bank << 2);
+}
+
+/**
+ * bank_is_io - test whether bank is used for IO
+ * @bankcon: The bank control register.
+ *
+ * This is a simplistic test to see if any BANKCON[x] is not an IO
+ * bank. It currently does not take into account whether BWSCON has
+ * an illegal width-setting in it, or if the pin connected to nCS[x]
+ * is actually being handled as a chip-select.
+ */
+static inline int bank_is_io(unsigned long bankcon)
+{
+        return !(bankcon & S3C2410_BANKCON_SDRAM);
+}
+
+/**
+ * to_div - convert cycle time to divisor
+ * @cyc: The cycle time, in 10ths of nanoseconds.
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ *
+ * Convert the given cycle time into the divisor to use to obtain it from
+ * HCLK.
+*/
+static inline unsigned int to_div(unsigned int cyc, unsigned int hclk_tns)
+{
+        if (cyc == 0)
+                return 0;
+
+        return DIV_ROUND_UP(cyc, hclk_tns);
+}
+
+/**
+ * calc_0124 - calculate divisor control for divisors that do /0, /1. /2 and /4
+ * @cyc: The cycle time, in 10ths of nanoseconds.
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ * @v: Pointer to register to alter.
+ * @shift: The shift to get to the control bits.
+ *
+ * Calculate the divisor, and turn it into the correct control bits to
+ * set in the result, @v.
+ */
+static unsigned int calc_0124(unsigned int cyc, unsigned long hclk_tns,
+                              unsigned long *v, int shift)
+{
+        unsigned int div = to_div(cyc, hclk_tns);
+        unsigned long val;
+
+        s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n",
+                       __func__, cyc, hclk_tns, shift, div);
+
+        switch (div) {
+        case 0:
+                val = 0;
+                break;
+        case 1:
+                val = 1;
+                break;
+        case 2:
+                val = 2;
+                break;
+        case 3:
+        case 4:
+                val = 3;
+                break;
+        default:
+                return -1;
+        }
+
+        *v |= val << shift;
+        return 0;
+}
+
+int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v)
+{
+        /* Currently no support for Tacp calculations. */
+        return 0;
+}
+
+/**
+ * calc_tacc - calculate divisor control for tacc.
+ * @cyc: The cycle time, in 10ths of nanoseconds.
+ * @nwait_en: IS nWAIT enabled for this bank.
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ * @v: Pointer to register to alter.
+ *
+ * Calculate the divisor control for tACC, taking into account whether
+ * the bank has nWAIT enabled. The result is used to modify the value
+ * pointed to by @v.
+*/
+static int calc_tacc(unsigned int cyc, int nwait_en,
+                     unsigned long hclk_tns, unsigned long *v)
+{
+        unsigned int div = to_div(cyc, hclk_tns);
+        unsigned long val;
+
+        s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n",
+                       __func__, cyc, nwait_en, hclk_tns, div);
+
+        /* if nWait enabled on an bank, Tacc must be at-least 4 cycles. */
+        if (nwait_en && div < 4)
+                div = 4;
+
+        switch (div) {
+        case 0:
+                val = 0;
+                break;
+
+        case 1:
+        case 2:
+        case 3:
+        case 4:
+                val = div - 1;
+                break;
+
+        case 5:
+        case 6:
+                val = 4;
+                break;
+
+        case 7:
+        case 8:
+                val = 5;
+                break;
+
+        case 9:
+        case 10:
+                val = 6;
+                break;
+
+        case 11:
+        case 12:
+        case 13:
+        case 14:
+                val = 7;
+                break;
+
+        default:
+                return -1;
+        }
+
+        *v |= val << 8;
+        return 0;
+}
+
+/**
+ * s3c2410_calc_bank - calculate bank timing infromation
+ * @cfg: The configuration we need to calculate for.
+ * @bt: The bank timing information.
+ *
+ * Given the cycle timine for a bank @bt, calculate the new BANKCON
+ * setting for the @cfg timing. This updates the timing information
+ * ready for the cpu frequency change.
+ */
+static int s3c2410_calc_bank(struct s3c_cpufreq_config *cfg,
+                             struct s3c2410_iobank_timing *bt)
+{
+        unsigned long hclk = cfg->freq.hclk_tns;
+        unsigned long res;
+        int ret;
+
+        res  = bt->bankcon;
+        res &= (S3C2410_BANKCON_SDRAM | S3C2410_BANKCON_PMC16);
+
+        /* tacp: 2,3,4,5 */
+        /* tcah: 0,1,2,4 */
+        /* tcoh: 0,1,2,4 */
+        /* tacc: 1,2,3,4,6,7,10,14 (>4 for nwait) */
+        /* tcos: 0,1,2,4 */
+        /* tacs: 0,1,2,4 */
+
+        ret  = calc_0124(bt->tacs, hclk, &res, S3C2410_BANKCON_Tacs_SHIFT);
+        ret |= calc_0124(bt->tcos, hclk, &res, S3C2410_BANKCON_Tcos_SHIFT);
+        ret |= calc_0124(bt->tcah, hclk, &res, S3C2410_BANKCON_Tcah_SHIFT);
+        ret |= calc_0124(bt->tcoh, hclk, &res, S3C2410_BANKCON_Tcoh_SHIFT);
+
+        if (ret)
+                return -EINVAL;
+
+        ret |= calc_tacp(bt->tacp, hclk, &res);
+        ret |= calc_tacc(bt->tacc, bt->nwait_en, hclk, &res);
+
+        if (ret)
+                return -EINVAL;
+
+        bt->bankcon = res;
+        return 0;
+}
+
+static unsigned int tacc_tab[] = {
+        [0]     = 1,
+        [1]     = 2,
+        [2]     = 3,
+        [3]     = 4,
+        [4]     = 6,
+        [5]     = 9,
+        [6]     = 10,
+        [7]     = 14,
+};
+
+/**
+ * get_tacc - turn tACC value into cycle time
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ * @val: The bank timing register value, shifed down.
+ */
+static unsigned int get_tacc(unsigned long hclk_tns,
+                             unsigned long val)
+{
+        val &= 7;
+        return hclk_tns * tacc_tab[val];
+}
+
+/**
+ * get_0124 - turn 0/1/2/4 divider into cycle time
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ * @val: The bank timing register value, shifed down.
+ */
+static unsigned int get_0124(unsigned long hclk_tns,
+                             unsigned long val)
+{
+        val &= 3;
+        return hclk_tns * ((val == 3) ? 4 : val);
+}
+
+/**
+ * s3c2410_iotiming_getbank - turn BANKCON into cycle time information
+ * @cfg: The frequency configuration
+ * @bt: The bank timing to fill in (uses cached BANKCON)
+ *
+ * Given the BANKCON setting in @bt and the current frequency settings
+ * in @cfg, update the cycle timing information.
+ */
+void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg,
+                              struct s3c2410_iobank_timing *bt)
+{
+        unsigned long bankcon = bt->bankcon;
+        unsigned long hclk = cfg->freq.hclk_tns;
+
+        bt->tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
+        bt->tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
+        bt->tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
+        bt->tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
+        bt->tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
+}
+
+/**
+ * s3c2410_iotiming_debugfs - debugfs show io bank timing information
+ * @seq: The seq_file to write output to using seq_printf().
+ * @cfg: The current configuration.
+ * @iob: The IO bank information to decode.
+ */
+void s3c2410_iotiming_debugfs(struct seq_file *seq,
+                              struct s3c_cpufreq_config *cfg,
+                              union s3c_iobank *iob)
+{
+        struct s3c2410_iobank_timing *bt = iob->io_2410;
+        unsigned long bankcon = bt->bankcon;
+        unsigned long hclk = cfg->freq.hclk_tns;
+        unsigned int tacs;
+        unsigned int tcos;
+        unsigned int tacc;
+        unsigned int tcoh;
+        unsigned int tcah;
+
+        seq_printf(seq, "BANKCON=0x%08lx\n", bankcon);
+
+        tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
+        tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
+        tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
+        tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
+        tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
+
+        seq_printf(seq,
+                   "\tRead: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
+                   print_ns(bt->tacs),
+                   print_ns(bt->tcos),
+                   print_ns(bt->tacc),
+                   print_ns(bt->tcoh),
+                   print_ns(bt->tcah));
+
+        seq_printf(seq,
+                   "\t Set: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
+                   print_ns(tacs),
+                   print_ns(tcos),
+                   print_ns(tacc),
+                   print_ns(tcoh),
+                   print_ns(tcah));
+}
+
+/**
+ * s3c2410_iotiming_calc - Calculate bank timing for frequency change.
+ * @cfg: The frequency configuration
+ * @iot: The IO timing information to fill out.
+ *
+ * Calculate the new values for the banks in @iot based on the new
+ * frequency information in @cfg. This is then used by s3c2410_iotiming_set()
+ * to update the timing when necessary.
+ */
+int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
+                          struct s3c_iotimings *iot)
+{
+        struct s3c2410_iobank_timing *bt;
+        unsigned long bankcon;
+        int bank;
+        int ret;
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bankcon = __raw_readl(bank_reg(bank));
+                bt = iot->bank[bank].io_2410;
+
+                if (!bt)
+                        continue;
+
+                bt->bankcon = bankcon;
+
+                ret = s3c2410_calc_bank(cfg, bt);
+                if (ret) {
+                        printk(KERN_ERR "%s: cannot calculate bank %d io\n",
+                               __func__, bank);
+                        goto err;
+                }
+
+                s3c_freq_iodbg("%s: bank %d: con=%08lx\n",
+                               __func__, bank, bt->bankcon);
+        }
+
+        return 0;
+ err:
+        return ret;
+}
+
+/**
+ * s3c2410_iotiming_set - set the IO timings from the given setup.
+ * @cfg: The frequency configuration
+ * @iot: The IO timing information to use.
+ *
+ * Set all the currently used IO bank timing information generated
+ * by s3c2410_iotiming_calc() once the core has validated that all
+ * the new values are within permitted bounds.
+ */
+void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
+                          struct s3c_iotimings *iot)
+{
+        struct s3c2410_iobank_timing *bt;
+        int bank;
+
+        /* set the io timings from the specifier */
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = iot->bank[bank].io_2410;
+                if (!bt)
+                        continue;
+
+                __raw_writel(bt->bankcon, bank_reg(bank));
+        }
+}
+
+/**
+ * s3c2410_iotiming_get - Get the timing information from current registers.
+ * @cfg: The frequency configuration
+ * @timings: The IO timing information to fill out.
+ *
+ * Calculate the @timings timing information from the current frequency
+ * information in @cfg, and the new frequency configur
+ * through all the IO banks, reading the state and then updating @iot
+ * as necessary.
+ *
+ * This is used at the moment on initialisation to get the current
+ * configuration so that boards do not have to carry their own setup
+ * if the timings are correct on initialisation.
+ */
+
+int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
+                         struct s3c_iotimings *timings)
+{
+        struct s3c2410_iobank_timing *bt;
+        unsigned long bankcon;
+        unsigned long bwscon;
+        int bank;
+
+        bwscon = __raw_readl(S3C2410_BWSCON);
+
+        /* look through all banks to see what is currently set. */
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bankcon = __raw_readl(bank_reg(bank));
+
+                if (!bank_is_io(bankcon))
+                        continue;
+
+                s3c_freq_iodbg("%s: bank %d: con %08lx\n",
+                               __func__, bank, bankcon);
+
+                bt = kzalloc(sizeof(struct s3c2410_iobank_timing), GFP_KERNEL);
+                if (!bt) {
+                        printk(KERN_ERR "%s: no memory for bank\n", __func__);
+                        return -ENOMEM;
+                }
+
+                /* find out in nWait is enabled for bank. */
+
+                if (bank != 0) {
+                        unsigned long tmp  = S3C2410_BWSCON_GET(bwscon, bank);
+                        if (tmp & S3C2410_BWSCON_WS)
+                                bt->nwait_en = 1;
+                }
+
+                timings->bank[bank].io_2410 = bt;
+                bt->bankcon = bankcon;
+
+                s3c2410_iotiming_getbank(cfg, bt);
+        }
+
+        s3c2410_print_timing("get", timings);
+        return 0;
+}
diff --git a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
new file mode 100644
index 000000000000..fd45e47facbc
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
@@ -0,0 +1,285 @@
+/* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
+ *
+ * Copyright (c) 2006,2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2412/S3C2443 (PL093 based) IO timing support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/seq_file.h>
+#include <linux/sysdev.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <linux/amba/pl093.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/regs-s3c2412-mem.h>
+
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+#include <plat/clock.h>
+
+#define print_ns(x) ((x) / 10), ((x) % 10)
+
+/**
+ * s3c2412_print_timing - print timing infromation via printk.
+ * @pfx: The prefix to print each line with.
+ * @iot: The IO timing information
+ */
+static void s3c2412_print_timing(const char *pfx, struct s3c_iotimings *iot)
+{
+        struct s3c2412_iobank_timing *bt;
+        unsigned int bank;
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = iot->bank[bank].io_2412;
+                if (!bt)
+                        continue;
+
+                printk(KERN_DEBUG "%s: %d: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
+                       "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank,
+                       print_ns(bt->idcy),
+                       print_ns(bt->wstrd),
+                       print_ns(bt->wstwr),
+                       print_ns(bt->wstoen),
+                       print_ns(bt->wstwen),
+                       print_ns(bt->wstbrd));
+        }
+}
+
+/**
+ * to_div - turn a cycle length into a divisor setting.
+ * @cyc_tns: The cycle time in 10ths of nanoseconds.
+ * @clk_tns: The clock period in 10ths of nanoseconds.
+ */
+static inline unsigned int to_div(unsigned int cyc_tns, unsigned int clk_tns)
+{
+        return cyc_tns ? DIV_ROUND_UP(cyc_tns, clk_tns) : 0;
+}
+
+/**
+ * calc_timing - calculate timing divisor value and check in range.
+ * @hwtm: The hardware timing in 10ths of nanoseconds.
+ * @clk_tns: The clock period in 10ths of nanoseconds.
+ * @err: Pointer to err variable to update in event of failure.
+ */
+static unsigned int calc_timing(unsigned int hwtm, unsigned int clk_tns,
+                                unsigned int *err)
+{
+        unsigned int ret = to_div(hwtm, clk_tns);
+
+        if (ret > 0xf)
+                *err = -EINVAL;
+
+        return ret;
+}
+
+/**
+ * s3c2412_calc_bank - calculate the bank divisor settings.
+ * @cfg: The current frequency configuration.
+ * @bt: The bank timing.
+ */
+static int s3c2412_calc_bank(struct s3c_cpufreq_config *cfg,
+                             struct s3c2412_iobank_timing *bt)
+{
+        unsigned int hclk = cfg->freq.hclk_tns;
+        int err = 0;
+
+        bt->smbidcyr = calc_timing(bt->idcy, hclk, &err);
+        bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err);
+        bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err);
+        bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err);
+        bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err);
+        bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err);
+
+        return err;
+}
+
+/**
+ * s3c2412_iotiming_debugfs - debugfs show io bank timing information
+ * @seq: The seq_file to write output to using seq_printf().
+ * @cfg: The current configuration.
+ * @iob: The IO bank information to decode.
+*/
+void s3c2412_iotiming_debugfs(struct seq_file *seq,
+                              struct s3c_cpufreq_config *cfg,
+                              union s3c_iobank *iob)
+{
+        struct s3c2412_iobank_timing *bt = iob->io_2412;
+
+        seq_printf(seq,
+                   "\tRead: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
+                   "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n",
+                   print_ns(bt->idcy),
+                   print_ns(bt->wstrd),
+                   print_ns(bt->wstwr),
+                   print_ns(bt->wstoen),
+                   print_ns(bt->wstwen),
+                   print_ns(bt->wstbrd));
+}
+
+/**
+ * s3c2412_iotiming_calc - calculate all the bank divisor settings.
+ * @cfg: The current frequency configuration.
+ * @iot: The bank timing information.
+ *
+ * Calculate the timing information for all the banks that are
+ * configured as IO, using s3c2412_calc_bank().
+ */
+int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
+                          struct s3c_iotimings *iot)
+{
+        struct s3c2412_iobank_timing *bt;
+        int bank;
+        int ret;
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = iot->bank[bank].io_2412;
+                if (!bt)
+                        continue;
+
+                ret = s3c2412_calc_bank(cfg, bt);
+                if (ret) {
+                        printk(KERN_ERR "%s: cannot calculate bank %d io\n",
+                               __func__, bank);
+                        goto err;
+                }
+        }
+
+        return 0;
+ err:
+        return ret;
+}
+
+/**
+ * s3c2412_iotiming_set - set the timing information
+ * @cfg: The current frequency configuration.
+ * @iot: The bank timing information.
+ *
+ * Set the IO bank information from the details calculated earlier from
+ * calling s3c2412_iotiming_calc().
+ */
+void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
+                          struct s3c_iotimings *iot)
+{
+        struct s3c2412_iobank_timing *bt;
+        void __iomem *regs;
+        int bank;
+
+        /* set the io timings from the specifier */
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = iot->bank[bank].io_2412;
+                if (!bt)
+                        continue;
+
+                regs = S3C2412_SSMC_BANK(bank);
+
+                __raw_writel(bt->smbidcyr, regs + SMBIDCYR);
+                __raw_writel(bt->smbwstrd, regs + SMBWSTRDR);
+                __raw_writel(bt->smbwstwr, regs + SMBWSTWRR);
+                __raw_writel(bt->smbwstoen, regs + SMBWSTOENR);
+                __raw_writel(bt->smbwstwen, regs + SMBWSTWENR);
+                __raw_writel(bt->smbwstbrd, regs + SMBWSTBRDR);
+        }
+}
+
+static inline unsigned int s3c2412_decode_timing(unsigned int clock, u32 reg)
+{
+        return (reg & 0xf) * clock;
+}
+
+static void s3c2412_iotiming_getbank(struct s3c_cpufreq_config *cfg,
+                                     struct s3c2412_iobank_timing *bt,
+                                     unsigned int bank)
+{
+        unsigned long clk = cfg->freq.hclk_tns;  /* ssmc clock??? */
+        void __iomem *regs = S3C2412_SSMC_BANK(bank);
+
+        bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR));
+        bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR));
+        bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR));
+        bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR));
+        bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR));
+}
+
+/**
+ * bank_is_io - return true if bank is (possibly) IO.
+ * @bank: The bank number.
+ * @bankcfg: The value of S3C2412_EBI_BANKCFG.
+ */
+static inline bool bank_is_io(unsigned int bank, u32 bankcfg)
+{
+        if (bank < 2)
+                return true;
+
+        return !(bankcfg & (1 << bank));
+}
+
+int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
+                         struct s3c_iotimings *timings)
+{
+        struct s3c2412_iobank_timing *bt;
+        u32 bankcfg = __raw_readl(S3C2412_EBI_BANKCFG);
+        unsigned int bank;
+
+        /* look through all banks to see what is currently set. */
+
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                if (!bank_is_io(bank, bankcfg))
+                        continue;
+
+                bt = kzalloc(sizeof(struct s3c2412_iobank_timing), GFP_KERNEL);
+                if (!bt) {
+                        printk(KERN_ERR "%s: no memory for bank\n", __func__);
+                        return -ENOMEM;
+                }
+
+                timings->bank[bank].io_2412 = bt;
+                s3c2412_iotiming_getbank(cfg, bt, bank);
+        }
+
+        s3c2412_print_timing("get", timings);
+        return 0;
+}
+
+/* this is in here as it is so small, it doesn't currently warrant a file
+ * to itself. We expect that any s3c24xx needing this is going to also
+ * need the iotiming support.
+ */
+void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
+{
+        struct s3c_cpufreq_board *board = cfg->board;
+        u32 refresh;
+
+        WARN_ON(board == NULL);
+
+        /* Reduce both the refresh time (in ns) and the frequency (in MHz)
+         * down to ensure that we do not overflow 32 bit numbers.
+         *
+         * This should work for HCLK up to 133MHz and refresh period up
+         * to 30usec.
+         */
+
+        refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
+        refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale  */
+        refresh &= ((1 << 16) - 1);
+
+        s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh);
+
+        __raw_writel(refresh, S3C2412_REFRESH);
+}
diff --git a/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c b/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
new file mode 100644
index 000000000000..ae2e6c604f27
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
@@ -0,0 +1,311 @@
+/* linux/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
+ *
+ * Copyright (c) 2006,2008,2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@simtec.co.uk>
+ *
+ * S3C2440/S3C2442 CPU Frequency scaling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/sysdev.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/regs-clock.h>
+
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+#include <plat/clock.h>
+
+static struct clk *xtal;
+static struct clk *fclk;
+static struct clk *hclk;
+static struct clk *armclk;
+
+/* HDIV: 1, 2, 3, 4, 6, 8 */
+
+static inline int within_khz(unsigned long a, unsigned long b)
+{
+        long diff = a - b;
+
+        return (diff >= -1000 && diff <= 1000);
+}
+
+/**
+ * s3c2440_cpufreq_calcdivs - calculate divider settings
+ * @cfg: The cpu frequency settings.
+ *
+ * Calcualte the divider values for the given frequency settings
+ * specified in @cfg. The values are stored in @cfg for later use
+ * by the relevant set routine if the request settings can be reached.
+ */
+int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned int hdiv, pdiv;
+        unsigned long hclk, fclk, armclk;
+        unsigned long hclk_max;
+
+        fclk = cfg->freq.fclk;
+        armclk = cfg->freq.armclk;
+        hclk_max = cfg->max.hclk;
+
+        s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n",
+                     __func__, fclk, armclk, hclk_max);
+
+        if (armclk > fclk) {
+                printk(KERN_WARNING "%s: armclk > fclk\n", __func__);
+                armclk = fclk;
+        }
+
+        /* if we are in DVS, we need HCLK to be <= ARMCLK */
+        if (armclk < fclk && armclk < hclk_max)
+                hclk_max = armclk;
+
+        for (hdiv = 1; hdiv < 9; hdiv++) {
+                if (hdiv == 5 || hdiv == 7)
+                        hdiv++;
+
+                hclk = (fclk / hdiv);
+                if (hclk <= hclk_max || within_khz(hclk, hclk_max))
+                        break;
+        }
+
+        s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv);
+
+        if (hdiv > 8)
+                goto invalid;
+
+        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
+
+        if ((hclk / pdiv) > cfg->max.pclk)
+                pdiv++;
+
+        s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
+
+        if (pdiv > 2)
+                goto invalid;
+
+        pdiv *= hdiv;
+
+        /* calculate a valid armclk */
+
+        if (armclk < hclk)
+                armclk = hclk;
+
+        /* if we're running armclk lower than fclk, this really means
+         * that the system should go into dvs mode, which means that
+         * armclk is connected to hclk. */
+        if (armclk < fclk) {
+                cfg->divs.dvs = 1;
+                armclk = hclk;
+        } else
+                cfg->divs.dvs = 0;
+
+        cfg->freq.armclk = armclk;
+
+        /* store the result, and then return */
+
+        cfg->divs.h_divisor = hdiv;
+        cfg->divs.p_divisor = pdiv;
+
+        return 0;
+
+ invalid:
+        return -EINVAL;
+}
+
+#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \
+                           S3C2440_CAMDIVN_HCLK4_HALF)
+
+/**
+ * s3c2440_cpufreq_setdivs - set the cpu frequency divider settings
+ * @cfg: The cpu frequency settings.
+ *
+ * Set the divisors from the settings in @cfg, which where generated
+ * during the calculation phase by s3c2440_cpufreq_calcdivs().
+ */
+static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long clkdiv, camdiv;
+
+        s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__,
+                     cfg->divs.h_divisor, cfg->divs.p_divisor);
+
+        clkdiv = __raw_readl(S3C2410_CLKDIVN);
+        camdiv = __raw_readl(S3C2440_CAMDIVN);
+
+        clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN);
+        camdiv &= ~CAMDIVN_HCLK_HALF;
+
+        switch (cfg->divs.h_divisor) {
+        case 1:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_1;
+                break;
+
+        case 2:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_2;
+                break;
+
+        case 6:
+                camdiv |= S3C2440_CAMDIVN_HCLK3_HALF;
+        case 3:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6;
+                break;
+
+        case 8:
+                camdiv |= S3C2440_CAMDIVN_HCLK4_HALF;
+        case 4:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8;
+                break;
+
+        default:
+                BUG();  /* we don't expect to get here. */
+        }
+
+        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
+                clkdiv |= S3C2440_CLKDIVN_PDIVN;
+
+        /* todo - set pclk. */
+
+        /* Write the divisors first with hclk intentionally halved so that
+         * when we write clkdiv we will under-frequency instead of over. We
+         * then make a short delay and remove the hclk halving if necessary.
+         */
+
+        __raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
+        __raw_writel(clkdiv, S3C2410_CLKDIVN);
+
+        ndelay(20);
+        __raw_writel(camdiv, S3C2440_CAMDIVN);
+
+        clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
+}
+
+static int run_freq_for(unsigned long max_hclk, unsigned long fclk,
+                        int *divs,
+                        struct cpufreq_frequency_table *table,
+                        size_t table_size)
+{
+        unsigned long freq;
+        int index = 0;
+        int div;
+
+        for (div = *divs; div > 0; div = *divs++) {
+                freq = fclk / div;
+
+                if (freq > max_hclk && div != 1)
+                        continue;
+
+                freq /= 1000; /* table is in kHz */
+                index = s3c_cpufreq_addfreq(table, index, table_size, freq);
+                if (index < 0)
+                        break;
+        }
+
+        return index;
+}
+
+static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 };
+
+static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg,
+                                     struct cpufreq_frequency_table *table,
+                                     size_t table_size)
+{
+        int ret;
+
+        WARN_ON(cfg->info == NULL);
+        WARN_ON(cfg->board == NULL);
+
+        ret = run_freq_for(cfg->info->max.hclk,
+                           cfg->info->max.fclk,
+                           hclk_divs,
+                           table, table_size);
+
+        s3c_freq_dbg("%s: returning %d\n", __func__, ret);
+
+        return ret;
+}
+
+struct s3c_cpufreq_info s3c2440_cpufreq_info = {
+        .max            = {
+                .fclk   = 400000000,
+                .hclk   = 133333333,
+                .pclk   =  66666666,
+        },
+
+        .locktime_m     = 300,
+        .locktime_u     = 300,
+        .locktime_bits  = 16,
+
+        .name           = "s3c244x",
+        .calc_iotiming  = s3c2410_iotiming_calc,
+        .set_iotiming   = s3c2410_iotiming_set,
+        .get_iotiming   = s3c2410_iotiming_get,
+        .set_fvco       = s3c2410_set_fvco,
+
+        .set_refresh    = s3c2410_cpufreq_setrefresh,
+        .set_divs       = s3c2440_cpufreq_setdivs,
+        .calc_divs      = s3c2440_cpufreq_calcdivs,
+        .calc_freqtable = s3c2440_cpufreq_calctable,
+
+        .resume_clocks  = s3c244x_setup_clocks,
+
+        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
+};
+
+static int s3c2440_cpufreq_add(struct sys_device *sysdev)
+{
+        xtal = s3c_cpufreq_clk_get(NULL, "xtal");
+        hclk = s3c_cpufreq_clk_get(NULL, "hclk");
+        fclk = s3c_cpufreq_clk_get(NULL, "fclk");
+        armclk = s3c_cpufreq_clk_get(NULL, "armclk");
+
+        if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) {
+                printk(KERN_ERR "%s: failed to get clocks\n", __func__);
+                return -ENOENT;
+        }
+
+        return s3c_cpufreq_register(&s3c2440_cpufreq_info);
+}
+
+static struct sysdev_driver s3c2440_cpufreq_driver = {
+        .add            = s3c2440_cpufreq_add,
+};
+
+static int s3c2440_cpufreq_init(void)
+{
+        return sysdev_driver_register(&s3c2440_sysclass,
+                                      &s3c2440_cpufreq_driver);
+}
+
+/* arch_initcall adds the clocks we need, so use subsys_initcall. */
+subsys_initcall(s3c2440_cpufreq_init);
+
+static struct sysdev_driver s3c2442_cpufreq_driver = {
+        .add            = s3c2440_cpufreq_add,
+};
+
+static int s3c2442_cpufreq_init(void)
+{
+        return sysdev_driver_register(&s3c2442_sysclass,
+                                      &s3c2442_cpufreq_driver);
+}
+
+subsys_initcall(s3c2442_cpufreq_init);
diff --git a/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
new file mode 100644
index 000000000000..ff9443b233aa
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
@@ -0,0 +1,97 @@
+/* arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
+ *
+ * Copyright (c) 2006,2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@arm.linux.org.uk>
+ *
+ * S3C2440/S3C2442 CPU PLL tables (12MHz Crystal)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sysdev.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+
+static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
+        { .frequency = 75000000,        .index = PLLVAL(0x75, 3, 3),  },        /* FVco 600.000000 */
+        { .frequency = 80000000,        .index = PLLVAL(0x98, 4, 3),  },        /* FVco 640.000000 */
+        { .frequency = 90000000,        .index = PLLVAL(0x70, 2, 3),  },        /* FVco 720.000000 */
+        { .frequency = 100000000,       .index = PLLVAL(0x5c, 1, 3),  },        /* FVco 800.000000 */
+        { .frequency = 110000000,       .index = PLLVAL(0x66, 1, 3),  },        /* FVco 880.000000 */
+        { .frequency = 120000000,       .index = PLLVAL(0x70, 1, 3),  },        /* FVco 960.000000 */
+        { .frequency = 150000000,       .index = PLLVAL(0x75, 3, 2),  },        /* FVco 600.000000 */
+        { .frequency = 160000000,       .index = PLLVAL(0x98, 4, 2),  },        /* FVco 640.000000 */
+        { .frequency = 170000000,       .index = PLLVAL(0x4d, 1, 2),  },        /* FVco 680.000000 */
+        { .frequency = 180000000,       .index = PLLVAL(0x70, 2, 2),  },        /* FVco 720.000000 */
+        { .frequency = 190000000,       .index = PLLVAL(0x57, 1, 2),  },        /* FVco 760.000000 */
+        { .frequency = 200000000,       .index = PLLVAL(0x5c, 1, 2),  },        /* FVco 800.000000 */
+        { .frequency = 210000000,       .index = PLLVAL(0x84, 2, 2),  },        /* FVco 840.000000 */
+        { .frequency = 220000000,       .index = PLLVAL(0x66, 1, 2),  },        /* FVco 880.000000 */
+        { .frequency = 230000000,       .index = PLLVAL(0x6b, 1, 2),  },        /* FVco 920.000000 */
+        { .frequency = 240000000,       .index = PLLVAL(0x70, 1, 2),  },        /* FVco 960.000000 */
+        { .frequency = 300000000,       .index = PLLVAL(0x75, 3, 1),  },        /* FVco 600.000000 */
+        { .frequency = 310000000,       .index = PLLVAL(0x93, 4, 1),  },        /* FVco 620.000000 */
+        { .frequency = 320000000,       .index = PLLVAL(0x98, 4, 1),  },        /* FVco 640.000000 */
+        { .frequency = 330000000,       .index = PLLVAL(0x66, 2, 1),  },        /* FVco 660.000000 */
+        { .frequency = 340000000,       .index = PLLVAL(0x4d, 1, 1),  },        /* FVco 680.000000 */
+        { .frequency = 350000000,       .index = PLLVAL(0xa7, 4, 1),  },        /* FVco 700.000000 */
+        { .frequency = 360000000,       .index = PLLVAL(0x70, 2, 1),  },        /* FVco 720.000000 */
+        { .frequency = 370000000,       .index = PLLVAL(0xb1, 4, 1),  },        /* FVco 740.000000 */
+        { .frequency = 380000000,       .index = PLLVAL(0x57, 1, 1),  },        /* FVco 760.000000 */
+        { .frequency = 390000000,       .index = PLLVAL(0x7a, 2, 1),  },        /* FVco 780.000000 */
+        { .frequency = 400000000,       .index = PLLVAL(0x5c, 1, 1),  },        /* FVco 800.000000 */
+};
+
+static int s3c2440_plls12_add(struct sys_device *dev)
+{
+        struct clk *xtal_clk;
+        unsigned long xtal;
+
+        xtal_clk = clk_get(NULL, "xtal");
+        if (IS_ERR(xtal_clk))
+                return PTR_ERR(xtal_clk);
+
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        if (xtal == 12000000) {
+                printk(KERN_INFO "Using PLL table for 12MHz crystal\n");
+                return s3c_plltab_register(s3c2440_plls_12,
+                                           ARRAY_SIZE(s3c2440_plls_12));
+        }
+
+        return 0;
+}
+
+static struct sysdev_driver s3c2440_plls12_drv = {
+        .add    = s3c2440_plls12_add,
+};
+
+static int __init s3c2440_pll_12mhz(void)
+{
+        return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_plls12_drv);
+
+}
+
+arch_initcall(s3c2440_pll_12mhz);
+
+static struct sysdev_driver s3c2442_plls12_drv = {
+        .add    = s3c2440_plls12_add,
+};
+
+static int __init s3c2442_pll_12mhz(void)
+{
+        return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_plls12_drv);
+
+}
+
+arch_initcall(s3c2442_pll_12mhz);
diff --git a/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c b/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c
new file mode 100644
index 000000000000..7679af13a94d
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c
@@ -0,0 +1,127 @@
+/* arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c
+ *
+ * Copyright (c) 2006-2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@arm.linux.org.uk>
+ *
+ * S3C2440/S3C2442 CPU PLL tables (16.93444MHz Crystal)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sysdev.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+
+static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
+        { .frequency = 78019200,        .index = PLLVAL(121, 5, 3),     },      /* FVco 624.153600 */
+        { .frequency = 84067200,        .index = PLLVAL(131, 5, 3),     },      /* FVco 672.537600 */
+        { .frequency = 90115200,        .index = PLLVAL(141, 5, 3),     },      /* FVco 720.921600 */
+        { .frequency = 96163200,        .index = PLLVAL(151, 5, 3),     },      /* FVco 769.305600 */
+        { .frequency = 102135600,       .index = PLLVAL(185, 6, 3),     },      /* FVco 817.084800 */
+        { .frequency = 108259200,       .index = PLLVAL(171, 5, 3),     },      /* FVco 866.073600 */
+        { .frequency = 114307200,       .index = PLLVAL(127, 3, 3),     },      /* FVco 914.457600 */
+        { .frequency = 120234240,       .index = PLLVAL(134, 3, 3),     },      /* FVco 961.873920 */
+        { .frequency = 126161280,       .index = PLLVAL(141, 3, 3),     },      /* FVco 1009.290240 */
+        { .frequency = 132088320,       .index = PLLVAL(148, 3, 3),     },      /* FVco 1056.706560 */
+        { .frequency = 138015360,       .index = PLLVAL(155, 3, 3),     },      /* FVco 1104.122880 */
+        { .frequency = 144789120,       .index = PLLVAL(163, 3, 3),     },      /* FVco 1158.312960 */
+        { .frequency = 150100363,       .index = PLLVAL(187, 9, 2),     },      /* FVco 600.401454 */
+        { .frequency = 156038400,       .index = PLLVAL(121, 5, 2),     },      /* FVco 624.153600 */
+        { .frequency = 162086400,       .index = PLLVAL(126, 5, 2),     },      /* FVco 648.345600 */
+        { .frequency = 168134400,       .index = PLLVAL(131, 5, 2),     },      /* FVco 672.537600 */
+        { .frequency = 174048000,       .index = PLLVAL(177, 7, 2),     },      /* FVco 696.192000 */
+        { .frequency = 180230400,       .index = PLLVAL(141, 5, 2),     },      /* FVco 720.921600 */
+        { .frequency = 186278400,       .index = PLLVAL(124, 4, 2),     },      /* FVco 745.113600 */
+        { .frequency = 192326400,       .index = PLLVAL(151, 5, 2),     },      /* FVco 769.305600 */
+        { .frequency = 198132480,       .index = PLLVAL(109, 3, 2),     },      /* FVco 792.529920 */
+        { .frequency = 204271200,       .index = PLLVAL(185, 6, 2),     },      /* FVco 817.084800 */
+        { .frequency = 210268800,       .index = PLLVAL(141, 4, 2),     },      /* FVco 841.075200 */
+        { .frequency = 216518400,       .index = PLLVAL(171, 5, 2),     },      /* FVco 866.073600 */
+        { .frequency = 222264000,       .index = PLLVAL(97, 2, 2),      },      /* FVco 889.056000 */
+        { .frequency = 228614400,       .index = PLLVAL(127, 3, 2),     },      /* FVco 914.457600 */
+        { .frequency = 234259200,       .index = PLLVAL(158, 4, 2),     },      /* FVco 937.036800 */
+        { .frequency = 240468480,       .index = PLLVAL(134, 3, 2),     },      /* FVco 961.873920 */
+        { .frequency = 246960000,       .index = PLLVAL(167, 4, 2),     },      /* FVco 987.840000 */
+        { .frequency = 252322560,       .index = PLLVAL(141, 3, 2),     },      /* FVco 1009.290240 */
+        { .frequency = 258249600,       .index = PLLVAL(114, 2, 2),     },      /* FVco 1032.998400 */
+        { .frequency = 264176640,       .index = PLLVAL(148, 3, 2),     },      /* FVco 1056.706560 */
+        { .frequency = 270950400,       .index = PLLVAL(120, 2, 2),     },      /* FVco 1083.801600 */
+        { .frequency = 276030720,       .index = PLLVAL(155, 3, 2),     },      /* FVco 1104.122880 */
+        { .frequency = 282240000,       .index = PLLVAL(92, 1, 2),      },      /* FVco 1128.960000 */
+        { .frequency = 289578240,       .index = PLLVAL(163, 3, 2),     },      /* FVco 1158.312960 */
+        { .frequency = 294235200,       .index = PLLVAL(131, 2, 2),     },      /* FVco 1176.940800 */
+        { .frequency = 300200727,       .index = PLLVAL(187, 9, 1),     },      /* FVco 600.401454 */
+        { .frequency = 306358690,       .index = PLLVAL(191, 9, 1),     },      /* FVco 612.717380 */
+        { .frequency = 312076800,       .index = PLLVAL(121, 5, 1),     },      /* FVco 624.153600 */
+        { .frequency = 318366720,       .index = PLLVAL(86, 3, 1),      },      /* FVco 636.733440 */
+        { .frequency = 324172800,       .index = PLLVAL(126, 5, 1),     },      /* FVco 648.345600 */
+        { .frequency = 330220800,       .index = PLLVAL(109, 4, 1),     },      /* FVco 660.441600 */
+        { .frequency = 336268800,       .index = PLLVAL(131, 5, 1),     },      /* FVco 672.537600 */
+        { .frequency = 342074880,       .index = PLLVAL(93, 3, 1),      },      /* FVco 684.149760 */
+        { .frequency = 348096000,       .index = PLLVAL(177, 7, 1),     },      /* FVco 696.192000 */
+        { .frequency = 355622400,       .index = PLLVAL(118, 4, 1),     },      /* FVco 711.244800 */
+        { .frequency = 360460800,       .index = PLLVAL(141, 5, 1),     },      /* FVco 720.921600 */
+        { .frequency = 366206400,       .index = PLLVAL(165, 6, 1),     },      /* FVco 732.412800 */
+        { .frequency = 372556800,       .index = PLLVAL(124, 4, 1),     },      /* FVco 745.113600 */
+        { .frequency = 378201600,       .index = PLLVAL(126, 4, 1),     },      /* FVco 756.403200 */
+        { .frequency = 384652800,       .index = PLLVAL(151, 5, 1),     },      /* FVco 769.305600 */
+        { .frequency = 391608000,       .index = PLLVAL(177, 6, 1),     },      /* FVco 783.216000 */
+        { .frequency = 396264960,       .index = PLLVAL(109, 3, 1),     },      /* FVco 792.529920 */
+        { .frequency = 402192000,       .index = PLLVAL(87, 2, 1),      },      /* FVco 804.384000 */
+};
+
+static int s3c2440_plls169344_add(struct sys_device *dev)
+{
+        struct clk *xtal_clk;
+        unsigned long xtal;
+
+        xtal_clk = clk_get(NULL, "xtal");
+        if (IS_ERR(xtal_clk))
+                return PTR_ERR(xtal_clk);
+
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        if (xtal == 169344000) {
+                printk(KERN_INFO "Using PLL table for 16.9344MHz crystal\n");
+                return s3c_plltab_register(s3c2440_plls_169344,
+                                           ARRAY_SIZE(s3c2440_plls_169344));
+        }
+
+        return 0;
+}
+
+static struct sysdev_driver s3c2440_plls169344_drv = {
+        .add    = s3c2440_plls169344_add,
+};
+
+static int __init s3c2440_pll_16934400(void)
+{
+        return sysdev_driver_register(&s3c2440_sysclass,
+                                      &s3c2440_plls169344_drv);
+
+}
+
+arch_initcall(s3c2440_pll_16934400);
+
+static struct sysdev_driver s3c2442_plls169344_drv = {
+        .add    = s3c2440_plls169344_add,
+};
+
+static int __init s3c2442_pll_16934400(void)
+{
+        return sysdev_driver_register(&s3c2442_sysclass,
+                                      &s3c2442_plls169344_drv);
+
+}
+
+arch_initcall(s3c2442_pll_16934400);
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
new file mode 100644
index 000000000000..89fcf5308cf6
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
@@ -0,0 +1,38 @@
+/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpd8_9_10.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX SPI - gpio configuration for bus 1 on gpd8,9,10
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+
+#include <mach/spi.h>
+#include <mach/regs-gpio.h>
+
+void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
+                                        int enable)
+{
+
+        printk(KERN_INFO "%s(%d)\n", __func__, enable);
+        if (enable) {
+                s3c2410_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1);
+                s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1);
+                s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1);
+                s3c2410_gpio_pullup(S3C2410_GPD(10), 0);
+                s3c2410_gpio_pullup(S3C2410_GPD(9), 0);
+        } else {
+                s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT);
+                s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT);
+                s3c2410_gpio_pullup(S3C2410_GPD(10), 1);
+                s3c2410_gpio_pullup(S3C2410_GPD(9), 1);
+                s3c2410_gpio_pullup(S3C2410_GPD(8), 1);
+        }
+}
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig
index 5ebd8b425a54..bcfa778614d8 100644
--- a/arch/arm/plat-s3c64xx/Kconfig
+++ b/arch/arm/plat-s3c64xx/Kconfig
@@ -19,6 +19,7 @@ config PLAT_S3C64XX
         select S3C_GPIO_PULL_UPDOWN
         select S3C_GPIO_CFG_S3C24XX
         select S3C_GPIO_CFG_S3C64XX
+        select S3C_DEV_NAND
         select USB_ARCH_HAS_OHCI
         help
           Base platform code for any Samsung S3C64XX device
diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile
index 3c8882cd6268..b85b4359e935 100644
--- a/arch/arm/plat-s3c64xx/Makefile
+++ b/arch/arm/plat-s3c64xx/Makefile
@@ -40,4 +40,5 @@ obj-$(CONFIG_S3C64XX_DMA)	+= dma.o
 obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
 obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
 obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
-obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
\ No newline at end of file
+obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
+obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o
diff --git a/arch/arm/plat-s3c/dev-audio.c b/arch/arm/plat-s3c64xx/dev-audio.c
index 1322beb40dd7..1322beb40dd7 100644
--- a/arch/arm/plat-s3c/dev-audio.c
+++ b/arch/arm/plat-s3c64xx/dev-audio.c
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
new file mode 100644
index 000000000000..a8a711c3c064
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -0,0 +1,50 @@
+# arch/arm/plat-s5pc1xx/Kconfig
+#
+# Copyright 2009 Samsung Electronics Co.
+#       Byungho Min <bhmin@samsung.com>
+#
+# Licensed under GPLv2
+
+config PLAT_S5PC1XX
+        bool
+        depends on ARCH_S5PC1XX
+        default y
+        select PLAT_S3C
+        select ARM_VIC
+        select NO_IOPORT
+        select ARCH_REQUIRE_GPIOLIB
+        select S3C_GPIO_TRACK
+        select S3C_GPIO_PULL_UPDOWN
+        help
+          Base platform code for any Samsung S5PC1XX device
+
+if PLAT_S5PC1XX
+
+# Configuration options shared by all S3C64XX implementations
+
+config CPU_S5PC100_INIT
+        bool
+        help
+          Common initialisation code for the S5PC1XX
+
+config CPU_S5PC100_CLOCK
+        bool
+        help
+          Common clock support code for the S5PC1XX
+
+# platform specific device setup
+
+config S5PC100_SETUP_I2C0
+        bool
+        default y
+        help
+          Common setup code for i2c bus 0.
+
+          Note, currently since i2c0 is always compiled, this setup helper
+          is always compiled with it.
+
+config S5PC100_SETUP_I2C1
+        bool
+        help
+          Common setup code for i2c bus 1.
+endif
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
new file mode 100644
index 000000000000..f1ecb2c37ee2
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/Makefile
@@ -0,0 +1,26 @@
+# arch/arm/plat-s5pc1xx/Makefile
+#
+# Copyright 2009 Samsung Electronics Co.
+#
+# Licensed under GPLv2
+
+obj-y                           :=
+obj-m                           :=
+obj-n                           := dummy.o
+obj-                            :=
+
+# Core files
+
+obj-y                           += dev-uart.o
+obj-y                           += cpu.o
+obj-y                           += irq.o
+
+# CPU support
+
+obj-$(CONFIG_CPU_S5PC100_INIT)  += s5pc100-init.o
+obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o
+
+# Device setup
+
+obj-$(CONFIG_S5PC100_SETUP_I2C0) += setup-i2c0.o
+obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c
new file mode 100644
index 000000000000..715a7330794d
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/cpu.c
@@ -0,0 +1,112 @@
+/* linux/arch/arm/plat-s5pc1xx/cpu.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX CPU Support
+ *
+ * Based on plat-s3c64xx/cpu.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <asm/mach/map.h>
+
+#include <plat/regs-serial.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+
+#include <plat/s5pc100.h>
+
+/* table of supported CPUs */
+
+static const char name_s5pc100[] = "S5PC100";
+
+static struct cpu_table cpu_ids[] __initdata = {
+        {
+                .idcode         = 0x43100000,
+                .idmask         = 0xfffff000,
+                .map_io         = s5pc100_map_io,
+                .init_clocks    = s5pc100_init_clocks,
+                .init_uarts     = s5pc100_init_uarts,
+                .init           = s5pc100_init,
+                .name           = name_s5pc100,
+        },
+};
+/* minimal IO mapping */
+
+/* see notes on uart map in arch/arm/mach-s5pc100/include/mach/debug-macro.S */
+#define UART_OFFS (S3C_PA_UART & 0xffff)
+
+static struct map_desc s5pc1xx_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5PC1XX_VA_CHIPID,
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_CHIPID),
+                .length         = SZ_16,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC1XX_VA_CLK,
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_CLK),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC1XX_VA_PWR,
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_PWR),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)(S5PC1XX_VA_UART),
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_UART),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC1XX_VA_VIC(0),
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_VIC(0)),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC1XX_VA_VIC(1),
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_VIC(1)),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC1XX_VA_VIC(2),
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_VIC(2)),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC1XX_VA_TIMER,
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_TIMER),
+                .length         = SZ_256,
+                .type           = MT_DEVICE,
+        },
+};
+
+/* read cpu identification code */
+
+void __init s5pc1xx_init_io(struct map_desc *mach_desc, int size)
+{
+        unsigned long idcode;
+
+        /* initialise the io descriptors we need for initialisation */
+        iotable_init(s5pc1xx_iodesc, ARRAY_SIZE(s5pc1xx_iodesc));
+        iotable_init(mach_desc, size);
+
+        idcode = __raw_readl(S5PC1XX_VA_CHIPID);
+        s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
+}
diff --git a/arch/arm/plat-s5pc1xx/dev-uart.c b/arch/arm/plat-s5pc1xx/dev-uart.c
new file mode 100644
index 000000000000..f749bc5407b5
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/dev-uart.c
@@ -0,0 +1,174 @@
+/* linux/arch/arm/plat-s5pc1xx/dev-uart.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Based on plat-s3c64xx/dev-uart.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+/* Serial port registrations */
+
+/* 64xx uarts are closer together */
+
+static struct resource s5pc1xx_uart0_resource[] = {
+        [0] = {
+                .start  = S3C_PA_UART0,
+                .end    = S3C_PA_UART0 + 0x100,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S3CUART_RX0,
+                .end    = IRQ_S3CUART_RX0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S3CUART_TX0,
+                .end    = IRQ_S3CUART_TX0,
+                .flags  = IORESOURCE_IRQ,
+
+        },
+        [3] = {
+                .start  = IRQ_S3CUART_ERR0,
+                .end    = IRQ_S3CUART_ERR0,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct resource s5pc1xx_uart1_resource[] = {
+        [0] = {
+                .start = S3C_PA_UART1,
+                .end   = S3C_PA_UART1 + 0x100,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S3CUART_RX1,
+                .end    = IRQ_S3CUART_RX1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S3CUART_TX1,
+                .end    = IRQ_S3CUART_TX1,
+                .flags  = IORESOURCE_IRQ,
+
+        },
+        [3] = {
+                .start  = IRQ_S3CUART_ERR1,
+                .end    = IRQ_S3CUART_ERR1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource s5pc1xx_uart2_resource[] = {
+        [0] = {
+                .start = S3C_PA_UART2,
+                .end   = S3C_PA_UART2 + 0x100,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S3CUART_RX2,
+                .end    = IRQ_S3CUART_RX2,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S3CUART_TX2,
+                .end    = IRQ_S3CUART_TX2,
+                .flags  = IORESOURCE_IRQ,
+
+        },
+        [3] = {
+                .start  = IRQ_S3CUART_ERR2,
+                .end    = IRQ_S3CUART_ERR2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource s5pc1xx_uart3_resource[] = {
+        [0] = {
+                .start = S3C_PA_UART3,
+                .end   = S3C_PA_UART3 + 0x100,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S3CUART_RX3,
+                .end    = IRQ_S3CUART_RX3,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S3CUART_TX3,
+                .end    = IRQ_S3CUART_TX3,
+                .flags  = IORESOURCE_IRQ,
+
+        },
+        [3] = {
+                .start  = IRQ_S3CUART_ERR3,
+                .end    = IRQ_S3CUART_ERR3,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+
+struct s3c24xx_uart_resources s5pc1xx_uart_resources[] __initdata = {
+        [0] = {
+                .resources      = s5pc1xx_uart0_resource,
+                .nr_resources   = ARRAY_SIZE(s5pc1xx_uart0_resource),
+        },
+        [1] = {
+                .resources      = s5pc1xx_uart1_resource,
+                .nr_resources   = ARRAY_SIZE(s5pc1xx_uart1_resource),
+        },
+        [2] = {
+                .resources      = s5pc1xx_uart2_resource,
+                .nr_resources   = ARRAY_SIZE(s5pc1xx_uart2_resource),
+        },
+        [3] = {
+                .resources      = s5pc1xx_uart3_resource,
+                .nr_resources   = ARRAY_SIZE(s5pc1xx_uart3_resource),
+        },
+};
+
+/* uart devices */
+
+static struct platform_device s3c24xx_uart_device0 = {
+        .id             = 0,
+};
+
+static struct platform_device s3c24xx_uart_device1 = {
+        .id             = 1,
+};
+
+static struct platform_device s3c24xx_uart_device2 = {
+        .id             = 2,
+};
+
+static struct platform_device s3c24xx_uart_device3 = {
+        .id             = 3,
+};
+
+struct platform_device *s3c24xx_uart_src[4] = {
+        &s3c24xx_uart_device0,
+        &s3c24xx_uart_device1,
+        &s3c24xx_uart_device2,
+        &s3c24xx_uart_device3,
+};
+
+struct platform_device *s3c24xx_uart_devs[4] = {
+};
+
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
new file mode 100644
index 000000000000..f07d8c3b25d6
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
@@ -0,0 +1,182 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/irqs.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX - Common IRQ support
+ *
+ * Based on plat-s3c64xx/include/plat/irqs.h
+ */
+
+#ifndef __ASM_PLAT_S5PC1XX_IRQS_H
+#define __ASM_PLAT_S5PC1XX_IRQS_H __FILE__
+
+/* we keep the first set of CPU IRQs out of the range of
+ * the ISA space, so that the PC104 has them to itself
+ * and we don't end up having to do horrible things to the
+ * standard ISA drivers....
+ *
+ * note, since we're using the VICs, our start must be a
+ * mulitple of 32 to allow the common code to work
+ */
+
+#define S3C_IRQ_OFFSET          (32)
+
+#define S3C_IRQ(x)              ((x) + S3C_IRQ_OFFSET)
+
+#define S3C_VIC0_BASE           S3C_IRQ(0)
+#define S3C_VIC1_BASE           S3C_IRQ(32)
+#define S3C_VIC2_BASE           S3C_IRQ(64)
+
+/* UART interrupts, each UART has 4 intterupts per channel so
+ * use the space between the ISA and S3C main interrupts. Note, these
+ * are not in the same order as the S3C24XX series! */
+
+#define IRQ_S3CUART_BASE0       (16)
+#define IRQ_S3CUART_BASE1       (20)
+#define IRQ_S3CUART_BASE2       (24)
+#define IRQ_S3CUART_BASE3       (28)
+
+#define UART_IRQ_RXD            (0)
+#define UART_IRQ_ERR            (1)
+#define UART_IRQ_TXD            (2)
+#define UART_IRQ_MODEM          (3)
+
+#define IRQ_S3CUART_RX0         (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX0         (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR0        (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX1         (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX1         (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR1        (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX2         (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX2         (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR2        (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX3         (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX3         (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR3        (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
+
+/* VIC based IRQs */
+
+#define S5PC1XX_IRQ_VIC0(x)     (S3C_VIC0_BASE + (x))
+#define S5PC1XX_IRQ_VIC1(x)     (S3C_VIC1_BASE + (x))
+#define S5PC1XX_IRQ_VIC2(x)     (S3C_VIC2_BASE + (x))
+
+/*
+ * VIC0: system, DMA, timer
+ */
+#define IRQ_EINT0               S5PC1XX_IRQ_VIC0(0)
+#define IRQ_EINT1               S5PC1XX_IRQ_VIC0(1)
+#define IRQ_EINT2               S5PC1XX_IRQ_VIC0(2)
+#define IRQ_EINT3               S5PC1XX_IRQ_VIC0(3)
+#define IRQ_EINT4               S5PC1XX_IRQ_VIC0(4)
+#define IRQ_EINT5               S5PC1XX_IRQ_VIC0(5)
+#define IRQ_EINT6               S5PC1XX_IRQ_VIC0(6)
+#define IRQ_EINT7               S5PC1XX_IRQ_VIC0(7)
+#define IRQ_EINT8               S5PC1XX_IRQ_VIC0(8)
+#define IRQ_EINT9               S5PC1XX_IRQ_VIC0(9)
+#define IRQ_EINT10              S5PC1XX_IRQ_VIC0(10)
+#define IRQ_EINT11              S5PC1XX_IRQ_VIC0(11)
+#define IRQ_EINT12              S5PC1XX_IRQ_VIC0(12)
+#define IRQ_EINT13              S5PC1XX_IRQ_VIC0(13)
+#define IRQ_EINT14              S5PC1XX_IRQ_VIC0(14)
+#define IRQ_EINT15              S5PC1XX_IRQ_VIC0(15)
+#define IRQ_EINT16_31           S5PC1XX_IRQ_VIC0(16)
+#define IRQ_BATF                S5PC1XX_IRQ_VIC0(17)
+#define IRQ_MDMA                S5PC1XX_IRQ_VIC0(18)
+#define IRQ_PDMA0               S5PC1XX_IRQ_VIC0(19)
+#define IRQ_PDMA1               S5PC1XX_IRQ_VIC0(20)
+#define IRQ_TIMER0              S5PC1XX_IRQ_VIC0(21)
+#define IRQ_TIMER1              S5PC1XX_IRQ_VIC0(22)
+#define IRQ_TIMER2              S5PC1XX_IRQ_VIC0(23)
+#define IRQ_TIMER3              S5PC1XX_IRQ_VIC0(24)
+#define IRQ_TIMER4              S5PC1XX_IRQ_VIC0(25)
+#define IRQ_SYSTIMER            S5PC1XX_IRQ_VIC0(26)
+#define IRQ_WDT                 S5PC1XX_IRQ_VIC0(27)
+#define IRQ_RTC_ALARM           S5PC1XX_IRQ_VIC0(28)
+#define IRQ_RTC_TIC             S5PC1XX_IRQ_VIC0(29)
+#define IRQ_GPIOINT             S5PC1XX_IRQ_VIC0(30)
+
+/*
+ * VIC1: ARM, power, memory, connectivity
+ */
+#define IRQ_CORTEX0             S5PC1XX_IRQ_VIC1(0)
+#define IRQ_CORTEX1             S5PC1XX_IRQ_VIC1(1)
+#define IRQ_CORTEX2             S5PC1XX_IRQ_VIC1(2)
+#define IRQ_CORTEX3             S5PC1XX_IRQ_VIC1(3)
+#define IRQ_CORTEX4             S5PC1XX_IRQ_VIC1(4)
+#define IRQ_IEMAPC              S5PC1XX_IRQ_VIC1(5)
+#define IRQ_IEMIEC              S5PC1XX_IRQ_VIC1(6)
+#define IRQ_ONENAND             S5PC1XX_IRQ_VIC1(7)
+#define IRQ_NFC                 S5PC1XX_IRQ_VIC1(8)
+#define IRQ_CFC                 S5PC1XX_IRQ_VIC1(9)
+#define IRQ_UART0               S5PC1XX_IRQ_VIC1(10)
+#define IRQ_UART1               S5PC1XX_IRQ_VIC1(11)
+#define IRQ_UART2               S5PC1XX_IRQ_VIC1(12)
+#define IRQ_UART3               S5PC1XX_IRQ_VIC1(13)
+#define IRQ_IIC                 S5PC1XX_IRQ_VIC1(14)
+#define IRQ_SPI0                S5PC1XX_IRQ_VIC1(15)
+#define IRQ_SPI1                S5PC1XX_IRQ_VIC1(16)
+#define IRQ_SPI2                S5PC1XX_IRQ_VIC1(17)
+#define IRQ_IRDA                S5PC1XX_IRQ_VIC1(18)
+#define IRQ_CAN0                S5PC1XX_IRQ_VIC1(19)
+#define IRQ_CAN1                S5PC1XX_IRQ_VIC1(20)
+#define IRQ_HSIRX               S5PC1XX_IRQ_VIC1(21)
+#define IRQ_HSITX               S5PC1XX_IRQ_VIC1(22)
+#define IRQ_UHOST               S5PC1XX_IRQ_VIC1(23)
+#define IRQ_OTG                 S5PC1XX_IRQ_VIC1(24)
+#define IRQ_MSM                 S5PC1XX_IRQ_VIC1(25)
+#define IRQ_HSMMC0              S5PC1XX_IRQ_VIC1(26)
+#define IRQ_HSMMC1              S5PC1XX_IRQ_VIC1(27)
+#define IRQ_HSMMC2              S5PC1XX_IRQ_VIC1(28)
+#define IRQ_MIPICSI             S5PC1XX_IRQ_VIC1(29)
+#define IRQ_MIPIDSI             S5PC1XX_IRQ_VIC1(30)
+
+/*
+ * VIC2: multimedia, audio, security
+ */
+#define IRQ_LCD0                S5PC1XX_IRQ_VIC2(0)
+#define IRQ_LCD1                S5PC1XX_IRQ_VIC2(1)
+#define IRQ_LCD2                S5PC1XX_IRQ_VIC2(2)
+#define IRQ_LCD3                S5PC1XX_IRQ_VIC2(3)
+#define IRQ_ROTATOR             S5PC1XX_IRQ_VIC2(4)
+#define IRQ_FIMC0               S5PC1XX_IRQ_VIC2(5)
+#define IRQ_FIMC1               S5PC1XX_IRQ_VIC2(6)
+#define IRQ_FIMC2               S5PC1XX_IRQ_VIC2(7)
+#define IRQ_JPEG                S5PC1XX_IRQ_VIC2(8)
+#define IRQ_2D                  S5PC1XX_IRQ_VIC2(9)
+#define IRQ_3D                  S5PC1XX_IRQ_VIC2(10)
+#define IRQ_MIXER               S5PC1XX_IRQ_VIC2(11)
+#define IRQ_HDMI                S5PC1XX_IRQ_VIC2(12)
+#define IRQ_IIC1                S5PC1XX_IRQ_VIC2(13)
+#define IRQ_MFC                 S5PC1XX_IRQ_VIC2(14)
+#define IRQ_TVENC               S5PC1XX_IRQ_VIC2(15)
+#define IRQ_I2S0                S5PC1XX_IRQ_VIC2(16)
+#define IRQ_I2S1                S5PC1XX_IRQ_VIC2(17)
+#define IRQ_I2S2                S5PC1XX_IRQ_VIC2(18)
+#define IRQ_AC97                S5PC1XX_IRQ_VIC2(19)
+#define IRQ_PCM0                S5PC1XX_IRQ_VIC2(20)
+#define IRQ_PCM1                S5PC1XX_IRQ_VIC2(21)
+#define IRQ_SPDIF               S5PC1XX_IRQ_VIC2(22)
+#define IRQ_ADC                 S5PC1XX_IRQ_VIC2(23)
+#define IRQ_PENDN               S5PC1XX_IRQ_VIC2(24)
+#define IRQ_TC                  IRQ_PENDN
+#define IRQ_KEYPAD              S5PC1XX_IRQ_VIC2(25)
+#define IRQ_CG                  S5PC1XX_IRQ_VIC2(26)
+#define IRQ_SEC                 S5PC1XX_IRQ_VIC2(27)
+#define IRQ_SECRX               S5PC1XX_IRQ_VIC2(28)
+#define IRQ_SECTX               S5PC1XX_IRQ_VIC2(29)
+#define IRQ_SDMIRQ              S5PC1XX_IRQ_VIC2(30)
+#define IRQ_SDMFIQ              S5PC1XX_IRQ_VIC2(31)
+
+#define S3C_IRQ_EINT_BASE       (IRQ_SDMFIQ + 1)
+
+#define S3C_EINT(x)             ((x) + S3C_IRQ_EINT_BASE)
+#define IRQ_EINT(x)             S3C_EINT(x)
+
+#define NR_IRQS                 (IRQ_EINT(31)+1)
+
+#endif /* __ASM_PLAT_S5PC1XX_IRQS_H */
+
diff --git a/arch/arm/plat-s5pc1xx/include/plat/pll.h b/arch/arm/plat-s5pc1xx/include/plat/pll.h
new file mode 100644
index 000000000000..21afef1573e7
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/pll.h
@@ -0,0 +1,38 @@
+/* arch/arm/plat-s5pc1xx/include/plat/pll.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX PLL code
+ *
+ * Based on plat-s3c64xx/include/plat/pll.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S5P_PLL_MDIV_MASK       ((1 << (25-16+1)) - 1)
+#define S5P_PLL_PDIV_MASK       ((1 << (13-8+1)) - 1)
+#define S5P_PLL_SDIV_MASK       ((1 << (2-0+1)) - 1)
+#define S5P_PLL_MDIV_SHIFT      (16)
+#define S5P_PLL_PDIV_SHIFT      (8)
+#define S5P_PLL_SDIV_SHIFT      (0)
+
+#include <asm/div64.h>
+
+static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk,
+                                            u32 pllcon)
+{
+        u32 mdiv, pdiv, sdiv;
+        u64 fvco = baseclk;
+
+        mdiv = (pllcon >> S5P_PLL_MDIV_SHIFT) & S5P_PLL_MDIV_MASK;
+        pdiv = (pllcon >> S5P_PLL_PDIV_SHIFT) & S5P_PLL_PDIV_MASK;
+        sdiv = (pllcon >> S5P_PLL_SDIV_SHIFT) & S5P_PLL_SDIV_MASK;
+
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+
+        return (unsigned long)fvco;
+}
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
new file mode 100644
index 000000000000..75c8390cb827
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
@@ -0,0 +1,421 @@
+/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_CLOCK_H
+#define __PLAT_REGS_CLOCK_H __FILE__
+
+#define S5PC1XX_CLKREG(x)               (S5PC1XX_VA_CLK + (x))
+
+#define S5PC1XX_APLL_LOCK               S5PC1XX_CLKREG(0x00)
+#define S5PC1XX_MPLL_LOCK               S5PC1XX_CLKREG(0x04)
+#define S5PC1XX_EPLL_LOCK               S5PC1XX_CLKREG(0x08)
+#define S5PC100_HPLL_LOCK               S5PC1XX_CLKREG(0x0C)
+
+#define S5PC1XX_APLL_CON                S5PC1XX_CLKREG(0x100)
+#define S5PC1XX_MPLL_CON                S5PC1XX_CLKREG(0x104)
+#define S5PC1XX_EPLL_CON                S5PC1XX_CLKREG(0x108)
+#define S5PC100_HPLL_CON                S5PC1XX_CLKREG(0x10C)
+
+#define S5PC1XX_CLK_SRC0                S5PC1XX_CLKREG(0x200)
+#define S5PC1XX_CLK_SRC1                S5PC1XX_CLKREG(0x204)
+#define S5PC1XX_CLK_SRC2                S5PC1XX_CLKREG(0x208)
+#define S5PC1XX_CLK_SRC3                S5PC1XX_CLKREG(0x20C)
+
+#define S5PC1XX_CLK_DIV0                S5PC1XX_CLKREG(0x300)
+#define S5PC1XX_CLK_DIV1                S5PC1XX_CLKREG(0x304)
+#define S5PC1XX_CLK_DIV2                S5PC1XX_CLKREG(0x308)
+#define S5PC1XX_CLK_DIV3                S5PC1XX_CLKREG(0x30C)
+#define S5PC1XX_CLK_DIV4                S5PC1XX_CLKREG(0x310)
+
+#define S5PC100_CLK_OUT                 S5PC1XX_CLKREG(0x400)
+
+#define S5PC100_CLKGATE_D00             S5PC1XX_CLKREG(0x500)
+#define S5PC100_CLKGATE_D01             S5PC1XX_CLKREG(0x504)
+#define S5PC100_CLKGATE_D02             S5PC1XX_CLKREG(0x508)
+
+#define S5PC100_CLKGATE_D10             S5PC1XX_CLKREG(0x520)
+#define S5PC100_CLKGATE_D11             S5PC1XX_CLKREG(0x524)
+#define S5PC100_CLKGATE_D12             S5PC1XX_CLKREG(0x528)
+#define S5PC100_CLKGATE_D13             S5PC1XX_CLKREG(0x52C)
+#define S5PC100_CLKGATE_D14             S5PC1XX_CLKREG(0x530)
+#define S5PC100_CLKGATE_D15             S5PC1XX_CLKREG(0x534)
+
+#define S5PC100_CLKGATE_D20             S5PC1XX_CLKREG(0x540)
+
+#define S5PC100_SCLKGATE0               S5PC1XX_CLKREG(0x560)
+#define S5PC100_SCLKGATE1               S5PC1XX_CLKREG(0x564)
+
+#define S5PC100_OTHERS          S5PC1XX_CLKREG(0x8200)
+
+#define S5PC1XX_EPLL_EN     (1<<31)
+#define S5PC1XX_EPLL_MASK   0xffffffff
+#define S5PC1XX_EPLLVAL(_m, _p, _s)   ((_m) << 16 | ((_p) << 8) | ((_s)))
+
+/* CLKSRC0 */
+#define S5PC1XX_CLKSRC0_APLL_MASK               (0x1<<0)
+#define S5PC1XX_CLKSRC0_APLL_SHIFT              (0)
+#define S5PC1XX_CLKSRC0_MPLL_MASK               (0x1<<4)
+#define S5PC1XX_CLKSRC0_MPLL_SHIFT              (4)
+#define S5PC1XX_CLKSRC0_EPLL_MASK               (0x1<<8)
+#define S5PC1XX_CLKSRC0_EPLL_SHIFT              (8)
+#define S5PC100_CLKSRC0_HPLL_MASK               (0x1<<12)
+#define S5PC100_CLKSRC0_HPLL_SHIFT              (12)
+#define S5PC100_CLKSRC0_AMMUX_MASK              (0x1<<16)
+#define S5PC100_CLKSRC0_AMMUX_SHIFT             (16)
+#define S5PC100_CLKSRC0_HREF_MASK               (0x1<<20)
+#define S5PC100_CLKSRC0_HREF_SHIFT              (20)
+#define S5PC1XX_CLKSRC0_ONENAND_MASK    (0x1<<24)
+#define S5PC1XX_CLKSRC0_ONENAND_SHIFT   (24)
+
+
+/* CLKSRC1 */
+#define S5PC100_CLKSRC1_UART_MASK               (0x1<<0)
+#define S5PC100_CLKSRC1_UART_SHIFT              (0)
+#define S5PC100_CLKSRC1_SPI0_MASK               (0x3<<4)
+#define S5PC100_CLKSRC1_SPI0_SHIFT              (4)
+#define S5PC100_CLKSRC1_SPI1_MASK               (0x3<<8)
+#define S5PC100_CLKSRC1_SPI1_SHIFT              (8)
+#define S5PC100_CLKSRC1_SPI2_MASK               (0x3<<12)
+#define S5PC100_CLKSRC1_SPI2_SHIFT              (12)
+#define S5PC100_CLKSRC1_IRDA_MASK               (0x3<<16)
+#define S5PC100_CLKSRC1_IRDA_SHIFT              (16)
+#define S5PC100_CLKSRC1_UHOST_MASK              (0x3<<20)
+#define S5PC100_CLKSRC1_UHOST_SHIFT             (20)
+#define S5PC100_CLKSRC1_CLK48M_MASK             (0x1<<24)
+#define S5PC100_CLKSRC1_CLK48M_SHIFT    (24)
+
+/* CLKSRC2 */
+#define S5PC100_CLKSRC2_MMC0_MASK               (0x3<<0)
+#define S5PC100_CLKSRC2_MMC0_SHIFT              (0)
+#define S5PC100_CLKSRC2_MMC1_MASK               (0x3<<4)
+#define S5PC100_CLKSRC2_MMC1_SHIFT              (4)
+#define S5PC100_CLKSRC2_MMC2_MASK               (0x3<<8)
+#define S5PC100_CLKSRC2_MMC2_SHIFT              (8)
+#define S5PC100_CLKSRC2_LCD_MASK                (0x3<<12)
+#define S5PC100_CLKSRC2_LCD_SHIFT               (12)
+#define S5PC100_CLKSRC2_FIMC0_MASK              (0x3<<16)
+#define S5PC100_CLKSRC2_FIMC0_SHIFT             (16)
+#define S5PC100_CLKSRC2_FIMC1_MASK              (0x3<<20)
+#define S5PC100_CLKSRC2_FIMC1_SHIFT             (20)
+#define S5PC100_CLKSRC2_FIMC2_MASK              (0x3<<24)
+#define S5PC100_CLKSRC2_FIMC2_SHIFT             (24)
+#define S5PC100_CLKSRC2_MIXER_MASK              (0x3<<28)
+#define S5PC100_CLKSRC2_MIXER_SHIFT             (28)
+
+/* CLKSRC3 */
+#define S5PC100_CLKSRC3_PWI_MASK                (0x3<<0)
+#define S5PC100_CLKSRC3_PWI_SHIFT               (0)
+#define S5PC100_CLKSRC3_HCLKD2_MASK             (0x1<<4)
+#define S5PC100_CLKSRC3_HCLKD2_SHIFT    (4)
+#define S5PC100_CLKSRC3_I2SD2_MASK              (0x3<<8)
+#define S5PC100_CLKSRC3_I2SD2_SHIFT             (8)
+#define S5PC100_CLKSRC3_AUDIO0_MASK             (0x7<<12)
+#define S5PC100_CLKSRC3_AUDIO0_SHIFT    (12)
+#define S5PC100_CLKSRC3_AUDIO1_MASK             (0x7<<16)
+#define S5PC100_CLKSRC3_AUDIO1_SHIFT    (16)
+#define S5PC100_CLKSRC3_AUDIO2_MASK             (0x7<<20)
+#define S5PC100_CLKSRC3_AUDIO2_SHIFT    (20)
+#define S5PC100_CLKSRC3_SPDIF_MASK              (0x3<<24)
+#define S5PC100_CLKSRC3_SPDIF_SHIFT             (24)
+
+
+/* CLKDIV0 */
+#define S5PC1XX_CLKDIV0_APLL_MASK               (0x1<<0)
+#define S5PC1XX_CLKDIV0_APLL_SHIFT              (0)
+#define S5PC100_CLKDIV0_ARM_MASK                (0x7<<4)
+#define S5PC100_CLKDIV0_ARM_SHIFT               (4)
+#define S5PC100_CLKDIV0_D0_MASK         (0x7<<8)
+#define S5PC100_CLKDIV0_D0_SHIFT                (8)
+#define S5PC100_CLKDIV0_PCLKD0_MASK             (0x7<<12)
+#define S5PC100_CLKDIV0_PCLKD0_SHIFT    (12)
+#define S5PC100_CLKDIV0_SECSS_MASK              (0x7<<16)
+#define S5PC100_CLKDIV0_SECSS_SHIFT             (16)
+
+/* CLKDIV1 */
+#define S5PC100_CLKDIV1_AM_MASK         (0x7<<0)
+#define S5PC100_CLKDIV1_AM_SHIFT                (0)
+#define S5PC100_CLKDIV1_MPLL_MASK               (0x3<<4)
+#define S5PC100_CLKDIV1_MPLL_SHIFT              (4)
+#define S5PC100_CLKDIV1_MPLL2_MASK              (0x1<<8)
+#define S5PC100_CLKDIV1_MPLL2_SHIFT             (8)
+#define S5PC100_CLKDIV1_D1_MASK         (0x7<<12)
+#define S5PC100_CLKDIV1_D1_SHIFT                (12)
+#define S5PC100_CLKDIV1_PCLKD1_MASK             (0x7<<16)
+#define S5PC100_CLKDIV1_PCLKD1_SHIFT    (16)
+#define S5PC100_CLKDIV1_ONENAND_MASK    (0x3<<20)
+#define S5PC100_CLKDIV1_ONENAND_SHIFT   (20)
+#define S5PC100_CLKDIV1_CAM_MASK                (0x1F<<24)
+#define S5PC100_CLKDIV1_CAM_SHIFT               (24)
+
+/* CLKDIV2 */
+#define S5PC100_CLKDIV2_UART_MASK               (0x7<<0)
+#define S5PC100_CLKDIV2_UART_SHIFT              (0)
+#define S5PC100_CLKDIV2_SPI0_MASK               (0xf<<4)
+#define S5PC100_CLKDIV2_SPI0_SHIFT              (4)
+#define S5PC100_CLKDIV2_SPI1_MASK               (0xf<<8)
+#define S5PC100_CLKDIV2_SPI1_SHIFT              (8)
+#define S5PC100_CLKDIV2_SPI2_MASK               (0xf<<12)
+#define S5PC100_CLKDIV2_SPI2_SHIFT              (12)
+#define S5PC100_CLKDIV2_IRDA_MASK               (0xf<<16)
+#define S5PC100_CLKDIV2_IRDA_SHIFT              (16)
+#define S5PC100_CLKDIV2_UHOST_MASK              (0xf<<20)
+#define S5PC100_CLKDIV2_UHOST_SHIFT             (20)
+
+/* CLKDIV3 */
+#define S5PC100_CLKDIV3_MMC0_MASK               (0xf<<0)
+#define S5PC100_CLKDIV3_MMC0_SHIFT              (0)
+#define S5PC100_CLKDIV3_MMC1_MASK               (0xf<<4)
+#define S5PC100_CLKDIV3_MMC1_SHIFT              (4)
+#define S5PC100_CLKDIV3_MMC2_MASK               (0xf<<8)
+#define S5PC100_CLKDIV3_MMC2_SHIFT              (8)
+#define S5PC100_CLKDIV3_LCD_MASK                (0xf<<12)
+#define S5PC100_CLKDIV3_LCD_SHIFT               (12)
+#define S5PC100_CLKDIV3_FIMC0_MASK              (0xf<<16)
+#define S5PC100_CLKDIV3_FIMC0_SHIFT             (16)
+#define S5PC100_CLKDIV3_FIMC1_MASK              (0xf<<20)
+#define S5PC100_CLKDIV3_FIMC1_SHIFT             (20)
+#define S5PC100_CLKDIV3_FIMC2_MASK              (0xf<<24)
+#define S5PC100_CLKDIV3_FIMC2_SHIFT             (24)
+#define S5PC100_CLKDIV3_HDMI_MASK               (0xf<<28)
+#define S5PC100_CLKDIV3_HDMI_SHIFT              (28)
+
+/* CLKDIV4 */
+#define S5PC100_CLKDIV4_PWI_MASK                (0x7<<0)
+#define S5PC100_CLKDIV4_PWI_SHIFT               (0)
+#define S5PC100_CLKDIV4_HCLKD2_MASK             (0x7<<4)
+#define S5PC100_CLKDIV4_HCLKD2_SHIFT    (4)
+#define S5PC100_CLKDIV4_I2SD2_MASK              (0xf<<8)
+#define S5PC100_CLKDIV4_I2SD2_SHIFT             (8)
+#define S5PC100_CLKDIV4_AUDIO0_MASK             (0xf<<12)
+#define S5PC100_CLKDIV4_AUDIO0_SHIFT    (12)
+#define S5PC100_CLKDIV4_AUDIO1_MASK             (0xf<<16)
+#define S5PC100_CLKDIV4_AUDIO1_SHIFT    (16)
+#define S5PC100_CLKDIV4_AUDIO2_MASK             (0xf<<20)
+#define S5PC100_CLKDIV4_AUDIO2_SHIFT    (20)
+
+
+/* HCLKD0/PCLKD0 Clock Gate 0 Registers */
+#define S5PC100_CLKGATE_D00_INTC                (1<<0)
+#define S5PC100_CLKGATE_D00_TZIC                (1<<1)
+#define S5PC100_CLKGATE_D00_CFCON               (1<<2)
+#define S5PC100_CLKGATE_D00_MDMA                (1<<3)
+#define S5PC100_CLKGATE_D00_G2D         (1<<4)
+#define S5PC100_CLKGATE_D00_SECSS               (1<<5)
+#define S5PC100_CLKGATE_D00_CSSYS               (1<<6)
+
+/* HCLKD0/PCLKD0 Clock Gate 1 Registers */
+#define S5PC100_CLKGATE_D01_DMC         (1<<0)
+#define S5PC100_CLKGATE_D01_SROMC               (1<<1)
+#define S5PC100_CLKGATE_D01_ONENAND             (1<<2)
+#define S5PC100_CLKGATE_D01_NFCON               (1<<3)
+#define S5PC100_CLKGATE_D01_INTMEM              (1<<4)
+#define S5PC100_CLKGATE_D01_EBI         (1<<5)
+
+/* PCLKD0 Clock Gate 2 Registers */
+#define S5PC100_CLKGATE_D02_SECKEY              (1<<1)
+#define S5PC100_CLKGATE_D02_SDM         (1<<2)
+
+/* HCLKD1/PCLKD1 Clock Gate 0 Registers */
+#define S5PC100_CLKGATE_D10_PDMA0               (1<<0)
+#define S5PC100_CLKGATE_D10_PDMA1               (1<<1)
+#define S5PC100_CLKGATE_D10_USBHOST             (1<<2)
+#define S5PC100_CLKGATE_D10_USBOTG              (1<<3)
+#define S5PC100_CLKGATE_D10_MODEMIF             (1<<4)
+#define S5PC100_CLKGATE_D10_HSMMC0              (1<<5)
+#define S5PC100_CLKGATE_D10_HSMMC1              (1<<6)
+#define S5PC100_CLKGATE_D10_HSMMC2              (1<<7)
+
+/* HCLKD1/PCLKD1 Clock Gate 1 Registers */
+#define S5PC100_CLKGATE_D11_LCD         (1<<0)
+#define S5PC100_CLKGATE_D11_ROTATOR             (1<<1)
+#define S5PC100_CLKGATE_D11_FIMC0               (1<<2)
+#define S5PC100_CLKGATE_D11_FIMC1               (1<<3)
+#define S5PC100_CLKGATE_D11_FIMC2               (1<<4)
+#define S5PC100_CLKGATE_D11_JPEG                (1<<5)
+#define S5PC100_CLKGATE_D11_DSI         (1<<6)
+#define S5PC100_CLKGATE_D11_CSI         (1<<7)
+#define S5PC100_CLKGATE_D11_G3D         (1<<8)
+
+/* HCLKD1/PCLKD1 Clock Gate 2 Registers */
+#define S5PC100_CLKGATE_D12_TV          (1<<0)
+#define S5PC100_CLKGATE_D12_VP          (1<<1)
+#define S5PC100_CLKGATE_D12_MIXER               (1<<2)
+#define S5PC100_CLKGATE_D12_HDMI                (1<<3)
+#define S5PC100_CLKGATE_D12_MFC         (1<<4)
+
+/* HCLKD1/PCLKD1 Clock Gate 3 Registers */
+#define S5PC100_CLKGATE_D13_CHIPID              (1<<0)
+#define S5PC100_CLKGATE_D13_GPIO                (1<<1)
+#define S5PC100_CLKGATE_D13_APC         (1<<2)
+#define S5PC100_CLKGATE_D13_IEC         (1<<3)
+#define S5PC100_CLKGATE_D13_PWM         (1<<6)
+#define S5PC100_CLKGATE_D13_SYSTIMER    (1<<7)
+#define S5PC100_CLKGATE_D13_WDT         (1<<8)
+#define S5PC100_CLKGATE_D13_RTC         (1<<9)
+
+/* HCLKD1/PCLKD1 Clock Gate 4 Registers */
+#define S5PC100_CLKGATE_D14_UART0               (1<<0)
+#define S5PC100_CLKGATE_D14_UART1               (1<<1)
+#define S5PC100_CLKGATE_D14_UART2               (1<<2)
+#define S5PC100_CLKGATE_D14_UART3               (1<<3)
+#define S5PC100_CLKGATE_D14_IIC         (1<<4)
+#define S5PC100_CLKGATE_D14_HDMI_IIC    (1<<5)
+#define S5PC100_CLKGATE_D14_SPI0                (1<<6)
+#define S5PC100_CLKGATE_D14_SPI1                (1<<7)
+#define S5PC100_CLKGATE_D14_SPI2                (1<<8)
+#define S5PC100_CLKGATE_D14_IRDA                (1<<9)
+#define S5PC100_CLKGATE_D14_CCAN0               (1<<10)
+#define S5PC100_CLKGATE_D14_CCAN1               (1<<11)
+#define S5PC100_CLKGATE_D14_HSITX               (1<<12)
+#define S5PC100_CLKGATE_D14_HSIRX               (1<<13)
+
+/* HCLKD1/PCLKD1 Clock Gate 5 Registers */
+#define S5PC100_CLKGATE_D15_IIS0                (1<<0)
+#define S5PC100_CLKGATE_D15_IIS1                (1<<1)
+#define S5PC100_CLKGATE_D15_IIS2                (1<<2)
+#define S5PC100_CLKGATE_D15_AC97                (1<<3)
+#define S5PC100_CLKGATE_D15_PCM0                (1<<4)
+#define S5PC100_CLKGATE_D15_PCM1                (1<<5)
+#define S5PC100_CLKGATE_D15_SPDIF               (1<<6)
+#define S5PC100_CLKGATE_D15_TSADC               (1<<7)
+#define S5PC100_CLKGATE_D15_KEYIF               (1<<8)
+#define S5PC100_CLKGATE_D15_CG          (1<<9)
+
+/* HCLKD2 Clock Gate 0 Registers */
+#define S5PC100_CLKGATE_D20_HCLKD2              (1<<0)
+#define S5PC100_CLKGATE_D20_I2SD2               (1<<1)
+
+/* Special Clock Gate 0 Registers */
+#define S5PC1XX_CLKGATE_SCLK0_HPM               (1<<0)
+#define S5PC1XX_CLKGATE_SCLK0_PWI               (1<<1)
+#define S5PC100_CLKGATE_SCLK0_ONENAND   (1<<2)
+#define S5PC100_CLKGATE_SCLK0_UART              (1<<3)
+#define S5PC100_CLKGATE_SCLK0_SPI0              (1<<4)
+#define S5PC100_CLKGATE_SCLK0_SPI1              (1<<5)
+#define S5PC100_CLKGATE_SCLK0_SPI2              (1<<6)
+#define S5PC100_CLKGATE_SCLK0_SPI0_48   (1<<7)
+#define S5PC100_CLKGATE_SCLK0_SPI1_48   (1<<8)
+#define S5PC100_CLKGATE_SCLK0_SPI2_48   (1<<9)
+#define S5PC100_CLKGATE_SCLK0_IRDA              (1<<10)
+#define S5PC100_CLKGATE_SCLK0_USBHOST   (1<<11)
+#define S5PC100_CLKGATE_SCLK0_MMC0              (1<<12)
+#define S5PC100_CLKGATE_SCLK0_MMC1              (1<<13)
+#define S5PC100_CLKGATE_SCLK0_MMC2              (1<<14)
+#define S5PC100_CLKGATE_SCLK0_MMC0_48   (1<<15)
+#define S5PC100_CLKGATE_SCLK0_MMC1_48   (1<<16)
+#define S5PC100_CLKGATE_SCLK0_MMC2_48   (1<<17)
+
+/* Special Clock Gate 1 Registers */
+#define S5PC100_CLKGATE_SCLK1_LCD               (1<<0)
+#define S5PC100_CLKGATE_SCLK1_FIMC0             (1<<1)
+#define S5PC100_CLKGATE_SCLK1_FIMC1             (1<<2)
+#define S5PC100_CLKGATE_SCLK1_FIMC2             (1<<3)
+#define S5PC100_CLKGATE_SCLK1_TV54              (1<<4)
+#define S5PC100_CLKGATE_SCLK1_VDAC54    (1<<5)
+#define S5PC100_CLKGATE_SCLK1_MIXER             (1<<6)
+#define S5PC100_CLKGATE_SCLK1_HDMI              (1<<7)
+#define S5PC100_CLKGATE_SCLK1_AUDIO0    (1<<8)
+#define S5PC100_CLKGATE_SCLK1_AUDIO1    (1<<9)
+#define S5PC100_CLKGATE_SCLK1_AUDIO2    (1<<10)
+#define S5PC100_CLKGATE_SCLK1_SPDIF             (1<<11)
+#define S5PC100_CLKGATE_SCLK1_CAM               (1<<12)
+
+/* register for power management */
+#define S5PC100_PWR_CFG                 S5PC1XX_CLKREG(0x8000)
+#define S5PC100_EINT_WAKEUP_MASK        S5PC1XX_CLKREG(0x8004)
+#define S5PC100_NORMAL_CFG              S5PC1XX_CLKREG(0x8010)
+#define S5PC100_STOP_CFG                S5PC1XX_CLKREG(0x8014)
+#define S5PC100_SLEEP_CFG               S5PC1XX_CLKREG(0x8018)
+#define S5PC100_STOP_MEM_CFG    S5PC1XX_CLKREG(0x801C)
+#define S5PC100_OSC_FREQ                S5PC1XX_CLKREG(0x8100)
+#define S5PC100_OSC_STABLE              S5PC1XX_CLKREG(0x8104)
+#define S5PC100_PWR_STABLE              S5PC1XX_CLKREG(0x8108)
+#define S5PC100_MTC_STABLE              S5PC1XX_CLKREG(0x8110)
+#define S5PC100_CLAMP_STABLE    S5PC1XX_CLKREG(0x8114)
+#define S5PC100_OTHERS          S5PC1XX_CLKREG(0x8200)
+#define S5PC100_RST_STAT                S5PC1XX_CLKREG(0x8300)
+#define S5PC100_WAKEUP_STAT     S5PC1XX_CLKREG(0x8304)
+#define S5PC100_BLK_PWR_STAT    S5PC1XX_CLKREG(0x8308)
+#define S5PC100_INFORM0                 S5PC1XX_CLKREG(0x8400)
+#define S5PC100_INFORM1                 S5PC1XX_CLKREG(0x8404)
+#define S5PC100_INFORM2                 S5PC1XX_CLKREG(0x8408)
+#define S5PC100_INFORM3                 S5PC1XX_CLKREG(0x840C)
+#define S5PC100_INFORM4                 S5PC1XX_CLKREG(0x8410)
+#define S5PC100_INFORM5                 S5PC1XX_CLKREG(0x8414)
+#define S5PC100_INFORM6                 S5PC1XX_CLKREG(0x8418)
+#define S5PC100_INFORM7                 S5PC1XX_CLKREG(0x841C)
+#define S5PC100_DCGIDX_MAP0     S5PC1XX_CLKREG(0x8500)
+#define S5PC100_DCGIDX_MAP1     S5PC1XX_CLKREG(0x8504)
+#define S5PC100_DCGIDX_MAP2     S5PC1XX_CLKREG(0x8508)
+#define S5PC100_DCGPERF_MAP0    S5PC1XX_CLKREG(0x850C)
+#define S5PC100_DCGPERF_MAP1    S5PC1XX_CLKREG(0x8510)
+#define S5PC100_DVCIDX_MAP              S5PC1XX_CLKREG(0x8514)
+#define S5PC100_FREQ_CPU                S5PC1XX_CLKREG(0x8518)
+#define S5PC100_FREQ_DPM                S5PC1XX_CLKREG(0x851C)
+#define S5PC100_DVSEMCLK_EN     S5PC1XX_CLKREG(0x8520)
+#define S5PC100_APLL_CON_L8     S5PC1XX_CLKREG(0x8600)
+#define S5PC100_APLL_CON_L7     S5PC1XX_CLKREG(0x8604)
+#define S5PC100_APLL_CON_L6     S5PC1XX_CLKREG(0x8608)
+#define S5PC100_APLL_CON_L5     S5PC1XX_CLKREG(0x860C)
+#define S5PC100_APLL_CON_L4     S5PC1XX_CLKREG(0x8610)
+#define S5PC100_APLL_CON_L3     S5PC1XX_CLKREG(0x8614)
+#define S5PC100_APLL_CON_L2     S5PC1XX_CLKREG(0x8618)
+#define S5PC100_APLL_CON_L1     S5PC1XX_CLKREG(0x861C)
+#define S5PC100_IEM_CONTROL     S5PC1XX_CLKREG(0x8620)
+#define S5PC100_CLKDIV_IEM_L8   S5PC1XX_CLKREG(0x8700)
+#define S5PC100_CLKDIV_IEM_L7   S5PC1XX_CLKREG(0x8704)
+#define S5PC100_CLKDIV_IEM_L6   S5PC1XX_CLKREG(0x8708)
+#define S5PC100_CLKDIV_IEM_L5   S5PC1XX_CLKREG(0x870C)
+#define S5PC100_CLKDIV_IEM_L4   S5PC1XX_CLKREG(0x8710)
+#define S5PC100_CLKDIV_IEM_L3   S5PC1XX_CLKREG(0x8714)
+#define S5PC100_CLKDIV_IEM_L2   S5PC1XX_CLKREG(0x8718)
+#define S5PC100_CLKDIV_IEM_L1   S5PC1XX_CLKREG(0x871C)
+#define S5PC100_IEM_HPMCLK_DIV  S5PC1XX_CLKREG(0x8724)
+
+#define S5PC100_SWRESET         S5PC1XX_CLKREG(0x100000)
+#define S5PC100_OND_SWRESET             S5PC1XX_CLKREG(0x100008)
+#define S5PC100_GEN_CTRL                S5PC1XX_CLKREG(0x100100)
+#define S5PC100_GEN_STATUS              S5PC1XX_CLKREG(0x100104)
+#define S5PC100_MEM_SYS_CFG             S5PC1XX_CLKREG(0x100200)
+#define S5PC100_CAM_MUX_SEL             S5PC1XX_CLKREG(0x100300)
+#define S5PC100_MIXER_OUT_SEL   S5PC1XX_CLKREG(0x100304)
+#define S5PC100_LPMP_MODE_SEL   S5PC1XX_CLKREG(0x100308)
+#define S5PC100_MIPI_PHY_CON0   S5PC1XX_CLKREG(0x100400)
+#define S5PC100_MIPI_PHY_CON1   S5PC1XX_CLKREG(0x100414)
+#define S5PC100_HDMI_PHY_CON0   S5PC1XX_CLKREG(0x100420)
+
+#define S5PC100_CFG_WFI_CLEAN   (~(3<<5))
+#define S5PC100_CFG_WFI_IDLE    (1<<5)
+#define S5PC100_CFG_WFI_STOP    (2<<5)
+#define S5PC100_CFG_WFI_SLEEP   (3<<5)
+
+#define S5PC100_OTHER_SYS_INT   24
+#define S5PC100_OTHER_STA_TYPE  23
+#define STA_TYPE_EXPON          0
+#define STA_TYPE_SFR            1
+
+#define S5PC100_PWR_STA_EXP_SCALE       0
+#define S5PC100_PWR_STA_CNT             4
+
+#define S5PC100_PWR_STABLE_COUNT        85500
+
+#define S5PC100_SLEEP_CFG_OSC_EN        0
+
+/* OTHERS Resgister */
+#define S5PC100_OTHERS_USB_SIG_MASK     (1 << 16)
+#define S5PC100_OTHERS_MIPI_DPHY_EN             (1 << 28)
+
+/* MIPI D-PHY Control Register 0 */
+#define S5PC100_MIPI_PHY_CON0_M_RESETN  (1 << 1)
+#define S5PC100_MIPI_PHY_CON0_S_RESETN  (1 << 0)
+
+#endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
new file mode 100644
index 000000000000..45e275131665
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
@@ -0,0 +1,65 @@
+/* arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Header file for s5pc100 cpu support
+ *
+ * Based on plat-s3c64xx/include/plat/s3c6400.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for S5PC100 related SoCs */
+extern  int s5pc100_init(void);
+extern void s5pc100_map_io(void);
+extern void s5pc100_init_clocks(int xtal);
+extern  int s5pc100_register_baseclocks(unsigned long xtal);
+extern void s5pc100_init_irq(void);
+extern void s5pc100_init_io(struct map_desc *mach_desc, int size);
+extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s5pc100_register_clocks(void);
+extern void s5pc100_setup_clocks(void);
+extern struct sysdev_class s5pc100_sysclass;
+
+#define s5pc100_init_uarts s5pc100_common_init_uarts
+
+/* Some day, belows will be moved to plat-s5pc/include/plat/cpu.h */
+extern void s5pc1xx_init_irq(u32 *vic_valid, int num);
+extern void s5pc1xx_init_io(struct map_desc *mach_desc, int size);
+
+/* Some day, belows will be moved to plat-s5pc/include/plat/clock.h */
+extern struct clk clk_hpll;
+extern struct clk clk_hd0;
+extern struct clk clk_pd0;
+extern struct clk clk_54m;
+extern struct clk clk_dout_mpll2;
+extern void s5pc1xx_register_clocks(void);
+extern int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable);
+extern int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable);
+
+/* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */
+extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
+extern struct platform_device s3c_device_g2d;
+extern struct platform_device s3c_device_g3d;
+extern struct platform_device s3c_device_vpp;
+extern struct platform_device s3c_device_tvenc;
+extern struct platform_device s3c_device_tvscaler;
+extern struct platform_device s3c_device_rotator;
+extern struct platform_device s3c_device_jpeg;
+extern struct platform_device s3c_device_onenand;
+extern struct platform_device s3c_device_usb_otghcd;
+extern struct platform_device s3c_device_keypad;
+extern struct platform_device s3c_device_ts;
+extern struct platform_device s3c_device_g3d;
+extern struct platform_device s3c_device_smc911x;
+extern struct platform_device s3c_device_fimc0;
+extern struct platform_device s3c_device_fimc1;
+extern struct platform_device s3c_device_mfc;
+extern struct platform_device s3c_device_ac97;
+extern struct platform_device s3c_device_fimc0;
+extern struct platform_device s3c_device_fimc1;
+extern struct platform_device s3c_device_fimc2;
+
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c
new file mode 100644
index 000000000000..80d6dd942cb8
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/irq.c
@@ -0,0 +1,259 @@
+/* arch/arm/plat-s5pc1xx/irq.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX - Interrupt handling
+ *
+ * Based on plat-s3c64xx/irq.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <asm/hardware/vic.h>
+
+#include <mach/map.h>
+#include <plat/regs-timer.h>
+#include <plat/cpu.h>
+
+/* Timer interrupt handling */
+
+static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
+{
+        generic_handle_irq(sub_irq);
+}
+
+static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_timer(irq, IRQ_TIMER0);
+}
+
+static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_timer(irq, IRQ_TIMER1);
+}
+
+static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_timer(irq, IRQ_TIMER2);
+}
+
+static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_timer(irq, IRQ_TIMER3);
+}
+
+static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_timer(irq, IRQ_TIMER4);
+}
+
+/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
+
+static void s3c_irq_timer_mask(unsigned int irq)
+{
+        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+
+        reg &= 0x1f;  /* mask out pending interrupts */
+        reg &= ~(1 << (irq - IRQ_TIMER0));
+        __raw_writel(reg, S3C64XX_TINT_CSTAT);
+}
+
+static void s3c_irq_timer_unmask(unsigned int irq)
+{
+        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+
+        reg &= 0x1f;  /* mask out pending interrupts */
+        reg |= 1 << (irq - IRQ_TIMER0);
+        __raw_writel(reg, S3C64XX_TINT_CSTAT);
+}
+
+static void s3c_irq_timer_ack(unsigned int irq)
+{
+        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+
+        reg &= 0x1f;
+        reg |= (1 << 5) << (irq - IRQ_TIMER0);
+        __raw_writel(reg, S3C64XX_TINT_CSTAT);
+}
+
+static struct irq_chip s3c_irq_timer = {
+        .name           = "s3c-timer",
+        .mask           = s3c_irq_timer_mask,
+        .unmask         = s3c_irq_timer_unmask,
+        .ack            = s3c_irq_timer_ack,
+};
+
+struct uart_irq {
+        void __iomem    *regs;
+        unsigned int     base_irq;
+        unsigned int     parent_irq;
+};
+
+/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
+ * are consecutive when looking up the interrupt in the demux routines.
+ */
+static struct uart_irq uart_irqs[] = {
+        [0] = {
+                .regs           = (void *)S3C_VA_UART0,
+                .base_irq       = IRQ_S3CUART_BASE0,
+                .parent_irq     = IRQ_UART0,
+        },
+        [1] = {
+                .regs           = (void *)S3C_VA_UART1,
+                .base_irq       = IRQ_S3CUART_BASE1,
+                .parent_irq     = IRQ_UART1,
+        },
+        [2] = {
+                .regs           = (void *)S3C_VA_UART2,
+                .base_irq       = IRQ_S3CUART_BASE2,
+                .parent_irq     = IRQ_UART2,
+        },
+        [3] = {
+                .regs           = (void *)S3C_VA_UART3,
+                .base_irq       = IRQ_S3CUART_BASE3,
+                .parent_irq     = IRQ_UART3,
+        },
+};
+
+static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
+{
+        struct uart_irq *uirq = get_irq_chip_data(irq);
+        return uirq->regs;
+}
+
+static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
+{
+        return irq & 3;
+}
+
+/* UART interrupt registers, not worth adding to seperate include header */
+#define S3C64XX_UINTP   0x30
+#define S3C64XX_UINTSP  0x34
+#define S3C64XX_UINTM   0x38
+
+static void s3c_irq_uart_mask(unsigned int irq)
+{
+        void __iomem *regs = s3c_irq_uart_base(irq);
+        unsigned int bit = s3c_irq_uart_bit(irq);
+        u32 reg;
+
+        reg = __raw_readl(regs + S3C64XX_UINTM);
+        reg |= (1 << bit);
+        __raw_writel(reg, regs + S3C64XX_UINTM);
+}
+
+static void s3c_irq_uart_maskack(unsigned int irq)
+{
+        void __iomem *regs = s3c_irq_uart_base(irq);
+        unsigned int bit = s3c_irq_uart_bit(irq);
+        u32 reg;
+
+        reg = __raw_readl(regs + S3C64XX_UINTM);
+        reg |= (1 << bit);
+        __raw_writel(reg, regs + S3C64XX_UINTM);
+        __raw_writel(1 << bit, regs + S3C64XX_UINTP);
+}
+
+static void s3c_irq_uart_unmask(unsigned int irq)
+{
+        void __iomem *regs = s3c_irq_uart_base(irq);
+        unsigned int bit = s3c_irq_uart_bit(irq);
+        u32 reg;
+
+        reg = __raw_readl(regs + S3C64XX_UINTM);
+        reg &= ~(1 << bit);
+        __raw_writel(reg, regs + S3C64XX_UINTM);
+}
+
+static void s3c_irq_uart_ack(unsigned int irq)
+{
+        void __iomem *regs = s3c_irq_uart_base(irq);
+        unsigned int bit = s3c_irq_uart_bit(irq);
+
+        __raw_writel(1 << bit, regs + S3C64XX_UINTP);
+}
+
+static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
+{
+        struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
+        u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
+        int base = uirq->base_irq;
+
+        if (pend & (1 << 0))
+                generic_handle_irq(base);
+        if (pend & (1 << 1))
+                generic_handle_irq(base + 1);
+        if (pend & (1 << 2))
+                generic_handle_irq(base + 2);
+        if (pend & (1 << 3))
+                generic_handle_irq(base + 3);
+}
+
+static struct irq_chip s3c_irq_uart = {
+        .name           = "s3c-uart",
+        .mask           = s3c_irq_uart_mask,
+        .unmask         = s3c_irq_uart_unmask,
+        .mask_ack       = s3c_irq_uart_maskack,
+        .ack            = s3c_irq_uart_ack,
+};
+
+static void __init s5pc1xx_uart_irq(struct uart_irq *uirq)
+{
+        void __iomem *reg_base = uirq->regs;
+        unsigned int irq;
+        int offs;
+
+        /* mask all interrupts at the start. */
+        __raw_writel(0xf, reg_base + S3C64XX_UINTM);
+
+        for (offs = 0; offs < 3; offs++) {
+                irq = uirq->base_irq + offs;
+
+                set_irq_chip(irq, &s3c_irq_uart);
+                set_irq_chip_data(irq, uirq);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+
+        set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
+}
+
+void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
+{
+        int i;
+        int uart, irq;
+
+        printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
+
+        /* initialise the pair of VICs */
+        for (i = 0; i < num; i++)
+                vic_init((void *)S5PC1XX_VA_VIC(i), S3C_IRQ(i * S3C_IRQ_OFFSET),
+                                vic_valid[i], 0);
+
+        /* add the timer sub-irqs */
+
+        set_irq_chained_handler(IRQ_TIMER0, s3c_irq_demux_timer0);
+        set_irq_chained_handler(IRQ_TIMER1, s3c_irq_demux_timer1);
+        set_irq_chained_handler(IRQ_TIMER2, s3c_irq_demux_timer2);
+        set_irq_chained_handler(IRQ_TIMER3, s3c_irq_demux_timer3);
+        set_irq_chained_handler(IRQ_TIMER4, s3c_irq_demux_timer4);
+
+        for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
+                set_irq_chip(irq, &s3c_irq_timer);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+
+        for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
+                s5pc1xx_uart_irq(&uart_irqs[uart]);
+}
+
+
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
new file mode 100644
index 000000000000..6b24035172fa
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
@@ -0,0 +1,1139 @@
+/* linux/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+ *
+ * Copyright 2009 Samsung Electronics, Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 based common clock support
+ *
+ * Based on plat-s3c64xx/s3c6400-clock.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/cpu-freq.h>
+
+#include <plat/regs-clock.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/devs.h>
+#include <plat/s5pc100.h>
+
+/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
+ * ext_xtal_mux for want of an actual name from the manual.
+*/
+
+static struct clk clk_ext_xtal_mux = {
+        .name           = "ext_xtal",
+        .id             = -1,
+};
+
+#define clk_fin_apll clk_ext_xtal_mux
+#define clk_fin_mpll clk_ext_xtal_mux
+#define clk_fin_epll clk_ext_xtal_mux
+#define clk_fin_hpll clk_ext_xtal_mux
+
+#define clk_fout_mpll   clk_mpll
+
+struct clk_sources {
+        unsigned int    nr_sources;
+        struct clk      **sources;
+};
+
+struct clksrc_clk {
+        struct clk              clk;
+        unsigned int            mask;
+        unsigned int            shift;
+
+        struct clk_sources      *sources;
+
+        unsigned int            divider_shift;
+        void __iomem            *reg_divider;
+        void __iomem            *reg_source;
+};
+
+static int clk_default_setrate(struct clk *clk, unsigned long rate)
+{
+        clk->rate = rate;
+        return 1;
+}
+
+struct clk clk_27m = {
+        .name           = "clk_27m",
+        .id             = -1,
+        .rate           = 27000000,
+};
+
+static int clk_48m_ctrl(struct clk *clk, int enable)
+{
+        unsigned long flags;
+        u32 val;
+
+        /* can't rely on clock lock, this register has other usages */
+        local_irq_save(flags);
+
+        val = __raw_readl(S5PC1XX_CLK_SRC1);
+        if (enable)
+                val |= S5PC100_CLKSRC1_CLK48M_MASK;
+        else
+                val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
+
+        __raw_writel(val, S5PC1XX_CLK_SRC1);
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+struct clk clk_48m = {
+        .name           = "clk_48m",
+        .id             = -1,
+        .rate           = 48000000,
+        .enable         = clk_48m_ctrl,
+};
+
+struct clk clk_54m = {
+        .name           = "clk_54m",
+        .id             = -1,
+        .rate           = 54000000,
+};
+
+struct clk clk_hpll = {
+        .name           = "hpll",
+        .id             = -1,
+};
+
+struct clk clk_hd0 = {
+        .name           = "hclkd0",
+        .id             = -1,
+        .rate           = 0,
+        .parent         = NULL,
+        .ctrlbit        = 0,
+        .set_rate       = clk_default_setrate,
+};
+
+struct clk clk_pd0 = {
+        .name           = "pclkd0",
+        .id             = -1,
+        .rate           = 0,
+        .parent         = NULL,
+        .ctrlbit        = 0,
+        .set_rate       = clk_default_setrate,
+};
+
+static int s5pc1xx_clk_gate(void __iomem *reg,
+                                struct clk *clk,
+                                int enable)
+{
+        unsigned int ctrlbit = clk->ctrlbit;
+        u32 con;
+
+        con = __raw_readl(reg);
+
+        if (enable)
+                con |= ctrlbit;
+        else
+                con &= ~ctrlbit;
+
+        __raw_writel(con, reg);
+        return 0;
+}
+
+static int s5pc1xx_clk_d00_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
+}
+
+static int s5pc1xx_clk_d01_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
+}
+
+static int s5pc1xx_clk_d02_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
+}
+
+static int s5pc1xx_clk_d10_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
+}
+
+static int s5pc1xx_clk_d11_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
+}
+
+static int s5pc1xx_clk_d12_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
+}
+
+static int s5pc1xx_clk_d13_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
+}
+
+static int s5pc1xx_clk_d14_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
+}
+
+static int s5pc1xx_clk_d15_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
+}
+
+static int s5pc1xx_clk_d20_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
+}
+
+int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
+}
+
+int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
+}
+
+static struct clk init_clocks_disable[] = {
+        {
+                .name           = "dsi",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_DSI,
+        }, {
+                .name           = "csi",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_CSI,
+        }, {
+                .name           = "ccan0",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_CCAN0,
+        }, {
+                .name           = "ccan1",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_CCAN1,
+        }, {
+                .name           = "keypad",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_KEYIF,
+        }, {
+                .name           = "hclkd2",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc1xx_clk_d20_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D20_HCLKD2,
+        }, {
+                .name           = "iis-d2",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc1xx_clk_d20_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D20_I2SD2,
+        }, {
+                .name           = "otg",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_USBOTG,
+        },
+};
+
+static struct clk init_clocks[] = {
+        /* System1 (D0_0) devices */
+        {
+                .name           = "intc",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_INTC,
+        }, {
+                .name           = "tzic",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_TZIC,
+        }, {
+                .name           = "cf-ata",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_CFCON,
+        }, {
+                .name           = "mdma",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_MDMA,
+        }, {
+                .name           = "g2d",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_G2D,
+        }, {
+                .name           = "secss",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_SECSS,
+        }, {
+                .name           = "cssys",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_CSSYS,
+        },
+
+        /* Memory (D0_1) devices */
+        {
+                .name           = "dmc",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_DMC,
+        }, {
+                .name           = "sromc",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_SROMC,
+        }, {
+                .name           = "onenand",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_ONENAND,
+        }, {
+                .name           = "nand",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_NFCON,
+        }, {
+                .name           = "intmem",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_INTMEM,
+        }, {
+                .name           = "ebi",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_EBI,
+        },
+
+        /* System2 (D0_2) devices */
+        {
+                .name           = "seckey",
+                .id             = -1,
+                .parent         = &clk_pd0,
+                .enable         = s5pc1xx_clk_d02_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D02_SECKEY,
+        }, {
+                .name           = "sdm",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d02_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D02_SDM,
+        },
+
+        /* File (D1_0) devices */
+        {
+                .name           = "pdma0",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_PDMA0,
+        }, {
+                .name           = "pdma1",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_PDMA1,
+        }, {
+                .name           = "usb-host",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_USBHOST,
+        }, {
+                .name           = "modem",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_MODEMIF,
+        }, {
+                .name           = "hsmmc",
+                .id             = 0,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC0,
+        }, {
+                .name           = "hsmmc",
+                .id             = 1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC1,
+        }, {
+                .name           = "hsmmc",
+                .id             = 2,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC2,
+        },
+
+        /* Multimedia1 (D1_1) devices */
+        {
+                .name           = "lcd",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_LCD,
+        }, {
+                .name           = "rotator",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_ROTATOR,
+        }, {
+                .name           = "fimc",
+                .id             = 0,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC0,
+        }, {
+                .name           = "fimc",
+                .id             = 1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC1,
+        }, {
+                .name           = "fimc",
+                .id             = 2,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC2,
+        }, {
+                .name           = "jpeg",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_JPEG,
+        }, {
+                .name           = "g3d",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_G3D,
+        },
+
+        /* Multimedia2 (D1_2) devices */
+        {
+                .name           = "tv",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_TV,
+        }, {
+                .name           = "vp",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_VP,
+        }, {
+                .name           = "mixer",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_MIXER,
+        }, {
+                .name           = "hdmi",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_HDMI,
+        }, {
+                .name           = "mfc",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_MFC,
+        },
+
+        /* System (D1_3) devices */
+        {
+                .name           = "chipid",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_CHIPID,
+        }, {
+                .name           = "gpio",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_GPIO,
+        }, {
+                .name           = "apc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_APC,
+        }, {
+                .name           = "iec",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_IEC,
+        }, {
+                .name           = "timers",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_PWM,
+        }, {
+                .name           = "systimer",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_SYSTIMER,
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_WDT,
+        }, {
+                .name           = "rtc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_RTC,
+        },
+
+        /* Connectivity (D1_4) devices */
+        {
+                .name           = "uart",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART0,
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART1,
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART2,
+        }, {
+                .name           = "uart",
+                .id             = 3,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART3,
+        }, {
+                .name           = "i2c",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_IIC,
+        }, {
+                .name           = "hdmi-i2c",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_HDMI_IIC,
+        }, {
+                .name           = "spi",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_SPI0,
+        }, {
+                .name           = "spi",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_SPI1,
+        }, {
+                .name           = "spi",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_SPI2,
+        }, {
+                .name           = "irda",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_IRDA,
+        }, {
+                .name           = "hsitx",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_HSITX,
+        }, {
+                .name           = "hsirx",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_HSIRX,
+        },
+
+        /* Audio (D1_5) devices */
+        {
+                .name           = "iis",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_IIS0,
+        }, {
+                .name           = "iis",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_IIS1,
+        }, {
+                .name           = "iis",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_IIS2,
+        }, {
+                .name           = "ac97",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_AC97,
+        }, {
+                .name           = "pcm",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_PCM0,
+        }, {
+                .name           = "pcm",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_PCM1,
+        }, {
+                .name           = "spdif",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_SPDIF,
+        }, {
+                .name           = "adc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_TSADC,
+        }, {
+                .name           = "keyif",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_KEYIF,
+        }, {
+                .name           = "cg",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_CG,
+        },
+
+        /* Audio (D2_0) devices: all disabled */
+
+        /* Special Clocks 1 */
+        {
+                .name           = "sclk_hpm",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC1XX_CLKGATE_SCLK0_HPM,
+        }, {
+                .name           = "sclk_onenand",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_ONENAND,
+        }, {
+                .name           = "sclk_spi_48",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI0_48,
+        }, {
+                .name           = "sclk_spi_48",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI1_48,
+        }, {
+                .name           = "sclk_spi_48",
+                .id             = 2,
+                .parent         = &clk_48m,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI2_48,
+        }, {
+                .name           = "sclk_mmc_48",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC0_48,
+        }, {
+                .name           = "sclk_mmc_48",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC1_48,
+        }, {
+                .name           = "sclk_mmc_48",
+                .id             = 2,
+                .parent         = &clk_48m,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC2_48,
+        },
+
+        /* Special Clocks 2 */
+        {
+                .name           = "sclk_tv_54",
+                .id             = -1,
+                .parent         = &clk_54m,
+                .enable         = s5pc1xx_sclk1_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_TV54,
+        }, {
+                .name           = "sclk_vdac_54",
+                .id             = -1,
+                .parent         = &clk_54m,
+                .enable         = s5pc1xx_sclk1_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_VDAC54,
+        }, {
+                .name           = "sclk_spdif",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc1xx_sclk1_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_SPDIF,
+        },
+};
+
+void __init s5pc1xx_register_clocks(void)
+{
+        struct clk *clkp;
+        int ret;
+        int ptr;
+
+        clkp = init_clocks;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+        }
+
+        clkp = init_clocks_disable;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+
+                (clkp->enable)(clkp, 0);
+        }
+
+        s3c_pwmclk_init();
+}
+static struct clk clk_fout_apll = {
+        .name           = "fout_apll",
+        .id             = -1,
+};
+
+static struct clk *clk_src_apll_list[] = {
+        [0] = &clk_fin_apll,
+        [1] = &clk_fout_apll,
+};
+
+static struct clk_sources clk_src_apll = {
+        .sources        = clk_src_apll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
+};
+
+static struct clksrc_clk clk_mout_apll = {
+        .clk    = {
+                .name           = "mout_apll",
+                .id             = -1,
+        },
+        .shift          = S5PC1XX_CLKSRC0_APLL_SHIFT,
+        .mask           = S5PC1XX_CLKSRC0_APLL_MASK,
+        .sources        = &clk_src_apll,
+        .reg_source     = S5PC1XX_CLK_SRC0,
+};
+
+static struct clk clk_fout_epll = {
+        .name           = "fout_epll",
+        .id             = -1,
+};
+
+static struct clk *clk_src_epll_list[] = {
+        [0] = &clk_fin_epll,
+        [1] = &clk_fout_epll,
+};
+
+static struct clk_sources clk_src_epll = {
+        .sources        = clk_src_epll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
+};
+
+static struct clksrc_clk clk_mout_epll = {
+        .clk    = {
+                .name           = "mout_epll",
+                .id             = -1,
+        },
+        .shift          = S5PC1XX_CLKSRC0_EPLL_SHIFT,
+        .mask           = S5PC1XX_CLKSRC0_EPLL_MASK,
+        .sources        = &clk_src_epll,
+        .reg_source     = S5PC1XX_CLK_SRC0,
+};
+
+static struct clk *clk_src_mpll_list[] = {
+        [0] = &clk_fin_mpll,
+        [1] = &clk_fout_mpll,
+};
+
+static struct clk_sources clk_src_mpll = {
+        .sources        = clk_src_mpll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
+};
+
+static struct clksrc_clk clk_mout_mpll = {
+        .clk = {
+                .name           = "mout_mpll",
+                .id             = -1,
+        },
+        .shift          = S5PC1XX_CLKSRC0_MPLL_SHIFT,
+        .mask           = S5PC1XX_CLKSRC0_MPLL_MASK,
+        .sources        = &clk_src_mpll,
+        .reg_source     = S5PC1XX_CLK_SRC0,
+};
+
+static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned long clkdiv;
+
+        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
+
+        clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL_MASK;
+        rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL_SHIFT) + 1;
+
+        return rate;
+}
+
+static struct clk clk_dout_mpll = {
+        .name           = "dout_mpll",
+        .id             = -1,
+        .parent         = &clk_mout_mpll.clk,
+        .get_rate       = s5pc1xx_clk_doutmpll_get_rate,
+};
+
+static unsigned long s5pc1xx_clk_doutmpll2_get_rate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned long clkdiv;
+
+        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
+
+        clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
+        rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL2_SHIFT) + 1;
+
+        return rate;
+}
+
+struct clk clk_dout_mpll2 = {
+        .name           = "dout_mpll2",
+        .id             = -1,
+        .parent         = &clk_mout_mpll.clk,
+        .get_rate       = s5pc1xx_clk_doutmpll2_get_rate,
+};
+
+static struct clk *clkset_uart_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+        NULL,
+        NULL
+};
+
+static struct clk_sources clkset_uart = {
+        .sources        = clkset_uart_list,
+        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
+};
+
+static inline struct clksrc_clk *to_clksrc(struct clk *clk)
+{
+        return container_of(clk, struct clksrc_clk, clk);
+}
+
+static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk)
+{
+        struct clksrc_clk *sclk = to_clksrc(clk);
+        unsigned long rate = clk_get_rate(clk->parent);
+        u32 clkdiv = __raw_readl(sclk->reg_divider);
+
+        clkdiv >>= sclk->divider_shift;
+        clkdiv &= 0xf;
+        clkdiv++;
+
+        rate /= clkdiv;
+        return rate;
+}
+
+static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate)
+{
+        struct clksrc_clk *sclk = to_clksrc(clk);
+        void __iomem *reg = sclk->reg_divider;
+        unsigned int div;
+        u32 val;
+
+        rate = clk_round_rate(clk, rate);
+        div = clk_get_rate(clk->parent) / rate;
+        if (div > 16)
+                return -EINVAL;
+
+        val = __raw_readl(reg);
+        val &= ~(0xf << sclk->shift);
+        val |= (div - 1) << sclk->shift;
+        __raw_writel(val, reg);
+
+        return 0;
+}
+
+static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent)
+{
+        struct clksrc_clk *sclk = to_clksrc(clk);
+        struct clk_sources *srcs = sclk->sources;
+        u32 clksrc = __raw_readl(sclk->reg_source);
+        int src_nr = -1;
+        int ptr;
+
+        for (ptr = 0; ptr < srcs->nr_sources; ptr++)
+                if (srcs->sources[ptr] == parent) {
+                        src_nr = ptr;
+                        break;
+                }
+
+        if (src_nr >= 0) {
+                clksrc &= ~sclk->mask;
+                clksrc |= src_nr << sclk->shift;
+
+                __raw_writel(clksrc, sclk->reg_source);
+                return 0;
+        }
+
+        return -EINVAL;
+}
+
+static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk,
+                                              unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        int div;
+
+        if (rate > parent_rate)
+                rate = parent_rate;
+        else {
+                div = rate / parent_rate;
+
+                if (div == 0)
+                        div = 1;
+                if (div > 16)
+                        div = 16;
+
+                rate = parent_rate / div;
+        }
+
+        return rate;
+}
+
+static struct clksrc_clk clk_uart_uclk1 = {
+        .clk    = {
+                .name           = "uclk1",
+                .id             = -1,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_UART,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .set_parent     = s5pc1xx_setparent_clksrc,
+                .get_rate       = s5pc1xx_getrate_clksrc,
+                .set_rate       = s5pc1xx_setrate_clksrc,
+                .round_rate     = s5pc1xx_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC1_UART_SHIFT,
+        .mask           = S5PC100_CLKSRC1_UART_MASK,
+        .sources        = &clkset_uart,
+        .divider_shift  = S5PC100_CLKDIV2_UART_SHIFT,
+        .reg_divider    = S5PC1XX_CLK_DIV2,
+        .reg_source     = S5PC1XX_CLK_SRC1,
+};
+
+/* Clock initialisation code */
+
+static struct clksrc_clk *init_parents[] = {
+        &clk_mout_apll,
+        &clk_mout_epll,
+        &clk_mout_mpll,
+        &clk_uart_uclk1,
+};
+
+static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk)
+{
+        struct clk_sources *srcs = clk->sources;
+        u32 clksrc = __raw_readl(clk->reg_source);
+
+        clksrc &= clk->mask;
+        clksrc >>= clk->shift;
+
+        if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
+                printk(KERN_ERR "%s: bad source %d\n",
+                       clk->clk.name, clksrc);
+                return;
+        }
+
+        clk->clk.parent = srcs->sources[clksrc];
+
+        printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
+               clk->clk.name, clk->clk.parent->name, clksrc,
+               clk_get_rate(&clk->clk));
+}
+
+#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
+
+void __init_or_cpufreq s5pc100_setup_clocks(void)
+{
+        struct clk *xtal_clk;
+        unsigned long xtal;
+        unsigned long armclk;
+        unsigned long hclkd0;
+        unsigned long hclk;
+        unsigned long pclkd0;
+        unsigned long pclk;
+        unsigned long apll;
+        unsigned long mpll;
+        unsigned long hpll;
+        unsigned long epll;
+        unsigned int ptr;
+        u32 clkdiv0, clkdiv1;
+
+        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+        clkdiv0 = __raw_readl(S5PC1XX_CLK_DIV0);
+        clkdiv1 = __raw_readl(S5PC1XX_CLK_DIV1);
+
+        printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
+                        __func__, clkdiv0, clkdiv1);
+
+        xtal_clk = clk_get(NULL, "xtal");
+        BUG_ON(IS_ERR(xtal_clk));
+
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+        apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_APLL_CON));
+        mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_MPLL_CON));
+        epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_EPLL_CON));
+        hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
+
+        printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n",
+               apll, mpll, epll, hpll);
+
+        armclk = apll / GET_DIV(clkdiv0, S5PC1XX_CLKDIV0_APLL);
+        armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM);
+        hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0);
+        pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0);
+        hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1);
+        pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1);
+
+        printk(KERN_INFO "S5PC100: ARMCLK=%ld, HCLKD0=%ld, PCLKD0=%ld, HCLK=%ld, PCLK=%ld\n",
+               armclk, hclkd0, pclkd0, hclk, pclk);
+
+        clk_fout_apll.rate = apll;
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+        clk_fout_apll.rate = apll;
+
+        clk_h.rate = hclk;
+        clk_p.rate = pclk;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
+                s5pc1xx_set_clksrc(init_parents[ptr]);
+}
+
+static struct clk *clks[] __initdata = {
+        &clk_ext_xtal_mux,
+        &clk_mout_epll.clk,
+        &clk_fout_epll,
+        &clk_mout_mpll.clk,
+        &clk_dout_mpll,
+        &clk_uart_uclk1.clk,
+        &clk_ext,
+        &clk_epll,
+        &clk_27m,
+        &clk_48m,
+        &clk_54m,
+};
+
+void __init s5pc100_register_clocks(void)
+{
+        struct clk *clkp;
+        int ret;
+        int ptr;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
+                clkp = clks[ptr];
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+        }
+
+        clk_mpll.parent = &clk_mout_mpll.clk;
+        clk_epll.parent = &clk_mout_epll.clk;
+}
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-init.c b/arch/arm/plat-s5pc1xx/s5pc100-init.c
new file mode 100644
index 000000000000..c58710884ceb
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/s5pc100-init.c
@@ -0,0 +1,27 @@
+/* linux/arch/arm/plat-s5pc1xx/s5pc100-init.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - CPU initialisation (common with other S5PC1XX chips)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/s5pc100.h>
+
+/* uart registration process */
+
+void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        /* The driver name is s3c6400-uart to reuse s3c6400_serial_drv  */
+        s3c24xx_init_uartdevs("s3c6400-uart", s5pc1xx_uart_resources, cfg, no);
+}
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c0.c b/arch/arm/plat-s5pc1xx/setup-i2c0.c
new file mode 100644
index 000000000000..3d00c025fffb
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/setup-i2c0.c
@@ -0,0 +1,25 @@
+/* linux/arch/arm/plat-s5pc1xx/setup-i2c0.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Base S5PC1XX I2C bus 0 gpio configuration
+ *
+ * Based on plat-s3c64xx/setup-i2c0.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <plat/iic.h>
+
+void s3c_i2c0_cfg_gpio(struct platform_device *dev)
+{
+        /* Pin configuration would be needed */
+}
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c1.c b/arch/arm/plat-s5pc1xx/setup-i2c1.c
new file mode 100644
index 000000000000..c8f3ca42f51d
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/setup-i2c1.c
@@ -0,0 +1,25 @@
+/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Base S5PC1XX I2C bus 1 gpio configuration
+ *
+ * Based on plat-s3c64xx/setup-i2c1.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <plat/iic.h>
+
+void s3c_i2c1_cfg_gpio(struct platform_device *dev)
+{
+        /* Pin configuration would be needed */
+}
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 33026eff2aa4..c8c55b469342 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Sat Jun 20 22:28:39 2009
+# Last update: Sat Sep 12 12:00:16 2009
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -1769,7 +1769,7 @@ mx31cicada		MACH_MX31CICADA		MX31CICADA		1777
 mi424wr                 MACH_MI424WR            MI424WR                 1778
 axs_ultrax              MACH_AXS_ULTRAX         AXS_ULTRAX              1779
 at572d940deb            MACH_AT572D940DEB       AT572D940DEB            1780
-davinci_da8xx_evm       MACH_DAVINCI_DA8XX_EVM  DAVINCI_DA8XX_EVM       1781
+davinci_da830_evm       MACH_DAVINCI_DA830_EVM  DAVINCI_DA830_EVM       1781
 ep9302                  MACH_EP9302             EP9302                  1782
 at572d940hfek           MACH_AT572D940HFEB      AT572D940HFEB           1783
 cybook3                 MACH_CYBOOK3            CYBOOK3                 1784
@@ -1962,7 +1962,7 @@ ethernut5		MACH_ETHERNUT5		ETHERNUT5		1971
 arm11                   MACH_ARM11              ARM11                   1972
 cpuat9260               MACH_CPUAT9260          CPUAT9260               1973
 cpupxa255               MACH_CPUPXA255          CPUPXA255               1974
-cpuimx27                MACH_CPUIMX27           CPUIMX27                1975
+eukrea_cpuimx27         MACH_CPUIMX27           CPUIMX27                1975
 cheflux                 MACH_CHEFLUX            CHEFLUX                 1976
 eb_cpux9k2              MACH_EB_CPUX9K2         EB_CPUX9K2              1977
 opcotec                 MACH_OPCOTEC            OPCOTEC                 1978
@@ -2249,14 +2249,14 @@ omap3_phrazer		MACH_OMAP3_PHRAZER	OMAP3_PHRAZER		2261
 darwin                  MACH_DARWIN             DARWIN                  2262
 oratiscomu              MACH_ORATISCOMU         ORATISCOMU              2263
 rtsbc20                 MACH_RTSBC20            RTSBC20                 2264
-i780                    MACH_I780               I780                    2265
+sgh_i780                MACH_I780               I780                    2265
 gemini324               MACH_GEMINI324          GEMINI324               2266
 oratislan               MACH_ORATISLAN          ORATISLAN               2267
 oratisalog              MACH_ORATISALOG         ORATISALOG              2268
 oratismadi              MACH_ORATISMADI         ORATISMADI              2269
 oratisot16              MACH_ORATISOT16         ORATISOT16              2270
 oratisdesk              MACH_ORATISDESK         ORATISDESK              2271
-v2p_ca9                 MACH_V2P_CA9            V2P_CA9                 2272
+v2_ca9                  MACH_V2P_CA9            V2P_CA9                 2272
 sintexo                 MACH_SINTEXO            SINTEXO                 2273
 cm3389                  MACH_CM3389             CM3389                  2274
 omap3_cio               MACH_OMAP3_CIO          OMAP3_CIO               2275
@@ -2280,3 +2280,132 @@ htcrhodium		MACH_HTCRHODIUM		HTCRHODIUM		2292
 htctopaz                MACH_HTCTOPAZ           HTCTOPAZ                2293
 matrix504               MACH_MATRIX504          MATRIX504               2294
 mrfsa                   MACH_MRFSA              MRFSA                   2295
+sc_p270                 MACH_SC_P270            SC_P270                 2296
+atlas5_evb              MACH_ATLAS5_EVB         ATLAS5_EVB              2297
+pelco_lobox             MACH_PELCO_LOBOX        PELCO_LOBOX             2298
+dilax_pcu200            MACH_DILAX_PCU200       DILAX_PCU200            2299
+leonardo                MACH_LEONARDO           LEONARDO                2300
+zoran_approach7         MACH_ZORAN_APPROACH7    ZORAN_APPROACH7         2301
+dp6xx                   MACH_DP6XX              DP6XX                   2302
+bcm2153_vesper          MACH_BCM2153_VESPER     BCM2153_VESPER          2303
+mahimahi                MACH_MAHIMAHI           MAHIMAHI                2304
+clickc                  MACH_CLICKC             CLICKC                  2305
+zb_gateway              MACH_ZB_GATEWAY         ZB_GATEWAY              2306
+tazcard                 MACH_TAZCARD            TAZCARD                 2307
+tazdev                  MACH_TAZDEV             TAZDEV                  2308
+annax_cb_arm            MACH_ANNAX_CB_ARM       ANNAX_CB_ARM            2309
+annax_dm3               MACH_ANNAX_DM3          ANNAX_DM3               2310
+cerebric                MACH_CEREBRIC           CEREBRIC                2311
+orca                    MACH_ORCA               ORCA                    2312
+pc9260                  MACH_PC9260             PC9260                  2313
+ems285a                 MACH_EMS285A            EMS285A                 2314
+gec2410                 MACH_GEC2410            GEC2410                 2315
+gec2440                 MACH_GEC2440            GEC2440                 2316
+mw903                   MACH_ARCH_MW903         ARCH_MW903              2317
+mw2440                  MACH_MW2440             MW2440                  2318
+ecac2378                MACH_ECAC2378           ECAC2378                2319
+tazkiosk                MACH_TAZKIOSK           TAZKIOSK                2320
+whiterabbit_mch         MACH_WHITERABBIT_MCH    WHITERABBIT_MCH         2321
+sbox9263                MACH_SBOX9263           SBOX9263                2322
+oreo                    MACH_OREO               OREO                    2323
+smdk6442                MACH_SMDK6442           SMDK6442                2324
+openrd_base             MACH_OPENRD_BASE        OPENRD_BASE             2325
+incredible              MACH_INCREDIBLE         INCREDIBLE              2326
+incrediblec             MACH_INCREDIBLEC        INCREDIBLEC             2327
+heroct                  MACH_HEROCT             HEROCT                  2328
+mmnet1000               MACH_MMNET1000          MMNET1000               2329
+devkit8000              MACH_DEVKIT8000         DEVKIT8000              2330
+devkit9000              MACH_DEVKIT9000         DEVKIT9000              2331
+mx31txtr                MACH_MX31TXTR           MX31TXTR                2332
+u380                    MACH_U380               U380                    2333
+oamp3_hualu             MACH_HUALU_BOARD        HUALU_BOARD             2334
+npcmx50                 MACH_NPCMX50            NPCMX50                 2335
+mx51_lange51            MACH_MX51_LANGE51       MX51_LANGE51            2336
+mx51_lange52            MACH_MX51_LANGE52       MX51_LANGE52            2337
+riom                    MACH_RIOM               RIOM                    2338
+comcas                  MACH_COMCAS             COMCAS                  2339
+wsi_mx27                MACH_WSI_MX27           WSI_MX27                2340
+cm_t35                  MACH_CM_T35             CM_T35                  2341
+net2big                 MACH_NET2BIG            NET2BIG                 2342
+motorola_a1600          MACH_MOTOROLA_A1600     MOTOROLA_A1600          2343
+igep0020                MACH_IGEP0020           IGEP0020                2344
+igep0010                MACH_IGEP0010           IGEP0010                2345
+mv6281gtwge2            MACH_MV6281GTWGE2       MV6281GTWGE2            2346
+scat100                 MACH_SCAT100            SCAT100                 2347
+sanmina                 MACH_SANMINA            SANMINA                 2348
+momento                 MACH_MOMENTO            MOMENTO                 2349
+nuc9xx                  MACH_NUC9XX             NUC9XX                  2350
+nuc910evb               MACH_NUC910EVB          NUC910EVB               2351
+nuc920evb               MACH_NUC920EVB          NUC920EVB               2352
+nuc950evb               MACH_NUC950EVB          NUC950EVB               2353
+nuc945evb               MACH_NUC945EVB          NUC945EVB               2354
+nuc960evb               MACH_NUC960EVB          NUC960EVB               2355
+nuc932evb               MACH_NUC932EVB          NUC932EVB               2356
+nuc900                  MACH_NUC900             NUC900                  2357
+sd1soc                  MACH_SD1SOC             SD1SOC                  2358
+ln2440bc                MACH_LN2440BC           LN2440BC                2359
+rsbc                    MACH_RSBC               RSBC                    2360
+openrd_client           MACH_OPENRD_CLIENT      OPENRD_CLIENT           2361
+hpipaq11x               MACH_HPIPAQ11X          HPIPAQ11X               2362
+wayland                 MACH_WAYLAND            WAYLAND                 2363
+acnbsx102               MACH_ACNBSX102          ACNBSX102               2364
+hwat91                  MACH_HWAT91             HWAT91                  2365
+at91sam9263cs           MACH_AT91SAM9263CS      AT91SAM9263CS           2366
+csb732                  MACH_CSB732             CSB732                  2367
+u8500                   MACH_U8500              U8500                   2368
+huqiu                   MACH_HUQIU              HUQIU                   2369
+mx51_kunlun             MACH_MX51_KUNLUN        MX51_KUNLUN             2370
+pmt1g                   MACH_PMT1G              PMT1G                   2371
+htcelf                  MACH_HTCELF             HTCELF                  2372
+armadillo420            MACH_ARMADILLO420       ARMADILLO420            2373
+armadillo440            MACH_ARMADILLO440       ARMADILLO440            2374
+u_chip_dual_arm         MACH_U_CHIP_DUAL_ARM    U_CHIP_DUAL_ARM         2375
+csr_bdb3                MACH_CSR_BDB3           CSR_BDB3                2376
+dolby_cat1018           MACH_DOLBY_CAT1018      DOLBY_CAT1018           2377
+hy9307                  MACH_HY9307             HY9307                  2378
+aspire_easystore        MACH_A_ES               A_ES                    2379
+davinci_irif            MACH_DAVINCI_IRIF       DAVINCI_IRIF            2380
+agama9263               MACH_AGAMA9263          AGAMA9263               2381
+marvell_jasper          MACH_MARVELL_JASPER     MARVELL_JASPER          2382
+flint                   MACH_FLINT              FLINT                   2383
+tavorevb3               MACH_TAVOREVB3          TAVOREVB3               2384
+sch_m490                MACH_SCH_M490           SCH_M490                2386
+rbl01                   MACH_RBL01              RBL01                   2387
+omnifi                  MACH_OMNIFI             OMNIFI                  2388
+otavalo                 MACH_OTAVALO            OTAVALO                 2389
+sienna                  MACH_SIENNA             SIENNA                  2390
+htc_excalibur_s620      MACH_HTC_EXCALIBUR_S620 HTC_EXCALIBUR_S620      2391
+htc_opal                MACH_HTC_OPAL           HTC_OPAL                2392
+touchbook               MACH_TOUCHBOOK          TOUCHBOOK               2393
+latte                   MACH_LATTE              LATTE                   2394
+xa200                   MACH_XA200              XA200                   2395
+nimrod                  MACH_NIMROD             NIMROD                  2396
+cc9p9215_3g             MACH_CC9P9215_3G        CC9P9215_3G             2397
+cc9p9215_3gjs           MACH_CC9P9215_3GJS      CC9P9215_3GJS           2398
+tk71                    MACH_TK71               TK71                    2399
+comham3525              MACH_COMHAM3525         COMHAM3525              2400
+mx31erebus              MACH_MX31EREBUS         MX31EREBUS              2401
+mcardmx27               MACH_MCARDMX27          MCARDMX27               2402
+paradise                MACH_PARADISE           PARADISE                2403
+tide                    MACH_TIDE               TIDE                    2404
+wzl2440                 MACH_WZL2440            WZL2440                 2405
+sdrdemo                 MACH_SDRDEMO            SDRDEMO                 2406
+ethercan2               MACH_ETHERCAN2          ETHERCAN2               2407
+ecmimg20                MACH_ECMIMG20           ECMIMG20                2408
+omap_dragon             MACH_OMAP_DRAGON        OMAP_DRAGON             2409
+halo                    MACH_HALO               HALO                    2410
+huangshan               MACH_HUANGSHAN          HUANGSHAN               2411
+vl_ma2sc                MACH_VL_MA2SC           VL_MA2SC                2412
+raumfeld_rc             MACH_RAUMFELD_RC        RAUMFELD_RC             2413
+raumfeld_connector      MACH_RAUMFELD_CONNECTOR RAUMFELD_CONNECTOR      2414
+raumfeld_speaker        MACH_RAUMFELD_SPEAKER   RAUMFELD_SPEAKER        2415
+multibus_master         MACH_MULTIBUS_MASTER    MULTIBUS_MASTER         2416
+multibus_pbk            MACH_MULTIBUS_PBK       MULTIBUS_PBK            2417
+tnetv107x               MACH_TNETV107X          TNETV107X               2418
+snake                   MACH_SNAKE              SNAKE                   2419
+cwmx27                  MACH_CWMX27             CWMX27                  2420
+sch_m480                MACH_SCH_M480           SCH_M480                2421
+platypus                MACH_PLATYPUS           PLATYPUS                2422
+pss2                    MACH_PSS2               PSS2                    2423
+davinci_apm150          MACH_DAVINCI_APM150     DAVINCI_APM150          2424
+str9100                 MACH_STR9100            STR9100                 2425
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
index a2bed62aec21..4fa9903b83cf 100644
--- a/arch/arm/vfp/entry.S
+++ b/arch/arm/vfp/entry.S
@@ -42,6 +42,7 @@ ENTRY(vfp_null_entry)
         mov     pc, lr
 ENDPROC(vfp_null_entry)
 
+        .align  2
 .LCvfp:
         .word   vfp_vector
 
@@ -61,6 +62,7 @@ ENTRY(vfp_testing_entry)
         mov     pc, r9                  @ we have handled the fault
 ENDPROC(vfp_testing_entry)
 
+        .align  2
 VFP_arch_address:
         .word   VFP_arch
 
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index 1aeae38725dd..66dc2d03b7fc 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -209,40 +209,55 @@ ENDPROC(vfp_save_state)
 last_VFP_context_address:
         .word   last_VFP_context
 
-ENTRY(vfp_get_float)
-        add     pc, pc, r0, lsl #3
+        .macro  tbl_branch, base, tmp, shift
+#ifdef CONFIG_THUMB2_KERNEL
+        adr     \tmp, 1f
+        add     \tmp, \tmp, \base, lsl \shift
+        mov     pc, \tmp
+#else
+        add     pc, pc, \base, lsl \shift
         mov     r0, r0
+#endif
+1:
+        .endm
+
+ENTRY(vfp_get_float)
+        tbl_branch r0, r3, #3
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        mrc     p10, 0, r0, c\dr, c0, 0 @ fmrs  r0, s0
+1:      mrc     p10, 0, r0, c\dr, c0, 0 @ fmrs  r0, s0
         mov     pc, lr
-        mrc     p10, 0, r0, c\dr, c0, 4 @ fmrs  r0, s1
+        .org    1b + 8
+1:      mrc     p10, 0, r0, c\dr, c0, 4 @ fmrs  r0, s1
         mov     pc, lr
+        .org    1b + 8
         .endr
 ENDPROC(vfp_get_float)
 
 ENTRY(vfp_put_float)
-        add     pc, pc, r1, lsl #3
-        mov     r0, r0
+        tbl_branch r1, r3, #3
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        mcr     p10, 0, r0, c\dr, c0, 0 @ fmsr  r0, s0
+1:      mcr     p10, 0, r0, c\dr, c0, 0 @ fmsr  r0, s0
         mov     pc, lr
-        mcr     p10, 0, r0, c\dr, c0, 4 @ fmsr  r0, s1
+        .org    1b + 8
+1:      mcr     p10, 0, r0, c\dr, c0, 4 @ fmsr  r0, s1
         mov     pc, lr
+        .org    1b + 8
         .endr
 ENDPROC(vfp_put_float)
 
 ENTRY(vfp_get_double)
-        add     pc, pc, r0, lsl #3
-        mov     r0, r0
+        tbl_branch r0, r3, #3
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        fmrrd   r0, r1, d\dr
+1:      fmrrd   r0, r1, d\dr
         mov     pc, lr
+        .org    1b + 8
         .endr
 #ifdef CONFIG_VFPv3
         @ d16 - d31 registers
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        mrrc    p11, 3, r0, r1, c\dr    @ fmrrd r0, r1, d\dr
+1:      mrrc    p11, 3, r0, r1, c\dr    @ fmrrd r0, r1, d\dr
         mov     pc, lr
+        .org    1b + 8
         .endr
 #endif
 
@@ -253,17 +268,18 @@ ENTRY(vfp_get_double)
 ENDPROC(vfp_get_double)
 
 ENTRY(vfp_put_double)
-        add     pc, pc, r2, lsl #3
-        mov     r0, r0
+        tbl_branch r2, r3, #3
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        fmdrr   d\dr, r0, r1
+1:      fmdrr   d\dr, r0, r1
         mov     pc, lr
+        .org    1b + 8
         .endr
 #ifdef CONFIG_VFPv3
         @ d16 - d31 registers
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        mcrr    p11, 3, r1, r2, c\dr    @ fmdrr r1, r2, d\dr
+1:      mcrr    p11, 3, r1, r2, c\dr    @ fmdrr r1, r2, d\dr
         mov     pc, lr
+        .org    1b + 8
         .endr
 #endif
 ENDPROC(vfp_put_double)