diff options
author | Eric Miao <eric.y.miao@gmail.com> | 2007-06-06 01:36:04 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-07-12 09:28:11 -0400 |
commit | 53665a50fdac6fe11e0dde4e2b95700ed5184dc4 (patch) | |
tree | 4eac4540a1f404f38fa6f1f83874ac8c2e77d7e5 /arch/arm | |
parent | c08b7b3ef6bf489ddabadc03e050f3db2ea44b5d (diff) |
[ARM] 4436/1: PXA: move low IRQ initialization code to pxa_init_irq_low()
1. move low IRQ initialization code to pxa_init_irq_low()
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-pxa/irq.c | 36 |
1 files changed, 21 insertions, 15 deletions
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 844d3de3ef44..42b2da2f213e 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
@@ -67,6 +67,26 @@ static struct irq_chip pxa_internal_chip_low = { | |||
67 | .set_wake = pxa_set_wake, | 67 | .set_wake = pxa_set_wake, |
68 | }; | 68 | }; |
69 | 69 | ||
70 | void __init pxa_init_irq_low(void) | ||
71 | { | ||
72 | int irq; | ||
73 | |||
74 | /* disable all IRQs */ | ||
75 | ICMR = 0; | ||
76 | |||
77 | /* all IRQs are IRQ, not FIQ */ | ||
78 | ICLR = 0; | ||
79 | |||
80 | /* only unmasked interrupts kick us out of idle */ | ||
81 | ICCR = 1; | ||
82 | |||
83 | for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) { | ||
84 | set_irq_chip(irq, &pxa_internal_chip_low); | ||
85 | set_irq_handler(irq, handle_level_irq); | ||
86 | set_irq_flags(irq, IRQF_VALID); | ||
87 | } | ||
88 | } | ||
89 | |||
70 | #ifdef CONFIG_PXA27x | 90 | #ifdef CONFIG_PXA27x |
71 | 91 | ||
72 | /* | 92 | /* |
@@ -331,12 +351,6 @@ void __init pxa_init_irq(void) | |||
331 | { | 351 | { |
332 | int irq; | 352 | int irq; |
333 | 353 | ||
334 | /* disable all IRQs */ | ||
335 | ICMR = 0; | ||
336 | |||
337 | /* all IRQs are IRQ, not FIQ */ | ||
338 | ICLR = 0; | ||
339 | |||
340 | /* clear all GPIO edge detects */ | 354 | /* clear all GPIO edge detects */ |
341 | GFER0 = 0; | 355 | GFER0 = 0; |
342 | GFER1 = 0; | 356 | GFER1 = 0; |
@@ -355,18 +369,10 @@ void __init pxa_init_irq(void) | |||
355 | GEDR3 = GEDR3; | 369 | GEDR3 = GEDR3; |
356 | #endif | 370 | #endif |
357 | 371 | ||
358 | /* only unmasked interrupts kick us out of idle */ | ||
359 | ICCR = 1; | ||
360 | |||
361 | /* GPIO 0 and 1 must have their mask bit always set */ | 372 | /* GPIO 0 and 1 must have their mask bit always set */ |
362 | GPIO_IRQ_mask[0] = 3; | 373 | GPIO_IRQ_mask[0] = 3; |
363 | 374 | ||
364 | for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) { | 375 | pxa_init_irq_low(); |
365 | set_irq_chip(irq, &pxa_internal_chip_low); | ||
366 | set_irq_handler(irq, handle_level_irq); | ||
367 | set_irq_flags(irq, IRQF_VALID); | ||
368 | } | ||
369 | |||
370 | #ifdef CONFIG_PXA27x | 376 | #ifdef CONFIG_PXA27x |
371 | pxa_init_irq_high(); | 377 | pxa_init_irq_high(); |
372 | #endif | 378 | #endif |