diff options
author | Heiko Stuebner <heiko@sntech.de> | 2011-10-14 02:08:57 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-14 02:15:53 -0400 |
commit | 33ccedfd1b79a7cf649b2991e95bae415c013240 (patch) | |
tree | a5210ff54f370adb3dd852cb1a99abaa0a7e2e27 /arch/arm | |
parent | 866a1c8c354e613c2bf378a1cd562756d4a32e75 (diff) |
ARM: S3C24XX: use clk_get_rate to init fclk in common_setup_clocks
Previously the fclk rate was calculated by dividing the pll through
the divider value of the armdiv. With a real armdiv clk in place it's
possible to simply read its value, which does essentially the same.
This change makes the whole fdiv_fn function pointers supplied to
s3c2443_common_init_clocks and s3c2443_common_setup_clocks
obsolete, so remove it too.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-s3c2416/clock.c | 11 | ||||
-rw-r--r-- | arch/arm/mach-s3c2443/clock.c | 11 | ||||
-rw-r--r-- | arch/arm/plat-s3c24xx/s3c2443-clock.c | 8 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/s3c2443.h | 5 |
4 files changed, 9 insertions, 26 deletions
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c index 7aa0cfa2f9bd..afbbe8bc21d1 100644 --- a/arch/arm/mach-s3c2416/clock.c +++ b/arch/arm/mach-s3c2416/clock.c | |||
@@ -133,16 +133,9 @@ static struct clk hsmmc0_clk = { | |||
133 | .ctrlbit = S3C2416_HCLKCON_HSMMC0, | 133 | .ctrlbit = S3C2416_HCLKCON_HSMMC0, |
134 | }; | 134 | }; |
135 | 135 | ||
136 | static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0) | ||
137 | { | ||
138 | clkcon0 &= S3C2416_CLKDIV0_ARMDIV_MASK; | ||
139 | |||
140 | return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]; | ||
141 | } | ||
142 | |||
143 | void __init_or_cpufreq s3c2416_setup_clocks(void) | 136 | void __init_or_cpufreq s3c2416_setup_clocks(void) |
144 | { | 137 | { |
145 | s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div); | 138 | s3c2443_common_setup_clocks(s3c2416_get_pll); |
146 | } | 139 | } |
147 | 140 | ||
148 | 141 | ||
@@ -166,7 +159,7 @@ void __init s3c2416_init_clocks(int xtal) | |||
166 | 159 | ||
167 | clk_epll.parent = &clk_epllref.clk; | 160 | clk_epll.parent = &clk_epllref.clk; |
168 | 161 | ||
169 | s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div, | 162 | s3c2443_common_init_clocks(xtal, s3c2416_get_pll, |
170 | armdiv, ARRAY_SIZE(armdiv), | 163 | armdiv, ARRAY_SIZE(armdiv), |
171 | S3C2416_CLKDIV0_ARMDIV_MASK); | 164 | S3C2416_CLKDIV0_ARMDIV_MASK); |
172 | 165 | ||
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 6fda4bf09cdd..b93cb96f57a5 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c | |||
@@ -76,13 +76,6 @@ static unsigned int armdiv[16] = { | |||
76 | [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16, | 76 | [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16, |
77 | }; | 77 | }; |
78 | 78 | ||
79 | static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0) | ||
80 | { | ||
81 | clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK; | ||
82 | |||
83 | return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]; | ||
84 | } | ||
85 | |||
86 | /* hsspi | 79 | /* hsspi |
87 | * | 80 | * |
88 | * high-speed spi clock, sourced from esysclk | 81 | * high-speed spi clock, sourced from esysclk |
@@ -191,7 +184,7 @@ static struct clk *clks[] __initdata = { | |||
191 | 184 | ||
192 | void __init_or_cpufreq s3c2443_setup_clocks(void) | 185 | void __init_or_cpufreq s3c2443_setup_clocks(void) |
193 | { | 186 | { |
194 | s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div); | 187 | s3c2443_common_setup_clocks(s3c2443_get_mpll); |
195 | } | 188 | } |
196 | 189 | ||
197 | void __init s3c2443_init_clocks(int xtal) | 190 | void __init s3c2443_init_clocks(int xtal) |
@@ -202,7 +195,7 @@ void __init s3c2443_init_clocks(int xtal) | |||
202 | clk_epll.rate = s3c2443_get_epll(epllcon, xtal); | 195 | clk_epll.rate = s3c2443_get_epll(epllcon, xtal); |
203 | clk_epll.parent = &clk_epllref.clk; | 196 | clk_epll.parent = &clk_epllref.clk; |
204 | 197 | ||
205 | s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div, | 198 | s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, |
206 | armdiv, ARRAY_SIZE(armdiv), | 199 | armdiv, ARRAY_SIZE(armdiv), |
207 | S3C2443_CLKDIV0_ARMDIV_MASK); | 200 | S3C2443_CLKDIV0_ARMDIV_MASK); |
208 | 201 | ||
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 40a87206400f..d3ebbeedf6d9 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c | |||
@@ -520,8 +520,7 @@ static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) | |||
520 | 520 | ||
521 | /* EPLLCON compatible enough to get on/off information */ | 521 | /* EPLLCON compatible enough to get on/off information */ |
522 | 522 | ||
523 | void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll, | 523 | void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll) |
524 | fdiv_fn get_fdiv) | ||
525 | { | 524 | { |
526 | unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); | 525 | unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); |
527 | unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); | 526 | unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); |
@@ -541,7 +540,7 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll, | |||
541 | pll = get_mpll(mpllcon, xtal); | 540 | pll = get_mpll(mpllcon, xtal); |
542 | clk_msysclk.clk.rate = pll; | 541 | clk_msysclk.clk.rate = pll; |
543 | 542 | ||
544 | fclk = pll / get_fdiv(clkdiv0); | 543 | fclk = clk_get_rate(&clk_armdiv); |
545 | hclk = s3c2443_prediv_getrate(&clk_prediv); | 544 | hclk = s3c2443_prediv_getrate(&clk_prediv); |
546 | hclk /= s3c2443_get_hdiv(clkdiv0); | 545 | hclk /= s3c2443_get_hdiv(clkdiv0); |
547 | pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); | 546 | pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); |
@@ -590,7 +589,6 @@ static struct clksrc_clk *clksrcs[] __initdata = { | |||
590 | }; | 589 | }; |
591 | 590 | ||
592 | void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, | 591 | void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, |
593 | fdiv_fn get_fdiv, | ||
594 | unsigned int *divs, int nr_divs, | 592 | unsigned int *divs, int nr_divs, |
595 | int divmask) | 593 | int divmask) |
596 | { | 594 | { |
@@ -620,5 +618,5 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, | |||
620 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | 618 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
621 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | 619 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
622 | 620 | ||
623 | s3c2443_common_setup_clocks(get_mpll, get_fdiv); | 621 | s3c2443_common_setup_clocks(get_mpll); |
624 | } | 622 | } |
diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h index 5fc4ad0fd756..7fae1a050694 100644 --- a/arch/arm/plat-samsung/include/plat/s3c2443.h +++ b/arch/arm/plat-samsung/include/plat/s3c2443.h | |||
@@ -37,10 +37,9 @@ extern int s3c2443_baseclk_add(void); | |||
37 | struct clk; /* some files don't need clk.h otherwise */ | 37 | struct clk; /* some files don't need clk.h otherwise */ |
38 | 38 | ||
39 | typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base); | 39 | typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base); |
40 | typedef unsigned int (*fdiv_fn)(unsigned long clkcon0); | ||
41 | 40 | ||
42 | extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv); | 41 | extern void s3c2443_common_setup_clocks(pll_fn get_mpll); |
43 | extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv, | 42 | extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, |
44 | unsigned int *divs, int nr_divs, | 43 | unsigned int *divs, int nr_divs, |
45 | int divmask); | 44 | int divmask); |
46 | 45 | ||