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authorDavid S. Miller <davem@davemloft.net>2010-02-17 01:09:29 -0500
committerDavid S. Miller <davem@davemloft.net>2010-02-17 01:09:29 -0500
commit2bb4646fce8d09916b351d1a62f98db7cec6fc41 (patch)
treec1f0d002e69868606eca9d1b919835f422892063 /arch/arm
parent6836b9bdd98e3b500cd49512484df68f46e14659 (diff)
parentb0483e78e5c4c9871fc5541875b3bc006846d46b (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/mach-kirkwood/rd88f6192-nas-setup.c6
-rw-r--r--arch/arm/mach-mx25/clock.c58
-rw-r--r--arch/arm/mach-mx25/mx25pdk.c2
-rw-r--r--arch/arm/mach-mx3/mx31ads.c4
-rw-r--r--arch/arm/mach-omap1/clock.c6
-rw-r--r--arch/arm/mach-omap2/clock34xx_data.c4
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c62
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c2
-rw-r--r--arch/arm/mach-omap2/gpmc.c7
-rw-r--r--arch/arm/mach-omap2/id.c41
-rw-r--r--arch/arm/mach-omap2/irq.c22
-rw-r--r--arch/arm/mach-omap2/mmc-twl4030.c7
-rw-r--r--arch/arm/mach-omap2/mux.c37
-rw-r--r--arch/arm/mach-omap2/mux.h24
-rw-r--r--arch/arm/mach-omap2/mux34xx.c47
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c3
-rw-r--r--arch/arm/mach-omap2/pm-debug.c12
-rw-r--r--arch/arm/mach-omap2/pm.h8
-rw-r--r--arch/arm/mach-omap2/pm34xx.c47
-rw-r--r--arch/arm/mach-omap2/prcm.c11
-rw-r--r--arch/arm/mach-omap2/prm.h2
-rw-r--r--arch/arm/mach-omap2/prm44xx.h32
-rw-r--r--arch/arm/mach-omap2/serial.c11
-rw-r--r--arch/arm/mach-omap2/sleep34xx.S13
-rw-r--r--arch/arm/mach-orion5x/dns323-setup.c33
-rw-r--r--arch/arm/mach-orion5x/wrt350n-v2-setup.c79
-rw-r--r--arch/arm/mach-pxa/corgi.c1
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa25x.h6
-rw-r--r--arch/arm/mach-pxa/irq.c14
-rw-r--r--arch/arm/mach-realview/realview_pbx.c4
-rw-r--r--arch/arm/mach-s3c6410/mach-hmt.c2
-rw-r--r--arch/arm/mm/proc-arm6_7.S2
-rw-r--r--arch/arm/plat-mxc/audmux-v2.c137
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31lite.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx35.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h5
-rw-r--r--arch/arm/plat-omap/clock.c4
-rw-r--r--arch/arm/plat-omap/common.c26
-rw-r--r--arch/arm/plat-omap/dma.c2
-rw-r--r--arch/arm/plat-omap/dmtimer.c13
-rw-r--r--arch/arm/plat-omap/gpio.c4
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h1
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h3
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h1
-rw-r--r--arch/arm/plat-omap/omap_device.c10
-rw-r--r--arch/arm/plat-orion/pcie.c6
-rw-r--r--arch/arm/tools/mach-types60
-rw-r--r--arch/arm/vfp/vfpmodule.c5
51 files changed, 700 insertions, 195 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4c33ca82f9b1..184a6bd54825 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -702,6 +702,7 @@ config ARCH_OMAP
702 select ARCH_HAS_CPUFREQ 702 select ARCH_HAS_CPUFREQ
703 select GENERIC_TIME 703 select GENERIC_TIME
704 select GENERIC_CLOCKEVENTS 704 select GENERIC_CLOCKEVENTS
705 select ARCH_HAS_HOLES_MEMORYMODEL
705 help 706 help
706 Support for TI's OMAP platform (OMAP1 and OMAP2). 707 Support for TI's OMAP platform (OMAP1 and OMAP2).
707 708
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 9e7582572741..356d702c0808 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -94,7 +94,7 @@ CFLAGS_ABI +=-funwind-tables
94endif 94endif
95 95
96ifeq ($(CONFIG_THUMB2_KERNEL),y) 96ifeq ($(CONFIG_THUMB2_KERNEL),y)
97AFLAGS_AUTOIT :=$(call as-option,-Wa$(comma)-mimplicit-it=thumb,-Wa$(comma)-mauto-it) 97AFLAGS_AUTOIT :=$(call as-option,-Wa$(comma)-mimplicit-it=always,-Wa$(comma)-mauto-it)
98AFLAGS_NOWARN :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W) 98AFLAGS_NOWARN :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)
99CFLAGS_THUMB2 :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN) 99CFLAGS_THUMB2 :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)
100AFLAGS_THUMB2 :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb 100AFLAGS_THUMB2 :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 8bf4153d0840..3bf6304158f6 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -13,6 +13,7 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/ata_platform.h> 14#include <linux/ata_platform.h>
15#include <linux/mv643xx_eth.h> 15#include <linux/mv643xx_eth.h>
16#include <linux/gpio.h>
16#include <linux/spi/flash.h> 17#include <linux/spi/flash.h>
17#include <linux/spi/spi.h> 18#include <linux/spi/spi.h>
18#include <linux/spi/orion_spi.h> 19#include <linux/spi/orion_spi.h>
@@ -53,6 +54,11 @@ static void __init rd88f6192_init(void)
53 */ 54 */
54 kirkwood_init(); 55 kirkwood_init();
55 56
57 orion_gpio_set_valid(RD88F6192_GPIO_USB_VBUS, 1);
58 if (gpio_request(RD88F6192_GPIO_USB_VBUS, "USB VBUS") != 0 ||
59 gpio_direction_output(RD88F6192_GPIO_USB_VBUS, 1) != 0)
60 pr_err("RD-88F6192-NAS: failed to setup USB VBUS GPIO\n");
61
56 kirkwood_ehci_init(); 62 kirkwood_ehci_init();
57 kirkwood_ge00_init(&rd88f6192_ge00_data); 63 kirkwood_ge00_init(&rd88f6192_ge00_data);
58 kirkwood_sata_init(&rd88f6192_sata_data); 64 kirkwood_sata_init(&rd88f6192_sata_data);
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 6e838b857712..6acc88bcdc40 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -119,6 +119,11 @@ static unsigned long get_rate_nfc(struct clk *clk)
119 return get_rate_per(8); 119 return get_rate_per(8);
120} 120}
121 121
122static unsigned long get_rate_gpt(struct clk *clk)
123{
124 return get_rate_per(5);
125}
126
122static unsigned long get_rate_otg(struct clk *clk) 127static unsigned long get_rate_otg(struct clk *clk)
123{ 128{
124 return 48000000; /* FIXME */ 129 return 48000000; /* FIXME */
@@ -144,7 +149,7 @@ static void clk_cgcr_disable(struct clk *clk)
144 __raw_writel(reg, clk->enable_reg); 149 __raw_writel(reg, clk->enable_reg);
145} 150}
146 151
147#define DEFINE_CLOCK(name, i, er, es, gr, sr) \ 152#define DEFINE_CLOCK(name, i, er, es, gr, sr, s) \
148 static struct clk name = { \ 153 static struct clk name = { \
149 .id = i, \ 154 .id = i, \
150 .enable_reg = CRM_BASE + er, \ 155 .enable_reg = CRM_BASE + er, \
@@ -153,27 +158,30 @@ static void clk_cgcr_disable(struct clk *clk)
153 .set_rate = sr, \ 158 .set_rate = sr, \
154 .enable = clk_cgcr_enable, \ 159 .enable = clk_cgcr_enable, \
155 .disable = clk_cgcr_disable, \ 160 .disable = clk_cgcr_disable, \
161 .secondary = s, \
156 } 162 }
157 163
158DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_ipg, NULL); 164DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL);
159DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL); 165DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
160DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL); 166DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL);
161DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL); 167DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL);
162DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL); 168DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
163DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL); 169DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
164DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL); 170DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
165DEFINE_CLOCK(uart4_clk, 0, CCM_CGCR2, 17, get_rate_uart, NULL); 171DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
166DEFINE_CLOCK(uart5_clk, 0, CCM_CGCR2, 18, get_rate_uart, NULL); 172DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
167DEFINE_CLOCK(nfc_clk, 0, CCM_CGCR0, 8, get_rate_nfc, NULL); 173DEFINE_CLOCK(uart4_clk, 0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk);
168DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL); 174DEFINE_CLOCK(uart5_clk, 0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk);
169DEFINE_CLOCK(pwm1_clk, 0, CCM_CGCR1, 31, get_rate_ipg, NULL); 175DEFINE_CLOCK(nfc_clk, 0, CCM_CGCR0, 8, get_rate_nfc, NULL, NULL);
170DEFINE_CLOCK(pwm2_clk, 0, CCM_CGCR2, 0, get_rate_ipg, NULL); 176DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL);
171DEFINE_CLOCK(pwm3_clk, 0, CCM_CGCR2, 1, get_rate_ipg, NULL); 177DEFINE_CLOCK(pwm1_clk, 0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL);
172DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL); 178DEFINE_CLOCK(pwm2_clk, 0, CCM_CGCR2, 0, get_rate_ipg, NULL, NULL);
173DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL); 179DEFINE_CLOCK(pwm3_clk, 0, CCM_CGCR2, 1, get_rate_ipg, NULL, NULL);
174DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL); 180DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL, NULL);
175DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL); 181DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL);
176DEFINE_CLOCK(fec_clk, 0, CCM_CGCR0, 23, get_rate_ipg, NULL); 182DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);
183DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL);
184DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
177 185
178#define _REGISTER_CLOCK(d, n, c) \ 186#define _REGISTER_CLOCK(d, n, c) \
179 { \ 187 { \
@@ -208,13 +216,21 @@ static struct clk_lookup lookups[] = {
208 _REGISTER_CLOCK("fec.0", NULL, fec_clk) 216 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
209}; 217};
210 218
211int __init mx25_clocks_init(unsigned long fref) 219int __init mx25_clocks_init(void)
212{ 220{
213 int i; 221 int i;
214 222
215 for (i = 0; i < ARRAY_SIZE(lookups); i++) 223 for (i = 0; i < ARRAY_SIZE(lookups); i++)
216 clkdev_add(&lookups[i]); 224 clkdev_add(&lookups[i]);
217 225
226 /* Turn off all clocks except the ones we need to survive, namely:
227 * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
228 * SCC
229 */
230 __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
231 __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
232 __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
233
218 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); 234 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
219 235
220 return 0; 236 return 0;
diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mx25pdk.c
index 921bc99ea231..6f06089246eb 100644
--- a/arch/arm/mach-mx25/mx25pdk.c
+++ b/arch/arm/mach-mx25/mx25pdk.c
@@ -91,7 +91,7 @@ static void __init mx25pdk_init(void)
91 91
92static void __init mx25pdk_timer_init(void) 92static void __init mx25pdk_timer_init(void)
93{ 93{
94 mx25_clocks_init(26000000); 94 mx25_clocks_init();
95} 95}
96 96
97static struct sys_timer mx25pdk_timer = { 97static struct sys_timer mx25pdk_timer = {
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index 3e7bafa2ddbb..938c549767dc 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -173,6 +173,7 @@ static void expio_unmask_irq(u32 irq)
173} 173}
174 174
175static struct irq_chip expio_irq_chip = { 175static struct irq_chip expio_irq_chip = {
176 .name = "EXPIO(CPLD)",
176 .ack = expio_ack_irq, 177 .ack = expio_ack_irq,
177 .mask = expio_mask_irq, 178 .mask = expio_mask_irq,
178 .unmask = expio_unmask_irq, 179 .unmask = expio_unmask_irq,
@@ -302,6 +303,7 @@ static struct regulator_init_data ldo1_data = {
302 .min_uV = 2800000, 303 .min_uV = 2800000,
303 .max_uV = 2800000, 304 .max_uV = 2800000,
304 .valid_modes_mask = REGULATOR_MODE_NORMAL, 305 .valid_modes_mask = REGULATOR_MODE_NORMAL,
306 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
305 .apply_uV = 1, 307 .apply_uV = 1,
306 }, 308 },
307}; 309};
@@ -322,6 +324,7 @@ static struct regulator_init_data ldo2_data = {
322 .min_uV = 3300000, 324 .min_uV = 3300000,
323 .max_uV = 3300000, 325 .max_uV = 3300000,
324 .valid_modes_mask = REGULATOR_MODE_NORMAL, 326 .valid_modes_mask = REGULATOR_MODE_NORMAL,
327 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
325 .apply_uV = 1, 328 .apply_uV = 1,
326 }, 329 },
327 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers), 330 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
@@ -459,6 +462,7 @@ static int mx31_wm8350_init(struct wm8350 *wm8350)
459 462
460static struct wm8350_platform_data __initdata mx31_wm8350_pdata = { 463static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
461 .init = mx31_wm8350_init, 464 .init = mx31_wm8350_init,
465 .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
462}; 466};
463#endif 467#endif
464 468
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 2ba9ab953731..04f1d29cba2c 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -214,8 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
214 struct mpu_rate * ptr; 214 struct mpu_rate * ptr;
215 unsigned long dpll1_rate, ref_rate; 215 unsigned long dpll1_rate, ref_rate;
216 216
217 dpll1_rate = clk_get_rate(ck_dpll1_p); 217 dpll1_rate = ck_dpll1_p->rate;
218 ref_rate = clk_get_rate(ck_ref_p); 218 ref_rate = ck_ref_p->rate;
219 219
220 for (ptr = omap1_rate_table; ptr->rate; ptr++) { 220 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
221 if (ptr->xtal != ref_rate) 221 if (ptr->xtal != ref_rate)
@@ -306,7 +306,7 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
306 long highest_rate; 306 long highest_rate;
307 unsigned long ref_rate; 307 unsigned long ref_rate;
308 308
309 ref_rate = clk_get_rate(ck_ref_p); 309 ref_rate = ck_ref_p->rate;
310 310
311 highest_rate = -EINVAL; 311 highest_rate = -EINVAL;
312 312
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
index c6031d74d6f6..74930e3158e3 100644
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -671,7 +671,6 @@ static struct clk dpll4_m3x2_ck = {
671 .name = "dpll4_m3x2_ck", 671 .name = "dpll4_m3x2_ck",
672 .ops = &clkops_omap2_dflt_wait, 672 .ops = &clkops_omap2_dflt_wait,
673 .parent = &dpll4_m3_ck, 673 .parent = &dpll4_m3_ck,
674 .init = &omap2_init_clksel_parent,
675 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 674 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
676 .enable_bit = OMAP3430_PWRDN_TV_SHIFT, 675 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
677 .flags = INVERT_ENABLE, 676 .flags = INVERT_ENABLE,
@@ -811,7 +810,6 @@ static struct clk dpll4_m6x2_ck = {
811 .name = "dpll4_m6x2_ck", 810 .name = "dpll4_m6x2_ck",
812 .ops = &clkops_omap2_dflt_wait, 811 .ops = &clkops_omap2_dflt_wait,
813 .parent = &dpll4_m6_ck, 812 .parent = &dpll4_m6_ck,
814 .init = &omap2_init_clksel_parent,
815 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 813 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
816 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, 814 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
817 .flags = INVERT_ENABLE, 815 .flags = INVERT_ENABLE,
@@ -1047,7 +1045,6 @@ static struct clk iva2_ck = {
1047 .name = "iva2_ck", 1045 .name = "iva2_ck",
1048 .ops = &clkops_omap2_dflt_wait, 1046 .ops = &clkops_omap2_dflt_wait,
1049 .parent = &dpll2_m2_ck, 1047 .parent = &dpll2_m2_ck,
1050 .init = &omap2_init_clksel_parent,
1051 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), 1048 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1052 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 1049 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1053 .clkdm_name = "iva2_clkdm", 1050 .clkdm_name = "iva2_clkdm",
@@ -1121,7 +1118,6 @@ static struct clk gfx_l3_ck = {
1121 .name = "gfx_l3_ck", 1118 .name = "gfx_l3_ck",
1122 .ops = &clkops_omap2_dflt_wait, 1119 .ops = &clkops_omap2_dflt_wait,
1123 .parent = &l3_ick, 1120 .parent = &l3_ick,
1124 .init = &omap2_init_clksel_parent,
1125 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1121 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1126 .enable_bit = OMAP_EN_GFX_SHIFT, 1122 .enable_bit = OMAP_EN_GFX_SHIFT,
1127 .recalc = &followparent_recalc, 1123 .recalc = &followparent_recalc,
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 2210e227d78a..9d882bcb56e3 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -346,37 +346,37 @@ static struct clk aess_fclk = {
346}; 346};
347 347
348static const struct clksel_rate div31_1to31_rates[] = { 348static const struct clksel_rate div31_1to31_rates[] = {
349 { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 349 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
350 { .div = 2, .val = 1, .flags = RATE_IN_4430 }, 350 { .div = 2, .val = 2, .flags = RATE_IN_4430 },
351 { .div = 3, .val = 2, .flags = RATE_IN_4430 }, 351 { .div = 3, .val = 3, .flags = RATE_IN_4430 },
352 { .div = 4, .val = 3, .flags = RATE_IN_4430 }, 352 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
353 { .div = 5, .val = 4, .flags = RATE_IN_4430 }, 353 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
354 { .div = 6, .val = 5, .flags = RATE_IN_4430 }, 354 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
355 { .div = 7, .val = 6, .flags = RATE_IN_4430 }, 355 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
356 { .div = 8, .val = 7, .flags = RATE_IN_4430 }, 356 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
357 { .div = 9, .val = 8, .flags = RATE_IN_4430 }, 357 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
358 { .div = 10, .val = 9, .flags = RATE_IN_4430 }, 358 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
359 { .div = 11, .val = 10, .flags = RATE_IN_4430 }, 359 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
360 { .div = 12, .val = 11, .flags = RATE_IN_4430 }, 360 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
361 { .div = 13, .val = 12, .flags = RATE_IN_4430 }, 361 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
362 { .div = 14, .val = 13, .flags = RATE_IN_4430 }, 362 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
363 { .div = 15, .val = 14, .flags = RATE_IN_4430 }, 363 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
364 { .div = 16, .val = 15, .flags = RATE_IN_4430 }, 364 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
365 { .div = 17, .val = 16, .flags = RATE_IN_4430 }, 365 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
366 { .div = 18, .val = 17, .flags = RATE_IN_4430 }, 366 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
367 { .div = 19, .val = 18, .flags = RATE_IN_4430 }, 367 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
368 { .div = 20, .val = 19, .flags = RATE_IN_4430 }, 368 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
369 { .div = 21, .val = 20, .flags = RATE_IN_4430 }, 369 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
370 { .div = 22, .val = 21, .flags = RATE_IN_4430 }, 370 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
371 { .div = 23, .val = 22, .flags = RATE_IN_4430 }, 371 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
372 { .div = 24, .val = 23, .flags = RATE_IN_4430 }, 372 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
373 { .div = 25, .val = 24, .flags = RATE_IN_4430 }, 373 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
374 { .div = 26, .val = 25, .flags = RATE_IN_4430 }, 374 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
375 { .div = 27, .val = 26, .flags = RATE_IN_4430 }, 375 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
376 { .div = 28, .val = 27, .flags = RATE_IN_4430 }, 376 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
377 { .div = 29, .val = 28, .flags = RATE_IN_4430 }, 377 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
378 { .div = 30, .val = 29, .flags = RATE_IN_4430 }, 378 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
379 { .div = 31, .val = 30, .flags = RATE_IN_4430 }, 379 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
380 { .div = 0 }, 380 { .div = 0 },
381}; 381};
382 382
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index a26d6a08ae3f..12f0cbfc2894 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -137,7 +137,7 @@ return_sleep_time:
137 local_irq_enable(); 137 local_irq_enable();
138 local_fiq_enable(); 138 local_fiq_enable();
139 139
140 return (u32)timespec_to_ns(&ts_idle)/1000; 140 return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
141} 141}
142 142
143/** 143/**
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index bd8cb5974726..7027cdc1ba49 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -505,7 +505,7 @@ static void __init gpmc_mem_init(void)
505void __init gpmc_init(void) 505void __init gpmc_init(void)
506{ 506{
507 u32 l; 507 u32 l;
508 char *ck; 508 char *ck = NULL;
509 509
510 if (cpu_is_omap24xx()) { 510 if (cpu_is_omap24xx()) {
511 ck = "core_l3_ck"; 511 ck = "core_l3_ck";
@@ -521,6 +521,9 @@ void __init gpmc_init(void)
521 l = OMAP44XX_GPMC_BASE; 521 l = OMAP44XX_GPMC_BASE;
522 } 522 }
523 523
524 if (WARN_ON(!ck))
525 return;
526
524 gpmc_l3_clk = clk_get(NULL, ck); 527 gpmc_l3_clk = clk_get(NULL, ck);
525 if (IS_ERR(gpmc_l3_clk)) { 528 if (IS_ERR(gpmc_l3_clk)) {
526 printk(KERN_ERR "Could not get GPMC clock %s\n", ck); 529 printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
@@ -534,6 +537,8 @@ void __init gpmc_init(void)
534 BUG(); 537 BUG();
535 } 538 }
536 539
540 clk_enable(gpmc_l3_clk);
541
537 l = gpmc_read_reg(GPMC_REVISION); 542 l = gpmc_read_reg(GPMC_REVISION);
538 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); 543 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
539 /* Set smart idle mode and automatic L3 clock gating */ 544 /* Set smart idle mode and automatic L3 clock gating */
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index a091b53657b9..3d65c50bd017 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -188,6 +188,8 @@ void __init omap3_check_revision(void)
188 u16 hawkeye; 188 u16 hawkeye;
189 u8 rev; 189 u8 rev;
190 190
191 omap_chip.oc = CHIP_IS_OMAP3430;
192
191 /* 193 /*
192 * We cannot access revision registers on ES1.0. 194 * We cannot access revision registers on ES1.0.
193 * If the processor type is Cortex-A8 and the revision is 0x0 195 * If the processor type is Cortex-A8 and the revision is 0x0
@@ -196,6 +198,7 @@ void __init omap3_check_revision(void)
196 cpuid = read_cpuid(CPUID_ID); 198 cpuid = read_cpuid(CPUID_ID);
197 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { 199 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
198 omap_revision = OMAP3430_REV_ES1_0; 200 omap_revision = OMAP3430_REV_ES1_0;
201 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
199 return; 202 return;
200 } 203 }
201 204
@@ -216,18 +219,28 @@ void __init omap3_check_revision(void)
216 case 0: /* Take care of early samples */ 219 case 0: /* Take care of early samples */
217 case 1: 220 case 1:
218 omap_revision = OMAP3430_REV_ES2_0; 221 omap_revision = OMAP3430_REV_ES2_0;
222 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
219 break; 223 break;
220 case 2: 224 case 2:
221 omap_revision = OMAP3430_REV_ES2_1; 225 omap_revision = OMAP3430_REV_ES2_1;
226 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
222 break; 227 break;
223 case 3: 228 case 3:
224 omap_revision = OMAP3430_REV_ES3_0; 229 omap_revision = OMAP3430_REV_ES3_0;
230 omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
225 break; 231 break;
226 case 4: 232 case 4:
233 omap_revision = OMAP3430_REV_ES3_1;
234 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
235 break;
236 case 7:
227 /* FALLTHROUGH */ 237 /* FALLTHROUGH */
228 default: 238 default:
229 /* Use the latest known revision as default */ 239 /* Use the latest known revision as default */
230 omap_revision = OMAP3430_REV_ES3_1; 240 omap_revision = OMAP3430_REV_ES3_1_2;
241
242 /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
243 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
231 } 244 }
232 break; 245 break;
233 case 0xb868: 246 case 0xb868:
@@ -235,14 +248,18 @@ void __init omap3_check_revision(void)
235 * 248 *
236 * Set the device to be OMAP3505 here. Actual device 249 * Set the device to be OMAP3505 here. Actual device
237 * is identified later based on the features. 250 * is identified later based on the features.
251 *
252 * REVISIT: AM3505/AM3517 should have their own CHIP_IS
238 */ 253 */
239 omap_revision = OMAP3505_REV(rev); 254 omap_revision = OMAP3505_REV(rev);
255 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
240 break; 256 break;
241 case 0xb891: 257 case 0xb891:
242 /* FALLTHROUGH */ 258 /* FALLTHROUGH */
243 default: 259 default:
244 /* Unknown default to latest silicon rev as default*/ 260 /* Unknown default to latest silicon rev as default*/
245 omap_revision = OMAP3630_REV_ES1_0; 261 omap_revision = OMAP3630_REV_ES1_0;
262 omap_chip.oc |= CHIP_IS_OMAP3630ES1;
246 } 263 }
247} 264}
248 265
@@ -360,6 +377,7 @@ void __init omap2_check_revision(void)
360 omap3_check_revision(); 377 omap3_check_revision();
361 omap3_check_features(); 378 omap3_check_features();
362 omap3_cpuinfo(); 379 omap3_cpuinfo();
380 return;
363 } else if (cpu_is_omap44xx()) { 381 } else if (cpu_is_omap44xx()) {
364 omap4_check_revision(); 382 omap4_check_revision();
365 return; 383 return;
@@ -374,27 +392,14 @@ void __init omap2_check_revision(void)
374 if (cpu_is_omap243x()) { 392 if (cpu_is_omap243x()) {
375 /* Currently only supports 2430ES2.1 and 2430-all */ 393 /* Currently only supports 2430ES2.1 and 2430-all */
376 omap_chip.oc |= CHIP_IS_OMAP2430; 394 omap_chip.oc |= CHIP_IS_OMAP2430;
395 return;
377 } else if (cpu_is_omap242x()) { 396 } else if (cpu_is_omap242x()) {
378 /* Currently only supports 2420ES2.1.1 and 2420-all */ 397 /* Currently only supports 2420ES2.1.1 and 2420-all */
379 omap_chip.oc |= CHIP_IS_OMAP2420; 398 omap_chip.oc |= CHIP_IS_OMAP2420;
380 } else if (cpu_is_omap3505() || cpu_is_omap3517()) { 399 return;
381 omap_chip.oc = CHIP_IS_OMAP3430 | CHIP_IS_OMAP3430ES3_1;
382 } else if (cpu_is_omap343x()) {
383 omap_chip.oc = CHIP_IS_OMAP3430;
384 if (omap_rev() == OMAP3430_REV_ES1_0)
385 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
386 else if (omap_rev() >= OMAP3430_REV_ES2_0 &&
387 omap_rev() <= OMAP3430_REV_ES2_1)
388 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
389 else if (omap_rev() == OMAP3430_REV_ES3_0)
390 omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
391 else if (omap_rev() == OMAP3430_REV_ES3_1)
392 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
393 else if (omap_rev() == OMAP3630_REV_ES1_0)
394 omap_chip.oc |= CHIP_IS_OMAP3630ES1;
395 } else {
396 pr_err("Uninitialized omap_chip, please fix!\n");
397 } 400 }
401
402 pr_err("Uninitialized omap_chip, please fix!\n");
398} 403}
399 404
400/* 405/*
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index e9bc782fa414..26aeef560aa3 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -194,7 +194,7 @@ void __init omap_init_irq(void)
194 int i; 194 int i;
195 195
196 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { 196 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
197 unsigned long base; 197 unsigned long base = 0;
198 struct omap_irq_bank *bank = irq_banks + i; 198 struct omap_irq_bank *bank = irq_banks + i;
199 199
200 if (cpu_is_omap24xx()) 200 if (cpu_is_omap24xx())
@@ -202,6 +202,8 @@ void __init omap_init_irq(void)
202 else if (cpu_is_omap34xx()) 202 else if (cpu_is_omap34xx())
203 base = OMAP34XX_IC_BASE; 203 base = OMAP34XX_IC_BASE;
204 204
205 BUG_ON(!base);
206
205 /* Static mapping, never released */ 207 /* Static mapping, never released */
206 bank->base_reg = ioremap(base, SZ_4K); 208 bank->base_reg = ioremap(base, SZ_4K);
207 if (!bank->base_reg) { 209 if (!bank->base_reg) {
@@ -274,4 +276,22 @@ void omap_intc_restore_context(void)
274 } 276 }
275 /* MIRs are saved and restore with other PRCM registers */ 277 /* MIRs are saved and restore with other PRCM registers */
276} 278}
279
280void omap3_intc_suspend(void)
281{
282 /* A pending interrupt would prevent OMAP from entering suspend */
283 omap_ack_irq(0);
284}
285
286void omap3_intc_prepare_idle(void)
287{
288 /* Disable autoidle as it can stall interrupt controller */
289 intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
290}
291
292void omap3_intc_resume_idle(void)
293{
294 /* Re-enable autoidle */
295 intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
296}
277#endif /* CONFIG_ARCH_OMAP3 */ 297#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c
index 0c3c72d934bf..8afe9dd3f150 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.c
+++ b/arch/arm/mach-omap2/mmc-twl4030.c
@@ -408,6 +408,7 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
408{ 408{
409 struct twl4030_hsmmc_info *c; 409 struct twl4030_hsmmc_info *c;
410 int nr_hsmmc = ARRAY_SIZE(hsmmc_data); 410 int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
411 int i;
411 412
412 if (cpu_is_omap2430()) { 413 if (cpu_is_omap2430()) {
413 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; 414 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
@@ -434,7 +435,7 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
434 mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); 435 mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
435 if (!mmc) { 436 if (!mmc) {
436 pr_err("Cannot allocate memory for mmc device!\n"); 437 pr_err("Cannot allocate memory for mmc device!\n");
437 return; 438 goto done;
438 } 439 }
439 440
440 if (c->name) 441 if (c->name)
@@ -532,6 +533,10 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
532 continue; 533 continue;
533 c->dev = mmc->dev; 534 c->dev = mmc->dev;
534 } 535 }
536
537done:
538 for (i = 0; i < nr_hsmmc; i++)
539 kfree(hsmmc_data[i]);
535} 540}
536 541
537#endif 542#endif
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 459ef23ab8a8..5fedc50c58e4 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -51,7 +51,7 @@ struct omap_mux_entry {
51static unsigned long mux_phys; 51static unsigned long mux_phys;
52static void __iomem *mux_base; 52static void __iomem *mux_base;
53 53
54static inline u16 omap_mux_read(u16 reg) 54u16 omap_mux_read(u16 reg)
55{ 55{
56 if (cpu_is_omap24xx()) 56 if (cpu_is_omap24xx())
57 return __raw_readb(mux_base + reg); 57 return __raw_readb(mux_base + reg);
@@ -59,7 +59,7 @@ static inline u16 omap_mux_read(u16 reg)
59 return __raw_readw(mux_base + reg); 59 return __raw_readw(mux_base + reg);
60} 60}
61 61
62static inline void omap_mux_write(u16 val, u16 reg) 62void omap_mux_write(u16 val, u16 reg)
63{ 63{
64 if (cpu_is_omap24xx()) 64 if (cpu_is_omap24xx())
65 __raw_writeb(val, mux_base + reg); 65 __raw_writeb(val, mux_base + reg);
@@ -67,6 +67,14 @@ static inline void omap_mux_write(u16 val, u16 reg)
67 __raw_writew(val, mux_base + reg); 67 __raw_writew(val, mux_base + reg);
68} 68}
69 69
70void omap_mux_write_array(struct omap_board_mux *board_mux)
71{
72 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
73 omap_mux_write(board_mux->value, board_mux->reg_offset);
74 board_mux++;
75 }
76}
77
70#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX) 78#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX)
71 79
72static struct omap_mux_cfg arch_mux_cfg; 80static struct omap_mux_cfg arch_mux_cfg;
@@ -478,7 +486,7 @@ int __init omap_mux_init_signal(char *muxname, int val)
478static inline void omap_mux_decode(struct seq_file *s, u16 val) 486static inline void omap_mux_decode(struct seq_file *s, u16 val)
479{ 487{
480 char *flags[OMAP_MUX_MAX_NR_FLAGS]; 488 char *flags[OMAP_MUX_MAX_NR_FLAGS];
481 char mode[14]; 489 char mode[sizeof("OMAP_MUX_MODE") + 1];
482 int i = -1; 490 int i = -1;
483 491
484 sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7); 492 sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
@@ -545,6 +553,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
545 if (!m0_name) 553 if (!m0_name)
546 continue; 554 continue;
547 555
556 /* REVISIT: Needs to be updated if mode0 names get longer */
548 for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) { 557 for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
549 if (m0_name[i] == '\0') { 558 if (m0_name[i] == '\0') {
550 m0_def[i] = m0_name[i]; 559 m0_def[i] = m0_name[i];
@@ -833,14 +842,6 @@ static void __init omap_mux_set_cmdline_signals(void)
833 kfree(options); 842 kfree(options);
834} 843}
835 844
836static void __init omap_mux_set_board_signals(struct omap_board_mux *board_mux)
837{
838 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
839 omap_mux_write(board_mux->value, board_mux->reg_offset);
840 board_mux++;
841 }
842}
843
844static int __init omap_mux_copy_names(struct omap_mux *src, 845static int __init omap_mux_copy_names(struct omap_mux *src,
845 struct omap_mux *dst) 846 struct omap_mux *dst)
846{ 847{
@@ -968,6 +969,13 @@ static void __init omap_mux_init_list(struct omap_mux *superset)
968 } 969 }
969#endif 970#endif
970 971
972#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)
973 if (!superset->muxnames || !superset->muxnames[0]) {
974 superset++;
975 continue;
976 }
977#endif
978
971 entry = omap_mux_list_add(superset); 979 entry = omap_mux_list_add(superset);
972 if (!entry) { 980 if (!entry) {
973 printk(KERN_ERR "mux: Could not add entry\n"); 981 printk(KERN_ERR "mux: Could not add entry\n");
@@ -998,12 +1006,15 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
998 omap_mux_package_fixup(package_subset, superset); 1006 omap_mux_package_fixup(package_subset, superset);
999 if (package_balls) 1007 if (package_balls)
1000 omap_mux_package_init_balls(package_balls, superset); 1008 omap_mux_package_init_balls(package_balls, superset);
1001 omap_mux_set_cmdline_signals();
1002 omap_mux_set_board_signals(board_mux);
1003#endif 1009#endif
1004 1010
1005 omap_mux_init_list(superset); 1011 omap_mux_init_list(superset);
1006 1012
1013#ifdef CONFIG_OMAP_MUX
1014 omap_mux_set_cmdline_signals();
1015 omap_mux_write_array(board_mux);
1016#endif
1017
1007 return 0; 1018 return 0;
1008} 1019}
1009 1020
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index d8b4d5ad2278..f8c2e7a8f063 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -147,6 +147,30 @@ u16 omap_mux_get_gpio(int gpio);
147void omap_mux_set_gpio(u16 val, int gpio); 147void omap_mux_set_gpio(u16 val, int gpio);
148 148
149/** 149/**
150 * omap_mux_read() - read mux register
151 * @mux_offset: Offset of the mux register
152 *
153 */
154u16 omap_mux_read(u16 mux_offset);
155
156/**
157 * omap_mux_write() - write mux register
158 * @val: New mux register value
159 * @mux_offset: Offset of the mux register
160 *
161 * This should be only needed for dynamic remuxing of non-gpio signals.
162 */
163void omap_mux_write(u16 val, u16 mux_offset);
164
165/**
166 * omap_mux_write_array() - write an array of mux registers
167 * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
168 *
169 * This should be only needed for dynamic remuxing of non-gpio signals.
170 */
171void omap_mux_write_array(struct omap_board_mux *board_mux);
172
173/**
150 * omap3_mux_init() - initialize mux system with board specific set 174 * omap3_mux_init() - initialize mux system with board specific set
151 * @board_mux: Board specific mux table 175 * @board_mux: Board specific mux table
152 * @flags: OMAP package type used for the board 176 * @flags: OMAP package type used for the board
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index 68e0a595f9a1..07aa7b3c95f7 100644
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -649,6 +649,53 @@ static struct omap_mux __initdata omap3_muxmodes[] = {
649 _OMAP3_MUXENTRY(UART3_TX_IRTX, 166, 649 _OMAP3_MUXENTRY(UART3_TX_IRTX, 166,
650 "uart3_tx_irtx", NULL, NULL, NULL, 650 "uart3_tx_irtx", NULL, NULL, NULL,
651 "gpio_166", NULL, NULL, "safe_mode"), 651 "gpio_166", NULL, NULL, "safe_mode"),
652
653 /* Only on 3630, see omap36xx_cbp_subset for the signals */
654 _OMAP3_MUXENTRY(GPMC_A11, 0,
655 NULL, NULL, NULL, NULL,
656 NULL, NULL, NULL, NULL),
657 _OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
658 NULL, NULL, NULL, NULL,
659 NULL, NULL, NULL, NULL),
660 _OMAP3_MUXENTRY(SAD2D_MREAD, 0,
661 NULL, NULL, NULL, NULL,
662 NULL, NULL, NULL, NULL),
663 _OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
664 NULL, NULL, NULL, NULL,
665 NULL, NULL, NULL, NULL),
666 _OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
667 NULL, NULL, NULL, NULL,
668 NULL, NULL, NULL, NULL),
669 _OMAP3_MUXENTRY(SAD2D_SREAD, 0,
670 NULL, NULL, NULL, NULL,
671 NULL, NULL, NULL, NULL),
672 _OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
673 NULL, NULL, NULL, NULL,
674 NULL, NULL, NULL, NULL),
675 _OMAP3_MUXENTRY(GPMC_A11, 0,
676 NULL, NULL, NULL, NULL,
677 NULL, NULL, NULL, NULL),
678 _OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
679 NULL, NULL, NULL, NULL,
680 NULL, NULL, NULL, NULL),
681 _OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
682 NULL, NULL, NULL, NULL,
683 NULL, NULL, NULL, NULL),
684 _OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
685 NULL, NULL, NULL, NULL,
686 NULL, NULL, NULL, NULL),
687 _OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
688 NULL, NULL, NULL, NULL,
689 NULL, NULL, NULL, NULL),
690 _OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
691 NULL, NULL, NULL, NULL,
692 NULL, NULL, NULL, NULL),
693 _OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
694 NULL, NULL, NULL, NULL,
695 NULL, NULL, NULL, NULL),
696 _OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
697 NULL, NULL, NULL, NULL,
698 NULL, NULL, NULL, NULL),
652 { .reg_offset = OMAP_MUX_TERMINATOR }, 699 { .reg_offset = OMAP_MUX_TERMINATOR },
653}; 700};
654 701
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index d8c8545875b1..478ae585ca39 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -94,7 +94,8 @@ static int _update_sysc_cache(struct omap_hwmod *oh)
94 94
95 oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs); 95 oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs);
96 96
97 oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; 97 if (!(oh->sysconfig->sysc_flags & SYSC_NO_CACHE))
98 oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
98 99
99 return 0; 100 return 0;
100} 101}
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 860b755d2220..a0866268aa41 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -54,8 +54,6 @@ int omap2_pm_debug;
54 regs[reg_count++].val = \ 54 regs[reg_count++].val = \
55 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off))) 55 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
56 56
57static int __init pm_dbg_init(void);
58
59void omap2_pm_dump(int mode, int resume, unsigned int us) 57void omap2_pm_dump(int mode, int resume, unsigned int us)
60{ 58{
61 struct reg { 59 struct reg {
@@ -167,6 +165,8 @@ struct dentry *pm_dbg_dir;
167 165
168static int pm_dbg_init_done; 166static int pm_dbg_init_done;
169 167
168static int __init pm_dbg_init(void);
169
170enum { 170enum {
171 DEBUG_FILE_COUNTERS = 0, 171 DEBUG_FILE_COUNTERS = 0,
172 DEBUG_FILE_TIMERS, 172 DEBUG_FILE_TIMERS,
@@ -488,9 +488,11 @@ int pm_dbg_regset_init(int reg_set)
488 488
489static int pwrdm_suspend_get(void *data, u64 *val) 489static int pwrdm_suspend_get(void *data, u64 *val)
490{ 490{
491 *val = omap3_pm_get_suspend_state((struct powerdomain *)data); 491 int ret;
492 ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
493 *val = ret;
492 494
493 if (*val >= 0) 495 if (ret >= 0)
494 return 0; 496 return 0;
495 return *val; 497 return *val;
496} 498}
@@ -604,6 +606,4 @@ static int __init pm_dbg_init(void)
604} 606}
605arch_initcall(pm_dbg_init); 607arch_initcall(pm_dbg_init);
606 608
607#else
608void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) {}
609#endif 609#endif
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0bf345db7147..7a9c2d004511 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -32,12 +32,16 @@ extern struct omap_dm_timer *gptimer_wakeup;
32#ifdef CONFIG_PM_DEBUG 32#ifdef CONFIG_PM_DEBUG
33extern void omap2_pm_dump(int mode, int resume, unsigned int us); 33extern void omap2_pm_dump(int mode, int resume, unsigned int us);
34extern int omap2_pm_debug; 34extern int omap2_pm_debug;
35#else
36#define omap2_pm_dump(mode, resume, us) do {} while (0);
37#define omap2_pm_debug 0
38#endif
39
40#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
35extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev); 41extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
36extern int pm_dbg_regset_save(int reg_set); 42extern int pm_dbg_regset_save(int reg_set);
37extern int pm_dbg_regset_init(int reg_set); 43extern int pm_dbg_regset_init(int reg_set);
38#else 44#else
39#define omap2_pm_dump(mode, resume, us) do {} while (0);
40#define omap2_pm_debug 0
41#define pm_dbg_update_time(pwrdm, prev) do {} while (0); 45#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
42#define pm_dbg_regset_save(reg_set) do {} while (0); 46#define pm_dbg_regset_save(reg_set) do {} while (0);
43#define pm_dbg_regset_init(reg_set) do {} while (0); 47#define pm_dbg_regset_init(reg_set) do {} while (0);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c6cc809afb79..910a7acf542d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -26,6 +26,7 @@
26#include <linux/err.h> 26#include <linux/err.h>
27#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <linux/clk.h> 28#include <linux/clk.h>
29#include <linux/delay.h>
29 30
30#include <plat/sram.h> 31#include <plat/sram.h>
31#include <plat/clockdomain.h> 32#include <plat/clockdomain.h>
@@ -126,7 +127,15 @@ static void omap3_core_save_context(void)
126 /* wait for the save to complete */ 127 /* wait for the save to complete */
127 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 128 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
128 & PADCONF_SAVE_DONE)) 129 & PADCONF_SAVE_DONE))
129 ; 130 udelay(1);
131
132 /*
133 * Force write last pad into memory, as this can fail in some
134 * cases according to erratas 1.157, 1.185
135 */
136 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
137 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
138
130 /* Save the Interrupt controller context */ 139 /* Save the Interrupt controller context */
131 omap_intc_save_context(); 140 omap_intc_save_context();
132 /* Save the GPMC context */ 141 /* Save the GPMC context */
@@ -392,6 +401,7 @@ void omap_sram_idle(void)
392 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 401 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
393 omap3_enable_io_chain(); 402 omap3_enable_io_chain();
394 } 403 }
404 omap3_intc_prepare_idle();
395 405
396 /* 406 /*
397 * On EMU/HS devices ROM code restores a SRDC value 407 * On EMU/HS devices ROM code restores a SRDC value
@@ -438,6 +448,7 @@ void omap_sram_idle(void)
438 OMAP3430_GR_MOD, 448 OMAP3430_GR_MOD,
439 OMAP3_PRM_VOLTCTRL_OFFSET); 449 OMAP3_PRM_VOLTCTRL_OFFSET);
440 } 450 }
451 omap3_intc_resume_idle();
441 452
442 /* PER */ 453 /* PER */
443 if (per_next_state < PWRDM_POWER_ON) { 454 if (per_next_state < PWRDM_POWER_ON) {
@@ -578,6 +589,8 @@ static int omap3_pm_suspend(void)
578 } 589 }
579 590
580 omap_uart_prepare_suspend(); 591 omap_uart_prepare_suspend();
592 omap3_intc_suspend();
593
581 omap_sram_idle(); 594 omap_sram_idle();
582 595
583restore: 596restore:
@@ -835,6 +848,8 @@ static void __init prcm_setup_regs(void)
835 CM_AUTOIDLE); 848 CM_AUTOIDLE);
836 } 849 }
837 850
851 omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG);
852
838 /* 853 /*
839 * Set all plls to autoidle. This is needed until autoidle is 854 * Set all plls to autoidle. This is needed until autoidle is
840 * enabled by clockfw 855 * enabled by clockfw
@@ -875,15 +890,23 @@ static void __init prcm_setup_regs(void)
875 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 890 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
876 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 891 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
877 892
893 /* Enable PM_WKEN to support DSS LPR */
894 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS,
895 OMAP3430_DSS_MOD, PM_WKEN);
896
878 /* Enable wakeups in PER */ 897 /* Enable wakeups in PER */
879 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | 898 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
880 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | 899 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
881 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3, 900 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 |
901 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
902 OMAP3430_EN_MCBSP4,
882 OMAP3430_PER_MOD, PM_WKEN); 903 OMAP3430_PER_MOD, PM_WKEN);
883 /* and allow them to wake up MPU */ 904 /* and allow them to wake up MPU */
884 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | 905 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
885 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | 906 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
886 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3, 907 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 |
908 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
909 OMAP3430_EN_MCBSP4,
887 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 910 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
888 911
889 /* Don't attach IVA interrupts */ 912 /* Don't attach IVA interrupts */
@@ -904,24 +927,6 @@ static void __init prcm_setup_regs(void)
904 /* Clear any pending PRCM interrupts */ 927 /* Clear any pending PRCM interrupts */
905 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 928 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
906 929
907 /* Don't attach IVA interrupts */
908 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
909 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
910 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
911 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
912
913 /* Clear any pending 'reset' flags */
914 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
915 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
916 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
917 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
918 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
919 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
920 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
921
922 /* Clear any pending PRCM interrupts */
923 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
924
925 omap3_iva_idle(); 930 omap3_iva_idle();
926 omap3_d2d_idle(); 931 omap3_d2d_idle();
927} 932}
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 3ea8177ffb25..cf466ea1dffc 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -44,7 +44,6 @@ struct omap3_prcm_regs {
44 u32 iva2_cm_clksel2; 44 u32 iva2_cm_clksel2;
45 u32 cm_sysconfig; 45 u32 cm_sysconfig;
46 u32 sgx_cm_clksel; 46 u32 sgx_cm_clksel;
47 u32 wkup_cm_clksel;
48 u32 dss_cm_clksel; 47 u32 dss_cm_clksel;
49 u32 cam_cm_clksel; 48 u32 cam_cm_clksel;
50 u32 per_cm_clksel; 49 u32 per_cm_clksel;
@@ -53,7 +52,6 @@ struct omap3_prcm_regs {
53 u32 pll_cm_autoidle2; 52 u32 pll_cm_autoidle2;
54 u32 pll_cm_clksel4; 53 u32 pll_cm_clksel4;
55 u32 pll_cm_clksel5; 54 u32 pll_cm_clksel5;
56 u32 pll_cm_clken;
57 u32 pll_cm_clken2; 55 u32 pll_cm_clken2;
58 u32 cm_polctrl; 56 u32 cm_polctrl;
59 u32 iva2_cm_fclken; 57 u32 iva2_cm_fclken;
@@ -77,7 +75,6 @@ struct omap3_prcm_regs {
77 u32 usbhost_cm_iclken; 75 u32 usbhost_cm_iclken;
78 u32 iva2_cm_autiidle2; 76 u32 iva2_cm_autiidle2;
79 u32 mpu_cm_autoidle2; 77 u32 mpu_cm_autoidle2;
80 u32 pll_cm_autoidle;
81 u32 iva2_cm_clkstctrl; 78 u32 iva2_cm_clkstctrl;
82 u32 mpu_cm_clkstctrl; 79 u32 mpu_cm_clkstctrl;
83 u32 core_cm_clkstctrl; 80 u32 core_cm_clkstctrl;
@@ -274,7 +271,6 @@ void omap3_prcm_save_context(void)
274 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); 271 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
275 prcm_context.sgx_cm_clksel = 272 prcm_context.sgx_cm_clksel =
276 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); 273 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
277 prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
278 prcm_context.dss_cm_clksel = 274 prcm_context.dss_cm_clksel =
279 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); 275 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
280 prcm_context.cam_cm_clksel = 276 prcm_context.cam_cm_clksel =
@@ -291,8 +287,6 @@ void omap3_prcm_save_context(void)
291 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); 287 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
292 prcm_context.pll_cm_clksel5 = 288 prcm_context.pll_cm_clksel5 =
293 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); 289 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
294 prcm_context.pll_cm_clken =
295 cm_read_mod_reg(PLL_MOD, CM_CLKEN);
296 prcm_context.pll_cm_clken2 = 290 prcm_context.pll_cm_clken2 =
297 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); 291 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
298 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); 292 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
@@ -338,8 +332,6 @@ void omap3_prcm_save_context(void)
338 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 332 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
339 prcm_context.mpu_cm_autoidle2 = 333 prcm_context.mpu_cm_autoidle2 =
340 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); 334 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
341 prcm_context.pll_cm_autoidle =
342 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
343 prcm_context.iva2_cm_clkstctrl = 335 prcm_context.iva2_cm_clkstctrl =
344 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL); 336 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
345 prcm_context.mpu_cm_clkstctrl = 337 prcm_context.mpu_cm_clkstctrl =
@@ -431,7 +423,6 @@ void omap3_prcm_restore_context(void)
431 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); 423 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
432 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, 424 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
433 CM_CLKSEL); 425 CM_CLKSEL);
434 cm_write_mod_reg(prcm_context.wkup_cm_clksel, WKUP_MOD, CM_CLKSEL);
435 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD, 426 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
436 CM_CLKSEL); 427 CM_CLKSEL);
437 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD, 428 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
@@ -448,7 +439,6 @@ void omap3_prcm_restore_context(void)
448 OMAP3430ES2_CM_CLKSEL4); 439 OMAP3430ES2_CM_CLKSEL4);
449 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD, 440 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
450 OMAP3430ES2_CM_CLKSEL5); 441 OMAP3430ES2_CM_CLKSEL5);
451 cm_write_mod_reg(prcm_context.pll_cm_clken, PLL_MOD, CM_CLKEN);
452 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD, 442 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
453 OMAP3430ES2_CM_CLKEN2); 443 OMAP3430ES2_CM_CLKEN2);
454 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL); 444 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
@@ -487,7 +477,6 @@ void omap3_prcm_restore_context(void)
487 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD, 477 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
488 CM_AUTOIDLE2); 478 CM_AUTOIDLE2);
489 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); 479 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
490 cm_write_mod_reg(prcm_context.pll_cm_autoidle, PLL_MOD, CM_AUTOIDLE);
491 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, 480 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
492 CM_CLKSTCTRL); 481 CM_CLKSTCTRL);
493 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL); 482 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ea050ce188a7..40f006285163 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -24,6 +24,8 @@
24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) 24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
25#define OMAP44XX_PRM_REGADDR(module, reg) \ 25#define OMAP44XX_PRM_REGADDR(module, reg) \
26 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg)) 26 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
27#define OMAP44XX_CHIRONSS_REGADDR(module, reg) \
28 OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg))
27 29
28#include "prm44xx.h" 30#include "prm44xx.h"
29 31
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 89be97f0589d..adb2558bb121 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -386,26 +386,26 @@
386 386
387 387
388/* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */ 388/* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */
389#define OMAP4430_REVISION_PRCM OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000) 389#define OMAP4430_REVISION_PRCM OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000)
390 390
391/* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */ 391/* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */
392#define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000) 392#define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000)
393 393
394/* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */ 394/* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */
395#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000) 395#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000)
396#define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004) 396#define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004)
397#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008) 397#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008)
398#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c) 398#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c)
399#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010) 399#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010)
400#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014) 400#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014)
401#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018) 401#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018)
402 402
403/* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */ 403/* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */
404#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000) 404#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000)
405#define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004) 405#define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004)
406#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008) 406#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008)
407#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c) 407#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c)
408#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010) 408#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010)
409#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014) 409#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014)
410#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018) 410#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018)
411#endif 411#endif
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 8c964bec8159..e10a02df6e1d 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -36,7 +36,13 @@
36#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 36#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
37#define UART_OMAP_WER 0x17 /* Wake-up enable register */ 37#define UART_OMAP_WER 0x17 /* Wake-up enable register */
38 38
39#define DEFAULT_TIMEOUT (5 * HZ) 39/*
40 * NOTE: By default the serial timeout is disabled as it causes lost characters
41 * over the serial ports. This means that the UART clocks will stay on until
42 * disabled via sysfs. This also causes that any deeper omap sleep states are
43 * blocked.
44 */
45#define DEFAULT_TIMEOUT 0
40 46
41struct omap_uart_state { 47struct omap_uart_state {
42 int num; 48 int num;
@@ -422,7 +428,8 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
422 uart->timeout = DEFAULT_TIMEOUT; 428 uart->timeout = DEFAULT_TIMEOUT;
423 setup_timer(&uart->timer, omap_uart_idle_timer, 429 setup_timer(&uart->timer, omap_uart_idle_timer,
424 (unsigned long) uart); 430 (unsigned long) uart);
425 mod_timer(&uart->timer, jiffies + uart->timeout); 431 if (uart->timeout)
432 mod_timer(&uart->timer, jiffies + uart->timeout);
426 omap_uart_smart_idle_enable(uart, 0); 433 omap_uart_smart_idle_enable(uart, 0);
427 434
428 if (cpu_is_omap34xx()) { 435 if (cpu_is_omap34xx()) {
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 15268f8b61de..c3626ea48143 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -245,7 +245,8 @@ restore:
245 mov r1, #0 @ set task id for ROM code in r1 245 mov r1, #0 @ set task id for ROM code in r1
246 mov r2, #4 @ set some flags in r2, r6 246 mov r2, #4 @ set some flags in r2, r6
247 mov r6, #0xff 247 mov r6, #0xff
248 adr r3, write_aux_control_params @ r3 points to parameters 248 ldr r4, scratchpad_base
249 ldr r3, [r4, #0xBC] @ r3 points to parameters
249 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 250 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
250 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 251 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
251 .word 0xE1600071 @ call SMI monitor (smi #1) 252 .word 0xE1600071 @ call SMI monitor (smi #1)
@@ -253,14 +254,14 @@ restore:
253 b logic_l1_restore 254 b logic_l1_restore
254l2_inv_api_params: 255l2_inv_api_params:
255 .word 0x1, 0x00 256 .word 0x1, 0x00
256write_aux_control_params:
257 .word 0x1, 0x72
258l2_inv_gp: 257l2_inv_gp:
259 /* Execute smi to invalidate L2 cache */ 258 /* Execute smi to invalidate L2 cache */
260 mov r12, #0x1 @ set up to invalide L2 259 mov r12, #0x1 @ set up to invalide L2
261smi: .word 0xE1600070 @ Call SMI monitor (smieq) 260smi: .word 0xE1600070 @ Call SMI monitor (smieq)
262 /* Write to Aux control register to set some bits */ 261 /* Write to Aux control register to set some bits */
263 mov r0, #0x72 262 ldr r4, scratchpad_base
263 ldr r3, [r4,#0xBC]
264 ldr r0, [r3,#4]
264 mov r12, #0x3 265 mov r12, #0x3
265 .word 0xE1600070 @ Call SMI monitor (smieq) 266 .word 0xE1600070 @ Call SMI monitor (smieq)
266logic_l1_restore: 267logic_l1_restore:
@@ -271,6 +272,7 @@ logic_l1_restore:
271 272
272 ldr r4, scratchpad_base 273 ldr r4, scratchpad_base
273 ldr r3, [r4,#0xBC] 274 ldr r3, [r4,#0xBC]
275 adds r3, r3, #8
274 ldmia r3!, {r4-r6} 276 ldmia r3!, {r4-r6}
275 mov sp, r4 277 mov sp, r4
276 msr spsr_cxsf, r5 278 msr spsr_cxsf, r5
@@ -387,6 +389,9 @@ usettbr0:
387save_context_wfi: 389save_context_wfi:
388 /*b save_context_wfi*/ @ enable to debug save code 390 /*b save_context_wfi*/ @ enable to debug save code
389 mov r8, r0 /* Store SDRAM address in r8 */ 391 mov r8, r0 /* Store SDRAM address in r8 */
392 mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
393 mov r4, #0x1 @ Number of parameters for restore call
394 stmia r8!, {r4-r5}
390 /* Check what that target sleep state is:stored in r1*/ 395 /* Check what that target sleep state is:stored in r1*/
391 /* 1 - Only L1 and logic lost */ 396 /* 1 - Only L1 and logic lost */
392 /* 2 - Only L2 lost */ 397 /* 2 - Only L2 lost */
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index b31ca4cef365..8f159db4d08a 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/delay.h>
15#include <linux/platform_device.h> 16#include <linux/platform_device.h>
16#include <linux/pci.h> 17#include <linux/pci.h>
17#include <linux/irq.h> 18#include <linux/irq.h>
@@ -32,6 +33,7 @@
32 33
33#define DNS323_GPIO_LED_RIGHT_AMBER 1 34#define DNS323_GPIO_LED_RIGHT_AMBER 1
34#define DNS323_GPIO_LED_LEFT_AMBER 2 35#define DNS323_GPIO_LED_LEFT_AMBER 2
36#define DNS323_GPIO_SYSTEM_UP 3
35#define DNS323_GPIO_LED_POWER 5 37#define DNS323_GPIO_LED_POWER 5
36#define DNS323_GPIO_OVERTEMP 6 38#define DNS323_GPIO_OVERTEMP 6
37#define DNS323_GPIO_RTC 7 39#define DNS323_GPIO_RTC 7
@@ -239,7 +241,7 @@ static struct gpio_led dns323_leds[] = {
239 { 241 {
240 .name = "power:blue", 242 .name = "power:blue",
241 .gpio = DNS323_GPIO_LED_POWER, 243 .gpio = DNS323_GPIO_LED_POWER,
242 .active_low = 1, 244 .default_state = LEDS_GPIO_DEFSTATE_ON,
243 }, { 245 }, {
244 .name = "right:amber", 246 .name = "right:amber",
245 .gpio = DNS323_GPIO_LED_RIGHT_AMBER, 247 .gpio = DNS323_GPIO_LED_RIGHT_AMBER,
@@ -334,7 +336,7 @@ static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = {
334 { 0, MPP_UNUSED }, 336 { 0, MPP_UNUSED },
335 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ 337 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */
336 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ 338 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */
337 { 3, MPP_UNUSED }, 339 { 3, MPP_GPIO }, /* system up flag */
338 { 4, MPP_GPIO }, /* power button LED */ 340 { 4, MPP_GPIO }, /* power button LED */
339 { 5, MPP_GPIO }, /* power button LED */ 341 { 5, MPP_GPIO }, /* power button LED */
340 { 6, MPP_GPIO }, /* GMT G751-2f overtemp */ 342 { 6, MPP_GPIO }, /* GMT G751-2f overtemp */
@@ -372,13 +374,23 @@ static struct i2c_board_info __initdata dns323_i2c_devices[] = {
372 }, 374 },
373}; 375};
374 376
375/* DNS-323 specific power off method */ 377/* DNS-323 rev. A specific power off method */
376static void dns323_power_off(void) 378static void dns323a_power_off(void)
377{ 379{
378 pr_info("%s: triggering power-off...\n", __func__); 380 pr_info("%s: triggering power-off...\n", __func__);
379 gpio_set_value(DNS323_GPIO_POWER_OFF, 1); 381 gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
380} 382}
381 383
384/* DNS-323 rev B specific power off method */
385static void dns323b_power_off(void)
386{
387 pr_info("%s: triggering power-off...\n", __func__);
388 /* Pin has to be changed to 1 and back to 0 to do actual power off. */
389 gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
390 mdelay(100);
391 gpio_set_value(DNS323_GPIO_POWER_OFF, 0);
392}
393
382static void __init dns323_init(void) 394static void __init dns323_init(void)
383{ 395{
384 /* Setup basic Orion functions. Need to be called early. */ 396 /* Setup basic Orion functions. Need to be called early. */
@@ -424,11 +436,20 @@ static void __init dns323_init(void)
424 if (dns323_dev_id() == MV88F5182_DEV_ID) 436 if (dns323_dev_id() == MV88F5182_DEV_ID)
425 orion5x_sata_init(&dns323_sata_data); 437 orion5x_sata_init(&dns323_sata_data);
426 438
427 /* register dns323 specific power-off method */ 439 /* The 5182 has flag to indicate the system is up. Without this flag
440 * set, power LED will flash and cannot be controlled via leds-gpio.
441 */
442 if (dns323_dev_id() == MV88F5182_DEV_ID)
443 gpio_set_value(DNS323_GPIO_SYSTEM_UP, 1);
444
445 /* Register dns323 specific power-off method */
428 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 || 446 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
429 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0) 447 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
430 pr_err("DNS323: failed to setup power-off GPIO\n"); 448 pr_err("DNS323: failed to setup power-off GPIO\n");
431 pm_power_off = dns323_power_off; 449 if (dns323_dev_id() == MV88F5182_DEV_ID)
450 pm_power_off = dns323b_power_off;
451 else
452 pm_power_off = dns323a_power_off;
432} 453}
433 454
434/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ 455/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index 1b4ad9d5e2eb..cb0feca193d4 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -15,6 +15,9 @@
15#include <linux/mtd/physmap.h> 15#include <linux/mtd/physmap.h>
16#include <linux/mv643xx_eth.h> 16#include <linux/mv643xx_eth.h>
17#include <linux/ethtool.h> 17#include <linux/ethtool.h>
18#include <linux/leds.h>
19#include <linux/gpio_keys.h>
20#include <linux/input.h>
18#include <net/dsa.h> 21#include <net/dsa.h>
19#include <asm/mach-types.h> 22#include <asm/mach-types.h>
20#include <asm/gpio.h> 23#include <asm/gpio.h>
@@ -24,6 +27,80 @@
24#include "common.h" 27#include "common.h"
25#include "mpp.h" 28#include "mpp.h"
26 29
30/*
31 * LEDs attached to GPIO
32 */
33static struct gpio_led wrt350n_v2_led_pins[] = {
34 {
35 .name = "wrt350nv2:green:power",
36 .gpio = 0,
37 .active_low = 1,
38 }, {
39 .name = "wrt350nv2:green:security",
40 .gpio = 1,
41 .active_low = 1,
42 }, {
43 .name = "wrt350nv2:orange:power",
44 .gpio = 5,
45 .active_low = 1,
46 }, {
47 .name = "wrt350nv2:green:usb",
48 .gpio = 6,
49 .active_low = 1,
50 }, {
51 .name = "wrt350nv2:green:wireless",
52 .gpio = 7,
53 .active_low = 1,
54 },
55};
56
57static struct gpio_led_platform_data wrt350n_v2_led_data = {
58 .leds = wrt350n_v2_led_pins,
59 .num_leds = ARRAY_SIZE(wrt350n_v2_led_pins),
60};
61
62static struct platform_device wrt350n_v2_leds = {
63 .name = "leds-gpio",
64 .id = -1,
65 .dev = {
66 .platform_data = &wrt350n_v2_led_data,
67 },
68};
69
70/*
71 * Buttons attached to GPIO
72 */
73static struct gpio_keys_button wrt350n_v2_buttons[] = {
74 {
75 .code = KEY_RESTART,
76 .gpio = 3,
77 .desc = "Reset Button",
78 .active_low = 1,
79 }, {
80 .code = KEY_WLAN,
81 .gpio = 2,
82 .desc = "WPS Button",
83 .active_low = 1,
84 },
85};
86
87static struct gpio_keys_platform_data wrt350n_v2_button_data = {
88 .buttons = wrt350n_v2_buttons,
89 .nbuttons = ARRAY_SIZE(wrt350n_v2_buttons),
90};
91
92static struct platform_device wrt350n_v2_button_device = {
93 .name = "gpio-keys",
94 .id = -1,
95 .num_resources = 0,
96 .dev = {
97 .platform_data = &wrt350n_v2_button_data,
98 },
99};
100
101/*
102 * General setup
103 */
27static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = { 104static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = {
28 { 0, MPP_GPIO }, /* Power LED green (0=on) */ 105 { 0, MPP_GPIO }, /* Power LED green (0=on) */
29 { 1, MPP_GPIO }, /* Security LED (0=on) */ 106 { 1, MPP_GPIO }, /* Security LED (0=on) */
@@ -140,6 +217,8 @@ static void __init wrt350n_v2_init(void)
140 orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE, 217 orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE,
141 WRT350N_V2_NOR_BOOT_SIZE); 218 WRT350N_V2_NOR_BOOT_SIZE);
142 platform_device_register(&wrt350n_v2_nor_flash); 219 platform_device_register(&wrt350n_v2_nor_flash);
220 platform_device_register(&wrt350n_v2_leds);
221 platform_device_register(&wrt350n_v2_button_device);
143} 222}
144 223
145static int __init wrt350n_v2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 224static int __init wrt350n_v2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 74446cf8ae69..da3156d8690b 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -457,6 +457,7 @@ static struct pxaficp_platform_data corgi_ficp_platform_data = {
457 * USB Device Controller 457 * USB Device Controller
458 */ 458 */
459static struct pxa2xx_udc_mach_info udc_info __initdata = { 459static struct pxa2xx_udc_mach_info udc_info __initdata = {
460 .gpio_vbus = -1,
460 /* no connect GPIO; corgi can't tell connection status */ 461 /* no connect GPIO; corgi can't tell connection status */
461 .gpio_pullup = CORGI_GPIO_USB_PULLUP, 462 .gpio_pullup = CORGI_GPIO_USB_PULLUP,
462}; 463};
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
index b13dc0269a6d..9c787855cf24 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
@@ -169,7 +169,6 @@
169#define GPIO86_nSDCS2 MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH) 169#define GPIO86_nSDCS2 MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH)
170#define GPIO87_nSDCS3 MFP_CFG_OUT(GPIO87, AF0, DRIVE_HIGH) 170#define GPIO87_nSDCS3 MFP_CFG_OUT(GPIO87, AF0, DRIVE_HIGH)
171#define GPIO88_RDnWR MFP_CFG_OUT(GPIO88, AF0, DRIVE_HIGH) 171#define GPIO88_RDnWR MFP_CFG_OUT(GPIO88, AF0, DRIVE_HIGH)
172#define GPIO89_nACRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH)
173 172
174/* USB */ 173/* USB */
175#define GPIO9_USB_RCV MFP_CFG_IN(GPIO9, AF1) 174#define GPIO9_USB_RCV MFP_CFG_IN(GPIO9, AF1)
@@ -186,6 +185,9 @@
186#define GPIO30_ASSP_TXD MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) 185#define GPIO30_ASSP_TXD MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW)
187#define GPIO31_ASSP_SFRM_IN MFP_CFG_IN(GPIO31, AF1) 186#define GPIO31_ASSP_SFRM_IN MFP_CFG_IN(GPIO31, AF1)
188#define GPIO31_ASSP_SFRM_OUT MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) 187#define GPIO31_ASSP_SFRM_OUT MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW)
189#endif 188
189/* AC97 */
190#define GPIO89_AC97_nRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH)
191#endif /* CONFIG_CPU_PXA26x */
190 192
191#endif /* __ASM_ARCH_MFP_PXA25X_H */ 193#endif /* __ASM_ARCH_MFP_PXA25X_H */
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 6112af431fa4..1beb40f692fc 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -164,8 +164,11 @@ static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
164 saved_icmr[i] = _ICMR(irq); 164 saved_icmr[i] = _ICMR(irq);
165 _ICMR(irq) = 0; 165 _ICMR(irq) = 0;
166 } 166 }
167 for (i = 0; i < pxa_internal_irq_nr; i++) 167
168 saved_ipr[i] = IPR(i); 168 if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
169 for (i = 0; i < pxa_internal_irq_nr; i++)
170 saved_ipr[i] = IPR(i);
171 }
169 172
170 return 0; 173 return 0;
171} 174}
@@ -174,12 +177,15 @@ static int pxa_irq_resume(struct sys_device *dev)
174{ 177{
175 int i, irq = PXA_IRQ(0); 178 int i, irq = PXA_IRQ(0);
176 179
180 if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
181 for (i = 0; i < pxa_internal_irq_nr; i++)
182 IPR(i) = saved_ipr[i];
183 }
184
177 for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) { 185 for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
178 _ICMR(irq) = saved_icmr[i]; 186 _ICMR(irq) = saved_icmr[i];
179 _ICLR(irq) = 0; 187 _ICLR(irq) = 0;
180 } 188 }
181 for (i = 0; i < pxa_internal_irq_nr; i++)
182 IPR(i) = saved_ipr[i];
183 189
184 ICCR = 1; 190 ICCR = 1;
185 return 0; 191 return 0;
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index a21a4b395f73..d94857eb0690 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -334,8 +334,8 @@ static void realview_pbx_reset(char mode)
334 * in the system FPGA 334 * in the system FPGA
335 */ 335 */
336 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl); 336 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
337 __raw_writel(0x0000, reset_ctrl); 337 __raw_writel(0x00F0, reset_ctrl);
338 __raw_writel(0x0004, reset_ctrl); 338 __raw_writel(0x00F4, reset_ctrl);
339} 339}
340 340
341static void __init realview_pbx_init(void) 341static void __init realview_pbx_init(void)
diff --git a/arch/arm/mach-s3c6410/mach-hmt.c b/arch/arm/mach-s3c6410/mach-hmt.c
index cdd4b5378552..7619456f2ae8 100644
--- a/arch/arm/mach-s3c6410/mach-hmt.c
+++ b/arch/arm/mach-s3c6410/mach-hmt.c
@@ -82,7 +82,7 @@ static int hmt_bl_init(struct device *dev)
82 return ret; 82 return ret;
83} 83}
84 84
85static int hmt_bl_notify(int brightness) 85static int hmt_bl_notify(struct device *dev, int brightness)
86{ 86{
87 /* 87 /*
88 * translate from CIELUV/CIELAB L*->brightness, E.G. from 88 * translate from CIELUV/CIELAB L*->brightness, E.G. from
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 3f9cd3d8f6d5..795dc615f43b 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -41,7 +41,7 @@ ENTRY(cpu_arm7_dcache_clean_area)
41ENTRY(cpu_arm7_data_abort) 41ENTRY(cpu_arm7_data_abort)
42 mrc p15, 0, r1, c5, c0, 0 @ get FSR 42 mrc p15, 0, r1, c5, c0, 0 @ get FSR
43 mrc p15, 0, r0, c6, c0, 0 @ get FAR 43 mrc p15, 0, r0, c6, c0, 0 @ get FAR
44 ldr r8, [r0] @ read arm instruction 44 ldr r8, [r2] @ read arm instruction
45 tst r8, #1 << 20 @ L = 0 -> write? 45 tst r8, #1 << 20 @ L = 0 -> write?
46 orreq r1, r1, #1 << 11 @ yes. 46 orreq r1, r1, #1 << 11 @ yes.
47 and r7, r8, #15 << 24 47 and r7, r8, #15 << 24
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 6f21096086fd..b06954a84436 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -23,6 +23,7 @@
23#include <linux/err.h> 23#include <linux/err.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/clk.h> 25#include <linux/clk.h>
26#include <linux/debugfs.h>
26#include <mach/audmux.h> 27#include <mach/audmux.h>
27#include <mach/hardware.h> 28#include <mach/hardware.h>
28 29
@@ -32,6 +33,140 @@ static void __iomem *audmux_base;
32#define MXC_AUDMUX_V2_PTCR(x) ((x) * 8) 33#define MXC_AUDMUX_V2_PTCR(x) ((x) * 8)
33#define MXC_AUDMUX_V2_PDCR(x) ((x) * 8 + 4) 34#define MXC_AUDMUX_V2_PDCR(x) ((x) * 8 + 4)
34 35
36#ifdef CONFIG_DEBUG_FS
37static struct dentry *audmux_debugfs_root;
38
39static int audmux_open_file(struct inode *inode, struct file *file)
40{
41 file->private_data = inode->i_private;
42 return 0;
43}
44
45/* There is an annoying discontinuity in the SSI numbering with regard
46 * to the Linux number of the devices */
47static const char *audmux_port_string(int port)
48{
49 switch (port) {
50 case MX31_AUDMUX_PORT1_SSI0:
51 return "imx-ssi.0";
52 case MX31_AUDMUX_PORT2_SSI1:
53 return "imx-ssi.1";
54 case MX31_AUDMUX_PORT3_SSI_PINS_3:
55 return "SSI3";
56 case MX31_AUDMUX_PORT4_SSI_PINS_4:
57 return "SSI4";
58 case MX31_AUDMUX_PORT5_SSI_PINS_5:
59 return "SSI5";
60 case MX31_AUDMUX_PORT6_SSI_PINS_6:
61 return "SSI6";
62 default:
63 return "UNKNOWN";
64 }
65}
66
67static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
68 size_t count, loff_t *ppos)
69{
70 ssize_t ret;
71 char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
72 int port = (int)file->private_data;
73 u32 pdcr, ptcr;
74
75 if (!buf)
76 return -ENOMEM;
77
78 if (audmux_clk)
79 clk_enable(audmux_clk);
80
81 ptcr = readl(audmux_base + MXC_AUDMUX_V2_PTCR(port));
82 pdcr = readl(audmux_base + MXC_AUDMUX_V2_PDCR(port));
83
84 if (audmux_clk)
85 clk_disable(audmux_clk);
86
87 ret = snprintf(buf, PAGE_SIZE, "PDCR: %08x\nPTCR: %08x\n",
88 pdcr, ptcr);
89
90 if (ptcr & MXC_AUDMUX_V2_PTCR_TFSDIR)
91 ret += snprintf(buf + ret, PAGE_SIZE - ret,
92 "TxFS output from %s, ",
93 audmux_port_string((ptcr >> 27) & 0x7));
94 else
95 ret += snprintf(buf + ret, PAGE_SIZE - ret,
96 "TxFS input, ");
97
98 if (ptcr & MXC_AUDMUX_V2_PTCR_TCLKDIR)
99 ret += snprintf(buf + ret, PAGE_SIZE - ret,
100 "TxClk output from %s",
101 audmux_port_string((ptcr >> 22) & 0x7));
102 else
103 ret += snprintf(buf + ret, PAGE_SIZE - ret,
104 "TxClk input");
105
106 ret += snprintf(buf + ret, PAGE_SIZE - ret, "\n");
107
108 if (ptcr & MXC_AUDMUX_V2_PTCR_SYN) {
109 ret += snprintf(buf + ret, PAGE_SIZE - ret,
110 "Port is symmetric");
111 } else {
112 if (ptcr & MXC_AUDMUX_V2_PTCR_RFSDIR)
113 ret += snprintf(buf + ret, PAGE_SIZE - ret,
114 "RxFS output from %s, ",
115 audmux_port_string((ptcr >> 17) & 0x7));
116 else
117 ret += snprintf(buf + ret, PAGE_SIZE - ret,
118 "RxFS input, ");
119
120 if (ptcr & MXC_AUDMUX_V2_PTCR_RCLKDIR)
121 ret += snprintf(buf + ret, PAGE_SIZE - ret,
122 "RxClk output from %s",
123 audmux_port_string((ptcr >> 12) & 0x7));
124 else
125 ret += snprintf(buf + ret, PAGE_SIZE - ret,
126 "RxClk input");
127 }
128
129 ret += snprintf(buf + ret, PAGE_SIZE - ret,
130 "\nData received from %s\n",
131 audmux_port_string((pdcr >> 13) & 0x7));
132
133 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
134
135 kfree(buf);
136
137 return ret;
138}
139
140static const struct file_operations audmux_debugfs_fops = {
141 .open = audmux_open_file,
142 .read = audmux_read_file,
143};
144
145static void audmux_debugfs_init(void)
146{
147 int i;
148 char buf[20];
149
150 audmux_debugfs_root = debugfs_create_dir("audmux", NULL);
151 if (!audmux_debugfs_root) {
152 pr_warning("Failed to create AUDMUX debugfs root\n");
153 return;
154 }
155
156 for (i = 1; i < 8; i++) {
157 snprintf(buf, sizeof(buf), "ssi%d", i);
158 if (!debugfs_create_file(buf, 0444, audmux_debugfs_root,
159 (void *)i, &audmux_debugfs_fops))
160 pr_warning("Failed to create AUDMUX port %d debugfs file\n",
161 i);
162 }
163}
164#else
165static inline void audmux_debugfs_init(void)
166{
167}
168#endif
169
35int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr, 170int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
36 unsigned int pdcr) 171 unsigned int pdcr)
37{ 172{
@@ -68,6 +203,8 @@ static int mxc_audmux_v2_init(void)
68 if (cpu_is_mx31() || cpu_is_mx35()) 203 if (cpu_is_mx31() || cpu_is_mx35())
69 audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR); 204 audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
70 205
206 audmux_debugfs_init();
207
71 return 0; 208 return 0;
72} 209}
73 210
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 0184b638c268..2b2da0367578 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -25,7 +25,7 @@
25 25
26#ifndef __ASSEMBLY__ 26#ifndef __ASSEMBLY__
27 27
28enum mx31lilly_boards { 28enum mx31lite_boards {
29 MX31LITE_NOBOARD = 0, 29 MX31LITE_NOBOARD = 0,
30 MX31LITE_DB = 1, 30 MX31LITE_DB = 1,
31}; 31};
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 286cb9b0a25b..4bf1068ffad9 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -32,7 +32,7 @@ extern void mxc91231_init_irq(void);
32extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 32extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
33extern int mx1_clocks_init(unsigned long fref); 33extern int mx1_clocks_init(unsigned long fref);
34extern int mx21_clocks_init(unsigned long lref, unsigned long fref); 34extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
35extern int mx25_clocks_init(unsigned long fref); 35extern int mx25_clocks_init(void);
36extern int mx27_clocks_init(unsigned long fref); 36extern int mx27_clocks_init(unsigned long fref);
37extern int mx31_clocks_init(unsigned long fref); 37extern int mx31_clocks_init(unsigned long fref);
38extern int mx35_clocks_init(void); 38extern int mx35_clocks_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
index 00b0ac1db225..c88d40795f7a 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
@@ -671,7 +671,7 @@
671#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL) 671#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL)
672 672
673#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL) 673#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL)
674#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4 0, NO_PAD_CTRL) 674#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL)
675#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL) 675#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL)
676 676
677#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL) 677#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index ead9d592168d..0cb347645db4 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -37,7 +37,12 @@
37 * within sensible limits. 37 * within sensible limits.
38 */ 38 */
39#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS) 39#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
40
41#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
42#define MXC_BOARD_IRQS 80
43#else
40#define MXC_BOARD_IRQS 16 44#define MXC_BOARD_IRQS 16
45#endif
41 46
42#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) 47#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
43 48
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index d9f8c844c385..4becbdd1935c 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -391,7 +391,7 @@ static struct dentry *clk_debugfs_root;
391static int clk_debugfs_register_one(struct clk *c) 391static int clk_debugfs_register_one(struct clk *c)
392{ 392{
393 int err; 393 int err;
394 struct dentry *d, *child; 394 struct dentry *d, *child, *child_tmp;
395 struct clk *pa = c->parent; 395 struct clk *pa = c->parent;
396 char s[255]; 396 char s[255];
397 char *p = s; 397 char *p = s;
@@ -423,7 +423,7 @@ static int clk_debugfs_register_one(struct clk *c)
423 423
424err_out: 424err_out:
425 d = c->dent; 425 d = c->dent;
426 list_for_each_entry(child, &d->d_subdirs, d_u.d_child) 426 list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
427 debugfs_remove(child); 427 debugfs_remove(child);
428 debugfs_remove(c->dent); 428 debugfs_remove(c->dent);
429 return err; 429 return err;
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index bf1eaf3a27d4..dddc0273bc8b 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -172,6 +172,32 @@ unsigned long long sched_clock(void)
172 clocksource_32k.mult, clocksource_32k.shift); 172 clocksource_32k.mult, clocksource_32k.shift);
173} 173}
174 174
175/**
176 * read_persistent_clock - Return time from a persistent clock.
177 *
178 * Reads the time from a source which isn't disabled during PM, the
179 * 32k sync timer. Convert the cycles elapsed since last read into
180 * nsecs and adds to a monotonically increasing timespec.
181 */
182static struct timespec persistent_ts;
183static cycles_t cycles, last_cycles;
184void read_persistent_clock(struct timespec *ts)
185{
186 unsigned long long nsecs;
187 cycles_t delta;
188 struct timespec *tsp = &persistent_ts;
189
190 last_cycles = cycles;
191 cycles = clocksource_32k.read(&clocksource_32k);
192 delta = cycles - last_cycles;
193
194 nsecs = clocksource_cyc2ns(delta,
195 clocksource_32k.mult, clocksource_32k.shift);
196
197 timespec_add_ns(tsp, nsecs);
198 *ts = *tsp;
199}
200
175static int __init omap_init_clocksource_32k(void) 201static int __init omap_init_clocksource_32k(void)
176{ 202{
177 static char err[] __initdata = KERN_ERR 203 static char err[] __initdata = KERN_ERR
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 09d82b3c66ce..728c64204184 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1183,7 +1183,7 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
1183 } 1183 }
1184 1184
1185 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || 1185 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1186 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) { 1186 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1187 printk(KERN_ERR "omap_dma: You need to stop the DMA channels " 1187 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1188 "before unlinking\n"); 1188 "before unlinking\n");
1189 dump_stack(); 1189 dump_stack();
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 64f407ee0f4e..08ccf8922520 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -551,6 +551,19 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
551 if (l & OMAP_TIMER_CTRL_ST) { 551 if (l & OMAP_TIMER_CTRL_ST) {
552 l &= ~0x1; 552 l &= ~0x1;
553 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 553 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
554#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
555 defined(CONFIG_ARCH_OMAP4)
556 /* Readback to make sure write has completed */
557 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
558 /*
559 * Wait for functional clock period x 3.5 to make sure that
560 * timer is stopped
561 */
562 udelay(3500000 / clk_get_rate(timer->fclk) + 1);
563 /* Ack possibly pending interrupt */
564 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
565 OMAP_TIMER_INT_OVERFLOW);
566#endif
554 } 567 }
555} 568}
556EXPORT_SYMBOL_GPL(omap_dm_timer_stop); 569EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index d17620c50c28..d2422c766cca 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -750,6 +750,7 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
750} 750}
751#endif 751#endif
752 752
753#ifdef CONFIG_ARCH_OMAP1
753/* 754/*
754 * This only applies to chips that can't do both rising and falling edge 755 * This only applies to chips that can't do both rising and falling edge
755 * detection at once. For all other chips, this function is a noop. 756 * detection at once. For all other chips, this function is a noop.
@@ -760,11 +761,9 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
760 u32 l = 0; 761 u32 l = 0;
761 762
762 switch (bank->method) { 763 switch (bank->method) {
763#ifdef CONFIG_ARCH_OMAP1
764 case METHOD_MPUIO: 764 case METHOD_MPUIO:
765 reg += OMAP_MPUIO_GPIO_INT_EDGE; 765 reg += OMAP_MPUIO_GPIO_INT_EDGE;
766 break; 766 break;
767#endif
768#ifdef CONFIG_ARCH_OMAP15XX 767#ifdef CONFIG_ARCH_OMAP15XX
769 case METHOD_GPIO_1510: 768 case METHOD_GPIO_1510:
770 reg += OMAP1510_GPIO_INT_CONTROL; 769 reg += OMAP1510_GPIO_INT_CONTROL;
@@ -787,6 +786,7 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
787 786
788 __raw_writel(l, reg); 787 __raw_writel(l, reg);
789} 788}
789#endif
790 790
791static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 791static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
792{ 792{
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 9a028bdebb06..a162f585b1e3 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -434,6 +434,7 @@ IS_OMAP_TYPE(3517, 0x3517)
434#define OMAP3430_REV_ES2_1 0x34302034 434#define OMAP3430_REV_ES2_1 0x34302034
435#define OMAP3430_REV_ES3_0 0x34303034 435#define OMAP3430_REV_ES3_0 0x34303034
436#define OMAP3430_REV_ES3_1 0x34304034 436#define OMAP3430_REV_ES3_1 0x34304034
437#define OMAP3430_REV_ES3_1_2 0x34305034
437 438
438#define OMAP3630_REV_ES1_0 0x36300034 439#define OMAP3630_REV_ES1_0 0x36300034
439 440
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 97d6c50c3dcb..c0ab7c80f72e 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -499,6 +499,9 @@ extern void omap_init_irq(void);
499extern int omap_irq_pending(void); 499extern int omap_irq_pending(void);
500void omap_intc_save_context(void); 500void omap_intc_save_context(void);
501void omap_intc_restore_context(void); 501void omap_intc_restore_context(void);
502void omap3_intc_suspend(void);
503void omap3_intc_prepare_idle(void);
504void omap3_intc_resume_idle(void);
502#endif 505#endif
503 506
504#include <mach/hardware.h> 507#include <mach/hardware.h>
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 007935a921ea..33933256a226 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -227,6 +227,7 @@ struct omap_hwmod_ocp_if {
227#define SYSC_HAS_SIDLEMODE (1 << 5) 227#define SYSC_HAS_SIDLEMODE (1 << 5)
228#define SYSC_HAS_MIDLEMODE (1 << 6) 228#define SYSC_HAS_MIDLEMODE (1 << 6)
229#define SYSS_MISSING (1 << 7) 229#define SYSS_MISSING (1 << 7)
230#define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */
230 231
231/* omap_hwmod_sysconfig.clockact flags */ 232/* omap_hwmod_sysconfig.clockact flags */
232#define CLOCKACT_TEST_BOTH 0x0 233#define CLOCKACT_TEST_BOTH 0x0
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 1e5648d3e3d8..2ed72013c2e2 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -89,16 +89,6 @@
89#define USE_WAKEUP_LAT 0 89#define USE_WAKEUP_LAT 0
90#define IGNORE_WAKEUP_LAT 1 90#define IGNORE_WAKEUP_LAT 1
91 91
92/* XXX this should be moved into a separate file */
93#if defined(CONFIG_ARCH_OMAP2420)
94# define OMAP_32KSYNCT_BASE 0x48004000
95#elif defined(CONFIG_ARCH_OMAP2430)
96# define OMAP_32KSYNCT_BASE 0x49020000
97#elif defined(CONFIG_ARCH_OMAP3430)
98# define OMAP_32KSYNCT_BASE 0x48320000
99#else
100# error Unknown OMAP device
101#endif
102 92
103/* Private functions */ 93/* Private functions */
104 94
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index d41d41d78ad9..54c84a492a0f 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -133,6 +133,12 @@ static void __init orion_pcie_setup_wins(void __iomem *base,
133 } 133 }
134 134
135 /* 135 /*
136 * Round up 'size' to the nearest power of two.
137 */
138 if ((size & (size - 1)) != 0)
139 size = 1 << fls(size);
140
141 /*
136 * Setup BAR[1] to all DRAM banks. 142 * Setup BAR[1] to all DRAM banks.
137 */ 143 */
138 writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1)); 144 writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1));
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index c3a74ce24ef6..5a79fc6ee818 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
12# 12#
13# http://www.arm.linux.org.uk/developer/machines/?action=new 13# http://www.arm.linux.org.uk/developer/machines/?action=new
14# 14#
15# Last update: Wed Dec 16 20:06:34 2009 15# Last update: Thu Jan 28 22:15:54 2010
16# 16#
17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number 17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
18# 18#
@@ -2536,6 +2536,7 @@ davinci_dm6467tevm MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM 2548
2536c3ax03 MACH_C3AX03 C3AX03 2549 2536c3ax03 MACH_C3AX03 C3AX03 2549
2537mxt_td60 MACH_MXT_TD60 MXT_TD60 2550 2537mxt_td60 MACH_MXT_TD60 MXT_TD60 2550
2538esyx MACH_ESYX ESYX 2551 2538esyx MACH_ESYX ESYX 2551
2539dove_db2 MACH_DOVE_DB2 DOVE_DB2 2552
2539bulldog MACH_BULLDOG BULLDOG 2553 2540bulldog MACH_BULLDOG BULLDOG 2553
2540derell_me2000 MACH_DERELL_ME2000 DERELL_ME2000 2554 2541derell_me2000 MACH_DERELL_ME2000 DERELL_ME2000 2554
2541bcmring_base MACH_BCMRING_BASE BCMRING_BASE 2555 2542bcmring_base MACH_BCMRING_BASE BCMRING_BASE 2555
@@ -2555,6 +2556,7 @@ iseo MACH_ISEO ISEO 2568
2555cezanne MACH_CEZANNE CEZANNE 2569 2556cezanne MACH_CEZANNE CEZANNE 2569
2556lucca MACH_LUCCA LUCCA 2570 2557lucca MACH_LUCCA LUCCA 2570
2557supersmart MACH_SUPERSMART SUPERSMART 2571 2558supersmart MACH_SUPERSMART SUPERSMART 2571
2559arm11_board MACH_CS_MISANO CS_MISANO 2572
2558magnolia2 MACH_MAGNOLIA2 MAGNOLIA2 2573 2560magnolia2 MACH_MAGNOLIA2 MAGNOLIA2 2573
2559emxx MACH_EMXX EMXX 2574 2561emxx MACH_EMXX EMXX 2574
2560outlaw MACH_OUTLAW OUTLAW 2575 2562outlaw MACH_OUTLAW OUTLAW 2575
@@ -2578,3 +2580,59 @@ glacier MACH_GLACIER GLACIER 2592
2578phrazer_bulldog MACH_PHRAZER_BULLDOG PHRAZER_BULLDOG 2593 2580phrazer_bulldog MACH_PHRAZER_BULLDOG PHRAZER_BULLDOG 2593
2579omap3_bulldog MACH_OMAP3_BULLDOG OMAP3_BULLDOG 2594 2581omap3_bulldog MACH_OMAP3_BULLDOG OMAP3_BULLDOG 2594
2580pca101 MACH_PCA101 PCA101 2595 2582pca101 MACH_PCA101 PCA101 2595
2583buzzc MACH_BUZZC BUZZC 2596
2584sasie2 MACH_SASIE2 SASIE2 2597
2585davinci_cio MACH_DAVINCI_CIO DAVINCI_CIO 2598
2586smartmeter_dl MACH_SMARTMETER_DL SMARTMETER_DL 2599
2587wzl6410 MACH_WZL6410 WZL6410 2600
2588wzl6410m MACH_WZL6410M WZL6410M 2601
2589wzl6410f MACH_WZL6410F WZL6410F 2602
2590wzl6410i MACH_WZL6410I WZL6410I 2603
2591spacecom1 MACH_SPACECOM1 SPACECOM1 2604
2592pingu920 MACH_PINGU920 PINGU920 2605
2593bravoc MACH_BRAVOC BRAVOC 2606
2594cybo2440 MACH_CYBO2440 CYBO2440 2607
2595vdssw MACH_VDSSW VDSSW 2608
2596romulus MACH_ROMULUS ROMULUS 2609
2597omap_magic MACH_OMAP_MAGIC OMAP_MAGIC 2610
2598eltd100 MACH_ELTD100 ELTD100 2611
2599capc7117 MACH_CAPC7117 CAPC7117 2612
2600swan MACH_SWAN SWAN 2613
2601veu MACH_VEU VEU 2614
2602rm2 MACH_RM2 RM2 2615
2603tt2100 MACH_TT2100 TT2100 2616
2604venice MACH_VENICE VENICE 2617
2605pc7323 MACH_PC7323 PC7323 2618
2606masp MACH_MASP MASP 2619
2607fujitsu_tvstbsoc0 MACH_FUJITSU_TVSTBSOC FUJITSU_TVSTBSOC 2620
2608fujitsu_tvstbsoc1 MACH_FUJITSU_TVSTBSOC1 FUJITSU_TVSTBSOC1 2621
2609lexikon MACH_LEXIKON LEXIKON 2622
2610mini2440v2 MACH_MINI2440V2 MINI2440V2 2623
2611icontrol MACH_ICONTROL ICONTROL 2624
2612sheevad MACH_SHEEVAD SHEEVAD 2625
2613qsd8x50a_st1_1 MACH_QSD8X50A_ST1_1 QSD8X50A_ST1_1 2626
2614qsd8x50a_st1_5 MACH_QSD8X50A_ST1_5 QSD8X50A_ST1_5 2627
2615bee MACH_BEE BEE 2628
2616mx23evk MACH_MX23EVK MX23EVK 2629
2617ap4evb MACH_AP4EVB AP4EVB 2630
2618stockholm MACH_STOCKHOLM STOCKHOLM 2631
2619lpc_h3131 MACH_LPC_H3131 LPC_H3131 2632
2620stingray MACH_STINGRAY STINGRAY 2633
2621kraken MACH_KRAKEN KRAKEN 2634
2622gw2388 MACH_GW2388 GW2388 2635
2623jadecpu MACH_JADECPU JADECPU 2636
2624carlisle MACH_CARLISLE CARLISLE 2637
2625lux_sf9 MACH_LUX_SFT9 LUX_SFT9 2638
2626nemid_tb MACH_NEMID_TB NEMID_TB 2639
2627terrier MACH_TERRIER TERRIER 2640
2628turbot MACH_TURBOT TURBOT 2641
2629sanddab MACH_SANDDAB SANDDAB 2642
2630mx35_cicada MACH_MX35_CICADA MX35_CICADA 2643
2631ghi2703d MACH_GHI2703D GHI2703D 2644
2632lux_sfx9 MACH_LUX_SFX9 LUX_SFX9 2645
2633lux_sf9g MACH_LUX_SF9G LUX_SF9G 2646
2634lux_edk9 MACH_LUX_EDK9 LUX_EDK9 2647
2635hw90240 MACH_HW90240 HW90240 2648
2636dm365_leopard MACH_DM365_LEOPARD DM365_LEOPARD 2649
2637mityomapl138 MACH_MITYOMAPL138 MITYOMAPL138 2650
2638scat110 MACH_SCAT110 SCAT110 2651
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index f60a5400a25b..a63c4be99b36 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -197,10 +197,13 @@ static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_
197 } 197 }
198 198
199 /* 199 /*
200 * Update the FPSCR with the additional exception flags. 200 * If any of the status flags are set, update the FPSCR.
201 * Comparison instructions always return at least one of 201 * Comparison instructions always return at least one of
202 * these flags set. 202 * these flags set.
203 */ 203 */
204 if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
205 fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V);
206
204 fpscr |= exceptions; 207 fpscr |= exceptions;
205 208
206 fmxr(FPSCR, fpscr); 209 fmxr(FPSCR, fpscr);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 01:55:16 -0500