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authorThomas Abraham <thomas.abraham@linaro.org>2011-10-24 06:08:42 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-12-22 20:06:58 -0500
commit0cfb26e1fb9d7afe9c79a40a257808eafb2aff34 (patch)
treef79fb4267e4b0814b4cb3bfda69acda6bc3bd579 /arch/arm
parentc3310fbbeb9db6967900ed22eb3d0bd0bb0e892c (diff)
ARM: SAMSUNG: register uart clocks to clock lookup list
Samsung uart driver lookups the clock using the connection id 'clk_uart_baud'. The uart clocks for all Samsung platforms are reorganized to register them with the lookup name as required by the uart driver. Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-exynos/clock.c106
-rw-r--r--arch/arm/mach-exynos/init.c2
-rw-r--r--arch/arm/mach-s3c2410/s3c2410.c6
-rw-r--r--arch/arm/mach-s3c2412/clock.c7
-rw-r--r--arch/arm/mach-s3c2440/clock.c7
-rw-r--r--arch/arm/mach-s3c64xx/clock.c37
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c32
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c32
-rw-r--r--arch/arm/mach-s5pc100/clock.c33
-rw-r--r--arch/arm/mach-s5pv210/clock.c107
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c23
11 files changed, 266 insertions, 126 deletions
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 2894f0adef5c..fe1851914dac 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -1009,46 +1009,6 @@ static struct clksrc_clk clk_dout_mmc4 = {
1009 1009
1010static struct clksrc_clk clksrcs[] = { 1010static struct clksrc_clk clksrcs[] = {
1011 { 1011 {
1012 .clk = {
1013 .name = "uclk1",
1014 .devname = "s5pv210-uart.0",
1015 .enable = exynos4_clksrc_mask_peril0_ctrl,
1016 .ctrlbit = (1 << 0),
1017 },
1018 .sources = &clkset_group,
1019 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1020 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1021 }, {
1022 .clk = {
1023 .name = "uclk1",
1024 .devname = "s5pv210-uart.1",
1025 .enable = exynos4_clksrc_mask_peril0_ctrl,
1026 .ctrlbit = (1 << 4),
1027 },
1028 .sources = &clkset_group,
1029 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1030 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1031 }, {
1032 .clk = {
1033 .name = "uclk1",
1034 .devname = "s5pv210-uart.2",
1035 .enable = exynos4_clksrc_mask_peril0_ctrl,
1036 .ctrlbit = (1 << 8),
1037 },
1038 .sources = &clkset_group,
1039 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1040 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1041 }, {
1042 .clk = {
1043 .name = "uclk1",
1044 .devname = "s5pv210-uart.3",
1045 .enable = exynos4_clksrc_mask_peril0_ctrl,
1046 .ctrlbit = (1 << 12),
1047 },
1048 .sources = &clkset_group,
1049 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1050 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1051 }, {
1052 .clk = { 1012 .clk = {
1053 .name = "sclk_pwm", 1013 .name = "sclk_pwm",
1054 .enable = exynos4_clksrc_mask_peril0_ctrl, 1014 .enable = exynos4_clksrc_mask_peril0_ctrl,
@@ -1237,6 +1197,54 @@ static struct clksrc_clk clksrcs[] = {
1237 } 1197 }
1238}; 1198};
1239 1199
1200static struct clksrc_clk clk_sclk_uart0 = {
1201 .clk = {
1202 .name = "uclk1",
1203 .devname = "exynos4210-uart.0",
1204 .enable = exynos4_clksrc_mask_peril0_ctrl,
1205 .ctrlbit = (1 << 0),
1206 },
1207 .sources = &clkset_group,
1208 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1209 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1210};
1211
1212static struct clksrc_clk clk_sclk_uart1 = {
1213 .clk = {
1214 .name = "uclk1",
1215 .devname = "exynos4210-uart.1",
1216 .enable = exynos4_clksrc_mask_peril0_ctrl,
1217 .ctrlbit = (1 << 4),
1218 },
1219 .sources = &clkset_group,
1220 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1221 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1222};
1223
1224static struct clksrc_clk clk_sclk_uart2 = {
1225 .clk = {
1226 .name = "uclk1",
1227 .devname = "exynos4210-uart.2",
1228 .enable = exynos4_clksrc_mask_peril0_ctrl,
1229 .ctrlbit = (1 << 8),
1230 },
1231 .sources = &clkset_group,
1232 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1233 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1234};
1235
1236static struct clksrc_clk clk_sclk_uart3 = {
1237 .clk = {
1238 .name = "uclk1",
1239 .devname = "exynos4210-uart.3",
1240 .enable = exynos4_clksrc_mask_peril0_ctrl,
1241 .ctrlbit = (1 << 12),
1242 },
1243 .sources = &clkset_group,
1244 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1245 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1246};
1247
1240/* Clock initialization code */ 1248/* Clock initialization code */
1241static struct clksrc_clk *sysclks[] = { 1249static struct clksrc_clk *sysclks[] = {
1242 &clk_mout_apll, 1250 &clk_mout_apll,
@@ -1271,6 +1279,20 @@ static struct clksrc_clk *sysclks[] = {
1271 &clk_mout_mfc1, 1279 &clk_mout_mfc1,
1272}; 1280};
1273 1281
1282static struct clksrc_clk *clksrc_cdev[] = {
1283 &clk_sclk_uart0,
1284 &clk_sclk_uart1,
1285 &clk_sclk_uart2,
1286 &clk_sclk_uart3,
1287};
1288
1289static struct clk_lookup exynos4_clk_lookup[] = {
1290 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
1291 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
1292 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
1293 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
1294};
1295
1274static int xtal_rate; 1296static int xtal_rate;
1275 1297
1276static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) 1298static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
@@ -1478,11 +1500,15 @@ void __init exynos4_register_clocks(void)
1478 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) 1500 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1479 s3c_register_clksrc(sclk_tv[ptr], 1); 1501 s3c_register_clksrc(sclk_tv[ptr], 1);
1480 1502
1503 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1504 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1505
1481 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1506 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1482 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1507 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1483 1508
1484 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1509 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1485 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1510 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1511 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1486 1512
1487 register_syscore_ops(&exynos4_clock_syscore_ops); 1513 register_syscore_ops(&exynos4_clock_syscore_ops);
1488 s3c24xx_register_clock(&dummy_apb_pclk); 1514 s3c24xx_register_clock(&dummy_apb_pclk);
diff --git a/arch/arm/mach-exynos/init.c b/arch/arm/mach-exynos/init.c
index 3c9590b1703f..5b35978029be 100644
--- a/arch/arm/mach-exynos/init.c
+++ b/arch/arm/mach-exynos/init.c
@@ -23,5 +23,5 @@ void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
23 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) 23 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
24 tcfg->has_fracval = 1; 24 tcfg->has_fracval = 1;
25 25
26 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); 26 s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
27} 27}
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 3d7ebc557a72..af74927bca14 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -123,12 +123,18 @@ static struct clk s3c2410_armclk = {
123 .id = -1, 123 .id = -1,
124}; 124};
125 125
126static struct clk_lookup s3c2410_clk_lookup[] = {
127 CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
128 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
129};
130
126void __init s3c2410_init_clocks(int xtal) 131void __init s3c2410_init_clocks(int xtal)
127{ 132{
128 s3c24xx_register_baseclocks(xtal); 133 s3c24xx_register_baseclocks(xtal);
129 s3c2410_setup_clocks(); 134 s3c2410_setup_clocks();
130 s3c2410_baseclk_add(); 135 s3c2410_baseclk_add();
131 s3c24xx_register_clock(&s3c2410_armclk); 136 s3c24xx_register_clock(&s3c2410_armclk);
137 clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
132} 138}
133 139
134struct sysdev_class s3c2410_sysclass = { 140struct sysdev_class s3c2410_sysclass = {
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 140711db6c89..cd50291931f7 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -659,6 +659,12 @@ static struct clk *clks[] __initdata = {
659 &clk_armclk, 659 &clk_armclk,
660}; 660};
661 661
662static struct clk_lookup s3c2412_clk_lookup[] = {
663 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
664 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
665 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
666};
667
662int __init s3c2412_baseclk_add(void) 668int __init s3c2412_baseclk_add(void)
663{ 669{
664 unsigned long clkcon = __raw_readl(S3C2410_CLKCON); 670 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
@@ -751,6 +757,7 @@ int __init s3c2412_baseclk_add(void)
751 s3c2412_clkcon_enable(clkp, 0); 757 s3c2412_clkcon_enable(clkp, 0);
752 } 758 }
753 759
760 clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
754 s3c_pwmclk_init(); 761 s3c_pwmclk_init();
755 return 0; 762 return 0;
756} 763}
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index f85853c5d5eb..c9879af42b08 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -144,6 +144,12 @@ static struct clk s3c2440_clk_fclk_n = {
144 }, 144 },
145}; 145};
146 146
147static struct clk_lookup s3c2440_clk_lookup[] = {
148 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
149 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
150 CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
151};
152
147static int s3c2440_clk_add(struct sys_device *sysdev) 153static int s3c2440_clk_add(struct sys_device *sysdev)
148{ 154{
149 struct clk *clock_upll; 155 struct clk *clock_upll;
@@ -167,6 +173,7 @@ static int s3c2440_clk_add(struct sys_device *sysdev)
167 s3c24xx_register_clock(&s3c2440_clk_ac97); 173 s3c24xx_register_clock(&s3c2440_clk_ac97);
168 s3c24xx_register_clock(&s3c2440_clk_cam); 174 s3c24xx_register_clock(&s3c2440_clk_cam);
169 s3c24xx_register_clock(&s3c2440_clk_cam_upll); 175 s3c24xx_register_clock(&s3c2440_clk_cam_upll);
176 clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));
170 177
171 clk_disable(&s3c2440_clk_ac97); 178 clk_disable(&s3c2440_clk_ac97);
172 clk_disable(&s3c2440_clk_cam); 179 clk_disable(&s3c2440_clk_cam);
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 39c238d7a3dc..2addd988141c 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -617,16 +617,6 @@ static struct clksrc_clk clksrcs[] = {
617 .sources = &clkset_uhost, 617 .sources = &clkset_uhost,
618 }, { 618 }, {
619 .clk = { 619 .clk = {
620 .name = "uclk1",
621 .ctrlbit = S3C_CLKCON_SCLK_UART,
622 .enable = s3c64xx_sclk_ctrl,
623 },
624 .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
625 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
626 .sources = &clkset_uart,
627 }, {
628/* Where does UCLK0 come from? */
629 .clk = {
630 .name = "spi-bus", 620 .name = "spi-bus",
631 .devname = "s3c64xx-spi.0", 621 .devname = "s3c64xx-spi.0",
632 .ctrlbit = S3C_CLKCON_SCLK_SPI0, 622 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
@@ -695,6 +685,18 @@ static struct clksrc_clk clksrcs[] = {
695 }, 685 },
696}; 686};
697 687
688/* Where does UCLK0 come from? */
689static struct clksrc_clk clk_sclk_uclk = {
690 .clk = {
691 .name = "uclk1",
692 .ctrlbit = S3C_CLKCON_SCLK_UART,
693 .enable = s3c64xx_sclk_ctrl,
694 },
695 .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
696 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
697 .sources = &clkset_uart,
698};
699
698/* Clock initialisation code */ 700/* Clock initialisation code */
699 701
700static struct clksrc_clk *init_parents[] = { 702static struct clksrc_clk *init_parents[] = {
@@ -703,6 +705,15 @@ static struct clksrc_clk *init_parents[] = {
703 &clk_mout_mpll, 705 &clk_mout_mpll,
704}; 706};
705 707
708static struct clksrc_clk *clksrc_cdev[] = {
709 &clk_sclk_uclk,
710};
711
712static struct clk_lookup s3c64xx_clk_lookup[] = {
713 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
714 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
715};
716
706#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 717#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
707 718
708void __init_or_cpufreq s3c6400_setup_clocks(void) 719void __init_or_cpufreq s3c6400_setup_clocks(void)
@@ -811,6 +822,8 @@ static struct clk *clks[] __initdata = {
811void __init s3c64xx_register_clocks(unsigned long xtal, 822void __init s3c64xx_register_clocks(unsigned long xtal,
812 unsigned armclk_divlimit) 823 unsigned armclk_divlimit)
813{ 824{
825 unsigned int cnt;
826
814 armclk_mask = armclk_divlimit; 827 armclk_mask = armclk_divlimit;
815 828
816 s3c24xx_register_baseclocks(xtal); 829 s3c24xx_register_baseclocks(xtal);
@@ -823,5 +836,9 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
823 836
824 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); 837 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
825 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 838 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
839 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
840 s3c_register_clksrc(clksrc_cdev[cnt], 1);
841 clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
842
826 s3c_pwmclk_init(); 843 s3c_pwmclk_init();
827} 844}
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index c54c65d511f0..bfb1917ad0da 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -421,15 +421,6 @@ static struct clksrc_clk clksrcs[] = {
421 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, 421 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
422 }, { 422 }, {
423 .clk = { 423 .clk = {
424 .name = "uclk1",
425 .ctrlbit = (1 << 5),
426 .enable = s5p64x0_sclk_ctrl,
427 },
428 .sources = &clkset_uart,
429 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
430 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
431 }, {
432 .clk = {
433 .name = "sclk_spi", 424 .name = "sclk_spi",
434 .devname = "s3c64xx-spi.0", 425 .devname = "s3c64xx-spi.0",
435 .ctrlbit = (1 << 20), 426 .ctrlbit = (1 << 20),
@@ -487,6 +478,17 @@ static struct clksrc_clk clksrcs[] = {
487 }, 478 },
488}; 479};
489 480
481static struct clksrc_clk clk_sclk_uclk = {
482 .clk = {
483 .name = "uclk1",
484 .ctrlbit = (1 << 5),
485 .enable = s5p64x0_sclk_ctrl,
486 },
487 .sources = &clkset_uart,
488 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
489 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
490};
491
490/* Clock initialization code */ 492/* Clock initialization code */
491static struct clksrc_clk *sysclks[] = { 493static struct clksrc_clk *sysclks[] = {
492 &clk_mout_apll, 494 &clk_mout_apll,
@@ -505,6 +507,15 @@ static struct clk dummy_apb_pclk = {
505 .id = -1, 507 .id = -1,
506}; 508};
507 509
510static struct clksrc_clk *clksrc_cdev[] = {
511 &clk_sclk_uclk,
512};
513
514static struct clk_lookup s5p6440_clk_lookup[] = {
515 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
516 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
517};
518
508void __init_or_cpufreq s5p6440_setup_clocks(void) 519void __init_or_cpufreq s5p6440_setup_clocks(void)
509{ 520{
510 struct clk *xtal_clk; 521 struct clk *xtal_clk;
@@ -583,9 +594,12 @@ void __init s5p6440_register_clocks(void)
583 594
584 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 595 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
585 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 596 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
597 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
598 s3c_register_clksrc(clksrc_cdev[ptr], 1);
586 599
587 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 600 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
588 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 601 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
602 clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
589 603
590 s3c24xx_register_clock(&dummy_apb_pclk); 604 s3c24xx_register_clock(&dummy_apb_pclk);
591 605
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 2d04abfba12e..d132638c7b23 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -443,15 +443,6 @@ static struct clksrc_clk clksrcs[] = {
443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, 443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
444 }, { 444 }, {
445 .clk = { 445 .clk = {
446 .name = "uclk1",
447 .ctrlbit = (1 << 5),
448 .enable = s5p64x0_sclk_ctrl,
449 },
450 .sources = &clkset_uart,
451 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
452 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
453 }, {
454 .clk = {
455 .name = "sclk_spi", 446 .name = "sclk_spi",
456 .devname = "s3c64xx-spi.0", 447 .devname = "s3c64xx-spi.0",
457 .ctrlbit = (1 << 20), 448 .ctrlbit = (1 << 20),
@@ -536,6 +527,26 @@ static struct clksrc_clk clksrcs[] = {
536 }, 527 },
537}; 528};
538 529
530static struct clksrc_clk clk_sclk_uclk = {
531 .clk = {
532 .name = "uclk1",
533 .ctrlbit = (1 << 5),
534 .enable = s5p64x0_sclk_ctrl,
535 },
536 .sources = &clkset_uart,
537 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
538 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
539};
540
541static struct clksrc_clk *clksrc_cdev[] = {
542 &clk_sclk_uclk,
543};
544
545static struct clk_lookup s5p6450_clk_lookup[] = {
546 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
547 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
548};
549
539/* Clock initialization code */ 550/* Clock initialization code */
540static struct clksrc_clk *sysclks[] = { 551static struct clksrc_clk *sysclks[] = {
541 &clk_mout_apll, 552 &clk_mout_apll,
@@ -634,9 +645,12 @@ void __init s5p6450_register_clocks(void)
634 645
635 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 646 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
636 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 647 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
648 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
649 s3c_register_clksrc(clksrc_cdev[ptr], 1);
637 650
638 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 651 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
639 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 652 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
653 clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
640 654
641 s3c24xx_register_clock(&dummy_apb_pclk); 655 s3c24xx_register_clock(&dummy_apb_pclk);
642 656
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 8d47709da713..9d644ece2604 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -962,16 +962,6 @@ static struct clksrc_clk clksrcs[] = {
962 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 }, 962 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
963 }, { 963 }, {
964 .clk = { 964 .clk = {
965 .name = "uclk1",
966 .ctrlbit = (1 << 3),
967 .enable = s5pc100_sclk0_ctrl,
968
969 },
970 .sources = &clk_src_group2,
971 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
972 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
973 }, {
974 .clk = {
975 .name = "sclk_mixer", 965 .name = "sclk_mixer",
976 .ctrlbit = (1 << 6), 966 .ctrlbit = (1 << 6),
977 .enable = s5pc100_sclk0_ctrl, 967 .enable = s5pc100_sclk0_ctrl,
@@ -1098,6 +1088,17 @@ static struct clksrc_clk clksrcs[] = {
1098 }, 1088 },
1099}; 1089};
1100 1090
1091static struct clksrc_clk clk_sclk_uart = {
1092 .clk = {
1093 .name = "uclk1",
1094 .ctrlbit = (1 << 3),
1095 .enable = s5pc100_sclk0_ctrl,
1096 },
1097 .sources = &clk_src_group2,
1098 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
1099 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1100};
1101
1101/* Clock initialisation code */ 1102/* Clock initialisation code */
1102static struct clksrc_clk *sysclks[] = { 1103static struct clksrc_clk *sysclks[] = {
1103 &clk_mout_apll, 1104 &clk_mout_apll,
@@ -1127,6 +1128,10 @@ static struct clksrc_clk *sysclks[] = {
1127 &clk_sclk_spdif, 1128 &clk_sclk_spdif,
1128}; 1129};
1129 1130
1131static struct clksrc_clk *clksrc_cdev[] = {
1132 &clk_sclk_uart,
1133};
1134
1130void __init_or_cpufreq s5pc100_setup_clocks(void) 1135void __init_or_cpufreq s5pc100_setup_clocks(void)
1131{ 1136{
1132 unsigned long xtal; 1137 unsigned long xtal;
@@ -1266,6 +1271,11 @@ static struct clk *clks[] __initdata = {
1266 &clk_pcmcdclk1, 1271 &clk_pcmcdclk1,
1267}; 1272};
1268 1273
1274static struct clk_lookup s5pc100_clk_lookup[] = {
1275 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
1276 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
1277};
1278
1269void __init s5pc100_register_clocks(void) 1279void __init s5pc100_register_clocks(void)
1270{ 1280{
1271 int ptr; 1281 int ptr;
@@ -1277,9 +1287,12 @@ void __init s5pc100_register_clocks(void)
1277 1287
1278 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1288 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1279 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1289 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1290 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1291 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1280 1292
1281 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1293 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1282 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1294 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1295 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
1283 1296
1284 s3c24xx_register_clock(&dummy_apb_pclk); 1297 s3c24xx_register_clock(&dummy_apb_pclk);
1285 1298
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 4c5ac7a69e9e..43a045d354ec 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -809,46 +809,6 @@ static struct clksrc_clk clksrcs[] = {
809 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, 809 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
810 }, { 810 }, {
811 .clk = { 811 .clk = {
812 .name = "uclk1",
813 .devname = "s5pv210-uart.0",
814 .enable = s5pv210_clk_mask0_ctrl,
815 .ctrlbit = (1 << 12),
816 },
817 .sources = &clkset_uart,
818 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
819 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
820 }, {
821 .clk = {
822 .name = "uclk1",
823 .devname = "s5pv210-uart.1",
824 .enable = s5pv210_clk_mask0_ctrl,
825 .ctrlbit = (1 << 13),
826 },
827 .sources = &clkset_uart,
828 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
829 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
830 }, {
831 .clk = {
832 .name = "uclk1",
833 .devname = "s5pv210-uart.2",
834 .enable = s5pv210_clk_mask0_ctrl,
835 .ctrlbit = (1 << 14),
836 },
837 .sources = &clkset_uart,
838 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
839 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
840 }, {
841 .clk = {
842 .name = "uclk1",
843 .devname = "s5pv210-uart.3",
844 .enable = s5pv210_clk_mask0_ctrl,
845 .ctrlbit = (1 << 15),
846 },
847 .sources = &clkset_uart,
848 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
849 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
850 }, {
851 .clk = {
852 .name = "sclk_fimc", 812 .name = "sclk_fimc",
853 .devname = "s5pv210-fimc.0", 813 .devname = "s5pv210-fimc.0",
854 .enable = s5pv210_clk_mask1_ctrl, 814 .enable = s5pv210_clk_mask1_ctrl,
@@ -1022,6 +982,61 @@ static struct clksrc_clk clksrcs[] = {
1022 }, 982 },
1023}; 983};
1024 984
985static struct clksrc_clk clk_sclk_uart0 = {
986 .clk = {
987 .name = "uclk1",
988 .devname = "s5pv210-uart.0",
989 .enable = s5pv210_clk_mask0_ctrl,
990 .ctrlbit = (1 << 12),
991 },
992 .sources = &clkset_uart,
993 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
994 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
995};
996
997static struct clksrc_clk clk_sclk_uart1 = {
998 .clk = {
999 .name = "uclk1",
1000 .devname = "s5pv210-uart.1",
1001 .enable = s5pv210_clk_mask0_ctrl,
1002 .ctrlbit = (1 << 13),
1003 },
1004 .sources = &clkset_uart,
1005 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
1006 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
1007};
1008
1009static struct clksrc_clk clk_sclk_uart2 = {
1010 .clk = {
1011 .name = "uclk1",
1012 .devname = "s5pv210-uart.2",
1013 .enable = s5pv210_clk_mask0_ctrl,
1014 .ctrlbit = (1 << 14),
1015 },
1016 .sources = &clkset_uart,
1017 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
1018 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
1019};
1020
1021static struct clksrc_clk clk_sclk_uart3 = {
1022 .clk = {
1023 .name = "uclk1",
1024 .devname = "s5pv210-uart.3",
1025 .enable = s5pv210_clk_mask0_ctrl,
1026 .ctrlbit = (1 << 15),
1027 },
1028 .sources = &clkset_uart,
1029 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
1030 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
1031};
1032
1033static struct clksrc_clk *clksrc_cdev[] = {
1034 &clk_sclk_uart0,
1035 &clk_sclk_uart1,
1036 &clk_sclk_uart2,
1037 &clk_sclk_uart3,
1038};
1039
1025/* Clock initialisation code */ 1040/* Clock initialisation code */
1026static struct clksrc_clk *sysclks[] = { 1041static struct clksrc_clk *sysclks[] = {
1027 &clk_mout_apll, 1042 &clk_mout_apll,
@@ -1261,6 +1276,14 @@ static struct clk *clks[] __initdata = {
1261 &clk_pcmcdclk2, 1276 &clk_pcmcdclk2,
1262}; 1277};
1263 1278
1279static struct clk_lookup s5pv210_clk_lookup[] = {
1280 CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
1281 CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk),
1282 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
1283 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
1284 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
1285};
1286
1264void __init s5pv210_register_clocks(void) 1287void __init s5pv210_register_clocks(void)
1265{ 1288{
1266 int ptr; 1289 int ptr;
@@ -1273,11 +1296,15 @@ void __init s5pv210_register_clocks(void)
1273 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) 1296 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1274 s3c_register_clksrc(sclk_tv[ptr], 1); 1297 s3c_register_clksrc(sclk_tv[ptr], 1);
1275 1298
1299 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1300 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1301
1276 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1302 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1277 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1303 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1278 1304
1279 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1305 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1280 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1306 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1307 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
1281 1308
1282 s3c24xx_register_clock(&dummy_apb_pclk); 1309 s3c24xx_register_clock(&dummy_apb_pclk);
1283 s3c_pwmclk_init(); 1310 s3c_pwmclk_init();
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 5a21b15b2a97..4eab2cca2d92 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -297,13 +297,6 @@ static struct clksrc_clk clk_usb_bus_host = {
297 297
298static struct clksrc_clk clksrc_clks[] = { 298static struct clksrc_clk clksrc_clks[] = {
299 { 299 {
300 /* ART baud-rate clock sourced from esysclk via a divisor */
301 .clk = {
302 .name = "uartclk",
303 .parent = &clk_esysclk.clk,
304 },
305 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
306 }, {
307 /* camera interface bus-clock, divided down from esysclk */ 300 /* camera interface bus-clock, divided down from esysclk */
308 .clk = { 301 .clk = {
309 .name = "camif-upll", /* same as 2440 name */ 302 .name = "camif-upll", /* same as 2440 name */
@@ -323,6 +316,15 @@ static struct clksrc_clk clksrc_clks[] = {
323 }, 316 },
324}; 317};
325 318
319static struct clksrc_clk clk_esys_uart = {
320 /* ART baud-rate clock sourced from esysclk via a divisor */
321 .clk = {
322 .name = "uartclk",
323 .parent = &clk_esysclk.clk,
324 },
325 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
326};
327
326static struct clk clk_i2s_ext = { 328static struct clk clk_i2s_ext = {
327 .name = "i2s-ext", 329 .name = "i2s-ext",
328}; 330};
@@ -589,6 +591,12 @@ static struct clksrc_clk *clksrcs[] __initdata = {
589 &clk_arm, 591 &clk_arm,
590}; 592};
591 593
594static struct clk_lookup s3c2443_clk_lookup[] = {
595 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
596 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
597 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
598};
599
592void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, 600void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
593 unsigned int *divs, int nr_divs, 601 unsigned int *divs, int nr_divs,
594 int divmask) 602 int divmask)
@@ -618,6 +626,7 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
618 /* See s3c2443/etc notes on disabling clocks at init time */ 626 /* See s3c2443/etc notes on disabling clocks at init time */
619 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 627 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
620 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 628 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
629 clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
621 630
622 s3c2443_common_setup_clocks(get_mpll); 631 s3c2443_common_setup_clocks(get_mpll);
623} 632}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 17:17:02 -0500