Merge tag 'v3.9-rc1_cns3xxx_fixes' of git://git.infradead.org/users/cbou/linux-cns3xxx into fixes

From Anton Vorontsov <anton@enomsg.org>:

This tag includes Mac Lin's work to revive CNS3xxx booting:

 "Since commit 0536bdf33faf (ARM: move iotable mappings within the vmalloc
 region), [...] the pre-defined iotable mappings is not in the vmalloc
 region. [...] move the iotable mappings into the vmalloc region, and
 merge the MPCore private memory region (containing the SCU, the GIC and
 the TWD) as a single region."

Plus there is a small cosmetic fix, also from Mac Lin.

* tag 'v3.9-rc1_cns3xxx_fixes' of git://git.infradead.org/users/cbou/linux-cns3xxx:
  ARM: cns3xxx: fix mapping of private memory region

[arnd: dropped the cosmetic fix from the merge as it is not needed for 3.9]

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

2 files changed, 11 insertions, 21 deletions

diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index e698f26cc0cb..52e4bb5cf12d 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -22,19 +22,9 @@
 
 static struct map_desc cns3xxx_io_desc[] __initdata = {
         {
-                .virtual        = CNS3XXX_TC11MP_TWD_BASE_VIRT,
-                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
-                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
-                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
-                .length         = SZ_4K,
+                .virtual        = CNS3XXX_TC11MP_SCU_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE),
+                .length         = SZ_8K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = CNS3XXX_TIMER1_2_3_BASE_VIRT,
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
index 191c8e57f289..b1021aafa481 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -94,10 +94,10 @@
 #define RTC_INTR_STS_OFFSET                     0x34
 
 #define CNS3XXX_MISC_BASE                       0x76000000      /* Misc Control */
-#define CNS3XXX_MISC_BASE_VIRT                  0xFFF07000      /* Misc Control */
+#define CNS3XXX_MISC_BASE_VIRT                  0xFB000000      /* Misc Control */
 
 #define CNS3XXX_PM_BASE                         0x77000000      /* Power Management Control */
-#define CNS3XXX_PM_BASE_VIRT                    0xFFF08000
+#define CNS3XXX_PM_BASE_VIRT                    0xFB001000
 
 #define PM_CLK_GATE_OFFSET                      0x00
 #define PM_SOFT_RST_OFFSET                      0x04
@@ -109,7 +109,7 @@
 #define PM_PLL_HM_PD_OFFSET                     0x1C
 
 #define CNS3XXX_UART0_BASE                      0x78000000      /* UART 0 */
-#define CNS3XXX_UART0_BASE_VIRT                 0xFFF09000
+#define CNS3XXX_UART0_BASE_VIRT                 0xFB002000
 
 #define CNS3XXX_UART1_BASE                      0x78400000      /* UART 1 */
 #define CNS3XXX_UART1_BASE_VIRT                 0xFFF0A000
@@ -130,7 +130,7 @@
 #define CNS3XXX_I2S_BASE_VIRT                   0xFFF10000
 
 #define CNS3XXX_TIMER1_2_3_BASE                 0x7C800000      /* Timer */
-#define CNS3XXX_TIMER1_2_3_BASE_VIRT            0xFFF10800
+#define CNS3XXX_TIMER1_2_3_BASE_VIRT            0xFB003000
 
 #define TIMER1_COUNTER_OFFSET                   0x00
 #define TIMER1_AUTO_RELOAD_OFFSET               0x04
@@ -227,16 +227,16 @@
  * Testchip peripheral and fpga gic regions
  */
 #define CNS3XXX_TC11MP_SCU_BASE                 0x90000000      /* IRQ, Test chip */
-#define CNS3XXX_TC11MP_SCU_BASE_VIRT            0xFF000000
+#define CNS3XXX_TC11MP_SCU_BASE_VIRT            0xFB004000
 
 #define CNS3XXX_TC11MP_GIC_CPU_BASE             0x90000100      /* Test chip interrupt controller CPU interface */
-#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT        0xFF000100
+#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT        (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
 
 #define CNS3XXX_TC11MP_TWD_BASE                 0x90000600
-#define CNS3XXX_TC11MP_TWD_BASE_VIRT            0xFF000600
+#define CNS3XXX_TC11MP_TWD_BASE_VIRT            (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)
 
 #define CNS3XXX_TC11MP_GIC_DIST_BASE            0x90001000      /* Test chip interrupt controller distributor */
-#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT       0xFF001000
+#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT       (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
 
 #define CNS3XXX_TC11MP_L220_BASE                0x92002000      /* L220 registers */
 #define CNS3XXX_TC11MP_L220_BASE_VIRT           0xFF002000