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authorHaojian Zhuang <haojian.zhuang@gmail.com>2009-12-30 02:27:24 -0500
committerEric Miao <eric.y.miao@gmail.com>2010-01-01 02:50:34 -0500
commitdc8601a224d546bb321b058fc5ecabdb688a3582 (patch)
tree9cdb8feef2c2734abf4a2511378c64af0cac1f6b /arch/arm
parent91a86a964f0773fdf466fe02577c8494ca8e2083 (diff)
[ARM] pxa: do not enable L2 after MMU is enabled
Outer cache checked whether L2 is enabled or not. If L2 isn't enabled in XSC3, it would enable L2. This operation is evil that would make system hang. In XSC3 core document, these words are mentioned in below. "Following reset, the L2 Unified Cache Enable bit is cleared. To enable the L2 Cache, software may set the bit to a '1' before or at the same time as enabling the MMU. Enabling the L2 Cache after the MMU has been enabled or disabling the L2 Cache after the L2 Cache has been enabled, may result in unpredictable behavior of the processor." When outer cache is initialized, the MMU is already enabled. We couldn't enable L2 after MMU enabled. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mm/cache-xsc3l2.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c
index 5d180cb0bd94..c3154928bccd 100644
--- a/arch/arm/mm/cache-xsc3l2.c
+++ b/arch/arm/mm/cache-xsc3l2.c
@@ -221,15 +221,14 @@ static int __init xsc3_l2_init(void)
221 if (!cpu_is_xsc3() || !xsc3_l2_present()) 221 if (!cpu_is_xsc3() || !xsc3_l2_present())
222 return 0; 222 return 0;
223 223
224 if (!(get_cr() & CR_L2)) { 224 if (get_cr() & CR_L2) {
225 pr_info("XScale3 L2 cache enabled.\n"); 225 pr_info("XScale3 L2 cache enabled.\n");
226 adjust_cr(CR_L2, CR_L2);
227 xsc3_l2_inv_all(); 226 xsc3_l2_inv_all();
228 }
229 227
230 outer_cache.inv_range = xsc3_l2_inv_range; 228 outer_cache.inv_range = xsc3_l2_inv_range;
231 outer_cache.clean_range = xsc3_l2_clean_range; 229 outer_cache.clean_range = xsc3_l2_clean_range;
232 outer_cache.flush_range = xsc3_l2_flush_range; 230 outer_cache.flush_range = xsc3_l2_flush_range;
231 }
233 232
234 return 0; 233 return 0;
235} 234}