diff options
author | Oskar Schirmer <oskar@linutronix.de> | 2011-02-17 10:43:01 -0500 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2011-03-11 04:06:06 -0500 |
commit | cfeeb2f99867c075f3a1a6ac59c0a42e1cd741b0 (patch) | |
tree | 39628caef162160d023c08e3efd1180f62dcfe80 /arch/arm | |
parent | 25d7a6003b5c76b735fdfc3dc5030d9d9c93844e (diff) |
arm: tcc8k: Fix indent, coding syle
Remove double definition of ACLKUSBH, change parameter name in
root_clk_disable, as there is no reason to have a different name than
in root_clk_enable.
No functional change.
Signed-off-by: Oskar Schirmer <oskar@linutronix.de>
Cc: bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-tcc8k/clock.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c index a25e3fcb716f..8d8c99f89558 100644 --- a/arch/arm/mach-tcc8k/clock.c +++ b/arch/arm/mach-tcc8k/clock.c | |||
@@ -45,7 +45,6 @@ | |||
45 | #define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS) | 45 | #define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS) |
46 | #define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS) | 46 | #define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS) |
47 | #define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS) | 47 | #define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS) |
48 | #define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS) | ||
49 | #define ACLKTCT (CKC_BASE + ACLKTCT_OFFS) | 48 | #define ACLKTCT (CKC_BASE + ACLKTCT_OFFS) |
50 | #define ACLKTCX (CKC_BASE + ACLKTCX_OFFS) | 49 | #define ACLKTCX (CKC_BASE + ACLKTCX_OFFS) |
51 | #define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS) | 50 | #define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS) |
@@ -108,9 +107,9 @@ static int root_clk_enable(enum root_clks src) | |||
108 | return 0; | 107 | return 0; |
109 | } | 108 | } |
110 | 109 | ||
111 | static int root_clk_disable(enum root_clks root_src) | 110 | static int root_clk_disable(enum root_clks src) |
112 | { | 111 | { |
113 | switch (root_src) { | 112 | switch (src) { |
114 | case CLK_SRC_PLL0: return pll_enable(0, 0); | 113 | case CLK_SRC_PLL0: return pll_enable(0, 0); |
115 | case CLK_SRC_PLL1: return pll_enable(1, 0); | 114 | case CLK_SRC_PLL1: return pll_enable(1, 0); |
116 | case CLK_SRC_PLL2: return pll_enable(2, 0); | 115 | case CLK_SRC_PLL2: return pll_enable(2, 0); |
@@ -304,7 +303,7 @@ static unsigned long get_rate_sys(struct clk *clk) | |||
304 | unsigned int src; | 303 | unsigned int src; |
305 | 304 | ||
306 | src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK; | 305 | src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK; |
307 | return root_clk_get_rate(src); | 306 | return root_clk_get_rate(src); |
308 | } | 307 | } |
309 | 308 | ||
310 | static unsigned long get_rate_bus(struct clk *clk) | 309 | static unsigned long get_rate_bus(struct clk *clk) |