diff options
author | Kukjin Kim <kgene.kim@samsung.com> | 2010-02-03 19:42:13 -0500 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2010-02-23 20:52:15 -0500 |
commit | b6f837575edc5213e00903afea240f0119ee5ec9 (patch) | |
tree | d115bae68ec67a5abf8663579e192f5c8ed856a2 /arch/arm | |
parent | 5f7f6a4a0df9b43051d57fdb8ea96c083247a08f (diff) |
ARM: S5P6442: Add clock support for S5P6442
This patch adds clock support for S5P6442. This patch adds the clock
register definitions and the various system clocks in S5P6442.
Signed-off-by: Adityapratap Sharma <aditya.ps@samsung.com>
Signed-off-by: Atul Dahiya <atul.dahiya@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-s5p6442/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/mach-s5p6442/clock.c | 396 | ||||
-rw-r--r-- | arch/arm/mach-s5p6442/include/mach/pwm-clock.h | 69 | ||||
-rw-r--r-- | arch/arm/mach-s5p6442/include/mach/regs-clock.h | 103 | ||||
-rw-r--r-- | arch/arm/mach-s5p6442/include/mach/tick.h | 26 |
5 files changed, 595 insertions, 1 deletions
diff --git a/arch/arm/mach-s5p6442/Makefile b/arch/arm/mach-s5p6442/Makefile index 8a0f8ac65602..501d2510a9a2 100644 --- a/arch/arm/mach-s5p6442/Makefile +++ b/arch/arm/mach-s5p6442/Makefile | |||
@@ -12,7 +12,7 @@ obj- := | |||
12 | 12 | ||
13 | # Core support for S5P6442 system | 13 | # Core support for S5P6442 system |
14 | 14 | ||
15 | obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o | 15 | obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o |
16 | 16 | ||
17 | # machine support | 17 | # machine support |
18 | 18 | ||
diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c new file mode 100644 index 000000000000..3aadbf42c112 --- /dev/null +++ b/arch/arm/mach-s5p6442/clock.c | |||
@@ -0,0 +1,396 @@ | |||
1 | /* linux/arch/arm/mach-s5p6442/clock.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * S5P6442 - Clock support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/init.h> | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/list.h> | ||
17 | #include <linux/err.h> | ||
18 | #include <linux/clk.h> | ||
19 | #include <linux/io.h> | ||
20 | |||
21 | #include <mach/map.h> | ||
22 | |||
23 | #include <plat/cpu-freq.h> | ||
24 | #include <mach/regs-clock.h> | ||
25 | #include <plat/clock.h> | ||
26 | #include <plat/cpu.h> | ||
27 | #include <plat/pll.h> | ||
28 | #include <plat/s5p-clock.h> | ||
29 | #include <plat/clock-clksrc.h> | ||
30 | #include <plat/s5p6442.h> | ||
31 | |||
32 | static struct clksrc_clk clk_mout_apll = { | ||
33 | .clk = { | ||
34 | .name = "mout_apll", | ||
35 | .id = -1, | ||
36 | }, | ||
37 | .sources = &clk_src_apll, | ||
38 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, | ||
39 | }; | ||
40 | |||
41 | static struct clksrc_clk clk_mout_mpll = { | ||
42 | .clk = { | ||
43 | .name = "mout_mpll", | ||
44 | .id = -1, | ||
45 | }, | ||
46 | .sources = &clk_src_mpll, | ||
47 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, | ||
48 | }; | ||
49 | |||
50 | static struct clksrc_clk clk_mout_epll = { | ||
51 | .clk = { | ||
52 | .name = "mout_epll", | ||
53 | .id = -1, | ||
54 | }, | ||
55 | .sources = &clk_src_epll, | ||
56 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, | ||
57 | }; | ||
58 | |||
59 | /* Possible clock sources for ARM Mux */ | ||
60 | static struct clk *clk_src_arm_list[] = { | ||
61 | [1] = &clk_mout_apll.clk, | ||
62 | [2] = &clk_mout_mpll.clk, | ||
63 | }; | ||
64 | |||
65 | static struct clksrc_sources clk_src_arm = { | ||
66 | .sources = clk_src_arm_list, | ||
67 | .nr_sources = ARRAY_SIZE(clk_src_arm_list), | ||
68 | }; | ||
69 | |||
70 | static struct clksrc_clk clk_mout_arm = { | ||
71 | .clk = { | ||
72 | .name = "mout_arm", | ||
73 | .id = -1, | ||
74 | }, | ||
75 | .sources = &clk_src_arm, | ||
76 | .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 }, | ||
77 | }; | ||
78 | |||
79 | static struct clk clk_dout_a2m = { | ||
80 | .name = "dout_a2m", | ||
81 | .id = -1, | ||
82 | .parent = &clk_mout_apll.clk, | ||
83 | }; | ||
84 | |||
85 | /* Possible clock sources for D0 Mux */ | ||
86 | static struct clk *clk_src_d0_list[] = { | ||
87 | [1] = &clk_mout_mpll.clk, | ||
88 | [2] = &clk_dout_a2m, | ||
89 | }; | ||
90 | |||
91 | static struct clksrc_sources clk_src_d0 = { | ||
92 | .sources = clk_src_d0_list, | ||
93 | .nr_sources = ARRAY_SIZE(clk_src_d0_list), | ||
94 | }; | ||
95 | |||
96 | static struct clksrc_clk clk_mout_d0 = { | ||
97 | .clk = { | ||
98 | .name = "mout_d0", | ||
99 | .id = -1, | ||
100 | }, | ||
101 | .sources = &clk_src_d0, | ||
102 | .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 20, .size = 3 }, | ||
103 | }; | ||
104 | |||
105 | static struct clk clk_dout_apll = { | ||
106 | .name = "dout_apll", | ||
107 | .id = -1, | ||
108 | .parent = &clk_mout_arm.clk, | ||
109 | }; | ||
110 | |||
111 | /* Possible clock sources for D0SYNC Mux */ | ||
112 | static struct clk *clk_src_d0sync_list[] = { | ||
113 | [1] = &clk_mout_d0.clk, | ||
114 | [2] = &clk_dout_apll, | ||
115 | }; | ||
116 | |||
117 | static struct clksrc_sources clk_src_d0sync = { | ||
118 | .sources = clk_src_d0sync_list, | ||
119 | .nr_sources = ARRAY_SIZE(clk_src_d0sync_list), | ||
120 | }; | ||
121 | |||
122 | static struct clksrc_clk clk_mout_d0sync = { | ||
123 | .clk = { | ||
124 | .name = "mout_d0sync", | ||
125 | .id = -1, | ||
126 | }, | ||
127 | .sources = &clk_src_d0sync, | ||
128 | .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 }, | ||
129 | }; | ||
130 | |||
131 | /* Possible clock sources for D1 Mux */ | ||
132 | static struct clk *clk_src_d1_list[] = { | ||
133 | [1] = &clk_mout_mpll.clk, | ||
134 | [2] = &clk_dout_a2m, | ||
135 | }; | ||
136 | |||
137 | static struct clksrc_sources clk_src_d1 = { | ||
138 | .sources = clk_src_d1_list, | ||
139 | .nr_sources = ARRAY_SIZE(clk_src_d1_list), | ||
140 | }; | ||
141 | |||
142 | static struct clksrc_clk clk_mout_d1 = { | ||
143 | .clk = { | ||
144 | .name = "mout_d1", | ||
145 | .id = -1, | ||
146 | }, | ||
147 | .sources = &clk_src_d1, | ||
148 | .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 24, .size = 3 }, | ||
149 | }; | ||
150 | |||
151 | /* Possible clock sources for D1SYNC Mux */ | ||
152 | static struct clk *clk_src_d1sync_list[] = { | ||
153 | [1] = &clk_mout_d1.clk, | ||
154 | [2] = &clk_dout_apll, | ||
155 | }; | ||
156 | |||
157 | static struct clksrc_sources clk_src_d1sync = { | ||
158 | .sources = clk_src_d1sync_list, | ||
159 | .nr_sources = ARRAY_SIZE(clk_src_d1sync_list), | ||
160 | }; | ||
161 | |||
162 | static struct clksrc_clk clk_mout_d1sync = { | ||
163 | .clk = { | ||
164 | .name = "mout_d1sync", | ||
165 | .id = -1, | ||
166 | }, | ||
167 | .sources = &clk_src_d1sync, | ||
168 | .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 }, | ||
169 | }; | ||
170 | |||
171 | static struct clk clk_hclkd0 = { | ||
172 | .name = "hclkd0", | ||
173 | .id = -1, | ||
174 | .parent = &clk_mout_d0sync.clk, | ||
175 | }; | ||
176 | |||
177 | static struct clk clk_hclkd1 = { | ||
178 | .name = "hclkd1", | ||
179 | .id = -1, | ||
180 | .parent = &clk_mout_d1sync.clk, | ||
181 | }; | ||
182 | |||
183 | static struct clk clk_pclkd0 = { | ||
184 | .name = "pclkd0", | ||
185 | .id = -1, | ||
186 | .parent = &clk_hclkd0, | ||
187 | }; | ||
188 | |||
189 | static struct clk clk_pclkd1 = { | ||
190 | .name = "pclkd1", | ||
191 | .id = -1, | ||
192 | .parent = &clk_hclkd1, | ||
193 | }; | ||
194 | |||
195 | int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable) | ||
196 | { | ||
197 | return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); | ||
198 | } | ||
199 | |||
200 | static struct clksrc_clk clksrcs[] = { | ||
201 | { | ||
202 | .clk = { | ||
203 | .name = "dout_a2m", | ||
204 | .id = -1, | ||
205 | .parent = &clk_mout_apll.clk, | ||
206 | }, | ||
207 | .sources = &clk_src_apll, | ||
208 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, | ||
209 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, | ||
210 | }, { | ||
211 | .clk = { | ||
212 | .name = "dout_apll", | ||
213 | .id = -1, | ||
214 | .parent = &clk_mout_arm.clk, | ||
215 | }, | ||
216 | .sources = &clk_src_arm, | ||
217 | .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 }, | ||
218 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 }, | ||
219 | }, { | ||
220 | .clk = { | ||
221 | .name = "hclkd1", | ||
222 | .id = -1, | ||
223 | .parent = &clk_mout_d1sync.clk, | ||
224 | }, | ||
225 | .sources = &clk_src_d1sync, | ||
226 | .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 }, | ||
227 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 }, | ||
228 | }, { | ||
229 | .clk = { | ||
230 | .name = "hclkd0", | ||
231 | .id = -1, | ||
232 | .parent = &clk_mout_d0sync.clk, | ||
233 | }, | ||
234 | .sources = &clk_src_d0sync, | ||
235 | .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 }, | ||
236 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, | ||
237 | }, { | ||
238 | .clk = { | ||
239 | .name = "pclkd0", | ||
240 | .id = -1, | ||
241 | .parent = &clk_hclkd0, | ||
242 | }, | ||
243 | .sources = &clk_src_d0sync, | ||
244 | .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 }, | ||
245 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, | ||
246 | }, { | ||
247 | .clk = { | ||
248 | .name = "pclkd1", | ||
249 | .id = -1, | ||
250 | .parent = &clk_hclkd1, | ||
251 | }, | ||
252 | .sources = &clk_src_d1sync, | ||
253 | .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 }, | ||
254 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, | ||
255 | } | ||
256 | }; | ||
257 | |||
258 | /* Clock initialisation code */ | ||
259 | static struct clksrc_clk *init_parents[] = { | ||
260 | &clk_mout_apll, | ||
261 | &clk_mout_mpll, | ||
262 | &clk_mout_epll, | ||
263 | &clk_mout_arm, | ||
264 | &clk_mout_d0, | ||
265 | &clk_mout_d0sync, | ||
266 | &clk_mout_d1, | ||
267 | &clk_mout_d1sync, | ||
268 | }; | ||
269 | |||
270 | void __init_or_cpufreq s5p6442_setup_clocks(void) | ||
271 | { | ||
272 | struct clk *pclkd0_clk; | ||
273 | struct clk *pclkd1_clk; | ||
274 | |||
275 | unsigned long xtal; | ||
276 | unsigned long arm; | ||
277 | unsigned long hclkd0 = 0; | ||
278 | unsigned long hclkd1 = 0; | ||
279 | unsigned long pclkd0 = 0; | ||
280 | unsigned long pclkd1 = 0; | ||
281 | |||
282 | unsigned long apll; | ||
283 | unsigned long mpll; | ||
284 | unsigned long epll; | ||
285 | unsigned int ptr; | ||
286 | |||
287 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | ||
288 | |||
289 | xtal = clk_get_rate(&clk_xtal); | ||
290 | |||
291 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | ||
292 | |||
293 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); | ||
294 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); | ||
295 | epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); | ||
296 | |||
297 | printk(KERN_INFO "S5P6440: PLL settings, A=%ld, M=%ld, E=%ld", | ||
298 | apll, mpll, epll); | ||
299 | |||
300 | clk_fout_apll.rate = apll; | ||
301 | clk_fout_mpll.rate = mpll; | ||
302 | clk_fout_epll.rate = epll; | ||
303 | |||
304 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) | ||
305 | s3c_set_clksrc(init_parents[ptr], true); | ||
306 | |||
307 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | ||
308 | s3c_set_clksrc(&clksrcs[ptr], true); | ||
309 | |||
310 | arm = clk_get_rate(&clk_dout_apll); | ||
311 | hclkd0 = clk_get_rate(&clk_hclkd0); | ||
312 | hclkd1 = clk_get_rate(&clk_hclkd1); | ||
313 | |||
314 | pclkd0_clk = clk_get(NULL, "pclkd0"); | ||
315 | BUG_ON(IS_ERR(pclkd0_clk)); | ||
316 | |||
317 | pclkd0 = clk_get_rate(pclkd0_clk); | ||
318 | clk_put(pclkd0_clk); | ||
319 | |||
320 | pclkd1_clk = clk_get(NULL, "pclkd1"); | ||
321 | BUG_ON(IS_ERR(pclkd1_clk)); | ||
322 | |||
323 | pclkd1 = clk_get_rate(pclkd1_clk); | ||
324 | clk_put(pclkd1_clk); | ||
325 | |||
326 | printk(KERN_INFO "S5P6442: HCLKD0=%ld, HCLKD1=%ld, PCLKD0=%ld, PCLKD1=%ld\n", | ||
327 | hclkd0, hclkd1, pclkd0, pclkd1); | ||
328 | |||
329 | /* For backward compatibility */ | ||
330 | clk_f.rate = arm; | ||
331 | clk_h.rate = hclkd1; | ||
332 | clk_p.rate = pclkd1; | ||
333 | |||
334 | clk_pclkd0.rate = pclkd0; | ||
335 | clk_pclkd1.rate = pclkd1; | ||
336 | } | ||
337 | |||
338 | static struct clk init_clocks[] = { | ||
339 | { | ||
340 | .name = "systimer", | ||
341 | .id = -1, | ||
342 | .parent = &clk_pclkd1, | ||
343 | .enable = s5p6442_clk_ip3_ctrl, | ||
344 | .ctrlbit = (1<<16), | ||
345 | }, { | ||
346 | .name = "uart", | ||
347 | .id = 0, | ||
348 | .parent = &clk_pclkd1, | ||
349 | .enable = s5p6442_clk_ip3_ctrl, | ||
350 | .ctrlbit = (1<<17), | ||
351 | }, { | ||
352 | .name = "uart", | ||
353 | .id = 1, | ||
354 | .parent = &clk_pclkd1, | ||
355 | .enable = s5p6442_clk_ip3_ctrl, | ||
356 | .ctrlbit = (1<<18), | ||
357 | }, { | ||
358 | .name = "uart", | ||
359 | .id = 2, | ||
360 | .parent = &clk_pclkd1, | ||
361 | .enable = s5p6442_clk_ip3_ctrl, | ||
362 | .ctrlbit = (1<<19), | ||
363 | }, { | ||
364 | .name = "timers", | ||
365 | .id = -1, | ||
366 | .parent = &clk_pclkd1, | ||
367 | .enable = s5p6442_clk_ip3_ctrl, | ||
368 | .ctrlbit = (1<<23), | ||
369 | }, | ||
370 | }; | ||
371 | |||
372 | static struct clk *clks[] __initdata = { | ||
373 | &clk_ext, | ||
374 | &clk_epll, | ||
375 | &clk_mout_apll.clk, | ||
376 | &clk_mout_mpll.clk, | ||
377 | &clk_mout_epll.clk, | ||
378 | &clk_mout_d0.clk, | ||
379 | &clk_mout_d0sync.clk, | ||
380 | &clk_mout_d1.clk, | ||
381 | &clk_mout_d1sync.clk, | ||
382 | &clk_hclkd0, | ||
383 | &clk_pclkd0, | ||
384 | &clk_hclkd1, | ||
385 | &clk_pclkd1, | ||
386 | }; | ||
387 | |||
388 | void __init s5p6442_register_clocks(void) | ||
389 | { | ||
390 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | ||
391 | |||
392 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | ||
393 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | ||
394 | |||
395 | s3c_pwmclk_init(); | ||
396 | } | ||
diff --git a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h new file mode 100644 index 000000000000..15e8525da0f1 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h | |||
@@ -0,0 +1,69 @@ | |||
1 | /* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * Copyright 2010 Samsung Electronics Co., Ltd. | ||
8 | * http://www.samsung.com/ | ||
9 | * | ||
10 | * Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h | ||
11 | * | ||
12 | * S5P6442 - pwm clock and timer support | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify | ||
15 | * it under the terms of the GNU General Public License version 2 as | ||
16 | * published by the Free Software Foundation. | ||
17 | */ | ||
18 | |||
19 | #ifndef __ASM_ARCH_PWMCLK_H | ||
20 | #define __ASM_ARCH_PWMCLK_H __FILE__ | ||
21 | |||
22 | /** | ||
23 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk | ||
24 | * @cfg: The timer TCFG1 register bits shifted down to 0. | ||
25 | * | ||
26 | * Return true if the given configuration from TCFG1 is a TCLK instead | ||
27 | * any of the TDIV clocks. | ||
28 | */ | ||
29 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | ||
30 | { | ||
31 | return tcfg == S3C2410_TCFG1_MUX_TCLK; | ||
32 | } | ||
33 | |||
34 | /** | ||
35 | * tcfg_to_divisor() - convert tcfg1 setting to a divisor | ||
36 | * @tcfg1: The tcfg1 setting, shifted down. | ||
37 | * | ||
38 | * Get the divisor value for the given tcfg1 setting. We assume the | ||
39 | * caller has already checked to see if this is not a TCLK source. | ||
40 | */ | ||
41 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | ||
42 | { | ||
43 | return 1 << (1 + tcfg1); | ||
44 | } | ||
45 | |||
46 | /** | ||
47 | * pwm_tdiv_has_div1() - does the tdiv setting have a /1 | ||
48 | * | ||
49 | * Return true if we have a /1 in the tdiv setting. | ||
50 | */ | ||
51 | static inline unsigned int pwm_tdiv_has_div1(void) | ||
52 | { | ||
53 | return 0; | ||
54 | } | ||
55 | |||
56 | /** | ||
57 | * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. | ||
58 | * @div: The divisor to calculate the bit information for. | ||
59 | * | ||
60 | * Turn a divisor into the necessary bit field for TCFG1. | ||
61 | */ | ||
62 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) | ||
63 | { | ||
64 | return ilog2(div) - 1; | ||
65 | } | ||
66 | |||
67 | #define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK | ||
68 | |||
69 | #endif /* __ASM_ARCH_PWMCLK_H */ | ||
diff --git a/arch/arm/mach-s5p6442/include/mach/regs-clock.h b/arch/arm/mach-s5p6442/include/mach/regs-clock.h new file mode 100644 index 000000000000..d8360b5d4ece --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/regs-clock.h | |||
@@ -0,0 +1,103 @@ | |||
1 | /* linux/arch/arm/mach-s5p6442/include/mach/regs-clock.h | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * S5P6442 - Clock register definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_CLOCK_H | ||
14 | #define __ASM_ARCH_REGS_CLOCK_H __FILE__ | ||
15 | |||
16 | #include <mach/map.h> | ||
17 | |||
18 | #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) | ||
19 | |||
20 | #define S5P_APLL_LOCK S5P_CLKREG(0x00) | ||
21 | #define S5P_MPLL_LOCK S5P_CLKREG(0x08) | ||
22 | #define S5P_EPLL_LOCK S5P_CLKREG(0x10) | ||
23 | #define S5P_VPLL_LOCK S5P_CLKREG(0x20) | ||
24 | |||
25 | #define S5P_APLL_CON S5P_CLKREG(0x100) | ||
26 | #define S5P_MPLL_CON S5P_CLKREG(0x108) | ||
27 | #define S5P_EPLL_CON S5P_CLKREG(0x110) | ||
28 | #define S5P_VPLL_CON S5P_CLKREG(0x120) | ||
29 | |||
30 | #define S5P_CLK_SRC0 S5P_CLKREG(0x200) | ||
31 | #define S5P_CLK_SRC1 S5P_CLKREG(0x204) | ||
32 | #define S5P_CLK_SRC2 S5P_CLKREG(0x208) | ||
33 | #define S5P_CLK_SRC3 S5P_CLKREG(0x20C) | ||
34 | #define S5P_CLK_SRC4 S5P_CLKREG(0x210) | ||
35 | #define S5P_CLK_SRC5 S5P_CLKREG(0x214) | ||
36 | #define S5P_CLK_SRC6 S5P_CLKREG(0x218) | ||
37 | |||
38 | #define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280) | ||
39 | #define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284) | ||
40 | |||
41 | #define S5P_CLK_DIV0 S5P_CLKREG(0x300) | ||
42 | #define S5P_CLK_DIV1 S5P_CLKREG(0x304) | ||
43 | #define S5P_CLK_DIV2 S5P_CLKREG(0x308) | ||
44 | #define S5P_CLK_DIV3 S5P_CLKREG(0x30C) | ||
45 | #define S5P_CLK_DIV4 S5P_CLKREG(0x310) | ||
46 | #define S5P_CLK_DIV5 S5P_CLKREG(0x314) | ||
47 | #define S5P_CLK_DIV6 S5P_CLKREG(0x318) | ||
48 | |||
49 | #define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C) | ||
50 | |||
51 | /* CLK_OUT */ | ||
52 | #define S5P_CLK_OUT_SHIFT (12) | ||
53 | #define S5P_CLK_OUT_MASK (0x1F << S5P_CLK_OUT_SHIFT) | ||
54 | #define S5P_CLK_OUT S5P_CLKREG(0x500) | ||
55 | |||
56 | #define S5P_CLK_DIV_STAT0 S5P_CLKREG(0x1000) | ||
57 | #define S5P_CLK_DIV_STAT1 S5P_CLKREG(0x1004) | ||
58 | |||
59 | #define S5P_CLK_MUX_STAT0 S5P_CLKREG(0x1100) | ||
60 | #define S5P_CLK_MUX_STAT1 S5P_CLKREG(0x1104) | ||
61 | |||
62 | #define S5P_MDNIE_SEL S5P_CLKREG(0x7008) | ||
63 | |||
64 | /* Register Bit definition */ | ||
65 | #define S5P_EPLL_EN (1<<31) | ||
66 | #define S5P_EPLL_MASK 0xffffffff | ||
67 | #define S5P_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) | ||
68 | |||
69 | /* CLKDIV0 */ | ||
70 | #define S5P_CLKDIV0_APLL_SHIFT (0) | ||
71 | #define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT) | ||
72 | #define S5P_CLKDIV0_A2M_SHIFT (4) | ||
73 | #define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT) | ||
74 | #define S5P_CLKDIV0_D0CLK_SHIFT (16) | ||
75 | #define S5P_CLKDIV0_D0CLK_MASK (0xF << S5P_CLKDIV0_D0CLK_SHIFT) | ||
76 | #define S5P_CLKDIV0_P0CLK_SHIFT (20) | ||
77 | #define S5P_CLKDIV0_P0CLK_MASK (0x7 << S5P_CLKDIV0_P0CLK_SHIFT) | ||
78 | #define S5P_CLKDIV0_D1CLK_SHIFT (24) | ||
79 | #define S5P_CLKDIV0_D1CLK_MASK (0xF << S5P_CLKDIV0_D1CLK_SHIFT) | ||
80 | #define S5P_CLKDIV0_P1CLK_SHIFT (28) | ||
81 | #define S5P_CLKDIV0_P1CLK_MASK (0x7 << S5P_CLKDIV0_P1CLK_SHIFT) | ||
82 | |||
83 | /* Clock MUX status Registers */ | ||
84 | #define S5P_CLK_MUX_STAT0_APLL_SHIFT (0) | ||
85 | #define S5P_CLK_MUX_STAT0_APLL_MASK (0x7 << S5P_CLK_MUX_STAT0_APLL_SHIFT) | ||
86 | #define S5P_CLK_MUX_STAT0_MPLL_SHIFT (4) | ||
87 | #define S5P_CLK_MUX_STAT0_MPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_MPLL_SHIFT) | ||
88 | #define S5P_CLK_MUX_STAT0_EPLL_SHIFT (8) | ||
89 | #define S5P_CLK_MUX_STAT0_EPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_EPLL_SHIFT) | ||
90 | #define S5P_CLK_MUX_STAT0_VPLL_SHIFT (12) | ||
91 | #define S5P_CLK_MUX_STAT0_VPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_VPLL_SHIFT) | ||
92 | #define S5P_CLK_MUX_STAT0_MUXARM_SHIFT (16) | ||
93 | #define S5P_CLK_MUX_STAT0_MUXARM_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXARM_SHIFT) | ||
94 | #define S5P_CLK_MUX_STAT0_MUXD0_SHIFT (20) | ||
95 | #define S5P_CLK_MUX_STAT0_MUXD0_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD0_SHIFT) | ||
96 | #define S5P_CLK_MUX_STAT0_MUXD1_SHIFT (24) | ||
97 | #define S5P_CLK_MUX_STAT0_MUXD1_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD1_SHIFT) | ||
98 | #define S5P_CLK_MUX_STAT1_D1SYNC_SHIFT (24) | ||
99 | #define S5P_CLK_MUX_STAT1_D1SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D1SYNC_SHIFT) | ||
100 | #define S5P_CLK_MUX_STAT1_D0SYNC_SHIFT (28) | ||
101 | #define S5P_CLK_MUX_STAT1_D0SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D0SYNC_SHIFT) | ||
102 | |||
103 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ | ||
diff --git a/arch/arm/mach-s5p6442/include/mach/tick.h b/arch/arm/mach-s5p6442/include/mach/tick.h new file mode 100644 index 000000000000..e1d4cabf8297 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/tick.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /* linux/arch/arm/mach-s5p6442/include/mach/tick.h | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * Based on arch/arm/mach-s3c6400/include/mach/tick.h | ||
7 | * | ||
8 | * S5P6442 - Timer tick support definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_TICK_H | ||
16 | #define __ASM_ARCH_TICK_H __FILE__ | ||
17 | |||
18 | static inline u32 s3c24xx_ostimer_pending(void) | ||
19 | { | ||
20 | u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); | ||
21 | return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); | ||
22 | } | ||
23 | |||
24 | #define TICK_MAX (0xffffffff) | ||
25 | |||
26 | #endif /* __ASM_ARCH_TICK_H */ | ||