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authorMarc Zyngier <marc.zyngier@arm.com>2014-04-24 09:11:48 -0400
committerChristoffer Dall <christoffer.dall@linaro.org>2014-07-11 07:57:45 -0400
commita9866ba0cddfc497335fa02a175c4578b96722ff (patch)
treee5eeca5f3808ae9ba830a4b2fc8fd185cc26a552 /arch/arm64
parent72564016aae45f42e488f926bc803f9a2e1c771c (diff)
arm64: KVM: use separate tables for AArch32 32 and 64bit traps
An interesting "feature" of the CP14 encoding is that there is an overlap between 32 and 64bit registers, meaning they cannot live in the same table as we did for CP15. Create separate tables for 64bit CP14 and CP15 registers, and let the top level handler use the right one. Reviewed-by: Anup Patel <anup.patel@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/kvm/sys_regs.c13
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 266afd972ad3..499a351fd1b9 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -498,13 +498,16 @@ static const struct sys_reg_desc sys_reg_descs[] = {
498static const struct sys_reg_desc cp14_regs[] = { 498static const struct sys_reg_desc cp14_regs[] = {
499}; 499};
500 500
501/* Trapped cp14 64bit registers */
502static const struct sys_reg_desc cp14_64_regs[] = {
503};
504
501/* 505/*
502 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 506 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
503 * depending on the way they are accessed (as a 32bit or a 64bit 507 * depending on the way they are accessed (as a 32bit or a 64bit
504 * register). 508 * register).
505 */ 509 */
506static const struct sys_reg_desc cp15_regs[] = { 510static const struct sys_reg_desc cp15_regs[] = {
507 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
508 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_sctlr, NULL, c1_SCTLR }, 511 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_sctlr, NULL, c1_SCTLR },
509 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, 512 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
510 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 }, 513 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
@@ -545,6 +548,10 @@ static const struct sys_reg_desc cp15_regs[] = {
545 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 }, 548 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
546 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID }, 549 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
547 550
551};
552
553static const struct sys_reg_desc cp15_64_regs[] = {
554 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
548 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 }, 555 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
549}; 556};
550 557
@@ -770,7 +777,7 @@ int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
770 777
771 target_specific = get_target_table(vcpu->arch.target, false, &num); 778 target_specific = get_target_table(vcpu->arch.target, false, &num);
772 return kvm_handle_cp_64(vcpu, 779 return kvm_handle_cp_64(vcpu,
773 cp15_regs, ARRAY_SIZE(cp15_regs), 780 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
774 target_specific, num); 781 target_specific, num);
775} 782}
776 783
@@ -788,7 +795,7 @@ int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
788int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run) 795int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
789{ 796{
790 return kvm_handle_cp_64(vcpu, 797 return kvm_handle_cp_64(vcpu,
791 cp14_regs, ARRAY_SIZE(cp14_regs), 798 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
792 NULL, 0); 799 NULL, 0);
793} 800}
794 801