Merge tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64

Pull ARM64 update from Catalin Marinas:
 - User tagged pointers support (top 8-bit of user pointers
   automatically ignored by the CPU).
 - Kernel mode NEON (no users for arm64 yet but work in progress).
 - arm64 kernel Image header extended to accommodate future EFI stub.
 - Remove BogoMIPS reporting (not relevant, it's just the timer
   frequency).
 - Clean-up (EM_AARCH64/EM_ARM to elf-em.h, ELF notes in read-only
   segment, unused variable).
 - Bug-fixes (RAM boundaries not 2MB aligned, perf, includes).

* tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64:
  Documentation/arm64: clarify requirements for DTB placement
  arm64: mm: permit use of tagged pointers at EL0
  Move the EM_ARM and EM_AARCH64 definitions to uapi/linux/elf-em.h
  arm64: Remove unused cpu_name ascii in arch/arm64/mm/proc.S
  arm64: delay: don't bother reporting bogomips in /proc/cpuinfo
  arm64: Fix mapping of memory banks not ending on a PMD_SIZE boundary
  arm64: move elf notes into readonly segment
  arm64: Enable interrupts in the EL0 undef handler
  arm64: Expand arm64 image header
  ARM64: include: asm: include "asm/types.h" in "pgtable-2level-types.h" and "pgtable-3level-types.h"
  arm64: add support for kernel mode NEON
  arm64: perf: fix ARMv8 EVTYPE_MASK to include NSH bit
  arm64: perf: fix group validation when using enable_on_exec

15 files changed, 90 insertions, 22 deletions

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 9737e97f9f38..ae323a45c28c 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -96,6 +96,9 @@ config SWIOTLB
 config IOMMU_HELPER
         def_bool SWIOTLB
 
+config KERNEL_MODE_NEON
+        def_bool y
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
index fe32c0e4ac01..e7fa87f9201b 100644
--- a/arch/arm64/include/asm/elf.h
+++ b/arch/arm64/include/asm/elf.h
@@ -33,8 +33,6 @@ typedef unsigned long elf_greg_t;
 typedef elf_greg_t elf_gregset_t[ELF_NGREG];
 typedef struct user_fpsimd_state elf_fpregset_t;
 
-#define EM_AARCH64              183
-
 /*
  * AArch64 static relocation types.
  */
@@ -151,7 +149,6 @@ extern unsigned long arch_randomize_brk(struct mm_struct *mm);
 #define arch_randomize_brk arch_randomize_brk
 
 #ifdef CONFIG_COMPAT
-#define EM_ARM                          40
 #define COMPAT_ELF_PLATFORM             ("v8l")
 
 #define COMPAT_ELF_ET_DYN_BASE          (randomize_et_dyn(2 * TASK_SIZE_32 / 3))
diff --git a/arch/arm64/include/asm/neon.h b/arch/arm64/include/asm/neon.h
new file mode 100644
index 000000000000..b0cc58a97780
--- /dev/null
+++ b/arch/arm64/include/asm/neon.h
@@ -0,0 +1,14 @@
+/*
+ * linux/arch/arm64/include/asm/neon.h
+ *
+ * Copyright (C) 2013 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define cpu_has_neon()          (1)
+
+void kernel_neon_begin(void);
+void kernel_neon_end(void);
diff --git a/arch/arm64/include/asm/pgtable-2level-types.h b/arch/arm64/include/asm/pgtable-2level-types.h
index 3c3ca7d361e4..5f101e63dfc1 100644
--- a/arch/arm64/include/asm/pgtable-2level-types.h
+++ b/arch/arm64/include/asm/pgtable-2level-types.h
@@ -16,6 +16,8 @@
 #ifndef __ASM_PGTABLE_2LEVEL_TYPES_H
 #define __ASM_PGTABLE_2LEVEL_TYPES_H
 
+#include <asm/types.h>
+
 typedef u64 pteval_t;
 typedef u64 pgdval_t;
 typedef pgdval_t pmdval_t;
diff --git a/arch/arm64/include/asm/pgtable-3level-types.h b/arch/arm64/include/asm/pgtable-3level-types.h
index 4489615f14a9..4e94424938a4 100644
--- a/arch/arm64/include/asm/pgtable-3level-types.h
+++ b/arch/arm64/include/asm/pgtable-3level-types.h
@@ -16,6 +16,8 @@
 #ifndef __ASM_PGTABLE_3LEVEL_TYPES_H
 #define __ASM_PGTABLE_3LEVEL_TYPES_H
 
+#include <asm/types.h>
+
 typedef u64 pteval_t;
 typedef u64 pmdval_t;
 typedef u64 pgdval_t;
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index e182a356c979..d57e66845c86 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -122,5 +122,6 @@
 #define TCR_TG1_64K             (UL(1) << 30)
 #define TCR_IPS_40BIT           (UL(2) << 32)
 #define TCR_ASID16              (UL(1) << 36)
+#define TCR_TBI0                (UL(1) << 37)
 
 #endif
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 6ad781b21c08..3881fd115ebb 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -423,6 +423,7 @@ el0_da:
          * Data abort handling
          */
         mrs     x0, far_el1
+        bic     x0, x0, #(0xff << 56)
         disable_step x1
         isb
         enable_dbg
@@ -476,6 +477,8 @@ el0_undef:
          * Undefined instruction
          */
         mov     x0, sp
+        // enable interrupts before calling the main handler
+        enable_irq
         b       do_undefinstr
 el0_dbg:
         /*
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index e8b8357aedb4..1f2e4d5a5c0f 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/signal.h>
+#include <linux/hardirq.h>
 
 #include <asm/fpsimd.h>
 #include <asm/cputype.h>
@@ -83,6 +84,33 @@ void fpsimd_flush_thread(void)
         fpsimd_load_state(&current->thread.fpsimd_state);
 }
 
+#ifdef CONFIG_KERNEL_MODE_NEON
+
+/*
+ * Kernel-side NEON support functions
+ */
+void kernel_neon_begin(void)
+{
+        /* Avoid using the NEON in interrupt context */
+        BUG_ON(in_interrupt());
+        preempt_disable();
+
+        if (current->mm)
+                fpsimd_save_state(&current->thread.fpsimd_state);
+}
+EXPORT_SYMBOL(kernel_neon_begin);
+
+void kernel_neon_end(void)
+{
+        if (current->mm)
+                fpsimd_load_state(&current->thread.fpsimd_state);
+
+        preempt_enable();
+}
+EXPORT_SYMBOL(kernel_neon_end);
+
+#endif /* CONFIG_KERNEL_MODE_NEON */
+
 /*
  * FP/SIMD support code initialisation.
  */
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 53dcae49e729..7090c126797c 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -112,6 +112,14 @@
         .quad   TEXT_OFFSET                     // Image load offset from start of RAM
         .quad   0                               // reserved
         .quad   0                               // reserved
+        .quad   0                               // reserved
+        .quad   0                               // reserved
+        .quad   0                               // reserved
+        .byte   0x41                            // Magic number, "ARM\x64"
+        .byte   0x52
+        .byte   0x4d
+        .byte   0x64
+        .word   0                               // reserved
 
 ENTRY(stext)
         mov     x21, x0                         // x21=FDT
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 12e6ccb88691..cea1594ff933 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -325,7 +325,10 @@ validate_event(struct pmu_hw_events *hw_events,
         if (is_software_event(event))
                 return 1;
 
-        if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
+        if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)
+                return 1;
+
+        if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
                 return 1;
 
         return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
@@ -781,7 +784,7 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 /*
  * PMXEVTYPER: Event selection reg
  */
-#define ARMV8_EVTYPE_MASK       0xc00000ff      /* Mask for writable bits */
+#define ARMV8_EVTYPE_MASK       0xc80000ff      /* Mask for writable bits */
 #define ARMV8_EVTYPE_EVENT      0xff            /* Mask for EVENT bits */
 
 /*
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index add6ea616843..bca4c1c2052a 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -328,9 +328,6 @@ static int c_show(struct seq_file *m, void *v)
 #ifdef CONFIG_SMP
                 seq_printf(m, "processor\t: %d\n", i);
 #endif
-                seq_printf(m, "BogoMIPS\t: %lu.%02lu\n\n",
-                           loops_per_jiffy / (500000UL/HZ),
-                           loops_per_jiffy / (5000UL/HZ) % 100);
         }
 
         /* dump out the processor features */
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index fee5cce83450..78db90dcc910 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -223,11 +223,7 @@ asmlinkage void secondary_start_kernel(void)
 
 void __init smp_cpus_done(unsigned int max_cpus)
 {
-        unsigned long bogosum = loops_per_jiffy * num_online_cpus();
-
-        pr_info("SMP: Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
-                num_online_cpus(), bogosum / (500000/HZ),
-                (bogosum / (5000/HZ)) % 100);
+        pr_info("SMP: Total of %d processors activated.\n", num_online_cpus());
 }
 
 void __init smp_prepare_boot_cpu(void)
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index f5e55747242f..f8ab9d8e2ea3 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -71,6 +71,7 @@ SECTIONS
 
         RO_DATA(PAGE_SIZE)
         EXCEPTION_TABLE(8)
+        NOTES
         _etext = .;                     /* End of text and rodata section */
 
         . = ALIGN(PAGE_SIZE);
@@ -122,8 +123,6 @@ SECTIONS
         }
         _edata_loc = __data_loc + SIZEOF(.data);
 
-        NOTES
-
         BSS_SECTION(0, 0, 0)
         _end = .;
 
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index a8d1059b91b2..f557ebbe7013 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -296,6 +296,7 @@ void __iomem * __init early_io_map(phys_addr_t phys, unsigned long virt)
 static void __init map_mem(void)
 {
         struct memblock_region *reg;
+        phys_addr_t limit;
 
         /*
          * Temporarily limit the memblock range. We need to do this as
@@ -303,9 +304,11 @@ static void __init map_mem(void)
          * memory addressable from the initial direct kernel mapping.
          *
          * The initial direct kernel mapping, located at swapper_pg_dir,
-         * gives us PGDIR_SIZE memory starting from PHYS_OFFSET (aligned).
+         * gives us PGDIR_SIZE memory starting from PHYS_OFFSET (which must be
+         * aligned to 2MB as per Documentation/arm64/booting.txt).
          */
-        memblock_set_current_limit((PHYS_OFFSET & PGDIR_MASK) + PGDIR_SIZE);
+        limit = PHYS_OFFSET + PGDIR_SIZE;
+        memblock_set_current_limit(limit);
 
         /* map all the memory banks */
         for_each_memblock(memory, reg) {
@@ -315,6 +318,22 @@ static void __init map_mem(void)
                 if (start >= end)
                         break;
 
+#ifndef CONFIG_ARM64_64K_PAGES
+                /*
+                 * For the first memory bank align the start address and
+                 * current memblock limit to prevent create_mapping() from
+                 * allocating pte page tables from unmapped memory.
+                 * When 64K pages are enabled, the pte page table for the
+                 * first PGDIR_SIZE is already present in swapper_pg_dir.
+                 */
+                if (start < limit)
+                        start = ALIGN(start, PMD_SIZE);
+                if (end < limit) {
+                        limit = end & PMD_MASK;
+                        memblock_set_current_limit(limit);
+                }
+#endif
+
                 create_mapping(start, __phys_to_virt(start), end - start);
         }
 
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index a82ae8868077..b1b31bbc967b 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -95,10 +95,6 @@ ENTRY(cpu_do_switch_mm)
         ret
 ENDPROC(cpu_do_switch_mm)
 
-cpu_name:
-        .ascii  "AArch64 Processor"
-        .align
-
         .section ".text.init", #alloc, #execinstr
 
 /*
@@ -151,7 +147,7 @@ ENTRY(__cpu_setup)
          * both user and kernel.
          */
         ldr     x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \
-                      TCR_ASID16 | (1 << 31)
+                      TCR_ASID16 | TCR_TBI0 | (1 << 31)
 #ifdef CONFIG_ARM64_64K_PAGES
         orr     x10, x10, TCR_TG0_64K
         orr     x10, x10, TCR_TG1_64K