diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2014-04-04 06:49:05 -0400 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2014-05-09 10:47:46 -0400 |
commit | 6400111399e16a535231ebd76389c894ea1837ff (patch) | |
tree | 1cc0bda4fc7b2c8e1706fcff940b011235c14d3b /arch/arm64 | |
parent | a41dc0e841523efe1df7fa5ad48b5e9027a921df (diff) |
arm64: Remove boot thread synchronisation for spin-table release method
The synchronisation with the boot thread already happens in __cpu_up()
via wait_for_completion_timeout(). In addition, __cpu_up() calls are
protected by the cpu_add_remove_lock mutex and already serialised.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r-- | arch/arm64/kernel/smp_spin_table.c | 39 |
1 files changed, 1 insertions, 38 deletions
diff --git a/arch/arm64/kernel/smp_spin_table.c b/arch/arm64/kernel/smp_spin_table.c index 7a530d2cc807..0347d38eea29 100644 --- a/arch/arm64/kernel/smp_spin_table.c +++ b/arch/arm64/kernel/smp_spin_table.c | |||
@@ -30,7 +30,6 @@ extern void secondary_holding_pen(void); | |||
30 | volatile unsigned long secondary_holding_pen_release = INVALID_HWID; | 30 | volatile unsigned long secondary_holding_pen_release = INVALID_HWID; |
31 | 31 | ||
32 | static phys_addr_t cpu_release_addr[NR_CPUS]; | 32 | static phys_addr_t cpu_release_addr[NR_CPUS]; |
33 | static DEFINE_RAW_SPINLOCK(boot_lock); | ||
34 | 33 | ||
35 | /* | 34 | /* |
36 | * Write secondary_holding_pen_release in a way that is guaranteed to be | 35 | * Write secondary_holding_pen_release in a way that is guaranteed to be |
@@ -94,14 +93,6 @@ static int smp_spin_table_cpu_prepare(unsigned int cpu) | |||
94 | 93 | ||
95 | static int smp_spin_table_cpu_boot(unsigned int cpu) | 94 | static int smp_spin_table_cpu_boot(unsigned int cpu) |
96 | { | 95 | { |
97 | unsigned long timeout; | ||
98 | |||
99 | /* | ||
100 | * Set synchronisation state between this boot processor | ||
101 | * and the secondary one | ||
102 | */ | ||
103 | raw_spin_lock(&boot_lock); | ||
104 | |||
105 | /* | 96 | /* |
106 | * Update the pen release flag. | 97 | * Update the pen release flag. |
107 | */ | 98 | */ |
@@ -112,34 +103,7 @@ static int smp_spin_table_cpu_boot(unsigned int cpu) | |||
112 | */ | 103 | */ |
113 | sev(); | 104 | sev(); |
114 | 105 | ||
115 | timeout = jiffies + (1 * HZ); | 106 | return 0; |
116 | while (time_before(jiffies, timeout)) { | ||
117 | if (secondary_holding_pen_release == INVALID_HWID) | ||
118 | break; | ||
119 | udelay(10); | ||
120 | } | ||
121 | |||
122 | /* | ||
123 | * Now the secondary core is starting up let it run its | ||
124 | * calibrations, then wait for it to finish | ||
125 | */ | ||
126 | raw_spin_unlock(&boot_lock); | ||
127 | |||
128 | return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0; | ||
129 | } | ||
130 | |||
131 | static void smp_spin_table_cpu_postboot(void) | ||
132 | { | ||
133 | /* | ||
134 | * Let the primary processor know we're out of the pen. | ||
135 | */ | ||
136 | write_pen_release(INVALID_HWID); | ||
137 | |||
138 | /* | ||
139 | * Synchronise with the boot thread. | ||
140 | */ | ||
141 | raw_spin_lock(&boot_lock); | ||
142 | raw_spin_unlock(&boot_lock); | ||
143 | } | 107 | } |
144 | 108 | ||
145 | const struct cpu_operations smp_spin_table_ops = { | 109 | const struct cpu_operations smp_spin_table_ops = { |
@@ -147,5 +111,4 @@ const struct cpu_operations smp_spin_table_ops = { | |||
147 | .cpu_init = smp_spin_table_cpu_init, | 111 | .cpu_init = smp_spin_table_cpu_init, |
148 | .cpu_prepare = smp_spin_table_cpu_prepare, | 112 | .cpu_prepare = smp_spin_table_cpu_prepare, |
149 | .cpu_boot = smp_spin_table_cpu_boot, | 113 | .cpu_boot = smp_spin_table_cpu_boot, |
150 | .cpu_postboot = smp_spin_table_cpu_postboot, | ||
151 | }; | 114 | }; |