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authorWill Deacon <will.deacon@arm.com>2013-06-12 11:28:04 -0400
committerCatalin Marinas <catalin.marinas@arm.com>2013-09-03 05:18:02 -0400
commitd50240a5f6ceaf690a77b0fccb17be51cfa151c2 (patch)
tree843603100f6987bf50a4e40713121c1e2a323b7f /arch/arm64
parent909e3ee4119f87b85c6e1b8534b2287ed1ea3ca2 (diff)
arm64: mm: permit use of tagged pointers at EL0
TCR.TBI0 can be used to cause hardware address translation to ignore the top byte of userspace virtual addresses. Whilst not especially useful in standard C programs, this can be used by JITs to `tag' pointers with various pieces of metadata. This patch enables this bit for AArch64 Linux, and adds a new file to Documentation/arm64/ which describes some potential caveats when using tagged virtual addresses. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/include/asm/pgtable-hwdef.h1
-rw-r--r--arch/arm64/kernel/entry.S1
-rw-r--r--arch/arm64/mm/proc.S2
3 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index e182a356c979..d57e66845c86 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -122,5 +122,6 @@
122#define TCR_TG1_64K (UL(1) << 30) 122#define TCR_TG1_64K (UL(1) << 30)
123#define TCR_IPS_40BIT (UL(2) << 32) 123#define TCR_IPS_40BIT (UL(2) << 32)
124#define TCR_ASID16 (UL(1) << 36) 124#define TCR_ASID16 (UL(1) << 36)
125#define TCR_TBI0 (UL(1) << 37)
125 126
126#endif 127#endif
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 57640df9d70c..3881fd115ebb 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -423,6 +423,7 @@ el0_da:
423 * Data abort handling 423 * Data abort handling
424 */ 424 */
425 mrs x0, far_el1 425 mrs x0, far_el1
426 bic x0, x0, #(0xff << 56)
426 disable_step x1 427 disable_step x1
427 isb 428 isb
428 enable_dbg 429 enable_dbg
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index f84fcf71f129..b1b31bbc967b 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -147,7 +147,7 @@ ENTRY(__cpu_setup)
147 * both user and kernel. 147 * both user and kernel.
148 */ 148 */
149 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \ 149 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \
150 TCR_ASID16 | (1 << 31) 150 TCR_ASID16 | TCR_TBI0 | (1 << 31)
151#ifdef CONFIG_ARM64_64K_PAGES 151#ifdef CONFIG_ARM64_64K_PAGES
152 orr x10, x10, TCR_TG0_64K 152 orr x10, x10, TCR_TG0_64K
153 orr x10, x10, TCR_TG1_64K 153 orr x10, x10, TCR_TG1_64K