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authorLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2013-08-05 10:24:27 -0400
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2013-12-16 12:17:29 -0500
commitb058450f38c337d12a6d1a1bcaa8610859055e2e (patch)
tree38452a169a846c55760530eaa2340588f95524c4 /arch/arm64
parent319e2e3f63c348a9b66db4667efa73178e18b17d (diff)
arm64: kernel: add MPIDR_EL1 accessors macros
In order to simplify access to different affinity levels within the MPIDR_EL1 register values, this patch implements some preprocessor macros that allow to retrieve the MPIDR_EL1 affinity level value according to the level passed as input parameter. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/include/asm/cputype.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 5fe138e0b828..e371936b8ab2 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -30,6 +30,16 @@
30 30
31#define MPIDR_HWID_BITMASK 0xff00ffffff 31#define MPIDR_HWID_BITMASK 0xff00ffffff
32 32
33#define MPIDR_LEVEL_BITS_SHIFT 3
34#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
35#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
36
37#define MPIDR_LEVEL_SHIFT(level) \
38 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
39
40#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
41 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
42
33#define read_cpuid(reg) ({ \ 43#define read_cpuid(reg) ({ \
34 u64 __val; \ 44 u64 __val; \
35 asm("mrs %0, " reg : "=r" (__val)); \ 45 asm("mrs %0, " reg : "=r" (__val)); \