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authorPawel Moll <Pawel.Moll@arm.com>2012-11-21 06:44:28 -0500
committerCatalin Marinas <catalin.marinas@arm.com>2013-04-26 09:32:03 -0400
commit90556ca1ebdd01fbedaf9e56a826d4ce84346466 (patch)
tree3748af28b4f4a82b9146a53243c9cc33ccad4de9 /arch/arm64
parent39a90ca639db5fcd33064ddf754793ec85764239 (diff)
arm64: vexpress: Add dts files for the ARMv8 RTSM models
This patch adds the DTS files for the ARMv8 RTSM and Foundation models. Signed-off-by: Pawel Moll <Pawel.Moll@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/Makefile2
-rw-r--r--arch/arm64/boot/dts/foundation-v8.dts230
-rw-r--r--arch/arm64/boot/dts/rtsm_ve-aemv8a.dts159
-rw-r--r--arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi234
-rw-r--r--arch/arm64/boot/dts/skeleton.dtsi13
5 files changed, 638 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 32ac0aef0068..68457e9e0975 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,5 @@
1dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
2
1targets += dtbs 3targets += dtbs
2targets += $(dtb-y) 4targets += $(dtb-y)
3 5
diff --git a/arch/arm64/boot/dts/foundation-v8.dts b/arch/arm64/boot/dts/foundation-v8.dts
new file mode 100644
index 000000000000..198682b6de31
--- /dev/null
+++ b/arch/arm64/boot/dts/foundation-v8.dts
@@ -0,0 +1,230 @@
1/*
2 * ARM Ltd.
3 *
4 * ARMv8 Foundation model DTS
5 */
6
7/dts-v1/;
8
9/ {
10 model = "Foundation-v8A";
11 compatible = "arm,foundation-aarch64", "arm,vexpress";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 chosen { };
17
18 aliases {
19 serial0 = &v2m_serial0;
20 serial1 = &v2m_serial1;
21 serial2 = &v2m_serial2;
22 serial3 = &v2m_serial3;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,armv8";
32 reg = <0x0 0x0>;
33 enable-method = "spin-table";
34 cpu-release-addr = <0x0 0x8000fff8>;
35 };
36 cpu@1 {
37 device_type = "cpu";
38 compatible = "arm,armv8";
39 reg = <0x0 0x1>;
40 enable-method = "spin-table";
41 cpu-release-addr = <0x0 0x8000fff8>;
42 };
43 cpu@2 {
44 device_type = "cpu";
45 compatible = "arm,armv8";
46 reg = <0x0 0x2>;
47 enable-method = "spin-table";
48 cpu-release-addr = <0x0 0x8000fff8>;
49 };
50 cpu@3 {
51 device_type = "cpu";
52 compatible = "arm,armv8";
53 reg = <0x0 0x3>;
54 enable-method = "spin-table";
55 cpu-release-addr = <0x0 0x8000fff8>;
56 };
57 };
58
59 memory@80000000 {
60 device_type = "memory";
61 reg = <0x00000000 0x80000000 0 0x80000000>,
62 <0x00000008 0x80000000 0 0x80000000>;
63 };
64
65 gic: interrupt-controller@2c001000 {
66 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
67 #interrupt-cells = <3>;
68 #address-cells = <0>;
69 interrupt-controller;
70 reg = <0x0 0x2c001000 0 0x1000>,
71 <0x0 0x2c002000 0 0x1000>,
72 <0x0 0x2c004000 0 0x2000>,
73 <0x0 0x2c006000 0 0x2000>;
74 interrupts = <1 9 0xf04>;
75 };
76
77 timer {
78 compatible = "arm,armv8-timer";
79 interrupts = <1 13 0xff01>,
80 <1 14 0xff01>,
81 <1 11 0xff01>,
82 <1 10 0xff01>;
83 clock-frequency = <100000000>;
84 };
85
86 pmu {
87 compatible = "arm,armv8-pmuv3";
88 interrupts = <0 60 4>,
89 <0 61 4>,
90 <0 62 4>,
91 <0 63 4>;
92 };
93
94 smb {
95 compatible = "arm,vexpress,v2m-p1", "simple-bus";
96 arm,v2m-memory-map = "rs1";
97 #address-cells = <2>; /* SMB chipselect number and offset */
98 #size-cells = <1>;
99
100 ranges = <0 0 0 0x08000000 0x04000000>,
101 <1 0 0 0x14000000 0x04000000>,
102 <2 0 0 0x18000000 0x04000000>,
103 <3 0 0 0x1c000000 0x04000000>,
104 <4 0 0 0x0c000000 0x04000000>,
105 <5 0 0 0x10000000 0x04000000>;
106
107 #interrupt-cells = <1>;
108 interrupt-map-mask = <0 0 63>;
109 interrupt-map = <0 0 0 &gic 0 0 4>,
110 <0 0 1 &gic 0 1 4>,
111 <0 0 2 &gic 0 2 4>,
112 <0 0 3 &gic 0 3 4>,
113 <0 0 4 &gic 0 4 4>,
114 <0 0 5 &gic 0 5 4>,
115 <0 0 6 &gic 0 6 4>,
116 <0 0 7 &gic 0 7 4>,
117 <0 0 8 &gic 0 8 4>,
118 <0 0 9 &gic 0 9 4>,
119 <0 0 10 &gic 0 10 4>,
120 <0 0 11 &gic 0 11 4>,
121 <0 0 12 &gic 0 12 4>,
122 <0 0 13 &gic 0 13 4>,
123 <0 0 14 &gic 0 14 4>,
124 <0 0 15 &gic 0 15 4>,
125 <0 0 16 &gic 0 16 4>,
126 <0 0 17 &gic 0 17 4>,
127 <0 0 18 &gic 0 18 4>,
128 <0 0 19 &gic 0 19 4>,
129 <0 0 20 &gic 0 20 4>,
130 <0 0 21 &gic 0 21 4>,
131 <0 0 22 &gic 0 22 4>,
132 <0 0 23 &gic 0 23 4>,
133 <0 0 24 &gic 0 24 4>,
134 <0 0 25 &gic 0 25 4>,
135 <0 0 26 &gic 0 26 4>,
136 <0 0 27 &gic 0 27 4>,
137 <0 0 28 &gic 0 28 4>,
138 <0 0 29 &gic 0 29 4>,
139 <0 0 30 &gic 0 30 4>,
140 <0 0 31 &gic 0 31 4>,
141 <0 0 32 &gic 0 32 4>,
142 <0 0 33 &gic 0 33 4>,
143 <0 0 34 &gic 0 34 4>,
144 <0 0 35 &gic 0 35 4>,
145 <0 0 36 &gic 0 36 4>,
146 <0 0 37 &gic 0 37 4>,
147 <0 0 38 &gic 0 38 4>,
148 <0 0 39 &gic 0 39 4>,
149 <0 0 40 &gic 0 40 4>,
150 <0 0 41 &gic 0 41 4>,
151 <0 0 42 &gic 0 42 4>;
152
153 ethernet@2,02000000 {
154 compatible = "smsc,lan91c111";
155 reg = <2 0x02000000 0x10000>;
156 interrupts = <15>;
157 };
158
159 v2m_clk24mhz: clk24mhz {
160 compatible = "fixed-clock";
161 #clock-cells = <0>;
162 clock-frequency = <24000000>;
163 clock-output-names = "v2m:clk24mhz";
164 };
165
166 v2m_refclk1mhz: refclk1mhz {
167 compatible = "fixed-clock";
168 #clock-cells = <0>;
169 clock-frequency = <1000000>;
170 clock-output-names = "v2m:refclk1mhz";
171 };
172
173 v2m_refclk32khz: refclk32khz {
174 compatible = "fixed-clock";
175 #clock-cells = <0>;
176 clock-frequency = <32768>;
177 clock-output-names = "v2m:refclk32khz";
178 };
179
180 iofpga@3,00000000 {
181 compatible = "arm,amba-bus", "simple-bus";
182 #address-cells = <1>;
183 #size-cells = <1>;
184 ranges = <0 3 0 0x200000>;
185
186 v2m_sysreg: sysreg@010000 {
187 compatible = "arm,vexpress-sysreg";
188 reg = <0x010000 0x1000>;
189 };
190
191 v2m_serial0: uart@090000 {
192 compatible = "arm,pl011", "arm,primecell";
193 reg = <0x090000 0x1000>;
194 interrupts = <5>;
195 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
196 clock-names = "uartclk", "apb_pclk";
197 };
198
199 v2m_serial1: uart@0a0000 {
200 compatible = "arm,pl011", "arm,primecell";
201 reg = <0x0a0000 0x1000>;
202 interrupts = <6>;
203 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
204 clock-names = "uartclk", "apb_pclk";
205 };
206
207 v2m_serial2: uart@0b0000 {
208 compatible = "arm,pl011", "arm,primecell";
209 reg = <0x0b0000 0x1000>;
210 interrupts = <7>;
211 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
212 clock-names = "uartclk", "apb_pclk";
213 };
214
215 v2m_serial3: uart@0c0000 {
216 compatible = "arm,pl011", "arm,primecell";
217 reg = <0x0c0000 0x1000>;
218 interrupts = <8>;
219 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
220 clock-names = "uartclk", "apb_pclk";
221 };
222
223 virtio_block@0130000 {
224 compatible = "virtio,mmio";
225 reg = <0x130000 0x1000>;
226 interrupts = <42>;
227 };
228 };
229 };
230};
diff --git a/arch/arm64/boot/dts/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/rtsm_ve-aemv8a.dts
new file mode 100644
index 000000000000..572005ea2217
--- /dev/null
+++ b/arch/arm64/boot/dts/rtsm_ve-aemv8a.dts
@@ -0,0 +1,159 @@
1/*
2 * ARM Ltd. Fast Models
3 *
4 * Architecture Envelope Model (AEM) ARMv8-A
5 * ARMAEMv8AMPCT
6 *
7 * RTSM_VE_AEMv8A.lisa
8 */
9
10/dts-v1/;
11
12/memreserve/ 0x80000000 0x00010000;
13
14/ {
15 model = "RTSM_VE_AEMv8A";
16 compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen { };
22
23 aliases {
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
28 };
29
30 cpus {
31 #address-cells = <2>;
32 #size-cells = <0>;
33
34 cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,armv8";
37 reg = <0x0 0x0>;
38 enable-method = "spin-table";
39 cpu-release-addr = <0x0 0x8000fff8>;
40 };
41 cpu@1 {
42 device_type = "cpu";
43 compatible = "arm,armv8";
44 reg = <0x0 0x1>;
45 enable-method = "spin-table";
46 cpu-release-addr = <0x0 0x8000fff8>;
47 };
48 cpu@2 {
49 device_type = "cpu";
50 compatible = "arm,armv8";
51 reg = <0x0 0x2>;
52 enable-method = "spin-table";
53 cpu-release-addr = <0x0 0x8000fff8>;
54 };
55 cpu@3 {
56 device_type = "cpu";
57 compatible = "arm,armv8";
58 reg = <0x0 0x3>;
59 enable-method = "spin-table";
60 cpu-release-addr = <0x0 0x8000fff8>;
61 };
62 };
63
64 memory@80000000 {
65 device_type = "memory";
66 reg = <0x00000000 0x80000000 0 0x80000000>,
67 <0x00000008 0x80000000 0 0x80000000>;
68 };
69
70 gic: interrupt-controller@2c001000 {
71 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
72 #interrupt-cells = <3>;
73 #address-cells = <0>;
74 interrupt-controller;
75 reg = <0x0 0x2c001000 0 0x1000>,
76 <0x0 0x2c002000 0 0x1000>,
77 <0x0 0x2c004000 0 0x2000>,
78 <0x0 0x2c006000 0 0x2000>;
79 interrupts = <1 9 0xf04>;
80 };
81
82 timer {
83 compatible = "arm,armv8-timer";
84 interrupts = <1 13 0xff01>,
85 <1 14 0xff01>,
86 <1 11 0xff01>,
87 <1 10 0xff01>;
88 clock-frequency = <100000000>;
89 };
90
91 pmu {
92 compatible = "arm,armv8-pmuv3";
93 interrupts = <0 60 4>,
94 <0 61 4>,
95 <0 62 4>,
96 <0 63 4>;
97 };
98
99 smb {
100 compatible = "simple-bus";
101
102 #address-cells = <2>;
103 #size-cells = <1>;
104 ranges = <0 0 0 0x08000000 0x04000000>,
105 <1 0 0 0x14000000 0x04000000>,
106 <2 0 0 0x18000000 0x04000000>,
107 <3 0 0 0x1c000000 0x04000000>,
108 <4 0 0 0x0c000000 0x04000000>,
109 <5 0 0 0x10000000 0x04000000>;
110
111 #interrupt-cells = <1>;
112 interrupt-map-mask = <0 0 63>;
113 interrupt-map = <0 0 0 &gic 0 0 4>,
114 <0 0 1 &gic 0 1 4>,
115 <0 0 2 &gic 0 2 4>,
116 <0 0 3 &gic 0 3 4>,
117 <0 0 4 &gic 0 4 4>,
118 <0 0 5 &gic 0 5 4>,
119 <0 0 6 &gic 0 6 4>,
120 <0 0 7 &gic 0 7 4>,
121 <0 0 8 &gic 0 8 4>,
122 <0 0 9 &gic 0 9 4>,
123 <0 0 10 &gic 0 10 4>,
124 <0 0 11 &gic 0 11 4>,
125 <0 0 12 &gic 0 12 4>,
126 <0 0 13 &gic 0 13 4>,
127 <0 0 14 &gic 0 14 4>,
128 <0 0 15 &gic 0 15 4>,
129 <0 0 16 &gic 0 16 4>,
130 <0 0 17 &gic 0 17 4>,
131 <0 0 18 &gic 0 18 4>,
132 <0 0 19 &gic 0 19 4>,
133 <0 0 20 &gic 0 20 4>,
134 <0 0 21 &gic 0 21 4>,
135 <0 0 22 &gic 0 22 4>,
136 <0 0 23 &gic 0 23 4>,
137 <0 0 24 &gic 0 24 4>,
138 <0 0 25 &gic 0 25 4>,
139 <0 0 26 &gic 0 26 4>,
140 <0 0 27 &gic 0 27 4>,
141 <0 0 28 &gic 0 28 4>,
142 <0 0 29 &gic 0 29 4>,
143 <0 0 30 &gic 0 30 4>,
144 <0 0 31 &gic 0 31 4>,
145 <0 0 32 &gic 0 32 4>,
146 <0 0 33 &gic 0 33 4>,
147 <0 0 34 &gic 0 34 4>,
148 <0 0 35 &gic 0 35 4>,
149 <0 0 36 &gic 0 36 4>,
150 <0 0 37 &gic 0 37 4>,
151 <0 0 38 &gic 0 38 4>,
152 <0 0 39 &gic 0 39 4>,
153 <0 0 40 &gic 0 40 4>,
154 <0 0 41 &gic 0 41 4>,
155 <0 0 42 &gic 0 42 4>;
156
157 /include/ "rtsm_ve-motherboard.dtsi"
158 };
159};
diff --git a/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi
new file mode 100644
index 000000000000..b45e5f39f577
--- /dev/null
+++ b/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi
@@ -0,0 +1,234 @@
1/*
2 * ARM Ltd. Fast Models
3 *
4 * Versatile Express (VE) system model
5 * Motherboard component
6 *
7 * VEMotherBoard.lisa
8 */
9
10 motherboard {
11 arm,v2m-memory-map = "rs1";
12 compatible = "arm,vexpress,v2m-p1", "simple-bus";
13 #address-cells = <2>; /* SMB chipselect number and offset */
14 #size-cells = <1>;
15 #interrupt-cells = <1>;
16 ranges;
17
18 flash@0,00000000 {
19 compatible = "arm,vexpress-flash", "cfi-flash";
20 reg = <0 0x00000000 0x04000000>,
21 <4 0x00000000 0x04000000>;
22 bank-width = <4>;
23 };
24
25 vram@2,00000000 {
26 compatible = "arm,vexpress-vram";
27 reg = <2 0x00000000 0x00800000>;
28 };
29
30 ethernet@2,02000000 {
31 compatible = "smsc,lan91c111";
32 reg = <2 0x02000000 0x10000>;
33 interrupts = <15>;
34 };
35
36 v2m_clk24mhz: clk24mhz {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <24000000>;
40 clock-output-names = "v2m:clk24mhz";
41 };
42
43 v2m_refclk1mhz: refclk1mhz {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <1000000>;
47 clock-output-names = "v2m:refclk1mhz";
48 };
49
50 v2m_refclk32khz: refclk32khz {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <32768>;
54 clock-output-names = "v2m:refclk32khz";
55 };
56
57 iofpga@3,00000000 {
58 compatible = "arm,amba-bus", "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges = <0 3 0 0x200000>;
62
63 v2m_sysreg: sysreg@010000 {
64 compatible = "arm,vexpress-sysreg";
65 reg = <0x010000 0x1000>;
66 gpio-controller;
67 #gpio-cells = <2>;
68 };
69
70 v2m_sysctl: sysctl@020000 {
71 compatible = "arm,sp810", "arm,primecell";
72 reg = <0x020000 0x1000>;
73 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
74 clock-names = "refclk", "timclk", "apb_pclk";
75 #clock-cells = <1>;
76 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
77 };
78
79 aaci@040000 {
80 compatible = "arm,pl041", "arm,primecell";
81 reg = <0x040000 0x1000>;
82 interrupts = <11>;
83 clocks = <&v2m_clk24mhz>;
84 clock-names = "apb_pclk";
85 };
86
87 mmci@050000 {
88 compatible = "arm,pl180", "arm,primecell";
89 reg = <0x050000 0x1000>;
90 interrupts = <9 10>;
91 cd-gpios = <&v2m_sysreg 0 0>;
92 wp-gpios = <&v2m_sysreg 1 0>;
93 max-frequency = <12000000>;
94 vmmc-supply = <&v2m_fixed_3v3>;
95 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
96 clock-names = "mclk", "apb_pclk";
97 };
98
99 kmi@060000 {
100 compatible = "arm,pl050", "arm,primecell";
101 reg = <0x060000 0x1000>;
102 interrupts = <12>;
103 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
104 clock-names = "KMIREFCLK", "apb_pclk";
105 };
106
107 kmi@070000 {
108 compatible = "arm,pl050", "arm,primecell";
109 reg = <0x070000 0x1000>;
110 interrupts = <13>;
111 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
112 clock-names = "KMIREFCLK", "apb_pclk";
113 };
114
115 v2m_serial0: uart@090000 {
116 compatible = "arm,pl011", "arm,primecell";
117 reg = <0x090000 0x1000>;
118 interrupts = <5>;
119 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
120 clock-names = "uartclk", "apb_pclk";
121 };
122
123 v2m_serial1: uart@0a0000 {
124 compatible = "arm,pl011", "arm,primecell";
125 reg = <0x0a0000 0x1000>;
126 interrupts = <6>;
127 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
128 clock-names = "uartclk", "apb_pclk";
129 };
130
131 v2m_serial2: uart@0b0000 {
132 compatible = "arm,pl011", "arm,primecell";
133 reg = <0x0b0000 0x1000>;
134 interrupts = <7>;
135 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
136 clock-names = "uartclk", "apb_pclk";
137 };
138
139 v2m_serial3: uart@0c0000 {
140 compatible = "arm,pl011", "arm,primecell";
141 reg = <0x0c0000 0x1000>;
142 interrupts = <8>;
143 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
144 clock-names = "uartclk", "apb_pclk";
145 };
146
147 wdt@0f0000 {
148 compatible = "arm,sp805", "arm,primecell";
149 reg = <0x0f0000 0x1000>;
150 interrupts = <0>;
151 clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
152 clock-names = "wdogclk", "apb_pclk";
153 };
154
155 v2m_timer01: timer@110000 {
156 compatible = "arm,sp804", "arm,primecell";
157 reg = <0x110000 0x1000>;
158 interrupts = <2>;
159 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
160 clock-names = "timclken1", "timclken2", "apb_pclk";
161 };
162
163 v2m_timer23: timer@120000 {
164 compatible = "arm,sp804", "arm,primecell";
165 reg = <0x120000 0x1000>;
166 interrupts = <3>;
167 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
168 clock-names = "timclken1", "timclken2", "apb_pclk";
169 };
170
171 rtc@170000 {
172 compatible = "arm,pl031", "arm,primecell";
173 reg = <0x170000 0x1000>;
174 interrupts = <4>;
175 clocks = <&v2m_clk24mhz>;
176 clock-names = "apb_pclk";
177 };
178
179 clcd@1f0000 {
180 compatible = "arm,pl111", "arm,primecell";
181 reg = <0x1f0000 0x1000>;
182 interrupts = <14>;
183 clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
184 clock-names = "clcdclk", "apb_pclk";
185 };
186 };
187
188 v2m_fixed_3v3: fixedregulator@0 {
189 compatible = "regulator-fixed";
190 regulator-name = "3V3";
191 regulator-min-microvolt = <3300000>;
192 regulator-max-microvolt = <3300000>;
193 regulator-always-on;
194 };
195
196 mcc {
197 compatible = "arm,vexpress,config-bus", "simple-bus";
198 arm,vexpress,config-bridge = <&v2m_sysreg>;
199
200 v2m_oscclk1: osc@1 {
201 /* CLCD clock */
202 compatible = "arm,vexpress-osc";
203 arm,vexpress-sysreg,func = <1 1>;
204 freq-range = <23750000 63500000>;
205 #clock-cells = <0>;
206 clock-output-names = "v2m:oscclk1";
207 };
208
209 reset@0 {
210 compatible = "arm,vexpress-reset";
211 arm,vexpress-sysreg,func = <5 0>;
212 };
213
214 muxfpga@0 {
215 compatible = "arm,vexpress-muxfpga";
216 arm,vexpress-sysreg,func = <7 0>;
217 };
218
219 shutdown@0 {
220 compatible = "arm,vexpress-shutdown";
221 arm,vexpress-sysreg,func = <8 0>;
222 };
223
224 reboot@0 {
225 compatible = "arm,vexpress-reboot";
226 arm,vexpress-sysreg,func = <9 0>;
227 };
228
229 dvimode@0 {
230 compatible = "arm,vexpress-dvimode";
231 arm,vexpress-sysreg,func = <11 0>;
232 };
233 };
234 };
diff --git a/arch/arm64/boot/dts/skeleton.dtsi b/arch/arm64/boot/dts/skeleton.dtsi
new file mode 100644
index 000000000000..38ead821bb42
--- /dev/null
+++ b/arch/arm64/boot/dts/skeleton.dtsi
@@ -0,0 +1,13 @@
1/*
2 * Skeleton device tree; the bare minimum needed to boot; just include and
3 * add a compatible value. The bootloader will typically populate the memory
4 * node.
5 */
6
7/ {
8 #address-cells = <2>;
9 #size-cells = <1>;
10 chosen { };
11 aliases { };
12 memory { device_type = "memory"; reg = <0 0 0>; };
13};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 02:28:15 -0500