arm64: introduce aarch64_insn_gen_logical_shifted_reg()

Introduce function to generate logical (shifted register)
instructions.

Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

1 files changed, 60 insertions, 0 deletions

diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index f73a4bfbb946..0668ee5c5bf9 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -874,3 +874,63 @@ u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
         return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
                                             reg2);
 }
+
+u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
+                                         enum aarch64_insn_register src,
+                                         enum aarch64_insn_register reg,
+                                         int shift,
+                                         enum aarch64_insn_variant variant,
+                                         enum aarch64_insn_logic_type type)
+{
+        u32 insn;
+
+        switch (type) {
+        case AARCH64_INSN_LOGIC_AND:
+                insn = aarch64_insn_get_and_value();
+                break;
+        case AARCH64_INSN_LOGIC_BIC:
+                insn = aarch64_insn_get_bic_value();
+                break;
+        case AARCH64_INSN_LOGIC_ORR:
+                insn = aarch64_insn_get_orr_value();
+                break;
+        case AARCH64_INSN_LOGIC_ORN:
+                insn = aarch64_insn_get_orn_value();
+                break;
+        case AARCH64_INSN_LOGIC_EOR:
+                insn = aarch64_insn_get_eor_value();
+                break;
+        case AARCH64_INSN_LOGIC_EON:
+                insn = aarch64_insn_get_eon_value();
+                break;
+        case AARCH64_INSN_LOGIC_AND_SETFLAGS:
+                insn = aarch64_insn_get_ands_value();
+                break;
+        case AARCH64_INSN_LOGIC_BIC_SETFLAGS:
+                insn = aarch64_insn_get_bics_value();
+                break;
+        default:
+                BUG_ON(1);
+        }
+
+        switch (variant) {
+        case AARCH64_INSN_VARIANT_32BIT:
+                BUG_ON(shift & ~(SZ_32 - 1));
+                break;
+        case AARCH64_INSN_VARIANT_64BIT:
+                insn |= AARCH64_INSN_SF_BIT;
+                BUG_ON(shift & ~(SZ_64 - 1));
+                break;
+        default:
+                BUG_ON(1);
+        }
+
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
+
+        insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
+
+        return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
+}