diff options
author | Suzuki K. Poulose <suzuki.poulose@arm.com> | 2015-01-21 07:43:09 -0500 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2015-01-23 12:02:19 -0500 |
commit | 04597a65c5efc207257a736d339c6f2f5b00250f (patch) | |
tree | 953d59d84ff90345401756301e9eaeee2a4d580f /arch/arm64/kernel/cpuinfo.c | |
parent | 78d51e0b8b57728099a3da74f4a10b6f8c71b764 (diff) |
arm64: Track system support for mixed endian EL0
This patch keeps track of the mixed endian EL0 support across
the system and provides helper functions to export it. The status
is a boolean indicating whether all the CPUs on the system supports
mixed endian at EL0.
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/kernel/cpuinfo.c')
-rw-r--r-- | arch/arm64/kernel/cpuinfo.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 49782282a027..929855691dae 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c | |||
@@ -35,6 +35,7 @@ | |||
35 | */ | 35 | */ |
36 | DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); | 36 | DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); |
37 | static struct cpuinfo_arm64 boot_cpu_data; | 37 | static struct cpuinfo_arm64 boot_cpu_data; |
38 | static bool mixed_endian_el0 = true; | ||
38 | 39 | ||
39 | static char *icache_policy_str[] = { | 40 | static char *icache_policy_str[] = { |
40 | [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN", | 41 | [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN", |
@@ -68,6 +69,26 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) | |||
68 | pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); | 69 | pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); |
69 | } | 70 | } |
70 | 71 | ||
72 | bool cpu_supports_mixed_endian_el0(void) | ||
73 | { | ||
74 | return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1)); | ||
75 | } | ||
76 | |||
77 | bool system_supports_mixed_endian_el0(void) | ||
78 | { | ||
79 | return mixed_endian_el0; | ||
80 | } | ||
81 | |||
82 | static void update_mixed_endian_el0_support(struct cpuinfo_arm64 *info) | ||
83 | { | ||
84 | mixed_endian_el0 &= id_aa64mmfr0_mixed_endian_el0(info->reg_id_aa64mmfr0); | ||
85 | } | ||
86 | |||
87 | static void update_cpu_features(struct cpuinfo_arm64 *info) | ||
88 | { | ||
89 | update_mixed_endian_el0_support(info); | ||
90 | } | ||
91 | |||
71 | static int check_reg_mask(char *name, u64 mask, u64 boot, u64 cur, int cpu) | 92 | static int check_reg_mask(char *name, u64 mask, u64 boot, u64 cur, int cpu) |
72 | { | 93 | { |
73 | if ((boot & mask) == (cur & mask)) | 94 | if ((boot & mask) == (cur & mask)) |
@@ -215,6 +236,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) | |||
215 | cpuinfo_detect_icache_policy(info); | 236 | cpuinfo_detect_icache_policy(info); |
216 | 237 | ||
217 | check_local_cpu_errata(); | 238 | check_local_cpu_errata(); |
239 | update_cpu_features(info); | ||
218 | } | 240 | } |
219 | 241 | ||
220 | void cpuinfo_store_cpu(void) | 242 | void cpuinfo_store_cpu(void) |