Merge branch 'kvm-arm64/kvm-for-3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into upstream

* 'kvm-arm64/kvm-for-3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms: (33 commits)
  arm64: KVM: document kernel object mappings in HYP
  arm64: KVM: MAINTAINERS update
  arm64: KVM: userspace API documentation
  arm64: KVM: enable initialization of a 32bit vcpu
  arm64: KVM: 32bit guest fault injection
  arm64: KVM: 32bit specific register world switch
  arm64: KVM: CPU specific 32bit coprocessor access
  arm64: KVM: 32bit handling of coprocessor traps
  arm64: KVM: 32bit conditional execution emulation
  arm64: KVM: 32bit GP register access
  arm64: KVM: define 32bit specific registers
  arm64: KVM: Build system integration
  arm64: KVM: PSCI implementation
  arm64: KVM: Plug the arch timer
  ARM: KVM: timer: allow DT matching for ARMv8 cores
  arm64: KVM: Plug the VGIC
  arm64: KVM: Exit handling
  arm64: KVM: HYP mode world switch implementation
  arm64: KVM: hypervisor initialization code
  arm64: KVM: guest one-reg interface
  ...

Conflicts:
	arch/arm64/Makefile

12 files changed, 1209 insertions, 0 deletions

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
new file mode 100644
index 000000000000..a5f28e2720c7
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_ARM_H__
+#define __ARM64_KVM_ARM_H__
+
+#include <asm/types.h>
+
+/* Hyp Configuration Register (HCR) bits */
+#define HCR_ID          (UL(1) << 33)
+#define HCR_CD          (UL(1) << 32)
+#define HCR_RW_SHIFT    31
+#define HCR_RW          (UL(1) << HCR_RW_SHIFT)
+#define HCR_TRVM        (UL(1) << 30)
+#define HCR_HCD         (UL(1) << 29)
+#define HCR_TDZ         (UL(1) << 28)
+#define HCR_TGE         (UL(1) << 27)
+#define HCR_TVM         (UL(1) << 26)
+#define HCR_TTLB        (UL(1) << 25)
+#define HCR_TPU         (UL(1) << 24)
+#define HCR_TPC         (UL(1) << 23)
+#define HCR_TSW         (UL(1) << 22)
+#define HCR_TAC         (UL(1) << 21)
+#define HCR_TIDCP       (UL(1) << 20)
+#define HCR_TSC         (UL(1) << 19)
+#define HCR_TID3        (UL(1) << 18)
+#define HCR_TID2        (UL(1) << 17)
+#define HCR_TID1        (UL(1) << 16)
+#define HCR_TID0        (UL(1) << 15)
+#define HCR_TWE         (UL(1) << 14)
+#define HCR_TWI         (UL(1) << 13)
+#define HCR_DC          (UL(1) << 12)
+#define HCR_BSU         (3 << 10)
+#define HCR_BSU_IS      (UL(1) << 10)
+#define HCR_FB          (UL(1) << 9)
+#define HCR_VA          (UL(1) << 8)
+#define HCR_VI          (UL(1) << 7)
+#define HCR_VF          (UL(1) << 6)
+#define HCR_AMO         (UL(1) << 5)
+#define HCR_IMO         (UL(1) << 4)
+#define HCR_FMO         (UL(1) << 3)
+#define HCR_PTW         (UL(1) << 2)
+#define HCR_SWIO        (UL(1) << 1)
+#define HCR_VM          (UL(1) << 0)
+
+/*
+ * The bits we set in HCR:
+ * RW:          64bit by default, can be overriden for 32bit VMs
+ * TAC:         Trap ACTLR
+ * TSC:         Trap SMC
+ * TSW:         Trap cache operations by set/way
+ * TWI:         Trap WFI
+ * TIDCP:       Trap L2CTLR/L2ECTLR
+ * BSU_IS:      Upgrade barriers to the inner shareable domain
+ * FB:          Force broadcast of all maintainance operations
+ * AMO:         Override CPSR.A and enable signaling with VA
+ * IMO:         Override CPSR.I and enable signaling with VI
+ * FMO:         Override CPSR.F and enable signaling with VF
+ * SWIO:        Turn set/way invalidates into set/way clean+invalidate
+ */
+#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \
+                         HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \
+                         HCR_SWIO | HCR_TIDCP | HCR_RW)
+#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
+
+/* Hyp System Control Register (SCTLR_EL2) bits */
+#define SCTLR_EL2_EE    (1 << 25)
+#define SCTLR_EL2_WXN   (1 << 19)
+#define SCTLR_EL2_I     (1 << 12)
+#define SCTLR_EL2_SA    (1 << 3)
+#define SCTLR_EL2_C     (1 << 2)
+#define SCTLR_EL2_A     (1 << 1)
+#define SCTLR_EL2_M     1
+#define SCTLR_EL2_FLAGS (SCTLR_EL2_M | SCTLR_EL2_A | SCTLR_EL2_C |      \
+                         SCTLR_EL2_SA | SCTLR_EL2_I)
+
+/* TCR_EL2 Registers bits */
+#define TCR_EL2_TBI     (1 << 20)
+#define TCR_EL2_PS      (7 << 16)
+#define TCR_EL2_PS_40B  (2 << 16)
+#define TCR_EL2_TG0     (1 << 14)
+#define TCR_EL2_SH0     (3 << 12)
+#define TCR_EL2_ORGN0   (3 << 10)
+#define TCR_EL2_IRGN0   (3 << 8)
+#define TCR_EL2_T0SZ    0x3f
+#define TCR_EL2_MASK    (TCR_EL2_TG0 | TCR_EL2_SH0 | \
+                         TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ)
+
+#define TCR_EL2_FLAGS   (TCR_EL2_PS_40B)
+
+/* VTCR_EL2 Registers bits */
+#define VTCR_EL2_PS_MASK        (7 << 16)
+#define VTCR_EL2_PS_40B         (2 << 16)
+#define VTCR_EL2_TG0_MASK       (1 << 14)
+#define VTCR_EL2_TG0_4K         (0 << 14)
+#define VTCR_EL2_TG0_64K        (1 << 14)
+#define VTCR_EL2_SH0_MASK       (3 << 12)
+#define VTCR_EL2_SH0_INNER      (3 << 12)
+#define VTCR_EL2_ORGN0_MASK     (3 << 10)
+#define VTCR_EL2_ORGN0_WBWA     (1 << 10)
+#define VTCR_EL2_IRGN0_MASK     (3 << 8)
+#define VTCR_EL2_IRGN0_WBWA     (1 << 8)
+#define VTCR_EL2_SL0_MASK       (3 << 6)
+#define VTCR_EL2_SL0_LVL1       (1 << 6)
+#define VTCR_EL2_T0SZ_MASK      0x3f
+#define VTCR_EL2_T0SZ_40B       24
+
+#ifdef CONFIG_ARM64_64K_PAGES
+/*
+ * Stage2 translation configuration:
+ * 40bits output (PS = 2)
+ * 40bits input  (T0SZ = 24)
+ * 64kB pages (TG0 = 1)
+ * 2 level page tables (SL = 1)
+ */
+#define VTCR_EL2_FLAGS          (VTCR_EL2_PS_40B | VTCR_EL2_TG0_64K | \
+                                 VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
+                                 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \
+                                 VTCR_EL2_T0SZ_40B)
+#define VTTBR_X         (38 - VTCR_EL2_T0SZ_40B)
+#else
+/*
+ * Stage2 translation configuration:
+ * 40bits output (PS = 2)
+ * 40bits input  (T0SZ = 24)
+ * 4kB pages (TG0 = 0)
+ * 3 level page tables (SL = 1)
+ */
+#define VTCR_EL2_FLAGS          (VTCR_EL2_PS_40B | VTCR_EL2_TG0_4K | \
+                                 VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
+                                 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \
+                                 VTCR_EL2_T0SZ_40B)
+#define VTTBR_X         (37 - VTCR_EL2_T0SZ_40B)
+#endif
+
+#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
+#define VTTBR_BADDR_MASK  (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
+#define VTTBR_VMID_SHIFT  (48LLU)
+#define VTTBR_VMID_MASK   (0xffLLU << VTTBR_VMID_SHIFT)
+
+/* Hyp System Trap Register */
+#define HSTR_EL2_TTEE   (1 << 16)
+#define HSTR_EL2_T(x)   (1 << x)
+
+/* Hyp Coprocessor Trap Register */
+#define CPTR_EL2_TCPAC  (1 << 31)
+#define CPTR_EL2_TTA    (1 << 20)
+#define CPTR_EL2_TFP    (1 << 10)
+
+/* Hyp Debug Configuration Register bits */
+#define MDCR_EL2_TDRA           (1 << 11)
+#define MDCR_EL2_TDOSA          (1 << 10)
+#define MDCR_EL2_TDA            (1 << 9)
+#define MDCR_EL2_TDE            (1 << 8)
+#define MDCR_EL2_HPME           (1 << 7)
+#define MDCR_EL2_TPM            (1 << 6)
+#define MDCR_EL2_TPMCR          (1 << 5)
+#define MDCR_EL2_HPMN_MASK      (0x1F)
+
+/* Exception Syndrome Register (ESR) bits */
+#define ESR_EL2_EC_SHIFT        (26)
+#define ESR_EL2_EC              (0x3fU << ESR_EL2_EC_SHIFT)
+#define ESR_EL2_IL              (1U << 25)
+#define ESR_EL2_ISS             (ESR_EL2_IL - 1)
+#define ESR_EL2_ISV_SHIFT       (24)
+#define ESR_EL2_ISV             (1U << ESR_EL2_ISV_SHIFT)
+#define ESR_EL2_SAS_SHIFT       (22)
+#define ESR_EL2_SAS             (3U << ESR_EL2_SAS_SHIFT)
+#define ESR_EL2_SSE             (1 << 21)
+#define ESR_EL2_SRT_SHIFT       (16)
+#define ESR_EL2_SRT_MASK        (0x1f << ESR_EL2_SRT_SHIFT)
+#define ESR_EL2_SF              (1 << 15)
+#define ESR_EL2_AR              (1 << 14)
+#define ESR_EL2_EA              (1 << 9)
+#define ESR_EL2_CM              (1 << 8)
+#define ESR_EL2_S1PTW           (1 << 7)
+#define ESR_EL2_WNR             (1 << 6)
+#define ESR_EL2_FSC             (0x3f)
+#define ESR_EL2_FSC_TYPE        (0x3c)
+
+#define ESR_EL2_CV_SHIFT        (24)
+#define ESR_EL2_CV              (1U << ESR_EL2_CV_SHIFT)
+#define ESR_EL2_COND_SHIFT      (20)
+#define ESR_EL2_COND            (0xfU << ESR_EL2_COND_SHIFT)
+
+
+#define FSC_FAULT       (0x04)
+#define FSC_PERM        (0x0c)
+
+/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
+#define HPFAR_MASK      (~0xFUL)
+
+#define ESR_EL2_EC_UNKNOWN      (0x00)
+#define ESR_EL2_EC_WFI          (0x01)
+#define ESR_EL2_EC_CP15_32      (0x03)
+#define ESR_EL2_EC_CP15_64      (0x04)
+#define ESR_EL2_EC_CP14_MR      (0x05)
+#define ESR_EL2_EC_CP14_LS      (0x06)
+#define ESR_EL2_EC_FP_ASIMD     (0x07)
+#define ESR_EL2_EC_CP10_ID      (0x08)
+#define ESR_EL2_EC_CP14_64      (0x0C)
+#define ESR_EL2_EC_ILL_ISS      (0x0E)
+#define ESR_EL2_EC_SVC32        (0x11)
+#define ESR_EL2_EC_HVC32        (0x12)
+#define ESR_EL2_EC_SMC32        (0x13)
+#define ESR_EL2_EC_SVC64        (0x15)
+#define ESR_EL2_EC_HVC64        (0x16)
+#define ESR_EL2_EC_SMC64        (0x17)
+#define ESR_EL2_EC_SYS64        (0x18)
+#define ESR_EL2_EC_IABT         (0x20)
+#define ESR_EL2_EC_IABT_HYP     (0x21)
+#define ESR_EL2_EC_PC_ALIGN     (0x22)
+#define ESR_EL2_EC_DABT         (0x24)
+#define ESR_EL2_EC_DABT_HYP     (0x25)
+#define ESR_EL2_EC_SP_ALIGN     (0x26)
+#define ESR_EL2_EC_FP_EXC32     (0x28)
+#define ESR_EL2_EC_FP_EXC64     (0x2C)
+#define ESR_EL2_EC_SERRROR      (0x2F)
+#define ESR_EL2_EC_BREAKPT      (0x30)
+#define ESR_EL2_EC_BREAKPT_HYP  (0x31)
+#define ESR_EL2_EC_SOFTSTP      (0x32)
+#define ESR_EL2_EC_SOFTSTP_HYP  (0x33)
+#define ESR_EL2_EC_WATCHPT      (0x34)
+#define ESR_EL2_EC_WATCHPT_HYP  (0x35)
+#define ESR_EL2_EC_BKPT32       (0x38)
+#define ESR_EL2_EC_VECTOR32     (0x3A)
+#define ESR_EL2_EC_BRK64        (0x3C)
+
+#define ESR_EL2_EC_xABT_xFSR_EXTABT     0x10
+
+#endif /* __ARM64_KVM_ARM_H__ */
diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
new file mode 100644
index 000000000000..c92de4163eba
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM_KVM_ASM_H__
+#define __ARM_KVM_ASM_H__
+
+/*
+ * 0 is reserved as an invalid value.
+ * Order *must* be kept in sync with the hyp switch code.
+ */
+#define MPIDR_EL1       1       /* MultiProcessor Affinity Register */
+#define CSSELR_EL1      2       /* Cache Size Selection Register */
+#define SCTLR_EL1       3       /* System Control Register */
+#define ACTLR_EL1       4       /* Auxilliary Control Register */
+#define CPACR_EL1       5       /* Coprocessor Access Control */
+#define TTBR0_EL1       6       /* Translation Table Base Register 0 */
+#define TTBR1_EL1       7       /* Translation Table Base Register 1 */
+#define TCR_EL1         8       /* Translation Control Register */
+#define ESR_EL1         9       /* Exception Syndrome Register */
+#define AFSR0_EL1       10      /* Auxilary Fault Status Register 0 */
+#define AFSR1_EL1       11      /* Auxilary Fault Status Register 1 */
+#define FAR_EL1         12      /* Fault Address Register */
+#define MAIR_EL1        13      /* Memory Attribute Indirection Register */
+#define VBAR_EL1        14      /* Vector Base Address Register */
+#define CONTEXTIDR_EL1  15      /* Context ID Register */
+#define TPIDR_EL0       16      /* Thread ID, User R/W */
+#define TPIDRRO_EL0     17      /* Thread ID, User R/O */
+#define TPIDR_EL1       18      /* Thread ID, Privileged */
+#define AMAIR_EL1       19      /* Aux Memory Attribute Indirection Register */
+#define CNTKCTL_EL1     20      /* Timer Control Register (EL1) */
+/* 32bit specific registers. Keep them at the end of the range */
+#define DACR32_EL2      21      /* Domain Access Control Register */
+#define IFSR32_EL2      22      /* Instruction Fault Status Register */
+#define FPEXC32_EL2     23      /* Floating-Point Exception Control Register */
+#define DBGVCR32_EL2    24      /* Debug Vector Catch Register */
+#define TEECR32_EL1     25      /* ThumbEE Configuration Register */
+#define TEEHBR32_EL1    26      /* ThumbEE Handler Base Register */
+#define NR_SYS_REGS     27
+
+/* 32bit mapping */
+#define c0_MPIDR        (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
+#define c0_CSSELR       (CSSELR_EL1 * 2)/* Cache Size Selection Register */
+#define c1_SCTLR        (SCTLR_EL1 * 2) /* System Control Register */
+#define c1_ACTLR        (ACTLR_EL1 * 2) /* Auxiliary Control Register */
+#define c1_CPACR        (CPACR_EL1 * 2) /* Coprocessor Access Control */
+#define c2_TTBR0        (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
+#define c2_TTBR0_high   (c2_TTBR0 + 1)  /* TTBR0 top 32 bits */
+#define c2_TTBR1        (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
+#define c2_TTBR1_high   (c2_TTBR1 + 1)  /* TTBR1 top 32 bits */
+#define c2_TTBCR        (TCR_EL1 * 2)   /* Translation Table Base Control R. */
+#define c3_DACR         (DACR32_EL2 * 2)/* Domain Access Control Register */
+#define c5_DFSR         (ESR_EL1 * 2)   /* Data Fault Status Register */
+#define c5_IFSR         (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
+#define c5_ADFSR        (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
+#define c5_AIFSR        (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
+#define c6_DFAR         (FAR_EL1 * 2)   /* Data Fault Address Register */
+#define c6_IFAR         (c6_DFAR + 1)   /* Instruction Fault Address Register */
+#define c10_PRRR        (MAIR_EL1 * 2)  /* Primary Region Remap Register */
+#define c10_NMRR        (c10_PRRR + 1)  /* Normal Memory Remap Register */
+#define c12_VBAR        (VBAR_EL1 * 2)  /* Vector Base Address Register */
+#define c13_CID         (CONTEXTIDR_EL1 * 2)    /* Context ID Register */
+#define c13_TID_URW     (TPIDR_EL0 * 2) /* Thread ID, User R/W */
+#define c13_TID_URO     (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
+#define c13_TID_PRIV    (TPIDR_EL1 * 2) /* Thread ID, Privileged */
+#define c10_AMAIR       (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
+#define c14_CNTKCTL     (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
+#define NR_CP15_REGS    (NR_SYS_REGS * 2)
+
+#define ARM_EXCEPTION_IRQ         0
+#define ARM_EXCEPTION_TRAP        1
+
+#ifndef __ASSEMBLY__
+struct kvm;
+struct kvm_vcpu;
+
+extern char __kvm_hyp_init[];
+extern char __kvm_hyp_init_end[];
+
+extern char __kvm_hyp_vector[];
+
+extern char __kvm_hyp_code_start[];
+extern char __kvm_hyp_code_end[];
+
+extern void __kvm_flush_vm_context(void);
+extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
+
+extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
+#endif
+
+#endif /* __ARM_KVM_ASM_H__ */
diff --git a/arch/arm64/include/asm/kvm_coproc.h b/arch/arm64/include/asm/kvm_coproc.h
new file mode 100644
index 000000000000..9a59301cd014
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_coproc.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/include/asm/kvm_coproc.h
+ * Copyright (C) 2012 Rusty Russell IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_COPROC_H__
+#define __ARM64_KVM_COPROC_H__
+
+#include <linux/kvm_host.h>
+
+void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
+
+struct kvm_sys_reg_table {
+        const struct sys_reg_desc *table;
+        size_t num;
+};
+
+struct kvm_sys_reg_target_table {
+        struct kvm_sys_reg_table table64;
+        struct kvm_sys_reg_table table32;
+};
+
+void kvm_register_target_sys_reg_table(unsigned int target,
+                                       struct kvm_sys_reg_target_table *table);
+
+int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run);
+
+#define kvm_coproc_table_init kvm_sys_reg_table_init
+void kvm_sys_reg_table_init(void);
+
+struct kvm_one_reg;
+int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
+int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
+int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
+unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
+
+#endif /* __ARM64_KVM_COPROC_H__ */
diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
new file mode 100644
index 000000000000..eec073875218
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/include/kvm_emulate.h
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_EMULATE_H__
+#define __ARM64_KVM_EMULATE_H__
+
+#include <linux/kvm_host.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_mmio.h>
+#include <asm/ptrace.h>
+
+unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
+unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu);
+
+bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
+void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
+
+void kvm_inject_undefined(struct kvm_vcpu *vcpu);
+void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
+void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
+
+static inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
+{
+        return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;
+}
+
+static inline unsigned long *vcpu_elr_el1(const struct kvm_vcpu *vcpu)
+{
+        return (unsigned long *)&vcpu_gp_regs(vcpu)->elr_el1;
+}
+
+static inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
+{
+        return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;
+}
+
+static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
+{
+        return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
+}
+
+static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
+{
+        if (vcpu_mode_is_32bit(vcpu))
+                return kvm_condition_valid32(vcpu);
+
+        return true;
+}
+
+static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
+{
+        if (vcpu_mode_is_32bit(vcpu))
+                kvm_skip_instr32(vcpu, is_wide_instr);
+        else
+                *vcpu_pc(vcpu) += 4;
+}
+
+static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
+{
+        *vcpu_cpsr(vcpu) |= COMPAT_PSR_T_BIT;
+}
+
+static inline unsigned long *vcpu_reg(const struct kvm_vcpu *vcpu, u8 reg_num)
+{
+        if (vcpu_mode_is_32bit(vcpu))
+                return vcpu_reg32(vcpu, reg_num);
+
+        return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.regs[reg_num];
+}
+
+/* Get vcpu SPSR for current mode */
+static inline unsigned long *vcpu_spsr(const struct kvm_vcpu *vcpu)
+{
+        if (vcpu_mode_is_32bit(vcpu))
+                return vcpu_spsr32(vcpu);
+
+        return (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
+}
+
+static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
+{
+        u32 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
+
+        if (vcpu_mode_is_32bit(vcpu))
+                return mode > COMPAT_PSR_MODE_USR;
+
+        return mode != PSR_MODE_EL0t;
+}
+
+static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.fault.esr_el2;
+}
+
+static inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.fault.far_el2;
+}
+
+static inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
+{
+        return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
+}
+
+static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
+{
+        return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_ISV);
+}
+
+static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
+{
+        return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_WNR);
+}
+
+static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
+{
+        return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_SSE);
+}
+
+static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
+{
+        return (kvm_vcpu_get_hsr(vcpu) & ESR_EL2_SRT_MASK) >> ESR_EL2_SRT_SHIFT;
+}
+
+static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
+{
+        return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_EA);
+}
+
+static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)
+{
+        return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_S1PTW);
+}
+
+static inline int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
+{
+        return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_EL2_SAS) >> ESR_EL2_SAS_SHIFT);
+}
+
+/* This one is not specific to Data Abort */
+static inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
+{
+        return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_IL);
+}
+
+static inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_get_hsr(vcpu) >> ESR_EL2_EC_SHIFT;
+}
+
+static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_trap_get_class(vcpu) == ESR_EL2_EC_IABT;
+}
+
+static inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_get_hsr(vcpu) & ESR_EL2_FSC_TYPE;
+}
+
+#endif /* __ARM64_KVM_EMULATE_H__ */
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
new file mode 100644
index 000000000000..644d73956864
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/include/asm/kvm_host.h:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_HOST_H__
+#define __ARM64_KVM_HOST_H__
+
+#include <asm/kvm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_mmio.h>
+
+#define KVM_MAX_VCPUS 4
+#define KVM_USER_MEM_SLOTS 32
+#define KVM_PRIVATE_MEM_SLOTS 4
+#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
+
+#include <kvm/arm_vgic.h>
+#include <kvm/arm_arch_timer.h>
+
+#define KVM_VCPU_MAX_FEATURES 2
+
+/* We don't currently support large pages. */
+#define KVM_HPAGE_GFN_SHIFT(x)  0
+#define KVM_NR_PAGE_SIZES       1
+#define KVM_PAGES_PER_HPAGE(x)  (1UL<<31)
+
+struct kvm_vcpu;
+int kvm_target_cpu(void);
+int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
+int kvm_arch_dev_ioctl_check_extension(long ext);
+
+struct kvm_arch {
+        /* The VMID generation used for the virt. memory system */
+        u64    vmid_gen;
+        u32    vmid;
+
+        /* 1-level 2nd stage table and lock */
+        spinlock_t pgd_lock;
+        pgd_t *pgd;
+
+        /* VTTBR value associated with above pgd and vmid */
+        u64    vttbr;
+
+        /* Interrupt controller */
+        struct vgic_dist        vgic;
+
+        /* Timer */
+        struct arch_timer_kvm   timer;
+};
+
+#define KVM_NR_MEM_OBJS     40
+
+/*
+ * We don't want allocation failures within the mmu code, so we preallocate
+ * enough memory for a single page fault in a cache.
+ */
+struct kvm_mmu_memory_cache {
+        int nobjs;
+        void *objects[KVM_NR_MEM_OBJS];
+};
+
+struct kvm_vcpu_fault_info {
+        u32 esr_el2;            /* Hyp Syndrom Register */
+        u64 far_el2;            /* Hyp Fault Address Register */
+        u64 hpfar_el2;          /* Hyp IPA Fault Address Register */
+};
+
+struct kvm_cpu_context {
+        struct kvm_regs gp_regs;
+        union {
+                u64 sys_regs[NR_SYS_REGS];
+                u32 cp15[NR_CP15_REGS];
+        };
+};
+
+typedef struct kvm_cpu_context kvm_cpu_context_t;
+
+struct kvm_vcpu_arch {
+        struct kvm_cpu_context ctxt;
+
+        /* HYP configuration */
+        u64 hcr_el2;
+
+        /* Exception Information */
+        struct kvm_vcpu_fault_info fault;
+
+        /* Pointer to host CPU context */
+        kvm_cpu_context_t *host_cpu_context;
+
+        /* VGIC state */
+        struct vgic_cpu vgic_cpu;
+        struct arch_timer_cpu timer_cpu;
+
+        /*
+         * Anything that is not used directly from assembly code goes
+         * here.
+         */
+        /* dcache set/way operation pending */
+        int last_pcpu;
+        cpumask_t require_dcache_flush;
+
+        /* Don't run the guest */
+        bool pause;
+
+        /* IO related fields */
+        struct kvm_decode mmio_decode;
+
+        /* Interrupt related fields */
+        u64 irq_lines;          /* IRQ and FIQ levels */
+
+        /* Cache some mmu pages needed inside spinlock regions */
+        struct kvm_mmu_memory_cache mmu_page_cache;
+
+        /* Target CPU and feature flags */
+        u32 target;
+        DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
+
+        /* Detect first run of a vcpu */
+        bool has_run_once;
+};
+
+#define vcpu_gp_regs(v)         (&(v)->arch.ctxt.gp_regs)
+#define vcpu_sys_reg(v,r)       ((v)->arch.ctxt.sys_regs[(r)])
+#define vcpu_cp15(v,r)          ((v)->arch.ctxt.cp15[(r)])
+
+struct kvm_vm_stat {
+        u32 remote_tlb_flush;
+};
+
+struct kvm_vcpu_stat {
+        u32 halt_wakeup;
+};
+
+struct kvm_vcpu_init;
+int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
+                        const struct kvm_vcpu_init *init);
+unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
+int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
+struct kvm_one_reg;
+int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
+int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
+
+#define KVM_ARCH_WANT_MMU_NOTIFIER
+struct kvm;
+int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
+int kvm_unmap_hva_range(struct kvm *kvm,
+                        unsigned long start, unsigned long end);
+void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
+
+/* We do not have shadow page tables, hence the empty hooks */
+static inline int kvm_age_hva(struct kvm *kvm, unsigned long hva)
+{
+        return 0;
+}
+
+static inline int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
+{
+        return 0;
+}
+
+struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
+struct kvm_vcpu __percpu **kvm_get_running_vcpus(void);
+
+u64 kvm_call_hyp(void *hypfn, ...);
+
+int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                int exception_index);
+
+int kvm_perf_init(void);
+int kvm_perf_teardown(void);
+
+static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
+                                       phys_addr_t pgd_ptr,
+                                       unsigned long hyp_stack_ptr,
+                                       unsigned long vector_ptr)
+{
+        /*
+         * Call initialization code, and switch to the full blown
+         * HYP code.
+         */
+        kvm_call_hyp((void *)boot_pgd_ptr, pgd_ptr,
+                     hyp_stack_ptr, vector_ptr);
+}
+
+#endif /* __ARM64_KVM_HOST_H__ */
diff --git a/arch/arm64/include/asm/kvm_mmio.h b/arch/arm64/include/asm/kvm_mmio.h
new file mode 100644
index 000000000000..fc2f689c0694
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_mmio.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_MMIO_H__
+#define __ARM64_KVM_MMIO_H__
+
+#include <linux/kvm_host.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_arm.h>
+
+/*
+ * This is annoying. The mmio code requires this, even if we don't
+ * need any decoding. To be fixed.
+ */
+struct kvm_decode {
+        unsigned long rt;
+        bool sign_extend;
+};
+
+/*
+ * The in-kernel MMIO emulation code wants to use a copy of run->mmio,
+ * which is an anonymous type. Use our own type instead.
+ */
+struct kvm_exit_mmio {
+        phys_addr_t     phys_addr;
+        u8              data[8];
+        u32             len;
+        bool            is_write;
+};
+
+static inline void kvm_prepare_mmio(struct kvm_run *run,
+                                    struct kvm_exit_mmio *mmio)
+{
+        run->mmio.phys_addr     = mmio->phys_addr;
+        run->mmio.len           = mmio->len;
+        run->mmio.is_write      = mmio->is_write;
+        memcpy(run->mmio.data, mmio->data, mmio->len);
+        run->exit_reason        = KVM_EXIT_MMIO;
+}
+
+int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                 phys_addr_t fault_ipa);
+
+#endif  /* __ARM64_KVM_MMIO_H__ */
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
new file mode 100644
index 000000000000..efe609c6a3c9
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_MMU_H__
+#define __ARM64_KVM_MMU_H__
+
+#include <asm/page.h>
+#include <asm/memory.h>
+
+/*
+ * As we only have the TTBR0_EL2 register, we cannot express
+ * "negative" addresses. This makes it impossible to directly share
+ * mappings with the kernel.
+ *
+ * Instead, give the HYP mode its own VA region at a fixed offset from
+ * the kernel by just masking the top bits (which are all ones for a
+ * kernel address).
+ */
+#define HYP_PAGE_OFFSET_SHIFT   VA_BITS
+#define HYP_PAGE_OFFSET_MASK    ((UL(1) << HYP_PAGE_OFFSET_SHIFT) - 1)
+#define HYP_PAGE_OFFSET         (PAGE_OFFSET & HYP_PAGE_OFFSET_MASK)
+
+/*
+ * Our virtual mapping for the idmap-ed MMU-enable code. Must be
+ * shared across all the page-tables. Conveniently, we use the last
+ * possible page, where no kernel mapping will ever exist.
+ */
+#define TRAMPOLINE_VA           (HYP_PAGE_OFFSET_MASK & PAGE_MASK)
+
+#ifdef __ASSEMBLY__
+
+/*
+ * Convert a kernel VA into a HYP VA.
+ * reg: VA to be converted.
+ */
+.macro kern_hyp_va      reg
+        and     \reg, \reg, #HYP_PAGE_OFFSET_MASK
+.endm
+
+#else
+
+#include <asm/cachetype.h>
+#include <asm/cacheflush.h>
+
+#define KERN_TO_HYP(kva)        ((unsigned long)kva - PAGE_OFFSET + HYP_PAGE_OFFSET)
+
+/*
+ * Align KVM with the kernel's view of physical memory. Should be
+ * 40bit IPA, with PGD being 8kB aligned in the 4KB page configuration.
+ */
+#define KVM_PHYS_SHIFT  PHYS_MASK_SHIFT
+#define KVM_PHYS_SIZE   (1UL << KVM_PHYS_SHIFT)
+#define KVM_PHYS_MASK   (KVM_PHYS_SIZE - 1UL)
+
+/* Make sure we get the right size, and thus the right alignment */
+#define PTRS_PER_S2_PGD (1 << (KVM_PHYS_SHIFT - PGDIR_SHIFT))
+#define S2_PGD_ORDER    get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
+
+int create_hyp_mappings(void *from, void *to);
+int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
+void free_boot_hyp_pgd(void);
+void free_hyp_pgds(void);
+
+int kvm_alloc_stage2_pgd(struct kvm *kvm);
+void kvm_free_stage2_pgd(struct kvm *kvm);
+int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
+                          phys_addr_t pa, unsigned long size);
+
+int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
+
+void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
+
+phys_addr_t kvm_mmu_get_httbr(void);
+phys_addr_t kvm_mmu_get_boot_httbr(void);
+phys_addr_t kvm_get_idmap_vector(void);
+int kvm_mmu_init(void);
+void kvm_clear_hyp_idmap(void);
+
+#define kvm_set_pte(ptep, pte)          set_pte(ptep, pte)
+
+static inline bool kvm_is_write_fault(unsigned long esr)
+{
+        unsigned long esr_ec = esr >> ESR_EL2_EC_SHIFT;
+
+        if (esr_ec == ESR_EL2_EC_IABT)
+                return false;
+
+        if ((esr & ESR_EL2_ISV) && !(esr & ESR_EL2_WNR))
+                return false;
+
+        return true;
+}
+
+static inline void kvm_clean_dcache_area(void *addr, size_t size) {}
+static inline void kvm_clean_pgd(pgd_t *pgd) {}
+static inline void kvm_clean_pmd_entry(pmd_t *pmd) {}
+static inline void kvm_clean_pte(pte_t *pte) {}
+static inline void kvm_clean_pte_entry(pte_t *pte) {}
+
+static inline void kvm_set_s2pte_writable(pte_t *pte)
+{
+        pte_val(*pte) |= PTE_S2_RDWR;
+}
+
+struct kvm;
+
+static inline void coherent_icache_guest_page(struct kvm *kvm, gfn_t gfn)
+{
+        if (!icache_is_aliasing()) {            /* PIPT */
+                unsigned long hva = gfn_to_hva(kvm, gfn);
+                flush_icache_range(hva, hva + PAGE_SIZE);
+        } else if (!icache_is_aivivt()) {       /* non ASID-tagged VIVT */
+                /* any kind of VIPT cache */
+                __flush_icache_all();
+        }
+}
+
+#define kvm_flush_dcache_to_poc(a,l)    __flush_dcache_area((a), (l))
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARM64_KVM_MMU_H__ */
diff --git a/arch/arm64/include/asm/kvm_psci.h b/arch/arm64/include/asm/kvm_psci.h
new file mode 100644
index 000000000000..e301a4816355
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_psci.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_PSCI_H__
+#define __ARM64_KVM_PSCI_H__
+
+bool kvm_psci_call(struct kvm_vcpu *vcpu);
+
+#endif /* __ARM64_KVM_PSCI_H__ */
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index 381f556b664e..20925bcf4e2a 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -90,6 +90,12 @@
 #define MT_NORMAL_NC            3
 #define MT_NORMAL               4
 
+/*
+ * Memory types for Stage-2 translation
+ */
+#define MT_S2_NORMAL            0xf
+#define MT_S2_DEVICE_nGnRE      0x1
+
 #ifndef __ASSEMBLY__
 
 extern phys_addr_t              memstart_addr;
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 75fd13d289b9..66367c6c6527 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -35,6 +35,7 @@
 /*
  * Section
  */
+#define PMD_SECT_USER           (_AT(pteval_t, 1) << 6)         /* AP[1] */
 #define PMD_SECT_S              (_AT(pmdval_t, 3) << 8)
 #define PMD_SECT_AF             (_AT(pmdval_t, 1) << 10)
 #define PMD_SECT_NG             (_AT(pmdval_t, 1) << 11)
@@ -68,6 +69,24 @@
 #define PTE_ATTRINDX_MASK       (_AT(pteval_t, 7) << 2)
 
 /*
+ * 2nd stage PTE definitions
+ */
+#define PTE_S2_RDONLY           (_AT(pteval_t, 1) << 6)   /* HAP[2:1] */
+#define PTE_S2_RDWR             (_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
+
+/*
+ * Memory Attribute override for Stage-2 (MemAttr[3:0])
+ */
+#define PTE_S2_MEMATTR(t)       (_AT(pteval_t, (t)) << 2)
+#define PTE_S2_MEMATTR_MASK     (_AT(pteval_t, 0xf) << 2)
+
+/*
+ * EL2/HYP PTE/PMD definitions
+ */
+#define PMD_HYP                 PMD_SECT_USER
+#define PTE_HYP                 PTE_USER
+
+/*
  * 40-bit physical address supported.
  */
 #define PHYS_MASK_SHIFT         (40)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index b93bc2326f56..5588e8ad9762 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -76,6 +76,12 @@ extern pgprot_t pgprot_default;
 #define PAGE_KERNEL             _MOD_PROT(pgprot_default, PTE_PXN | PTE_UXN | PTE_DIRTY)
 #define PAGE_KERNEL_EXEC        _MOD_PROT(pgprot_default, PTE_UXN | PTE_DIRTY)
 
+#define PAGE_HYP                _MOD_PROT(pgprot_default, PTE_HYP)
+#define PAGE_HYP_DEVICE         __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
+
+#define PAGE_S2                 __pgprot_modify(pgprot_default, PTE_S2_MEMATTR_MASK, PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
+#define PAGE_S2_DEVICE          __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDWR | PTE_UXN)
+
 #define __PAGE_NONE             __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE)
 #define __PAGE_SHARED           __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
 #define __PAGE_SHARED_EXEC      __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
@@ -197,6 +203,12 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 
 #define pmd_bad(pmd)            (!(pmd_val(pmd) & 2))
 
+#define pmd_table(pmd)          ((pmd_val(pmd) & PMD_TYPE_MASK) == \
+                                 PMD_TYPE_TABLE)
+#define pmd_sect(pmd)           ((pmd_val(pmd) & PMD_TYPE_MASK) == \
+                                 PMD_TYPE_SECT)
+
+
 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
 {
         *pmdp = pmd;
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
new file mode 100644
index 000000000000..5031f4263937
--- /dev/null
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/include/uapi/asm/kvm.h:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM_KVM_H__
+#define __ARM_KVM_H__
+
+#define KVM_SPSR_EL1    0
+#define KVM_SPSR_SVC    KVM_SPSR_EL1
+#define KVM_SPSR_ABT    1
+#define KVM_SPSR_UND    2
+#define KVM_SPSR_IRQ    3
+#define KVM_SPSR_FIQ    4
+#define KVM_NR_SPSR     5
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/ptrace.h>
+
+#define __KVM_HAVE_GUEST_DEBUG
+#define __KVM_HAVE_IRQ_LINE
+
+#define KVM_REG_SIZE(id)                                                \
+        (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
+
+struct kvm_regs {
+        struct user_pt_regs regs;       /* sp = sp_el0 */
+
+        __u64   sp_el1;
+        __u64   elr_el1;
+
+        __u64   spsr[KVM_NR_SPSR];
+
+        struct user_fpsimd_state fp_regs;
+};
+
+/* Supported Processor Types */
+#define KVM_ARM_TARGET_AEM_V8           0
+#define KVM_ARM_TARGET_FOUNDATION_V8    1
+#define KVM_ARM_TARGET_CORTEX_A57       2
+
+#define KVM_ARM_NUM_TARGETS             3
+
+/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
+#define KVM_ARM_DEVICE_TYPE_SHIFT       0
+#define KVM_ARM_DEVICE_TYPE_MASK        (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
+#define KVM_ARM_DEVICE_ID_SHIFT         16
+#define KVM_ARM_DEVICE_ID_MASK          (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
+
+/* Supported device IDs */
+#define KVM_ARM_DEVICE_VGIC_V2          0
+
+/* Supported VGIC address types  */
+#define KVM_VGIC_V2_ADDR_TYPE_DIST      0
+#define KVM_VGIC_V2_ADDR_TYPE_CPU       1
+
+#define KVM_VGIC_V2_DIST_SIZE           0x1000
+#define KVM_VGIC_V2_CPU_SIZE            0x2000
+
+#define KVM_ARM_VCPU_POWER_OFF          0 /* CPU is started in OFF state */
+#define KVM_ARM_VCPU_EL1_32BIT          1 /* CPU running a 32bit VM */
+
+struct kvm_vcpu_init {
+        __u32 target;
+        __u32 features[7];
+};
+
+struct kvm_sregs {
+};
+
+struct kvm_fpu {
+};
+
+struct kvm_guest_debug_arch {
+};
+
+struct kvm_debug_exit_arch {
+};
+
+struct kvm_sync_regs {
+};
+
+struct kvm_arch_memory_slot {
+};
+
+/* If you need to interpret the index values, here is the key: */
+#define KVM_REG_ARM_COPROC_MASK         0x000000000FFF0000
+#define KVM_REG_ARM_COPROC_SHIFT        16
+
+/* Normal registers are mapped as coprocessor 16. */
+#define KVM_REG_ARM_CORE                (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_CORE_REG(name)      (offsetof(struct kvm_regs, name) / sizeof(__u32))
+
+/* Some registers need more space to represent values. */
+#define KVM_REG_ARM_DEMUX               (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_DEMUX_ID_MASK       0x000000000000FF00
+#define KVM_REG_ARM_DEMUX_ID_SHIFT      8
+#define KVM_REG_ARM_DEMUX_ID_CCSIDR     (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
+#define KVM_REG_ARM_DEMUX_VAL_MASK      0x00000000000000FF
+#define KVM_REG_ARM_DEMUX_VAL_SHIFT     0
+
+/* AArch64 system registers */
+#define KVM_REG_ARM64_SYSREG            (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM64_SYSREG_OP0_MASK   0x000000000000c000
+#define KVM_REG_ARM64_SYSREG_OP0_SHIFT  14
+#define KVM_REG_ARM64_SYSREG_OP1_MASK   0x0000000000003800
+#define KVM_REG_ARM64_SYSREG_OP1_SHIFT  11
+#define KVM_REG_ARM64_SYSREG_CRN_MASK   0x0000000000000780
+#define KVM_REG_ARM64_SYSREG_CRN_SHIFT  7
+#define KVM_REG_ARM64_SYSREG_CRM_MASK   0x0000000000000078
+#define KVM_REG_ARM64_SYSREG_CRM_SHIFT  3
+#define KVM_REG_ARM64_SYSREG_OP2_MASK   0x0000000000000007
+#define KVM_REG_ARM64_SYSREG_OP2_SHIFT  0
+
+/* KVM_IRQ_LINE irq field index values */
+#define KVM_ARM_IRQ_TYPE_SHIFT          24
+#define KVM_ARM_IRQ_TYPE_MASK           0xff
+#define KVM_ARM_IRQ_VCPU_SHIFT          16
+#define KVM_ARM_IRQ_VCPU_MASK           0xff
+#define KVM_ARM_IRQ_NUM_SHIFT           0
+#define KVM_ARM_IRQ_NUM_MASK            0xffff
+
+/* irq_type field */
+#define KVM_ARM_IRQ_TYPE_CPU            0
+#define KVM_ARM_IRQ_TYPE_SPI            1
+#define KVM_ARM_IRQ_TYPE_PPI            2
+
+/* out-of-kernel GIC cpu interrupt injection irq_number field */
+#define KVM_ARM_IRQ_CPU_IRQ             0
+#define KVM_ARM_IRQ_CPU_FIQ             1
+
+/* Highest supported SPI, from VGIC_NR_IRQS */
+#define KVM_ARM_IRQ_GIC_MAX             127
+
+/* PSCI interface */
+#define KVM_PSCI_FN_BASE                0x95c1ba5e
+#define KVM_PSCI_FN(n)                  (KVM_PSCI_FN_BASE + (n))
+
+#define KVM_PSCI_FN_CPU_SUSPEND         KVM_PSCI_FN(0)
+#define KVM_PSCI_FN_CPU_OFF             KVM_PSCI_FN(1)
+#define KVM_PSCI_FN_CPU_ON              KVM_PSCI_FN(2)
+#define KVM_PSCI_FN_MIGRATE             KVM_PSCI_FN(3)
+
+#define KVM_PSCI_RET_SUCCESS            0
+#define KVM_PSCI_RET_NI                 ((unsigned long)-1)
+#define KVM_PSCI_RET_INVAL              ((unsigned long)-2)
+#define KVM_PSCI_RET_DENIED             ((unsigned long)-3)
+
+#endif
+
+#endif /* __ARM_KVM_H__ */