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authorCatalin Marinas <catalin.marinas@arm.com>2013-12-05 11:56:50 -0500
committerCatalin Marinas <catalin.marinas@arm.com>2013-12-06 12:21:52 -0500
commit2f7dc6027522499582a520807cb9ffda589de47e (patch)
treea66a8bbd89cea0bb39e98638d0d805d72dd4a45d /arch/arm64/include
parent85cc00eaa81dfa0f5bf8076c48f3ee2c2c4a77ba (diff)
arm64: Fix memory shareability attribute for ioremap_wc/cache
Write-combine and cacheable mappings use Normal memory on arm64. On SMP systems, the pte needs the shareability bit which is set in pgprot_default. Use this for defining PROT_DEFAULT used by ioremap_wc and ioremap_cache (Device memory is shareable by default, does not need additional attributes). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include')
-rw-r--r--arch/arm64/include/asm/io.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index 4cc813eddacb..572769727227 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -229,7 +229,7 @@ extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot
229extern void __iounmap(volatile void __iomem *addr); 229extern void __iounmap(volatile void __iomem *addr);
230extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); 230extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
231 231
232#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY) 232#define PROT_DEFAULT (pgprot_default | PTE_DIRTY)
233#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE)) 233#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
234#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC)) 234#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))
235#define PROT_NORMAL (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL)) 235#define PROT_NORMAL (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))