diff options
author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2013-12-16 16:04:35 -0500 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2013-12-19 12:44:07 -0500 |
commit | 148eb0a1db8e37a5966afe98223cefe0c1837c26 (patch) | |
tree | 325d739ace4eb1f7834ec6e1a8b6fbbc67276d9c /arch/arm64/include | |
parent | 81cac699440fc3707fd80f16bf34a7e506d41487 (diff) |
arm64: drop redundant macros from read_cpuid()
asm/cputype.h contains a bunch of #defines for CPU id registers
that essentially map to themselves. Remove the #defines and pass
the tokens directly to the inline asm() that reads the registers.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include')
-rw-r--r-- | arch/arm64/include/asm/cputype.h | 18 |
1 files changed, 4 insertions, 14 deletions
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 5fe138e0b828..e1af1b4200d5 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h | |||
@@ -16,23 +16,13 @@ | |||
16 | #ifndef __ASM_CPUTYPE_H | 16 | #ifndef __ASM_CPUTYPE_H |
17 | #define __ASM_CPUTYPE_H | 17 | #define __ASM_CPUTYPE_H |
18 | 18 | ||
19 | #define ID_MIDR_EL1 "midr_el1" | ||
20 | #define ID_MPIDR_EL1 "mpidr_el1" | ||
21 | #define ID_CTR_EL0 "ctr_el0" | ||
22 | |||
23 | #define ID_AA64PFR0_EL1 "id_aa64pfr0_el1" | ||
24 | #define ID_AA64DFR0_EL1 "id_aa64dfr0_el1" | ||
25 | #define ID_AA64AFR0_EL1 "id_aa64afr0_el1" | ||
26 | #define ID_AA64ISAR0_EL1 "id_aa64isar0_el1" | ||
27 | #define ID_AA64MMFR0_EL1 "id_aa64mmfr0_el1" | ||
28 | |||
29 | #define INVALID_HWID ULONG_MAX | 19 | #define INVALID_HWID ULONG_MAX |
30 | 20 | ||
31 | #define MPIDR_HWID_BITMASK 0xff00ffffff | 21 | #define MPIDR_HWID_BITMASK 0xff00ffffff |
32 | 22 | ||
33 | #define read_cpuid(reg) ({ \ | 23 | #define read_cpuid(reg) ({ \ |
34 | u64 __val; \ | 24 | u64 __val; \ |
35 | asm("mrs %0, " reg : "=r" (__val)); \ | 25 | asm("mrs %0, " #reg : "=r" (__val)); \ |
36 | __val; \ | 26 | __val; \ |
37 | }) | 27 | }) |
38 | 28 | ||
@@ -54,12 +44,12 @@ | |||
54 | */ | 44 | */ |
55 | static inline u32 __attribute_const__ read_cpuid_id(void) | 45 | static inline u32 __attribute_const__ read_cpuid_id(void) |
56 | { | 46 | { |
57 | return read_cpuid(ID_MIDR_EL1); | 47 | return read_cpuid(MIDR_EL1); |
58 | } | 48 | } |
59 | 49 | ||
60 | static inline u64 __attribute_const__ read_cpuid_mpidr(void) | 50 | static inline u64 __attribute_const__ read_cpuid_mpidr(void) |
61 | { | 51 | { |
62 | return read_cpuid(ID_MPIDR_EL1); | 52 | return read_cpuid(MPIDR_EL1); |
63 | } | 53 | } |
64 | 54 | ||
65 | static inline unsigned int __attribute_const__ read_cpuid_implementor(void) | 55 | static inline unsigned int __attribute_const__ read_cpuid_implementor(void) |
@@ -74,7 +64,7 @@ static inline unsigned int __attribute_const__ read_cpuid_part_number(void) | |||
74 | 64 | ||
75 | static inline u32 __attribute_const__ read_cpuid_cachetype(void) | 65 | static inline u32 __attribute_const__ read_cpuid_cachetype(void) |
76 | { | 66 | { |
77 | return read_cpuid(ID_CTR_EL0); | 67 | return read_cpuid(CTR_EL0); |
78 | } | 68 | } |
79 | 69 | ||
80 | #endif /* __ASSEMBLY__ */ | 70 | #endif /* __ASSEMBLY__ */ |