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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/arm26
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/arm26')
-rw-r--r--arch/arm26/ACKNOWLEDGEMENTS29
-rw-r--r--arch/arm26/Kconfig227
-rw-r--r--arch/arm26/Kconfig.debug50
-rw-r--r--arch/arm26/Makefile118
-rw-r--r--arch/arm26/boot/Makefile80
-rw-r--r--arch/arm26/boot/compressed/Makefile50
-rw-r--r--arch/arm26/boot/compressed/head.S517
-rw-r--r--arch/arm26/boot/compressed/hw-bse.c74
-rw-r--r--arch/arm26/boot/compressed/ll_char_wr.S162
-rw-r--r--arch/arm26/boot/compressed/misc.c316
-rw-r--r--arch/arm26/boot/compressed/uncompress.h110
-rw-r--r--arch/arm26/boot/compressed/vmlinux.lds.in60
-rw-r--r--arch/arm26/boot/install.sh62
-rw-r--r--arch/arm26/defconfig362
-rw-r--r--arch/arm26/kernel/Makefile17
-rw-r--r--arch/arm26/kernel/armksyms.c220
-rw-r--r--arch/arm26/kernel/asm-offsets.c63
-rw-r--r--arch/arm26/kernel/calls.S265
-rw-r--r--arch/arm26/kernel/compat.c174
-rw-r--r--arch/arm26/kernel/dma.c273
-rw-r--r--arch/arm26/kernel/ecard.c850
-rw-r--r--arch/arm26/kernel/entry.S961
-rw-r--r--arch/arm26/kernel/fiq.c202
-rw-r--r--arch/arm26/kernel/head.S113
-rw-r--r--arch/arm26/kernel/init_task.c49
-rw-r--r--arch/arm26/kernel/irq.c716
-rw-r--r--arch/arm26/kernel/process.c401
-rw-r--r--arch/arm26/kernel/ptrace.c744
-rw-r--r--arch/arm26/kernel/ptrace.h13
-rw-r--r--arch/arm26/kernel/semaphore.c223
-rw-r--r--arch/arm26/kernel/setup.c573
-rw-r--r--arch/arm26/kernel/signal.c540
-rw-r--r--arch/arm26/kernel/sys_arm.c324
-rw-r--r--arch/arm26/kernel/time.c234
-rw-r--r--arch/arm26/kernel/traps.c548
-rw-r--r--arch/arm26/kernel/vmlinux-arm26-xip.lds.in134
-rw-r--r--arch/arm26/kernel/vmlinux-arm26.lds.in127
-rw-r--r--arch/arm26/kernel/vmlinux.lds.S12
-rw-r--r--arch/arm26/lib/Makefile26
-rw-r--r--arch/arm26/lib/ashldi3.c61
-rw-r--r--arch/arm26/lib/ashrdi3.c61
-rw-r--r--arch/arm26/lib/backtrace.S145
-rw-r--r--arch/arm26/lib/changebit.S28
-rw-r--r--arch/arm26/lib/clearbit.S31
-rw-r--r--arch/arm26/lib/copy_page.S62
-rw-r--r--arch/arm26/lib/csumipv6.S32
-rw-r--r--arch/arm26/lib/csumpartial.S130
-rw-r--r--arch/arm26/lib/csumpartialcopy.S52
-rw-r--r--arch/arm26/lib/csumpartialcopygeneric.S352
-rw-r--r--arch/arm26/lib/csumpartialcopyuser.S115
-rw-r--r--arch/arm26/lib/delay.S57
-rw-r--r--arch/arm26/lib/ecard.S41
-rw-r--r--arch/arm26/lib/findbit.S67
-rw-r--r--arch/arm26/lib/floppydma.S32
-rw-r--r--arch/arm26/lib/gcclib.h21
-rw-r--r--arch/arm26/lib/getuser.S112
-rw-r--r--arch/arm26/lib/io-acorn.S71
-rw-r--r--arch/arm26/lib/io-readsb.S116
-rw-r--r--arch/arm26/lib/io-readsl.S78
-rw-r--r--arch/arm26/lib/io-readsw.S107
-rw-r--r--arch/arm26/lib/io-writesb.S122
-rw-r--r--arch/arm26/lib/io-writesl.S56
-rw-r--r--arch/arm26/lib/io-writesw.S127
-rw-r--r--arch/arm26/lib/kbd.c279
-rw-r--r--arch/arm26/lib/lib1funcs.S314
-rw-r--r--arch/arm26/lib/longlong.h184
-rw-r--r--arch/arm26/lib/lshrdi3.c61
-rw-r--r--arch/arm26/lib/memchr.S25
-rw-r--r--arch/arm26/lib/memcpy.S318
-rw-r--r--arch/arm26/lib/memset.S80
-rw-r--r--arch/arm26/lib/memzero.S80
-rw-r--r--arch/arm26/lib/muldi3.c77
-rw-r--r--arch/arm26/lib/putuser.S109
-rw-r--r--arch/arm26/lib/setbit.S29
-rw-r--r--arch/arm26/lib/strchr.S25
-rw-r--r--arch/arm26/lib/strrchr.S25
-rw-r--r--arch/arm26/lib/testchangebit.S29
-rw-r--r--arch/arm26/lib/testclearbit.S29
-rw-r--r--arch/arm26/lib/testsetbit.S29
-rw-r--r--arch/arm26/lib/uaccess-kernel.S173
-rw-r--r--arch/arm26/lib/uaccess-user.S718
-rw-r--r--arch/arm26/lib/ucmpdi2.c51
-rw-r--r--arch/arm26/lib/udivdi3.c242
-rw-r--r--arch/arm26/machine/Makefile8
-rw-r--r--arch/arm26/machine/dma.c215
-rw-r--r--arch/arm26/machine/irq.c165
-rw-r--r--arch/arm26/machine/latches.c72
-rw-r--r--arch/arm26/mm/Makefile6
-rw-r--r--arch/arm26/mm/extable.c25
-rw-r--r--arch/arm26/mm/fault.c318
-rw-r--r--arch/arm26/mm/fault.h5
-rw-r--r--arch/arm26/mm/init.c412
-rw-r--r--arch/arm26/mm/memc.c202
-rw-r--r--arch/arm26/mm/proc-funcs.S359
-rw-r--r--arch/arm26/mm/small_page.c194
-rw-r--r--arch/arm26/nwfpe/ARM-gcc.h120
-rw-r--r--arch/arm26/nwfpe/ChangeLog83
-rw-r--r--arch/arm26/nwfpe/Makefile15
-rw-r--r--arch/arm26/nwfpe/double_cpdo.c288
-rw-r--r--arch/arm26/nwfpe/entry.S114
-rw-r--r--arch/arm26/nwfpe/extended_cpdo.c273
-rw-r--r--arch/arm26/nwfpe/fpa11.c221
-rw-r--r--arch/arm26/nwfpe/fpa11.h87
-rw-r--r--arch/arm26/nwfpe/fpa11.inl51
-rw-r--r--arch/arm26/nwfpe/fpa11_cpdo.c117
-rw-r--r--arch/arm26/nwfpe/fpa11_cpdt.c368
-rw-r--r--arch/arm26/nwfpe/fpa11_cprt.c289
-rw-r--r--arch/arm26/nwfpe/fpmodule.c182
-rw-r--r--arch/arm26/nwfpe/fpmodule.h47
-rw-r--r--arch/arm26/nwfpe/fpmodule.inl84
-rw-r--r--arch/arm26/nwfpe/fpopcode.c148
-rw-r--r--arch/arm26/nwfpe/fpopcode.h390
-rw-r--r--arch/arm26/nwfpe/fpsr.h108
-rw-r--r--arch/arm26/nwfpe/milieu.h48
-rw-r--r--arch/arm26/nwfpe/single_cpdo.c255
-rw-r--r--arch/arm26/nwfpe/softfloat-macros740
-rw-r--r--arch/arm26/nwfpe/softfloat-specialize366
-rw-r--r--arch/arm26/nwfpe/softfloat.c3439
-rw-r--r--arch/arm26/nwfpe/softfloat.h232
119 files changed, 25018 insertions, 0 deletions
diff --git a/arch/arm26/ACKNOWLEDGEMENTS b/arch/arm26/ACKNOWLEDGEMENTS
new file mode 100644
index 000000000000..0a17a45110e7
--- /dev/null
+++ b/arch/arm26/ACKNOWLEDGEMENTS
@@ -0,0 +1,29 @@
1The work in this architecture (ARM26) is that of a great many people.
2
3This is what has happened:
4
5I [Ian Molton] have been trying to repair the ARM26 architecture support, but it has become an impossible task whilst it is still merged with the ARM32 (arch/arm) code. The ARM26 code is too different to be sensible to keep with the ARM32 code now, and Russell King really doesnt have the time to maintain the ARM26 code. Add to that that most ARM32 developers dont know about or care about ARM26 when writing patches, and you have a reall mess.
6
7As a result, I've split it off into a new architecture of its own. I've named it arm26 since these CPUs have only a 26 bit address space, unlike the other ARMs.
8
9The upheaval in moving around so many source files and chopping out vasty ammounts of cruft was enormous, and the copyright of many files is sometimes unclear. Because of this, I am writing this, in order that no-one is left out / misaccredited / blamed for any of the code.
10
11People I KNOW have made major contributions to the code:
12
13David Alan Gilbert (former maintainer of ARM26 bits)
14Philip Blundell
15Russell King
16Keith Owens
17
18also thanks to Nicholas Pitre for hints, and for the basis or our XIP support.
19
20Currently maintaing the code are
21
22Ian Molton (Maintainer / Archimedes)
23John Appleby (kernel / A5K)
24
25If anyone has a problem with attributions in header files / source files, please do contact me to straighten things out.
26
27Ian Molton (aka spyro) - ARM26 maintainer
28spyro@f2s.com
29
diff --git a/arch/arm26/Kconfig b/arch/arm26/Kconfig
new file mode 100644
index 000000000000..3955de5af4c0
--- /dev/null
+++ b/arch/arm26/Kconfig
@@ -0,0 +1,227 @@
1#
2# For a description of the syntax of this configuration file,
3# see Documentation/kbuild/kconfig-language.txt.
4#
5
6mainmenu "Linux Kernel Configuration"
7
8config ARM
9 bool
10 default y
11
12config ARM26
13 bool
14 default y
15
16config MMU
17 bool
18 default y
19
20config ARCH_ACORN
21 bool
22 default y
23
24config CPU_26
25 bool
26 default y
27
28config FIQ
29 bool
30 default y
31
32# 9 = 512 pages 8 = 256 pages 7 = 128 pages
33config FORCE_MAX_ZONEORDER
34 int
35 default 9
36
37config UID16
38 bool
39 default y
40
41config RWSEM_GENERIC_SPINLOCK
42 bool
43 default y
44
45config RWSEM_XCHGADD_ALGORITHM
46 bool
47
48config GENERIC_CALIBRATE_DELAY
49 bool
50 default y
51
52config GENERIC_BUST_SPINLOCK
53 bool
54
55config GENERIC_ISA_DMA
56 bool
57
58source "init/Kconfig"
59
60
61menu "System Type"
62
63comment "Archimedes/A5000 Implementations (select only ONE)"
64
65config ARCH_ARC
66 bool "Archimedes"
67 help
68 Say Y to support the Acorn Archimedes.
69
70 The Acorn Archimedes was an personal computer based on an 8MHz ARM2
71 processor, released in 1987. It supported up to 16MB of RAM in
72 later models and floppy, harddisc, ethernet etc.
73
74config ARCH_A5K
75 bool "A5000"
76 help
77 Say Y here to to support the Acorn A5000.
78
79 Linux can support the
80 internal IDE disk and CD-ROM interface, serial and parallel port,
81 and the floppy drive. Note that on some A5000s the floppy is
82 plugged into the wrong socket on the motherboard.
83
84config PAGESIZE_16
85 bool "2MB physical memory (broken)"
86 help
87 Say Y here if your Archimedes or A5000 system has only 2MB of
88 memory, otherwise say N. The resulting kernel will not run on a
89 machine with 4MB of memory.
90endmenu
91
92menu "General setup"
93
94# Compressed boot loader in ROM. Yes, we really want to ask about
95# TEXT and BSS so we preserve their values in the config files.
96config ZBOOT_ROM
97 bool "Compressed boot loader in ROM/flash"
98 help
99 Say Y here if you intend to execute your compressed kernel image (zImage)
100 directly from ROM or flash. If unsure, say N.
101
102config ZBOOT_ROM_TEXT
103 depends on ZBOOT_ROM
104 hex "Compressed ROM boot loader base address"
105 default "0"
106 help
107 The base address for zImage. Unless you have special requirements, you
108 should not change this value.
109
110config ZBOOT_ROM_BSS
111 depends on ZBOOT_ROM
112 hex "Compressed ROM boot loader BSS address"
113 default "0"
114 help
115 The base address of 64KiB of read/write memory, which must be available
116 while the decompressor is running. Unless you have special requirements,
117 you should not change this value.
118
119config XIP_KERNEL
120 bool "Execute In Place (XIP) kernel image"
121 help
122 Select this option to create a kernel that can be programed into
123 the OS ROMs.
124
125comment "At least one math emulation must be selected"
126
127config FPE_NWFPE
128 tristate "NWFPE math emulation"
129 ---help---
130 Say Y to include the NWFPE floating point emulator in the kernel.
131 This is necessary to run most binaries. Linux does not currently
132 support floating point hardware so you need to say Y here even if
133 your machine has an FPA or floating point co-processor podule.
134
135 It is also possible to say M to build the emulator as a module
136 (nwfpe) or indeed to leave it out altogether. However, unless you
137 know what you are doing this can easily render your machine
138 unbootable. Saying Y is the safe option.
139
140 You may say N here if you are going to load the Acorn FPEmulator
141 early in the bootup.
142
143source "fs/Kconfig.binfmt"
144
145config PREEMPT
146 bool "Preemptible Kernel (EXPERIMENTAL)"
147 depends on CPU_32 && EXPERIMENTAL
148 help
149 This option reduces the latency of the kernel when reacting to
150 real-time or interactive events by allowing a low priority process to
151 be preempted even if it is in kernel mode executing a system call.
152 This allows applications to run more reliably even when the system is
153 under load.
154
155 Say Y here if you are building a kernel for a desktop, embedded
156 or real-time system. Say N if you are unsure.
157
158config ARTHUR
159 tristate "RISC OS personality"
160 depends on CPU_32
161 help
162 Say Y here to include the kernel code necessary if you want to run
163 Acorn RISC OS/Arthur binaries under Linux. This code is still very
164 experimental; if this sounds frightening, say N and sleep in peace.
165 You can also say M here to compile this support as a module (which
166 will be called arthur).
167
168config CMDLINE
169 string "Default kernel command string"
170 default ""
171 help
172 On some architectures (EBSA110 and CATS), there is currently no way
173 for the boot loader to pass arguments to the kernel. For these
174 architectures, you should supply some command-line options at build
175 time by entering them here. As a minimum, you should specify the
176 memory size and the root device (e.g., mem=64M root=/dev/nfs).
177
178endmenu
179
180source "drivers/base/Kconfig"
181
182source "drivers/parport/Kconfig"
183
184source "drivers/pnp/Kconfig"
185
186source "drivers/block/Kconfig"
187
188source "drivers/md/Kconfig"
189
190source "net/Kconfig"
191
192source "drivers/ide/Kconfig"
193
194source "drivers/scsi/Kconfig"
195
196source "drivers/isdn/Kconfig"
197
198#
199# input before char - char/joystick depends on it. As does USB.
200#
201source "drivers/input/Kconfig"
202
203source "drivers/char/Kconfig"
204
205source "drivers/media/Kconfig"
206
207source "fs/Kconfig"
208
209source "drivers/video/Kconfig"
210
211if ARCH_ACORN
212
213source "sound/Kconfig"
214
215endif
216
217source "drivers/misc/Kconfig"
218
219source "drivers/usb/Kconfig"
220
221source "arch/arm26/Kconfig.debug"
222
223source "security/Kconfig"
224
225source "crypto/Kconfig"
226
227source "lib/Kconfig"
diff --git a/arch/arm26/Kconfig.debug b/arch/arm26/Kconfig.debug
new file mode 100644
index 000000000000..611fc86503fc
--- /dev/null
+++ b/arch/arm26/Kconfig.debug
@@ -0,0 +1,50 @@
1menu "Kernel hacking"
2
3source "lib/Kconfig.debug"
4
5# RMK wants arm kernels compiled with frame pointers so hardwire this to y.
6# If you know what you are doing and are willing to live without stack
7# traces, you can get a slightly smaller kernel by setting this option to
8# n, but then RMK will have to kill you ;).
9config FRAME_POINTER
10 bool
11 default y
12 help
13 If you say N here, the resulting kernel will be slightly smaller and
14 faster. However, when a problem occurs with the kernel, the
15 information that is reported is severely limited. Most people
16 should say Y here.
17
18config DEBUG_USER
19 bool "Verbose user fault messages"
20 help
21 When a user program crashes due to an exception, the kernel can
22 print a brief message explaining what the problem was. This is
23 sometimes helpful for debugging but serves no purpose on a
24 production system. Most people should say N here.
25
26config DEBUG_WAITQ
27 bool "Wait queue debugging"
28 depends on DEBUG_KERNEL
29
30config DEBUG_ERRORS
31 bool "Verbose kernel error messages"
32 depends on DEBUG_KERNEL
33 help
34 This option controls verbose debugging information which can be
35 printed when the kernel detects an internal error. This debugging
36 information is useful to kernel hackers when tracking down problems,
37 but mostly meaningless to other people. It's safe to say Y unless
38 you are concerned with the code size or don't want to see these
39 messages.
40
41# These options are only for real kernel hackers who want to get their hands dirty.
42config DEBUG_LL
43 bool "Kernel low-level debugging functions"
44 depends on DEBUG_KERNEL
45 help
46 Say Y here to include definitions of printascii, printchar, printhex
47 in the kernel. This is helpful if you are debugging code that
48 executes before the console is initialized.
49
50endmenu
diff --git a/arch/arm26/Makefile b/arch/arm26/Makefile
new file mode 100644
index 000000000000..ada8985530a5
--- /dev/null
+++ b/arch/arm26/Makefile
@@ -0,0 +1,118 @@
1#
2# arch/arm26/Makefile
3#
4# This file is subject to the terms and conditions of the GNU General Public
5# License. See the file "COPYING" in the main directory of this archive
6# for more details.
7#
8# Copyright (C) 1995-2001 by Russell King
9# Copyright (c) 2004 Ian Molton
10
11LDFLAGS_vmlinux :=-p -X
12CPPFLAGS_vmlinux.lds = -DTEXTADDR=$(TEXTADDR) -DDATAADDR=$(DATAADDR)
13OBJCOPYFLAGS :=-O binary -R .note -R .comment -S
14GZFLAGS :=-9
15
16ifeq ($(CONFIG_FRAME_POINTER),y)
17CFLAGS +=-fno-omit-frame-pointer -mno-sched-prolog
18endif
19
20ifeq ($(CONFIG_DEBUG_INFO),y)
21CFLAGS +=-g
22endif
23
24CFLAGS_BOOT :=-mapcs-26 -mcpu=arm3 -msoft-float -Uarm
25CFLAGS +=-mapcs-26 -mcpu=arm3 -msoft-float -Uarm
26AFLAGS +=-mapcs-26 -mcpu=arm3 -msoft-float
27
28ifeq ($(CONFIG_XIP_KERNEL),y)
29 TEXTADDR := 0x03880000
30 DATAADDR := 0x02080000
31else
32 TEXTADDR := 0x02080000
33 DATAADDR := .
34endif
35
36head-y := arch/arm26/kernel/head.o arch/arm26/kernel/init_task.o
37
38ifeq ($(incdir-y),)
39incdir-y :=
40endif
41INCDIR :=
42
43export MACHINE TEXTADDR GZFLAGS CFLAGS_BOOT
44
45# If we have a machine-specific directory, then include it in the build.
46core-y += arch/arm26/kernel/ arch/arm26/mm/ arch/arm26/machine/
47core-$(CONFIG_FPE_NWFPE) += arch/arm26/nwfpe/
48
49libs-y += arch/arm26/lib/
50
51# Default target when executing plain make
52all: zImage
53
54boot := arch/arm26/boot
55
56prepare: include/asm-$(ARCH)/asm_offsets.h
57CLEAN_FILES += include/asm-$(ARCH)/asm_offsets.h
58
59
60.PHONY: maketools FORCE
61maketools: FORCE
62
63
64# Convert bzImage to zImage
65bzImage: vmlinux
66 $(Q)$(MAKE) $(build)=$(boot) $(boot)/zImage
67
68zImage Image bootpImage xipImage: vmlinux
69 $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
70
71zinstall install: vmlinux
72 $(Q)$(MAKE) $(build)=$(boot) $@
73
74# We use MRPROPER_FILES and CLEAN_FILES now
75archclean:
76 $(Q)$(MAKE) $(clean)=$(boot)
77
78# My testing targets (that short circuit a few dependencies)
79zImg:; $(Q)$(MAKE) $(build)=$(boot) $(boot)/zImage
80Img:; $(Q)$(MAKE) $(build)=$(boot) $(boot)/Image
81bp:; $(Q)$(MAKE) $(build)=$(boot) $(boot)/bootpImage
82i:; $(Q)$(MAKE) $(build)=$(boot) install
83zi:; $(Q)$(MAKE) $(build)=$(boot) zinstall
84
85#
86# Configuration targets. Use these to select a
87# configuration for your architecture
88%_config:
89 @( \
90 CFG=$(@:_config=); \
91 if [ -f arch/arm26/def-configs/$$CFG ]; then \
92 [ -f .config ] && mv -f .config .config.old; \
93 cp arch/arm26/def-configs/$$CFG .config; \
94 echo "*** Default configuration for $$CFG installed"; \
95 echo "*** Next, you may run 'make oldconfig'"; \
96 else \
97 echo "$$CFG does not exist"; \
98 fi; \
99 )
100
101arch/$(ARCH)/kernel/asm-offsets.s: include/asm include/linux/version.h \
102 include/config/MARKER
103
104include/asm-$(ARCH)/asm_offsets.h: arch/$(ARCH)/kernel/asm-offsets.s
105 $(call filechk,gen-asm-offsets)
106
107define archhelp
108 echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)'
109 echo ' Image - Uncompressed kernel image (arch/$(ARCH)/boot/Image)'
110 echo ' bootpImage - Combined zImage and initial RAM disk'
111 echo ' xipImage - eXecute In Place capable image for ROM use (arch/$(ARCH)/boot/xipImage)'
112 echo ' initrd - Create an initial image'
113 echo ' install - Install uncompressed kernel'
114 echo ' zinstall - Install compressed kernel'
115 echo ' Install using (your) ~/bin/installkernel or'
116 echo ' (distribution) /sbin/installkernel or'
117 echo ' install to $$(INSTALL_PATH) and run lilo'
118endef
diff --git a/arch/arm26/boot/Makefile b/arch/arm26/boot/Makefile
new file mode 100644
index 000000000000..b5c2277654d4
--- /dev/null
+++ b/arch/arm26/boot/Makefile
@@ -0,0 +1,80 @@
1#
2# arch/arm26/boot/Makefile
3#
4# This file is subject to the terms and conditions of the GNU General Public
5# License. See the file "COPYING" in the main directory of this archive
6# for more details.
7#
8# Copyright (C) 1995-2002 Russell King
9#
10
11# Note: the following conditions must always be true:
12# ZRELADDR == virt_to_phys(TEXTADDR)
13# PARAMS_PHYS must be with 4MB of ZRELADDR
14# INITRD_PHYS must be in RAM
15
16 zreladdr-y := 0x02080000
17params_phys-y := 0x0207c000
18initrd_phys-y := 0x02180000
19
20ZRELADDR := 0x02080000
21ZTEXTADDR := 0x0207c000
22PARAMS_PHYS := $(params_phys-y)
23INITRD_PHYS := 0x02180000
24
25# We now have a PIC decompressor implementation. Decompressors running
26# from RAM should not define ZTEXTADDR. Decompressors running directly
27# from ROM or Flash must define ZTEXTADDR (preferably via the config)
28# FIXME: Previous assignment to ztextaddr-y is lost here. See SHARK
29ifeq ($(CONFIG_ZBOOT_ROM),y)
30ZTEXTADDR := $(CONFIG_ZBOOT_ROM_TEXT)
31ZBSSADDR := $(CONFIG_ZBOOT_ROM_BSS)
32else
33ZTEXTADDR := 0
34ZBSSADDR := ALIGN(4)
35endif
36
37export ZTEXTADDR ZBSSADDR ZRELADDR INITRD_PHYS PARAMS_PHYS
38
39targets := Image zImage bootpImage xipImage
40
41$(obj)/Image: vmlinux FORCE
42 $(call if_changed,objcopy)
43 @echo ' Kernel: $@ is ready'
44
45$(obj)/zImage: $(obj)/compressed/vmlinux FORCE
46 $(call if_changed,objcopy)
47 @echo ' Kernel: $@ is ready'
48
49$(obj)/compressed/vmlinux: vmlinux FORCE
50 $(Q)$(MAKE) $(build)=$(obj)/compressed $@
51
52ifeq ($(CONFIG_XIP_KERNEL),y)
53$(obj)/xipImage: vmlinux FORCE
54# $(OBJCOPY) -S -O binary -R .data -R .comment vmlinux vmlinux-text.bin
55# FIXME - where has .pci_fixup crept in from?
56 $(OBJCOPY) -S -O binary -R .data -R .pci_fixup -R .comment vmlinux vmlinux-text.bin
57 $(OBJCOPY) -S -O binary -R .init -R .text -R __ex_table -R .pci_fixup -R __ksymtab -R __ksymtab_gpl -R __kcrctab -R __kcrctab_gpl -R __param -R .comment vmlinux vmlinux-data.bin
58 cat vmlinux-text.bin vmlinux-data.bin > $@
59 $(RM) -f vmlinux-text.bin vmlinux-data.bin
60 @echo ' Kernel: $@ is ready'
61endif
62
63.PHONY: initrd
64initrd:
65 @test "$(INITRD_PHYS)" != "" || \
66 (echo This machine does not support INITRD; exit -1)
67 @test "$(INITRD)" != "" || \
68 (echo You must specify INITRD; exit -1)
69
70install: $(obj)/Image
71 $(CONFIG_SHELL) $(obj)/install.sh \
72 $(KERNELRELEASE) \
73 $(obj)/Image System.map "$(INSTALL_PATH)"
74
75zinstall: $(obj)/zImage
76 $(CONFIG_SHELL) $(obj)/install.sh \
77 $(KERNELRELEASE) \
78 $(obj)/zImage System.map "$(INSTALL_PATH)"
79
80subdir- := compressed
diff --git a/arch/arm26/boot/compressed/Makefile b/arch/arm26/boot/compressed/Makefile
new file mode 100644
index 000000000000..b1d9ddebbe74
--- /dev/null
+++ b/arch/arm26/boot/compressed/Makefile
@@ -0,0 +1,50 @@
1#
2# linux/arch/arm26/boot/compressed/Makefile
3#
4# create a compressed vmlinuz image from the original vmlinux
5#
6# Note! ZTEXTADDR, ZBSSADDR and ZRELADDR are now exported
7# from arch/arm26/boot/Makefile
8#
9
10HEAD = head.o
11OBJS = misc.o
12FONTC = drivers/video/console/font_acorn_8x8.c
13
14OBJS += ll_char_wr.o font.o
15CFLAGS_misc.o := -DPARAMS_PHYS=$(PARAMS_PHYS)
16
17targets := vmlinux vmlinux.lds piggy piggy.gz piggy.o font.o head.o $(OBJS)
18
19SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/LOAD_ADDR/$(ZRELADDR)/;s/BSS_START/$(ZBSSADDR)/
20
21EXTRA_CFLAGS := $(CFLAGS_BOOT) -fpic
22EXTRA_AFLAGS := -traditional
23
24LDFLAGS_vmlinux := -p -X \
25 $(shell $(CC) $(CFLAGS)) -T
26
27$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.o \
28 $(addprefix $(obj)/, $(OBJS)) FORCE
29 $(call if_changed,ld)
30 @:
31
32
33$(obj)/piggy: vmlinux FORCE
34 $(call if_changed,objcopy)
35
36$(obj)/piggy.gz: $(obj)/piggy FORCE
37 $(call if_changed,gzip)
38
39LDFLAGS_piggy.o := -r -b binary
40$(obj)/piggy.o: $(obj)/piggy.gz FORCE
41 $(call if_changed,ld)
42
43$(obj)/font.o: $(FONTC)
44 $(CC) $(CFLAGS) -Dstatic= -c $(FONTC) -o $(obj)/font.o
45
46$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in Makefile arch/arm26/boot/Makefile .config
47 @sed "$(SEDFLAGS)" < $< > $@
48
49$(obj)/misc.o: $(obj)/misc.c $(obj)/uncompress.h lib/inflate.c
50
diff --git a/arch/arm26/boot/compressed/head.S b/arch/arm26/boot/compressed/head.S
new file mode 100644
index 000000000000..0307804a6070
--- /dev/null
+++ b/arch/arm26/boot/compressed/head.S
@@ -0,0 +1,517 @@
1/*
2 * linux/arch/arm26/boot/compressed/head.S
3 *
4 * Copyright (C) 1996-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/config.h>
11#include <linux/linkage.h>
12
13/*
14 * Debugging stuff
15 *
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
19 */
20
21 .macro kputc,val
22 mov r0, \val
23 bl putc
24 .endm
25
26 .macro kphex,val,len
27 mov r0, \val
28 mov r1, #\len
29 bl phex
30 .endm
31
32 .macro debug_reloc_start
33 .endm
34
35 .macro debug_reloc_end
36 .endm
37
38 .section ".start", #alloc, #execinstr
39/*
40 * sort out different calling conventions
41 */
42 .align
43start:
44 .type start,#function
45 .rept 8
46 mov r0, r0
47 .endr
48
49 b 1f
50 .word 0x016f2818 @ Magic numbers to help the loader
51 .word start @ absolute load/run zImage address
52 .word _edata @ zImage end address
531: mov r7, r1 @ save architecture ID
54 mov r8, #0 @ save r0
55 teqp pc, #0x0c000003 @ turn off interrupts
56
57 .text
58 adr r0, LC0
59 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
60 subs r0, r0, r1 @ calculate the delta offset
61
62 teq r0, #0 @ if delta is zero, we're
63 beq not_relocated @ running at the address we
64 @ were linked at.
65
66 add r2, r2, r0 @ different address, so we
67 add r3, r3, r0 @ need to fix up various
68 add r5, r5, r0 @ pointers.
69 add r6, r6, r0
70 add ip, ip, r0
71 add sp, sp, r0
72
731: ldr r1, [r6, #0] @ relocate entries in the GOT
74 add r1, r1, r0 @ table. This fixes up the
75 str r1, [r6], #4 @ C references.
76 cmp r6, ip
77 blo 1b
78
79not_relocated: mov r0, #0
801: str r0, [r2], #4 @ clear bss
81 str r0, [r2], #4
82 str r0, [r2], #4
83 str r0, [r2], #4
84 cmp r2, r3
85 blo 1b
86
87 bl cache_on
88
89 mov r1, sp @ malloc space above stack
90 add r2, sp, #0x10000 @ 64k max
91
92/*
93 * Check to see if we will overwrite ourselves.
94 * r4 = final kernel address
95 * r5 = start of this image
96 * r2 = end of malloc space (and therefore this image)
97 * We basically want:
98 * r4 >= r2 -> OK
99 * r4 + image length <= r5 -> OK
100 */
101 cmp r4, r2
102 bhs wont_overwrite
103 add r0, r4, #4096*1024 @ 4MB largest kernel size
104 cmp r0, r5
105 bls wont_overwrite
106
107 mov r5, r2 @ decompress after malloc space
108 mov r0, r5
109 mov r3, r7
110 bl decompress_kernel
111
112 add r0, r0, #127
113 bic r0, r0, #127 @ align the kernel length
114/*
115 * r0 = decompressed kernel length
116 * r1-r3 = unused
117 * r4 = kernel execution address
118 * r5 = decompressed kernel start
119 * r6 = processor ID
120 * r7 = architecture ID
121 * r8-r14 = unused
122 */
123 add r1, r5, r0 @ end of decompressed kernel
124 adr r2, reloc_start
125 ldr r3, LC1
126 add r3, r2, r3
1271: ldmia r2!, {r8 - r13} @ copy relocation code
128 stmia r1!, {r8 - r13}
129 ldmia r2!, {r8 - r13}
130 stmia r1!, {r8 - r13}
131 cmp r2, r3
132 blo 1b
133
134 bl cache_clean_flush
135 add pc, r5, r0 @ call relocation code
136
137/*
138 * We're not in danger of overwriting ourselves. Do this the simple way.
139 *
140 * r4 = kernel execution address
141 * r7 = architecture ID
142 */
143wont_overwrite: mov r0, r4
144 mov r3, r7
145 bl decompress_kernel
146 b call_kernel
147
148 .type LC0, #object
149LC0: .word LC0 @ r1
150 .word __bss_start @ r2
151 .word _end @ r3
152 .word _load_addr @ r4
153 .word _start @ r5
154 .word _got_start @ r6
155 .word _got_end @ ip
156 .word user_stack+4096 @ sp
157LC1: .word reloc_end - reloc_start
158 .size LC0, . - LC0
159
160/*
161 * Turn on the cache. We need to setup some page tables so that we
162 * can have both the I and D caches on.
163 *
164 * We place the page tables 16k down from the kernel execution address,
165 * and we hope that nothing else is using it. If we're using it, we
166 * will go pop!
167 *
168 * On entry,
169 * r4 = kernel execution address
170 * r6 = processor ID
171 * r7 = architecture number
172 * r8 = run-time address of "start"
173 * On exit,
174 * r1, r2, r3, r8, r9, r12 corrupted
175 * This routine must preserve:
176 * r4, r5, r6, r7
177 */
178 .align 5
179cache_on: mov r3, #8 @ cache_on function
180 b call_cache_fn
181
182__setup_mmu: sub r3, r4, #16384 @ Page directory size
183 bic r3, r3, #0xff @ Align the pointer
184 bic r3, r3, #0x3f00
185/*
186 * Initialise the page tables, turning on the cacheable and bufferable
187 * bits for the RAM area only.
188 */
189 mov r0, r3
190 mov r8, r0, lsr #18
191 mov r8, r8, lsl #18 @ start of RAM
192 add r9, r8, #0x10000000 @ a reasonable RAM size
193 mov r1, #0x12
194 orr r1, r1, #3 << 10
195 add r2, r3, #16384
1961: cmp r1, r8 @ if virt > start of RAM
197 orrhs r1, r1, #0x0c @ set cacheable, bufferable
198 cmp r1, r9 @ if virt > end of RAM
199 bichs r1, r1, #0x0c @ clear cacheable, bufferable
200 str r1, [r0], #4 @ 1:1 mapping
201 add r1, r1, #1048576
202 teq r0, r2
203 bne 1b
204/*
205 * If ever we are running from Flash, then we surely want the cache
206 * to be enabled also for our execution instance... We map 2MB of it
207 * so there is no map overlap problem for up to 1 MB compressed kernel.
208 * If the execution is in RAM then we would only be duplicating the above.
209 */
210 mov r1, #0x1e
211 orr r1, r1, #3 << 10
212 mov r2, pc, lsr #20
213 orr r1, r1, r2, lsl #20
214 add r0, r3, r2, lsl #2
215 str r1, [r0], #4
216 add r1, r1, #1048576
217 str r1, [r0]
218 mov pc, lr
219
220__armv4_cache_on:
221 mov r12, lr
222 bl __setup_mmu
223 mov r0, #0
224 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
225 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
226 mrc p15, 0, r0, c1, c0, 0 @ read control reg
227 orr r0, r0, #0x1000 @ I-cache enable
228 orr r0, r0, #0x0030
229 b __common_cache_on
230
231__arm6_cache_on:
232 mov r12, lr
233 bl __setup_mmu
234 mov r0, #0
235 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
236 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
237 mov r0, #0x30
238__common_cache_on:
239#ifndef DEBUG
240 orr r0, r0, #0x000d @ Write buffer, mmu
241#endif
242 mov r1, #-1
243 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
244 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
245 mcr p15, 0, r0, c1, c0, 0 @ load control register
246 mov pc, r12
247
248/*
249 * All code following this line is relocatable. It is relocated by
250 * the above code to the end of the decompressed kernel image and
251 * executed there. During this time, we have no stacks.
252 *
253 * r0 = decompressed kernel length
254 * r1-r3 = unused
255 * r4 = kernel execution address
256 * r5 = decompressed kernel start
257 * r6 = processor ID
258 * r7 = architecture ID
259 * r8-r14 = unused
260 */
261 .align 5
262reloc_start: add r8, r5, r0
263 debug_reloc_start
264 mov r1, r4
2651:
266 .rept 4
267 ldmia r5!, {r0, r2, r3, r9 - r13} @ relocate kernel
268 stmia r1!, {r0, r2, r3, r9 - r13}
269 .endr
270
271 cmp r5, r8
272 blo 1b
273 debug_reloc_end
274
275call_kernel: bl cache_clean_flush
276 bl cache_off
277 mov r0, #0
278 mov r1, r7 @ restore architecture number
279 mov pc, r4 @ call kernel
280
281/*
282 * Here follow the relocatable cache support functions for the
283 * various processors. This is a generic hook for locating an
284 * entry and jumping to an instruction at the specified offset
285 * from the start of the block. Please note this is all position
286 * independent code.
287 *
288 * r1 = corrupted
289 * r2 = corrupted
290 * r3 = block offset
291 * r6 = corrupted
292 * r12 = corrupted
293 */
294
295call_cache_fn: adr r12, proc_types
296 mrc p15, 0, r6, c0, c0 @ get processor ID
2971: ldr r1, [r12, #0] @ get value
298 ldr r2, [r12, #4] @ get mask
299 eor r1, r1, r6 @ (real ^ match)
300 tst r1, r2 @ & mask
301 addeq pc, r12, r3 @ call cache function
302 add r12, r12, #4*5
303 b 1b
304
305/*
306 * Table for cache operations. This is basically:
307 * - CPU ID match
308 * - CPU ID mask
309 * - 'cache on' method instruction
310 * - 'cache off' method instruction
311 * - 'cache flush' method instruction
312 *
313 * We match an entry using: ((real_id ^ match) & mask) == 0
314 *
315 * Writethrough caches generally only need 'on' and 'off'
316 * methods. Writeback caches _must_ have the flush method
317 * defined.
318 */
319 .type proc_types,#object
320proc_types:
321 .word 0x41560600 @ ARM6/610
322 .word 0xffffffe0
323 b __arm6_cache_off @ works, but slow
324 b __arm6_cache_off
325 mov pc, lr
326@ b __arm6_cache_on @ untested
327@ b __arm6_cache_off
328@ b __armv3_cache_flush
329
330 .word 0x41007000 @ ARM7/710
331 .word 0xfff8fe00
332 b __arm7_cache_off
333 b __arm7_cache_off
334 mov pc, lr
335
336 .word 0x41807200 @ ARM720T (writethrough)
337 .word 0xffffff00
338 b __armv4_cache_on
339 b __armv4_cache_off
340 mov pc, lr
341
342 .word 0x41129200 @ ARM920T
343 .word 0xff00fff0
344 b __armv4_cache_on
345 b __armv4_cache_off
346 b __armv4_cache_flush
347
348 .word 0x4401a100 @ sa110 / sa1100
349 .word 0xffffffe0
350 b __armv4_cache_on
351 b __armv4_cache_off
352 b __armv4_cache_flush
353
354 .word 0x6901b110 @ sa1110
355 .word 0xfffffff0
356 b __armv4_cache_on
357 b __armv4_cache_off
358 b __armv4_cache_flush
359
360 .word 0x69050000 @ xscale
361 .word 0xffff0000
362 b __armv4_cache_on
363 b __armv4_cache_off
364 b __armv4_cache_flush
365
366 .word 0 @ unrecognised type
367 .word 0
368 mov pc, lr
369 mov pc, lr
370 mov pc, lr
371
372 .size proc_types, . - proc_types
373
374/*
375 * Turn off the Cache and MMU. ARMv3 does not support
376 * reading the control register, but ARMv4 does.
377 *
378 * On entry, r6 = processor ID
379 * On exit, r0, r1, r2, r3, r12 corrupted
380 * This routine must preserve: r4, r6, r7
381 */
382 .align 5
383cache_off: mov r3, #12 @ cache_off function
384 b call_cache_fn
385
386__armv4_cache_off:
387 mrc p15, 0, r0, c1, c0
388 bic r0, r0, #0x000d
389 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
390 mov r0, #0
391 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
392 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
393 mov pc, lr
394
395__arm6_cache_off:
396 mov r0, #0x00000030 @ ARM6 control reg.
397 b __armv3_cache_off
398
399__arm7_cache_off:
400 mov r0, #0x00000070 @ ARM7 control reg.
401 b __armv3_cache_off
402
403__armv3_cache_off:
404 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
405 mov r0, #0
406 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
407 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
408 mov pc, lr
409
410/*
411 * Clean and flush the cache to maintain consistency.
412 *
413 * On entry,
414 * r6 = processor ID
415 * On exit,
416 * r1, r2, r3, r12 corrupted
417 * This routine must preserve:
418 * r0, r4, r5, r6, r7
419 */
420 .align 5
421cache_clean_flush:
422 mov r3, #16
423 b call_cache_fn
424
425__armv4_cache_flush:
426 bic r1, pc, #31
427 add r2, r1, #65536 @ 2x the largest dcache size
4281: ldr r12, [r1], #32 @ s/w flush D cache
429 teq r1, r2
430 bne 1b
431
432 mcr p15, 0, r1, c7, c7, 0 @ flush I cache
433 mcr p15, 0, r1, c7, c10, 4 @ drain WB
434 mov pc, lr
435
436__armv3_cache_flush:
437 mov r1, #0
438 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
439 mov pc, lr
440
441/*
442 * Various debugging routines for printing hex characters and
443 * memory, which again must be relocatable.
444 */
445#ifdef DEBUG
446 .type phexbuf,#object
447phexbuf: .space 12
448 .size phexbuf, . - phexbuf
449
450phex: adr r3, phexbuf
451 mov r2, #0
452 strb r2, [r3, r1]
4531: subs r1, r1, #1
454 movmi r0, r3
455 bmi puts
456 and r2, r0, #15
457 mov r0, r0, lsr #4
458 cmp r2, #10
459 addge r2, r2, #7
460 add r2, r2, #'0'
461 strb r2, [r3, r1]
462 b 1b
463
464puts: loadsp r3
4651: ldrb r2, [r0], #1
466 teq r2, #0
467 moveq pc, lr
4682: writeb r2
469 mov r1, #0x00020000
4703: subs r1, r1, #1
471 bne 3b
472 teq r2, #'\n'
473 moveq r2, #'\r'
474 beq 2b
475 teq r0, #0
476 bne 1b
477 mov pc, lr
478putc:
479 mov r2, r0
480 mov r0, #0
481 loadsp r3
482 b 2b
483
484memdump: mov r12, r0
485 mov r10, lr
486 mov r11, #0
4872: mov r0, r11, lsl #2
488 add r0, r0, r12
489 mov r1, #8
490 bl phex
491 mov r0, #':'
492 bl putc
4931: mov r0, #' '
494 bl putc
495 ldr r0, [r12, r11, lsl #2]
496 mov r1, #8
497 bl phex
498 and r0, r11, #7
499 teq r0, #3
500 moveq r0, #' '
501 bleq putc
502 and r0, r11, #7
503 add r11, r11, #1
504 teq r0, #7
505 bne 1b
506 mov r0, #'\n'
507 bl putc
508 cmp r11, #64
509 blt 2b
510 mov pc, r10
511#endif
512
513reloc_end:
514
515 .align
516 .section ".stack", "aw"
517user_stack: .space 4096
diff --git a/arch/arm26/boot/compressed/hw-bse.c b/arch/arm26/boot/compressed/hw-bse.c
new file mode 100644
index 000000000000..3e8f07f8e08a
--- /dev/null
+++ b/arch/arm26/boot/compressed/hw-bse.c
@@ -0,0 +1,74 @@
1/*
2 * Bright Star Engineering Inc.
3 *
4 * code for readng parameters from the
5 * parameter blocks of the boot block
6 * flash memory
7 *
8 */
9
10static int strcmp(const char *s1, const char *s2)
11{
12 while (*s1 != '\0' && *s1 == *s2)
13 {
14 s1++;
15 s2++;
16 }
17
18 return (*(unsigned char *) s1) - (*(unsigned char *) s2);
19}
20
21struct pblk_t {
22 char type;
23 unsigned short size;
24};
25
26static char *bse_getflashparam(char *name) {
27 unsigned int esize;
28 char *q,*r;
29 unsigned char *p,*e;
30 struct pblk_t *thepb = (struct pblk_t *) 0x00004000;
31 struct pblk_t *altpb = (struct pblk_t *) 0x00006000;
32 if (thepb->type&1) {
33 if (altpb->type&1) {
34 /* no valid param block */
35 return (char*)0;
36 } else {
37 /* altpb is valid */
38 struct pblk_t *tmp;
39 tmp = thepb;
40 thepb = altpb;
41 altpb = tmp;
42 }
43 }
44 p = (char*)thepb + sizeof(struct pblk_t);
45 e = p + thepb->size;
46 while (p < e) {
47 q = p;
48 esize = *p;
49 if (esize == 0xFF) break;
50 if (esize == 0) break;
51 if (esize > 127) {
52 esize = (esize&0x7F)<<8 | p[1];
53 q++;
54 }
55 q++;
56 r=q;
57 if (*r && ((name == 0) || (!strcmp(name,r)))) {
58 while (*q++) ;
59 return q;
60 }
61 p+=esize;
62 }
63 return (char*)0;
64}
65
66void bse_setup(void) {
67 /* extract the linux cmdline from flash */
68 char *name=bse_getflashparam("linuxboot");
69 char *x = (char *)0xc0000100;
70 if (name) {
71 while (*name) *x++=*name++;
72 }
73 *x=0;
74}
diff --git a/arch/arm26/boot/compressed/ll_char_wr.S b/arch/arm26/boot/compressed/ll_char_wr.S
new file mode 100644
index 000000000000..f024c3ebdfa5
--- /dev/null
+++ b/arch/arm26/boot/compressed/ll_char_wr.S
@@ -0,0 +1,162 @@
1/*
2 * linux/arch/arm26/lib/ll_char_wr.S
3 *
4 * Copyright (C) 1995, 1996 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Speedups & 1bpp code (C) 1996 Philip Blundell & Russell King.
11 *
12 * 10-04-96 RMK Various cleanups & reduced register usage.
13 * 08-04-98 RMK Shifts re-ordered
14 */
15
16@ Regs: [] = corruptible
17@ {} = used
18@ () = do not use
19
20#include <linux/linkage.h>
21#include <asm/assembler.h>
22 .text
23
24#define BOLD 0x01
25#define ITALIC 0x02
26#define UNDERLINE 0x04
27#define FLASH 0x08
28#define INVERSE 0x10
29
30LC0: .word bytes_per_char_h
31 .word video_size_row
32 .word acorndata_8x8
33 .word con_charconvtable
34
35ENTRY(ll_write_char)
36 stmfd sp!, {r4 - r7, lr}
37@
38@ Smashable regs: {r0 - r3}, [r4 - r7], (r8 - fp), [ip], (sp), [lr], (pc)
39@
40 eor ip, r1, #UNDERLINE << 9
41/*
42 * calculate colours
43 */
44 tst r1, #INVERSE << 9
45 moveq r2, r1, lsr #16
46 moveq r3, r1, lsr #24
47 movne r2, r1, lsr #24
48 movne r3, r1, lsr #16
49 and r3, r3, #255
50 and r2, r2, #255
51/*
52 * calculate offset into character table
53 */
54 mov r1, r1, lsl #23
55 mov r1, r1, lsr #20
56/*
57 * calculate offset required for each row [maybe I should make this an argument to this fn.
58 * Have to see what the register usage is like in the calling routines.
59 */
60 adr r4, LC0
61 ldmia r4, {r4, r5, r6, lr}
62 ldr r4, [r4]
63 ldr r5, [r5]
64/*
65 * Go to resolution-dependent routine...
66 */
67 cmp r4, #4
68 blt Lrow1bpp
69 eor r2, r3, r2 @ Create eor mask to change colour from bg
70 orr r3, r3, r3, lsl #8 @ to fg.
71 orr r3, r3, r3, lsl #16
72 add r0, r0, r5, lsl #3 @ Move to bottom of character
73 add r1, r1, #7
74 ldrb r7, [r6, r1]
75 tst ip, #UNDERLINE << 9
76 eoreq r7, r7, #255
77 teq r4, #8
78 beq Lrow8bpplp
79@
80@ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
81@
82 orr r3, r3, r3, lsl #4
83Lrow4bpplp: ldr r7, [lr, r7, lsl #2]
84 mul r7, r2, r7
85 tst r1, #7 @ avoid using r7 directly after
86 eor ip, r3, r7
87 str ip, [r0, -r5]!
88 LOADREGS(eqfd, sp!, {r4 - r7, pc})
89 sub r1, r1, #1
90 ldrb r7, [r6, r1]
91 ldr r7, [lr, r7, lsl #2]
92 mul r7, r2, r7
93 tst r1, #7 @ avoid using r7 directly after
94 eor ip, r3, r7
95 str ip, [r0, -r5]!
96 subne r1, r1, #1
97 ldrneb r7, [r6, r1]
98 bne Lrow4bpplp
99 LOADREGS(fd, sp!, {r4 - r7, pc})
100
101@
102@ Smashable regs: {r0 - r3}, [r4], {r5 - r7}, (r8 - fp), [ip], (sp), {lr}, (pc)
103@
104Lrow8bpplp: mov ip, r7, lsr #4
105 ldr ip, [lr, ip, lsl #2]
106 mul r4, r2, ip
107 and ip, r7, #15 @ avoid r4
108 ldr ip, [lr, ip, lsl #2] @ avoid r4
109 mul ip, r2, ip @ avoid r4
110 eor r4, r3, r4 @ avoid ip
111 tst r1, #7 @ avoid ip
112 sub r0, r0, r5 @ avoid ip
113 eor ip, r3, ip
114 stmia r0, {r4, ip}
115 LOADREGS(eqfd, sp!, {r4 - r7, pc})
116 sub r1, r1, #1
117 ldrb r7, [r6, r1]
118 mov ip, r7, lsr #4
119 ldr ip, [lr, ip, lsl #2]
120 mul r4, r2, ip
121 and ip, r7, #15 @ avoid r4
122 ldr ip, [lr, ip, lsl #2] @ avoid r4
123 mul ip, r2, ip @ avoid r4
124 eor r4, r3, r4 @ avoid ip
125 tst r1, #7 @ avoid ip
126 sub r0, r0, r5 @ avoid ip
127 eor ip, r3, ip
128 stmia r0, {r4, ip}
129 subne r1, r1, #1
130 ldrneb r7, [r6, r1]
131 bne Lrow8bpplp
132 LOADREGS(fd, sp!, {r4 - r7, pc})
133
134@
135@ Smashable regs: {r0 - r3}, [r4], {r5, r6}, [r7], (r8 - fp), [ip], (sp), [lr], (pc)
136@
137Lrow1bpp: add r6, r6, r1
138 ldmia r6, {r4, r7}
139 tst ip, #INVERSE << 9
140 mvnne r4, r4
141 mvnne r7, r7
142 strb r4, [r0], r5
143 mov r4, r4, lsr #8
144 strb r4, [r0], r5
145 mov r4, r4, lsr #8
146 strb r4, [r0], r5
147 mov r4, r4, lsr #8
148 strb r4, [r0], r5
149 strb r7, [r0], r5
150 mov r7, r7, lsr #8
151 strb r7, [r0], r5
152 mov r7, r7, lsr #8
153 strb r7, [r0], r5
154 mov r7, r7, lsr #8
155 tst ip, #UNDERLINE << 9
156 mvneq r7, r7
157 strb r7, [r0], r5
158 LOADREGS(fd, sp!, {r4 - r7, pc})
159
160 .bss
161ENTRY(con_charconvtable)
162 .space 1024
diff --git a/arch/arm26/boot/compressed/misc.c b/arch/arm26/boot/compressed/misc.c
new file mode 100644
index 000000000000..f17f50e5516f
--- /dev/null
+++ b/arch/arm26/boot/compressed/misc.c
@@ -0,0 +1,316 @@
1/*
2 * misc.c
3 *
4 * This is a collection of several routines from gzip-1.0.3
5 * adapted for Linux.
6 *
7 * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
8 *
9 * Modified for ARM Linux by Russell King
10 *
11 * Nicolas Pitre <nico@visuaide.com> 1999/04/14 :
12 * For this code to run directly from Flash, all constant variables must
13 * be marked with 'const' and all other variables initialized at run-time
14 * only. This way all non constant variables will end up in the bss segment,
15 * which should point to addresses in RAM and cleared to 0 on start.
16 * This allows for a much quicker boot time.
17 */
18
19unsigned int __machine_arch_type;
20
21#include <linux/kernel.h>
22
23#include <asm/uaccess.h>
24#include "uncompress.h"
25
26#ifdef STANDALONE_DEBUG
27#define puts printf
28#endif
29
30#define __ptr_t void *
31
32/*
33 * Optimised C version of memzero for the ARM.
34 */
35void __memzero (__ptr_t s, size_t n)
36{
37 union { void *vp; unsigned long *ulp; unsigned char *ucp; } u;
38 int i;
39
40 u.vp = s;
41
42 for (i = n >> 5; i > 0; i--) {
43 *u.ulp++ = 0;
44 *u.ulp++ = 0;
45 *u.ulp++ = 0;
46 *u.ulp++ = 0;
47 *u.ulp++ = 0;
48 *u.ulp++ = 0;
49 *u.ulp++ = 0;
50 *u.ulp++ = 0;
51 }
52
53 if (n & 1 << 4) {
54 *u.ulp++ = 0;
55 *u.ulp++ = 0;
56 *u.ulp++ = 0;
57 *u.ulp++ = 0;
58 }
59
60 if (n & 1 << 3) {
61 *u.ulp++ = 0;
62 *u.ulp++ = 0;
63 }
64
65 if (n & 1 << 2)
66 *u.ulp++ = 0;
67
68 if (n & 1 << 1) {
69 *u.ucp++ = 0;
70 *u.ucp++ = 0;
71 }
72
73 if (n & 1)
74 *u.ucp++ = 0;
75}
76
77static inline __ptr_t memcpy(__ptr_t __dest, __const __ptr_t __src,
78 size_t __n)
79{
80 int i = 0;
81 unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src;
82
83 for (i = __n >> 3; i > 0; i--) {
84 *d++ = *s++;
85 *d++ = *s++;
86 *d++ = *s++;
87 *d++ = *s++;
88 *d++ = *s++;
89 *d++ = *s++;
90 *d++ = *s++;
91 *d++ = *s++;
92 }
93
94 if (__n & 1 << 2) {
95 *d++ = *s++;
96 *d++ = *s++;
97 *d++ = *s++;
98 *d++ = *s++;
99 }
100
101 if (__n & 1 << 1) {
102 *d++ = *s++;
103 *d++ = *s++;
104 }
105
106 if (__n & 1)
107 *d++ = *s++;
108
109 return __dest;
110}
111
112/*
113 * gzip delarations
114 */
115#define OF(args) args
116#define STATIC static
117
118typedef unsigned char uch;
119typedef unsigned short ush;
120typedef unsigned long ulg;
121
122#define WSIZE 0x8000 /* Window size must be at least 32k, */
123 /* and a power of two */
124
125static uch *inbuf; /* input buffer */
126static uch window[WSIZE]; /* Sliding window buffer */
127
128static unsigned insize; /* valid bytes in inbuf */
129static unsigned inptr; /* index of next byte to be processed in inbuf */
130static unsigned outcnt; /* bytes in output buffer */
131
132/* gzip flag byte */
133#define ASCII_FLAG 0x01 /* bit 0 set: file probably ascii text */
134#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
135#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
136#define ORIG_NAME 0x08 /* bit 3 set: original file name present */
137#define COMMENT 0x10 /* bit 4 set: file comment present */
138#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
139#define RESERVED 0xC0 /* bit 6,7: reserved */
140
141#define get_byte() (inptr < insize ? inbuf[inptr++] : fill_inbuf())
142
143/* Diagnostic functions */
144#ifdef DEBUG
145# define Assert(cond,msg) {if(!(cond)) error(msg);}
146# define Trace(x) fprintf x
147# define Tracev(x) {if (verbose) fprintf x ;}
148# define Tracevv(x) {if (verbose>1) fprintf x ;}
149# define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
150# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
151#else
152# define Assert(cond,msg)
153# define Trace(x)
154# define Tracev(x)
155# define Tracevv(x)
156# define Tracec(c,x)
157# define Tracecv(c,x)
158#endif
159
160static int fill_inbuf(void);
161static void flush_window(void);
162static void error(char *m);
163static void gzip_mark(void **);
164static void gzip_release(void **);
165
166extern char input_data[];
167extern char input_data_end[];
168
169static uch *output_data;
170static ulg output_ptr;
171static ulg bytes_out;
172
173static void *malloc(int size);
174static void free(void *where);
175static void error(char *m);
176static void gzip_mark(void **);
177static void gzip_release(void **);
178
179static void puts(const char *);
180
181extern int end;
182static ulg free_mem_ptr;
183static ulg free_mem_ptr_end;
184
185#define HEAP_SIZE 0x2000
186
187#include "../../../../lib/inflate.c"
188
189#ifndef STANDALONE_DEBUG
190static void *malloc(int size)
191{
192 void *p;
193
194 if (size <0) error("Malloc error");
195 if (free_mem_ptr <= 0) error("Memory error");
196
197 free_mem_ptr = (free_mem_ptr + 3) & ~3; /* Align */
198
199 p = (void *)free_mem_ptr;
200 free_mem_ptr += size;
201
202 if (free_mem_ptr >= free_mem_ptr_end)
203 error("Out of memory");
204 return p;
205}
206
207static void free(void *where)
208{ /* gzip_mark & gzip_release do the free */
209}
210
211static void gzip_mark(void **ptr)
212{
213 arch_decomp_wdog();
214 *ptr = (void *) free_mem_ptr;
215}
216
217static void gzip_release(void **ptr)
218{
219 arch_decomp_wdog();
220 free_mem_ptr = (long) *ptr;
221}
222#else
223static void gzip_mark(void **ptr)
224{
225}
226
227static void gzip_release(void **ptr)
228{
229}
230#endif
231
232/* ===========================================================================
233 * Fill the input buffer. This is called only when the buffer is empty
234 * and at least one byte is really needed.
235 */
236int fill_inbuf(void)
237{
238 if (insize != 0)
239 error("ran out of input data");
240
241 inbuf = input_data;
242 insize = &input_data_end[0] - &input_data[0];
243
244 inptr = 1;
245 return inbuf[0];
246}
247
248/* ===========================================================================
249 * Write the output window window[0..outcnt-1] and update crc and bytes_out.
250 * (Used for the decompressed data only.)
251 */
252void flush_window(void)
253{
254 ulg c = crc;
255 unsigned n;
256 uch *in, *out, ch;
257
258 in = window;
259 out = &output_data[output_ptr];
260 for (n = 0; n < outcnt; n++) {
261 ch = *out++ = *in++;
262 c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
263 }
264 crc = c;
265 bytes_out += (ulg)outcnt;
266 output_ptr += (ulg)outcnt;
267 outcnt = 0;
268 puts(".");
269}
270
271static void error(char *x)
272{
273 int ptr;
274
275 puts("\n\n");
276 puts(x);
277 puts("\n\n -- System halted");
278
279 while(1); /* Halt */
280}
281
282#ifndef STANDALONE_DEBUG
283
284ulg
285decompress_kernel(ulg output_start, ulg free_mem_ptr_p, ulg free_mem_ptr_end_p,
286 int arch_id)
287{
288 output_data = (uch *)output_start; /* Points to kernel start */
289 free_mem_ptr = free_mem_ptr_p;
290 free_mem_ptr_end = free_mem_ptr_end_p;
291 __machine_arch_type = arch_id;
292
293 arch_decomp_setup();
294
295 makecrc();
296 puts("Uncompressing Linux...");
297 gunzip();
298 puts(" done, booting the kernel.\n");
299 return output_ptr;
300}
301#else
302
303char output_buffer[1500*1024];
304
305int main()
306{
307 output_data = output_buffer;
308
309 makecrc();
310 puts("Uncompressing Linux...");
311 gunzip();
312 puts("done.\n");
313 return 0;
314}
315#endif
316
diff --git a/arch/arm26/boot/compressed/uncompress.h b/arch/arm26/boot/compressed/uncompress.h
new file mode 100644
index 000000000000..66d9b938a7a4
--- /dev/null
+++ b/arch/arm26/boot/compressed/uncompress.h
@@ -0,0 +1,110 @@
1/*
2 *
3 * Copyright (C) 1996 Russell King
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#define VIDMEM ((char *)0x02000000)
10
11int video_num_columns, video_num_lines, video_size_row;
12int white, bytes_per_char_h;
13extern unsigned long con_charconvtable[256];
14
15struct param_struct {
16 unsigned long page_size;
17 unsigned long nr_pages;
18 unsigned long ramdisk_size;
19 unsigned long mountrootrdonly;
20 unsigned long rootdev;
21 unsigned long video_num_cols;
22 unsigned long video_num_rows;
23 unsigned long video_x;
24 unsigned long video_y;
25 unsigned long memc_control_reg;
26 unsigned char sounddefault;
27 unsigned char adfsdrives;
28 unsigned char bytes_per_char_h;
29 unsigned char bytes_per_char_v;
30 unsigned long unused[256/4-11];
31};
32
33static struct param_struct *params = (struct param_struct *)0x0207c000;
34
35/*
36 * This does not append a newline
37 */
38static void puts(const char *s)
39{
40 extern void ll_write_char(char *, unsigned long);
41 int x,y;
42 unsigned char c;
43 char *ptr;
44
45 x = params->video_x;
46 y = params->video_y;
47
48 while ( ( c = *(unsigned char *)s++ ) != '\0' ) {
49 if ( c == '\n' ) {
50 x = 0;
51 if ( ++y >= video_num_lines ) {
52 y--;
53 }
54 } else {
55 ptr = VIDMEM + ((y*video_num_columns*params->bytes_per_char_v+x)*bytes_per_char_h);
56 ll_write_char(ptr, c|(white<<16));
57 if ( ++x >= video_num_columns ) {
58 x = 0;
59 if ( ++y >= video_num_lines ) {
60 y--;
61 }
62 }
63 }
64 }
65
66 params->video_x = x;
67 params->video_y = y;
68}
69
70static void error(char *x);
71
72/*
73 * Setup for decompression
74 */
75static void arch_decomp_setup(void)
76{
77 int i;
78
79 video_num_lines = params->video_num_rows;
80 video_num_columns = params->video_num_cols;
81 bytes_per_char_h = params->bytes_per_char_h;
82 video_size_row = video_num_columns * bytes_per_char_h;
83 if (bytes_per_char_h == 4)
84 for (i = 0; i < 256; i++)
85 con_charconvtable[i] =
86 (i & 128 ? 1 << 0 : 0) |
87 (i & 64 ? 1 << 4 : 0) |
88 (i & 32 ? 1 << 8 : 0) |
89 (i & 16 ? 1 << 12 : 0) |
90 (i & 8 ? 1 << 16 : 0) |
91 (i & 4 ? 1 << 20 : 0) |
92 (i & 2 ? 1 << 24 : 0) |
93 (i & 1 ? 1 << 28 : 0);
94 else
95 for (i = 0; i < 16; i++)
96 con_charconvtable[i] =
97 (i & 8 ? 1 << 0 : 0) |
98 (i & 4 ? 1 << 8 : 0) |
99 (i & 2 ? 1 << 16 : 0) |
100 (i & 1 ? 1 << 24 : 0);
101
102 white = bytes_per_char_h == 8 ? 0xfc : 7;
103
104 if (params->nr_pages * params->page_size < 4096*1024) error("<4M of mem\n");
105}
106
107/*
108 * nothing to do
109 */
110#define arch_decomp_wdog()
diff --git a/arch/arm26/boot/compressed/vmlinux.lds.in b/arch/arm26/boot/compressed/vmlinux.lds.in
new file mode 100644
index 000000000000..86d821d5ab70
--- /dev/null
+++ b/arch/arm26/boot/compressed/vmlinux.lds.in
@@ -0,0 +1,60 @@
1/*
2 * linux/arch/arm26/boot/compressed/vmlinux.lds.in
3 *
4 * Copyright (C) 2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10OUTPUT_ARCH(arm)
11ENTRY(_start)
12SECTIONS
13{
14 . = LOAD_ADDR;
15 _load_addr = .;
16
17 . = TEXT_START;
18 _text = .;
19
20 .text : {
21 _start = .;
22 *(.start)
23 *(.text)
24 *(.fixup)
25 *(.gnu.warning)
26 *(.rodata)
27 *(.rodata.*)
28 *(.glue_7)
29 *(.glue_7t)
30 input_data = .;
31 arch/arm26/boot/compressed/piggy.o
32 input_data_end = .;
33 . = ALIGN(4);
34 }
35
36 _etext = .;
37
38 _got_start = .;
39 .got : { *(.got) }
40 _got_end = .;
41 .got.plt : { *(.got.plt) }
42 .data : { *(.data) }
43 _edata = .;
44
45 . = BSS_START;
46 __bss_start = .;
47 .bss : { *(.bss) }
48 _end = .;
49
50 .stack (NOLOAD) : { *(.stack) }
51
52 .stab 0 : { *(.stab) }
53 .stabstr 0 : { *(.stabstr) }
54 .stab.excl 0 : { *(.stab.excl) }
55 .stab.exclstr 0 : { *(.stab.exclstr) }
56 .stab.index 0 : { *(.stab.index) }
57 .stab.indexstr 0 : { *(.stab.indexstr) }
58 .comment 0 : { *(.comment) }
59}
60
diff --git a/arch/arm26/boot/install.sh b/arch/arm26/boot/install.sh
new file mode 100644
index 000000000000..c628328dd9ec
--- /dev/null
+++ b/arch/arm26/boot/install.sh
@@ -0,0 +1,62 @@
1#!/bin/sh
2#
3# arch/arm26/boot/install.sh
4#
5# This file is subject to the terms and conditions of the GNU General Public
6# License. See the file "COPYING" in the main directory of this archive
7# for more details.
8#
9# Copyright (C) 1995 by Linus Torvalds
10#
11# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin
12# Adapted from code in arch/i386/boot/install.sh by Russell King
13# Stolen from arm32 by Ian Molton
14#
15# "make install" script for arm architecture
16#
17# Arguments:
18# $1 - kernel version
19# $2 - kernel image file
20# $3 - kernel map file
21# $4 - default install path (blank if root directory)
22#
23
24# User may have a custom install script
25
26if [ -x /sbin/installkernel ]; then
27 exec /sbin/installkernel "$@"
28fi
29
30if [ "$2" = "zImage" ]; then
31# Compressed install
32 echo "Installing compressed kernel"
33 if [ -f $4/vmlinuz-$1 ]; then
34 mv $4/vmlinuz-$1 $4/vmlinuz.old
35 fi
36
37 if [ -f $4/System.map-$1 ]; then
38 mv $4/System.map-$1 $4/System.old
39 fi
40
41 cat $2 > $4/vmlinuz-$1
42 cp $3 $4/System.map-$1
43else
44# Normal install
45 echo "Installing normal kernel"
46 if [ -f $4/vmlinux-$1 ]; then
47 mv $4/vmlinux-$1 $4/vmlinux.old
48 fi
49
50 if [ -f $4/System.map ]; then
51 mv $4/System.map $4/System.old
52 fi
53
54 cat $2 > $4/vmlinux-$1
55 cp $3 $4/System.map
56fi
57
58if [ -x /sbin/loadmap ]; then
59 /sbin/loadmap --rdev /dev/ima
60else
61 echo "You have to install it yourself"
62fi
diff --git a/arch/arm26/defconfig b/arch/arm26/defconfig
new file mode 100644
index 000000000000..c4a89703c3d8
--- /dev/null
+++ b/arch/arm26/defconfig
@@ -0,0 +1,362 @@
1#
2# Automatically generated by make menuconfig: don't edit
3#
4CONFIG_ARM=y
5# CONFIG_EISA is not set
6# CONFIG_SBUS is not set
7# CONFIG_MCA is not set
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y
10# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
11# CONFIG_GENERIC_BUST_SPINLOCK is not set
12# CONFIG_GENERIC_ISA_DMA is not set
13
14#
15# Code maturity level options
16#
17CONFIG_EXPERIMENTAL=y
18
19#
20# General setup
21#
22# CONFIG_NET is not set
23# CONFIG_SYSVIPC is not set
24# CONFIG_BSD_PROCESS_ACCT is not set
25# CONFIG_SYSCTL is not set
26
27#
28# Loadable module support
29#
30# CONFIG_MODULES is not set
31
32#
33# System Type
34#
35CONFIG_ARCH_ARC=y
36# CONFIG_ARCH_A5K is not set
37CONFIG_ARCH_ACORN=y
38# CONFIG_CPU_32 is not set
39CONFIG_CPU_26=y
40# CONFIG_PAGESIZE_16 is not set
41
42#
43# General setup
44#
45CONFIG_FIQ=y
46# CONFIG_ZBOOT_ROM is not set
47CONFIG_ZBOOT_ROM_TEXT=0
48CONFIG_ZBOOT_ROM_BSS=0
49CONFIG_FPE_NWFPE=y
50CONFIG_KCORE_ELF=y
51# CONFIG_KCORE_AOUT is not set
52# CONFIG_BINFMT_AOUT is not set
53# CONFIG_BINFMT_ELF is not set
54# CONFIG_BINFMT_MISC is not set
55CONFIG_CMDLINE=""
56# CONFIG_ALIGNMENT_TRAP is not set
57
58#
59# Parallel port support
60#
61# CONFIG_PARPORT is not set
62
63#
64# Plug and Play configuration
65#
66# CONFIG_PNP is not set
67# CONFIG_ISAPNP is not set
68# CONFIG_PNPBIOS is not set
69
70#
71# Block devices
72#
73# CONFIG_BLK_DEV_FD is not set
74# CONFIG_BLK_DEV_XD is not set
75# CONFIG_PARIDE is not set
76# CONFIG_BLK_CPQ_DA is not set
77# CONFIG_BLK_CPQ_CISS_DA is not set
78# CONFIG_CISS_SCSI_TAPE is not set
79# CONFIG_BLK_DEV_DAC960 is not set
80# CONFIG_BLK_DEV_UMEM is not set
81# CONFIG_BLK_DEV_LOOP is not set
82# CONFIG_BLK_DEV_NBD is not set
83# CONFIG_BLK_DEV_RAM is not set
84# CONFIG_BLK_DEV_INITRD is not set
85
86#
87# Multi-device support (RAID and LVM)
88#
89# CONFIG_MD is not set
90# CONFIG_BLK_DEV_MD is not set
91# CONFIG_MD_LINEAR is not set
92# CONFIG_MD_RAID0 is not set
93# CONFIG_MD_RAID1 is not set
94# CONFIG_MD_RAID5 is not set
95# CONFIG_MD_MULTIPATH is not set
96# CONFIG_BLK_DEV_LVM is not set
97
98#
99# Acorn-specific block devices
100#
101# CONFIG_BLK_DEV_FD1772 is not set
102# CONFIG_BLK_DEV_MFM is not set
103
104#
105# ATA/ATAPI/MFM/RLL support
106#
107# CONFIG_IDE is not set
108# CONFIG_BLK_DEV_HD is not set
109
110#
111# SCSI support
112#
113# CONFIG_SCSI is not set
114
115#
116# ISDN subsystem
117#
118
119#
120# Input device support
121#
122# CONFIG_INPUT is not set
123# CONFIG_INPUT_KEYBDEV is not set
124# CONFIG_INPUT_MOUSEDEV is not set
125# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
126# CONFIG_INPUT_JOYDEV is not set
127# CONFIG_INPUT_TSDEV is not set
128# CONFIG_INPUT_TSLIBDEV is not set
129# CONFIG_INPUT_EVDEV is not set
130# CONFIG_INPUT_EVBUG is not set
131# CONFIG_INPUT_UINPUT is not set
132# CONFIG_GAMEPORT is not set
133CONFIG_SOUND_GAMEPORT=y
134# CONFIG_GAMEPORT_NS558 is not set
135# CONFIG_GAMEPORT_L4 is not set
136# CONFIG_GAMEPORT_EMU10K1 is not set
137# CONFIG_GAMEPORT_VORTEX is not set
138# CONFIG_GAMEPORT_FM801 is not set
139# CONFIG_GAMEPORT_CS461x is not set
140# CONFIG_SERIO is not set
141# CONFIG_SERIO_I8042 is not set
142# CONFIG_SERIO_SERPORT is not set
143# CONFIG_SERIO_CT82C710 is not set
144# CONFIG_SERIO_PARKBD is not set
145# CONFIG_SERIO_ACORN is not set
146
147#
148# Character devices
149#
150# CONFIG_VT is not set
151# CONFIG_SERIAL_NONSTANDARD is not set
152
153#
154# Serial drivers
155#
156# CONFIG_SERIAL_8250 is not set
157# CONFIG_SERIAL_8250_CONSOLE is not set
158# CONFIG_SERIAL_8250_CS is not set
159# CONFIG_SERIAL_8250_EXTENDED is not set
160# CONFIG_SERIAL_8250_MANY_PORTS is not set
161# CONFIG_SERIAL_8250_SHARE_IRQ is not set
162# CONFIG_SERIAL_8250_DETECT_IRQ is not set
163# CONFIG_SERIAL_8250_MULTIPORT is not set
164# CONFIG_SERIAL_8250_RSA is not set
165# CONFIG_ATOMWIDE_SERIAL is not set
166# CONFIG_DUALSP_SERIAL is not set
167# CONFIG_SERIAL_AMBA is not set
168# CONFIG_SERIAL_AMBA_CONSOLE is not set
169# CONFIG_SERIAL_CLPS711X is not set
170# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
171# CONFIG_SERIAL_CLPS711X_OLD_NAME is not set
172# CONFIG_SERIAL_21285 is not set
173# CONFIG_SERIAL_21285_OLD is not set
174# CONFIG_SERIAL_21285_CONSOLE is not set
175# CONFIG_SERIAL_UART00 is not set
176# CONFIG_SERIAL_UART00_CONSOLE is not set
177# CONFIG_SERIAL_SA1100 is not set
178# CONFIG_SERIAL_SA1100_CONSOLE is not set
179# CONFIG_UNIX98_PTYS is not set
180
181#
182# I2C support
183#
184CONFIG_I2C=y
185CONFIG_I2C_ALGOBIT=y
186CONFIG_I2C_ALGOPCF=y
187# CONFIG_I2C_ELEKTOR is not set
188CONFIG_I2C_CHARDEV=y
189# CONFIG_I2C_PROC is not set
190
191#
192# L3 serial bus support
193#
194# CONFIG_L3 is not set
195# CONFIG_L3_ALGOBIT is not set
196# CONFIG_L3_BIT_SA1100_GPIO is not set
197# CONFIG_L3_SA1111 is not set
198# CONFIG_BIT_SA1100_GPIO is not set
199
200#
201# Mice
202#
203# CONFIG_BUSMOUSE is not set
204# CONFIG_PSMOUSE is not set
205# CONFIG_QIC02_TAPE is not set
206
207#
208# Watchdog Cards
209#
210# CONFIG_WATCHDOG is not set
211# CONFIG_NVRAM is not set
212# CONFIG_RTC is not set
213# CONFIG_DTLK is not set
214# CONFIG_R3964 is not set
215# CONFIG_APPLICOM is not set
216
217#
218# Ftape, the floppy tape device driver
219#
220# CONFIG_FTAPE is not set
221# CONFIG_AGP is not set
222# CONFIG_DRM is not set
223# CONFIG_RAW_DRIVER is not set
224
225#
226# Multimedia devices
227#
228# CONFIG_VIDEO_DEV is not set
229
230#
231# File systems
232#
233# CONFIG_QUOTA is not set
234# CONFIG_QFMT_V1 is not set
235# CONFIG_QFMT_V2 is not set
236# CONFIG_AUTOFS_FS is not set
237# CONFIG_AUTOFS4_FS is not set
238# CONFIG_REISERFS_FS is not set
239# CONFIG_REISERFS_CHECK is not set
240# CONFIG_REISERFS_PROC_INFO is not set
241# CONFIG_ADFS_FS is not set
242# CONFIG_ADFS_FS_RW is not set
243# CONFIG_AFFS_FS is not set
244# CONFIG_HFS_FS is not set
245# CONFIG_BFS_FS is not set
246# CONFIG_EXT3_FS is not set
247# CONFIG_JBD is not set
248# CONFIG_JBD_DEBUG is not set
249# CONFIG_FAT_FS is not set
250# CONFIG_MSDOS_FS is not set
251# CONFIG_UMSDOS_FS is not set
252# CONFIG_VFAT_FS is not set
253# CONFIG_EFS_FS is not set
254# CONFIG_JFFS_FS is not set
255# CONFIG_JFFS2_FS is not set
256# CONFIG_CRAMFS is not set
257# CONFIG_TMPFS is not set
258CONFIG_RAMFS=y
259# CONFIG_ISO9660_FS is not set
260# CONFIG_JOLIET is not set
261# CONFIG_ZISOFS is not set
262# CONFIG_JFS_FS is not set
263# CONFIG_JFS_DEBUG is not set
264# CONFIG_JFS_STATISTICS is not set
265# CONFIG_MINIX_FS is not set
266# CONFIG_VXFS_FS is not set
267# CONFIG_NTFS_FS is not set
268# CONFIG_NTFS_DEBUG is not set
269# CONFIG_HPFS_FS is not set
270CONFIG_PROC_FS=y
271# CONFIG_DEVFS_FS is not set
272# CONFIG_DEVFS_MOUNT is not set
273# CONFIG_DEVFS_DEBUG is not set
274# CONFIG_DEVPTS_FS is not set
275# CONFIG_QNX4FS_FS is not set
276# CONFIG_QNX4FS_RW is not set
277# CONFIG_ROMFS_FS is not set
278CONFIG_EXT2_FS=y
279# CONFIG_SYSV_FS is not set
280# CONFIG_UDF_FS is not set
281# CONFIG_UDF_RW is not set
282# CONFIG_UFS_FS is not set
283# CONFIG_UFS_FS_WRITE is not set
284# CONFIG_NCPFS_NLS is not set
285# CONFIG_SMB_FS is not set
286# CONFIG_ZISOFS_FS is not set
287
288#
289# Partition Types
290#
291CONFIG_PARTITION_ADVANCED=y
292CONFIG_ACORN_PARTITION=y
293# CONFIG_ACORN_PARTITION_EESOX is not set
294# CONFIG_ACORN_PARTITION_ICS is not set
295CONFIG_ACORN_PARTITION_ADFS=y
296# CONFIG_ACORN_PARTITION_POWERTEC is not set
297CONFIG_ACORN_PARTITION_RISCIX=y
298# CONFIG_OSF_PARTITION is not set
299# CONFIG_AMIGA_PARTITION is not set
300# CONFIG_ATARI_PARTITION is not set
301# CONFIG_MAC_PARTITION is not set
302# CONFIG_MSDOS_PARTITION is not set
303# CONFIG_LDM_PARTITION is not set
304# CONFIG_SGI_PARTITION is not set
305# CONFIG_ULTRIX_PARTITION is not set
306# CONFIG_SUN_PARTITION is not set
307# CONFIG_EFI_PARTITION is not set
308# CONFIG_SMB_NLS is not set
309# CONFIG_NLS is not set
310
311#
312# Sound
313#
314# CONFIG_SOUND is not set
315
316#
317# Multimedia Capabilities Port drivers
318#
319# CONFIG_MCP is not set
320# CONFIG_MCP_SA1100 is not set
321# CONFIG_MCP_UCB1200 is not set
322# CONFIG_MCP_UCB1200_AUDIO is not set
323# CONFIG_MCP_UCB1200_TS is not set
324
325#
326# Console Switches
327#
328# CONFIG_SWITCHES is not set
329# CONFIG_SWITCHES_SA1100 is not set
330# CONFIG_SWITCHES_UCB1X00 is not set
331
332#
333# USB support
334#
335# CONFIG_USB is not set
336
337#
338# Kernel hacking
339#
340# CONFIG_NO_FRAME_POINTER is not set
341CONFIG_DEBUG_USER=y
342CONFIG_DEBUG_INFO=y
343CONFIG_DEBUG_KERNEL=y
344CONFIG_DEBUG_SLAB=y
345CONFIG_MAGIC_SYSRQ=y
346CONFIG_DEBUG_SPINLOCK=y
347CONFIG_DEBUG_WAITQ=y
348CONFIG_DEBUG_BUGVERBOSE=y
349CONFIG_DEBUG_ERRORS=y
350CONFIG_DEBUG_LL=y
351
352#
353# Security options
354#
355CONFIG_SECURITY_CAPABILITIES=y
356
357#
358# Library routines
359#
360CONFIG_CRC32=y
361# CONFIG_ZLIB_INFLATE is not set
362# CONFIG_ZLIB_DEFLATE is not set
diff --git a/arch/arm26/kernel/Makefile b/arch/arm26/kernel/Makefile
new file mode 100644
index 000000000000..ee9fb49fdb78
--- /dev/null
+++ b/arch/arm26/kernel/Makefile
@@ -0,0 +1,17 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7AFLAGS_head.o := -DTEXTADDR=$(TEXTADDR)
8
9obj-y := compat.o dma.o entry.o irq.o process.o ptrace.o \
10 semaphore.o setup.o signal.o sys_arm.o time.o traps.o \
11 ecard.o dma.o ecard.o fiq.o time.o
12
13extra-y := head.o init_task.o vmlinux.lds
14
15obj-$(CONFIG_FIQ) += fiq.o
16obj-$(CONFIG_MODULES) += armksyms.o
17
diff --git a/arch/arm26/kernel/armksyms.c b/arch/arm26/kernel/armksyms.c
new file mode 100644
index 000000000000..35514b398e2e
--- /dev/null
+++ b/arch/arm26/kernel/armksyms.c
@@ -0,0 +1,220 @@
1/*
2 * linux/arch/arm26/kernel/armksyms.c
3 *
4 * Copyright (C) 2003 Ian Molton
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/module.h>
11#include <linux/config.h>
12#include <linux/module.h>
13#include <linux/user.h>
14#include <linux/string.h>
15#include <linux/fs.h>
16#include <linux/mm.h>
17#include <linux/mman.h>
18#include <linux/delay.h>
19#include <linux/in6.h>
20#include <linux/interrupt.h>
21#include <linux/pm.h>
22#include <linux/tty.h>
23#include <linux/vt_kern.h>
24#include <linux/smp_lock.h>
25#include <linux/syscalls.h>
26
27#include <asm/byteorder.h>
28#include <asm/elf.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/processor.h>
32#include <asm/semaphore.h>
33#include <asm/system.h>
34#include <asm/uaccess.h>
35#include <asm/checksum.h>
36#include <asm/mach-types.h>
37
38extern void dump_thread(struct pt_regs *, struct user *);
39extern int dump_fpu(struct pt_regs *, struct user_fp_struct *);
40extern void inswb(unsigned int port, void *to, int len);
41extern void outswb(unsigned int port, const void *to, int len);
42
43extern void __bad_xchg(volatile void *ptr, int size);
44
45/*
46 * libgcc functions - functions that are used internally by the
47 * compiler... (prototypes are not correct though, but that
48 * doesn't really matter since they're not versioned).
49 */
50extern void __ashldi3(void);
51extern void __ashrdi3(void);
52extern void __divsi3(void);
53extern void __lshrdi3(void);
54extern void __modsi3(void);
55extern void __muldi3(void);
56extern void __ucmpdi2(void);
57extern void __udivdi3(void);
58extern void __umoddi3(void);
59extern void __udivmoddi4(void);
60extern void __udivsi3(void);
61extern void __umodsi3(void);
62extern void abort(void);
63
64extern void ret_from_exception(void);
65extern void fpundefinstr(void);
66extern void fp_enter(void);
67
68/*
69 * This has a special calling convention; it doesn't
70 * modify any of the usual registers, except for LR.
71 * FIXME - we used to use our own local version - looks to be in kernel/softirq now
72 */
73//extern void __do_softirq(void);
74
75#define EXPORT_SYMBOL_ALIAS(sym,orig) \
76 const char __kstrtab_##sym[] \
77 __attribute__((section(".kstrtab"))) = \
78 __MODULE_STRING(sym); \
79 const struct module_symbol __ksymtab_##sym \
80 __attribute__((section("__ksymtab"))) = \
81 { (unsigned long)&orig, __kstrtab_##sym };
82
83/*
84 * floating point math emulator support.
85 * These symbols will never change their calling convention...
86 */
87EXPORT_SYMBOL_ALIAS(kern_fp_enter,fp_enter);
88EXPORT_SYMBOL_ALIAS(fp_printk,printk);
89EXPORT_SYMBOL_ALIAS(fp_send_sig,send_sig);
90
91EXPORT_SYMBOL(fpundefinstr);
92EXPORT_SYMBOL(ret_from_exception);
93
94#ifdef CONFIG_VT
95EXPORT_SYMBOL(kd_mksound);
96#endif
97
98//EXPORT_SYMBOL(__do_softirq);
99
100 /* platform dependent support */
101EXPORT_SYMBOL(dump_thread);
102EXPORT_SYMBOL(dump_fpu);
103EXPORT_SYMBOL(udelay);
104EXPORT_SYMBOL(kernel_thread);
105EXPORT_SYMBOL(system_rev);
106EXPORT_SYMBOL(system_serial_low);
107EXPORT_SYMBOL(system_serial_high);
108#ifdef CONFIG_DEBUG_BUGVERBOSE
109EXPORT_SYMBOL(__bug);
110#endif
111EXPORT_SYMBOL(__bad_xchg);
112EXPORT_SYMBOL(__readwrite_bug);
113EXPORT_SYMBOL(enable_irq);
114EXPORT_SYMBOL(disable_irq);
115EXPORT_SYMBOL(set_irq_type);
116EXPORT_SYMBOL(pm_idle);
117EXPORT_SYMBOL(pm_power_off);
118
119 /* processor dependencies */
120EXPORT_SYMBOL(__machine_arch_type);
121
122 /* networking */
123EXPORT_SYMBOL(csum_partial_copy_nocheck);
124EXPORT_SYMBOL(__csum_ipv6_magic);
125
126 /* io */
127#ifndef __raw_readsb
128EXPORT_SYMBOL(__raw_readsb);
129#endif
130#ifndef __raw_readsw
131EXPORT_SYMBOL(__raw_readsw);
132#endif
133#ifndef __raw_readsl
134EXPORT_SYMBOL(__raw_readsl);
135#endif
136#ifndef __raw_writesb
137EXPORT_SYMBOL(__raw_writesb);
138#endif
139#ifndef __raw_writesw
140EXPORT_SYMBOL(__raw_writesw);
141#endif
142#ifndef __raw_writesl
143EXPORT_SYMBOL(__raw_writesl);
144#endif
145
146 /* string / mem functions */
147EXPORT_SYMBOL(strcpy);
148EXPORT_SYMBOL(strncpy);
149EXPORT_SYMBOL(strcat);
150EXPORT_SYMBOL(strncat);
151EXPORT_SYMBOL(strcmp);
152EXPORT_SYMBOL(strncmp);
153EXPORT_SYMBOL(strchr);
154EXPORT_SYMBOL(strlen);
155EXPORT_SYMBOL(strnlen);
156EXPORT_SYMBOL(strpbrk);
157EXPORT_SYMBOL(strrchr);
158EXPORT_SYMBOL(strstr);
159EXPORT_SYMBOL(memset);
160EXPORT_SYMBOL(memcpy);
161EXPORT_SYMBOL(memmove);
162EXPORT_SYMBOL(memcmp);
163EXPORT_SYMBOL(memscan);
164EXPORT_SYMBOL(__memzero);
165
166 /* user mem (segment) */
167EXPORT_SYMBOL(uaccess_kernel);
168EXPORT_SYMBOL(uaccess_user);
169
170EXPORT_SYMBOL(__get_user_1);
171EXPORT_SYMBOL(__get_user_2);
172EXPORT_SYMBOL(__get_user_4);
173EXPORT_SYMBOL(__get_user_8);
174
175EXPORT_SYMBOL(__put_user_1);
176EXPORT_SYMBOL(__put_user_2);
177EXPORT_SYMBOL(__put_user_4);
178EXPORT_SYMBOL(__put_user_8);
179
180 /* gcc lib functions */
181EXPORT_SYMBOL(__ashldi3);
182EXPORT_SYMBOL(__ashrdi3);
183EXPORT_SYMBOL(__divsi3);
184EXPORT_SYMBOL(__lshrdi3);
185EXPORT_SYMBOL(__modsi3);
186EXPORT_SYMBOL(__muldi3);
187EXPORT_SYMBOL(__ucmpdi2);
188EXPORT_SYMBOL(__udivdi3);
189EXPORT_SYMBOL(__umoddi3);
190EXPORT_SYMBOL(__udivmoddi4);
191EXPORT_SYMBOL(__udivsi3);
192EXPORT_SYMBOL(__umodsi3);
193
194 /* bitops */
195EXPORT_SYMBOL(_set_bit_le);
196EXPORT_SYMBOL(_test_and_set_bit_le);
197EXPORT_SYMBOL(_clear_bit_le);
198EXPORT_SYMBOL(_test_and_clear_bit_le);
199EXPORT_SYMBOL(_change_bit_le);
200EXPORT_SYMBOL(_test_and_change_bit_le);
201EXPORT_SYMBOL(_find_first_zero_bit_le);
202EXPORT_SYMBOL(_find_next_zero_bit_le);
203
204 /* elf */
205EXPORT_SYMBOL(elf_platform);
206EXPORT_SYMBOL(elf_hwcap);
207
208 /* syscalls */
209EXPORT_SYMBOL(sys_write);
210EXPORT_SYMBOL(sys_read);
211EXPORT_SYMBOL(sys_lseek);
212EXPORT_SYMBOL(sys_open);
213EXPORT_SYMBOL(sys_exit);
214EXPORT_SYMBOL(sys_wait4);
215
216EXPORT_SYMBOL(get_wchan);
217
218#ifdef CONFIG_PREEMPT
219EXPORT_SYMBOL(kernel_flag);
220#endif
diff --git a/arch/arm26/kernel/asm-offsets.c b/arch/arm26/kernel/asm-offsets.c
new file mode 100644
index 000000000000..4ccacaef94df
--- /dev/null
+++ b/arch/arm26/kernel/asm-offsets.c
@@ -0,0 +1,63 @@
1/*
2 * Copyright (C) 1995-2001 Russell King
3 * 2001-2002 Keith Owens
4 * 2003 Ian Molton
5 *
6 * Generate definitions needed by assembly language modules.
7 * This code generates raw asm output which is post-processed to extract
8 * and format the required data.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/config.h>
16#include <linux/sched.h>
17#include <linux/mm.h>
18
19#include <asm/pgtable.h>
20#include <asm/uaccess.h>
21
22/*
23 * Make sure that the compiler and target are compatible.
24 */
25#if defined(__APCS_32__) && defined(CONFIG_CPU_26)
26#error Sorry, your compiler targets APCS-32 but this kernel requires APCS-26
27#endif
28#if __GNUC__ < 2 || (__GNUC__ == 2 && __GNUC_MINOR__ < 95)
29#error Sorry, your compiler is known to miscompile kernels. Only use gcc 2.95.3 and later.
30#endif
31#if __GNUC__ == 2 && __GNUC_MINOR__ == 95
32/* shame we can't detect the .1 or .2 releases */
33#warning GCC 2.95.2 and earlier miscompiles kernels.
34#endif
35
36/* Use marker if you need to separate the values later */
37
38#define DEFINE(sym, val) \
39 asm volatile("\n->" #sym " %0 " #val : : "i" (val))
40
41#define BLANK() asm volatile("\n->" : : )
42
43int main(void)
44{
45 DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
46 BLANK();
47 DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
48 DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags));
49 BLANK();
50 DEFINE(VM_EXEC, VM_EXEC);
51 BLANK();
52 BLANK();
53 DEFINE(PAGE_PRESENT, _PAGE_PRESENT);
54 DEFINE(PAGE_READONLY, _PAGE_READONLY);
55 DEFINE(PAGE_NOT_USER, _PAGE_NOT_USER);
56 DEFINE(PAGE_OLD, _PAGE_OLD);
57 DEFINE(PAGE_CLEAN, _PAGE_CLEAN);
58 BLANK();
59 DEFINE(PAGE_SZ, PAGE_SIZE);
60 BLANK();
61 DEFINE(SYS_ERROR0, 0x9f0000);
62 return 0;
63}
diff --git a/arch/arm26/kernel/calls.S b/arch/arm26/kernel/calls.S
new file mode 100644
index 000000000000..e3d276827c84
--- /dev/null
+++ b/arch/arm26/kernel/calls.S
@@ -0,0 +1,265 @@
1/*
2 * linux/arch/arm26/kernel/calls.S
3 *
4 * Copyright (C) 2003 Ian Molton
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * FIXME
11 * This file is included twice in entry.S which may not be necessary
12 */
13
14//FIXME - clearly NR_syscalls is never defined here
15
16#ifndef NR_syscalls
17#define NR_syscalls 256
18#else
19
20__syscall_start:
21/* 0 */ .long sys_ni_syscall
22 .long sys_exit
23 .long sys_fork_wrapper
24 .long sys_read
25 .long sys_write
26/* 5 */ .long sys_open
27 .long sys_close
28 .long sys_ni_syscall /* was sys_waitpid */
29 .long sys_creat
30 .long sys_link
31/* 10 */ .long sys_unlink
32 .long sys_execve_wrapper
33 .long sys_chdir
34 .long sys_time /* used by libc4 */
35 .long sys_mknod
36/* 15 */ .long sys_chmod
37 .long sys_lchown16
38 .long sys_ni_syscall /* was sys_break */
39 .long sys_ni_syscall /* was sys_stat */
40 .long sys_lseek
41/* 20 */ .long sys_getpid
42 .long sys_mount
43 .long sys_oldumount /* used by libc4 */
44 .long sys_setuid16
45 .long sys_getuid16
46/* 25 */ .long sys_stime
47 .long sys_ptrace
48 .long sys_alarm /* used by libc4 */
49 .long sys_ni_syscall /* was sys_fstat */
50 .long sys_pause
51/* 30 */ .long sys_utime /* used by libc4 */
52 .long sys_ni_syscall /* was sys_stty */
53 .long sys_ni_syscall /* was sys_getty */
54 .long sys_access
55 .long sys_nice
56/* 35 */ .long sys_ni_syscall /* was sys_ftime */
57 .long sys_sync
58 .long sys_kill
59 .long sys_rename
60 .long sys_mkdir
61/* 40 */ .long sys_rmdir
62 .long sys_dup
63 .long sys_pipe
64 .long sys_times
65 .long sys_ni_syscall /* was sys_prof */
66/* 45 */ .long sys_brk
67 .long sys_setgid16
68 .long sys_getgid16
69 .long sys_ni_syscall /* was sys_signal */
70 .long sys_geteuid16
71/* 50 */ .long sys_getegid16
72 .long sys_acct
73 .long sys_umount
74 .long sys_ni_syscall /* was sys_lock */
75 .long sys_ioctl
76/* 55 */ .long sys_fcntl
77 .long sys_ni_syscall /* was sys_mpx */
78 .long sys_setpgid
79 .long sys_ni_syscall /* was sys_ulimit */
80 .long sys_ni_syscall /* was sys_olduname */
81/* 60 */ .long sys_umask
82 .long sys_chroot
83 .long sys_ustat
84 .long sys_dup2
85 .long sys_getppid
86/* 65 */ .long sys_getpgrp
87 .long sys_setsid
88 .long sys_sigaction
89 .long sys_ni_syscall /* was sys_sgetmask */
90 .long sys_ni_syscall /* was sys_ssetmask */
91/* 70 */ .long sys_setreuid16
92 .long sys_setregid16
93 .long sys_sigsuspend_wrapper
94 .long sys_sigpending
95 .long sys_sethostname
96/* 75 */ .long sys_setrlimit
97 .long sys_old_getrlimit /* used by libc4 */
98 .long sys_getrusage
99 .long sys_gettimeofday
100 .long sys_settimeofday
101/* 80 */ .long sys_getgroups16
102 .long sys_setgroups16
103 .long old_select /* used by libc4 */
104 .long sys_symlink
105 .long sys_ni_syscall /* was sys_lstat */
106/* 85 */ .long sys_readlink
107 .long sys_uselib
108 .long sys_swapon
109 .long sys_reboot
110 .long old_readdir /* used by libc4 */
111/* 90 */ .long old_mmap /* used by libc4 */
112 .long sys_munmap
113 .long sys_truncate
114 .long sys_ftruncate
115 .long sys_fchmod
116/* 95 */ .long sys_fchown16
117 .long sys_getpriority
118 .long sys_setpriority
119 .long sys_ni_syscall /* was sys_profil */
120 .long sys_statfs
121/* 100 */ .long sys_fstatfs
122 .long sys_ni_syscall
123 .long sys_socketcall
124 .long sys_syslog
125 .long sys_setitimer
126/* 105 */ .long sys_getitimer
127 .long sys_newstat
128 .long sys_newlstat
129 .long sys_newfstat
130 .long sys_ni_syscall /* was sys_uname */
131/* 110 */ .long sys_ni_syscall /* was sys_iopl */
132 .long sys_vhangup
133 .long sys_ni_syscall
134 .long sys_syscall /* call a syscall */
135 .long sys_wait4
136/* 115 */ .long sys_swapoff
137 .long sys_sysinfo
138 .long sys_ipc
139 .long sys_fsync
140 .long sys_sigreturn_wrapper
141/* 120 */ .long sys_clone_wapper
142 .long sys_setdomainname
143 .long sys_newuname
144 .long sys_ni_syscall
145 .long sys_adjtimex
146/* 125 */ .long sys_mprotect
147 .long sys_sigprocmask
148 .long sys_ni_syscall /* WAS: sys_create_module */
149 .long sys_init_module
150 .long sys_delete_module
151/* 130 */ .long sys_ni_syscall /* WAS: sys_get_kernel_syms */
152 .long sys_quotactl
153 .long sys_getpgid
154 .long sys_fchdir
155 .long sys_bdflush
156/* 135 */ .long sys_sysfs
157 .long sys_personality
158 .long sys_ni_syscall /* .long _sys_afs_syscall */
159 .long sys_setfsuid16
160 .long sys_setfsgid16
161/* 140 */ .long sys_llseek
162 .long sys_getdents
163 .long sys_select
164 .long sys_flock
165 .long sys_msync
166/* 145 */ .long sys_readv
167 .long sys_writev
168 .long sys_getsid
169 .long sys_fdatasync
170 .long sys_sysctl
171/* 150 */ .long sys_mlock
172 .long sys_munlock
173 .long sys_mlockall
174 .long sys_munlockall
175 .long sys_sched_setparam
176/* 155 */ .long sys_sched_getparam
177 .long sys_sched_setscheduler
178 .long sys_sched_getscheduler
179 .long sys_sched_yield
180 .long sys_sched_get_priority_max
181/* 160 */ .long sys_sched_get_priority_min
182 .long sys_sched_rr_get_interval
183 .long sys_nanosleep
184 .long sys_arm_mremap
185 .long sys_setresuid16
186/* 165 */ .long sys_getresuid16
187 .long sys_ni_syscall
188 .long sys_ni_syscall /* WAS: sys_query_module */
189 .long sys_poll
190 .long sys_nfsservctl
191/* 170 */ .long sys_setresgid16
192 .long sys_getresgid16
193 .long sys_prctl
194 .long sys_rt_sigreturn_wrapper
195 .long sys_rt_sigaction
196/* 175 */ .long sys_rt_sigprocmask
197 .long sys_rt_sigpending
198 .long sys_rt_sigtimedwait
199 .long sys_rt_sigqueueinfo
200 .long sys_rt_sigsuspend_wrapper
201/* 180 */ .long sys_pread64
202 .long sys_pwrite64
203 .long sys_chown16
204 .long sys_getcwd
205 .long sys_capget
206/* 185 */ .long sys_capset
207 .long sys_sigaltstack_wrapper
208 .long sys_sendfile
209 .long sys_ni_syscall
210 .long sys_ni_syscall
211/* 190 */ .long sys_vfork_wrapper
212 .long sys_getrlimit
213 .long sys_mmap2
214 .long sys_truncate64
215 .long sys_ftruncate64
216/* 195 */ .long sys_stat64
217 .long sys_lstat64
218 .long sys_fstat64
219 .long sys_lchown
220 .long sys_getuid
221/* 200 */ .long sys_getgid
222 .long sys_geteuid
223 .long sys_getegid
224 .long sys_setreuid
225 .long sys_setregid
226/* 205 */ .long sys_getgroups
227 .long sys_setgroups
228 .long sys_fchown
229 .long sys_setresuid
230 .long sys_getresuid
231/* 210 */ .long sys_setresgid
232 .long sys_getresgid
233 .long sys_chown
234 .long sys_setuid
235 .long sys_setgid
236/* 215 */ .long sys_setfsuid
237 .long sys_setfsgid
238 .long sys_getdents64
239 .long sys_pivot_root
240 .long sys_mincore
241/* 220 */ .long sys_madvise
242 .long sys_fcntl64
243 .long sys_ni_syscall /* TUX */
244 .long sys_ni_syscall /* WAS: sys_security */
245 .long sys_gettid
246/* 225 */ .long sys_readahead
247 .long sys_setxattr
248 .long sys_lsetxattr
249 .long sys_fsetxattr
250 .long sys_getxattr
251/* 230 */ .long sys_lgetxattr
252 .long sys_fgetxattr
253 .long sys_listxattr
254 .long sys_llistxattr
255 .long sys_flistxattr
256/* 235 */ .long sys_removexattr
257 .long sys_lremovexattr
258 .long sys_fremovexattr
259 .long sys_tkill
260__syscall_end:
261
262 .rept NR_syscalls - (__syscall_end - __syscall_start) / 4
263 .long sys_ni_syscall
264 .endr
265#endif
diff --git a/arch/arm26/kernel/compat.c b/arch/arm26/kernel/compat.c
new file mode 100644
index 000000000000..db0310db8998
--- /dev/null
+++ b/arch/arm26/kernel/compat.c
@@ -0,0 +1,174 @@
1/*
2 * linux/arch/arm26/kernel/compat.c
3 *
4 * Copyright (C) 2001 Russell King
5 * 2003 Ian Molton
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * We keep the old params compatibility cruft in one place (here)
12 * so we don't end up with lots of mess around other places.
13 *
14 * NOTE:
15 * The old struct param_struct is deprecated, but it will be kept in
16 * the kernel for 5 years from now (2001). This will allow boot loaders
17 * to convert to the new struct tag way.
18 */
19#include <linux/config.h>
20#include <linux/types.h>
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/init.h>
24
25#include <asm/setup.h>
26#include <asm/mach-types.h>
27#include <asm/page.h>
28
29//#include <asm/arch.h>
30//#include <asm/mach/irq.h>
31
32/*
33 * Usage:
34 * - do not go blindly adding fields, add them at the end
35 * - when adding fields, don't rely on the address until
36 * a patch from me has been released
37 * - unused fields should be zero (for future expansion)
38 * - this structure is relatively short-lived - only
39 * guaranteed to contain useful data in setup_arch()
40 *
41 * This is the old deprecated way to pass parameters to the kernel
42 */
43struct param_struct {
44 union {
45 struct {
46 unsigned long page_size; /* 0 */
47 unsigned long nr_pages; /* 4 */
48 unsigned long ramdisk_size; /* 8 */
49 unsigned long flags; /* 12 */
50#define FLAG_READONLY 1
51#define FLAG_RDLOAD 4
52#define FLAG_RDPROMPT 8
53 unsigned long rootdev; /* 16 */
54 unsigned long video_num_cols; /* 20 */
55 unsigned long video_num_rows; /* 24 */
56 unsigned long video_x; /* 28 */
57 unsigned long video_y; /* 32 */
58 unsigned long memc_control_reg; /* 36 */
59 unsigned char sounddefault; /* 40 */
60 unsigned char adfsdrives; /* 41 */
61 unsigned char bytes_per_char_h; /* 42 */
62 unsigned char bytes_per_char_v; /* 43 */
63 unsigned long pages_in_bank[4]; /* 44 */
64 unsigned long pages_in_vram; /* 60 */
65 unsigned long initrd_start; /* 64 */
66 unsigned long initrd_size; /* 68 */
67 unsigned long rd_start; /* 72 */
68 unsigned long system_rev; /* 76 */
69 unsigned long system_serial_low; /* 80 */
70 unsigned long system_serial_high; /* 84 */
71 unsigned long mem_fclk_21285; /* 88 */
72 } s;
73 char unused[256];
74 } u1;
75 union {
76 char paths[8][128];
77 struct {
78 unsigned long magic;
79 char n[1024 - sizeof(unsigned long)];
80 } s;
81 } u2;
82 char commandline[COMMAND_LINE_SIZE];
83};
84
85static struct tag * __init memtag(struct tag *tag, unsigned long start, unsigned long size)
86{
87 tag = tag_next(tag);
88 tag->hdr.tag = ATAG_MEM;
89 tag->hdr.size = tag_size(tag_mem32);
90 tag->u.mem.size = size;
91 tag->u.mem.start = start;
92
93 return tag;
94}
95
96static void __init build_tag_list(struct param_struct *params, void *taglist)
97{
98 struct tag *tag = taglist;
99
100 if (params->u1.s.page_size != PAGE_SIZE) {
101 printk(KERN_WARNING "Warning: bad configuration page, "
102 "trying to continue\n");
103 return;
104 }
105
106 printk(KERN_DEBUG "Converting old-style param struct to taglist\n");
107
108 tag->hdr.tag = ATAG_CORE;
109 tag->hdr.size = tag_size(tag_core);
110 tag->u.core.flags = params->u1.s.flags & FLAG_READONLY;
111 tag->u.core.pagesize = params->u1.s.page_size;
112 tag->u.core.rootdev = params->u1.s.rootdev;
113
114 tag = tag_next(tag);
115 tag->hdr.tag = ATAG_RAMDISK;
116 tag->hdr.size = tag_size(tag_ramdisk);
117 tag->u.ramdisk.flags = (params->u1.s.flags & FLAG_RDLOAD ? 1 : 0) |
118 (params->u1.s.flags & FLAG_RDPROMPT ? 2 : 0);
119 tag->u.ramdisk.size = params->u1.s.ramdisk_size;
120 tag->u.ramdisk.start = params->u1.s.rd_start;
121
122 tag = tag_next(tag);
123 tag->hdr.tag = ATAG_INITRD;
124 tag->hdr.size = tag_size(tag_initrd);
125 tag->u.initrd.start = params->u1.s.initrd_start;
126 tag->u.initrd.size = params->u1.s.initrd_size;
127
128 tag = tag_next(tag);
129 tag->hdr.tag = ATAG_SERIAL;
130 tag->hdr.size = tag_size(tag_serialnr);
131 tag->u.serialnr.low = params->u1.s.system_serial_low;
132 tag->u.serialnr.high = params->u1.s.system_serial_high;
133
134 tag = tag_next(tag);
135 tag->hdr.tag = ATAG_REVISION;
136 tag->hdr.size = tag_size(tag_revision);
137 tag->u.revision.rev = params->u1.s.system_rev;
138
139 tag = memtag(tag, PHYS_OFFSET, params->u1.s.nr_pages * PAGE_SIZE);
140
141 tag = tag_next(tag);
142 tag->hdr.tag = ATAG_ACORN;
143 tag->hdr.size = tag_size(tag_acorn);
144 tag->u.acorn.memc_control_reg = params->u1.s.memc_control_reg;
145 tag->u.acorn.vram_pages = params->u1.s.pages_in_vram;
146 tag->u.acorn.sounddefault = params->u1.s.sounddefault;
147 tag->u.acorn.adfsdrives = params->u1.s.adfsdrives;
148
149 tag = tag_next(tag);
150 tag->hdr.tag = ATAG_CMDLINE;
151 tag->hdr.size = (strlen(params->commandline) + 3 +
152 sizeof(struct tag_header)) >> 2;
153 strcpy(tag->u.cmdline.cmdline, params->commandline);
154
155 tag = tag_next(tag);
156 tag->hdr.tag = ATAG_NONE;
157 tag->hdr.size = 0;
158
159 memmove(params, taglist, ((int)tag) - ((int)taglist) +
160 sizeof(struct tag_header));
161}
162
163void __init convert_to_tag_list(struct tag *tags)
164{
165 struct param_struct *params = (struct param_struct *)tags;
166 build_tag_list(params, &params->u2);
167}
168
169void __init squash_mem_tags(struct tag *tag)
170{
171 for (; tag->hdr.size; tag = tag_next(tag))
172 if (tag->hdr.tag == ATAG_MEM)
173 tag->hdr.tag = ATAG_NONE;
174}
diff --git a/arch/arm26/kernel/dma.c b/arch/arm26/kernel/dma.c
new file mode 100644
index 000000000000..80b5a774d905
--- /dev/null
+++ b/arch/arm26/kernel/dma.c
@@ -0,0 +1,273 @@
1/*
2 * linux/arch/arm26/kernel/dma.c
3 *
4 * Copyright (C) 1995-2000 Russell King
5 * 2003 Ian Molton
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Front-end to the DMA handling. This handles the allocation/freeing
12 * of DMA channels, and provides a unified interface to the machines
13 * DMA facilities.
14 */
15#include <linux/module.h>
16#include <linux/slab.h>
17#include <linux/sched.h>
18#include <linux/mman.h>
19#include <linux/init.h>
20#include <linux/spinlock.h>
21#include <linux/errno.h>
22
23#include <asm/dma.h>
24
25DEFINE_SPINLOCK(dma_spin_lock);
26
27static dma_t dma_chan[MAX_DMA_CHANNELS];
28
29/*
30 * Get dma list for /proc/dma
31 */
32int get_dma_list(char *buf)
33{
34 dma_t *dma;
35 char *p = buf;
36 int i;
37
38 for (i = 0, dma = dma_chan; i < MAX_DMA_CHANNELS; i++, dma++)
39 if (dma->lock)
40 p += sprintf(p, "%2d: %14s %s\n", i,
41 dma->d_ops->type, dma->device_id);
42
43 return p - buf;
44}
45
46/*
47 * Request DMA channel
48 *
49 * On certain platforms, we have to allocate an interrupt as well...
50 */
51int request_dma(dmach_t channel, const char *device_id)
52{
53 dma_t *dma = dma_chan + channel;
54 int ret;
55
56 if (channel >= MAX_DMA_CHANNELS || !dma->d_ops)
57 goto bad_dma;
58
59 if (xchg(&dma->lock, 1) != 0)
60 goto busy;
61
62 dma->device_id = device_id;
63 dma->active = 0;
64 dma->invalid = 1;
65
66 ret = 0;
67 if (dma->d_ops->request)
68 ret = dma->d_ops->request(channel, dma);
69
70 if (ret)
71 xchg(&dma->lock, 0);
72
73 return ret;
74
75bad_dma:
76 printk(KERN_ERR "dma: trying to allocate DMA%d\n", channel);
77 return -EINVAL;
78
79busy:
80 return -EBUSY;
81}
82
83/*
84 * Free DMA channel
85 *
86 * On certain platforms, we have to free interrupt as well...
87 */
88void free_dma(dmach_t channel)
89{
90 dma_t *dma = dma_chan + channel;
91
92 if (channel >= MAX_DMA_CHANNELS || !dma->d_ops)
93 goto bad_dma;
94
95 if (dma->active) {
96 printk(KERN_ERR "dma%d: freeing active DMA\n", channel);
97 dma->d_ops->disable(channel, dma);
98 dma->active = 0;
99 }
100
101 if (xchg(&dma->lock, 0) != 0) {
102 if (dma->d_ops->free)
103 dma->d_ops->free(channel, dma);
104 return;
105 }
106
107 printk(KERN_ERR "dma%d: trying to free free DMA\n", channel);
108 return;
109
110bad_dma:
111 printk(KERN_ERR "dma: trying to free DMA%d\n", channel);
112}
113
114/* Set DMA Scatter-Gather list
115 */
116void set_dma_sg (dmach_t channel, struct scatterlist *sg, int nr_sg)
117{
118 dma_t *dma = dma_chan + channel;
119
120 if (dma->active)
121 printk(KERN_ERR "dma%d: altering DMA SG while "
122 "DMA active\n", channel);
123
124 dma->sg = sg;
125 dma->sgcount = nr_sg;
126 dma->using_sg = 1;
127 dma->invalid = 1;
128}
129
130/* Set DMA address
131 *
132 * Copy address to the structure, and set the invalid bit
133 */
134void set_dma_addr (dmach_t channel, unsigned long physaddr)
135{
136 dma_t *dma = dma_chan + channel;
137
138 if (dma->active)
139 printk(KERN_ERR "dma%d: altering DMA address while "
140 "DMA active\n", channel);
141
142 dma->sg = &dma->buf;
143 dma->sgcount = 1;
144 dma->buf.__address = (char *)physaddr;//FIXME - not pretty
145 dma->using_sg = 0;
146 dma->invalid = 1;
147}
148
149/* Set DMA byte count
150 *
151 * Copy address to the structure, and set the invalid bit
152 */
153void set_dma_count (dmach_t channel, unsigned long count)
154{
155 dma_t *dma = dma_chan + channel;
156
157 if (dma->active)
158 printk(KERN_ERR "dma%d: altering DMA count while "
159 "DMA active\n", channel);
160
161 dma->sg = &dma->buf;
162 dma->sgcount = 1;
163 dma->buf.length = count;
164 dma->using_sg = 0;
165 dma->invalid = 1;
166}
167
168/* Set DMA direction mode
169 */
170void set_dma_mode (dmach_t channel, dmamode_t mode)
171{
172 dma_t *dma = dma_chan + channel;
173
174 if (dma->active)
175 printk(KERN_ERR "dma%d: altering DMA mode while "
176 "DMA active\n", channel);
177
178 dma->dma_mode = mode;
179 dma->invalid = 1;
180}
181
182/* Enable DMA channel
183 */
184void enable_dma (dmach_t channel)
185{
186 dma_t *dma = dma_chan + channel;
187
188 if (!dma->lock)
189 goto free_dma;
190
191 if (dma->active == 0) {
192 dma->active = 1;
193 dma->d_ops->enable(channel, dma);
194 }
195 return;
196
197free_dma:
198 printk(KERN_ERR "dma%d: trying to enable free DMA\n", channel);
199 BUG();
200}
201
202/* Disable DMA channel
203 */
204void disable_dma (dmach_t channel)
205{
206 dma_t *dma = dma_chan + channel;
207
208 if (!dma->lock)
209 goto free_dma;
210
211 if (dma->active == 1) {
212 dma->active = 0;
213 dma->d_ops->disable(channel, dma);
214 }
215 return;
216
217free_dma:
218 printk(KERN_ERR "dma%d: trying to disable free DMA\n", channel);
219 BUG();
220}
221
222/*
223 * Is the specified DMA channel active?
224 */
225int dma_channel_active(dmach_t channel)
226{
227 return dma_chan[channel].active;
228}
229
230void set_dma_page(dmach_t channel, char pagenr)
231{
232 printk(KERN_ERR "dma%d: trying to set_dma_page\n", channel);
233}
234
235void set_dma_speed(dmach_t channel, int cycle_ns)
236{
237 dma_t *dma = dma_chan + channel;
238 int ret = 0;
239
240 if (dma->d_ops->setspeed)
241 ret = dma->d_ops->setspeed(channel, dma, cycle_ns);
242 dma->speed = ret;
243}
244
245int get_dma_residue(dmach_t channel)
246{
247 dma_t *dma = dma_chan + channel;
248 int ret = 0;
249
250 if (dma->d_ops->residue)
251 ret = dma->d_ops->residue(channel, dma);
252
253 return ret;
254}
255
256void __init init_dma(void)
257{
258 arch_dma_init(dma_chan);
259}
260
261EXPORT_SYMBOL(request_dma);
262EXPORT_SYMBOL(free_dma);
263EXPORT_SYMBOL(enable_dma);
264EXPORT_SYMBOL(disable_dma);
265EXPORT_SYMBOL(set_dma_addr);
266EXPORT_SYMBOL(set_dma_count);
267EXPORT_SYMBOL(set_dma_mode);
268EXPORT_SYMBOL(set_dma_page);
269EXPORT_SYMBOL(get_dma_residue);
270EXPORT_SYMBOL(set_dma_sg);
271EXPORT_SYMBOL(set_dma_speed);
272
273EXPORT_SYMBOL(dma_spin_lock);
diff --git a/arch/arm26/kernel/ecard.c b/arch/arm26/kernel/ecard.c
new file mode 100644
index 000000000000..824c6b571ad9
--- /dev/null
+++ b/arch/arm26/kernel/ecard.c
@@ -0,0 +1,850 @@
1/*
2 * linux/arch/arm26/kernel/ecard.c
3 *
4 * Copyright 1995-2001 Russell King
5 * Copyright 2003 Ian Molton
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Find all installed expansion cards, and handle interrupts from them.
12 *
13 * Created from information from Acorns RiscOS3 PRMs
14 * 15-Jun-2003 IM Modified from ARM32 (RiscPC capable) version
15 * 10-Jan-1999 RMK Run loaders in a simulated RISC OS environment.
16 * 06-May-1997 RMK Added blacklist for cards whose loader doesn't work.
17 * 12-Sep-1997 RMK Created new handling of interrupt enables/disables
18 * - cards can now register their own routine to control
19 * interrupts (recommended).
20 * 29-Sep-1997 RMK Expansion card interrupt hardware not being re-enabled
21 * on reset from Linux. (Caused cards not to respond
22 * under RiscOS without hard reset).
23 *
24 */
25#define ECARD_C
26
27#include <linux/config.h>
28#include <linux/module.h>
29#include <linux/kernel.h>
30#include <linux/types.h>
31#include <linux/sched.h>
32#include <linux/interrupt.h>
33#include <linux/reboot.h>
34#include <linux/mm.h>
35#include <linux/slab.h>
36#include <linux/proc_fs.h>
37#include <linux/device.h>
38#include <linux/init.h>
39
40#include <asm/dma.h>
41#include <asm/ecard.h>
42#include <asm/hardware.h>
43#include <asm/io.h>
44#include <asm/irq.h>
45#include <asm/mmu_context.h>
46#include <asm/irqchip.h>
47#include <asm/tlbflush.h>
48
49enum req {
50 req_readbytes,
51 req_reset
52};
53
54struct ecard_request {
55 enum req req;
56 ecard_t *ec;
57 unsigned int address;
58 unsigned int length;
59 unsigned int use_loader;
60 void *buffer;
61};
62
63struct expcard_blacklist {
64 unsigned short manufacturer;
65 unsigned short product;
66 const char *type;
67};
68
69static ecard_t *cards;
70static ecard_t *slot_to_expcard[MAX_ECARDS];
71static unsigned int ectcr;
72
73/* List of descriptions of cards which don't have an extended
74 * identification, or chunk directories containing a description.
75 */
76static struct expcard_blacklist __initdata blacklist[] = {
77 { MANU_ACORN, PROD_ACORN_ETHER1, "Acorn Ether1" }
78};
79
80asmlinkage extern int
81ecard_loader_reset(volatile unsigned char *pa, loader_t loader);
82asmlinkage extern int
83ecard_loader_read(int off, volatile unsigned char *pa, loader_t loader);
84
85static const struct ecard_id *
86ecard_match_device(const struct ecard_id *ids, struct expansion_card *ec);
87
88static inline unsigned short
89ecard_getu16(unsigned char *v)
90{
91 return v[0] | v[1] << 8;
92}
93
94static inline signed long
95ecard_gets24(unsigned char *v)
96{
97 return v[0] | v[1] << 8 | v[2] << 16 | ((v[2] & 0x80) ? 0xff000000 : 0);
98}
99
100static inline ecard_t *
101slot_to_ecard(unsigned int slot)
102{
103 return slot < MAX_ECARDS ? slot_to_expcard[slot] : NULL;
104}
105
106/* ===================== Expansion card daemon ======================== */
107/*
108 * Since the loader programs on the expansion cards need to be run
109 * in a specific environment, create a separate task with this
110 * environment up, and pass requests to this task as and when we
111 * need to.
112 *
113 * This should allow 99% of loaders to be called from Linux.
114 *
115 * From a security standpoint, we trust the card vendors. This
116 * may be a misplaced trust.
117 */
118#define BUS_ADDR(x) ((((unsigned long)(x)) << 2) + IO_BASE)
119#define POD_INT_ADDR(x) ((volatile unsigned char *)\
120 ((BUS_ADDR((x)) - IO_BASE) + IO_START))
121
122static inline void ecard_task_reset(struct ecard_request *req)
123{
124 struct expansion_card *ec = req->ec;
125 if (ec->loader)
126 ecard_loader_reset(POD_INT_ADDR(ec->podaddr), ec->loader);
127}
128
129static void
130ecard_task_readbytes(struct ecard_request *req)
131{
132 unsigned char *buf = (unsigned char *)req->buffer;
133 volatile unsigned char *base_addr =
134 (volatile unsigned char *)POD_INT_ADDR(req->ec->podaddr);
135 unsigned int len = req->length;
136 unsigned int off = req->address;
137
138 if (!req->use_loader || !req->ec->loader) {
139 off *= 4;
140 while (len--) {
141 *buf++ = base_addr[off];
142 off += 4;
143 }
144 } else {
145 while(len--) {
146 /*
147 * The following is required by some
148 * expansion card loader programs.
149 */
150 *(unsigned long *)0x108 = 0;
151 *buf++ = ecard_loader_read(off++, base_addr,
152 req->ec->loader);
153 }
154 }
155}
156
157static void ecard_do_request(struct ecard_request *req)
158{
159 switch (req->req) {
160 case req_readbytes:
161 ecard_task_readbytes(req);
162 break;
163
164 case req_reset:
165 ecard_task_reset(req);
166 break;
167 }
168}
169
170/*
171 * On 26-bit processors, we don't need the kcardd thread to access the
172 * expansion card loaders. We do it directly.
173 */
174#define ecard_call(req) ecard_do_request(req)
175
176/* ======================= Mid-level card control ===================== */
177
178static void
179ecard_readbytes(void *addr, ecard_t *ec, int off, int len, int useld)
180{
181 struct ecard_request req;
182
183 req.req = req_readbytes;
184 req.ec = ec;
185 req.address = off;
186 req.length = len;
187 req.use_loader = useld;
188 req.buffer = addr;
189
190 ecard_call(&req);
191}
192
193int ecard_readchunk(struct in_chunk_dir *cd, ecard_t *ec, int id, int num)
194{
195 struct ex_chunk_dir excd;
196 int index = 16;
197 int useld = 0;
198
199 if (!ec->cid.cd)
200 return 0;
201
202 while(1) {
203 ecard_readbytes(&excd, ec, index, 8, useld);
204 index += 8;
205 if (c_id(&excd) == 0) {
206 if (!useld && ec->loader) {
207 useld = 1;
208 index = 0;
209 continue;
210 }
211 return 0;
212 }
213 if (c_id(&excd) == 0xf0) { /* link */
214 index = c_start(&excd);
215 continue;
216 }
217 if (c_id(&excd) == 0x80) { /* loader */
218 if (!ec->loader) {
219 ec->loader = (loader_t)kmalloc(c_len(&excd),
220 GFP_KERNEL);
221 if (ec->loader)
222 ecard_readbytes(ec->loader, ec,
223 (int)c_start(&excd),
224 c_len(&excd), useld);
225 else
226 return 0;
227 }
228 continue;
229 }
230 if (c_id(&excd) == id && num-- == 0)
231 break;
232 }
233
234 if (c_id(&excd) & 0x80) {
235 switch (c_id(&excd) & 0x70) {
236 case 0x70:
237 ecard_readbytes((unsigned char *)excd.d.string, ec,
238 (int)c_start(&excd), c_len(&excd),
239 useld);
240 break;
241 case 0x00:
242 break;
243 }
244 }
245 cd->start_offset = c_start(&excd);
246 memcpy(cd->d.string, excd.d.string, 256);
247 return 1;
248}
249
250/* ======================= Interrupt control ============================ */
251
252static void ecard_def_irq_enable(ecard_t *ec, int irqnr)
253{
254}
255
256static void ecard_def_irq_disable(ecard_t *ec, int irqnr)
257{
258}
259
260static int ecard_def_irq_pending(ecard_t *ec)
261{
262 return !ec->irqmask || ec->irqaddr[0] & ec->irqmask;
263}
264
265static void ecard_def_fiq_enable(ecard_t *ec, int fiqnr)
266{
267 panic("ecard_def_fiq_enable called - impossible");
268}
269
270static void ecard_def_fiq_disable(ecard_t *ec, int fiqnr)
271{
272 panic("ecard_def_fiq_disable called - impossible");
273}
274
275static int ecard_def_fiq_pending(ecard_t *ec)
276{
277 return !ec->fiqmask || ec->fiqaddr[0] & ec->fiqmask;
278}
279
280static expansioncard_ops_t ecard_default_ops = {
281 ecard_def_irq_enable,
282 ecard_def_irq_disable,
283 ecard_def_irq_pending,
284 ecard_def_fiq_enable,
285 ecard_def_fiq_disable,
286 ecard_def_fiq_pending
287};
288
289/*
290 * Enable and disable interrupts from expansion cards.
291 * (interrupts are disabled for these functions).
292 *
293 * They are not meant to be called directly, but via enable/disable_irq.
294 */
295static void ecard_irq_unmask(unsigned int irqnr)
296{
297 ecard_t *ec = slot_to_ecard(irqnr - 32);
298
299 if (ec) {
300 if (!ec->ops)
301 ec->ops = &ecard_default_ops;
302
303 if (ec->claimed && ec->ops->irqenable)
304 ec->ops->irqenable(ec, irqnr);
305 else
306 printk(KERN_ERR "ecard: rejecting request to "
307 "enable IRQs for %d\n", irqnr);
308 }
309}
310
311static void ecard_irq_mask(unsigned int irqnr)
312{
313 ecard_t *ec = slot_to_ecard(irqnr - 32);
314
315 if (ec) {
316 if (!ec->ops)
317 ec->ops = &ecard_default_ops;
318
319 if (ec->ops && ec->ops->irqdisable)
320 ec->ops->irqdisable(ec, irqnr);
321 }
322}
323
324static struct irqchip ecard_chip = {
325 .ack = ecard_irq_mask,
326 .mask = ecard_irq_mask,
327 .unmask = ecard_irq_unmask,
328};
329
330void ecard_enablefiq(unsigned int fiqnr)
331{
332 ecard_t *ec = slot_to_ecard(fiqnr);
333
334 if (ec) {
335 if (!ec->ops)
336 ec->ops = &ecard_default_ops;
337
338 if (ec->claimed && ec->ops->fiqenable)
339 ec->ops->fiqenable(ec, fiqnr);
340 else
341 printk(KERN_ERR "ecard: rejecting request to "
342 "enable FIQs for %d\n", fiqnr);
343 }
344}
345
346void ecard_disablefiq(unsigned int fiqnr)
347{
348 ecard_t *ec = slot_to_ecard(fiqnr);
349
350 if (ec) {
351 if (!ec->ops)
352 ec->ops = &ecard_default_ops;
353
354 if (ec->ops->fiqdisable)
355 ec->ops->fiqdisable(ec, fiqnr);
356 }
357}
358
359static void
360ecard_dump_irq_state(ecard_t *ec)
361{
362 printk(" %d: %sclaimed, ",
363 ec->slot_no,
364 ec->claimed ? "" : "not ");
365
366 if (ec->ops && ec->ops->irqpending &&
367 ec->ops != &ecard_default_ops)
368 printk("irq %spending\n",
369 ec->ops->irqpending(ec) ? "" : "not ");
370 else
371 printk("irqaddr %p, mask = %02X, status = %02X\n",
372 ec->irqaddr, ec->irqmask, *ec->irqaddr);
373}
374
375static void ecard_check_lockup(struct irqdesc *desc)
376{
377 static int last, lockup;
378 ecard_t *ec;
379
380 /*
381 * If the timer interrupt has not run since the last million
382 * unrecognised expansion card interrupts, then there is
383 * something seriously wrong. Disable the expansion card
384 * interrupts so at least we can continue.
385 *
386 * Maybe we ought to start a timer to re-enable them some time
387 * later?
388 */
389 if (last == jiffies) {
390 lockup += 1;
391 if (lockup > 1000000) {
392 printk(KERN_ERR "\nInterrupt lockup detected - "
393 "disabling all expansion card interrupts\n");
394
395 desc->chip->mask(IRQ_EXPANSIONCARD);
396
397 printk("Expansion card IRQ state:\n");
398
399 for (ec = cards; ec; ec = ec->next)
400 ecard_dump_irq_state(ec);
401 }
402 } else
403 lockup = 0;
404
405 /*
406 * If we did not recognise the source of this interrupt,
407 * warn the user, but don't flood the user with these messages.
408 */
409 if (!last || time_after(jiffies, (unsigned long)(last + 5*HZ))) {
410 last = jiffies;
411 printk(KERN_WARNING "Unrecognised interrupt from backplane\n");
412 }
413}
414
415static void
416ecard_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
417{
418 ecard_t *ec;
419 int called = 0;
420
421 desc->chip->mask(irq);
422 for (ec = cards; ec; ec = ec->next) {
423 int pending;
424
425 if (!ec->claimed || ec->irq == NO_IRQ)
426 continue;
427
428 if (ec->ops && ec->ops->irqpending)
429 pending = ec->ops->irqpending(ec);
430 else
431 pending = ecard_default_ops.irqpending(ec);
432
433 if (pending) {
434 struct irqdesc *d = irq_desc + ec->irq;
435 d->handle(ec->irq, d, regs);
436 called ++;
437 }
438 }
439 desc->chip->unmask(irq);
440
441 if (called == 0)
442 ecard_check_lockup(desc);
443}
444
445#define ecard_irqexp_handler NULL
446#define ecard_probeirqhw() (0)
447
448unsigned int ecard_address(ecard_t *ec, card_type_t type, card_speed_t speed)
449{
450 unsigned long address = 0;
451 int slot = ec->slot_no;
452
453 ectcr &= ~(1 << slot);
454
455 switch (type) {
456 case ECARD_MEMC:
457 address = IO_EC_MEMC_BASE + (slot << 12);
458 break;
459
460 case ECARD_IOC:
461 address = IO_EC_IOC_BASE + (slot << 12) + (speed << 17);
462 break;
463
464 default:
465 break;
466 }
467
468 return address;
469}
470
471static int ecard_prints(char *buffer, ecard_t *ec)
472{
473 char *start = buffer;
474
475 buffer += sprintf(buffer, " %d: ", ec->slot_no);
476
477 if (ec->cid.id == 0) {
478 struct in_chunk_dir incd;
479
480 buffer += sprintf(buffer, "[%04X:%04X] ",
481 ec->cid.manufacturer, ec->cid.product);
482
483 if (!ec->card_desc && ec->cid.cd &&
484 ecard_readchunk(&incd, ec, 0xf5, 0)) {
485 ec->card_desc = kmalloc(strlen(incd.d.string)+1, GFP_KERNEL);
486
487 if (ec->card_desc)
488 strcpy((char *)ec->card_desc, incd.d.string);
489 }
490
491 buffer += sprintf(buffer, "%s\n", ec->card_desc ? ec->card_desc : "*unknown*");
492 } else
493 buffer += sprintf(buffer, "Simple card %d\n", ec->cid.id);
494
495 return buffer - start;
496}
497
498static int get_ecard_dev_info(char *buf, char **start, off_t pos, int count)
499{
500 ecard_t *ec = cards;
501 off_t at = 0;
502 int len, cnt;
503
504 cnt = 0;
505 while (ec && count > cnt) {
506 len = ecard_prints(buf, ec);
507 at += len;
508 if (at >= pos) {
509 if (!*start) {
510 *start = buf + (pos - (at - len));
511 cnt = at - pos;
512 } else
513 cnt += len;
514 buf += len;
515 }
516 ec = ec->next;
517 }
518 return (count > cnt) ? cnt : count;
519}
520
521static struct proc_dir_entry *proc_bus_ecard_dir = NULL;
522
523static void ecard_proc_init(void)
524{
525 proc_bus_ecard_dir = proc_mkdir("ecard", proc_bus);
526 create_proc_info_entry("devices", 0, proc_bus_ecard_dir,
527 get_ecard_dev_info);
528}
529
530#define ec_set_resource(ec,nr,st,sz,flg) \
531 do { \
532 (ec)->resource[nr].name = ec->dev.bus_id; \
533 (ec)->resource[nr].start = st; \
534 (ec)->resource[nr].end = (st) + (sz) - 1; \
535 (ec)->resource[nr].flags = flg; \
536 } while (0)
537
538static void __init ecard_init_resources(struct expansion_card *ec)
539{
540 unsigned long base = PODSLOT_IOC0_BASE;
541 unsigned int slot = ec->slot_no;
542 int i;
543
544 ec_set_resource(ec, ECARD_RES_MEMC,
545 PODSLOT_MEMC_BASE + (slot << 14),
546 PODSLOT_MEMC_SIZE, IORESOURCE_MEM);
547
548 for (i = 0; i < ECARD_RES_IOCSYNC - ECARD_RES_IOCSLOW; i++) {
549 ec_set_resource(ec, i + ECARD_RES_IOCSLOW,
550 base + (slot << 14) + (i << 19),
551 PODSLOT_IOC_SIZE, IORESOURCE_MEM);
552 }
553
554 for (i = 0; i < ECARD_NUM_RESOURCES; i++) {
555 if (ec->resource[i].start &&
556 request_resource(&iomem_resource, &ec->resource[i])) {
557 printk(KERN_ERR "%s: resource(s) not available\n",
558 ec->dev.bus_id);
559 ec->resource[i].end -= ec->resource[i].start;
560 ec->resource[i].start = 0;
561 }
562 }
563}
564
565static ssize_t ecard_show_irq(struct device *dev, char *buf)
566{
567 struct expansion_card *ec = ECARD_DEV(dev);
568 return sprintf(buf, "%u\n", ec->irq);
569}
570
571static ssize_t ecard_show_vendor(struct device *dev, char *buf)
572{
573 struct expansion_card *ec = ECARD_DEV(dev);
574 return sprintf(buf, "%u\n", ec->cid.manufacturer);
575}
576
577static ssize_t ecard_show_device(struct device *dev, char *buf)
578{
579 struct expansion_card *ec = ECARD_DEV(dev);
580 return sprintf(buf, "%u\n", ec->cid.product);
581}
582
583static ssize_t ecard_show_dma(struct device *dev, char *buf)
584{
585 struct expansion_card *ec = ECARD_DEV(dev);
586 return sprintf(buf, "%u\n", ec->dma);
587}
588
589static ssize_t ecard_show_resources(struct device *dev, char *buf)
590{
591 struct expansion_card *ec = ECARD_DEV(dev);
592 char *str = buf;
593 int i;
594
595 for (i = 0; i < ECARD_NUM_RESOURCES; i++)
596 str += sprintf(str, "%08lx %08lx %08lx\n",
597 ec->resource[i].start,
598 ec->resource[i].end,
599 ec->resource[i].flags);
600
601 return str - buf;
602}
603
604static DEVICE_ATTR(irq, S_IRUGO, ecard_show_irq, NULL);
605static DEVICE_ATTR(vendor, S_IRUGO, ecard_show_vendor, NULL);
606static DEVICE_ATTR(device, S_IRUGO, ecard_show_device, NULL);
607static DEVICE_ATTR(dma, S_IRUGO, ecard_show_dma, NULL);
608static DEVICE_ATTR(resource, S_IRUGO, ecard_show_resources, NULL);
609
610/*
611 * Probe for an expansion card.
612 *
613 * If bit 1 of the first byte of the card is set, then the
614 * card does not exist.
615 */
616static int __init
617ecard_probe(int slot, card_type_t type)
618{
619 ecard_t **ecp;
620 ecard_t *ec;
621 struct ex_ecid cid;
622 int i, rc = -ENOMEM;
623
624 ec = kmalloc(sizeof(ecard_t), GFP_KERNEL);
625 if (!ec)
626 goto nomem;
627
628 memset(ec, 0, sizeof(ecard_t));
629
630 ec->slot_no = slot;
631 ec->type = type;
632 ec->irq = NO_IRQ;
633 ec->fiq = NO_IRQ;
634 ec->dma = NO_DMA;
635 ec->card_desc = NULL;
636 ec->ops = &ecard_default_ops;
637
638 rc = -ENODEV;
639 if ((ec->podaddr = ecard_address(ec, type, ECARD_SYNC)) == 0)
640 goto nodev;
641
642 cid.r_zero = 1;
643 ecard_readbytes(&cid, ec, 0, 16, 0);
644 if (cid.r_zero)
645 goto nodev;
646
647 ec->cid.id = cid.r_id;
648 ec->cid.cd = cid.r_cd;
649 ec->cid.is = cid.r_is;
650 ec->cid.w = cid.r_w;
651 ec->cid.manufacturer = ecard_getu16(cid.r_manu);
652 ec->cid.product = ecard_getu16(cid.r_prod);
653 ec->cid.country = cid.r_country;
654 ec->cid.irqmask = cid.r_irqmask;
655 ec->cid.irqoff = ecard_gets24(cid.r_irqoff);
656 ec->cid.fiqmask = cid.r_fiqmask;
657 ec->cid.fiqoff = ecard_gets24(cid.r_fiqoff);
658 ec->fiqaddr =
659 ec->irqaddr = (unsigned char *)ioaddr(ec->podaddr);
660
661 if (ec->cid.is) {
662 ec->irqmask = ec->cid.irqmask;
663 ec->irqaddr += ec->cid.irqoff;
664 ec->fiqmask = ec->cid.fiqmask;
665 ec->fiqaddr += ec->cid.fiqoff;
666 } else {
667 ec->irqmask = 1;
668 ec->fiqmask = 4;
669 }
670
671 for (i = 0; i < sizeof(blacklist) / sizeof(*blacklist); i++)
672 if (blacklist[i].manufacturer == ec->cid.manufacturer &&
673 blacklist[i].product == ec->cid.product) {
674 ec->card_desc = blacklist[i].type;
675 break;
676 }
677
678 snprintf(ec->dev.bus_id, sizeof(ec->dev.bus_id), "ecard%d", slot);
679 ec->dev.parent = NULL;
680 ec->dev.bus = &ecard_bus_type;
681 ec->dev.dma_mask = &ec->dma_mask;
682 ec->dma_mask = (u64)0xffffffff;
683
684 ecard_init_resources(ec);
685
686 /*
687 * hook the interrupt handlers
688 */
689 ec->irq = 32 + slot;
690 set_irq_chip(ec->irq, &ecard_chip);
691 set_irq_handler(ec->irq, do_level_IRQ);
692 set_irq_flags(ec->irq, IRQF_VALID);
693
694 for (ecp = &cards; *ecp; ecp = &(*ecp)->next);
695
696 *ecp = ec;
697 slot_to_expcard[slot] = ec;
698
699 device_register(&ec->dev);
700 device_create_file(&ec->dev, &dev_attr_dma);
701 device_create_file(&ec->dev, &dev_attr_irq);
702 device_create_file(&ec->dev, &dev_attr_resource);
703 device_create_file(&ec->dev, &dev_attr_vendor);
704 device_create_file(&ec->dev, &dev_attr_device);
705
706 return 0;
707
708nodev:
709 kfree(ec);
710nomem:
711 return rc;
712}
713
714/*
715 * Initialise the expansion card system.
716 * Locate all hardware - interrupt management and
717 * actual cards.
718 */
719static int __init ecard_init(void)
720{
721 int slot, irqhw;
722
723 printk("Probing expansion cards\n");
724
725 for (slot = 0; slot < MAX_ECARDS; slot ++) {
726 ecard_probe(slot, ECARD_IOC);
727 }
728
729 irqhw = ecard_probeirqhw();
730
731 set_irq_chained_handler(IRQ_EXPANSIONCARD,
732 irqhw ? ecard_irqexp_handler : ecard_irq_handler);
733
734 ecard_proc_init();
735
736 return 0;
737}
738
739subsys_initcall(ecard_init);
740
741/*
742 * ECARD "bus"
743 */
744static const struct ecard_id *
745ecard_match_device(const struct ecard_id *ids, struct expansion_card *ec)
746{
747 int i;
748
749 for (i = 0; ids[i].manufacturer != 65535; i++)
750 if (ec->cid.manufacturer == ids[i].manufacturer &&
751 ec->cid.product == ids[i].product)
752 return ids + i;
753
754 return NULL;
755}
756
757static int ecard_drv_probe(struct device *dev)
758{
759 struct expansion_card *ec = ECARD_DEV(dev);
760 struct ecard_driver *drv = ECARD_DRV(dev->driver);
761 const struct ecard_id *id;
762 int ret;
763
764 id = ecard_match_device(drv->id_table, ec);
765
766 ecard_claim(ec);
767 ret = drv->probe(ec, id);
768 if (ret)
769 ecard_release(ec);
770 return ret;
771}
772
773static int ecard_drv_remove(struct device *dev)
774{
775 struct expansion_card *ec = ECARD_DEV(dev);
776 struct ecard_driver *drv = ECARD_DRV(dev->driver);
777
778 drv->remove(ec);
779 ecard_release(ec);
780
781 return 0;
782}
783
784/*
785 * Before rebooting, we must make sure that the expansion card is in a
786 * sensible state, so it can be re-detected. This means that the first
787 * page of the ROM must be visible. We call the expansion cards reset
788 * handler, if any.
789 */
790static void ecard_drv_shutdown(struct device *dev)
791{
792 struct expansion_card *ec = ECARD_DEV(dev);
793 struct ecard_driver *drv = ECARD_DRV(dev->driver);
794 struct ecard_request req;
795
796 if (drv->shutdown)
797 drv->shutdown(ec);
798 ecard_release(ec);
799 req.req = req_reset;
800 req.ec = ec;
801 ecard_call(&req);
802}
803
804int ecard_register_driver(struct ecard_driver *drv)
805{
806 drv->drv.bus = &ecard_bus_type;
807 drv->drv.probe = ecard_drv_probe;
808 drv->drv.remove = ecard_drv_remove;
809 drv->drv.shutdown = ecard_drv_shutdown;
810
811 return driver_register(&drv->drv);
812}
813
814void ecard_remove_driver(struct ecard_driver *drv)
815{
816 driver_unregister(&drv->drv);
817}
818
819static int ecard_match(struct device *_dev, struct device_driver *_drv)
820{
821 struct expansion_card *ec = ECARD_DEV(_dev);
822 struct ecard_driver *drv = ECARD_DRV(_drv);
823 int ret;
824
825 if (drv->id_table) {
826 ret = ecard_match_device(drv->id_table, ec) != NULL;
827 } else {
828 ret = ec->cid.id == drv->id;
829 }
830
831 return ret;
832}
833
834struct bus_type ecard_bus_type = {
835 .name = "ecard",
836 .match = ecard_match,
837};
838
839static int ecard_bus_init(void)
840{
841 return bus_register(&ecard_bus_type);
842}
843
844postcore_initcall(ecard_bus_init);
845
846EXPORT_SYMBOL(ecard_readchunk);
847EXPORT_SYMBOL(ecard_address);
848EXPORT_SYMBOL(ecard_register_driver);
849EXPORT_SYMBOL(ecard_remove_driver);
850EXPORT_SYMBOL(ecard_bus_type);
diff --git a/arch/arm26/kernel/entry.S b/arch/arm26/kernel/entry.S
new file mode 100644
index 000000000000..a231dd88d0e1
--- /dev/null
+++ b/arch/arm26/kernel/entry.S
@@ -0,0 +1,961 @@
1/* arch/arm26/kernel/entry.S
2 *
3 * Assembled from chunks of code in arch/arm
4 *
5 * Copyright (C) 2003 Ian Molton
6 * Based on the work of RMK.
7 *
8 */
9
10#include <linux/linkage.h>
11
12#include <asm/assembler.h>
13#include <asm/asm_offsets.h>
14#include <asm/errno.h>
15#include <asm/hardware.h>
16#include <asm/sysirq.h>
17#include <asm/thread_info.h>
18#include <asm/page.h>
19#include <asm/ptrace.h>
20
21 .macro zero_fp
22#ifndef CONFIG_NO_FRAME_POINTER
23 mov fp, #0
24#endif
25 .endm
26
27 .text
28
29@ Bad Abort numbers
30@ -----------------
31@
32#define BAD_PREFETCH 0
33#define BAD_DATA 1
34#define BAD_ADDREXCPTN 2
35#define BAD_IRQ 3
36#define BAD_UNDEFINSTR 4
37
38@ OS version number used in SWIs
39@ RISC OS is 0
40@ RISC iX is 8
41@
42#define OS_NUMBER 9
43#define ARMSWI_OFFSET 0x000f0000
44
45@
46@ Stack format (ensured by USER_* and SVC_*)
47@ PSR and PC are comined on arm26
48@
49
50#define S_OFF 8
51
52#define S_OLD_R0 64
53#define S_PC 60
54#define S_LR 56
55#define S_SP 52
56#define S_IP 48
57#define S_FP 44
58#define S_R10 40
59#define S_R9 36
60#define S_R8 32
61#define S_R7 28
62#define S_R6 24
63#define S_R5 20
64#define S_R4 16
65#define S_R3 12
66#define S_R2 8
67#define S_R1 4
68#define S_R0 0
69
70 .macro save_user_regs
71 str r0, [sp, #-4]! @ Store SVC r0
72 str lr, [sp, #-4]! @ Store user mode PC
73 sub sp, sp, #15*4
74 stmia sp, {r0 - lr}^ @ Store the other user-mode regs
75 mov r0, r0
76 .endm
77
78 .macro slow_restore_user_regs
79 ldmia sp, {r0 - lr}^ @ restore the user regs not including PC
80 mov r0, r0
81 ldr lr, [sp, #15*4] @ get user PC
82 add sp, sp, #15*4+8 @ free stack
83 movs pc, lr @ return
84 .endm
85
86 .macro fast_restore_user_regs
87 add sp, sp, #S_OFF
88 ldmib sp, {r1 - lr}^
89 mov r0, r0
90 ldr lr, [sp, #15*4]
91 add sp, sp, #15*4+8
92 movs pc, lr
93 .endm
94
95 .macro save_svc_regs
96 str sp, [sp, #-16]!
97 str lr, [sp, #8]
98 str lr, [sp, #4]
99 stmfd sp!, {r0 - r12}
100 mov r0, #-1
101 str r0, [sp, #S_OLD_R0]
102 zero_fp
103 .endm
104
105 .macro save_svc_regs_irq
106 str sp, [sp, #-16]!
107 str lr, [sp, #4]
108 ldr lr, .LCirq
109 ldr lr, [lr]
110 str lr, [sp, #8]
111 stmfd sp!, {r0 - r12}
112 mov r0, #-1
113 str r0, [sp, #S_OLD_R0]
114 zero_fp
115 .endm
116
117 .macro restore_svc_regs
118 ldmfd sp, {r0 - pc}^
119 .endm
120
121 .macro mask_pc, rd, rm
122 bic \rd, \rm, #PCMASK
123 .endm
124
125 .macro disable_irqs, temp
126 mov \temp, pc
127 orr \temp, \temp, #PSR_I_BIT
128 teqp \temp, #0
129 .endm
130
131 .macro enable_irqs, temp
132 mov \temp, pc
133 and \temp, \temp, #~PSR_I_BIT
134 teqp \temp, #0
135 .endm
136
137 .macro initialise_traps_extra
138 .endm
139
140 .macro get_thread_info, rd
141 mov \rd, sp, lsr #13
142 mov \rd, \rd, lsl #13
143 .endm
144
145/*
146 * These are the registers used in the syscall handler, and allow us to
147 * have in theory up to 7 arguments to a function - r0 to r6.
148 *
149 * Note that tbl == why is intentional.
150 *
151 * We must set at least "tsk" and "why" when calling ret_with_reschedule.
152 */
153scno .req r7 @ syscall number
154tbl .req r8 @ syscall table pointer
155why .req r8 @ Linux syscall (!= 0)
156tsk .req r9 @ current thread_info
157
158/*
159 * Get the system call number.
160 */
161 .macro get_scno
162 mask_pc lr, lr
163 ldr scno, [lr, #-4] @ get SWI instruction
164 .endm
165/*
166 * -----------------------------------------------------------------------
167 */
168
169/*
170 * We rely on the fact that R0 is at the bottom of the stack (due to
171 * slow/fast restore user regs).
172 */
173#if S_R0 != 0
174#error "Please fix"
175#endif
176
177/*
178 * This is the fast syscall return path. We do as little as
179 * possible here, and this includes saving r0 back into the SVC
180 * stack.
181 */
182ret_fast_syscall:
183 disable_irqs r1 @ disable interrupts
184 ldr r1, [tsk, #TI_FLAGS]
185 tst r1, #_TIF_WORK_MASK
186 bne fast_work_pending
187 fast_restore_user_regs
188
189/*
190 * Ok, we need to do extra processing, enter the slow path.
191 */
192fast_work_pending:
193 str r0, [sp, #S_R0+S_OFF]! @ returned r0
194work_pending:
195 tst r1, #_TIF_NEED_RESCHED
196 bne work_resched
197 tst r1, #_TIF_NOTIFY_RESUME | _TIF_SIGPENDING
198 beq no_work_pending
199 mov r0, sp @ 'regs'
200 mov r2, why @ 'syscall'
201 bl do_notify_resume
202 disable_irqs r1 @ disable interrupts
203 b no_work_pending
204
205work_resched:
206 bl schedule
207/*
208 * "slow" syscall return path. "why" tells us if this was a real syscall.
209 */
210ENTRY(ret_to_user)
211ret_slow_syscall:
212 disable_irqs r1 @ disable interrupts
213 ldr r1, [tsk, #TI_FLAGS]
214 tst r1, #_TIF_WORK_MASK
215 bne work_pending
216no_work_pending:
217 slow_restore_user_regs
218
219/*
220 * This is how we return from a fork.
221 */
222ENTRY(ret_from_fork)
223 bl schedule_tail
224 get_thread_info tsk
225 ldr r1, [tsk, #TI_FLAGS] @ check for syscall tracing
226 mov why, #1
227 tst r1, #_TIF_SYSCALL_TRACE @ are we tracing syscalls?
228 beq ret_slow_syscall
229 mov r1, sp
230 mov r0, #1 @ trace exit [IP = 1]
231 bl syscall_trace
232 b ret_slow_syscall
233
234// FIXME - is this strictly necessary?
235#include "calls.S"
236
237/*=============================================================================
238 * SWI handler
239 *-----------------------------------------------------------------------------
240 */
241
242 .align 5
243ENTRY(vector_swi)
244 save_user_regs
245 zero_fp
246 get_scno
247
248#ifdef CONFIG_ALIGNMENT_TRAP
249 ldr ip, __cr_alignment
250 ldr ip, [ip]
251 mcr p15, 0, ip, c1, c0 @ update control register
252#endif
253 enable_irqs ip
254
255 str r4, [sp, #-S_OFF]! @ push fifth arg
256
257 get_thread_info tsk
258 ldr ip, [tsk, #TI_FLAGS] @ check for syscall tracing
259 bic scno, scno, #0xff000000 @ mask off SWI op-code
260 eor scno, scno, #OS_NUMBER << 20 @ check OS number
261 adr tbl, sys_call_table @ load syscall table pointer
262 tst ip, #_TIF_SYSCALL_TRACE @ are we tracing syscalls?
263 bne __sys_trace
264
265 adral lr, ret_fast_syscall @ set return address
266 orral lr, lr, #PSR_I_BIT | MODE_SVC26 @ Force SVC mode on return
267 cmp scno, #NR_syscalls @ check upper syscall limit
268 ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine
269
270 add r1, sp, #S_OFF
2712: mov why, #0 @ no longer a real syscall
272 cmp scno, #ARMSWI_OFFSET
273 eor r0, scno, #OS_NUMBER << 20 @ put OS number back
274 bcs arm_syscall
275 b sys_ni_syscall @ not private func
276
277 /*
278 * This is the really slow path. We're going to be doing
279 * context switches, and waiting for our parent to respond.
280 */
281__sys_trace:
282 add r1, sp, #S_OFF
283 mov r0, #0 @ trace entry [IP = 0]
284 bl syscall_trace
285
286 adral lr, __sys_trace_return @ set return address
287 orral lr, lr, #PSR_I_BIT | MODE_SVC26 @ Force SVC mode on return
288 add r1, sp, #S_R0 + S_OFF @ pointer to regs
289 cmp scno, #NR_syscalls @ check upper syscall limit
290 ldmccia r1, {r0 - r3} @ have to reload r0 - r3
291 ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine
292 b 2b
293
294__sys_trace_return:
295 str r0, [sp, #S_R0 + S_OFF]! @ save returned r0
296 mov r1, sp
297 mov r0, #1 @ trace exit [IP = 1]
298 bl syscall_trace
299 b ret_slow_syscall
300
301 .align 5
302#ifdef CONFIG_ALIGNMENT_TRAP
303 .type __cr_alignment, #object
304__cr_alignment:
305 .word cr_alignment
306#endif
307
308 .type sys_call_table, #object
309ENTRY(sys_call_table)
310#include "calls.S"
311
312/*============================================================================
313 * Special system call wrappers
314 */
315@ r0 = syscall number
316@ r5 = syscall table
317 .type sys_syscall, #function
318sys_syscall:
319 eor scno, r0, #OS_NUMBER << 20
320 cmp scno, #NR_syscalls @ check range
321 stmleia sp, {r5, r6} @ shuffle args
322 movle r0, r1
323 movle r1, r2
324 movle r2, r3
325 movle r3, r4
326 ldrle pc, [tbl, scno, lsl #2]
327 b sys_ni_syscall
328
329sys_fork_wrapper:
330 add r0, sp, #S_OFF
331 b sys_fork
332
333sys_vfork_wrapper:
334 add r0, sp, #S_OFF
335 b sys_vfork
336
337sys_execve_wrapper:
338 add r3, sp, #S_OFF
339 b sys_execve
340
341sys_clone_wapper:
342 add r2, sp, #S_OFF
343 b sys_clone
344
345sys_sigsuspend_wrapper:
346 add r3, sp, #S_OFF
347 b sys_sigsuspend
348
349sys_rt_sigsuspend_wrapper:
350 add r2, sp, #S_OFF
351 b sys_rt_sigsuspend
352
353sys_sigreturn_wrapper:
354 add r0, sp, #S_OFF
355 b sys_sigreturn
356
357sys_rt_sigreturn_wrapper:
358 add r0, sp, #S_OFF
359 b sys_rt_sigreturn
360
361sys_sigaltstack_wrapper:
362 ldr r2, [sp, #S_OFF + S_SP]
363 b do_sigaltstack
364
365/*
366 * Note: off_4k (r5) is always units of 4K. If we can't do the requested
367 * offset, we return EINVAL. FIXME - this lost some stuff from arm32 to
368 * ifdefs. check it out.
369 */
370sys_mmap2:
371 tst r5, #((1 << (PAGE_SHIFT - 12)) - 1)
372 moveq r5, r5, lsr #PAGE_SHIFT - 12
373 streq r5, [sp, #4]
374 beq do_mmap2
375 mov r0, #-EINVAL
376 RETINSTR(mov,pc, lr)
377
378/*
379 * Design issues:
380 * - We have several modes that each vector can be called from,
381 * each with its own set of registers. On entry to any vector,
382 * we *must* save the registers used in *that* mode.
383 *
384 * - This code must be as fast as possible.
385 *
386 * There are a few restrictions on the vectors:
387 * - the SWI vector cannot be called from *any* non-user mode
388 *
389 * - the FP emulator is *never* called from *any* non-user mode undefined
390 * instruction.
391 *
392 */
393
394 .text
395
396 .macro handle_irq
3971: mov r4, #IOC_BASE
398 ldrb r6, [r4, #0x24] @ get high priority first
399 adr r5, irq_prio_h
400 teq r6, #0
401 ldreqb r6, [r4, #0x14] @ get low priority
402 adreq r5, irq_prio_l
403
404 teq r6, #0 @ If an IRQ happened...
405 ldrneb r0, [r5, r6] @ get IRQ number
406 movne r1, sp @ get struct pt_regs
407 adrne lr, 1b @ Set return address to 1b
408 orrne lr, lr, #PSR_I_BIT | MODE_SVC26 @ (and force SVC mode)
409 bne asm_do_IRQ @ process IRQ (if asserted)
410 .endm
411
412
413/*
414 * Interrupt table (incorporates priority)
415 */
416 .macro irq_prio_table
417irq_prio_l: .byte 0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
418 .byte 4, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
419 .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
420 .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
421 .byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3
422 .byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3
423 .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
424 .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
425 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
426 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
427 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
428 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
429 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
430 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
431 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
432 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
433irq_prio_h: .byte 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
434 .byte 12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
435 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
436 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
437 .byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10
438 .byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10
439 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
440 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
441 .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
442 .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
443 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
444 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
445 .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
446 .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
447 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
448 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
449 .endm
450
451#if 1
452/*
453 * Uncomment these if you wish to get more debugging into about data aborts.
454 * FIXME - I bet we can find a way to encode these and keep performance.
455 */
456#define FAULT_CODE_LDRSTRPOST 0x80
457#define FAULT_CODE_LDRSTRPRE 0x40
458#define FAULT_CODE_LDRSTRREG 0x20
459#define FAULT_CODE_LDMSTM 0x10
460#define FAULT_CODE_LDCSTC 0x08
461#endif
462#define FAULT_CODE_PREFETCH 0x04
463#define FAULT_CODE_WRITE 0x02
464#define FAULT_CODE_FORCECOW 0x01
465
466/*=============================================================================
467 * Undefined FIQs
468 *-----------------------------------------------------------------------------
469 */
470_unexp_fiq: ldr sp, .LCfiq
471 mov r12, #IOC_BASE
472 strb r12, [r12, #0x38] @ Disable FIQ register
473 teqp pc, #PSR_I_BIT | PSR_F_BIT | MODE_SVC26
474 mov r0, r0
475 stmfd sp!, {r0 - r3, ip, lr}
476 adr r0, Lfiqmsg
477 bl printk
478 ldmfd sp!, {r0 - r3, ip, lr}
479 teqp pc, #PSR_I_BIT | PSR_F_BIT | MODE_FIQ26
480 mov r0, r0
481 movs pc, lr
482
483Lfiqmsg: .ascii "*** Unexpected FIQ\n\0"
484 .align
485
486.LCfiq: .word __temp_fiq
487.LCirq: .word __temp_irq
488
489/*=============================================================================
490 * Undefined instruction handler
491 *-----------------------------------------------------------------------------
492 * Handles floating point instructions
493 */
494vector_undefinstr:
495 tst lr, #MODE_SVC26 @ did we come from a non-user mode?
496 bne __und_svc @ yes - deal with it.
497/* Otherwise, fall through for the user-space (common) case. */
498 save_user_regs
499 zero_fp @ zero frame pointer
500 teqp pc, #PSR_I_BIT | MODE_SVC26 @ disable IRQs
501.Lbug_undef:
502 ldr r4, .LC2
503 ldr pc, [r4] @ Call FP module entry point
504/* FIXME - should we trap for a null pointer here? */
505
506/* The SVC mode case */
507__und_svc: save_svc_regs @ Non-user mode
508 mask_pc r0, lr
509 and r2, lr, #3
510 sub r0, r0, #4
511 mov r1, sp
512 bl do_undefinstr
513 restore_svc_regs
514
515/* We get here if the FP emulator doesnt handle the undef instr.
516 * If the insn WAS handled, the emulator jumps to ret_from_exception by itself/
517 */
518 .globl fpundefinstr
519fpundefinstr:
520 mov r0, lr
521 mov r1, sp
522 teqp pc, #MODE_SVC26
523 bl do_undefinstr
524 b ret_from_exception @ Normal FP exit
525
526#if defined CONFIG_FPE_NWFPE || defined CONFIG_FPE_FASTFPE
527 /* The FPE is always present */
528 .equ fpe_not_present, 0
529#else
530/* We get here if an undefined instruction happens and the floating
531 * point emulator is not present. If the offending instruction was
532 * a WFS, we just perform a normal return as if we had emulated the
533 * operation. This is a hack to allow some basic userland binaries
534 * to run so that the emulator module proper can be loaded. --philb
535 * FIXME - probably a broken useless hack...
536 */
537fpe_not_present:
538 adr r10, wfs_mask_data
539 ldmia r10, {r4, r5, r6, r7, r8}
540 ldr r10, [sp, #S_PC] @ Load PC
541 sub r10, r10, #4
542 mask_pc r10, r10
543 ldrt r10, [r10] @ get instruction
544 and r5, r10, r5
545 teq r5, r4 @ Is it WFS?
546 beq ret_from_exception
547 and r5, r10, r8
548 teq r5, r6 @ Is it LDF/STF on sp or fp?
549 teqne r5, r7
550 bne fpundefinstr
551 tst r10, #0x00200000 @ Does it have WB
552 beq ret_from_exception
553 and r4, r10, #255 @ get offset
554 and r6, r10, #0x000f0000
555 tst r10, #0x00800000 @ +/-
556 ldr r5, [sp, r6, lsr #14] @ Load reg
557 rsbeq r4, r4, #0
558 add r5, r5, r4, lsl #2
559 str r5, [sp, r6, lsr #14] @ Save reg
560 b ret_from_exception
561
562wfs_mask_data: .word 0x0e200110 @ WFS/RFS
563 .word 0x0fef0fff
564 .word 0x0d0d0100 @ LDF [sp]/STF [sp]
565 .word 0x0d0b0100 @ LDF [fp]/STF [fp]
566 .word 0x0f0f0f00
567#endif
568
569.LC2: .word fp_enter
570
571/*=============================================================================
572 * Prefetch abort handler
573 *-----------------------------------------------------------------------------
574 */
575#define DEBUG_UNDEF
576/* remember: lr = USR pc */
577vector_prefetch:
578 sub lr, lr, #4
579 tst lr, #MODE_SVC26
580 bne __pabt_invalid
581 save_user_regs
582 teqp pc, #MODE_SVC26 @ Enable IRQs...
583 mask_pc r0, lr @ Address of abort
584 mov r1, sp @ Tasks registers
585 bl do_PrefetchAbort
586 teq r0, #0 @ If non-zero, we believe this abort..
587 bne ret_from_exception
588#ifdef DEBUG_UNDEF
589 adr r0, t
590 bl printk
591#endif
592 ldr lr, [sp,#S_PC] @ FIXME program to test this on. I think its
593 b .Lbug_undef @ broken at the moment though!)
594
595__pabt_invalid: save_svc_regs
596 mov r0, sp @ Prefetch aborts are definitely *not*
597 mov r1, #BAD_PREFETCH @ allowed in non-user modes. We cant
598 and r2, lr, #3 @ recover from this problem.
599 b bad_mode
600
601#ifdef DEBUG_UNDEF
602t: .ascii "*** undef ***\r\n\0"
603 .align
604#endif
605
606/*=============================================================================
607 * Address exception handler
608 *-----------------------------------------------------------------------------
609 * These aren't too critical.
610 * (they're not supposed to happen).
611 * In order to debug the reason for address exceptions in non-user modes,
612 * we have to obtain all the registers so that we can see what's going on.
613 */
614
615vector_addrexcptn:
616 sub lr, lr, #8
617 tst lr, #3
618 bne Laddrexcptn_not_user
619 save_user_regs
620 teq pc, #MODE_SVC26
621 mask_pc r0, lr @ Point to instruction
622 mov r1, sp @ Point to registers
623 mov r2, #0x400
624 mov lr, pc
625 bl do_excpt
626 b ret_from_exception
627
628Laddrexcptn_not_user:
629 save_svc_regs
630 and r2, lr, #3
631 teq r2, #3
632 bne Laddrexcptn_illegal_mode
633 teqp pc, #MODE_SVC26
634 mask_pc r0, lr
635 mov r1, sp
636 orr r2, r2, #0x400
637 bl do_excpt
638 ldmia sp, {r0 - lr} @ I cant remember the reason I changed this...
639 add sp, sp, #15*4
640 movs pc, lr
641
642Laddrexcptn_illegal_mode:
643 mov r0, sp
644 str lr, [sp, #-4]!
645 orr r1, r2, #PSR_I_BIT | PSR_F_BIT
646 teqp r1, #0 @ change into mode (wont be user mode)
647 mov r0, r0
648 mov r1, r8 @ Any register from r8 - r14 can be banked
649 mov r2, r9
650 mov r3, r10
651 mov r4, r11
652 mov r5, r12
653 mov r6, r13
654 mov r7, r14
655 teqp pc, #PSR_F_BIT | MODE_SVC26 @ back to svc
656 mov r0, r0
657 stmfd sp!, {r1-r7}
658 ldmia r0, {r0-r7}
659 stmfd sp!, {r0-r7}
660 mov r0, sp
661 mov r1, #BAD_ADDREXCPTN
662 b bad_mode
663
664/*=============================================================================
665 * Interrupt (IRQ) handler
666 *-----------------------------------------------------------------------------
667 * Note: if the IRQ was taken whilst in user mode, then *no* kernel routine
668 * is running, so do not have to save svc lr.
669 *
670 * Entered in IRQ mode.
671 */
672
673vector_IRQ: ldr sp, .LCirq @ Setup some temporary stack
674 sub lr, lr, #4
675 str lr, [sp] @ push return address
676
677 tst lr, #3
678 bne __irq_non_usr
679
680__irq_usr: teqp pc, #PSR_I_BIT | MODE_SVC26 @ Enter SVC mode
681 mov r0, r0
682
683 ldr lr, .LCirq
684 ldr lr, [lr] @ Restore lr for jump back to USR
685
686 save_user_regs
687
688 handle_irq
689
690 mov why, #0
691 get_thread_info tsk
692 b ret_to_user
693
694@ Place the IRQ priority table here so that the handle_irq macros above
695@ and below here can access it.
696
697 irq_prio_table
698
699__irq_non_usr: teqp pc, #PSR_I_BIT | MODE_SVC26 @ Enter SVC mode
700 mov r0, r0
701
702 save_svc_regs_irq
703
704 and r2, lr, #3
705 teq r2, #3
706 bne __irq_invalid @ IRQ not from SVC mode
707
708 handle_irq
709
710 restore_svc_regs
711
712__irq_invalid: mov r0, sp
713 mov r1, #BAD_IRQ
714 b bad_mode
715
716/*=============================================================================
717 * Data abort handler code
718 *-----------------------------------------------------------------------------
719 *
720 * This handles both exceptions from user and SVC modes, computes the address
721 * range of the problem, and does any correction that is required. It then
722 * calls the kernel data abort routine.
723 *
724 * This is where I wish that the ARM would tell you which address aborted.
725 */
726
727vector_data: sub lr, lr, #8 @ Correct lr
728 tst lr, #3
729 bne Ldata_not_user
730 save_user_regs
731 teqp pc, #MODE_SVC26
732 mask_pc r0, lr
733 bl Ldata_do
734 b ret_from_exception
735
736Ldata_not_user:
737 save_svc_regs
738 and r2, lr, #3
739 teq r2, #3
740 bne Ldata_illegal_mode
741 tst lr, #PSR_I_BIT
742 teqeqp pc, #MODE_SVC26
743 mask_pc r0, lr
744 bl Ldata_do
745 restore_svc_regs
746
747Ldata_illegal_mode:
748 mov r0, sp
749 mov r1, #BAD_DATA
750 b bad_mode
751
752Ldata_do: mov r3, sp
753 ldr r4, [r0] @ Get instruction
754 mov r2, #0
755 tst r4, #1 << 20 @ Check to see if it is a write instruction
756 orreq r2, r2, #FAULT_CODE_WRITE @ Indicate write instruction
757 mov r1, r4, lsr #22 @ Now branch to the relevent processing routine
758 and r1, r1, #15 << 2
759 add pc, pc, r1
760 movs pc, lr
761 b Ldata_unknown
762 b Ldata_unknown
763 b Ldata_unknown
764 b Ldata_unknown
765 b Ldata_ldrstr_post @ ldr rd, [rn], #m
766 b Ldata_ldrstr_numindex @ ldr rd, [rn, #m] @ RegVal
767 b Ldata_ldrstr_post @ ldr rd, [rn], rm
768 b Ldata_ldrstr_regindex @ ldr rd, [rn, rm]
769 b Ldata_ldmstm @ ldm*a rn, <rlist>
770 b Ldata_ldmstm @ ldm*b rn, <rlist>
771 b Ldata_unknown
772 b Ldata_unknown
773 b Ldata_ldrstr_post @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
774 b Ldata_ldcstc_pre @ ldc rd, [rn, #m]
775 b Ldata_unknown
776Ldata_unknown: @ Part of jumptable
777 mov r0, r1
778 mov r1, r4
779 mov r2, r3
780 b baddataabort
781
782Ldata_ldrstr_post:
783 mov r0, r4, lsr #14 @ Get Rn
784 and r0, r0, #15 << 2 @ Mask out reg.
785 teq r0, #15 << 2
786 ldr r0, [r3, r0] @ Get register
787 biceq r0, r0, #PCMASK
788 mov r1, r0
789#ifdef FAULT_CODE_LDRSTRPOST
790 orr r2, r2, #FAULT_CODE_LDRSTRPOST
791#endif
792 b do_DataAbort
793
794Ldata_ldrstr_numindex:
795 mov r0, r4, lsr #14 @ Get Rn
796 and r0, r0, #15 << 2 @ Mask out reg.
797 teq r0, #15 << 2
798 ldr r0, [r3, r0] @ Get register
799 mov r1, r4, lsl #20
800 biceq r0, r0, #PCMASK
801 tst r4, #1 << 23
802 addne r0, r0, r1, lsr #20
803 subeq r0, r0, r1, lsr #20
804 mov r1, r0
805#ifdef FAULT_CODE_LDRSTRPRE
806 orr r2, r2, #FAULT_CODE_LDRSTRPRE
807#endif
808 b do_DataAbort
809
810Ldata_ldrstr_regindex:
811 mov r0, r4, lsr #14 @ Get Rn
812 and r0, r0, #15 << 2 @ Mask out reg.
813 teq r0, #15 << 2
814 ldr r0, [r3, r0] @ Get register
815 and r7, r4, #15
816 biceq r0, r0, #PCMASK
817 teq r7, #15 @ Check for PC
818 ldr r7, [r3, r7, lsl #2] @ Get Rm
819 and r8, r4, #0x60 @ Get shift types
820 biceq r7, r7, #PCMASK
821 mov r9, r4, lsr #7 @ Get shift amount
822 and r9, r9, #31
823 teq r8, #0
824 moveq r7, r7, lsl r9
825 teq r8, #0x20 @ LSR shift
826 moveq r7, r7, lsr r9
827 teq r8, #0x40 @ ASR shift
828 moveq r7, r7, asr r9
829 teq r8, #0x60 @ ROR shift
830 moveq r7, r7, ror r9
831 tst r4, #1 << 23
832 addne r0, r0, r7
833 subeq r0, r0, r7 @ Apply correction
834 mov r1, r0
835#ifdef FAULT_CODE_LDRSTRREG
836 orr r2, r2, #FAULT_CODE_LDRSTRREG
837#endif
838 b do_DataAbort
839
840Ldata_ldmstm:
841 mov r7, #0x11
842 orr r7, r7, r7, lsl #8
843 and r0, r4, r7
844 and r1, r4, r7, lsl #1
845 add r0, r0, r1, lsr #1
846 and r1, r4, r7, lsl #2
847 add r0, r0, r1, lsr #2
848 and r1, r4, r7, lsl #3
849 add r0, r0, r1, lsr #3
850 add r0, r0, r0, lsr #8
851 add r0, r0, r0, lsr #4
852 and r7, r0, #15 @ r7 = no. of registers to transfer.
853 mov r5, r4, lsr #14 @ Get Rn
854 and r5, r5, #15 << 2
855 ldr r0, [r3, r5] @ Get reg
856 eor r6, r4, r4, lsl #2
857 tst r6, #1 << 23 @ Check inc/dec ^ writeback
858 rsbeq r7, r7, #0
859 add r7, r0, r7, lsl #2 @ Do correction (signed)
860 subne r1, r7, #1
861 subeq r1, r0, #1
862 moveq r0, r7
863 tst r4, #1 << 21 @ Check writeback
864 strne r7, [r3, r5]
865 eor r6, r4, r4, lsl #1
866 tst r6, #1 << 24 @ Check Pre/Post ^ inc/dec
867 addeq r0, r0, #4
868 addeq r1, r1, #4
869 teq r5, #15*4 @ CHECK FOR PC
870 biceq r1, r1, #PCMASK
871 biceq r0, r0, #PCMASK
872#ifdef FAULT_CODE_LDMSTM
873 orr r2, r2, #FAULT_CODE_LDMSTM
874#endif
875 b do_DataAbort
876
877Ldata_ldcstc_pre:
878 mov r0, r4, lsr #14 @ Get Rn
879 and r0, r0, #15 << 2 @ Mask out reg.
880 teq r0, #15 << 2
881 ldr r0, [r3, r0] @ Get register
882 mov r1, r4, lsl #24 @ Get offset
883 biceq r0, r0, #PCMASK
884 tst r4, #1 << 23
885 addne r0, r0, r1, lsr #24
886 subeq r0, r0, r1, lsr #24
887 mov r1, r0
888#ifdef FAULT_CODE_LDCSTC
889 orr r2, r2, #FAULT_CODE_LDCSTC
890#endif
891 b do_DataAbort
892
893
894/*
895 * This is the return code to user mode for abort handlers
896 */
897ENTRY(ret_from_exception)
898 get_thread_info tsk
899 mov why, #0
900 b ret_to_user
901
902 .data
903ENTRY(fp_enter)
904 .word fpe_not_present
905 .text
906/*
907 * Register switch for older 26-bit only ARMs
908 */
909ENTRY(__switch_to)
910 add r0, r0, #TI_CPU_SAVE
911 stmia r0, {r4 - sl, fp, sp, lr}
912 add r1, r1, #TI_CPU_SAVE
913 ldmia r1, {r4 - sl, fp, sp, pc}^
914
915/*
916 *=============================================================================
917 * Low-level interface code
918 *-----------------------------------------------------------------------------
919 * Trap initialisation
920 *-----------------------------------------------------------------------------
921 *
922 * Note - FIQ code has changed. The default is a couple of words in 0x1c, 0x20
923 * that call _unexp_fiq. Nowever, we now copy the FIQ routine to 0x1c (removes
924 * some excess cycles).
925 *
926 * What we need to put into 0-0x1c are branches to branch to the kernel.
927 */
928
929 .section ".init.text",#alloc,#execinstr
930
931.Ljump_addresses:
932 swi SYS_ERROR0
933 .word vector_undefinstr - 12
934 .word vector_swi - 16
935 .word vector_prefetch - 20
936 .word vector_data - 24
937 .word vector_addrexcptn - 28
938 .word vector_IRQ - 32
939 .word _unexp_fiq - 36
940 b . + 8
941/*
942 * initialise the trap system
943 */
944ENTRY(__trap_init)
945 stmfd sp!, {r4 - r7, lr}
946 adr r1, .Ljump_addresses
947 ldmia r1, {r1 - r7, ip, lr}
948 orr r2, lr, r2, lsr #2
949 orr r3, lr, r3, lsr #2
950 orr r4, lr, r4, lsr #2
951 orr r5, lr, r5, lsr #2
952 orr r6, lr, r6, lsr #2
953 orr r7, lr, r7, lsr #2
954 orr ip, lr, ip, lsr #2
955 mov r0, #0
956 stmia r0, {r1 - r7, ip}
957 ldmfd sp!, {r4 - r7, pc}^
958
959 .bss
960__temp_irq: .space 4 @ saved lr_irq
961__temp_fiq: .space 128
diff --git a/arch/arm26/kernel/fiq.c b/arch/arm26/kernel/fiq.c
new file mode 100644
index 000000000000..08a97c9498ff
--- /dev/null
+++ b/arch/arm26/kernel/fiq.c
@@ -0,0 +1,202 @@
1/*
2 * linux/arch/arm26/kernel/fiq.c
3 *
4 * Copyright (C) 1998 Russell King
5 * Copyright (C) 1998, 1999 Phil Blundell
6 * Copyright (C) 2003 Ian Molton
7 *
8 * FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
9 *
10 * FIQ support re-written by Russell King to be more generic
11 *
12 * We now properly support a method by which the FIQ handlers can
13 * be stacked onto the vector. We still do not support sharing
14 * the FIQ vector itself.
15 *
16 * Operation is as follows:
17 * 1. Owner A claims FIQ:
18 * - default_fiq relinquishes control.
19 * 2. Owner A:
20 * - inserts code.
21 * - sets any registers,
22 * - enables FIQ.
23 * 3. Owner B claims FIQ:
24 * - if owner A has a relinquish function.
25 * - disable FIQs.
26 * - saves any registers.
27 * - returns zero.
28 * 4. Owner B:
29 * - inserts code.
30 * - sets any registers,
31 * - enables FIQ.
32 * 5. Owner B releases FIQ:
33 * - Owner A is asked to reacquire FIQ:
34 * - inserts code.
35 * - restores saved registers.
36 * - enables FIQ.
37 * 6. Goto 3
38 */
39#include <linux/config.h>
40#include <linux/module.h>
41#include <linux/mm.h>
42#include <linux/mman.h>
43#include <linux/init.h>
44#include <linux/seq_file.h>
45
46#include <asm/fiq.h>
47#include <asm/io.h>
48#include <asm/irq.h>
49#include <asm/pgalloc.h>
50#include <asm/system.h>
51#include <asm/uaccess.h>
52
53#define FIQ_VECTOR (vectors_base() + 0x1c)
54
55static unsigned long no_fiq_insn;
56
57#define unprotect_page_0()
58#define protect_page_0()
59
60/* Default reacquire function
61 * - we always relinquish FIQ control
62 * - we always reacquire FIQ control
63 */
64static int fiq_def_op(void *ref, int relinquish)
65{
66 if (!relinquish) {
67 unprotect_page_0();
68 *(unsigned long *)FIQ_VECTOR = no_fiq_insn;
69 protect_page_0();
70 }
71
72 return 0;
73}
74
75static struct fiq_handler default_owner = {
76 .name = "default",
77 .fiq_op = fiq_def_op,
78};
79
80static struct fiq_handler *current_fiq = &default_owner;
81
82int show_fiq_list(struct seq_file *p, void *v)
83{
84 if (current_fiq != &default_owner)
85 seq_printf(p, "FIQ: %s\n", current_fiq->name);
86
87 return 0;
88}
89
90void set_fiq_handler(void *start, unsigned int length)
91{
92 unprotect_page_0();
93
94 memcpy((void *)FIQ_VECTOR, start, length);
95
96 protect_page_0();
97}
98
99/*
100 * Taking an interrupt in FIQ mode is death, so both these functions
101 * disable irqs for the duration.
102 */
103void set_fiq_regs(struct pt_regs *regs)
104{
105 register unsigned long tmp, tmp2;
106 __asm__ volatile (
107 "mov %0, pc
108 bic %1, %0, #0x3
109 orr %1, %1, %3
110 teqp %1, #0 @ select FIQ mode
111 mov r0, r0
112 ldmia %2, {r8 - r14}
113 teqp %0, #0 @ return to SVC mode
114 mov r0, r0"
115 : "=&r" (tmp), "=&r" (tmp2)
116 : "r" (&regs->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | MODE_FIQ26)
117 /* These registers aren't modified by the above code in a way
118 visible to the compiler, but we mark them as clobbers anyway
119 so that GCC won't put any of the input or output operands in
120 them. */
121 : "r8", "r9", "r10", "r11", "r12", "r13", "r14");
122}
123
124void get_fiq_regs(struct pt_regs *regs)
125{
126 register unsigned long tmp, tmp2;
127 __asm__ volatile (
128 "mov %0, pc
129 bic %1, %0, #0x3
130 orr %1, %1, %3
131 teqp %1, #0 @ select FIQ mode
132 mov r0, r0
133 stmia %2, {r8 - r14}
134 teqp %0, #0 @ return to SVC mode
135 mov r0, r0"
136 : "=&r" (tmp), "=&r" (tmp2)
137 : "r" (&regs->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | MODE_FIQ26)
138 /* These registers aren't modified by the above code in a way
139 visible to the compiler, but we mark them as clobbers anyway
140 so that GCC won't put any of the input or output operands in
141 them. */
142 : "r8", "r9", "r10", "r11", "r12", "r13", "r14");
143}
144
145int claim_fiq(struct fiq_handler *f)
146{
147 int ret = 0;
148
149 if (current_fiq) {
150 ret = -EBUSY;
151
152 if (current_fiq->fiq_op != NULL)
153 ret = current_fiq->fiq_op(current_fiq->dev_id, 1);
154 }
155
156 if (!ret) {
157 f->next = current_fiq;
158 current_fiq = f;
159 }
160
161 return ret;
162}
163
164void release_fiq(struct fiq_handler *f)
165{
166 if (current_fiq != f) {
167 printk(KERN_ERR "%s FIQ trying to release %s FIQ\n",
168 f->name, current_fiq->name);
169#ifdef CONFIG_DEBUG_ERRORS
170 __backtrace();
171#endif
172 return;
173 }
174
175 do
176 current_fiq = current_fiq->next;
177 while (current_fiq->fiq_op(current_fiq->dev_id, 0));
178}
179
180void enable_fiq(int fiq)
181{
182 enable_irq(fiq + FIQ_START);
183}
184
185void disable_fiq(int fiq)
186{
187 disable_irq(fiq + FIQ_START);
188}
189
190EXPORT_SYMBOL(set_fiq_handler);
191EXPORT_SYMBOL(set_fiq_regs);
192EXPORT_SYMBOL(get_fiq_regs);
193EXPORT_SYMBOL(claim_fiq);
194EXPORT_SYMBOL(release_fiq);
195EXPORT_SYMBOL(enable_fiq);
196EXPORT_SYMBOL(disable_fiq);
197
198void __init init_FIQ(void)
199{
200 no_fiq_insn = *(unsigned long *)FIQ_VECTOR;
201 set_fs(get_fs());
202}
diff --git a/arch/arm26/kernel/head.S b/arch/arm26/kernel/head.S
new file mode 100644
index 000000000000..8bfc62539ba6
--- /dev/null
+++ b/arch/arm26/kernel/head.S
@@ -0,0 +1,113 @@
1/*
2 * linux/arch/arm26/kernel/head.S
3 *
4 * Copyright (C) 1994-2000 Russell King
5 * Copyright (C) 2003 Ian Molton
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * 26-bit kernel startup code
12 */
13#include <linux/config.h>
14#include <linux/linkage.h>
15#include <asm/mach-types.h>
16
17 .globl swapper_pg_dir
18 .equ swapper_pg_dir, 0x0207d000
19
20/*
21 * Entry point.
22 */
23 .section ".init.text",#alloc,#execinstr
24ENTRY(stext)
25
26__entry:
27 cmp pc, #0x02000000
28 ldrlt pc, LC0 @ if 0x01800000, call at 0x02080000
29 teq r0, #0 @ Check for old calling method
30 blne oldparams @ Move page if old
31
32 adr r0, LC0
33 ldmib r0, {r2-r5, sp} @ Setup stack (and fetch other values)
34
35 mov r0, #0 @ Clear BSS
361: cmp r2, r3
37 strcc r0, [r2], #4
38 bcc 1b
39
40 bl detect_proc_type
41 str r0, [r4]
42 bl detect_arch_type
43 str r0, [r5]
44
45#ifdef CONFIG_XIP_KERNEL
46 ldr r3, ETEXT @ data section copy
47 ldr r4, SDATA
48 ldr r5, EDATA
491:
50 ldr r6, [r3], #4
51 str r6, [r4], #4
52 cmp r4, r5
53 blt 1b
54#endif
55 mov fp, #0
56 b start_kernel
57
58LC0: .word _stext
59 .word __bss_start @ r2
60 .word _end @ r3
61 .word processor_id @ r4
62 .word __machine_arch_type @ r5
63 .word init_thread_union+8192 @ sp
64#ifdef CONFIG_XIP_KERNEL
65ETEXT: .word _endtext
66SDATA: .word _sdata
67EDATA: .word __bss_start
68#endif
69
70arm2_id: .long 0x41560200 @ ARM2 and 250 dont have a CPUID
71arm250_id: .long 0x41560250 @ So we create some after probing for them
72 .align
73
74oldparams: mov r4, #0x02000000
75 add r3, r4, #0x00080000
76 add r4, r4, #0x0007c000
771: ldmia r0!, {r5 - r12}
78 stmia r4!, {r5 - r12}
79 cmp r4, r3
80 blt 1b
81 mov pc, lr
82
83/*
84 * We need some way to automatically detect the difference between
85 * these two machines. Unfortunately, it is not possible to detect
86 * the presence of the SuperIO chip, because that will hang the old
87 * Archimedes machines solid.
88 */
89/* DAG: Outdated, these have been combined !!!!!!! */
90detect_arch_type:
91#if defined(CONFIG_ARCH_ARC)
92 mov r0, #MACH_TYPE_ARCHIMEDES
93#elif defined(CONFIG_ARCH_A5K)
94 mov r0, #MACH_TYPE_A5K
95#endif
96 mov pc, lr
97
98detect_proc_type:
99 mov ip, lr
100 mov r2, #0xea000000 @ Point undef instr to continuation
101 adr r0, continue - 12
102 orr r0, r2, r0, lsr #2
103 mov r1, #0
104 str r0, [r1, #4]
105 ldr r0, arm2_id
106 swp r2, r2, [r1] @ check for swp (ARM2 cant)
107 ldr r0, arm250_id
108 mrc 15, 0, r3, c0, c0 @ check for CP#15 (ARM250 cant)
109 mov r0, r3
110continue: mov r2, #0xeb000000 @ Make undef vector loop
111 sub r2, r2, #2
112 str r2, [r1, #4]
113 mov pc, ip
diff --git a/arch/arm26/kernel/init_task.c b/arch/arm26/kernel/init_task.c
new file mode 100644
index 000000000000..4191565b889b
--- /dev/null
+++ b/arch/arm26/kernel/init_task.c
@@ -0,0 +1,49 @@
1/*
2 * linux/arch/arm26/kernel/init_task.c
3 *
4 * Copyright (C) 2003 Ian Molton
5 *
6 */
7#include <linux/mm.h>
8#include <linux/module.h>
9#include <linux/fs.h>
10#include <linux/sched.h>
11#include <linux/init.h>
12#include <linux/init_task.h>
13#include <linux/mqueue.h>
14
15#include <asm/uaccess.h>
16#include <asm/pgtable.h>
17
18static struct fs_struct init_fs = INIT_FS;
19static struct files_struct init_files = INIT_FILES;
20static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
21static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
22struct mm_struct init_mm = INIT_MM(init_mm);
23
24EXPORT_SYMBOL(init_mm);
25
26/*
27 * Initial thread structure.
28 *
29 * We need to make sure that this is 8192-byte aligned due to the
30 * way process stacks are handled. This is done by making sure
31 * the linker maps this in the .text segment right after head.S,
32 * and making the linker scripts ensure the proper alignment.
33 *
34 * FIXME - should this be 32K alignment on arm26?
35 *
36 * The things we do for performance...
37 */
38union thread_union init_thread_union
39 __attribute__((__section__(".init.task"))) =
40 { INIT_THREAD_INFO(init_task) };
41
42/*
43 * Initial task structure.
44 *
45 * All other task structs will be allocated on slabs in fork.c
46 */
47struct task_struct init_task = INIT_TASK(init_task);
48
49EXPORT_SYMBOL(init_task);
diff --git a/arch/arm26/kernel/irq.c b/arch/arm26/kernel/irq.c
new file mode 100644
index 000000000000..f3cc1036e5bc
--- /dev/null
+++ b/arch/arm26/kernel/irq.c
@@ -0,0 +1,716 @@
1/*
2 * linux/arch/arm/kernel/irq.c
3 *
4 * Copyright (C) 1992 Linus Torvalds
5 * Modifications for ARM processor Copyright (C) 1995-2000 Russell King.
6 * 'Borrowed' for ARM26 and (C) 2003 Ian Molton.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This file contains the code used by various IRQ handling routines:
13 * asking for different IRQ's should be done through these routines
14 * instead of just grabbing them. Thus setups with different IRQ numbers
15 * shouldn't result in any weird surprises, and installing new handlers
16 * should be easier.
17 *
18 * IRQ's are in fact implemented a bit like signal handlers for the kernel.
19 * Naturally it's not a 1:1 relation, but there are similarities.
20 */
21#include <linux/config.h>
22#include <linux/module.h>
23#include <linux/ptrace.h>
24#include <linux/kernel_stat.h>
25#include <linux/signal.h>
26#include <linux/sched.h>
27#include <linux/ioport.h>
28#include <linux/interrupt.h>
29#include <linux/slab.h>
30#include <linux/random.h>
31#include <linux/smp.h>
32#include <linux/init.h>
33#include <linux/seq_file.h>
34#include <linux/errno.h>
35
36#include <asm/irq.h>
37#include <asm/system.h>
38#include <asm/irqchip.h>
39
40//FIXME - this ought to be in a header IMO
41void __init arc_init_irq(void);
42
43/*
44 * Maximum IRQ count. Currently, this is arbitary. However, it should
45 * not be set too low to prevent false triggering. Conversely, if it
46 * is set too high, then you could miss a stuck IRQ.
47 *
48 * FIXME Maybe we ought to set a timer and re-enable the IRQ at a later time?
49 */
50#define MAX_IRQ_CNT 100000
51
52static volatile unsigned long irq_err_count;
53static DEFINE_SPINLOCK(irq_controller_lock);
54
55struct irqdesc irq_desc[NR_IRQS];
56
57/*
58 * Dummy mask/unmask handler
59 */
60void dummy_mask_unmask_irq(unsigned int irq)
61{
62}
63
64void do_bad_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
65{
66 irq_err_count += 1;
67 printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq);
68}
69
70static struct irqchip bad_chip = {
71 .ack = dummy_mask_unmask_irq,
72 .mask = dummy_mask_unmask_irq,
73 .unmask = dummy_mask_unmask_irq,
74};
75
76static struct irqdesc bad_irq_desc = {
77 .chip = &bad_chip,
78 .handle = do_bad_IRQ,
79 .depth = 1,
80};
81
82/**
83 * disable_irq - disable an irq and wait for completion
84 * @irq: Interrupt to disable
85 *
86 * Disable the selected interrupt line. We do this lazily.
87 *
88 * This function may be called from IRQ context.
89 */
90void disable_irq(unsigned int irq)
91{
92 struct irqdesc *desc = irq_desc + irq;
93 unsigned long flags;
94 spin_lock_irqsave(&irq_controller_lock, flags);
95 if (!desc->depth++)
96 desc->enabled = 0;
97 spin_unlock_irqrestore(&irq_controller_lock, flags);
98}
99
100/**
101 * enable_irq - enable interrupt handling on an irq
102 * @irq: Interrupt to enable
103 *
104 * Re-enables the processing of interrupts on this IRQ line.
105 * Note that this may call the interrupt handler, so you may
106 * get unexpected results if you hold IRQs disabled.
107 *
108 * This function may be called from IRQ context.
109 */
110void enable_irq(unsigned int irq)
111{
112 struct irqdesc *desc = irq_desc + irq;
113 unsigned long flags;
114 int pending = 0;
115
116 spin_lock_irqsave(&irq_controller_lock, flags);
117 if (unlikely(!desc->depth)) {
118 printk("enable_irq(%u) unbalanced from %p\n", irq,
119 __builtin_return_address(0)); //FIXME bum addresses reported - why?
120 } else if (!--desc->depth) {
121 desc->probing = 0;
122 desc->enabled = 1;
123 desc->chip->unmask(irq);
124 pending = desc->pending;
125 desc->pending = 0;
126 /*
127 * If the interrupt was waiting to be processed,
128 * retrigger it.
129 */
130 if (pending)
131 desc->chip->rerun(irq);
132 }
133 spin_unlock_irqrestore(&irq_controller_lock, flags);
134}
135
136int show_interrupts(struct seq_file *p, void *v)
137{
138 int i = *(loff_t *) v;
139 struct irqaction * action;
140
141 if (i < NR_IRQS) {
142 action = irq_desc[i].action;
143 if (!action)
144 continue;
145 seq_printf(p, "%3d: %10u ", i, kstat_irqs(i));
146 seq_printf(p, " %s", action->name);
147 for (action = action->next; action; action = action->next) {
148 seq_printf(p, ", %s", action->name);
149 }
150 seq_putc(p, '\n');
151 } else if (i == NR_IRQS) {
152 show_fiq_list(p, v);
153 seq_printf(p, "Err: %10lu\n", irq_err_count);
154 }
155 return 0;
156}
157
158/*
159 * IRQ lock detection.
160 *
161 * Hopefully, this should get us out of a few locked situations.
162 * However, it may take a while for this to happen, since we need
163 * a large number if IRQs to appear in the same jiffie with the
164 * same instruction pointer (or within 2 instructions).
165 */
166static int check_irq_lock(struct irqdesc *desc, int irq, struct pt_regs *regs)
167{
168 unsigned long instr_ptr = instruction_pointer(regs);
169
170 if (desc->lck_jif == jiffies &&
171 desc->lck_pc >= instr_ptr && desc->lck_pc < instr_ptr + 8) {
172 desc->lck_cnt += 1;
173
174 if (desc->lck_cnt > MAX_IRQ_CNT) {
175 printk(KERN_ERR "IRQ LOCK: IRQ%d is locking the system, disabled\n", irq);
176 return 1;
177 }
178 } else {
179 desc->lck_cnt = 0;
180 desc->lck_pc = instruction_pointer(regs);
181 desc->lck_jif = jiffies;
182 }
183 return 0;
184}
185
186static void
187__do_irq(unsigned int irq, struct irqaction *action, struct pt_regs *regs)
188{
189 unsigned int status;
190 int ret;
191
192 spin_unlock(&irq_controller_lock);
193 if (!(action->flags & SA_INTERRUPT))
194 local_irq_enable();
195
196 status = 0;
197 do {
198 ret = action->handler(irq, action->dev_id, regs);
199 if (ret == IRQ_HANDLED)
200 status |= action->flags;
201 action = action->next;
202 } while (action);
203
204 if (status & SA_SAMPLE_RANDOM)
205 add_interrupt_randomness(irq);
206
207 spin_lock_irq(&irq_controller_lock);
208}
209
210/*
211 * This is for software-decoded IRQs. The caller is expected to
212 * handle the ack, clear, mask and unmask issues.
213 */
214void
215do_simple_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
216{
217 struct irqaction *action;
218 const int cpu = smp_processor_id();
219
220 desc->triggered = 1;
221
222 kstat_cpu(cpu).irqs[irq]++;
223
224 action = desc->action;
225 if (action)
226 __do_irq(irq, desc->action, regs);
227}
228
229/*
230 * Most edge-triggered IRQ implementations seem to take a broken
231 * approach to this. Hence the complexity.
232 */
233void
234do_edge_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
235{
236 const int cpu = smp_processor_id();
237
238 desc->triggered = 1;
239
240 /*
241 * If we're currently running this IRQ, or its disabled,
242 * we shouldn't process the IRQ. Instead, turn on the
243 * hardware masks.
244 */
245 if (unlikely(desc->running || !desc->enabled))
246 goto running;
247
248 /*
249 * Acknowledge and clear the IRQ, but don't mask it.
250 */
251 desc->chip->ack(irq);
252
253 /*
254 * Mark the IRQ currently in progress.
255 */
256 desc->running = 1;
257
258 kstat_cpu(cpu).irqs[irq]++;
259
260 do {
261 struct irqaction *action;
262
263 action = desc->action;
264 if (!action)
265 break;
266
267 if (desc->pending && desc->enabled) {
268 desc->pending = 0;
269 desc->chip->unmask(irq);
270 }
271
272 __do_irq(irq, action, regs);
273 } while (desc->pending);
274
275 desc->running = 0;
276
277 /*
278 * If we were disabled or freed, shut down the handler.
279 */
280 if (likely(desc->action && !check_irq_lock(desc, irq, regs)))
281 return;
282
283 running:
284 /*
285 * We got another IRQ while this one was masked or
286 * currently running. Delay it.
287 */
288 desc->pending = 1;
289 desc->chip->mask(irq);
290 desc->chip->ack(irq);
291}
292
293/*
294 * Level-based IRQ handler. Nice and simple.
295 */
296void
297do_level_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
298{
299 struct irqaction *action;
300 const int cpu = smp_processor_id();
301
302 desc->triggered = 1;
303
304 /*
305 * Acknowledge, clear _AND_ disable the interrupt.
306 */
307 desc->chip->ack(irq);
308
309 if (likely(desc->enabled)) {
310 kstat_cpu(cpu).irqs[irq]++;
311
312 /*
313 * Return with this interrupt masked if no action
314 */
315 action = desc->action;
316 if (action) {
317 __do_irq(irq, desc->action, regs);
318
319 if (likely(desc->enabled &&
320 !check_irq_lock(desc, irq, regs)))
321 desc->chip->unmask(irq);
322 }
323 }
324}
325
326/*
327 * do_IRQ handles all hardware IRQ's. Decoded IRQs should not
328 * come via this function. Instead, they should provide their
329 * own 'handler'
330 */
331asmlinkage void asm_do_IRQ(int irq, struct pt_regs *regs)
332{
333 struct irqdesc *desc = irq_desc + irq;
334
335 /*
336 * Some hardware gives randomly wrong interrupts. Rather
337 * than crashing, do something sensible.
338 */
339 if (irq >= NR_IRQS)
340 desc = &bad_irq_desc;
341
342 irq_enter();
343 spin_lock(&irq_controller_lock);
344 desc->handle(irq, desc, regs);
345 spin_unlock(&irq_controller_lock);
346 irq_exit();
347}
348
349void __set_irq_handler(unsigned int irq, irq_handler_t handle, int is_chained)
350{
351 struct irqdesc *desc;
352 unsigned long flags;
353
354 if (irq >= NR_IRQS) {
355 printk(KERN_ERR "Trying to install handler for IRQ%d\n", irq);
356 return;
357 }
358
359 if (handle == NULL)
360 handle = do_bad_IRQ;
361
362 desc = irq_desc + irq;
363
364 if (is_chained && desc->chip == &bad_chip)
365 printk(KERN_WARNING "Trying to install chained handler for IRQ%d\n", irq);
366
367 spin_lock_irqsave(&irq_controller_lock, flags);
368 if (handle == do_bad_IRQ) {
369 desc->chip->mask(irq);
370 desc->chip->ack(irq);
371 desc->depth = 1;
372 desc->enabled = 0;
373 }
374 desc->handle = handle;
375 if (handle != do_bad_IRQ && is_chained) {
376 desc->valid = 0;
377 desc->probe_ok = 0;
378 desc->depth = 0;
379 desc->chip->unmask(irq);
380 }
381 spin_unlock_irqrestore(&irq_controller_lock, flags);
382}
383
384void set_irq_chip(unsigned int irq, struct irqchip *chip)
385{
386 struct irqdesc *desc;
387 unsigned long flags;
388
389 if (irq >= NR_IRQS) {
390 printk(KERN_ERR "Trying to install chip for IRQ%d\n", irq);
391 return;
392 }
393
394 if (chip == NULL)
395 chip = &bad_chip;
396
397 desc = irq_desc + irq;
398 spin_lock_irqsave(&irq_controller_lock, flags);
399 desc->chip = chip;
400 spin_unlock_irqrestore(&irq_controller_lock, flags);
401}
402
403int set_irq_type(unsigned int irq, unsigned int type)
404{
405 struct irqdesc *desc;
406 unsigned long flags;
407 int ret = -ENXIO;
408
409 if (irq >= NR_IRQS) {
410 printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq);
411 return -ENODEV;
412 }
413
414 desc = irq_desc + irq;
415 if (desc->chip->type) {
416 spin_lock_irqsave(&irq_controller_lock, flags);
417 ret = desc->chip->type(irq, type);
418 spin_unlock_irqrestore(&irq_controller_lock, flags);
419 }
420
421 return ret;
422}
423
424void set_irq_flags(unsigned int irq, unsigned int iflags)
425{
426 struct irqdesc *desc;
427 unsigned long flags;
428
429 if (irq >= NR_IRQS) {
430 printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq);
431 return;
432 }
433
434 desc = irq_desc + irq;
435 spin_lock_irqsave(&irq_controller_lock, flags);
436 desc->valid = (iflags & IRQF_VALID) != 0;
437 desc->probe_ok = (iflags & IRQF_PROBE) != 0;
438 desc->noautoenable = (iflags & IRQF_NOAUTOEN) != 0;
439 spin_unlock_irqrestore(&irq_controller_lock, flags);
440}
441
442int setup_irq(unsigned int irq, struct irqaction *new)
443{
444 int shared = 0;
445 struct irqaction *old, **p;
446 unsigned long flags;
447 struct irqdesc *desc;
448
449 /*
450 * Some drivers like serial.c use request_irq() heavily,
451 * so we have to be careful not to interfere with a
452 * running system.
453 */
454 if (new->flags & SA_SAMPLE_RANDOM) {
455 /*
456 * This function might sleep, we want to call it first,
457 * outside of the atomic block.
458 * Yes, this might clear the entropy pool if the wrong
459 * driver is attempted to be loaded, without actually
460 * installing a new handler, but is this really a problem,
461 * only the sysadmin is able to do this.
462 */
463 rand_initialize_irq(irq);
464 }
465
466 /*
467 * The following block of code has to be executed atomically
468 */
469 desc = irq_desc + irq;
470 spin_lock_irqsave(&irq_controller_lock, flags);
471 p = &desc->action;
472 if ((old = *p) != NULL) {
473 /* Can't share interrupts unless both agree to */
474 if (!(old->flags & new->flags & SA_SHIRQ)) {
475 spin_unlock_irqrestore(&irq_controller_lock, flags);
476 return -EBUSY;
477 }
478
479 /* add new interrupt at end of irq queue */
480 do {
481 p = &old->next;
482 old = *p;
483 } while (old);
484 shared = 1;
485 }
486
487 *p = new;
488
489 if (!shared) {
490 desc->probing = 0;
491 desc->running = 0;
492 desc->pending = 0;
493 desc->depth = 1;
494 if (!desc->noautoenable) {
495 desc->depth = 0;
496 desc->enabled = 1;
497 desc->chip->unmask(irq);
498 }
499 }
500
501 spin_unlock_irqrestore(&irq_controller_lock, flags);
502 return 0;
503}
504
505/**
506 * request_irq - allocate an interrupt line
507 * @irq: Interrupt line to allocate
508 * @handler: Function to be called when the IRQ occurs
509 * @irqflags: Interrupt type flags
510 * @devname: An ascii name for the claiming device
511 * @dev_id: A cookie passed back to the handler function
512 *
513 * This call allocates interrupt resources and enables the
514 * interrupt line and IRQ handling. From the point this
515 * call is made your handler function may be invoked. Since
516 * your handler function must clear any interrupt the board
517 * raises, you must take care both to initialise your hardware
518 * and to set up the interrupt handler in the right order.
519 *
520 * Dev_id must be globally unique. Normally the address of the
521 * device data structure is used as the cookie. Since the handler
522 * receives this value it makes sense to use it.
523 *
524 * If your interrupt is shared you must pass a non NULL dev_id
525 * as this is required when freeing the interrupt.
526 *
527 * Flags:
528 *
529 * SA_SHIRQ Interrupt is shared
530 *
531 * SA_INTERRUPT Disable local interrupts while processing
532 *
533 * SA_SAMPLE_RANDOM The interrupt can be used for entropy
534 *
535 */
536
537//FIXME - handler used to return void - whats the significance of the change?
538int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *),
539 unsigned long irq_flags, const char * devname, void *dev_id)
540{
541 unsigned long retval;
542 struct irqaction *action;
543
544 if (irq >= NR_IRQS || !irq_desc[irq].valid || !handler ||
545 (irq_flags & SA_SHIRQ && !dev_id))
546 return -EINVAL;
547
548 action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
549 if (!action)
550 return -ENOMEM;
551
552 action->handler = handler;
553 action->flags = irq_flags;
554 cpus_clear(action->mask);
555 action->name = devname;
556 action->next = NULL;
557 action->dev_id = dev_id;
558
559 retval = setup_irq(irq, action);
560
561 if (retval)
562 kfree(action);
563 return retval;
564}
565
566EXPORT_SYMBOL(request_irq);
567
568/**
569 * free_irq - free an interrupt
570 * @irq: Interrupt line to free
571 * @dev_id: Device identity to free
572 *
573 * Remove an interrupt handler. The handler is removed and if the
574 * interrupt line is no longer in use by any driver it is disabled.
575 * On a shared IRQ the caller must ensure the interrupt is disabled
576 * on the card it drives before calling this function.
577 *
578 * This function may be called from interrupt context.
579 */
580void free_irq(unsigned int irq, void *dev_id)
581{
582 struct irqaction * action, **p;
583 unsigned long flags;
584
585 if (irq >= NR_IRQS || !irq_desc[irq].valid) {
586 printk(KERN_ERR "Trying to free IRQ%d\n",irq);
587#ifdef CONFIG_DEBUG_ERRORS
588 __backtrace();
589#endif
590 return;
591 }
592
593 spin_lock_irqsave(&irq_controller_lock, flags);
594 for (p = &irq_desc[irq].action; (action = *p) != NULL; p = &action->next) {
595 if (action->dev_id != dev_id)
596 continue;
597
598 /* Found it - now free it */
599 *p = action->next;
600 kfree(action);
601 goto out;
602 }
603 printk(KERN_ERR "Trying to free free IRQ%d\n",irq);
604#ifdef CONFIG_DEBUG_ERRORS
605 __backtrace();
606#endif
607out:
608 spin_unlock_irqrestore(&irq_controller_lock, flags);
609}
610
611EXPORT_SYMBOL(free_irq);
612
613/* Start the interrupt probing. Unlike other architectures,
614 * we don't return a mask of interrupts from probe_irq_on,
615 * but return the number of interrupts enabled for the probe.
616 * The interrupts which have been enabled for probing is
617 * instead recorded in the irq_desc structure.
618 */
619unsigned long probe_irq_on(void)
620{
621 unsigned int i, irqs = 0;
622 unsigned long delay;
623
624 /*
625 * first snaffle up any unassigned but
626 * probe-able interrupts
627 */
628 spin_lock_irq(&irq_controller_lock);
629 for (i = 0; i < NR_IRQS; i++) {
630 if (!irq_desc[i].probe_ok || irq_desc[i].action)
631 continue;
632
633 irq_desc[i].probing = 1;
634 irq_desc[i].triggered = 0;
635 if (irq_desc[i].chip->type)
636 irq_desc[i].chip->type(i, IRQT_PROBE);
637 irq_desc[i].chip->unmask(i);
638 irqs += 1;
639 }
640 spin_unlock_irq(&irq_controller_lock);
641
642 /*
643 * wait for spurious interrupts to mask themselves out again
644 */
645 for (delay = jiffies + HZ/10; time_before(jiffies, delay); )
646 /* min 100ms delay */;
647
648 /*
649 * now filter out any obviously spurious interrupts
650 */
651 spin_lock_irq(&irq_controller_lock);
652 for (i = 0; i < NR_IRQS; i++) {
653 if (irq_desc[i].probing && irq_desc[i].triggered) {
654 irq_desc[i].probing = 0;
655 irqs -= 1;
656 }
657 }
658 spin_unlock_irq(&irq_controller_lock);
659
660 return irqs;
661}
662
663EXPORT_SYMBOL(probe_irq_on);
664
665/*
666 * Possible return values:
667 * >= 0 - interrupt number
668 * -1 - no interrupt/many interrupts
669 */
670int probe_irq_off(unsigned long irqs)
671{
672 unsigned int i;
673 int irq_found = NO_IRQ;
674
675 /*
676 * look at the interrupts, and find exactly one
677 * that we were probing has been triggered
678 */
679 spin_lock_irq(&irq_controller_lock);
680 for (i = 0; i < NR_IRQS; i++) {
681 if (irq_desc[i].probing &&
682 irq_desc[i].triggered) {
683 if (irq_found != NO_IRQ) {
684 irq_found = NO_IRQ;
685 goto out;
686 }
687 irq_found = i;
688 }
689 }
690
691 if (irq_found == -1)
692 irq_found = NO_IRQ;
693out:
694 spin_unlock_irq(&irq_controller_lock);
695
696 return irq_found;
697}
698
699EXPORT_SYMBOL(probe_irq_off);
700
701void __init init_irq_proc(void)
702{
703}
704
705void __init init_IRQ(void)
706{
707 struct irqdesc *desc;
708 extern void init_dma(void);
709 int irq;
710
711 for (irq = 0, desc = irq_desc; irq < NR_IRQS; irq++, desc++)
712 *desc = bad_irq_desc;
713
714 arc_init_irq();
715 init_dma();
716}
diff --git a/arch/arm26/kernel/process.c b/arch/arm26/kernel/process.c
new file mode 100644
index 000000000000..46aea6ac194d
--- /dev/null
+++ b/arch/arm26/kernel/process.c
@@ -0,0 +1,401 @@
1/*
2 * linux/arch/arm26/kernel/process.c
3 *
4 * Copyright (C) 2003 Ian Molton - adapted for ARM26
5 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
6 * Origional Copyright (C) 1995 Linus Torvalds
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <stdarg.h>
13
14#include <linux/config.h>
15#include <linux/module.h>
16#include <linux/sched.h>
17#include <linux/kernel.h>
18#include <linux/mm.h>
19#include <linux/stddef.h>
20#include <linux/unistd.h>
21#include <linux/ptrace.h>
22#include <linux/slab.h>
23#include <linux/user.h>
24#include <linux/a.out.h>
25#include <linux/delay.h>
26#include <linux/reboot.h>
27#include <linux/interrupt.h>
28#include <linux/init.h>
29
30#include <asm/system.h>
31#include <asm/io.h>
32#include <asm/leds.h>
33#include <asm/processor.h>
34#include <asm/uaccess.h>
35
36extern const char *processor_modes[];
37extern void setup_mm_for_reboot(char mode);
38
39static volatile int hlt_counter;
40
41void disable_hlt(void)
42{
43 hlt_counter++;
44}
45
46EXPORT_SYMBOL(disable_hlt);
47
48void enable_hlt(void)
49{
50 hlt_counter--;
51}
52
53EXPORT_SYMBOL(enable_hlt);
54
55static int __init nohlt_setup(char *__unused)
56{
57 hlt_counter = 1;
58 return 1;
59}
60
61static int __init hlt_setup(char *__unused)
62{
63 hlt_counter = 0;
64 return 1;
65}
66
67__setup("nohlt", nohlt_setup);
68__setup("hlt", hlt_setup);
69
70/*
71 * This is our default idle handler. We need to disable
72 * interrupts here to ensure we don't miss a wakeup call.
73 */
74void cpu_idle(void)
75{
76 /* endless idle loop with no priority at all */
77 preempt_disable();
78 while (1) {
79 while (!need_resched()) {
80 local_irq_disable();
81 if (!need_resched() && !hlt_counter)
82 local_irq_enable();
83 }
84 }
85 schedule();
86}
87
88static char reboot_mode = 'h';
89
90int __init reboot_setup(char *str)
91{
92 reboot_mode = str[0];
93 return 1;
94}
95
96__setup("reboot=", reboot_setup);
97
98/* ARM26 cant do these but we still need to define them. */
99void machine_halt(void)
100{
101}
102void machine_power_off(void)
103{
104}
105
106EXPORT_SYMBOL(machine_halt);
107EXPORT_SYMBOL(machine_power_off);
108
109void machine_restart(char * __unused)
110{
111 /*
112 * Clean and disable cache, and turn off interrupts
113 */
114 cpu_proc_fin();
115
116 /*
117 * Tell the mm system that we are going to reboot -
118 * we may need it to insert some 1:1 mappings so that
119 * soft boot works.
120 */
121 setup_mm_for_reboot(reboot_mode);
122
123 /*
124 * copy branch instruction to reset location and call it
125 */
126
127 *(unsigned long *)0 = *(unsigned long *)0x03800000;
128 ((void(*)(void))0)();
129
130 /*
131 * Whoops - the architecture was unable to reboot.
132 * Tell the user! Should never happen...
133 */
134 mdelay(1000);
135 printk("Reboot failed -- System halted\n");
136 while (1);
137}
138
139EXPORT_SYMBOL(machine_restart);
140
141void show_regs(struct pt_regs * regs)
142{
143 unsigned long flags;
144
145 flags = condition_codes(regs);
146
147 printk("pc : [<%08lx>] lr : [<%08lx>] %s\n"
148 "sp : %08lx ip : %08lx fp : %08lx\n",
149 instruction_pointer(regs),
150 regs->ARM_lr, print_tainted(), regs->ARM_sp,
151 regs->ARM_ip, regs->ARM_fp);
152 printk("r10: %08lx r9 : %08lx r8 : %08lx\n",
153 regs->ARM_r10, regs->ARM_r9,
154 regs->ARM_r8);
155 printk("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
156 regs->ARM_r7, regs->ARM_r6,
157 regs->ARM_r5, regs->ARM_r4);
158 printk("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
159 regs->ARM_r3, regs->ARM_r2,
160 regs->ARM_r1, regs->ARM_r0);
161 printk("Flags: %c%c%c%c",
162 flags & PSR_N_BIT ? 'N' : 'n',
163 flags & PSR_Z_BIT ? 'Z' : 'z',
164 flags & PSR_C_BIT ? 'C' : 'c',
165 flags & PSR_V_BIT ? 'V' : 'v');
166 printk(" IRQs o%s FIQs o%s Mode %s Segment %s\n",
167 interrupts_enabled(regs) ? "n" : "ff",
168 fast_interrupts_enabled(regs) ? "n" : "ff",
169 processor_modes[processor_mode(regs)],
170 get_fs() == get_ds() ? "kernel" : "user");
171}
172
173void show_fpregs(struct user_fp *regs)
174{
175 int i;
176
177 for (i = 0; i < 8; i++) {
178 unsigned long *p;
179 char type;
180
181 p = (unsigned long *)(regs->fpregs + i);
182
183 switch (regs->ftype[i]) {
184 case 1: type = 'f'; break;
185 case 2: type = 'd'; break;
186 case 3: type = 'e'; break;
187 default: type = '?'; break;
188 }
189 if (regs->init_flag)
190 type = '?';
191
192 printk(" f%d(%c): %08lx %08lx %08lx%c",
193 i, type, p[0], p[1], p[2], i & 1 ? '\n' : ' ');
194 }
195
196
197 printk("FPSR: %08lx FPCR: %08lx\n",
198 (unsigned long)regs->fpsr,
199 (unsigned long)regs->fpcr);
200}
201
202/*
203 * Task structure and kernel stack allocation.
204 */
205static unsigned long *thread_info_head;
206static unsigned int nr_thread_info;
207
208extern unsigned long get_page_8k(int priority);
209extern void free_page_8k(unsigned long page);
210
211// FIXME - is this valid?
212#define EXTRA_TASK_STRUCT 0
213#define ll_alloc_task_struct() ((struct thread_info *)get_page_8k(GFP_KERNEL))
214#define ll_free_task_struct(p) free_page_8k((unsigned long)(p))
215
216//FIXME - do we use *task param below looks like we dont, which is ok?
217//FIXME - if EXTRA_TASK_STRUCT is zero we can optimise the below away permanently. *IF* its supposed to be zero.
218struct thread_info *alloc_thread_info(struct task_struct *task)
219{
220 struct thread_info *thread = NULL;
221
222 if (EXTRA_TASK_STRUCT) {
223 unsigned long *p = thread_info_head;
224
225 if (p) {
226 thread_info_head = (unsigned long *)p[0];
227 nr_thread_info -= 1;
228 }
229 thread = (struct thread_info *)p;
230 }
231
232 if (!thread)
233 thread = ll_alloc_task_struct();
234
235#ifdef CONFIG_MAGIC_SYSRQ
236 /*
237 * The stack must be cleared if you want SYSRQ-T to
238 * give sensible stack usage information
239 */
240 if (thread) {
241 char *p = (char *)thread;
242 memzero(p+KERNEL_STACK_SIZE, KERNEL_STACK_SIZE);
243 }
244#endif
245 return thread;
246}
247
248void free_thread_info(struct thread_info *thread)
249{
250 if (EXTRA_TASK_STRUCT && nr_thread_info < EXTRA_TASK_STRUCT) {
251 unsigned long *p = (unsigned long *)thread;
252 p[0] = (unsigned long)thread_info_head;
253 thread_info_head = p;
254 nr_thread_info += 1;
255 } else
256 ll_free_task_struct(thread);
257}
258
259/*
260 * Free current thread data structures etc..
261 */
262void exit_thread(void)
263{
264}
265
266void flush_thread(void)
267{
268 struct thread_info *thread = current_thread_info();
269 struct task_struct *tsk = current;
270
271 memset(&tsk->thread.debug, 0, sizeof(struct debug_info));
272 memset(&thread->fpstate, 0, sizeof(union fp_state));
273
274 clear_used_math();
275}
276
277void release_thread(struct task_struct *dead_task)
278{
279}
280
281asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
282
283int
284copy_thread(int nr, unsigned long clone_flags, unsigned long stack_start,
285 unsigned long unused, struct task_struct *p, struct pt_regs *regs)
286{
287 struct thread_info *thread = p->thread_info;
288 struct pt_regs *childregs;
289
290 childregs = __get_user_regs(thread);
291 *childregs = *regs;
292 childregs->ARM_r0 = 0;
293 childregs->ARM_sp = stack_start;
294
295 memset(&thread->cpu_context, 0, sizeof(struct cpu_context_save));
296 thread->cpu_context.sp = (unsigned long)childregs;
297 thread->cpu_context.pc = (unsigned long)ret_from_fork | MODE_SVC26 | PSR_I_BIT;
298
299 return 0;
300}
301
302/*
303 * fill in the fpe structure for a core dump...
304 */
305int dump_fpu (struct pt_regs *regs, struct user_fp *fp)
306{
307 struct thread_info *thread = current_thread_info();
308 int used_math = !!used_math();
309
310 if (used_math)
311 memcpy(fp, &thread->fpstate.soft, sizeof (*fp));
312
313 return used_math;
314}
315
316/*
317 * fill in the user structure for a core dump..
318 */
319void dump_thread(struct pt_regs * regs, struct user * dump)
320{
321 struct task_struct *tsk = current;
322
323 dump->magic = CMAGIC;
324 dump->start_code = tsk->mm->start_code;
325 dump->start_stack = regs->ARM_sp & ~(PAGE_SIZE - 1);
326
327 dump->u_tsize = (tsk->mm->end_code - tsk->mm->start_code) >> PAGE_SHIFT;
328 dump->u_dsize = (tsk->mm->brk - tsk->mm->start_data + PAGE_SIZE - 1) >> PAGE_SHIFT;
329 dump->u_ssize = 0;
330
331 dump->u_debugreg[0] = tsk->thread.debug.bp[0].address;
332 dump->u_debugreg[1] = tsk->thread.debug.bp[1].address;
333 dump->u_debugreg[2] = tsk->thread.debug.bp[0].insn;
334 dump->u_debugreg[3] = tsk->thread.debug.bp[1].insn;
335 dump->u_debugreg[4] = tsk->thread.debug.nsaved;
336
337 if (dump->start_stack < 0x04000000)
338 dump->u_ssize = (0x04000000 - dump->start_stack) >> PAGE_SHIFT;
339
340 dump->regs = *regs;
341 dump->u_fpvalid = dump_fpu (regs, &dump->u_fp);
342}
343
344/*
345 * Shuffle the argument into the correct register before calling the
346 * thread function. r1 is the thread argument, r2 is the pointer to
347 * the thread function, and r3 points to the exit function.
348 * FIXME - make sure this is right - the older code used to zero fp
349 * and cause the parent to call sys_exit (do_exit in this version)
350 */
351extern void kernel_thread_helper(void);
352
353asm( ".section .text\n"
354" .align\n"
355" .type kernel_thread_helper, #function\n"
356"kernel_thread_helper:\n"
357" mov r0, r1\n"
358" mov lr, r3\n"
359" mov pc, r2\n"
360" .size kernel_thread_helper, . - kernel_thread_helper\n"
361" .previous");
362
363/*
364 * Create a kernel thread.
365 */
366pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
367{
368 struct pt_regs regs;
369
370 memset(&regs, 0, sizeof(regs));
371
372 regs.ARM_r1 = (unsigned long)arg;
373 regs.ARM_r2 = (unsigned long)fn;
374 regs.ARM_r3 = (unsigned long)do_exit;
375 regs.ARM_pc = (unsigned long)kernel_thread_helper | MODE_SVC26;
376
377 return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
378}
379EXPORT_SYMBOL(kernel_thread);
380
381
382unsigned long get_wchan(struct task_struct *p)
383{
384 unsigned long fp, lr;
385 unsigned long stack_page;
386 int count = 0;
387 if (!p || p == current || p->state == TASK_RUNNING)
388 return 0;
389
390 stack_page = 4096 + (unsigned long)p;
391 fp = thread_saved_fp(p);
392 do {
393 if (fp < stack_page || fp > 4092+stack_page)
394 return 0;
395 lr = pc_pointer (((unsigned long *)fp)[-1]);
396 if (!in_sched_functions(lr))
397 return lr;
398 fp = *(unsigned long *) (fp - 12);
399 } while (count ++ < 16);
400 return 0;
401}
diff --git a/arch/arm26/kernel/ptrace.c b/arch/arm26/kernel/ptrace.c
new file mode 100644
index 000000000000..2a137146a77c
--- /dev/null
+++ b/arch/arm26/kernel/ptrace.c
@@ -0,0 +1,744 @@
1/*
2 * linux/arch/arm26/kernel/ptrace.c
3 *
4 * By Ross Biro 1/23/92
5 * edited by Linus Torvalds
6 * ARM modifications Copyright (C) 2000 Russell King
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/config.h>
13#include <linux/kernel.h>
14#include <linux/sched.h>
15#include <linux/mm.h>
16#include <linux/smp.h>
17#include <linux/smp_lock.h>
18#include <linux/ptrace.h>
19#include <linux/user.h>
20#include <linux/security.h>
21
22#include <asm/uaccess.h>
23#include <asm/pgtable.h>
24#include <asm/system.h>
25//#include <asm/processor.h>
26
27#include "ptrace.h"
28
29#define REG_PC 15
30#define REG_PSR 15
31/*
32 * does not yet catch signals sent when the child dies.
33 * in exit.c or in signal.c.
34 */
35
36/*
37 * Breakpoint SWI instruction: SWI &9F0001
38 */
39#define BREAKINST_ARM 0xef9f0001
40
41/*
42 * Get the address of the live pt_regs for the specified task.
43 * These are saved onto the top kernel stack when the process
44 * is not running.
45 *
46 * Note: if a user thread is execve'd from kernel space, the
47 * kernel stack will not be empty on entry to the kernel, so
48 * ptracing these tasks will fail.
49 */
50static inline struct pt_regs *
51get_user_regs(struct task_struct *task)
52{
53 return __get_user_regs(task->thread_info);
54}
55
56/*
57 * this routine will get a word off of the processes privileged stack.
58 * the offset is how far from the base addr as stored in the THREAD.
59 * this routine assumes that all the privileged stacks are in our
60 * data space.
61 */
62static inline long get_user_reg(struct task_struct *task, int offset)
63{
64 return get_user_regs(task)->uregs[offset];
65}
66
67/*
68 * this routine will put a word on the processes privileged stack.
69 * the offset is how far from the base addr as stored in the THREAD.
70 * this routine assumes that all the privileged stacks are in our
71 * data space.
72 */
73static inline int
74put_user_reg(struct task_struct *task, int offset, long data)
75{
76 struct pt_regs newregs, *regs = get_user_regs(task);
77 int ret = -EINVAL;
78
79 newregs = *regs;
80 newregs.uregs[offset] = data;
81
82 if (valid_user_regs(&newregs)) {
83 regs->uregs[offset] = data;
84 ret = 0;
85 }
86
87 return ret;
88}
89
90static inline int
91read_u32(struct task_struct *task, unsigned long addr, u32 *res)
92{
93 int ret;
94
95 ret = access_process_vm(task, addr, res, sizeof(*res), 0);
96
97 return ret == sizeof(*res) ? 0 : -EIO;
98}
99
100static inline int
101read_instr(struct task_struct *task, unsigned long addr, u32 *res)
102{
103 int ret;
104 u32 val;
105 ret = access_process_vm(task, addr & ~3, &val, sizeof(val), 0);
106 ret = ret == sizeof(val) ? 0 : -EIO;
107 *res = val;
108 return ret;
109}
110
111/*
112 * Get value of register `rn' (in the instruction)
113 */
114static unsigned long
115ptrace_getrn(struct task_struct *child, unsigned long insn)
116{
117 unsigned int reg = (insn >> 16) & 15;
118 unsigned long val;
119
120 val = get_user_reg(child, reg);
121 if (reg == 15)
122 val = pc_pointer(val + 8); //FIXME - correct for arm26?
123
124 return val;
125}
126
127/*
128 * Get value of operand 2 (in an ALU instruction)
129 */
130static unsigned long
131ptrace_getaluop2(struct task_struct *child, unsigned long insn)
132{
133 unsigned long val;
134 int shift;
135 int type;
136
137 if (insn & 1 << 25) {
138 val = insn & 255;
139 shift = (insn >> 8) & 15;
140 type = 3;
141 } else {
142 val = get_user_reg (child, insn & 15);
143
144 if (insn & (1 << 4))
145 shift = (int)get_user_reg (child, (insn >> 8) & 15);
146 else
147 shift = (insn >> 7) & 31;
148
149 type = (insn >> 5) & 3;
150 }
151
152 switch (type) {
153 case 0: val <<= shift; break;
154 case 1: val >>= shift; break;
155 case 2:
156 val = (((signed long)val) >> shift);
157 break;
158 case 3:
159 val = (val >> shift) | (val << (32 - shift));
160 break;
161 }
162 return val;
163}
164
165/*
166 * Get value of operand 2 (in a LDR instruction)
167 */
168static unsigned long
169ptrace_getldrop2(struct task_struct *child, unsigned long insn)
170{
171 unsigned long val;
172 int shift;
173 int type;
174
175 val = get_user_reg(child, insn & 15);
176 shift = (insn >> 7) & 31;
177 type = (insn >> 5) & 3;
178
179 switch (type) {
180 case 0: val <<= shift; break;
181 case 1: val >>= shift; break;
182 case 2:
183 val = (((signed long)val) >> shift);
184 break;
185 case 3:
186 val = (val >> shift) | (val << (32 - shift));
187 break;
188 }
189 return val;
190}
191
192#define OP_MASK 0x01e00000
193#define OP_AND 0x00000000
194#define OP_EOR 0x00200000
195#define OP_SUB 0x00400000
196#define OP_RSB 0x00600000
197#define OP_ADD 0x00800000
198#define OP_ADC 0x00a00000
199#define OP_SBC 0x00c00000
200#define OP_RSC 0x00e00000
201#define OP_ORR 0x01800000
202#define OP_MOV 0x01a00000
203#define OP_BIC 0x01c00000
204#define OP_MVN 0x01e00000
205
206static unsigned long
207get_branch_address(struct task_struct *child, unsigned long pc, unsigned long insn)
208{
209 u32 alt = 0;
210
211 switch (insn & 0x0e000000) {
212 case 0x00000000:
213 case 0x02000000: {
214 /*
215 * data processing
216 */
217 long aluop1, aluop2, ccbit;
218
219 if ((insn & 0xf000) != 0xf000)
220 break;
221
222 aluop1 = ptrace_getrn(child, insn);
223 aluop2 = ptrace_getaluop2(child, insn);
224 ccbit = get_user_reg(child, REG_PSR) & PSR_C_BIT ? 1 : 0;
225
226 switch (insn & OP_MASK) {
227 case OP_AND: alt = aluop1 & aluop2; break;
228 case OP_EOR: alt = aluop1 ^ aluop2; break;
229 case OP_SUB: alt = aluop1 - aluop2; break;
230 case OP_RSB: alt = aluop2 - aluop1; break;
231 case OP_ADD: alt = aluop1 + aluop2; break;
232 case OP_ADC: alt = aluop1 + aluop2 + ccbit; break;
233 case OP_SBC: alt = aluop1 - aluop2 + ccbit; break;
234 case OP_RSC: alt = aluop2 - aluop1 + ccbit; break;
235 case OP_ORR: alt = aluop1 | aluop2; break;
236 case OP_MOV: alt = aluop2; break;
237 case OP_BIC: alt = aluop1 & ~aluop2; break;
238 case OP_MVN: alt = ~aluop2; break;
239 }
240 break;
241 }
242
243 case 0x04000000:
244 case 0x06000000:
245 /*
246 * ldr
247 */
248 if ((insn & 0x0010f000) == 0x0010f000) {
249 unsigned long base;
250
251 base = ptrace_getrn(child, insn);
252 if (insn & 1 << 24) {
253 long aluop2;
254
255 if (insn & 0x02000000)
256 aluop2 = ptrace_getldrop2(child, insn);
257 else
258 aluop2 = insn & 0xfff;
259
260 if (insn & 1 << 23)
261 base += aluop2;
262 else
263 base -= aluop2;
264 }
265 if (read_u32(child, base, &alt) == 0)
266 alt = pc_pointer(alt);
267 }
268 break;
269
270 case 0x08000000:
271 /*
272 * ldm
273 */
274 if ((insn & 0x00108000) == 0x00108000) {
275 unsigned long base;
276 unsigned int nr_regs;
277
278 if (insn & (1 << 23)) {
279 nr_regs = hweight16(insn & 65535) << 2;
280
281 if (!(insn & (1 << 24)))
282 nr_regs -= 4;
283 } else {
284 if (insn & (1 << 24))
285 nr_regs = -4;
286 else
287 nr_regs = 0;
288 }
289
290 base = ptrace_getrn(child, insn);
291
292 if (read_u32(child, base + nr_regs, &alt) == 0)
293 alt = pc_pointer(alt);
294 break;
295 }
296 break;
297
298 case 0x0a000000: {
299 /*
300 * bl or b
301 */
302 signed long displ;
303 /* It's a branch/branch link: instead of trying to
304 * figure out whether the branch will be taken or not,
305 * we'll put a breakpoint at both locations. This is
306 * simpler, more reliable, and probably not a whole lot
307 * slower than the alternative approach of emulating the
308 * branch.
309 */
310 displ = (insn & 0x00ffffff) << 8;
311 displ = (displ >> 6) + 8;
312 if (displ != 0 && displ != 4)
313 alt = pc + displ;
314 }
315 break;
316 }
317
318 return alt;
319}
320
321static int
322swap_insn(struct task_struct *task, unsigned long addr,
323 void *old_insn, void *new_insn, int size)
324{
325 int ret;
326
327 ret = access_process_vm(task, addr, old_insn, size, 0);
328 if (ret == size)
329 ret = access_process_vm(task, addr, new_insn, size, 1);
330 return ret;
331}
332
333static void
334add_breakpoint(struct task_struct *task, struct debug_info *dbg, unsigned long addr)
335{
336 int nr = dbg->nsaved;
337
338 if (nr < 2) {
339 u32 new_insn = BREAKINST_ARM;
340 int res;
341
342 res = swap_insn(task, addr, &dbg->bp[nr].insn, &new_insn, 4);
343
344 if (res == 4) {
345 dbg->bp[nr].address = addr;
346 dbg->nsaved += 1;
347 }
348 } else
349 printk(KERN_ERR "ptrace: too many breakpoints\n");
350}
351
352/*
353 * Clear one breakpoint in the user program. We copy what the hardware
354 * does and use bit 0 of the address to indicate whether this is a Thumb
355 * breakpoint or an ARM breakpoint.
356 */
357static void clear_breakpoint(struct task_struct *task, struct debug_entry *bp)
358{
359 unsigned long addr = bp->address;
360 u32 old_insn;
361 int ret;
362
363 ret = swap_insn(task, addr & ~3, &old_insn,
364 &bp->insn, 4);
365
366 if (ret != 4 || old_insn != BREAKINST_ARM)
367 printk(KERN_ERR "%s:%d: corrupted ARM breakpoint at "
368 "0x%08lx (0x%08x)\n", task->comm, task->pid,
369 addr, old_insn);
370}
371
372void ptrace_set_bpt(struct task_struct *child)
373{
374 struct pt_regs *regs;
375 unsigned long pc;
376 u32 insn;
377 int res;
378
379 regs = get_user_regs(child);
380 pc = instruction_pointer(regs);
381
382 res = read_instr(child, pc, &insn);
383 if (!res) {
384 struct debug_info *dbg = &child->thread.debug;
385 unsigned long alt;
386
387 dbg->nsaved = 0;
388
389 alt = get_branch_address(child, pc, insn);
390 if (alt)
391 add_breakpoint(child, dbg, alt);
392
393 /*
394 * Note that we ignore the result of setting the above
395 * breakpoint since it may fail. When it does, this is
396 * not so much an error, but a forewarning that we may
397 * be receiving a prefetch abort shortly.
398 *
399 * If we don't set this breakpoint here, then we can
400 * lose control of the thread during single stepping.
401 */
402 if (!alt || predicate(insn) != PREDICATE_ALWAYS)
403 add_breakpoint(child, dbg, pc + 4);
404 }
405}
406
407/*
408 * Ensure no single-step breakpoint is pending. Returns non-zero
409 * value if child was being single-stepped.
410 */
411void ptrace_cancel_bpt(struct task_struct *child)
412{
413 int i, nsaved = child->thread.debug.nsaved;
414
415 child->thread.debug.nsaved = 0;
416
417 if (nsaved > 2) {
418 printk("ptrace_cancel_bpt: bogus nsaved: %d!\n", nsaved);
419 nsaved = 2;
420 }
421
422 for (i = 0; i < nsaved; i++)
423 clear_breakpoint(child, &child->thread.debug.bp[i]);
424}
425
426/*
427 * Called by kernel/ptrace.c when detaching..
428 *
429 * Make sure the single step bit is not set.
430 */
431void ptrace_disable(struct task_struct *child)
432{
433 child->ptrace &= ~PT_SINGLESTEP;
434 ptrace_cancel_bpt(child);
435}
436
437/*
438 * Handle hitting a breakpoint.
439 */
440void ptrace_break(struct task_struct *tsk, struct pt_regs *regs)
441{
442 siginfo_t info;
443
444 /*
445 * The PC is always left pointing at the next instruction. Fix this.
446 */
447 regs->ARM_pc -= 4;
448
449 if (tsk->thread.debug.nsaved == 0)
450 printk(KERN_ERR "ptrace: bogus breakpoint trap\n");
451
452 ptrace_cancel_bpt(tsk);
453
454 info.si_signo = SIGTRAP;
455 info.si_errno = 0;
456 info.si_code = TRAP_BRKPT;
457 info.si_addr = (void *)instruction_pointer(regs) - 4;
458
459 force_sig_info(SIGTRAP, &info, tsk);
460}
461
462/*
463 * Read the word at offset "off" into the "struct user". We
464 * actually access the pt_regs stored on the kernel stack.
465 */
466static int ptrace_read_user(struct task_struct *tsk, unsigned long off,
467 unsigned long *ret)
468{
469 unsigned long tmp;
470
471 if (off & 3 || off >= sizeof(struct user))
472 return -EIO;
473
474 tmp = 0;
475 if (off < sizeof(struct pt_regs))
476 tmp = get_user_reg(tsk, off >> 2);
477
478 return put_user(tmp, ret);
479}
480
481/*
482 * Write the word at offset "off" into "struct user". We
483 * actually access the pt_regs stored on the kernel stack.
484 */
485static int ptrace_write_user(struct task_struct *tsk, unsigned long off,
486 unsigned long val)
487{
488 if (off & 3 || off >= sizeof(struct user))
489 return -EIO;
490
491 if (off >= sizeof(struct pt_regs))
492 return 0;
493
494 return put_user_reg(tsk, off >> 2, val);
495}
496
497/*
498 * Get all user integer registers.
499 */
500static int ptrace_getregs(struct task_struct *tsk, void *uregs)
501{
502 struct pt_regs *regs = get_user_regs(tsk);
503
504 return copy_to_user(uregs, regs, sizeof(struct pt_regs)) ? -EFAULT : 0;
505}
506
507/*
508 * Set all user integer registers.
509 */
510static int ptrace_setregs(struct task_struct *tsk, void *uregs)
511{
512 struct pt_regs newregs;
513 int ret;
514
515 ret = -EFAULT;
516 if (copy_from_user(&newregs, uregs, sizeof(struct pt_regs)) == 0) {
517 struct pt_regs *regs = get_user_regs(tsk);
518
519 ret = -EINVAL;
520 if (valid_user_regs(&newregs)) {
521 *regs = newregs;
522 ret = 0;
523 }
524 }
525
526 return ret;
527}
528
529/*
530 * Get the child FPU state.
531 */
532static int ptrace_getfpregs(struct task_struct *tsk, void *ufp)
533{
534 return copy_to_user(ufp, &tsk->thread_info->fpstate,
535 sizeof(struct user_fp)) ? -EFAULT : 0;
536}
537
538/*
539 * Set the child FPU state.
540 */
541static int ptrace_setfpregs(struct task_struct *tsk, void *ufp)
542{
543 set_stopped_child_used_math(tsk);
544 return copy_from_user(&tsk->thread_info->fpstate, ufp,
545 sizeof(struct user_fp)) ? -EFAULT : 0;
546}
547
548static int do_ptrace(int request, struct task_struct *child, long addr, long data)
549{
550 unsigned long tmp;
551 int ret;
552
553 switch (request) {
554 /*
555 * read word at location "addr" in the child process.
556 */
557 case PTRACE_PEEKTEXT:
558 case PTRACE_PEEKDATA:
559 ret = access_process_vm(child, addr, &tmp,
560 sizeof(unsigned long), 0);
561 if (ret == sizeof(unsigned long))
562 ret = put_user(tmp, (unsigned long *) data);
563 else
564 ret = -EIO;
565 break;
566
567 case PTRACE_PEEKUSR:
568 ret = ptrace_read_user(child, addr, (unsigned long *)data);
569 break;
570
571 /*
572 * write the word at location addr.
573 */
574 case PTRACE_POKETEXT:
575 case PTRACE_POKEDATA:
576 ret = access_process_vm(child, addr, &data,
577 sizeof(unsigned long), 1);
578 if (ret == sizeof(unsigned long))
579 ret = 0;
580 else
581 ret = -EIO;
582 break;
583
584 case PTRACE_POKEUSR:
585 ret = ptrace_write_user(child, addr, data);
586 break;
587
588 /*
589 * continue/restart and stop at next (return from) syscall
590 */
591 case PTRACE_SYSCALL:
592 case PTRACE_CONT:
593 ret = -EIO;
594 if ((unsigned long) data > _NSIG)
595 break;
596 if (request == PTRACE_SYSCALL)
597 set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
598 else
599 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
600 child->exit_code = data;
601 /* make sure single-step breakpoint is gone. */
602 child->ptrace &= ~PT_SINGLESTEP;
603 ptrace_cancel_bpt(child);
604 wake_up_process(child);
605 ret = 0;
606 break;
607
608 /*
609 * make the child exit. Best I can do is send it a sigkill.
610 * perhaps it should be put in the status that it wants to
611 * exit.
612 */
613 case PTRACE_KILL:
614 /* make sure single-step breakpoint is gone. */
615 child->ptrace &= ~PT_SINGLESTEP;
616 ptrace_cancel_bpt(child);
617 if (child->exit_state != EXIT_ZOMBIE) {
618 child->exit_code = SIGKILL;
619 wake_up_process(child);
620 }
621 ret = 0;
622 break;
623
624 /*
625 * execute single instruction.
626 */
627 case PTRACE_SINGLESTEP:
628 ret = -EIO;
629 if ((unsigned long) data > _NSIG)
630 break;
631 child->ptrace |= PT_SINGLESTEP;
632 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
633 child->exit_code = data;
634 /* give it a chance to run. */
635 wake_up_process(child);
636 ret = 0;
637 break;
638
639 case PTRACE_DETACH:
640 ret = ptrace_detach(child, data);
641 break;
642
643 case PTRACE_GETREGS:
644 ret = ptrace_getregs(child, (void *)data);
645 break;
646
647 case PTRACE_SETREGS:
648 ret = ptrace_setregs(child, (void *)data);
649 break;
650
651 case PTRACE_GETFPREGS:
652 ret = ptrace_getfpregs(child, (void *)data);
653 break;
654
655 case PTRACE_SETFPREGS:
656 ret = ptrace_setfpregs(child, (void *)data);
657 break;
658
659 default:
660 ret = ptrace_request(child, request, addr, data);
661 break;
662 }
663
664 return ret;
665}
666
667asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
668{
669 struct task_struct *child;
670 int ret;
671
672 lock_kernel();
673 ret = -EPERM;
674 if (request == PTRACE_TRACEME) {
675 /* are we already being traced? */
676 if (current->ptrace & PT_PTRACED)
677 goto out;
678 ret = security_ptrace(current->parent, current);
679 if (ret)
680 goto out;
681 /* set the ptrace bit in the process flags. */
682 current->ptrace |= PT_PTRACED;
683 ret = 0;
684 goto out;
685 }
686 ret = -ESRCH;
687 read_lock(&tasklist_lock);
688 child = find_task_by_pid(pid);
689 if (child)
690 get_task_struct(child);
691 read_unlock(&tasklist_lock);
692 if (!child)
693 goto out;
694
695 ret = -EPERM;
696 if (pid == 1) /* you may not mess with init */
697 goto out_tsk;
698
699 if (request == PTRACE_ATTACH) {
700 ret = ptrace_attach(child);
701 goto out_tsk;
702 }
703 ret = ptrace_check_attach(child, request == PTRACE_KILL);
704 if (ret == 0)
705 ret = do_ptrace(request, child, addr, data);
706
707out_tsk:
708 put_task_struct(child);
709out:
710 unlock_kernel();
711 return ret;
712}
713
714asmlinkage void syscall_trace(int why, struct pt_regs *regs)
715{
716 unsigned long ip;
717
718 if (!test_thread_flag(TIF_SYSCALL_TRACE))
719 return;
720 if (!(current->ptrace & PT_PTRACED))
721 return;
722
723 /*
724 * Save IP. IP is used to denote syscall entry/exit:
725 * IP = 0 -> entry, = 1 -> exit
726 */
727 ip = regs->ARM_ip;
728 regs->ARM_ip = why;
729
730 /* the 0x80 provides a way for the tracing parent to distinguish
731 between a syscall stop and SIGTRAP delivery */
732 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
733 ? 0x80 : 0));
734 /*
735 * this isn't the same as continuing with a signal, but it will do
736 * for normal use. strace only continues with a signal if the
737 * stopping signal is not SIGTRAP. -brl
738 */
739 if (current->exit_code) {
740 send_sig(current->exit_code, current, 1);
741 current->exit_code = 0;
742 }
743 regs->ARM_ip = ip;
744}
diff --git a/arch/arm26/kernel/ptrace.h b/arch/arm26/kernel/ptrace.h
new file mode 100644
index 000000000000..846c9d8d36ed
--- /dev/null
+++ b/arch/arm26/kernel/ptrace.h
@@ -0,0 +1,13 @@
1/*
2 * linux/arch/arm26/kernel/ptrace.h
3 *
4 * Copyright (C) 2000-2003 Russell King
5 * Copyright (C) 2003 Ian Molton
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11extern void ptrace_cancel_bpt(struct task_struct *);
12extern void ptrace_set_bpt(struct task_struct *);
13extern void ptrace_break(struct task_struct *, struct pt_regs *);
diff --git a/arch/arm26/kernel/semaphore.c b/arch/arm26/kernel/semaphore.c
new file mode 100644
index 000000000000..3023a53431ff
--- /dev/null
+++ b/arch/arm26/kernel/semaphore.c
@@ -0,0 +1,223 @@
1/*
2 * ARM semaphore implementation, taken from
3 *
4 * i386 semaphore implementation.
5 *
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 2003 Ian Molton (ARM26 mods)
8 *
9 * Modified for ARM by Russell King
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15#include <linux/module.h>
16#include <linux/config.h>
17#include <linux/sched.h>
18#include <linux/errno.h>
19#include <linux/init.h>
20
21#include <asm/semaphore.h>
22
23/*
24 * Semaphores are implemented using a two-way counter:
25 * The "count" variable is decremented for each process
26 * that tries to acquire the semaphore, while the "sleeping"
27 * variable is a count of such acquires.
28 *
29 * Notably, the inline "up()" and "down()" functions can
30 * efficiently test if they need to do any extra work (up
31 * needs to do something only if count was negative before
32 * the increment operation.
33 *
34 * "sleeping" and the contention routine ordering is
35 * protected by the semaphore spinlock.
36 *
37 * Note that these functions are only called when there is
38 * contention on the lock, and as such all this is the
39 * "non-critical" part of the whole semaphore business. The
40 * critical part is the inline stuff in <asm/semaphore.h>
41 * where we want to avoid any extra jumps and calls.
42 */
43
44/*
45 * Logic:
46 * - only on a boundary condition do we need to care. When we go
47 * from a negative count to a non-negative, we wake people up.
48 * - when we go from a non-negative count to a negative do we
49 * (a) synchronize with the "sleeper" count and (b) make sure
50 * that we're on the wakeup list before we synchronize so that
51 * we cannot lose wakeup events.
52 */
53
54void __up(struct semaphore *sem)
55{
56 wake_up(&sem->wait);
57}
58
59static DEFINE_SPINLOCK(semaphore_lock);
60
61void __sched __down(struct semaphore * sem)
62{
63 struct task_struct *tsk = current;
64 DECLARE_WAITQUEUE(wait, tsk);
65 tsk->state = TASK_UNINTERRUPTIBLE;
66 add_wait_queue_exclusive(&sem->wait, &wait);
67
68 spin_lock_irq(&semaphore_lock);
69 sem->sleepers++;
70 for (;;) {
71 int sleepers = sem->sleepers;
72
73 /*
74 * Add "everybody else" into it. They aren't
75 * playing, because we own the spinlock.
76 */
77 if (!atomic_add_negative(sleepers - 1, &sem->count)) {
78 sem->sleepers = 0;
79 break;
80 }
81 sem->sleepers = 1; /* us - see -1 above */
82 spin_unlock_irq(&semaphore_lock);
83
84 schedule();
85 tsk->state = TASK_UNINTERRUPTIBLE;
86 spin_lock_irq(&semaphore_lock);
87 }
88 spin_unlock_irq(&semaphore_lock);
89 remove_wait_queue(&sem->wait, &wait);
90 tsk->state = TASK_RUNNING;
91 wake_up(&sem->wait);
92}
93
94int __sched __down_interruptible(struct semaphore * sem)
95{
96 int retval = 0;
97 struct task_struct *tsk = current;
98 DECLARE_WAITQUEUE(wait, tsk);
99 tsk->state = TASK_INTERRUPTIBLE;
100 add_wait_queue_exclusive(&sem->wait, &wait);
101
102 spin_lock_irq(&semaphore_lock);
103 sem->sleepers ++;
104 for (;;) {
105 int sleepers = sem->sleepers;
106
107 /*
108 * With signals pending, this turns into
109 * the trylock failure case - we won't be
110 * sleeping, and we* can't get the lock as
111 * it has contention. Just correct the count
112 * and exit.
113 */
114 if (signal_pending(current)) {
115 retval = -EINTR;
116 sem->sleepers = 0;
117 atomic_add(sleepers, &sem->count);
118 break;
119 }
120
121 /*
122 * Add "everybody else" into it. They aren't
123 * playing, because we own the spinlock. The
124 * "-1" is because we're still hoping to get
125 * the lock.
126 */
127 if (!atomic_add_negative(sleepers - 1, &sem->count)) {
128 sem->sleepers = 0;
129 break;
130 }
131 sem->sleepers = 1; /* us - see -1 above */
132 spin_unlock_irq(&semaphore_lock);
133
134 schedule();
135 tsk->state = TASK_INTERRUPTIBLE;
136 spin_lock_irq(&semaphore_lock);
137 }
138 spin_unlock_irq(&semaphore_lock);
139 tsk->state = TASK_RUNNING;
140 remove_wait_queue(&sem->wait, &wait);
141 wake_up(&sem->wait);
142 return retval;
143}
144
145/*
146 * Trylock failed - make sure we correct for
147 * having decremented the count.
148 *
149 * We could have done the trylock with a
150 * single "cmpxchg" without failure cases,
151 * but then it wouldn't work on a 386.
152 */
153int __down_trylock(struct semaphore * sem)
154{
155 int sleepers;
156 unsigned long flags;
157
158 spin_lock_irqsave(&semaphore_lock, flags);
159 sleepers = sem->sleepers + 1;
160 sem->sleepers = 0;
161
162 /*
163 * Add "everybody else" and us into it. They aren't
164 * playing, because we own the spinlock.
165 */
166 if (!atomic_add_negative(sleepers, &sem->count))
167 wake_up(&sem->wait);
168
169 spin_unlock_irqrestore(&semaphore_lock, flags);
170 return 1;
171}
172
173/*
174 * The semaphore operations have a special calling sequence that
175 * allow us to do a simpler in-line version of them. These routines
176 * need to convert that sequence back into the C sequence when
177 * there is contention on the semaphore.
178 *
179 * ip contains the semaphore pointer on entry. Save the C-clobbered
180 * registers (r0 to r3 and lr), but not ip, as we use it as a return
181 * value in some cases..
182 */
183asm(" .section .sched.text , #alloc, #execinstr \n\
184 .align 5 \n\
185 .globl __down_failed \n\
186__down_failed: \n\
187 stmfd sp!, {r0 - r3, lr} \n\
188 mov r0, ip \n\
189 bl __down \n\
190 ldmfd sp!, {r0 - r3, pc}^ \n\
191 \n\
192 .align 5 \n\
193 .globl __down_interruptible_failed \n\
194__down_interruptible_failed: \n\
195 stmfd sp!, {r0 - r3, lr} \n\
196 mov r0, ip \n\
197 bl __down_interruptible \n\
198 mov ip, r0 \n\
199 ldmfd sp!, {r0 - r3, pc}^ \n\
200 \n\
201 .align 5 \n\
202 .globl __down_trylock_failed \n\
203__down_trylock_failed: \n\
204 stmfd sp!, {r0 - r3, lr} \n\
205 mov r0, ip \n\
206 bl __down_trylock \n\
207 mov ip, r0 \n\
208 ldmfd sp!, {r0 - r3, pc}^ \n\
209 \n\
210 .align 5 \n\
211 .globl __up_wakeup \n\
212__up_wakeup: \n\
213 stmfd sp!, {r0 - r3, lr} \n\
214 mov r0, ip \n\
215 bl __up \n\
216 ldmfd sp!, {r0 - r3, pc}^ \n\
217 ");
218
219EXPORT_SYMBOL(__down_failed);
220EXPORT_SYMBOL(__down_interruptible_failed);
221EXPORT_SYMBOL(__down_trylock_failed);
222EXPORT_SYMBOL(__up_wakeup);
223
diff --git a/arch/arm26/kernel/setup.c b/arch/arm26/kernel/setup.c
new file mode 100644
index 000000000000..4eb329e3828a
--- /dev/null
+++ b/arch/arm26/kernel/setup.c
@@ -0,0 +1,573 @@
1/*
2 * linux/arch/arm26/kernel/setup.c
3 *
4 * Copyright (C) 1995-2001 Russell King
5 * Copyright (C) 2003 Ian Molton
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/config.h>
12#include <linux/kernel.h>
13#include <linux/stddef.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/utsname.h>
17#include <linux/blkdev.h>
18#include <linux/console.h>
19#include <linux/bootmem.h>
20#include <linux/seq_file.h>
21#include <linux/tty.h>
22#include <linux/init.h>
23#include <linux/root_dev.h>
24
25#include <asm/elf.h>
26#include <asm/hardware.h>
27#include <asm/io.h>
28#include <asm/procinfo.h>
29#include <asm/setup.h>
30#include <asm/mach-types.h>
31#include <asm/tlbflush.h>
32
33#include <asm/irqchip.h>
34
35#ifndef MEM_SIZE
36#define MEM_SIZE (16*1024*1024)
37#endif
38
39#ifdef CONFIG_PREEMPT
40DEFINE_SPINLOCK(kernel_flag);
41#endif
42
43#if defined(CONFIG_FPE_NWFPE)
44char fpe_type[8];
45
46static int __init fpe_setup(char *line)
47{
48 memcpy(fpe_type, line, 8);
49 return 1;
50}
51
52__setup("fpe=", fpe_setup);
53#endif
54
55extern void paging_init(struct meminfo *);
56extern void convert_to_tag_list(struct tag *tags);
57extern void squash_mem_tags(struct tag *tag);
58extern void bootmem_init(struct meminfo *);
59extern int root_mountflags;
60extern int _stext, _text, _etext, _edata, _end;
61#ifdef CONFIG_XIP_KERNEL
62extern int _endtext, _sdata;
63#endif
64
65
66unsigned int processor_id;
67unsigned int __machine_arch_type;
68unsigned int system_rev;
69unsigned int system_serial_low;
70unsigned int system_serial_high;
71unsigned int elf_hwcap;
72unsigned int memc_ctrl_reg;
73unsigned int number_mfm_drives;
74
75struct processor processor;
76
77char elf_platform[ELF_PLATFORM_SIZE];
78
79unsigned long phys_initrd_start __initdata = 0;
80unsigned long phys_initrd_size __initdata = 0;
81static struct meminfo meminfo __initdata = { 0, };
82static struct proc_info_item proc_info;
83static const char *machine_name;
84static char command_line[COMMAND_LINE_SIZE];
85
86static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
87
88/*
89 * Standard memory resources
90 */
91static struct resource mem_res[] = {
92 { "Video RAM", 0, 0, IORESOURCE_MEM },
93 { "Kernel code", 0, 0, IORESOURCE_MEM },
94 { "Kernel data", 0, 0, IORESOURCE_MEM }
95};
96
97#define video_ram mem_res[0]
98#define kernel_code mem_res[1]
99#define kernel_data mem_res[2]
100
101static struct resource io_res[] = {
102 { "reserved", 0x3bc, 0x3be, IORESOURCE_IO | IORESOURCE_BUSY },
103 { "reserved", 0x378, 0x37f, IORESOURCE_IO | IORESOURCE_BUSY },
104 { "reserved", 0x278, 0x27f, IORESOURCE_IO | IORESOURCE_BUSY }
105};
106
107#define lp0 io_res[0]
108#define lp1 io_res[1]
109#define lp2 io_res[2]
110
111#define dump_cpu_info() do { } while (0)
112
113static void __init setup_processor(void)
114{
115 extern struct proc_info_list __proc_info_begin, __proc_info_end;
116 struct proc_info_list *list;
117
118 /*
119 * locate processor in the list of supported processor
120 * types. The linker builds this table for us from the
121 * entries in arch/arm26/mm/proc-*.S
122 */
123 for (list = &__proc_info_begin; list < &__proc_info_end ; list++)
124 if ((processor_id & list->cpu_mask) == list->cpu_val)
125 break;
126
127 /*
128 * If processor type is unrecognised, then we
129 * can do nothing...
130 */
131 if (list >= &__proc_info_end) {
132 printk("CPU configuration botched (ID %08x), unable "
133 "to continue.\n", processor_id);
134 while (1);
135 }
136
137 proc_info = *list->info;
138 processor = *list->proc;
139
140
141 printk("CPU: %s %s revision %d\n",
142 proc_info.manufacturer, proc_info.cpu_name,
143 (int)processor_id & 15);
144
145 dump_cpu_info();
146
147 sprintf(system_utsname.machine, "%s", list->arch_name);
148 sprintf(elf_platform, "%s", list->elf_name);
149 elf_hwcap = list->elf_hwcap;
150
151 cpu_proc_init();
152}
153
154/*
155 * Initial parsing of the command line. We need to pick out the
156 * memory size. We look for mem=size@start, where start and size
157 * are "size[KkMm]"
158 */
159static void __init
160parse_cmdline(struct meminfo *mi, char **cmdline_p, char *from)
161{
162 char c = ' ', *to = command_line;
163 int usermem = 0, len = 0;
164
165 for (;;) {
166 if (c == ' ' && !memcmp(from, "mem=", 4)) {
167 unsigned long size, start;
168
169 if (to != command_line)
170 to -= 1;
171
172 /*
173 * If the user specifies memory size, we
174 * blow away any automatically generated
175 * size.
176 */
177 if (usermem == 0) {
178 usermem = 1;
179 mi->nr_banks = 0;
180 }
181
182 start = PHYS_OFFSET;
183 size = memparse(from + 4, &from);
184 if (*from == '@')
185 start = memparse(from + 1, &from);
186
187 mi->bank[mi->nr_banks].start = start;
188 mi->bank[mi->nr_banks].size = size;
189 mi->bank[mi->nr_banks].node = PHYS_TO_NID(start);
190 mi->nr_banks += 1;
191 }
192 c = *from++;
193 if (!c)
194 break;
195 if (COMMAND_LINE_SIZE <= ++len)
196 break;
197 *to++ = c;
198 }
199 *to = '\0';
200 *cmdline_p = command_line;
201}
202
203static void __init
204setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz)
205{
206#ifdef CONFIG_BLK_DEV_RAM
207 extern int rd_size, rd_image_start, rd_prompt, rd_doload;
208
209 rd_image_start = image_start;
210 rd_prompt = prompt;
211 rd_doload = doload;
212
213 if (rd_sz)
214 rd_size = rd_sz;
215#endif
216}
217
218static void __init
219request_standard_resources(struct meminfo *mi)
220{
221 struct resource *res;
222 int i;
223
224 kernel_code.start = init_mm.start_code;
225 kernel_code.end = init_mm.end_code - 1;
226#ifdef CONFIG_XIP_KERNEL
227 kernel_data.start = init_mm.start_data;
228#else
229 kernel_data.start = init_mm.end_code;
230#endif
231 kernel_data.end = init_mm.brk - 1;
232
233 for (i = 0; i < mi->nr_banks; i++) {
234 unsigned long virt_start, virt_end;
235
236 if (mi->bank[i].size == 0)
237 continue;
238
239 virt_start = mi->bank[i].start;
240 virt_end = virt_start + mi->bank[i].size - 1;
241
242 res = alloc_bootmem_low(sizeof(*res));
243 res->name = "System RAM";
244 res->start = virt_start;
245 res->end = virt_end;
246 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
247
248 request_resource(&iomem_resource, res);
249
250 if (kernel_code.start >= res->start &&
251 kernel_code.end <= res->end)
252 request_resource(res, &kernel_code);
253 if (kernel_data.start >= res->start &&
254 kernel_data.end <= res->end)
255 request_resource(res, &kernel_data);
256 }
257
258/* FIXME - needed? if (mdesc->video_start) {
259 video_ram.start = mdesc->video_start;
260 video_ram.end = mdesc->video_end;
261 request_resource(&iomem_resource, &video_ram);
262 }*/
263
264 /*
265 * Some machines don't have the possibility of ever
266 * possessing lp1 or lp2
267 */
268 if (0) /* FIXME - need to do this for A5k at least */
269 request_resource(&ioport_resource, &lp0);
270}
271
272/*
273 * Tag parsing.
274 *
275 * This is the new way of passing data to the kernel at boot time. Rather
276 * than passing a fixed inflexible structure to the kernel, we pass a list
277 * of variable-sized tags to the kernel. The first tag must be a ATAG_CORE
278 * tag for the list to be recognised (to distinguish the tagged list from
279 * a param_struct). The list is terminated with a zero-length tag (this tag
280 * is not parsed in any way).
281 */
282static int __init parse_tag_core(const struct tag *tag)
283{
284 if (tag->hdr.size > 2) {
285 if ((tag->u.core.flags & 1) == 0)
286 root_mountflags &= ~MS_RDONLY;
287 ROOT_DEV = old_decode_dev(tag->u.core.rootdev);
288 }
289 return 0;
290}
291
292__tagtable(ATAG_CORE, parse_tag_core);
293
294static int __init parse_tag_mem32(const struct tag *tag)
295{
296 if (meminfo.nr_banks >= NR_BANKS) {
297 printk(KERN_WARNING
298 "Ignoring memory bank 0x%08x size %dKB\n",
299 tag->u.mem.start, tag->u.mem.size / 1024);
300 return -EINVAL;
301 }
302 meminfo.bank[meminfo.nr_banks].start = tag->u.mem.start;
303 meminfo.bank[meminfo.nr_banks].size = tag->u.mem.size;
304 meminfo.bank[meminfo.nr_banks].node = PHYS_TO_NID(tag->u.mem.start);
305 meminfo.nr_banks += 1;
306
307 return 0;
308}
309
310__tagtable(ATAG_MEM, parse_tag_mem32);
311
312#if defined(CONFIG_DUMMY_CONSOLE)
313struct screen_info screen_info = {
314 .orig_video_lines = 30,
315 .orig_video_cols = 80,
316 .orig_video_mode = 0,
317 .orig_video_ega_bx = 0,
318 .orig_video_isVGA = 1,
319 .orig_video_points = 8
320};
321
322static int __init parse_tag_videotext(const struct tag *tag)
323{
324 screen_info.orig_x = tag->u.videotext.x;
325 screen_info.orig_y = tag->u.videotext.y;
326 screen_info.orig_video_page = tag->u.videotext.video_page;
327 screen_info.orig_video_mode = tag->u.videotext.video_mode;
328 screen_info.orig_video_cols = tag->u.videotext.video_cols;
329 screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx;
330 screen_info.orig_video_lines = tag->u.videotext.video_lines;
331 screen_info.orig_video_isVGA = tag->u.videotext.video_isvga;
332 screen_info.orig_video_points = tag->u.videotext.video_points;
333 return 0;
334}
335
336__tagtable(ATAG_VIDEOTEXT, parse_tag_videotext);
337#endif
338
339static int __init parse_tag_acorn(const struct tag *tag)
340{
341 memc_ctrl_reg = tag->u.acorn.memc_control_reg;
342 number_mfm_drives = tag->u.acorn.adfsdrives;
343 return 0;
344}
345
346__tagtable(ATAG_ACORN, parse_tag_acorn);
347
348static int __init parse_tag_ramdisk(const struct tag *tag)
349{
350 setup_ramdisk((tag->u.ramdisk.flags & 1) == 0,
351 (tag->u.ramdisk.flags & 2) == 0,
352 tag->u.ramdisk.start, tag->u.ramdisk.size);
353 return 0;
354}
355
356__tagtable(ATAG_RAMDISK, parse_tag_ramdisk);
357
358static int __init parse_tag_initrd(const struct tag *tag)
359{
360 printk(KERN_WARNING "ATAG_INITRD is deprecated; please update your bootloader. \n");
361 phys_initrd_start = (unsigned long)tag->u.initrd.start;
362 phys_initrd_size = (unsigned long)tag->u.initrd.size;
363 return 0;
364}
365
366__tagtable(ATAG_INITRD, parse_tag_initrd);
367
368static int __init parse_tag_initrd2(const struct tag *tag)
369{
370 printk(KERN_WARNING "ATAG_INITRD is deprecated; please update your bootloader. \n");
371 phys_initrd_start = (unsigned long)tag->u.initrd.start;
372 phys_initrd_size = (unsigned long)tag->u.initrd.size;
373 return 0;
374}
375
376__tagtable(ATAG_INITRD2, parse_tag_initrd2);
377
378static int __init parse_tag_serialnr(const struct tag *tag)
379{
380 system_serial_low = tag->u.serialnr.low;
381 system_serial_high = tag->u.serialnr.high;
382 return 0;
383}
384
385__tagtable(ATAG_SERIAL, parse_tag_serialnr);
386
387static int __init parse_tag_revision(const struct tag *tag)
388{
389 system_rev = tag->u.revision.rev;
390 return 0;
391}
392
393__tagtable(ATAG_REVISION, parse_tag_revision);
394
395static int __init parse_tag_cmdline(const struct tag *tag)
396{
397 strncpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE);
398 default_command_line[COMMAND_LINE_SIZE - 1] = '\0';
399 return 0;
400}
401
402__tagtable(ATAG_CMDLINE, parse_tag_cmdline);
403
404/*
405 * Scan the tag table for this tag, and call its parse function.
406 * The tag table is built by the linker from all the __tagtable
407 * declarations.
408 */
409static int __init parse_tag(const struct tag *tag)
410{
411 extern struct tagtable __tagtable_begin, __tagtable_end;
412 struct tagtable *t;
413
414 for (t = &__tagtable_begin; t < &__tagtable_end; t++)
415 if (tag->hdr.tag == t->tag) {
416 t->parse(tag);
417 break;
418 }
419
420 return t < &__tagtable_end;
421}
422
423/*
424 * Parse all tags in the list, checking both the global and architecture
425 * specific tag tables.
426 */
427static void __init parse_tags(const struct tag *t)
428{
429 for (; t->hdr.size; t = tag_next(t))
430 if (!parse_tag(t))
431 printk(KERN_WARNING
432 "Ignoring unrecognised tag 0x%08x\n",
433 t->hdr.tag);
434}
435
436/*
437 * This holds our defaults.
438 */
439static struct init_tags {
440 struct tag_header hdr1;
441 struct tag_core core;
442 struct tag_header hdr2;
443 struct tag_mem32 mem;
444 struct tag_header hdr3;
445} init_tags __initdata = {
446 { tag_size(tag_core), ATAG_CORE },
447 { 1, PAGE_SIZE, 0xff },
448 { tag_size(tag_mem32), ATAG_MEM },
449 { MEM_SIZE, PHYS_OFFSET },
450 { 0, ATAG_NONE }
451};
452
453void __init setup_arch(char **cmdline_p)
454{
455 struct tag *tags = (struct tag *)&init_tags;
456 char *from = default_command_line;
457
458 setup_processor();
459 if(machine_arch_type == MACH_TYPE_A5K)
460 machine_name = "A5000";
461 else if(machine_arch_type == MACH_TYPE_ARCHIMEDES)
462 machine_name = "Archimedes";
463 else
464 machine_name = "UNKNOWN";
465
466 //FIXME - the tag struct is always copied here but this is a block
467 // of RAM that is accidentally reserved along with video RAM. perhaps
468 // it would be a good idea to explicitly reserve this?
469
470 tags = (struct tag *)0x0207c000;
471
472 /*
473 * If we have the old style parameters, convert them to
474 * a tag list.
475 */
476 if (tags->hdr.tag != ATAG_CORE)
477 convert_to_tag_list(tags);
478 if (tags->hdr.tag != ATAG_CORE)
479 tags = (struct tag *)&init_tags;
480 if (tags->hdr.tag == ATAG_CORE) {
481 if (meminfo.nr_banks != 0)
482 squash_mem_tags(tags);
483 parse_tags(tags);
484 }
485
486 init_mm.start_code = (unsigned long) &_text;
487#ifndef CONFIG_XIP_KERNEL
488 init_mm.end_code = (unsigned long) &_etext;
489#else
490 init_mm.end_code = (unsigned long) &_endtext;
491 init_mm.start_data = (unsigned long) &_sdata;
492#endif
493 init_mm.end_data = (unsigned long) &_edata;
494 init_mm.brk = (unsigned long) &_end;
495
496 memcpy(saved_command_line, from, COMMAND_LINE_SIZE);
497 saved_command_line[COMMAND_LINE_SIZE-1] = '\0';
498 parse_cmdline(&meminfo, cmdline_p, from);
499 bootmem_init(&meminfo);
500 paging_init(&meminfo);
501 request_standard_resources(&meminfo);
502
503#ifdef CONFIG_VT
504#if defined(CONFIG_DUMMY_CONSOLE)
505 conswitchp = &dummy_con;
506#endif
507#endif
508}
509
510static const char *hwcap_str[] = {
511 "swp",
512 "half",
513 "thumb",
514 "26bit",
515 "fastmult",
516 "fpa",
517 "vfp",
518 "edsp",
519 NULL
520};
521
522static int c_show(struct seq_file *m, void *v)
523{
524 int i;
525
526 seq_printf(m, "Processor\t: %s %s rev %d (%s)\n",
527 proc_info.manufacturer, proc_info.cpu_name,
528 (int)processor_id & 15, elf_platform);
529
530 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
531 loops_per_jiffy / (500000/HZ),
532 (loops_per_jiffy / (5000/HZ)) % 100);
533
534 /* dump out the processor features */
535 seq_puts(m, "Features\t: ");
536
537 for (i = 0; hwcap_str[i]; i++)
538 if (elf_hwcap & (1 << i))
539 seq_printf(m, "%s ", hwcap_str[i]);
540
541 seq_puts(m, "\n");
542
543 seq_printf(m, "CPU part\t\t: %07x\n", processor_id >> 4);
544 seq_printf(m, "CPU revision\t: %d\n\n", processor_id & 15);
545 seq_printf(m, "Hardware\t: %s\n", machine_name);
546 seq_printf(m, "Revision\t: %04x\n", system_rev);
547 seq_printf(m, "Serial\t\t: %08x%08x\n",
548 system_serial_high, system_serial_low);
549
550 return 0;
551}
552
553static void *c_start(struct seq_file *m, loff_t *pos)
554{
555 return *pos < 1 ? (void *)1 : NULL;
556}
557
558static void *c_next(struct seq_file *m, void *v, loff_t *pos)
559{
560 ++*pos;
561 return NULL;
562}
563
564static void c_stop(struct seq_file *m, void *v)
565{
566}
567
568struct seq_operations cpuinfo_op = {
569 .start = c_start,
570 .next = c_next,
571 .stop = c_stop,
572 .show = c_show
573};
diff --git a/arch/arm26/kernel/signal.c b/arch/arm26/kernel/signal.c
new file mode 100644
index 000000000000..356d9809cc0b
--- /dev/null
+++ b/arch/arm26/kernel/signal.c
@@ -0,0 +1,540 @@
1/*
2 * linux/arch/arm26/kernel/signal.c
3 *
4 * Copyright (C) 1995-2002 Russell King
5 * Copyright (C) 2003 Ian Molton (ARM26)
6 *
7 * FIXME!!! This is probably very broken (13/05/2003)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/config.h>
14#include <linux/sched.h>
15#include <linux/mm.h>
16#include <linux/smp.h>
17#include <linux/smp_lock.h>
18#include <linux/kernel.h>
19#include <linux/errno.h>
20#include <linux/signal.h>
21#include <linux/wait.h>
22#include <linux/ptrace.h>
23#include <linux/personality.h>
24#include <linux/tty.h>
25#include <linux/binfmts.h>
26#include <linux/elf.h>
27
28#include <asm/pgalloc.h>
29#include <asm/ucontext.h>
30#include <asm/uaccess.h>
31#include <asm/unistd.h>
32
33#include "ptrace.h"
34
35#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
36
37/*
38 * For ARM syscalls, we encode the syscall number into the instruction.
39 */
40#define SWI_SYS_SIGRETURN (0xef000000|(__NR_sigreturn))
41#define SWI_SYS_RT_SIGRETURN (0xef000000|(__NR_rt_sigreturn))
42
43static int do_signal(sigset_t *oldset, struct pt_regs * regs, int syscall);
44
45/*
46 * atomically swap in the new signal mask, and wait for a signal.
47 */
48asmlinkage int sys_sigsuspend(int restart, unsigned long oldmask, old_sigset_t mask, struct pt_regs *regs)
49{
50 sigset_t saveset;
51
52 mask &= _BLOCKABLE;
53 spin_lock_irq(&current->sighand->siglock);
54 saveset = current->blocked;
55 siginitset(&current->blocked, mask);
56 recalc_sigpending();
57 spin_unlock_irq(&current->sighand->siglock);
58 regs->ARM_r0 = -EINTR;
59
60 while (1) {
61 current->state = TASK_INTERRUPTIBLE;
62 schedule();
63 if (do_signal(&saveset, regs, 0))
64 return regs->ARM_r0;
65 }
66}
67
68asmlinkage int
69sys_rt_sigsuspend(sigset_t *unewset, size_t sigsetsize, struct pt_regs *regs)
70{
71 sigset_t saveset, newset;
72
73 /* XXX: Don't preclude handling different sized sigset_t's. */
74 if (sigsetsize != sizeof(sigset_t))
75 return -EINVAL;
76
77 if (copy_from_user(&newset, unewset, sizeof(newset)))
78 return -EFAULT;
79 sigdelsetmask(&newset, ~_BLOCKABLE);
80
81 spin_lock_irq(&current->sighand->siglock);
82 saveset = current->blocked;
83 current->blocked = newset;
84 recalc_sigpending();
85 spin_unlock_irq(&current->sighand->siglock);
86 regs->ARM_r0 = -EINTR;
87
88 while (1) {
89 current->state = TASK_INTERRUPTIBLE;
90 schedule();
91 if (do_signal(&saveset, regs, 0))
92 return regs->ARM_r0;
93 }
94}
95
96asmlinkage int
97sys_sigaction(int sig, const struct old_sigaction *act,
98 struct old_sigaction *oact)
99{
100 struct k_sigaction new_ka, old_ka;
101 int ret;
102
103 if (act) {
104 old_sigset_t mask;
105 if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
106 __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
107 __get_user(new_ka.sa.sa_restorer, &act->sa_restorer))
108 return -EFAULT;
109 __get_user(new_ka.sa.sa_flags, &act->sa_flags);
110 __get_user(mask, &act->sa_mask);
111 siginitset(&new_ka.sa.sa_mask, mask);
112 }
113
114 ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
115
116 if (!ret && oact) {
117 if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
118 __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
119 __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer))
120 return -EFAULT;
121 __put_user(old_ka.sa.sa_flags, &oact->sa_flags);
122 __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
123 }
124
125 return ret;
126}
127
128/*
129 * Do a signal return; undo the signal stack.
130 */
131struct sigframe
132{
133 struct sigcontext sc;
134 unsigned long extramask[_NSIG_WORDS-1];
135 unsigned long retcode;
136};
137
138struct rt_sigframe
139{
140 struct siginfo *pinfo;
141 void *puc;
142 struct siginfo info;
143 struct ucontext uc;
144 unsigned long retcode;
145};
146
147static int
148restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
149{
150 int err = 0;
151
152 __get_user_error(regs->ARM_r0, &sc->arm_r0, err);
153 __get_user_error(regs->ARM_r1, &sc->arm_r1, err);
154 __get_user_error(regs->ARM_r2, &sc->arm_r2, err);
155 __get_user_error(regs->ARM_r3, &sc->arm_r3, err);
156 __get_user_error(regs->ARM_r4, &sc->arm_r4, err);
157 __get_user_error(regs->ARM_r5, &sc->arm_r5, err);
158 __get_user_error(regs->ARM_r6, &sc->arm_r6, err);
159 __get_user_error(regs->ARM_r7, &sc->arm_r7, err);
160 __get_user_error(regs->ARM_r8, &sc->arm_r8, err);
161 __get_user_error(regs->ARM_r9, &sc->arm_r9, err);
162 __get_user_error(regs->ARM_r10, &sc->arm_r10, err);
163 __get_user_error(regs->ARM_fp, &sc->arm_fp, err);
164 __get_user_error(regs->ARM_ip, &sc->arm_ip, err);
165 __get_user_error(regs->ARM_sp, &sc->arm_sp, err);
166 __get_user_error(regs->ARM_lr, &sc->arm_lr, err);
167 __get_user_error(regs->ARM_pc, &sc->arm_pc, err);
168
169 err |= !valid_user_regs(regs);
170
171 return err;
172}
173
174asmlinkage int sys_sigreturn(struct pt_regs *regs)
175{
176 struct sigframe *frame;
177 sigset_t set;
178
179 /*
180 * Since we stacked the signal on a 64-bit boundary,
181 * then 'sp' should be word aligned here. If it's
182 * not, then the user is trying to mess with us.
183 */
184 if (regs->ARM_sp & 7)
185 goto badframe;
186
187 frame = (struct sigframe *)regs->ARM_sp;
188
189 if (!access_ok(VERIFY_READ, frame, sizeof (*frame)))
190 goto badframe;
191 if (__get_user(set.sig[0], &frame->sc.oldmask)
192 || (_NSIG_WORDS > 1
193 && __copy_from_user(&set.sig[1], &frame->extramask,
194 sizeof(frame->extramask))))
195 goto badframe;
196
197 sigdelsetmask(&set, ~_BLOCKABLE);
198 spin_lock_irq(&current->sighand->siglock);
199 current->blocked = set;
200 recalc_sigpending();
201 spin_unlock_irq(&current->sighand->siglock);
202
203 if (restore_sigcontext(regs, &frame->sc))
204 goto badframe;
205
206 /* Send SIGTRAP if we're single-stepping */
207 if (current->ptrace & PT_SINGLESTEP) {
208 ptrace_cancel_bpt(current);
209 send_sig(SIGTRAP, current, 1);
210 }
211
212 return regs->ARM_r0;
213
214badframe:
215 force_sig(SIGSEGV, current);
216 return 0;
217}
218
219asmlinkage int sys_rt_sigreturn(struct pt_regs *regs)
220{
221 struct rt_sigframe *frame;
222 sigset_t set;
223
224 /*
225 * Since we stacked the signal on a 64-bit boundary,
226 * then 'sp' should be word aligned here. If it's
227 * not, then the user is trying to mess with us.
228 */
229 if (regs->ARM_sp & 7)
230 goto badframe;
231
232 frame = (struct rt_sigframe *)regs->ARM_sp;
233
234 if (!access_ok(VERIFY_READ, frame, sizeof (*frame)))
235 goto badframe;
236 if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
237 goto badframe;
238
239 sigdelsetmask(&set, ~_BLOCKABLE);
240 spin_lock_irq(&current->sighand->siglock);
241 current->blocked = set;
242 recalc_sigpending();
243 spin_unlock_irq(&current->sighand->siglock);
244
245 if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
246 goto badframe;
247
248 /* Send SIGTRAP if we're single-stepping */
249 if (current->ptrace & PT_SINGLESTEP) {
250 ptrace_cancel_bpt(current);
251 send_sig(SIGTRAP, current, 1);
252 }
253
254 return regs->ARM_r0;
255
256badframe:
257 force_sig(SIGSEGV, current);
258 return 0;
259}
260
261static int
262setup_sigcontext(struct sigcontext *sc, /*struct _fpstate *fpstate,*/
263 struct pt_regs *regs, unsigned long mask)
264{
265 int err = 0;
266
267 __put_user_error(regs->ARM_r0, &sc->arm_r0, err);
268 __put_user_error(regs->ARM_r1, &sc->arm_r1, err);
269 __put_user_error(regs->ARM_r2, &sc->arm_r2, err);
270 __put_user_error(regs->ARM_r3, &sc->arm_r3, err);
271 __put_user_error(regs->ARM_r4, &sc->arm_r4, err);
272 __put_user_error(regs->ARM_r5, &sc->arm_r5, err);
273 __put_user_error(regs->ARM_r6, &sc->arm_r6, err);
274 __put_user_error(regs->ARM_r7, &sc->arm_r7, err);
275 __put_user_error(regs->ARM_r8, &sc->arm_r8, err);
276 __put_user_error(regs->ARM_r9, &sc->arm_r9, err);
277 __put_user_error(regs->ARM_r10, &sc->arm_r10, err);
278 __put_user_error(regs->ARM_fp, &sc->arm_fp, err);
279 __put_user_error(regs->ARM_ip, &sc->arm_ip, err);
280 __put_user_error(regs->ARM_sp, &sc->arm_sp, err);
281 __put_user_error(regs->ARM_lr, &sc->arm_lr, err);
282 __put_user_error(regs->ARM_pc, &sc->arm_pc, err);
283
284 __put_user_error(current->thread.trap_no, &sc->trap_no, err);
285 __put_user_error(current->thread.error_code, &sc->error_code, err);
286 __put_user_error(current->thread.address, &sc->fault_address, err);
287 __put_user_error(mask, &sc->oldmask, err);
288
289 return err;
290}
291
292static inline void *
293get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, int framesize)
294{
295 unsigned long sp = regs->ARM_sp;
296
297 /*
298 * This is the X/Open sanctioned signal stack switching.
299 */
300 if ((ka->sa.sa_flags & SA_ONSTACK) && !sas_ss_flags(sp))
301 sp = current->sas_ss_sp + current->sas_ss_size;
302
303 /*
304 * ATPCS B01 mandates 8-byte alignment
305 */
306 return (void *)((sp - framesize) & ~7);
307}
308
309static int
310setup_return(struct pt_regs *regs, struct k_sigaction *ka,
311 unsigned long *rc, void *frame, int usig)
312{
313 unsigned long handler = (unsigned long)ka->sa.sa_handler;
314 unsigned long retcode;
315
316 if (ka->sa.sa_flags & SA_RESTORER) {
317 retcode = (unsigned long)ka->sa.sa_restorer;
318 } else {
319
320 if (__put_user((ka->sa.sa_flags & SA_SIGINFO)?SWI_SYS_RT_SIGRETURN:SWI_SYS_SIGRETURN, rc))
321 return 1;
322
323 retcode = ((unsigned long)rc);
324 }
325
326 regs->ARM_r0 = usig;
327 regs->ARM_sp = (unsigned long)frame;
328 regs->ARM_lr = retcode;
329 regs->ARM_pc = handler & ~3;
330
331 return 0;
332}
333
334static int
335setup_frame(int usig, struct k_sigaction *ka, sigset_t *set, struct pt_regs *regs)
336{
337 struct sigframe *frame = get_sigframe(ka, regs, sizeof(*frame));
338 int err = 0;
339
340 if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame)))
341 return 1;
342
343 err |= setup_sigcontext(&frame->sc, /*&frame->fpstate,*/ regs, set->sig[0]);
344
345 if (_NSIG_WORDS > 1) {
346 err |= __copy_to_user(frame->extramask, &set->sig[1],
347 sizeof(frame->extramask));
348 }
349
350 if (err == 0)
351 err = setup_return(regs, ka, &frame->retcode, frame, usig);
352
353 return err;
354}
355
356static int
357setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
358 sigset_t *set, struct pt_regs *regs)
359{
360 struct rt_sigframe *frame = get_sigframe(ka, regs, sizeof(*frame));
361 int err = 0;
362
363 if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame)))
364 return 1;
365
366 __put_user_error(&frame->info, &frame->pinfo, err);
367 __put_user_error(&frame->uc, &frame->puc, err);
368 err |= copy_siginfo_to_user(&frame->info, info);
369
370 /* Clear all the bits of the ucontext we don't use. */
371 err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext));
372
373 err |= setup_sigcontext(&frame->uc.uc_mcontext, /*&frame->fpstate,*/
374 regs, set->sig[0]);
375 err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
376
377 if (err == 0)
378 err = setup_return(regs, ka, &frame->retcode, frame, usig);
379
380 if (err == 0) {
381 /*
382 * For realtime signals we must also set the second and third
383 * arguments for the signal handler.
384 * -- Peter Maydell <pmaydell@chiark.greenend.org.uk> 2000-12-06
385 */
386 regs->ARM_r1 = (unsigned long)frame->pinfo;
387 regs->ARM_r2 = (unsigned long)frame->puc;
388 }
389
390 return err;
391}
392
393static inline void restart_syscall(struct pt_regs *regs)
394{
395 regs->ARM_r0 = regs->ARM_ORIG_r0;
396 regs->ARM_pc -= 4;
397}
398
399/*
400 * OK, we're invoking a handler
401 */
402static void
403handle_signal(unsigned long sig, siginfo_t *info, sigset_t *oldset,
404 struct pt_regs * regs, int syscall)
405{
406 struct thread_info *thread = current_thread_info();
407 struct task_struct *tsk = current;
408 struct k_sigaction *ka = &tsk->sighand->action[sig-1];
409 int usig = sig;
410 int ret;
411
412 /*
413 * If we were from a system call, check for system call restarting...
414 */
415 if (syscall) {
416 switch (regs->ARM_r0) {
417 case -ERESTART_RESTARTBLOCK:
418 current_thread_info()->restart_block.fn =
419 do_no_restart_syscall;
420 case -ERESTARTNOHAND:
421 regs->ARM_r0 = -EINTR;
422 break;
423 case -ERESTARTSYS:
424 if (!(ka->sa.sa_flags & SA_RESTART)) {
425 regs->ARM_r0 = -EINTR;
426 break;
427 }
428 /* fallthrough */
429 case -ERESTARTNOINTR:
430 restart_syscall(regs);
431 }
432 }
433
434 /*
435 * translate the signal
436 */
437 if (usig < 32 && thread->exec_domain && thread->exec_domain->signal_invmap)
438 usig = thread->exec_domain->signal_invmap[usig];
439
440 /*
441 * Set up the stack frame
442 */
443 if (ka->sa.sa_flags & SA_SIGINFO)
444 ret = setup_rt_frame(usig, ka, info, oldset, regs);
445 else
446 ret = setup_frame(usig, ka, oldset, regs);
447
448 /*
449 * Check that the resulting registers are actually sane.
450 */
451 ret |= !valid_user_regs(regs);
452
453 if (ret == 0) {
454 if (ka->sa.sa_flags & SA_ONESHOT)
455 ka->sa.sa_handler = SIG_DFL;
456
457 if (!(ka->sa.sa_flags & SA_NODEFER)) {
458 spin_lock_irq(&tsk->sighand->siglock);
459 sigorsets(&tsk->blocked, &tsk->blocked,
460 &ka->sa.sa_mask);
461 sigaddset(&tsk->blocked, sig);
462 recalc_sigpending();
463 spin_unlock_irq(&tsk->sighand->siglock);
464 }
465 return;
466 }
467
468 force_sigsegv(sig, tsk);
469}
470
471/*
472 * Note that 'init' is a special process: it doesn't get signals it doesn't
473 * want to handle. Thus you cannot kill init even with a SIGKILL even by
474 * mistake.
475 *
476 * Note that we go through the signals twice: once to check the signals that
477 * the kernel can handle, and then we build all the user-level signal handling
478 * stack-frames in one go after that.
479 */
480static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
481{
482 siginfo_t info;
483 int signr;
484
485 /*
486 * We want the common case to go fast, which
487 * is why we may in certain cases get here from
488 * kernel mode. Just return without doing anything
489 * if so.
490 */
491 if (!user_mode(regs))
492 return 0;
493
494 if (current->ptrace & PT_SINGLESTEP)
495 ptrace_cancel_bpt(current);
496
497 signr = get_signal_to_deliver(&info, regs, NULL);
498 if (signr > 0) {
499 handle_signal(signr, &info, oldset, regs, syscall);
500 if (current->ptrace & PT_SINGLESTEP)
501 ptrace_set_bpt(current);
502 return 1;
503 }
504
505 /*
506 * No signal to deliver to the process - restart the syscall.
507 */
508 if (syscall) {
509 if (regs->ARM_r0 == -ERESTART_RESTARTBLOCK) {
510 u32 *usp;
511
512 regs->ARM_sp -= 12;
513 usp = (u32 *)regs->ARM_sp;
514
515 put_user(regs->ARM_pc, &usp[0]);
516 /* swi __NR_restart_syscall */
517 put_user(0xef000000 | __NR_restart_syscall, &usp[1]);
518 /* ldr pc, [sp], #12 */
519// FIXME!!! is #12 correct there?
520 put_user(0xe49df00c, &usp[2]);
521
522 regs->ARM_pc = regs->ARM_sp + 4;
523 }
524 if (regs->ARM_r0 == -ERESTARTNOHAND ||
525 regs->ARM_r0 == -ERESTARTSYS ||
526 regs->ARM_r0 == -ERESTARTNOINTR) {
527 restart_syscall(regs);
528 }
529 }
530 if (current->ptrace & PT_SINGLESTEP)
531 ptrace_set_bpt(current);
532 return 0;
533}
534
535asmlinkage void
536do_notify_resume(struct pt_regs *regs, unsigned int thread_flags, int syscall)
537{
538 if (thread_flags & _TIF_SIGPENDING)
539 do_signal(&current->blocked, regs, syscall);
540}
diff --git a/arch/arm26/kernel/sys_arm.c b/arch/arm26/kernel/sys_arm.c
new file mode 100644
index 000000000000..e7edd201579a
--- /dev/null
+++ b/arch/arm26/kernel/sys_arm.c
@@ -0,0 +1,324 @@
1/*
2 * linux/arch/arm26/kernel/sys_arm.c
3 *
4 * Copyright (C) People who wrote linux/arch/i386/kernel/sys_i386.c
5 * Copyright (C) 1995, 1996 Russell King.
6 * Copyright (C) 2003 Ian Molton.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This file contains various random system calls that
13 * have a non-standard calling sequence on the Linux/arm
14 * platform.
15 */
16#include <linux/module.h>
17#include <linux/errno.h>
18#include <linux/sched.h>
19#include <linux/slab.h>
20#include <linux/mm.h>
21#include <linux/sem.h>
22#include <linux/msg.h>
23#include <linux/shm.h>
24#include <linux/stat.h>
25#include <linux/syscalls.h>
26#include <linux/mman.h>
27#include <linux/fs.h>
28#include <linux/file.h>
29#include <linux/utsname.h>
30
31#include <asm/uaccess.h>
32#include <asm/ipc.h>
33
34extern unsigned long do_mremap(unsigned long addr, unsigned long old_len,
35 unsigned long new_len, unsigned long flags,
36 unsigned long new_addr);
37
38/*
39 * sys_pipe() is the normal C calling standard for creating
40 * a pipe. It's not the way unix traditionally does this, though.
41 */
42asmlinkage int sys_pipe(unsigned long * fildes)
43{
44 int fd[2];
45 int error;
46
47 error = do_pipe(fd);
48 if (!error) {
49 if (copy_to_user(fildes, fd, 2*sizeof(int)))
50 error = -EFAULT;
51 }
52 return error;
53}
54
55/* common code for old and new mmaps */
56inline long do_mmap2(
57 unsigned long addr, unsigned long len,
58 unsigned long prot, unsigned long flags,
59 unsigned long fd, unsigned long pgoff)
60{
61 int error = -EINVAL;
62 struct file * file = NULL;
63
64 flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
65
66 /*
67 * If we are doing a fixed mapping, and address < PAGE_SIZE,
68 * then deny it.
69 */
70 if (flags & MAP_FIXED && addr < PAGE_SIZE && vectors_base() == 0)
71 goto out;
72
73 error = -EBADF;
74 if (!(flags & MAP_ANONYMOUS)) {
75 file = fget(fd);
76 if (!file)
77 goto out;
78 }
79
80 down_write(&current->mm->mmap_sem);
81 error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
82 up_write(&current->mm->mmap_sem);
83
84 if (file)
85 fput(file);
86out:
87 return error;
88}
89
90struct mmap_arg_struct {
91 unsigned long addr;
92 unsigned long len;
93 unsigned long prot;
94 unsigned long flags;
95 unsigned long fd;
96 unsigned long offset;
97};
98
99asmlinkage int old_mmap(struct mmap_arg_struct *arg)
100{
101 int error = -EFAULT;
102 struct mmap_arg_struct a;
103
104 if (copy_from_user(&a, arg, sizeof(a)))
105 goto out;
106
107 error = -EINVAL;
108 if (a.offset & ~PAGE_MASK)
109 goto out;
110
111 error = do_mmap2(a.addr, a.len, a.prot, a.flags, a.fd, a.offset >> PAGE_SHIFT);
112out:
113 return error;
114}
115
116asmlinkage unsigned long
117sys_arm_mremap(unsigned long addr, unsigned long old_len,
118 unsigned long new_len, unsigned long flags,
119 unsigned long new_addr)
120{
121 unsigned long ret = -EINVAL;
122
123 /*
124 * If we are doing a fixed mapping, and address < PAGE_SIZE,
125 * then deny it.
126 */
127 if (flags & MREMAP_FIXED && new_addr < PAGE_SIZE &&
128 vectors_base() == 0)
129 goto out;
130
131 down_write(&current->mm->mmap_sem);
132 ret = do_mremap(addr, old_len, new_len, flags, new_addr);
133 up_write(&current->mm->mmap_sem);
134
135out:
136 return ret;
137}
138
139/*
140 * Perform the select(nd, in, out, ex, tv) and mmap() system
141 * calls.
142 */
143
144struct sel_arg_struct {
145 unsigned long n;
146 fd_set *inp, *outp, *exp;
147 struct timeval *tvp;
148};
149
150asmlinkage int old_select(struct sel_arg_struct *arg)
151{
152 struct sel_arg_struct a;
153
154 if (copy_from_user(&a, arg, sizeof(a)))
155 return -EFAULT;
156 /* sys_select() does the appropriate kernel locking */
157 return sys_select(a.n, a.inp, a.outp, a.exp, a.tvp);
158}
159
160/*
161 * sys_ipc() is the de-multiplexer for the SysV IPC calls..
162 *
163 * This is really horribly ugly.
164 */
165asmlinkage int sys_ipc (uint call, int first, int second, int third, void *ptr, long fifth)
166{
167 int version, ret;
168
169 version = call >> 16; /* hack for backward compatibility */
170 call &= 0xffff;
171
172 switch (call) {
173 case SEMOP:
174 return sys_semop (first, (struct sembuf *)ptr, second);
175 case SEMGET:
176 return sys_semget (first, second, third);
177 case SEMCTL: {
178 union semun fourth;
179 if (!ptr)
180 return -EINVAL;
181 if (get_user(fourth.__pad, (void **) ptr))
182 return -EFAULT;
183 return sys_semctl (first, second, third, fourth);
184 }
185
186 case MSGSND:
187 return sys_msgsnd (first, (struct msgbuf *) ptr,
188 second, third);
189 case MSGRCV:
190 switch (version) {
191 case 0: {
192 struct ipc_kludge tmp;
193 if (!ptr)
194 return -EINVAL;
195 if (copy_from_user(&tmp,(struct ipc_kludge *) ptr,
196 sizeof (tmp)))
197 return -EFAULT;
198 return sys_msgrcv (first, tmp.msgp, second,
199 tmp.msgtyp, third);
200 }
201 default:
202 return sys_msgrcv (first,
203 (struct msgbuf *) ptr,
204 second, fifth, third);
205 }
206 case MSGGET:
207 return sys_msgget ((key_t) first, second);
208 case MSGCTL:
209 return sys_msgctl (first, second, (struct msqid_ds *) ptr);
210
211 case SHMAT:
212 switch (version) {
213 default: {
214 ulong raddr;
215 ret = do_shmat (first, (char *) ptr, second, &raddr);
216 if (ret)
217 return ret;
218 return put_user (raddr, (ulong *) third);
219 }
220 case 1: /* iBCS2 emulator entry point */
221 if (!segment_eq(get_fs(), get_ds()))
222 return -EINVAL;
223 return do_shmat (first, (char *) ptr,
224 second, (ulong *) third);
225 }
226 case SHMDT:
227 return sys_shmdt ((char *)ptr);
228 case SHMGET:
229 return sys_shmget (first, second, third);
230 case SHMCTL:
231 return sys_shmctl (first, second,
232 (struct shmid_ds *) ptr);
233 default:
234 return -EINVAL;
235 }
236}
237
238/* Fork a new task - this creates a new program thread.
239 * This is called indirectly via a small wrapper
240 */
241asmlinkage int sys_fork(struct pt_regs *regs)
242{
243 return do_fork(SIGCHLD, regs->ARM_sp, regs, 0, NULL, NULL);
244}
245
246/* Clone a task - this clones the calling program thread.
247 * This is called indirectly via a small wrapper
248 */
249asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp, struct pt_regs *regs)
250{
251 /*
252 * We don't support SETTID / CLEARTID (FIXME!!! (nicked from arm32))
253 */
254 if (clone_flags & (CLONE_PARENT_SETTID | CLONE_CHILD_CLEARTID))
255 return -EINVAL;
256
257 if (!newsp)
258 newsp = regs->ARM_sp;
259
260 return do_fork(clone_flags, newsp, regs, 0, NULL, NULL);
261}
262
263asmlinkage int sys_vfork(struct pt_regs *regs)
264{
265 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->ARM_sp, regs, 0, NULL, NULL);
266}
267
268/* sys_execve() executes a new program.
269 * This is called indirectly via a small wrapper
270 */
271asmlinkage int sys_execve(char *filenamei, char **argv, char **envp, struct pt_regs *regs)
272{
273 int error;
274 char * filename;
275
276 filename = getname(filenamei);
277 error = PTR_ERR(filename);
278 if (IS_ERR(filename))
279 goto out;
280 error = do_execve(filename, argv, envp, regs);
281 putname(filename);
282out:
283 return error;
284}
285
286/* FIXME - see if this is correct for arm26 */
287long execve(const char *filename, char **argv, char **envp)
288{
289 struct pt_regs regs;
290 int ret;
291 memset(&regs, 0, sizeof(struct pt_regs));
292 ret = do_execve((char *)filename, (char __user * __user *)argv, (char __user * __user *)envp, &regs);
293 if (ret < 0)
294 goto out;
295
296 /*
297 * Save argc to the register structure for userspace.
298 */
299 regs.ARM_r0 = ret;
300
301 /*
302 * We were successful. We won't be returning to our caller, but
303 * instead to user space by manipulating the kernel stack.
304 */
305 asm( "add r0, %0, %1\n\t"
306 "mov r1, %2\n\t"
307 "mov r2, %3\n\t"
308 "bl memmove\n\t" /* copy regs to top of stack */
309 "mov r8, #0\n\t" /* not a syscall */
310 "mov r9, %0\n\t" /* thread structure */
311 "mov sp, r0\n\t" /* reposition stack pointer */
312 "b ret_to_user"
313 :
314 : "r" (current_thread_info()),
315 "Ir" (THREAD_SIZE - 8 - sizeof(regs)),
316 "r" (&regs),
317 "Ir" (sizeof(regs))
318 : "r0", "r1", "r2", "r3", "ip", "memory");
319
320 out:
321 return ret;
322}
323
324EXPORT_SYMBOL(execve);
diff --git a/arch/arm26/kernel/time.c b/arch/arm26/kernel/time.c
new file mode 100644
index 000000000000..549a6b2e177e
--- /dev/null
+++ b/arch/arm26/kernel/time.c
@@ -0,0 +1,234 @@
1/*
2 * linux/arch/arm26/kernel/time.c
3 *
4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
5 * Modifications for ARM (C) 1994-2001 Russell King
6 * Mods for ARM26 (C) 2003 Ian Molton
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This file contains the ARM-specific time handling details:
13 * reading the RTC at bootup, etc...
14 *
15 * 1994-07-02 Alan Modra
16 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
17 * 1998-12-20 Updated NTP code according to technical memorandum Jan '96
18 * "A Kernel Model for Precision Timekeeping" by Dave Mills
19 */
20
21#include <linux/config.h>
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/interrupt.h>
25#include <linux/time.h>
26#include <linux/init.h>
27#include <linux/smp.h>
28#include <linux/timex.h>
29#include <linux/errno.h>
30#include <linux/profile.h>
31
32#include <asm/hardware.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/ioc.h>
36
37u64 jiffies_64 = INITIAL_JIFFIES;
38
39EXPORT_SYMBOL(jiffies_64);
40
41extern unsigned long wall_jiffies;
42
43/* this needs a better home */
44DEFINE_SPINLOCK(rtc_lock);
45
46/* change this if you have some constant time drift */
47#define USECS_PER_JIFFY (1000000/HZ)
48
49static int dummy_set_rtc(void)
50{
51 return 0;
52}
53
54/*
55 * hook for setting the RTC's idea of the current time.
56 */
57int (*set_rtc)(void) = dummy_set_rtc;
58
59/*
60 * Get time offset based on IOCs timer.
61 * FIXME - if this is called with interrutps off, why the shennanigans
62 * below ?
63 */
64static unsigned long gettimeoffset(void)
65{
66 unsigned int count1, count2, status;
67 long offset;
68
69 ioc_writeb (0, IOC_T0LATCH);
70 barrier ();
71 count1 = ioc_readb(IOC_T0CNTL) | (ioc_readb(IOC_T0CNTH) << 8);
72 barrier ();
73 status = ioc_readb(IOC_IRQREQA);
74 barrier ();
75 ioc_writeb (0, IOC_T0LATCH);
76 barrier ();
77 count2 = ioc_readb(IOC_T0CNTL) | (ioc_readb(IOC_T0CNTH) << 8);
78
79 offset = count2;
80 if (count2 < count1) {
81 /*
82 * We have not had an interrupt between reading count1
83 * and count2.
84 */
85 if (status & (1 << 5))
86 offset -= LATCH;
87 } else if (count2 > count1) {
88 /*
89 * We have just had another interrupt between reading
90 * count1 and count2.
91 */
92 offset -= LATCH;
93 }
94
95 offset = (LATCH - offset) * (tick_nsec / 1000);
96 return (offset + LATCH/2) / LATCH;
97}
98
99/*
100 * Scheduler clock - returns current time in nanosec units.
101 */
102unsigned long long sched_clock(void)
103{
104 return (unsigned long long)jiffies * (1000000000 / HZ);
105}
106
107static unsigned long next_rtc_update;
108
109/*
110 * If we have an externally synchronized linux clock, then update
111 * CMOS clock accordingly every ~11 minutes. set_rtc() has to be
112 * called as close as possible to 500 ms before the new second
113 * starts.
114 */
115static inline void do_set_rtc(void)
116{
117 if (time_status & STA_UNSYNC || set_rtc == NULL)
118 return;
119
120//FIXME - timespec.tv_sec is a time_t not unsigned long
121 if (next_rtc_update &&
122 time_before((unsigned long)xtime.tv_sec, next_rtc_update))
123 return;
124
125 if (xtime.tv_nsec < 500000000 - ((unsigned) tick_nsec >> 1) &&
126 xtime.tv_nsec >= 500000000 + ((unsigned) tick_nsec >> 1))
127 return;
128
129 if (set_rtc())
130 /*
131 * rtc update failed. Try again in 60s
132 */
133 next_rtc_update = xtime.tv_sec + 60;
134 else
135 next_rtc_update = xtime.tv_sec + 660;
136}
137
138#define do_leds()
139
140void do_gettimeofday(struct timeval *tv)
141{
142 unsigned long flags;
143 unsigned long seq;
144 unsigned long usec, sec, lost;
145
146 do {
147 seq = read_seqbegin_irqsave(&xtime_lock, flags);
148 usec = gettimeoffset();
149
150 lost = jiffies - wall_jiffies;
151 if (lost)
152 usec += lost * USECS_PER_JIFFY;
153
154 sec = xtime.tv_sec;
155 usec += xtime.tv_nsec / 1000;
156 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
157
158 /* usec may have gone up a lot: be safe */
159 while (usec >= 1000000) {
160 usec -= 1000000;
161 sec++;
162 }
163
164 tv->tv_sec = sec;
165 tv->tv_usec = usec;
166}
167
168EXPORT_SYMBOL(do_gettimeofday);
169
170int do_settimeofday(struct timespec *tv)
171{
172 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
173 return -EINVAL;
174
175 write_seqlock_irq(&xtime_lock);
176 /*
177 * This is revolting. We need to set "xtime" correctly. However, the
178 * value in this location is the value at the most recent update of
179 * wall time. Discover what correction gettimeofday() would have
180 * done, and then undo it!
181 */
182 tv->tv_nsec -= 1000 * (gettimeoffset() +
183 (jiffies - wall_jiffies) * USECS_PER_JIFFY);
184
185 while (tv->tv_nsec < 0) {
186 tv->tv_nsec += NSEC_PER_SEC;
187 tv->tv_sec--;
188 }
189
190 xtime.tv_sec = tv->tv_sec;
191 xtime.tv_nsec = tv->tv_nsec;
192 time_adjust = 0; /* stop active adjtime() */
193 time_status |= STA_UNSYNC;
194 time_maxerror = NTP_PHASE_LIMIT;
195 time_esterror = NTP_PHASE_LIMIT;
196 write_sequnlock_irq(&xtime_lock);
197 clock_was_set();
198 return 0;
199}
200
201EXPORT_SYMBOL(do_settimeofday);
202
203static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
204{
205 do_timer(regs);
206#ifndef CONFIG_SMP
207 update_process_times(user_mode(regs));
208#endif
209 do_set_rtc(); //FIME - EVERY timer IRQ?
210 profile_tick(CPU_PROFILING, regs);
211 return IRQ_HANDLED; //FIXME - is this right?
212}
213
214static struct irqaction timer_irq = {
215 .name = "timer",
216 .flags = SA_INTERRUPT,
217 .handler = timer_interrupt,
218};
219
220extern void ioctime_init(void);
221
222/*
223 * Set up timer interrupt.
224 */
225void __init time_init(void)
226{
227 ioc_writeb(LATCH & 255, IOC_T0LTCHL);
228 ioc_writeb(LATCH >> 8, IOC_T0LTCHH);
229 ioc_writeb(0, IOC_T0GO);
230
231
232 setup_irq(IRQ_TIMER, &timer_irq);
233}
234
diff --git a/arch/arm26/kernel/traps.c b/arch/arm26/kernel/traps.c
new file mode 100644
index 000000000000..f64f59022392
--- /dev/null
+++ b/arch/arm26/kernel/traps.c
@@ -0,0 +1,548 @@
1/*
2 * linux/arch/arm26/kernel/traps.c
3 *
4 * Copyright (C) 1995-2002 Russell King
5 * Fragments that appear the same as linux/arch/i386/kernel/traps.c (C) Linus Torvalds
6 * Copyright (C) 2003 Ian Molton (ARM26)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * 'traps.c' handles hardware exceptions after we have saved some state in
13 * 'linux/arch/arm26/lib/traps.S'. Mostly a debugging aid, but will probably
14 * kill the offending process.
15 */
16
17#include <linux/module.h>
18#include <linux/config.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/signal.h>
22#include <linux/sched.h>
23#include <linux/mm.h>
24#include <linux/spinlock.h>
25#include <linux/personality.h>
26#include <linux/ptrace.h>
27#include <linux/elf.h>
28#include <linux/interrupt.h>
29#include <linux/init.h>
30
31#include <asm/atomic.h>
32#include <asm/io.h>
33#include <asm/pgtable.h>
34#include <asm/system.h>
35#include <asm/uaccess.h>
36#include <asm/unistd.h>
37#include <asm/semaphore.h>
38
39#include "ptrace.h"
40
41extern void c_backtrace (unsigned long fp, int pmode);
42extern void show_pte(struct mm_struct *mm, unsigned long addr);
43
44const char *processor_modes[] = { "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" };
45
46static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" "*bad reason*"};
47
48/*
49 * Stack pointers should always be within the kernels view of
50 * physical memory. If it is not there, then we can't dump
51 * out any information relating to the stack.
52 */
53static int verify_stack(unsigned long sp)
54{
55 if (sp < PAGE_OFFSET || (sp > (unsigned long)high_memory && high_memory != 0))
56 return -EFAULT;
57
58 return 0;
59}
60
61/*
62 * Dump out the contents of some memory nicely...
63 */
64static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
65{
66 unsigned long p = bottom & ~31;
67 mm_segment_t fs;
68 int i;
69
70 /*
71 * We need to switch to kernel mode so that we can use __get_user
72 * to safely read from kernel space. Note that we now dump the
73 * code first, just in case the backtrace kills us.
74 */
75 fs = get_fs();
76 set_fs(KERNEL_DS);
77
78 printk("%s", str);
79 printk("(0x%08lx to 0x%08lx)\n", bottom, top);
80
81 for (p = bottom & ~31; p < top;) {
82 printk("%04lx: ", p & 0xffff);
83
84 for (i = 0; i < 8; i++, p += 4) {
85 unsigned int val;
86
87 if (p < bottom || p >= top)
88 printk(" ");
89 else {
90 __get_user(val, (unsigned long *)p);
91 printk("%08x ", val);
92 }
93 }
94 printk ("\n");
95 }
96
97 set_fs(fs);
98}
99
100static void dump_instr(struct pt_regs *regs)
101{
102 unsigned long addr = instruction_pointer(regs);
103 const int width = 8;
104 mm_segment_t fs;
105 int i;
106
107 /*
108 * We need to switch to kernel mode so that we can use __get_user
109 * to safely read from kernel space. Note that we now dump the
110 * code first, just in case the backtrace kills us.
111 */
112 fs = get_fs();
113 set_fs(KERNEL_DS);
114
115 printk("Code: ");
116 for (i = -4; i < 1; i++) {
117 unsigned int val, bad;
118
119 bad = __get_user(val, &((u32 *)addr)[i]);
120
121 if (!bad)
122 printk(i == 0 ? "(%0*x) " : "%0*x ", width, val);
123 else {
124 printk("bad PC value.");
125 break;
126 }
127 }
128 printk("\n");
129
130 set_fs(fs);
131}
132
133/*static*/ void __dump_stack(struct task_struct *tsk, unsigned long sp)
134{
135 dump_mem("Stack: ", sp, 8192+(unsigned long)tsk->thread_info);
136}
137
138void dump_stack(void)
139{
140#ifdef CONFIG_DEBUG_ERRORS
141 __backtrace();
142#endif
143}
144
145EXPORT_SYMBOL(dump_stack);
146
147//FIXME - was a static fn
148void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
149{
150 unsigned int fp;
151 int ok = 1;
152
153 printk("Backtrace: ");
154 fp = regs->ARM_fp;
155 if (!fp) {
156 printk("no frame pointer");
157 ok = 0;
158 } else if (verify_stack(fp)) {
159 printk("invalid frame pointer 0x%08x", fp);
160 ok = 0;
161 } else if (fp < (unsigned long)(tsk->thread_info + 1))
162 printk("frame pointer underflow");
163 printk("\n");
164
165 if (ok)
166 c_backtrace(fp, processor_mode(regs));
167}
168
169/* FIXME - this is probably wrong.. */
170void show_stack(struct task_struct *task, unsigned long *sp) {
171 dump_mem("Stack: ", (unsigned long)sp, 8192+(unsigned long)task->thread_info);
172}
173
174DEFINE_SPINLOCK(die_lock);
175
176/*
177 * This function is protected against re-entrancy.
178 */
179NORET_TYPE void die(const char *str, struct pt_regs *regs, int err)
180{
181 struct task_struct *tsk = current;
182
183 console_verbose();
184 spin_lock_irq(&die_lock);
185
186 printk("Internal error: %s: %x\n", str, err);
187 printk("CPU: %d\n", smp_processor_id());
188 show_regs(regs);
189 printk("Process %s (pid: %d, stack limit = 0x%p)\n",
190 current->comm, current->pid, tsk->thread_info + 1);
191
192 if (!user_mode(regs) || in_interrupt()) {
193 __dump_stack(tsk, (unsigned long)(regs + 1));
194 dump_backtrace(regs, tsk);
195 dump_instr(regs);
196 }
197while(1);
198 spin_unlock_irq(&die_lock);
199 do_exit(SIGSEGV);
200}
201
202void die_if_kernel(const char *str, struct pt_regs *regs, int err)
203{
204 if (user_mode(regs))
205 return;
206
207 die(str, regs, err);
208}
209
210static DECLARE_MUTEX(undef_sem);
211static int (*undef_hook)(struct pt_regs *);
212
213int request_undef_hook(int (*fn)(struct pt_regs *))
214{
215 int ret = -EBUSY;
216
217 down(&undef_sem);
218 if (undef_hook == NULL) {
219 undef_hook = fn;
220 ret = 0;
221 }
222 up(&undef_sem);
223
224 return ret;
225}
226
227int release_undef_hook(int (*fn)(struct pt_regs *))
228{
229 int ret = -EINVAL;
230
231 down(&undef_sem);
232 if (undef_hook == fn) {
233 undef_hook = NULL;
234 ret = 0;
235 }
236 up(&undef_sem);
237
238 return ret;
239}
240
241static int undefined_extension(struct pt_regs *regs, unsigned int op)
242{
243 switch (op) {
244 case 1: /* 0xde01 / 0x?7f001f0 */
245 ptrace_break(current, regs);
246 return 0;
247 }
248 return 1;
249}
250
251asmlinkage void do_undefinstr(struct pt_regs *regs)
252{
253 siginfo_t info;
254 void *pc;
255
256 regs->ARM_pc -= 4;
257
258 pc = (unsigned long *)instruction_pointer(regs); /* strip PSR */
259
260 if (user_mode(regs)) {
261 u32 instr;
262
263 get_user(instr, (u32 *)pc);
264
265 if ((instr & 0x0fff00ff) == 0x07f000f0 &&
266 undefined_extension(regs, (instr >> 8) & 255) == 0) {
267 regs->ARM_pc += 4;
268 return;
269 }
270 } else {
271 if (undef_hook && undef_hook(regs) == 0) {
272 regs->ARM_pc += 4;
273 return;
274 }
275 }
276
277#ifdef CONFIG_DEBUG_USER
278 printk(KERN_INFO "%s (%d): undefined instruction: pc=%p\n",
279 current->comm, current->pid, pc);
280 dump_instr(regs);
281#endif
282
283 current->thread.error_code = 0;
284 current->thread.trap_no = 6;
285
286 info.si_signo = SIGILL;
287 info.si_errno = 0;
288 info.si_code = ILL_ILLOPC;
289 info.si_addr = pc;
290
291 force_sig_info(SIGILL, &info, current);
292
293 die_if_kernel("Oops - undefined instruction", regs, 0);
294}
295
296asmlinkage void do_excpt(unsigned long address, struct pt_regs *regs, int mode)
297{
298 siginfo_t info;
299
300#ifdef CONFIG_DEBUG_USER
301 printk(KERN_INFO "%s (%d): address exception: pc=%08lx\n",
302 current->comm, current->pid, instruction_pointer(regs));
303 dump_instr(regs);
304#endif
305
306 current->thread.error_code = 0;
307 current->thread.trap_no = 11;
308
309 info.si_signo = SIGBUS;
310 info.si_errno = 0;
311 info.si_code = BUS_ADRERR;
312 info.si_addr = (void *)address;
313
314 force_sig_info(SIGBUS, &info, current);
315
316 die_if_kernel("Oops - address exception", regs, mode);
317}
318
319asmlinkage void do_unexp_fiq (struct pt_regs *regs)
320{
321#ifndef CONFIG_IGNORE_FIQ
322 printk("Hmm. Unexpected FIQ received, but trying to continue\n");
323 printk("You may have a hardware problem...\n");
324#endif
325}
326
327/*
328 * bad_mode handles the impossible case in the vectors. If you see one of
329 * these, then it's extremely serious, and could mean you have buggy hardware.
330 * It never returns, and never tries to sync. We hope that we can at least
331 * dump out some state information...
332 */
333asmlinkage void bad_mode(struct pt_regs *regs, int reason, int proc_mode)
334{
335 unsigned int vectors = vectors_base();
336
337 console_verbose();
338
339 printk(KERN_CRIT "Bad mode in %s handler detected: mode %s\n",
340 handler[reason<5?reason:4], processor_modes[proc_mode]);
341
342 /*
343 * Dump out the vectors and stub routines. Maybe a better solution
344 * would be to dump them out only if we detect that they are corrupted.
345 */
346 dump_mem(KERN_CRIT "Vectors: ", vectors, vectors + 0x40);
347 dump_mem(KERN_CRIT "Stubs: ", vectors + 0x200, vectors + 0x4b8);
348
349 die("Oops", regs, 0);
350 local_irq_disable();
351 panic("bad mode");
352}
353
354static int bad_syscall(int n, struct pt_regs *regs)
355{
356 struct thread_info *thread = current_thread_info();
357 siginfo_t info;
358
359 if (current->personality != PER_LINUX && thread->exec_domain->handler) {
360 thread->exec_domain->handler(n, regs);
361 return regs->ARM_r0;
362 }
363
364#ifdef CONFIG_DEBUG_USER
365 printk(KERN_ERR "[%d] %s: obsolete system call %08x.\n",
366 current->pid, current->comm, n);
367 dump_instr(regs);
368#endif
369
370 info.si_signo = SIGILL;
371 info.si_errno = 0;
372 info.si_code = ILL_ILLTRP;
373 info.si_addr = (void *)instruction_pointer(regs) - 4;
374
375 force_sig_info(SIGILL, &info, current);
376 die_if_kernel("Oops", regs, n);
377 return regs->ARM_r0;
378}
379
380static inline void
381do_cache_op(unsigned long start, unsigned long end, int flags)
382{
383 struct vm_area_struct *vma;
384
385 if (end < start)
386 return;
387
388 vma = find_vma(current->active_mm, start);
389 if (vma && vma->vm_start < end) {
390 if (start < vma->vm_start)
391 start = vma->vm_start;
392 if (end > vma->vm_end)
393 end = vma->vm_end;
394 }
395}
396
397/*
398 * Handle all unrecognised system calls.
399 * 0x9f0000 - 0x9fffff are some more esoteric system calls
400 */
401#define NR(x) ((__ARM_NR_##x) - __ARM_NR_BASE)
402asmlinkage int arm_syscall(int no, struct pt_regs *regs)
403{
404 siginfo_t info;
405
406 if ((no >> 16) != 0x9f)
407 return bad_syscall(no, regs);
408
409 switch (no & 0xffff) {
410 case 0: /* branch through 0 */
411 info.si_signo = SIGSEGV;
412 info.si_errno = 0;
413 info.si_code = SEGV_MAPERR;
414 info.si_addr = NULL;
415
416 force_sig_info(SIGSEGV, &info, current);
417
418 die_if_kernel("branch through zero", regs, 0);
419 return 0;
420
421 case NR(breakpoint): /* SWI BREAK_POINT */
422 ptrace_break(current, regs);
423 return regs->ARM_r0;
424
425 case NR(cacheflush):
426 return 0;
427
428 case NR(usr26):
429 break;
430
431 default:
432 /* Calls 9f00xx..9f07ff are defined to return -ENOSYS
433 if not implemented, rather than raising SIGILL. This
434 way the calling program can gracefully determine whether
435 a feature is supported. */
436 if (no <= 0x7ff)
437 return -ENOSYS;
438 break;
439 }
440#ifdef CONFIG_DEBUG_USER
441 /*
442 * experience shows that these seem to indicate that
443 * something catastrophic has happened
444 */
445 printk("[%d] %s: arm syscall %d\n", current->pid, current->comm, no);
446 dump_instr(regs);
447 if (user_mode(regs)) {
448 show_regs(regs);
449 c_backtrace(regs->ARM_fp, processor_mode(regs));
450 }
451#endif
452 info.si_signo = SIGILL;
453 info.si_errno = 0;
454 info.si_code = ILL_ILLTRP;
455 info.si_addr = (void *)instruction_pointer(regs) - 4;
456
457 force_sig_info(SIGILL, &info, current);
458 die_if_kernel("Oops", regs, no);
459 return 0;
460}
461
462void __bad_xchg(volatile void *ptr, int size)
463{
464 printk("xchg: bad data size: pc 0x%p, ptr 0x%p, size %d\n",
465 __builtin_return_address(0), ptr, size);
466 BUG();
467}
468
469/*
470 * A data abort trap was taken, but we did not handle the instruction.
471 * Try to abort the user program, or panic if it was the kernel.
472 */
473asmlinkage void
474baddataabort(int code, unsigned long instr, struct pt_regs *regs)
475{
476 unsigned long addr = instruction_pointer(regs);
477 siginfo_t info;
478
479#ifdef CONFIG_DEBUG_USER
480 printk(KERN_ERR "[%d] %s: bad data abort: code %d instr 0x%08lx\n",
481 current->pid, current->comm, code, instr);
482 dump_instr(regs);
483 show_pte(current->mm, addr);
484#endif
485
486 info.si_signo = SIGILL;
487 info.si_errno = 0;
488 info.si_code = ILL_ILLOPC;
489 info.si_addr = (void *)addr;
490
491 force_sig_info(SIGILL, &info, current);
492 die_if_kernel("unknown data abort code", regs, instr);
493}
494
495volatile void __bug(const char *file, int line, void *data)
496{
497 printk(KERN_CRIT"kernel BUG at %s:%d!", file, line);
498 if (data)
499 printk(KERN_CRIT" - extra data = %p", data);
500 printk("\n");
501 *(int *)0 = 0;
502}
503
504void __readwrite_bug(const char *fn)
505{
506 printk("%s called, but not implemented", fn);
507 BUG();
508}
509
510void __pte_error(const char *file, int line, unsigned long val)
511{
512 printk("%s:%d: bad pte %08lx.\n", file, line, val);
513}
514
515void __pmd_error(const char *file, int line, unsigned long val)
516{
517 printk("%s:%d: bad pmd %08lx.\n", file, line, val);
518}
519
520void __pgd_error(const char *file, int line, unsigned long val)
521{
522 printk("%s:%d: bad pgd %08lx.\n", file, line, val);
523}
524
525asmlinkage void __div0(void)
526{
527 printk("Division by zero in kernel.\n");
528 dump_stack();
529}
530
531void abort(void)
532{
533 BUG();
534
535 /* if that doesn't kill us, halt */
536 panic("Oops failed to kill thread");
537}
538
539void __init trap_init(void)
540{
541 extern void __trap_init(unsigned long);
542 unsigned long base = vectors_base();
543
544 __trap_init(base);
545 if (base != 0)
546 printk(KERN_DEBUG "Relocating machine vectors to 0x%08lx\n",
547 base);
548}
diff --git a/arch/arm26/kernel/vmlinux-arm26-xip.lds.in b/arch/arm26/kernel/vmlinux-arm26-xip.lds.in
new file mode 100644
index 000000000000..ca61ec8218fe
--- /dev/null
+++ b/arch/arm26/kernel/vmlinux-arm26-xip.lds.in
@@ -0,0 +1,134 @@
1/* ld script to make ARM Linux kernel
2 * taken from the i386 version by Russell King
3 * Written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>
4 * borrowed from Russels ARM port by Ian Molton
5 */
6
7#include <asm-generic/vmlinux.lds.h>
8
9OUTPUT_ARCH(arm)
10ENTRY(stext)
11jiffies = jiffies_64;
12SECTIONS
13{
14 . = TEXTADDR;
15 .init : { /* Init code and data */
16 _stext = .;
17 __init_begin = .;
18 _sinittext = .;
19 *(.init.text)
20 _einittext = .;
21 __proc_info_begin = .;
22 *(.proc.info)
23 __proc_info_end = .;
24 __arch_info_begin = .;
25 *(.arch.info)
26 __arch_info_end = .;
27 __tagtable_begin = .;
28 *(.taglist)
29 __tagtable_end = .;
30 . = ALIGN(16);
31 __setup_start = .;
32 *(.init.setup)
33 __setup_end = .;
34 __early_begin = .;
35 *(__early_param)
36 __early_end = .;
37 __initcall_start = .;
38 *(.initcall1.init)
39 *(.initcall2.init)
40 *(.initcall3.init)
41 *(.initcall4.init)
42 *(.initcall5.init)
43 *(.initcall6.init)
44 *(.initcall7.init)
45 __initcall_end = .;
46 __con_initcall_start = .;
47 *(.con_initcall.init)
48 __con_initcall_end = .;
49 . = ALIGN(32);
50 __initramfs_start = .;
51 usr/built-in.o(.init.ramfs)
52 __initramfs_end = .;
53 . = ALIGN(32768);
54 __init_end = .;
55 }
56
57 /DISCARD/ : { /* Exit code and data */
58 *(.exit.text)
59 *(.exit.data)
60 *(.exitcall.exit)
61 }
62
63 .text : { /* Real text segment */
64 _text = .; /* Text and read-only data */
65 *(.text)
66 SCHED_TEXT
67 LOCK_TEXT /* FIXME - borrowed from arm32 - check*/
68 *(.fixup)
69 *(.gnu.warning)
70 *(.rodata)
71 *(.rodata.*)
72 *(.glue_7)
73 *(.glue_7t)
74 *(.got) /* Global offset table */
75
76 _etext = .; /* End of text section */
77 }
78
79 . = ALIGN(16);
80 __ex_table : { /* Exception table */
81 __start___ex_table = .;
82 *(__ex_table)
83 __stop___ex_table = .;
84 }
85
86 RODATA
87
88 _endtext = .;
89
90 . = DATAADDR;
91
92 _sdata = .;
93
94 .data : {
95 . = ALIGN(8192);
96 /*
97 * first, the init thread union, aligned
98 * to an 8192 byte boundary. (see arm26/kernel/init_task.c)
99 * FIXME - sould this be 32K aligned on arm26?
100 */
101 *(.init.task)
102
103 /*
104 * The cacheline aligned data
105 */
106 . = ALIGN(32);
107 *(.data.cacheline_aligned)
108
109 /*
110 * and the usual data section
111 */
112 *(.data)
113 CONSTRUCTORS
114
115 *(.init.data)
116
117 _edata = .;
118 }
119
120 .bss : {
121 __bss_start = .; /* BSS */
122 *(.bss)
123 *(COMMON)
124 _end = . ;
125 }
126 /* Stabs debugging sections. */
127 .stab 0 : { *(.stab) }
128 .stabstr 0 : { *(.stabstr) }
129 .stab.excl 0 : { *(.stab.excl) }
130 .stab.exclstr 0 : { *(.stab.exclstr) }
131 .stab.index 0 : { *(.stab.index) }
132 .stab.indexstr 0 : { *(.stab.indexstr) }
133 .comment 0 : { *(.comment) }
134}
diff --git a/arch/arm26/kernel/vmlinux-arm26.lds.in b/arch/arm26/kernel/vmlinux-arm26.lds.in
new file mode 100644
index 000000000000..d1d3418d7eb6
--- /dev/null
+++ b/arch/arm26/kernel/vmlinux-arm26.lds.in
@@ -0,0 +1,127 @@
1/* ld script to make ARM Linux kernel
2 * taken from the i386 version by Russell King
3 * Written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>
4 * borrowed from Russels ARM port by Ian Molton and subsequently modified.
5 */
6
7#include <asm-generic/vmlinux.lds.h>
8
9OUTPUT_ARCH(arm)
10ENTRY(stext)
11jiffies = jiffies_64;
12SECTIONS
13{
14 . = TEXTADDR;
15 .init : { /* Init code and data */
16 _stext = .;
17 __init_begin = .;
18 _sinittext = .;
19 *(.init.text)
20 _einittext = .;
21 __proc_info_begin = .;
22 *(.proc.info)
23 __proc_info_end = .;
24 __arch_info_begin = .;
25 *(.arch.info)
26 __arch_info_end = .;
27 __tagtable_begin = .;
28 *(.taglist)
29 __tagtable_end = .;
30 *(.init.data)
31 . = ALIGN(16);
32 __setup_start = .;
33 *(.init.setup)
34 __setup_end = .;
35 __early_begin = .;
36 *(__early_param)
37 __early_end = .;
38 __initcall_start = .;
39 *(.initcall1.init)
40 *(.initcall2.init)
41 *(.initcall3.init)
42 *(.initcall4.init)
43 *(.initcall5.init)
44 *(.initcall6.init)
45 *(.initcall7.init)
46 __initcall_end = .;
47 __con_initcall_start = .;
48 *(.con_initcall.init)
49 __con_initcall_end = .;
50 . = ALIGN(32);
51 __initramfs_start = .;
52 usr/built-in.o(.init.ramfs)
53 __initramfs_end = .;
54 . = ALIGN(32768);
55 __init_end = .;
56 }
57
58 /DISCARD/ : { /* Exit code and data */
59 *(.exit.text)
60 *(.exit.data)
61 *(.exitcall.exit)
62 }
63
64 .text : { /* Real text segment */
65 _text = .; /* Text and read-only data */
66 *(.text)
67 SCHED_TEXT
68 LOCK_TEXT
69 *(.fixup)
70 *(.gnu.warning)
71 *(.rodata)
72 *(.rodata.*)
73 *(.glue_7)
74 *(.glue_7t)
75 *(.got) /* Global offset table */
76
77 _etext = .; /* End of text section */
78 }
79
80 . = ALIGN(16);
81 __ex_table : { /* Exception table */
82 __start___ex_table = .;
83 *(__ex_table)
84 __stop___ex_table = .;
85 }
86
87 RODATA
88
89 . = ALIGN(8192);
90
91 .data : {
92 /*
93 * first, the init task union, aligned
94 * to an 8192 byte boundary. (see arm26/kernel/init_task.c)
95 */
96 *(.init.task)
97
98 /*
99 * The cacheline aligned data
100 */
101 . = ALIGN(32);
102 *(.data.cacheline_aligned)
103
104 /*
105 * and the usual data section
106 */
107 *(.data)
108 CONSTRUCTORS
109
110 _edata = .;
111 }
112
113 .bss : {
114 __bss_start = .; /* BSS */
115 *(.bss)
116 *(COMMON)
117 _end = . ;
118 }
119 /* Stabs debugging sections. */
120 .stab 0 : { *(.stab) }
121 .stabstr 0 : { *(.stabstr) }
122 .stab.excl 0 : { *(.stab.excl) }
123 .stab.exclstr 0 : { *(.stab.exclstr) }
124 .stab.index 0 : { *(.stab.index) }
125 .stab.indexstr 0 : { *(.stab.indexstr) }
126 .comment 0 : { *(.comment) }
127}
diff --git a/arch/arm26/kernel/vmlinux.lds.S b/arch/arm26/kernel/vmlinux.lds.S
new file mode 100644
index 000000000000..811a69048010
--- /dev/null
+++ b/arch/arm26/kernel/vmlinux.lds.S
@@ -0,0 +1,12 @@
1#include <linux/config.h>
2
3#ifdef CONFIG_XIP_KERNEL
4
5#include "vmlinux-arm26-xip.lds.in"
6
7#else
8
9#include "vmlinux-arm26.lds.in"
10
11#endif
12
diff --git a/arch/arm26/lib/Makefile b/arch/arm26/lib/Makefile
new file mode 100644
index 000000000000..6df2b793d367
--- /dev/null
+++ b/arch/arm26/lib/Makefile
@@ -0,0 +1,26 @@
1#
2# linux/arch/arm26/lib/Makefile
3#
4# Copyright (C) 1995-2000 Russell King
5#
6
7lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \
8 csumpartialcopy.o csumpartialcopyuser.o clearbit.o \
9 copy_page.o delay.o findbit.o memchr.o memcpy.o \
10 memset.o memzero.o setbit.o \
11 strchr.o strrchr.o testchangebit.o \
12 testclearbit.o testsetbit.o getuser.o \
13 putuser.o ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
14 ucmpdi2.o udivdi3.o lib1funcs.o ecard.o io-acorn.o \
15 floppydma.o io-readsb.o io-writesb.o io-writesl.o \
16 uaccess-kernel.o uaccess-user.o io-readsw.o \
17 io-writesw.o io-readsl.o ecard.o io-acorn.o \
18 floppydma.o
19
20lib-n :=
21
22lib-$(CONFIG_VT)+= kbd.o
23
24csumpartialcopy.o: csumpartialcopygeneric.S
25csumpartialcopyuser.o: csumpartialcopygeneric.S
26
diff --git a/arch/arm26/lib/ashldi3.c b/arch/arm26/lib/ashldi3.c
new file mode 100644
index 000000000000..130f5a839669
--- /dev/null
+++ b/arch/arm26/lib/ashldi3.c
@@ -0,0 +1,61 @@
1/* More subroutines needed by GCC output code on some machines. */
2/* Compile this one with gcc. */
3/* Copyright (C) 1989, 92-98, 1999 Free Software Foundation, Inc.
4
5This file is part of GNU CC.
6
7GNU CC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12GNU CC is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GNU CC; see the file COPYING. If not, write to
19the Free Software Foundation, 59 Temple Place - Suite 330,
20Boston, MA 02111-1307, USA. */
21
22/* As a special exception, if you link this library with other files,
23 some of which are compiled with GCC, to produce an executable,
24 this library does not by itself cause the resulting executable
25 to be covered by the GNU General Public License.
26 This exception does not however invalidate any other reasons why
27 the executable file might be covered by the GNU General Public License.
28 */
29/* support functions required by the kernel. based on code from gcc-2.95.3 */
30/* I Molton 29/07/01 */
31
32#include "gcclib.h"
33
34DItype
35__ashldi3 (DItype u, word_type b)
36{
37 DIunion w;
38 word_type bm;
39 DIunion uu;
40
41 if (b == 0)
42 return u;
43
44 uu.ll = u;
45
46 bm = (sizeof (SItype) * BITS_PER_UNIT) - b;
47 if (bm <= 0)
48 {
49 w.s.low = 0;
50 w.s.high = (USItype)uu.s.low << -bm;
51 }
52 else
53 {
54 USItype carries = (USItype)uu.s.low >> bm;
55 w.s.low = (USItype)uu.s.low << b;
56 w.s.high = ((USItype)uu.s.high << b) | carries;
57 }
58
59 return w.ll;
60}
61
diff --git a/arch/arm26/lib/ashrdi3.c b/arch/arm26/lib/ashrdi3.c
new file mode 100644
index 000000000000..71625d218f8d
--- /dev/null
+++ b/arch/arm26/lib/ashrdi3.c
@@ -0,0 +1,61 @@
1/* More subroutines needed by GCC output code on some machines. */
2/* Compile this one with gcc. */
3/* Copyright (C) 1989, 92-98, 1999 Free Software Foundation, Inc.
4
5This file is part of GNU CC.
6
7GNU CC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12GNU CC is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GNU CC; see the file COPYING. If not, write to
19the Free Software Foundation, 59 Temple Place - Suite 330,
20Boston, MA 02111-1307, USA. */
21
22/* As a special exception, if you link this library with other files,
23 some of which are compiled with GCC, to produce an executable,
24 this library does not by itself cause the resulting executable
25 to be covered by the GNU General Public License.
26 This exception does not however invalidate any other reasons why
27 the executable file might be covered by the GNU General Public License.
28 */
29/* support functions required by the kernel. based on code from gcc-2.95.3 */
30/* I Molton 29/07/01 */
31
32#include "gcclib.h"
33
34DItype
35__ashrdi3 (DItype u, word_type b)
36{
37 DIunion w;
38 word_type bm;
39 DIunion uu;
40
41 if (b == 0)
42 return u;
43
44 uu.ll = u;
45
46 bm = (sizeof (SItype) * BITS_PER_UNIT) - b;
47 if (bm <= 0)
48 {
49 /* w.s.high = 1..1 or 0..0 */
50 w.s.high = uu.s.high >> (sizeof (SItype) * BITS_PER_UNIT - 1);
51 w.s.low = uu.s.high >> -bm;
52 }
53 else
54 {
55 USItype carries = (USItype)uu.s.high << bm;
56 w.s.high = uu.s.high >> b;
57 w.s.low = ((USItype)uu.s.low >> b) | carries;
58 }
59
60 return w.ll;
61}
diff --git a/arch/arm26/lib/backtrace.S b/arch/arm26/lib/backtrace.S
new file mode 100644
index 000000000000..d793fe4339fc
--- /dev/null
+++ b/arch/arm26/lib/backtrace.S
@@ -0,0 +1,145 @@
1/*
2 * linux/arch/arm26/lib/backtrace.S
3 *
4 * Copyright (C) 1995, 1996 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/config.h>
11#include <linux/linkage.h>
12#include <asm/assembler.h>
13 .text
14
15@ fp is 0 or stack frame
16
17#define frame r4
18#define next r5
19#define save r6
20#define mask r7
21#define offset r8
22
23ENTRY(__backtrace)
24 mov r1, #0x10
25 mov r0, fp
26
27ENTRY(c_backtrace)
28
29#ifdef CONFIG_NO_FRAME_POINTER
30 mov pc, lr
31#else
32
33 stmfd sp!, {r4 - r8, lr} @ Save an extra register so we have a location...
34 mov mask, #0xfc000003
35 tst mask, r0
36 movne r0, #0
37 movs frame, r0
381: moveq r0, #-2
39 LOADREGS(eqfd, sp!, {r4 - r8, pc})
40
412: stmfd sp!, {pc} @ calculate offset of PC in STMIA instruction
42 ldr r0, [sp], #4
43 adr r1, 2b - 4
44 sub offset, r0, r1
45
463: tst frame, mask @ Check for address exceptions...
47 bne 1b
48
491001: ldr next, [frame, #-12] @ get fp
501002: ldr r2, [frame, #-4] @ get lr
511003: ldr r3, [frame, #0] @ get pc
52 sub save, r3, offset @ Correct PC for prefetching
53 bic save, save, mask
541004: ldr r1, [save, #0] @ get instruction at function
55 mov r1, r1, lsr #10
56 ldr r3, .Ldsi+4
57 teq r1, r3
58 subeq save, save, #4
59 adr r0, .Lfe
60 mov r1, save
61 bic r2, r2, mask
62 bl printk @ print pc and link register
63
64 ldr r0, [frame, #-8] @ get sp
65 sub r0, r0, #4
661005: ldr r1, [save, #4] @ get instruction at function+4
67 mov r3, r1, lsr #10
68 ldr r2, .Ldsi+4
69 teq r3, r2 @ Check for stmia sp!, {args}
70 addeq save, save, #4 @ next instruction
71 bleq .Ldumpstm
72
73 sub r0, frame, #16
741006: ldr r1, [save, #4] @ Get 'stmia sp!, {rlist, fp, ip, lr, pc}' instruction
75 mov r3, r1, lsr #10
76 ldr r2, .Ldsi
77 teq r3, r2
78 bleq .Ldumpstm
79
80 teq frame, next
81 movne frame, next
82 teqne frame, #0
83 bne 3b
84 LOADREGS(fd, sp!, {r4 - r8, pc})
85
86/*
87 * Fixup for LDMDB
88 */
89 .section .fixup,"ax"
90 .align 0
911007: ldr r0, =.Lbad
92 mov r1, frame
93 bl printk
94 LOADREGS(fd, sp!, {r4 - r8, pc})
95 .ltorg
96 .previous
97
98 .section __ex_table,"a"
99 .align 3
100 .long 1001b, 1007b
101 .long 1002b, 1007b
102 .long 1003b, 1007b
103 .long 1004b, 1007b
104 .long 1005b, 1007b
105 .long 1006b, 1007b
106 .previous
107
108#define instr r4
109#define reg r5
110#define stack r6
111
112.Ldumpstm: stmfd sp!, {instr, reg, stack, r7, lr}
113 mov stack, r0
114 mov instr, r1
115 mov reg, #9
116 mov r7, #0
1171: mov r3, #1
118 tst instr, r3, lsl reg
119 beq 2f
120 add r7, r7, #1
121 teq r7, #4
122 moveq r7, #0
123 moveq r3, #'\n'
124 movne r3, #' '
125 ldr r2, [stack], #-4
126 mov r1, reg
127 adr r0, .Lfp
128 bl printk
1292: subs reg, reg, #1
130 bpl 1b
131 teq r7, #0
132 adrne r0, .Lcr
133 blne printk
134 mov r0, stack
135 LOADREGS(fd, sp!, {instr, reg, stack, r7, pc})
136
137.Lfe: .asciz "Function entered at [<%p>] from [<%p>]\n"
138.Lfp: .asciz " r%d = %08X%c"
139.Lcr: .asciz "\n"
140.Lbad: .asciz "Backtrace aborted due to bad frame pointer <%p>\n"
141 .align
142.Ldsi: .word 0x00e92dd8 >> 2
143 .word 0x00e92d00 >> 2
144
145#endif
diff --git a/arch/arm26/lib/changebit.S b/arch/arm26/lib/changebit.S
new file mode 100644
index 000000000000..1b6a077be5a6
--- /dev/null
+++ b/arch/arm26/lib/changebit.S
@@ -0,0 +1,28 @@
1/*
2 * linux/arch/arm26/lib/changebit.S
3 *
4 * Copyright (C) 1995-1996 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12 .text
13
14/* Purpose : Function to change a bit
15 * Prototype: int change_bit(int bit, void *addr)
16 */
17ENTRY(_change_bit_be)
18 eor r0, r0, #0x18 @ big endian byte ordering
19ENTRY(_change_bit_le)
20 and r2, r0, #7
21 mov r3, #1
22 mov r3, r3, lsl r2
23 save_and_disable_irqs ip, r2
24 ldrb r2, [r1, r0, lsr #3]
25 eor r2, r2, r3
26 strb r2, [r1, r0, lsr #3]
27 restore_irqs ip
28 RETINSTR(mov,pc,lr)
diff --git a/arch/arm26/lib/clearbit.S b/arch/arm26/lib/clearbit.S
new file mode 100644
index 000000000000..0a895b0c759f
--- /dev/null
+++ b/arch/arm26/lib/clearbit.S
@@ -0,0 +1,31 @@
1/*
2 * linux/arch/arm26/lib/clearbit.S
3 *
4 * Copyright (C) 1995-1996 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12 .text
13
14/*
15 * Purpose : Function to clear a bit
16 * Prototype: int clear_bit(int bit, void *addr)
17 */
18ENTRY(_clear_bit_be)
19 eor r0, r0, #0x18 @ big endian byte ordering
20ENTRY(_clear_bit_le)
21 and r2, r0, #7
22 mov r3, #1
23 mov r3, r3, lsl r2
24 save_and_disable_irqs ip, r2
25 ldrb r2, [r1, r0, lsr #3]
26 bic r2, r2, r3
27 strb r2, [r1, r0, lsr #3]
28 restore_irqs ip
29 RETINSTR(mov,pc,lr)
30
31
diff --git a/arch/arm26/lib/copy_page.S b/arch/arm26/lib/copy_page.S
new file mode 100644
index 000000000000..2d79ee12ea1f
--- /dev/null
+++ b/arch/arm26/lib/copy_page.S
@@ -0,0 +1,62 @@
1/*
2 * linux/arch/arm26/lib/copypage.S
3 *
4 * Copyright (C) 1995-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * ASM optimised string functions
11 */
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14#include <asm/asm_offsets.h>
15
16 .text
17 .align 5
18/*
19 * ARMv3 optimised copy_user_page
20 *
21 * FIXME: rmk do we need to handle cache stuff...
22 * FIXME: im is this right on ARM26?
23 */
24ENTRY(__copy_user_page)
25 stmfd sp!, {r4, lr} @ 2
26 mov r2, #PAGE_SZ/64 @ 1
27 ldmia r1!, {r3, r4, ip, lr} @ 4+1
281: stmia r0!, {r3, r4, ip, lr} @ 4
29 ldmia r1!, {r3, r4, ip, lr} @ 4+1
30 stmia r0!, {r3, r4, ip, lr} @ 4
31 ldmia r1!, {r3, r4, ip, lr} @ 4+1
32 stmia r0!, {r3, r4, ip, lr} @ 4
33 ldmia r1!, {r3, r4, ip, lr} @ 4
34 subs r2, r2, #1 @ 1
35 stmia r0!, {r3, r4, ip, lr} @ 4
36 ldmneia r1!, {r3, r4, ip, lr} @ 4
37 bne 1b @ 1
38 LOADREGS(fd, sp!, {r4, pc}) @ 3
39
40 .align 5
41/*
42 * ARMv3 optimised clear_user_page
43 *
44 * FIXME: rmk do we need to handle cache stuff...
45 */
46ENTRY(__clear_user_page)
47 str lr, [sp, #-4]!
48 mov r1, #PAGE_SZ/64 @ 1
49 mov r2, #0 @ 1
50 mov r3, #0 @ 1
51 mov ip, #0 @ 1
52 mov lr, #0 @ 1
531: stmia r0!, {r2, r3, ip, lr} @ 4
54 stmia r0!, {r2, r3, ip, lr} @ 4
55 stmia r0!, {r2, r3, ip, lr} @ 4
56 stmia r0!, {r2, r3, ip, lr} @ 4
57 subs r1, r1, #1 @ 1
58 bne 1b @ 1
59 ldr pc, [sp], #4
60
61 .section ".init.text", #alloc, #execinstr
62
diff --git a/arch/arm26/lib/csumipv6.S b/arch/arm26/lib/csumipv6.S
new file mode 100644
index 000000000000..62831155acde
--- /dev/null
+++ b/arch/arm26/lib/csumipv6.S
@@ -0,0 +1,32 @@
1/*
2 * linux/arch/arm26/lib/csumipv6.S
3 *
4 * Copyright (C) 1995-1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12
13 .text
14
15ENTRY(__csum_ipv6_magic)
16 str lr, [sp, #-4]!
17 adds ip, r2, r3
18 ldmia r1, {r1 - r3, lr}
19 adcs ip, ip, r1
20 adcs ip, ip, r2
21 adcs ip, ip, r3
22 adcs ip, ip, lr
23 ldmia r0, {r0 - r3}
24 adcs r0, ip, r0
25 adcs r0, r0, r1
26 adcs r0, r0, r2
27 ldr r2, [sp, #4]
28 adcs r0, r0, r3
29 adcs r0, r0, r2
30 adcs r0, r0, #0
31 LOADREGS(fd, sp!, {pc})
32
diff --git a/arch/arm26/lib/csumpartial.S b/arch/arm26/lib/csumpartial.S
new file mode 100644
index 000000000000..e53e7109e623
--- /dev/null
+++ b/arch/arm26/lib/csumpartial.S
@@ -0,0 +1,130 @@
1/*
2 * linux/arch/arm26/lib/csumpartial.S
3 *
4 * Copyright (C) 1995-1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12
13 .text
14
15/*
16 * Function: __u32 csum_partial(const char *src, int len, __u32 sum)
17 * Params : r0 = buffer, r1 = len, r2 = checksum
18 * Returns : r0 = new checksum
19 */
20
21buf .req r0
22len .req r1
23sum .req r2
24td0 .req r3
25td1 .req r4 @ save before use
26td2 .req r5 @ save before use
27td3 .req lr
28
29.zero: mov r0, sum
30 add sp, sp, #4
31 ldr pc, [sp], #4
32
33 /*
34 * Handle 0 to 7 bytes, with any alignment of source and
35 * destination pointers. Note that when we get here, C = 0
36 */
37.less8: teq len, #0 @ check for zero count
38 beq .zero
39
40 /* we must have at least one byte. */
41 tst buf, #1 @ odd address?
42 ldrneb td0, [buf], #1
43 subne len, len, #1
44 adcnes sum, sum, td0, lsl #byte(1)
45
46.less4: tst len, #6
47 beq .less8_byte
48
49 /* we are now half-word aligned */
50
51.less8_wordlp:
52#if __LINUX_ARM_ARCH__ >= 4
53 ldrh td0, [buf], #2
54 sub len, len, #2
55#else
56 ldrb td0, [buf], #1
57 ldrb td3, [buf], #1
58 sub len, len, #2
59 orr td0, td0, td3, lsl #8
60#endif
61 adcs sum, sum, td0
62 tst len, #6
63 bne .less8_wordlp
64
65.less8_byte: tst len, #1 @ odd number of bytes
66 ldrneb td0, [buf], #1 @ include last byte
67 adcnes sum, sum, td0, lsl #byte(0) @ update checksum
68
69.done: adc r0, sum, #0 @ collect up the last carry
70 ldr td0, [sp], #4
71 tst td0, #1 @ check buffer alignment
72 movne td0, r0, lsl #8 @ rotate checksum by 8 bits
73 orrne r0, td0, r0, lsr #24
74 ldr pc, [sp], #4 @ return
75
76.not_aligned: tst buf, #1 @ odd address
77 ldrneb td0, [buf], #1 @ make even
78 subne len, len, #1
79 adcnes sum, sum, td0, lsl #byte(1) @ update checksum
80
81 tst buf, #2 @ 32-bit aligned?
82#if __LINUX_ARM_ARCH__ >= 4
83 ldrneh td0, [buf], #2 @ make 32-bit aligned
84 subne len, len, #2
85#else
86 ldrneb td0, [buf], #1
87 ldrneb ip, [buf], #1
88 subne len, len, #2
89 orrne td0, td0, ip, lsl #8
90#endif
91 adcnes sum, sum, td0 @ update checksum
92 mov pc, lr
93
94ENTRY(csum_partial)
95 stmfd sp!, {buf, lr}
96 cmp len, #8 @ Ensure that we have at least
97 blo .less8 @ 8 bytes to copy.
98
99 adds sum, sum, #0 @ C = 0
100 tst buf, #3 @ Test destination alignment
101 blne .not_aligned @ aligh destination, return here
102
1031: bics ip, len, #31
104 beq 3f
105
106 stmfd sp!, {r4 - r5}
1072: ldmia buf!, {td0, td1, td2, td3}
108 adcs sum, sum, td0
109 adcs sum, sum, td1
110 adcs sum, sum, td2
111 adcs sum, sum, td3
112 ldmia buf!, {td0, td1, td2, td3}
113 adcs sum, sum, td0
114 adcs sum, sum, td1
115 adcs sum, sum, td2
116 adcs sum, sum, td3
117 sub ip, ip, #32
118 teq ip, #0
119 bne 2b
120 ldmfd sp!, {r4 - r5}
121
1223: tst len, #0x1c @ should not change C
123 beq .less4
124
1254: ldr td0, [buf], #4
126 sub len, len, #4
127 adcs sum, sum, td0
128 tst len, #0x1c
129 bne 4b
130 b .less4
diff --git a/arch/arm26/lib/csumpartialcopy.S b/arch/arm26/lib/csumpartialcopy.S
new file mode 100644
index 000000000000..a1c4b5fdd498
--- /dev/null
+++ b/arch/arm26/lib/csumpartialcopy.S
@@ -0,0 +1,52 @@
1/*
2 * linux/arch/arm26/lib/csumpartialcopy.S
3 *
4 * Copyright (C) 1995-1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12
13 .text
14
15/* Function: __u32 csum_partial_copy_nocheck(const char *src, char *dst, int len, __u32 sum)
16 * Params : r0 = src, r1 = dst, r2 = len, r3 = checksum
17 * Returns : r0 = new checksum
18 */
19
20 .macro save_regs
21 stmfd sp!, {r1, r4 - r8, fp, ip, lr, pc}
22 .endm
23
24 .macro load_regs,flags
25 LOADREGS(\flags,fp,{r1, r4 - r8, fp, sp, pc})
26 .endm
27
28 .macro load1b, reg1
29 ldrb \reg1, [r0], #1
30 .endm
31
32 .macro load2b, reg1, reg2
33 ldrb \reg1, [r0], #1
34 ldrb \reg2, [r0], #1
35 .endm
36
37 .macro load1l, reg1
38 ldr \reg1, [r0], #4
39 .endm
40
41 .macro load2l, reg1, reg2
42 ldr \reg1, [r0], #4
43 ldr \reg2, [r0], #4
44 .endm
45
46 .macro load4l, reg1, reg2, reg3, reg4
47 ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
48 .endm
49
50#define FN_ENTRY ENTRY(csum_partial_copy_nocheck)
51
52#include "csumpartialcopygeneric.S"
diff --git a/arch/arm26/lib/csumpartialcopygeneric.S b/arch/arm26/lib/csumpartialcopygeneric.S
new file mode 100644
index 000000000000..5249c3ad11db
--- /dev/null
+++ b/arch/arm26/lib/csumpartialcopygeneric.S
@@ -0,0 +1,352 @@
1/*
2 * linux/arch/arm26/lib/csumpartialcopygeneric.S
3 *
4 * Copyright (C) 1995-2001 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * JMA 01/06/03 Commented out some shl0s; probobly irrelevant to arm26
11 *
12 */
13
14/*
15 * unsigned int
16 * csum_partial_copy_xxx(const char *src, char *dst, int len, int sum, )
17 * r0 = src, r1 = dst, r2 = len, r3 = sum
18 * Returns : r0 = checksum
19 *
20 * Note that 'tst' and 'teq' preserve the carry flag.
21 */
22
23/* Quick hack */
24 .macro save_regs
25 stmfd sp!, {r1, r4 - r8, fp, ip, lr, pc}
26 .endm
27
28/* end Quick Hack */
29
30src .req r0
31dst .req r1
32len .req r2
33sum .req r3
34
35.zero: mov r0, sum
36 load_regs ea
37
38 /*
39 * Align an unaligned destination pointer. We know that
40 * we have >= 8 bytes here, so we don't need to check
41 * the length. Note that the source pointer hasn't been
42 * aligned yet.
43 */
44.dst_unaligned: tst dst, #1
45 beq .dst_16bit
46
47 load1b ip
48 sub len, len, #1
49 adcs sum, sum, ip, lsl #byte(1) @ update checksum
50 strb ip, [dst], #1
51 tst dst, #2
52 moveq pc, lr @ dst is now 32bit aligned
53
54.dst_16bit: load2b r8, ip
55 sub len, len, #2
56 adcs sum, sum, r8, lsl #byte(0)
57 strb r8, [dst], #1
58 adcs sum, sum, ip, lsl #byte(1)
59 strb ip, [dst], #1
60 mov pc, lr @ dst is now 32bit aligned
61
62 /*
63 * Handle 0 to 7 bytes, with any alignment of source and
64 * destination pointers. Note that when we get here, C = 0
65 */
66.less8: teq len, #0 @ check for zero count
67 beq .zero
68
69 /* we must have at least one byte. */
70 tst dst, #1 @ dst 16-bit aligned
71 beq .less8_aligned
72
73 /* Align dst */
74 load1b ip
75 sub len, len, #1
76 adcs sum, sum, ip, lsl #byte(1) @ update checksum
77 strb ip, [dst], #1
78 tst len, #6
79 beq .less8_byteonly
80
811: load2b r8, ip
82 sub len, len, #2
83 adcs sum, sum, r8, lsl #byte(0)
84 strb r8, [dst], #1
85 adcs sum, sum, ip, lsl #byte(1)
86 strb ip, [dst], #1
87.less8_aligned: tst len, #6
88 bne 1b
89.less8_byteonly:
90 tst len, #1
91 beq .done
92 load1b r8
93 adcs sum, sum, r8, lsl #byte(0) @ update checksum
94 strb r8, [dst], #1
95 b .done
96
97FN_ENTRY
98 mov ip, sp
99 save_regs
100 sub fp, ip, #4
101
102 cmp len, #8 @ Ensure that we have at least
103 blo .less8 @ 8 bytes to copy.
104
105 adds sum, sum, #0 @ C = 0
106 tst dst, #3 @ Test destination alignment
107 blne .dst_unaligned @ align destination, return here
108
109 /*
110 * Ok, the dst pointer is now 32bit aligned, and we know
111 * that we must have more than 4 bytes to copy. Note
112 * that C contains the carry from the dst alignment above.
113 */
114
115 tst src, #3 @ Test source alignment
116 bne .src_not_aligned
117
118 /* Routine for src & dst aligned */
119
120 bics ip, len, #15
121 beq 2f
122
1231: load4l r4, r5, r6, r7
124 stmia dst!, {r4, r5, r6, r7}
125 adcs sum, sum, r4
126 adcs sum, sum, r5
127 adcs sum, sum, r6
128 adcs sum, sum, r7
129 sub ip, ip, #16
130 teq ip, #0
131 bne 1b
132
1332: ands ip, len, #12
134 beq 4f
135 tst ip, #8
136 beq 3f
137 load2l r4, r5
138 stmia dst!, {r4, r5}
139 adcs sum, sum, r4
140 adcs sum, sum, r5
141 tst ip, #4
142 beq 4f
143
1443: load1l r4
145 str r4, [dst], #4
146 adcs sum, sum, r4
147
1484: ands len, len, #3
149 beq .done
150 load1l r4
151 tst len, #2
152/* mov r5, r4, lsr #byte(0)
153FIXME? 0 Shift anyhow!
154*/
155 beq .exit
156 adcs sum, sum, r4, push #16
157 strb r5, [dst], #1
158 mov r5, r4, lsr #byte(1)
159 strb r5, [dst], #1
160 mov r5, r4, lsr #byte(2)
161.exit: tst len, #1
162 strneb r5, [dst], #1
163 andne r5, r5, #255
164 adcnes sum, sum, r5, lsl #byte(0)
165
166 /*
167 * If the dst pointer was not 16-bit aligned, we
168 * need to rotate the checksum here to get around
169 * the inefficient byte manipulations in the
170 * architecture independent code.
171 */
172.done: adc r0, sum, #0
173 ldr sum, [sp, #0] @ dst
174 tst sum, #1
175 movne sum, r0, lsl #8
176 orrne r0, sum, r0, lsr #24
177 load_regs ea
178
179.src_not_aligned:
180 adc sum, sum, #0 @ include C from dst alignment
181 and ip, src, #3
182 bic src, src, #3
183 load1l r5
184 cmp ip, #2
185 beq .src2_aligned
186 bhi .src3_aligned
187 mov r4, r5, pull #8 @ C = 0
188 bics ip, len, #15
189 beq 2f
1901: load4l r5, r6, r7, r8
191 orr r4, r4, r5, push #24
192 mov r5, r5, pull #8
193 orr r5, r5, r6, push #24
194 mov r6, r6, pull #8
195 orr r6, r6, r7, push #24
196 mov r7, r7, pull #8
197 orr r7, r7, r8, push #24
198 stmia dst!, {r4, r5, r6, r7}
199 adcs sum, sum, r4
200 adcs sum, sum, r5
201 adcs sum, sum, r6
202 adcs sum, sum, r7
203 mov r4, r8, pull #8
204 sub ip, ip, #16
205 teq ip, #0
206 bne 1b
2072: ands ip, len, #12
208 beq 4f
209 tst ip, #8
210 beq 3f
211 load2l r5, r6
212 orr r4, r4, r5, push #24
213 mov r5, r5, pull #8
214 orr r5, r5, r6, push #24
215 stmia dst!, {r4, r5}
216 adcs sum, sum, r4
217 adcs sum, sum, r5
218 mov r4, r6, pull #8
219 tst ip, #4
220 beq 4f
2213: load1l r5
222 orr r4, r4, r5, push #24
223 str r4, [dst], #4
224 adcs sum, sum, r4
225 mov r4, r5, pull #8
2264: ands len, len, #3
227 beq .done
228/* mov r5, r4, lsr #byte(0)
229FIXME? 0 Shift anyhow
230*/
231 tst len, #2
232 beq .exit
233 adcs sum, sum, r4, push #16
234 strb r5, [dst], #1
235 mov r5, r4, lsr #byte(1)
236 strb r5, [dst], #1
237 mov r5, r4, lsr #byte(2)
238 b .exit
239
240.src2_aligned: mov r4, r5, pull #16
241 adds sum, sum, #0
242 bics ip, len, #15
243 beq 2f
2441: load4l r5, r6, r7, r8
245 orr r4, r4, r5, push #16
246 mov r5, r5, pull #16
247 orr r5, r5, r6, push #16
248 mov r6, r6, pull #16
249 orr r6, r6, r7, push #16
250 mov r7, r7, pull #16
251 orr r7, r7, r8, push #16
252 stmia dst!, {r4, r5, r6, r7}
253 adcs sum, sum, r4
254 adcs sum, sum, r5
255 adcs sum, sum, r6
256 adcs sum, sum, r7
257 mov r4, r8, pull #16
258 sub ip, ip, #16
259 teq ip, #0
260 bne 1b
2612: ands ip, len, #12
262 beq 4f
263 tst ip, #8
264 beq 3f
265 load2l r5, r6
266 orr r4, r4, r5, push #16
267 mov r5, r5, pull #16
268 orr r5, r5, r6, push #16
269 stmia dst!, {r4, r5}
270 adcs sum, sum, r4
271 adcs sum, sum, r5
272 mov r4, r6, pull #16
273 tst ip, #4
274 beq 4f
2753: load1l r5
276 orr r4, r4, r5, push #16
277 str r4, [dst], #4
278 adcs sum, sum, r4
279 mov r4, r5, pull #16
2804: ands len, len, #3
281 beq .done
282/* mov r5, r4, lsr #byte(0)
283FIXME? 0 Shift anyhow
284*/
285 tst len, #2
286 beq .exit
287 adcs sum, sum, r4
288 strb r5, [dst], #1
289 mov r5, r4, lsr #byte(1)
290 strb r5, [dst], #1
291 tst len, #1
292 beq .done
293 load1b r5
294 b .exit
295
296.src3_aligned: mov r4, r5, pull #24
297 adds sum, sum, #0
298 bics ip, len, #15
299 beq 2f
3001: load4l r5, r6, r7, r8
301 orr r4, r4, r5, push #8
302 mov r5, r5, pull #24
303 orr r5, r5, r6, push #8
304 mov r6, r6, pull #24
305 orr r6, r6, r7, push #8
306 mov r7, r7, pull #24
307 orr r7, r7, r8, push #8
308 stmia dst!, {r4, r5, r6, r7}
309 adcs sum, sum, r4
310 adcs sum, sum, r5
311 adcs sum, sum, r6
312 adcs sum, sum, r7
313 mov r4, r8, pull #24
314 sub ip, ip, #16
315 teq ip, #0
316 bne 1b
3172: ands ip, len, #12
318 beq 4f
319 tst ip, #8
320 beq 3f
321 load2l r5, r6
322 orr r4, r4, r5, push #8
323 mov r5, r5, pull #24
324 orr r5, r5, r6, push #8
325 stmia dst!, {r4, r5}
326 adcs sum, sum, r4
327 adcs sum, sum, r5
328 mov r4, r6, pull #24
329 tst ip, #4
330 beq 4f
3313: load1l r5
332 orr r4, r4, r5, push #8
333 str r4, [dst], #4
334 adcs sum, sum, r4
335 mov r4, r5, pull #24
3364: ands len, len, #3
337 beq .done
338/* mov r5, r4, lsr #byte(0)
339FIXME? 0 Shift anyhow
340*/
341 tst len, #2
342 beq .exit
343 strb r5, [dst], #1
344 adcs sum, sum, r4
345 load1l r4
346/* mov r5, r4, lsr #byte(0)
347FIXME? 0 Shift anyhow
348*/
349 strb r5, [dst], #1
350 adcs sum, sum, r4, push #24
351 mov r5, r4, lsr #byte(1)
352 b .exit
diff --git a/arch/arm26/lib/csumpartialcopyuser.S b/arch/arm26/lib/csumpartialcopyuser.S
new file mode 100644
index 000000000000..5b821188e479
--- /dev/null
+++ b/arch/arm26/lib/csumpartialcopyuser.S
@@ -0,0 +1,115 @@
1/*
2 * linux/arch/arm26/lib/csumpartialcopyuser.S
3 *
4 * Copyright (C) 1995-1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/config.h>
11#include <linux/linkage.h>
12#include <asm/assembler.h>
13#include <asm/errno.h>
14#include <asm/asm_offsets.h>
15
16 .text
17
18 .macro save_regs
19 stmfd sp!, {r1 - r2, r4 - r9, fp, ip, lr, pc}
20 mov r9, sp, lsr #13
21 mov r9, r9, lsl #13
22 ldr r9, [r9, #TSK_ADDR_LIMIT]
23 mov r9, r9, lsr #24
24 .endm
25
26 .macro load_regs,flags
27 ldm\flags fp, {r1, r2, r4-r9, fp, sp, pc}^
28 .endm
29
30 .macro load1b, reg1
31 tst r9, #0x01
329999: ldreqbt \reg1, [r0], #1
33 ldrneb \reg1, [r0], #1
34 .section __ex_table, "a"
35 .align 3
36 .long 9999b, 6001f
37 .previous
38 .endm
39
40 .macro load2b, reg1, reg2
41 tst r9, #0x01
429999: ldreqbt \reg1, [r0], #1
43 ldrneb \reg1, [r0], #1
449998: ldreqbt \reg2, [r0], #1
45 ldrneb \reg2, [r0], #1
46 .section __ex_table, "a"
47 .long 9999b, 6001f
48 .long 9998b, 6001f
49 .previous
50 .endm
51
52 .macro load1l, reg1
53 tst r9, #0x01
549999: ldreqt \reg1, [r0], #4
55 ldrne \reg1, [r0], #4
56 .section __ex_table, "a"
57 .align 3
58 .long 9999b, 6001f
59 .previous
60 .endm
61
62 .macro load2l, reg1, reg2
63 tst r9, #0x01
64 ldmneia r0!, {\reg1, \reg2}
659999: ldreqt \reg1, [r0], #4
669998: ldreqt \reg2, [r0], #4
67 .section __ex_table, "a"
68 .long 9999b, 6001f
69 .long 9998b, 6001f
70 .previous
71 .endm
72
73 .macro load4l, reg1, reg2, reg3, reg4
74 tst r9, #0x01
75 ldmneia r0!, {\reg1, \reg2, \reg3, \reg4}
769999: ldreqt \reg1, [r0], #4
779998: ldreqt \reg2, [r0], #4
789997: ldreqt \reg3, [r0], #4
799996: ldreqt \reg4, [r0], #4
80 .section __ex_table, "a"
81 .long 9999b, 6001f
82 .long 9998b, 6001f
83 .long 9997b, 6001f
84 .long 9996b, 6001f
85 .previous
86 .endm
87
88/*
89 * unsigned int
90 * csum_partial_copy_from_user(const char *src, char *dst, int len, int sum, int *err_ptr)
91 * r0 = src, r1 = dst, r2 = len, r3 = sum, [sp] = *err_ptr
92 * Returns : r0 = checksum, [[sp, #0], #0] = 0 or -EFAULT
93 */
94
95#define FN_ENTRY ENTRY(csum_partial_copy_from_user)
96
97#include "csumpartialcopygeneric.S"
98
99/*
100 * FIXME: minor buglet here
101 * We don't return the checksum for the data present in the buffer. To do
102 * so properly, we would have to add in whatever registers were loaded before
103 * the fault, which, with the current asm above is not predictable.
104 */
105 .align 4
1066001: mov r4, #-EFAULT
107 ldr r5, [fp, #4] @ *err_ptr
108 str r4, [r5]
109 ldmia sp, {r1, r2} @ retrieve dst, len
110 add r2, r2, r1
111 mov r0, #0 @ zero the buffer
1126002: teq r2, r1
113 strneb r0, [r1], #1
114 bne 6002b
115 load_regs ea
diff --git a/arch/arm26/lib/delay.S b/arch/arm26/lib/delay.S
new file mode 100644
index 000000000000..66f2b68e1b13
--- /dev/null
+++ b/arch/arm26/lib/delay.S
@@ -0,0 +1,57 @@
1/*
2 * linux/arch/arm26/lib/delay.S
3 *
4 * Copyright (C) 1995, 1996 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12 .text
13
14LC0: .word loops_per_jiffy
15
16/*
17 * 0 <= r0 <= 2000
18 */
19ENTRY(udelay)
20 mov r2, #0x6800
21 orr r2, r2, #0x00db
22 mul r1, r0, r2
23 ldr r2, LC0
24 ldr r2, [r2]
25 mov r1, r1, lsr #11
26 mov r2, r2, lsr #11
27 mul r0, r1, r2
28 movs r0, r0, lsr #6
29 RETINSTR(moveq,pc,lr)
30
31/*
32 * loops = (r0 * 0x10c6 * 100 * loops_per_jiffy) / 2^32
33 *
34 * Oh, if only we had a cycle counter...
35 */
36
37@ Delay routine
38ENTRY(__delay)
39 subs r0, r0, #1
40#if 0
41 RETINSTR(movls,pc,lr)
42 subs r0, r0, #1
43 RETINSTR(movls,pc,lr)
44 subs r0, r0, #1
45 RETINSTR(movls,pc,lr)
46 subs r0, r0, #1
47 RETINSTR(movls,pc,lr)
48 subs r0, r0, #1
49 RETINSTR(movls,pc,lr)
50 subs r0, r0, #1
51 RETINSTR(movls,pc,lr)
52 subs r0, r0, #1
53 RETINSTR(movls,pc,lr)
54 subs r0, r0, #1
55#endif
56 bhi __delay
57 RETINSTR(mov,pc,lr)
diff --git a/arch/arm26/lib/ecard.S b/arch/arm26/lib/ecard.S
new file mode 100644
index 000000000000..b4633150f01c
--- /dev/null
+++ b/arch/arm26/lib/ecard.S
@@ -0,0 +1,41 @@
1/*
2 * linux/arch/arm26/lib/ecard.S
3 *
4 * Copyright (C) 1995, 1996 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/config.h> /* for CONFIG_CPU_nn */
11#include <linux/linkage.h>
12#include <asm/assembler.h>
13#include <asm/hardware.h>
14
15#define CPSR2SPSR(rt)
16
17@ Purpose: call an expansion card loader to read bytes.
18@ Proto : char read_loader(int offset, char *card_base, char *loader);
19@ Returns: byte read
20
21ENTRY(ecard_loader_read)
22 stmfd sp!, {r4 - r12, lr}
23 mov r11, r1
24 mov r1, r0
25 CPSR2SPSR(r0)
26 mov lr, pc
27 mov pc, r2
28 LOADREGS(fd, sp!, {r4 - r12, pc})
29
30@ Purpose: call an expansion card loader to reset the card
31@ Proto : void read_loader(int card_base, char *loader);
32@ Returns: byte read
33
34ENTRY(ecard_loader_reset)
35 stmfd sp!, {r4 - r12, lr}
36 mov r11, r0
37 CPSR2SPSR(r0)
38 mov lr, pc
39 add pc, r1, #8
40 LOADREGS(fd, sp!, {r4 - r12, pc})
41
diff --git a/arch/arm26/lib/findbit.S b/arch/arm26/lib/findbit.S
new file mode 100644
index 000000000000..26f67cccc37c
--- /dev/null
+++ b/arch/arm26/lib/findbit.S
@@ -0,0 +1,67 @@
1/*
2 * linux/arch/arm/lib/findbit.S
3 *
4 * Copyright (C) 1995-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * 16th March 2001 - John Ripley <jripley@sonicblue.com>
11 * Fixed so that "size" is an exclusive not an inclusive quantity.
12 * All users of these functions expect exclusive sizes, and may
13 * also call with zero size.
14 * Reworked by rmk.
15 */
16#include <linux/linkage.h>
17#include <asm/assembler.h>
18 .text
19
20/*
21 * Purpose : Find a 'zero' bit
22 * Prototype: int find_first_zero_bit(void *addr, unsigned int maxbit);
23 */
24ENTRY(_find_first_zero_bit_le)
25 teq r1, #0
26 beq 3f
27 mov r2, #0
281: ldrb r3, [r0, r2, lsr #3]
29 eors r3, r3, #0xff @ invert bits
30 bne .found @ any now set - found zero bit
31 add r2, r2, #8 @ next bit pointer
322: cmp r2, r1 @ any more?
33 blo 1b
343: mov r0, r1 @ no free bits
35 RETINSTR(mov,pc,lr)
36
37/*
38 * Purpose : Find next 'zero' bit
39 * Prototype: int find_next_zero_bit(void *addr, unsigned int maxbit, int offset)
40 */
41ENTRY(_find_next_zero_bit_le)
42 teq r1, #0
43 beq 2b
44 ands ip, r2, #7
45 beq 1b @ If new byte, goto old routine
46 ldrb r3, [r0, r2, lsr #3]
47 eor r3, r3, #0xff @ now looking for a 1 bit
48 movs r3, r3, lsr ip @ shift off unused bits
49 bne .found
50 orr r2, r2, #7 @ if zero, then no bits here
51 add r2, r2, #1 @ align bit pointer
52 b 2b @ loop for next bit
53
54/*
55 * One or more bits in the LSB of r3 are assumed to be set.
56 */
57.found: tst r3, #0x0f
58 addeq r2, r2, #4
59 movne r3, r3, lsl #4
60 tst r3, #0x30
61 addeq r2, r2, #2
62 movne r3, r3, lsl #2
63 tst r3, #0x40
64 addeq r2, r2, #1
65 mov r0, r2
66 RETINSTR(mov,pc,lr)
67
diff --git a/arch/arm26/lib/floppydma.S b/arch/arm26/lib/floppydma.S
new file mode 100644
index 000000000000..e99ebbb20353
--- /dev/null
+++ b/arch/arm26/lib/floppydma.S
@@ -0,0 +1,32 @@
1/*
2 * linux/arch/arm26/lib/floppydma.S
3 *
4 * Copyright (C) 1995, 1996 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12 .text
13
14 .global floppy_fiqin_end
15ENTRY(floppy_fiqin_start)
16 subs r9, r9, #1
17 ldrgtb r12, [r11, #-4]
18 ldrleb r12, [r11], #0
19 strb r12, [r10], #1
20 subs pc, lr, #4
21floppy_fiqin_end:
22
23 .global floppy_fiqout_end
24ENTRY(floppy_fiqout_start)
25 subs r9, r9, #1
26 ldrgeb r12, [r10], #1
27 movlt r12, #0
28 strleb r12, [r11], #0
29 subles pc, lr, #4
30 strb r12, [r11, #-4]
31 subs pc, lr, #4
32floppy_fiqout_end:
diff --git a/arch/arm26/lib/gcclib.h b/arch/arm26/lib/gcclib.h
new file mode 100644
index 000000000000..9895e78904b5
--- /dev/null
+++ b/arch/arm26/lib/gcclib.h
@@ -0,0 +1,21 @@
1/* gcclib.h -- definitions for various functions 'borrowed' from gcc-2.95.3 */
2/* I Molton 29/07/01 */
3
4#define BITS_PER_UNIT 8
5#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT)
6
7typedef unsigned int UQItype __attribute__ ((mode (QI)));
8typedef int SItype __attribute__ ((mode (SI)));
9typedef unsigned int USItype __attribute__ ((mode (SI)));
10typedef int DItype __attribute__ ((mode (DI)));
11typedef int word_type __attribute__ ((mode (__word__)));
12typedef unsigned int UDItype __attribute__ ((mode (DI)));
13
14struct DIstruct {SItype low, high;};
15
16typedef union
17{
18 struct DIstruct s;
19 DItype ll;
20} DIunion;
21
diff --git a/arch/arm26/lib/getuser.S b/arch/arm26/lib/getuser.S
new file mode 100644
index 000000000000..e6d59b334851
--- /dev/null
+++ b/arch/arm26/lib/getuser.S
@@ -0,0 +1,112 @@
1/*
2 * linux/arch/arm26/lib/getuser.S
3 *
4 * Copyright (C) 2001 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Idea from x86 version, (C) Copyright 1998 Linus Torvalds
11 *
12 * These functions have a non-standard call interface to make them more
13 * efficient, especially as they return an error value in addition to
14 * the "real" return value.
15 *
16 * __get_user_X
17 *
18 * Inputs: r0 contains the address
19 * Outputs: r0 is the error code
20 * r1, r2 contains the zero-extended value
21 * lr corrupted
22 *
23 * No other registers must be altered. (see include/asm-arm/uaccess.h
24 * for specific ASM register usage).
25 *
26 * Note that ADDR_LIMIT is either 0 or 0xc0000000.
27 * Note also that it is intended that __get_user_bad is not global.
28 */
29#include <asm/asm_offsets.h>
30#include <asm/thread_info.h>
31#include <asm/errno.h>
32
33 .global __get_user_1
34__get_user_1:
35 bic r1, sp, #0x1f00
36 bic r1, r1, #0x00ff
37 str lr, [sp, #-4]!
38 ldr r1, [r1, #TI_ADDR_LIMIT]
39 sub r1, r1, #1
40 cmp r0, r1
41 bge __get_user_bad
42 cmp r0, #0x02000000
431: ldrlsbt r1, [r0]
44 ldrgeb r1, [r0]
45 mov r0, #0
46 ldmfd sp!, {pc}^
47
48 .global __get_user_2
49__get_user_2:
50 bic r2, sp, #0x1f00
51 bic r2, r2, #0x00ff
52 str lr, [sp, #-4]!
53 ldr r2, [r2, #TI_ADDR_LIMIT]
54 sub r2, r2, #2
55 cmp r0, r2
56 bge __get_user_bad
57 cmp r0, #0x02000000
582: ldrlsbt r1, [r0], #1
593: ldrlsbt r2, [r0]
60 ldrgeb r1, [r0], #1
61 ldrgeb r2, [r0]
62 orr r1, r1, r2, lsl #8
63 mov r0, #0
64 ldmfd sp!, {pc}^
65
66 .global __get_user_4
67__get_user_4:
68 bic r1, sp, #0x1f00
69 bic r1, r1, #0x00ff
70 str lr, [sp, #-4]!
71 ldr r1, [r1, #TI_ADDR_LIMIT]
72 sub r1, r1, #4
73 cmp r0, r1
74 bge __get_user_bad
75 cmp r0, #0x02000000
764: ldrlst r1, [r0]
77 ldrge r1, [r0]
78 mov r0, #0
79 ldmfd sp!, {pc}^
80
81 .global __get_user_8
82__get_user_8:
83 bic r2, sp, #0x1f00
84 bic r2, r2, #0x00ff
85 str lr, [sp, #-4]!
86 ldr r2, [r2, #TI_ADDR_LIMIT]
87 sub r2, r2, #8
88 cmp r0, r2
89 bge __get_user_bad_8
90 cmp r0, #0x02000000
915: ldrlst r1, [r0], #4
926: ldrlst r2, [r0]
93 ldrge r1, [r0], #4
94 ldrge r2, [r0]
95 mov r0, #0
96 ldmfd sp!, {pc}^
97
98__get_user_bad_8:
99 mov r2, #0
100__get_user_bad:
101 mov r1, #0
102 mov r0, #-EFAULT
103 ldmfd sp!, {pc}^
104
105.section __ex_table, "a"
106 .long 1b, __get_user_bad
107 .long 2b, __get_user_bad
108 .long 3b, __get_user_bad
109 .long 4b, __get_user_bad
110 .long 5b, __get_user_bad_8
111 .long 6b, __get_user_bad_8
112.previous
diff --git a/arch/arm26/lib/io-acorn.S b/arch/arm26/lib/io-acorn.S
new file mode 100644
index 000000000000..f6c3e30b1b4f
--- /dev/null
+++ b/arch/arm26/lib/io-acorn.S
@@ -0,0 +1,71 @@
1/*
2 * linux/arch/arm26/lib/io-acorn.S
3 *
4 * Copyright (C) 1995, 1996 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/config.h> /* for CONFIG_CPU_nn */
11#include <linux/linkage.h>
12#include <asm/assembler.h>
13#include <asm/hardware.h>
14
15 .text
16 .align
17
18 .equ diff_pcio_base, PCIO_BASE - IO_BASE
19
20 .macro outw2 rd
21 mov r8, \rd, lsl #16
22 orr r8, r8, r8, lsr #16
23 str r8, [r3, r0, lsl #2]
24 mov r8, \rd, lsr #16
25 orr r8, r8, r8, lsl #16
26 str r8, [r3, r0, lsl #2]
27 .endm
28
29 .macro inw2 rd, mask, temp
30 ldr \rd, [r0]
31 and \rd, \rd, \mask
32 ldr \temp, [r0]
33 orr \rd, \rd, \temp, lsl #16
34 .endm
35
36 .macro addr rd
37 tst \rd, #0x80000000
38 mov \rd, \rd, lsl #2
39 add \rd, \rd, #IO_BASE
40 addeq \rd, \rd, #diff_pcio_base
41 .endm
42
43.iosl_warning:
44 .ascii "<4>insl/outsl not implemented, called from %08lX\0"
45 .align
46
47/*
48 * These make no sense on Acorn machines.
49 * Print a warning message.
50 */
51ENTRY(insl)
52ENTRY(outsl)
53 adr r0, .iosl_warning
54 mov r1, lr
55 b printk
56
57@ Purpose: write a memc register
58@ Proto : void memc_write(int register, int value);
59@ Returns: nothing
60
61ENTRY(memc_write)
62 cmp r0, #7
63 RETINSTR(movgt,pc,lr)
64 mov r0, r0, lsl #17
65 mov r1, r1, lsl #15
66 mov r1, r1, lsr #17
67 orr r0, r0, r1, lsl #2
68 add r0, r0, #0x03600000
69 strb r0, [r0]
70 RETINSTR(mov,pc,lr)
71
diff --git a/arch/arm26/lib/io-readsb.S b/arch/arm26/lib/io-readsb.S
new file mode 100644
index 000000000000..4c4d99c05856
--- /dev/null
+++ b/arch/arm26/lib/io-readsb.S
@@ -0,0 +1,116 @@
1/*
2 * linux/arch/arm26/lib/io-readsb.S
3 *
4 * Copyright (C) 1995-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12#include <asm/hardware.h>
13
14.insb_align: rsb ip, ip, #4
15 cmp ip, r2
16 movgt ip, r2
17 cmp ip, #2
18 ldrb r3, [r0]
19 strb r3, [r1], #1
20 ldrgeb r3, [r0]
21 strgeb r3, [r1], #1
22 ldrgtb r3, [r0]
23 strgtb r3, [r1], #1
24 subs r2, r2, ip
25 bne .insb_aligned
26
27ENTRY(__raw_readsb)
28 teq r2, #0 @ do we have to check for the zero len?
29 moveq pc, lr
30 ands ip, r1, #3
31 bne .insb_align
32
33.insb_aligned: stmfd sp!, {r4 - r6, lr}
34
35 subs r2, r2, #16
36 bmi .insb_no_16
37
38.insb_16_lp: ldrb r3, [r0]
39 ldrb r4, [r0]
40 orr r3, r3, r4, lsl #8
41 ldrb r4, [r0]
42 orr r3, r3, r4, lsl #16
43 ldrb r4, [r0]
44 orr r3, r3, r4, lsl #24
45 ldrb r4, [r0]
46 ldrb r5, [r0]
47 orr r4, r4, r5, lsl #8
48 ldrb r5, [r0]
49 orr r4, r4, r5, lsl #16
50 ldrb r5, [r0]
51 orr r4, r4, r5, lsl #24
52 ldrb r5, [r0]
53 ldrb r6, [r0]
54 orr r5, r5, r6, lsl #8
55 ldrb r6, [r0]
56 orr r5, r5, r6, lsl #16
57 ldrb r6, [r0]
58 orr r5, r5, r6, lsl #24
59 ldrb r6, [r0]
60 ldrb ip, [r0]
61 orr r6, r6, ip, lsl #8
62 ldrb ip, [r0]
63 orr r6, r6, ip, lsl #16
64 ldrb ip, [r0]
65 orr r6, r6, ip, lsl #24
66 stmia r1!, {r3 - r6}
67
68 subs r2, r2, #16
69 bpl .insb_16_lp
70
71 tst r2, #15
72 LOADREGS(eqfd, sp!, {r4 - r6, pc})
73
74.insb_no_16: tst r2, #8
75 beq .insb_no_8
76
77 ldrb r3, [r0]
78 ldrb r4, [r0]
79 orr r3, r3, r4, lsl #8
80 ldrb r4, [r0]
81 orr r3, r3, r4, lsl #16
82 ldrb r4, [r0]
83 orr r3, r3, r4, lsl #24
84 ldrb r4, [r0]
85 ldrb r5, [r0]
86 orr r4, r4, r5, lsl #8
87 ldrb r5, [r0]
88 orr r4, r4, r5, lsl #16
89 ldrb r5, [r0]
90 orr r4, r4, r5, lsl #24
91 stmia r1!, {r3, r4}
92
93.insb_no_8: tst r2, #4
94 beq .insb_no_4
95
96 ldrb r3, [r0]
97 ldrb r4, [r0]
98 orr r3, r3, r4, lsl #8
99 ldrb r4, [r0]
100 orr r3, r3, r4, lsl #16
101 ldrb r4, [r0]
102 orr r3, r3, r4, lsl #24
103 str r3, [r1], #4
104
105.insb_no_4: ands r2, r2, #3
106 LOADREGS(eqfd, sp!, {r4 - r6, pc})
107
108 cmp r2, #2
109 ldrb r3, [r0]
110 strb r3, [r1], #1
111 ldrgeb r3, [r0]
112 strgeb r3, [r1], #1
113 ldrgtb r3, [r0]
114 strgtb r3, [r1]
115
116 LOADREGS(fd, sp!, {r4 - r6, pc})
diff --git a/arch/arm26/lib/io-readsl.S b/arch/arm26/lib/io-readsl.S
new file mode 100644
index 000000000000..7be208bd23c6
--- /dev/null
+++ b/arch/arm26/lib/io-readsl.S
@@ -0,0 +1,78 @@
1/*
2 * linux/arch/arm26/lib/io-readsl.S
3 *
4 * Copyright (C) 1995-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12#include <asm/hardware.h>
13
14/*
15 * Note that some reads can be aligned on half-word boundaries.
16 */
17ENTRY(__raw_readsl)
18 teq r2, #0 @ do we have to check for the zero len?
19 moveq pc, lr
20 ands ip, r1, #3
21 bne 2f
22
231: ldr r3, [r0]
24 str r3, [r1], #4
25 subs r2, r2, #1
26 bne 1b
27 mov pc, lr
28
292: cmp ip, #2
30 ldr ip, [r0]
31 blt 4f
32 bgt 6f
33
34 strb ip, [r1], #1
35 mov ip, ip, lsr #8
36 strb ip, [r1], #1
37 mov ip, ip, lsr #8
383: subs r2, r2, #1
39 ldrne r3, [r0]
40 orrne ip, ip, r3, lsl #16
41 strne ip, [r1], #4
42 movne ip, r3, lsr #16
43 bne 3b
44 strb ip, [r1], #1
45 mov ip, ip, lsr #8
46 strb ip, [r1], #1
47 mov pc, lr
48
494: strb ip, [r1], #1
50 mov ip, ip, lsr #8
51 strb ip, [r1], #1
52 mov ip, ip, lsr #8
53 strb ip, [r1], #1
54 mov ip, ip, lsr #8
555: subs r2, r2, #1
56 ldrne r3, [r0]
57 orrne ip, ip, r3, lsl #8
58 strne ip, [r1], #4
59 movne ip, r3, lsr #24
60 bne 5b
61 strb ip, [r1], #1
62 mov pc, lr
63
646: strb ip, [r1], #1
65 mov ip, ip, lsr #8
667: subs r2, r2, #1
67 ldrne r3, [r0]
68 orrne ip, ip, r3, lsl #24
69 strne ip, [r1], #4
70 movne ip, r3, lsr #8
71 bne 7b
72 strb ip, [r1], #1
73 mov ip, ip, lsr #8
74 strb ip, [r1], #1
75 mov ip, ip, lsr #8
76 strb ip, [r1], #1
77 mov pc, lr
78
diff --git a/arch/arm26/lib/io-readsw.S b/arch/arm26/lib/io-readsw.S
new file mode 100644
index 000000000000..c65c1f28fcff
--- /dev/null
+++ b/arch/arm26/lib/io-readsw.S
@@ -0,0 +1,107 @@
1/*
2 * linux/arch/arm26/lib/io-readsw.S
3 *
4 * Copyright (C) 1995-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12#include <asm/hardware.h>
13
14.insw_bad_alignment:
15 adr r0, .insw_bad_align_msg
16 mov r2, lr
17 b panic
18.insw_bad_align_msg:
19 .asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
20 .align
21
22.insw_align: tst r1, #1
23 bne .insw_bad_alignment
24
25 ldr r3, [r0]
26 strb r3, [r1], #1
27 mov r3, r3, lsr #8
28 strb r3, [r1], #1
29
30 subs r2, r2, #1
31 RETINSTR(moveq, pc, lr)
32
33ENTRY(__raw_readsw)
34 teq r2, #0 @ do we have to check for the zero len?
35 moveq pc, lr
36 tst r1, #3
37 bne .insw_align
38
39.insw_aligned: mov ip, #0xff
40 orr ip, ip, ip, lsl #8
41 stmfd sp!, {r4, r5, r6, lr}
42
43 subs r2, r2, #8
44 bmi .no_insw_8
45
46.insw_8_lp: ldr r3, [r0]
47 and r3, r3, ip
48 ldr r4, [r0]
49 orr r3, r3, r4, lsl #16
50
51 ldr r4, [r0]
52 and r4, r4, ip
53 ldr r5, [r0]
54 orr r4, r4, r5, lsl #16
55
56 ldr r5, [r0]
57 and r5, r5, ip
58 ldr r6, [r0]
59 orr r5, r5, r6, lsl #16
60
61 ldr r6, [r0]
62 and r6, r6, ip
63 ldr lr, [r0]
64 orr r6, r6, lr, lsl #16
65
66 stmia r1!, {r3 - r6}
67
68 subs r2, r2, #8
69 bpl .insw_8_lp
70
71 tst r2, #7
72 LOADREGS(eqfd, sp!, {r4, r5, r6, pc})
73
74.no_insw_8: tst r2, #4
75 beq .no_insw_4
76
77 ldr r3, [r0]
78 and r3, r3, ip
79 ldr r4, [r0]
80 orr r3, r3, r4, lsl #16
81
82 ldr r4, [r0]
83 and r4, r4, ip
84 ldr r5, [r0]
85 orr r4, r4, r5, lsl #16
86
87 stmia r1!, {r3, r4}
88
89.no_insw_4: tst r2, #2
90 beq .no_insw_2
91
92 ldr r3, [r0]
93 and r3, r3, ip
94 ldr r4, [r0]
95 orr r3, r3, r4, lsl #16
96
97 str r3, [r1], #4
98
99.no_insw_2: tst r2, #1
100 ldrne r3, [r0]
101 strneb r3, [r1], #1
102 movne r3, r3, lsr #8
103 strneb r3, [r1]
104
105 LOADREGS(fd, sp!, {r4, r5, r6, pc})
106
107
diff --git a/arch/arm26/lib/io-writesb.S b/arch/arm26/lib/io-writesb.S
new file mode 100644
index 000000000000..16251b4d5101
--- /dev/null
+++ b/arch/arm26/lib/io-writesb.S
@@ -0,0 +1,122 @@
1/*
2 * linux/arch/arm26/lib/io-writesb.S
3 *
4 * Copyright (C) 1995-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12#include <asm/hardware.h>
13
14.outsb_align: rsb ip, ip, #4
15 cmp ip, r2
16 movgt ip, r2
17 cmp ip, #2
18 ldrb r3, [r1], #1
19 strb r3, [r0]
20 ldrgeb r3, [r1], #1
21 strgeb r3, [r0]
22 ldrgtb r3, [r1], #1
23 strgtb r3, [r0]
24 subs r2, r2, ip
25 bne .outsb_aligned
26
27ENTRY(__raw_writesb)
28 teq r2, #0 @ do we have to check for the zero len?
29 moveq pc, lr
30 ands ip, r1, #3
31 bne .outsb_align
32
33.outsb_aligned: stmfd sp!, {r4 - r6, lr}
34
35 subs r2, r2, #16
36 bmi .outsb_no_16
37
38.outsb_16_lp: ldmia r1!, {r3 - r6}
39
40 strb r3, [r0]
41 mov r3, r3, lsr #8
42 strb r3, [r0]
43 mov r3, r3, lsr #8
44 strb r3, [r0]
45 mov r3, r3, lsr #8
46 strb r3, [r0]
47
48 strb r4, [r0]
49 mov r4, r4, lsr #8
50 strb r4, [r0]
51 mov r4, r4, lsr #8
52 strb r4, [r0]
53 mov r4, r4, lsr #8
54 strb r4, [r0]
55
56 strb r5, [r0]
57 mov r5, r5, lsr #8
58 strb r5, [r0]
59 mov r5, r5, lsr #8
60 strb r5, [r0]
61 mov r5, r5, lsr #8
62 strb r5, [r0]
63
64 strb r6, [r0]
65 mov r6, r6, lsr #8
66 strb r6, [r0]
67 mov r6, r6, lsr #8
68 strb r6, [r0]
69 mov r6, r6, lsr #8
70 strb r6, [r0]
71
72 subs r2, r2, #16
73 bpl .outsb_16_lp
74
75 tst r2, #15
76 LOADREGS(eqfd, sp!, {r4 - r6, pc})
77
78.outsb_no_16: tst r2, #8
79 beq .outsb_no_8
80
81 ldmia r1!, {r3, r4}
82
83 strb r3, [r0]
84 mov r3, r3, lsr #8
85 strb r3, [r0]
86 mov r3, r3, lsr #8
87 strb r3, [r0]
88 mov r3, r3, lsr #8
89 strb r3, [r0]
90
91 strb r4, [r0]
92 mov r4, r4, lsr #8
93 strb r4, [r0]
94 mov r4, r4, lsr #8
95 strb r4, [r0]
96 mov r4, r4, lsr #8
97 strb r4, [r0]
98
99.outsb_no_8: tst r2, #4
100 beq .outsb_no_4
101
102 ldr r3, [r1], #4
103 strb r3, [r0]
104 mov r3, r3, lsr #8
105 strb r3, [r0]
106 mov r3, r3, lsr #8
107 strb r3, [r0]
108 mov r3, r3, lsr #8
109 strb r3, [r0]
110
111.outsb_no_4: ands r2, r2, #3
112 LOADREGS(eqfd, sp!, {r4 - r6, pc})
113
114 cmp r2, #2
115 ldrb r3, [r1], #1
116 strb r3, [r0]
117 ldrgeb r3, [r1], #1
118 strgeb r3, [r0]
119 ldrgtb r3, [r1]
120 strgtb r3, [r0]
121
122 LOADREGS(fd, sp!, {r4 - r6, pc})
diff --git a/arch/arm26/lib/io-writesl.S b/arch/arm26/lib/io-writesl.S
new file mode 100644
index 000000000000..4d6049b16e71
--- /dev/null
+++ b/arch/arm26/lib/io-writesl.S
@@ -0,0 +1,56 @@
1/*
2 * linux/arch/arm26/lib/io-writesl.S
3 *
4 * Copyright (C) 1995-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12#include <asm/hardware.h>
13
14ENTRY(__raw_writesl)
15 teq r2, #0 @ do we have to check for the zero len?
16 moveq pc, lr
17 ands ip, r1, #3
18 bne 2f
19
201: ldr r3, [r1], #4
21 str r3, [r0]
22 subs r2, r2, #1
23 bne 1b
24 mov pc, lr
25
262: bic r1, r1, #3
27 cmp ip, #2
28 ldr r3, [r1], #4
29 bgt 4f
30 blt 5f
31
323: mov ip, r3, lsr #16
33 ldr r3, [r1], #4
34 orr ip, ip, r3, lsl #16
35 str ip, [r0]
36 subs r2, r2, #1
37 bne 3b
38 mov pc, lr
39
404: mov ip, r3, lsr #24
41 ldr r3, [r1], #4
42 orr ip, ip, r3, lsl #8
43 str ip, [r0]
44 subs r2, r2, #1
45 bne 4b
46 mov pc, lr
47
485: mov ip, r3, lsr #8
49 ldr r3, [r1], #4
50 orr ip, ip, r3, lsl #24
51 str ip, [r0]
52 subs r2, r2, #1
53 bne 5b
54 mov pc, lr
55
56
diff --git a/arch/arm26/lib/io-writesw.S b/arch/arm26/lib/io-writesw.S
new file mode 100644
index 000000000000..a24f891f6b1c
--- /dev/null
+++ b/arch/arm26/lib/io-writesw.S
@@ -0,0 +1,127 @@
1/*
2 * linux/arch/arm26/lib/io-writesw.S
3 *
4 * Copyright (C) 1995-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12#include <asm/hardware.h>
13
14.outsw_bad_alignment:
15 adr r0, .outsw_bad_align_msg
16 mov r2, lr
17 b panic
18.outsw_bad_align_msg:
19 .asciz "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
20 .align
21
22.outsw_align: tst r1, #1
23 bne .outsw_bad_alignment
24
25 add r1, r1, #2
26
27 ldr r3, [r1, #-4]
28 mov r3, r3, lsr #16
29 orr r3, r3, r3, lsl #16
30 str r3, [r0]
31 subs r2, r2, #1
32 RETINSTR(moveq, pc, lr)
33
34ENTRY(__raw_writesw)
35 teq r2, #0 @ do we have to check for the zero len?
36 moveq pc, lr
37 tst r1, #3
38 bne .outsw_align
39
40.outsw_aligned: stmfd sp!, {r4, r5, r6, lr}
41
42 subs r2, r2, #8
43 bmi .no_outsw_8
44
45.outsw_8_lp: ldmia r1!, {r3, r4, r5, r6}
46
47 mov ip, r3, lsl #16
48 orr ip, ip, ip, lsr #16
49 str ip, [r0]
50
51 mov ip, r3, lsr #16
52 orr ip, ip, ip, lsl #16
53 str ip, [r0]
54
55 mov ip, r4, lsl #16
56 orr ip, ip, ip, lsr #16
57 str ip, [r0]
58
59 mov ip, r4, lsr #16
60 orr ip, ip, ip, lsl #16
61 str ip, [r0]
62
63 mov ip, r5, lsl #16
64 orr ip, ip, ip, lsr #16
65 str ip, [r0]
66
67 mov ip, r5, lsr #16
68 orr ip, ip, ip, lsl #16
69 str ip, [r0]
70
71 mov ip, r6, lsl #16
72 orr ip, ip, ip, lsr #16
73 str ip, [r0]
74
75 mov ip, r6, lsr #16
76 orr ip, ip, ip, lsl #16
77 str ip, [r0]
78
79 subs r2, r2, #8
80 bpl .outsw_8_lp
81
82 tst r2, #7
83 LOADREGS(eqfd, sp!, {r4, r5, r6, pc})
84
85.no_outsw_8: tst r2, #4
86 beq .no_outsw_4
87
88 ldmia r1!, {r3, r4}
89
90 mov ip, r3, lsl #16
91 orr ip, ip, ip, lsr #16
92 str ip, [r0]
93
94 mov ip, r3, lsr #16
95 orr ip, ip, ip, lsl #16
96 str ip, [r0]
97
98 mov ip, r4, lsl #16
99 orr ip, ip, ip, lsr #16
100 str ip, [r0]
101
102 mov ip, r4, lsr #16
103 orr ip, ip, ip, lsl #16
104 str ip, [r0]
105
106.no_outsw_4: tst r2, #2
107 beq .no_outsw_2
108
109 ldr r3, [r1], #4
110
111 mov ip, r3, lsl #16
112 orr ip, ip, ip, lsr #16
113 str ip, [r0]
114
115 mov ip, r3, lsr #16
116 orr ip, ip, ip, lsl #16
117 str ip, [r0]
118
119.no_outsw_2: tst r2, #1
120
121 ldrne r3, [r1]
122
123 movne ip, r3, lsl #16
124 orrne ip, ip, ip, lsr #16
125 strne ip, [r0]
126
127 LOADREGS(fd, sp!, {r4, r5, r6, pc})
diff --git a/arch/arm26/lib/kbd.c b/arch/arm26/lib/kbd.c
new file mode 100644
index 000000000000..22d2c93aaf1a
--- /dev/null
+++ b/arch/arm26/lib/kbd.c
@@ -0,0 +1,279 @@
1#include <linux/config.h>
2#include <linux/kd.h>
3//#include <linux/kbd_ll.h>
4#include <linux/kbd_kern.h>
5
6/*
7 * Translation of escaped scancodes to keycodes.
8 * This is now user-settable.
9 * The keycodes 1-88,96-111,119 are fairly standard, and
10 * should probably not be changed - changing might confuse X.
11 * X also interprets scancode 0x5d (KEY_Begin).
12 *
13 * For 1-88 keycode equals scancode.
14 */
15
16#define E0_KPENTER 96
17#define E0_RCTRL 97
18#define E0_KPSLASH 98
19#define E0_PRSCR 99
20#define E0_RALT 100
21#define E0_BREAK 101 /* (control-pause) */
22#define E0_HOME 102
23#define E0_UP 103
24#define E0_PGUP 104
25#define E0_LEFT 105
26#define E0_RIGHT 106
27#define E0_END 107
28#define E0_DOWN 108
29#define E0_PGDN 109
30#define E0_INS 110
31#define E0_DEL 111
32
33/* for USB 106 keyboard */
34#define E0_YEN 124
35#define E0_BACKSLASH 89
36
37
38#define E1_PAUSE 119
39
40/*
41 * The keycodes below are randomly located in 89-95,112-118,120-127.
42 * They could be thrown away (and all occurrences below replaced by 0),
43 * but that would force many users to use the `setkeycodes' utility, where
44 * they needed not before. It does not matter that there are duplicates, as
45 * long as no duplication occurs for any single keyboard.
46 */
47#define SC_LIM 89
48
49#define FOCUS_PF1 85 /* actual code! */
50#define FOCUS_PF2 89
51#define FOCUS_PF3 90
52#define FOCUS_PF4 91
53#define FOCUS_PF5 92
54#define FOCUS_PF6 93
55#define FOCUS_PF7 94
56#define FOCUS_PF8 95
57#define FOCUS_PF9 120
58#define FOCUS_PF10 121
59#define FOCUS_PF11 122
60#define FOCUS_PF12 123
61
62#define JAP_86 124
63/* tfj@olivia.ping.dk:
64 * The four keys are located over the numeric keypad, and are
65 * labelled A1-A4. It's an rc930 keyboard, from
66 * Regnecentralen/RC International, Now ICL.
67 * Scancodes: 59, 5a, 5b, 5c.
68 */
69#define RGN1 124
70#define RGN2 125
71#define RGN3 126
72#define RGN4 127
73
74static unsigned char high_keys[128 - SC_LIM] = {
75 RGN1, RGN2, RGN3, RGN4, 0, 0, 0, /* 0x59-0x5f */
76 0, 0, 0, 0, 0, 0, 0, 0, /* 0x60-0x67 */
77 0, 0, 0, 0, 0, FOCUS_PF11, 0, FOCUS_PF12, /* 0x68-0x6f */
78 0, 0, 0, FOCUS_PF2, FOCUS_PF9, 0, 0, FOCUS_PF3, /* 0x70-0x77 */
79 FOCUS_PF4, FOCUS_PF5, FOCUS_PF6, FOCUS_PF7, /* 0x78-0x7b */
80 FOCUS_PF8, JAP_86, FOCUS_PF10, 0 /* 0x7c-0x7f */
81};
82
83/* BTC */
84#define E0_MACRO 112
85/* LK450 */
86#define E0_F13 113
87#define E0_F14 114
88#define E0_HELP 115
89#define E0_DO 116
90#define E0_F17 117
91#define E0_KPMINPLUS 118
92/*
93 * My OmniKey generates e0 4c for the "OMNI" key and the
94 * right alt key does nada. [kkoller@nyx10.cs.du.edu]
95 */
96#define E0_OK 124
97/*
98 * New microsoft keyboard is rumoured to have
99 * e0 5b (left window button), e0 5c (right window button),
100 * e0 5d (menu button). [or: LBANNER, RBANNER, RMENU]
101 * [or: Windows_L, Windows_R, TaskMan]
102 */
103#define E0_MSLW 125
104#define E0_MSRW 126
105#define E0_MSTM 127
106
107static unsigned char e0_keys[128] = {
108 0, 0, 0, 0, 0, 0, 0, 0, /* 0x00-0x07 */
109 0, 0, 0, 0, 0, 0, 0, 0, /* 0x08-0x0f */
110 0, 0, 0, 0, 0, 0, 0, 0, /* 0x10-0x17 */
111 0, 0, 0, 0, E0_KPENTER, E0_RCTRL, 0, 0, /* 0x18-0x1f */
112 0, 0, 0, 0, 0, 0, 0, 0, /* 0x20-0x27 */
113 0, 0, 0, 0, 0, 0, 0, 0, /* 0x28-0x2f */
114 0, 0, 0, 0, 0, E0_KPSLASH, 0, E0_PRSCR, /* 0x30-0x37 */
115 E0_RALT, 0, 0, 0, 0, E0_F13, E0_F14, E0_HELP, /* 0x38-0x3f */
116 E0_DO, E0_F17, 0, 0, 0, 0, E0_BREAK, E0_HOME, /* 0x40-0x47 */
117 E0_UP, E0_PGUP, 0, E0_LEFT, E0_OK, E0_RIGHT, E0_KPMINPLUS, E0_END, /* 0x48-0x4f */
118 E0_DOWN, E0_PGDN, E0_INS, E0_DEL, 0, 0, 0, 0, /* 0x50-0x57 */
119 0, 0, 0, E0_MSLW, E0_MSRW, E0_MSTM, 0, 0, /* 0x58-0x5f */
120 0, 0, 0, 0, 0, 0, 0, 0, /* 0x60-0x67 */
121 0, 0, 0, 0, 0, 0, 0, E0_MACRO, /* 0x68-0x6f */
122 //0, 0, 0, 0, 0, 0, 0, 0, /* 0x70-0x77 */
123 0, 0, 0, 0, 0, E0_BACKSLASH, 0, 0, /* 0x70-0x77 */
124 0, 0, 0, E0_YEN, 0, 0, 0, 0 /* 0x78-0x7f */
125};
126
127static int gen_setkeycode(unsigned int scancode, unsigned int keycode)
128{
129 if (scancode < SC_LIM || scancode > 255 || keycode > 127)
130 return -EINVAL;
131 if (scancode < 128)
132 high_keys[scancode - SC_LIM] = keycode;
133 else
134 e0_keys[scancode - 128] = keycode;
135 return 0;
136}
137
138static int gen_getkeycode(unsigned int scancode)
139{
140 return
141 (scancode < SC_LIM || scancode > 255) ? -EINVAL :
142 (scancode <
143 128) ? high_keys[scancode - SC_LIM] : e0_keys[scancode - 128];
144}
145
146static int
147gen_translate(unsigned char scancode, unsigned char *keycode, char raw_mode)
148{
149 static int prev_scancode;
150
151 /* special prefix scancodes.. */
152 if (scancode == 0xe0 || scancode == 0xe1) {
153 prev_scancode = scancode;
154 return 0;
155 }
156
157 /* 0xFF is sent by a few keyboards, ignore it. 0x00 is error */
158 if (scancode == 0x00 || scancode == 0xff) {
159 prev_scancode = 0;
160 return 0;
161 }
162
163 scancode &= 0x7f;
164
165 if (prev_scancode) {
166 /*
167 * usually it will be 0xe0, but a Pause key generates
168 * e1 1d 45 e1 9d c5 when pressed, and nothing when released
169 */
170 if (prev_scancode != 0xe0) {
171 if (prev_scancode == 0xe1 && scancode == 0x1d) {
172 prev_scancode = 0x100;
173 return 0;
174 }
175 else if (prev_scancode == 0x100
176 && scancode == 0x45) {
177 *keycode = E1_PAUSE;
178 prev_scancode = 0;
179 } else {
180#ifdef KBD_REPORT_UNKN
181 if (!raw_mode)
182 printk(KERN_INFO
183 "keyboard: unknown e1 escape sequence\n");
184#endif
185 prev_scancode = 0;
186 return 0;
187 }
188 } else {
189 prev_scancode = 0;
190 /*
191 * The keyboard maintains its own internal caps lock and
192 * num lock statuses. In caps lock mode E0 AA precedes make
193 * code and E0 2A follows break code. In num lock mode,
194 * E0 2A precedes make code and E0 AA follows break code.
195 * We do our own book-keeping, so we will just ignore these.
196 */
197 /*
198 * For my keyboard there is no caps lock mode, but there are
199 * both Shift-L and Shift-R modes. The former mode generates
200 * E0 2A / E0 AA pairs, the latter E0 B6 / E0 36 pairs.
201 * So, we should also ignore the latter. - aeb@cwi.nl
202 */
203 if (scancode == 0x2a || scancode == 0x36)
204 return 0;
205
206 if (e0_keys[scancode])
207 *keycode = e0_keys[scancode];
208 else {
209#ifdef KBD_REPORT_UNKN
210 if (!raw_mode)
211 printk(KERN_INFO
212 "keyboard: unknown scancode e0 %02x\n",
213 scancode);
214#endif
215 return 0;
216 }
217 }
218 } else if (scancode >= SC_LIM) {
219 /* This happens with the FOCUS 9000 keyboard
220 Its keys PF1..PF12 are reported to generate
221 55 73 77 78 79 7a 7b 7c 74 7e 6d 6f
222 Moreover, unless repeated, they do not generate
223 key-down events, so we have to zero up_flag below */
224 /* Also, Japanese 86/106 keyboards are reported to
225 generate 0x73 and 0x7d for \ - and \ | respectively. */
226 /* Also, some Brazilian keyboard is reported to produce
227 0x73 and 0x7e for \ ? and KP-dot, respectively. */
228
229 *keycode = high_keys[scancode - SC_LIM];
230
231 if (!*keycode) {
232 if (!raw_mode) {
233#ifdef KBD_REPORT_UNKN
234 printk(KERN_INFO
235 "keyboard: unrecognized scancode (%02x)"
236 " - ignored\n", scancode);
237#endif
238 }
239 return 0;
240 }
241 } else
242 *keycode = scancode;
243 return 1;
244}
245
246static char gen_unexpected_up(unsigned char keycode)
247{
248 /* unexpected, but this can happen: maybe this was a key release for a
249 FOCUS 9000 PF key; if we want to see it, we have to clear up_flag */
250 if (keycode >= SC_LIM || keycode == 85)
251 return 0;
252 else
253 return 0200;
254}
255
256/*
257 * These are the default mappings
258 */
259int (*k_setkeycode)(unsigned int, unsigned int) = gen_setkeycode;
260int (*k_getkeycode)(unsigned int) = gen_getkeycode;
261int (*k_translate)(unsigned char, unsigned char *, char) = gen_translate;
262char (*k_unexpected_up)(unsigned char) = gen_unexpected_up;
263void (*k_leds)(unsigned char);
264
265/* Simple translation table for the SysRq keys */
266
267#ifdef CONFIG_MAGIC_SYSRQ
268static unsigned char gen_sysrq_xlate[128] =
269 "\000\0331234567890-=\177\t" /* 0x00 - 0x0f */
270 "qwertyuiop[]\r\000as" /* 0x10 - 0x1f */
271 "dfghjkl;'`\000\\zxcv" /* 0x20 - 0x2f */
272 "bnm,./\000*\000 \000\201\202\203\204\205" /* 0x30 - 0x3f */
273 "\206\207\210\211\212\000\000789-456+1" /* 0x40 - 0x4f */
274 "230\177\000\000\213\214\000\000\000\000\000\000\000\000\000\000" /* 0x50 - 0x5f */
275 "\r\000/"; /* 0x60 - 0x6f */
276
277unsigned char *k_sysrq_xlate = gen_sysrq_xlate;
278int k_sysrq_key = 0x54;
279#endif
diff --git a/arch/arm26/lib/lib1funcs.S b/arch/arm26/lib/lib1funcs.S
new file mode 100644
index 000000000000..b8f9518db871
--- /dev/null
+++ b/arch/arm26/lib/lib1funcs.S
@@ -0,0 +1,314 @@
1@ libgcc1 routines for ARM cpu.
2@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
3
4/* Copyright (C) 1995, 1996, 1998 Free Software Foundation, Inc.
5
6This file is free software; you can redistribute it and/or modify it
7under the terms of the GNU General Public License as published by the
8Free Software Foundation; either version 2, or (at your option) any
9later version.
10
11In addition to the permissions in the GNU General Public License, the
12Free Software Foundation gives you unlimited permission to link the
13compiled version of this file with other programs, and to distribute
14those programs without any restriction coming from the use of this
15file. (The General Public License restrictions do apply in other
16respects; for example, they cover modification of the file, and
17distribution when not linked into another program.)
18
19This file is distributed in the hope that it will be useful, but
20WITHOUT ANY WARRANTY; without even the implied warranty of
21MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22General Public License for more details.
23
24You should have received a copy of the GNU General Public License
25along with this program; see the file COPYING. If not, write to
26the Free Software Foundation, 59 Temple Place - Suite 330,
27Boston, MA 02111-1307, USA. */
28
29/* As a special exception, if you link this library with other files,
30 some of which are compiled with GCC, to produce an executable,
31 this library does not by itself cause the resulting executable
32 to be covered by the GNU General Public License.
33 This exception does not however invalidate any other reasons why
34 the executable file might be covered by the GNU General Public License.
35 */
36/* This code is derived from gcc 2.95.3 */
37/* I Molton 29/07/01 */
38
39#include <linux/linkage.h>
40#include <asm/assembler.h>
41#include <asm/hardware.h>
42#include <linux/config.h>
43
44#define RET movs
45#define RETc(x) mov##x##s
46#define RETCOND ^
47
48dividend .req r0
49divisor .req r1
50result .req r2
51overdone .req r2
52curbit .req r3
53ip .req r12
54sp .req r13
55lr .req r14
56pc .req r15
57
58ENTRY(__udivsi3)
59 cmp divisor, #0
60 beq Ldiv0
61 mov curbit, #1
62 mov result, #0
63 cmp dividend, divisor
64 bcc Lgot_result_udivsi3
651:
66 @ Unless the divisor is very big, shift it up in multiples of
67 @ four bits, since this is the amount of unwinding in the main
68 @ division loop. Continue shifting until the divisor is
69 @ larger than the dividend.
70 cmp divisor, #0x10000000
71 cmpcc divisor, dividend
72 movcc divisor, divisor, lsl #4
73 movcc curbit, curbit, lsl #4
74 bcc 1b
75
762:
77 @ For very big divisors, we must shift it a bit at a time, or
78 @ we will be in danger of overflowing.
79 cmp divisor, #0x80000000
80 cmpcc divisor, dividend
81 movcc divisor, divisor, lsl #1
82 movcc curbit, curbit, lsl #1
83 bcc 2b
84
853:
86 @ Test for possible subtractions, and note which bits
87 @ are done in the result. On the final pass, this may subtract
88 @ too much from the dividend, but the result will be ok, since the
89 @ "bit" will have been shifted out at the bottom.
90 cmp dividend, divisor
91 subcs dividend, dividend, divisor
92 orrcs result, result, curbit
93 cmp dividend, divisor, lsr #1
94 subcs dividend, dividend, divisor, lsr #1
95 orrcs result, result, curbit, lsr #1
96 cmp dividend, divisor, lsr #2
97 subcs dividend, dividend, divisor, lsr #2
98 orrcs result, result, curbit, lsr #2
99 cmp dividend, divisor, lsr #3
100 subcs dividend, dividend, divisor, lsr #3
101 orrcs result, result, curbit, lsr #3
102 cmp dividend, #0 @ Early termination?
103 movnes curbit, curbit, lsr #4 @ No, any more bits to do?
104 movne divisor, divisor, lsr #4
105 bne 3b
106Lgot_result_udivsi3:
107 mov r0, result
108 RET pc, lr
109
110Ldiv0:
111 str lr, [sp, #-4]!
112 bl __div0
113 mov r0, #0 @ about as wrong as it could be
114 ldmia sp!, {pc}RETCOND
115
116/* __umodsi3 ----------------------- */
117
118ENTRY(__umodsi3)
119 cmp divisor, #0
120 beq Ldiv0
121 mov curbit, #1
122 cmp dividend, divisor
123 RETc(cc) pc, lr
1241:
125 @ Unless the divisor is very big, shift it up in multiples of
126 @ four bits, since this is the amount of unwinding in the main
127 @ division loop. Continue shifting until the divisor is
128 @ larger than the dividend.
129 cmp divisor, #0x10000000
130 cmpcc divisor, dividend
131 movcc divisor, divisor, lsl #4
132 movcc curbit, curbit, lsl #4
133 bcc 1b
134
1352:
136 @ For very big divisors, we must shift it a bit at a time, or
137 @ we will be in danger of overflowing.
138 cmp divisor, #0x80000000
139 cmpcc divisor, dividend
140 movcc divisor, divisor, lsl #1
141 movcc curbit, curbit, lsl #1
142 bcc 2b
143
1443:
145 @ Test for possible subtractions. On the final pass, this may
146 @ subtract too much from the dividend, so keep track of which
147 @ subtractions are done, we can fix them up afterwards...
148 mov overdone, #0
149 cmp dividend, divisor
150 subcs dividend, dividend, divisor
151 cmp dividend, divisor, lsr #1
152 subcs dividend, dividend, divisor, lsr #1
153 orrcs overdone, overdone, curbit, ror #1
154 cmp dividend, divisor, lsr #2
155 subcs dividend, dividend, divisor, lsr #2
156 orrcs overdone, overdone, curbit, ror #2
157 cmp dividend, divisor, lsr #3
158 subcs dividend, dividend, divisor, lsr #3
159 orrcs overdone, overdone, curbit, ror #3
160 mov ip, curbit
161 cmp dividend, #0 @ Early termination?
162 movnes curbit, curbit, lsr #4 @ No, any more bits to do?
163 movne divisor, divisor, lsr #4
164 bne 3b
165
166 @ Any subtractions that we should not have done will be recorded in
167 @ the top three bits of "overdone". Exactly which were not needed
168 @ are governed by the position of the bit, stored in ip.
169 @ If we terminated early, because dividend became zero,
170 @ then none of the below will match, since the bit in ip will not be
171 @ in the bottom nibble.
172 ands overdone, overdone, #0xe0000000
173 RETc(eq) pc, lr @ No fixups needed
174 tst overdone, ip, ror #3
175 addne dividend, dividend, divisor, lsr #3
176 tst overdone, ip, ror #2
177 addne dividend, dividend, divisor, lsr #2
178 tst overdone, ip, ror #1
179 addne dividend, dividend, divisor, lsr #1
180 RET pc, lr
181
182ENTRY(__divsi3)
183 eor ip, dividend, divisor @ Save the sign of the result.
184 mov curbit, #1
185 mov result, #0
186 cmp divisor, #0
187 rsbmi divisor, divisor, #0 @ Loops below use unsigned.
188 beq Ldiv0
189 cmp dividend, #0
190 rsbmi dividend, dividend, #0
191 cmp dividend, divisor
192 bcc Lgot_result_divsi3
193
1941:
195 @ Unless the divisor is very big, shift it up in multiples of
196 @ four bits, since this is the amount of unwinding in the main
197 @ division loop. Continue shifting until the divisor is
198 @ larger than the dividend.
199 cmp divisor, #0x10000000
200 cmpcc divisor, dividend
201 movcc divisor, divisor, lsl #4
202 movcc curbit, curbit, lsl #4
203 bcc 1b
204
2052:
206 @ For very big divisors, we must shift it a bit at a time, or
207 @ we will be in danger of overflowing.
208 cmp divisor, #0x80000000
209 cmpcc divisor, dividend
210 movcc divisor, divisor, lsl #1
211 movcc curbit, curbit, lsl #1
212 bcc 2b
213
2143:
215 @ Test for possible subtractions, and note which bits
216 @ are done in the result. On the final pass, this may subtract
217 @ too much from the dividend, but the result will be ok, since the
218 @ "bit" will have been shifted out at the bottom.
219 cmp dividend, divisor
220 subcs dividend, dividend, divisor
221 orrcs result, result, curbit
222 cmp dividend, divisor, lsr #1
223 subcs dividend, dividend, divisor, lsr #1
224 orrcs result, result, curbit, lsr #1
225 cmp dividend, divisor, lsr #2
226 subcs dividend, dividend, divisor, lsr #2
227 orrcs result, result, curbit, lsr #2
228 cmp dividend, divisor, lsr #3
229 subcs dividend, dividend, divisor, lsr #3
230 orrcs result, result, curbit, lsr #3
231 cmp dividend, #0 @ Early termination?
232 movnes curbit, curbit, lsr #4 @ No, any more bits to do?
233 movne divisor, divisor, lsr #4
234 bne 3b
235Lgot_result_divsi3:
236 mov r0, result
237 cmp ip, #0
238 rsbmi r0, r0, #0
239 RET pc, lr
240
241ENTRY(__modsi3)
242 mov curbit, #1
243 cmp divisor, #0
244 rsbmi divisor, divisor, #0 @ Loops below use unsigned.
245 beq Ldiv0
246 @ Need to save the sign of the dividend, unfortunately, we need
247 @ ip later on; this is faster than pushing lr and using that.
248 str dividend, [sp, #-4]!
249 cmp dividend, #0
250 rsbmi dividend, dividend, #0
251 cmp dividend, divisor
252 bcc Lgot_result_modsi3
253
2541:
255 @ Unless the divisor is very big, shift it up in multiples of
256 @ four bits, since this is the amount of unwinding in the main
257 @ division loop. Continue shifting until the divisor is
258 @ larger than the dividend.
259 cmp divisor, #0x10000000
260 cmpcc divisor, dividend
261 movcc divisor, divisor, lsl #4
262 movcc curbit, curbit, lsl #4
263 bcc 1b
264
2652:
266 @ For very big divisors, we must shift it a bit at a time, or
267 @ we will be in danger of overflowing.
268 cmp divisor, #0x80000000
269 cmpcc divisor, dividend
270 movcc divisor, divisor, lsl #1
271 movcc curbit, curbit, lsl #1
272 bcc 2b
273
2743:
275 @ Test for possible subtractions. On the final pass, this may
276 @ subtract too much from the dividend, so keep track of which
277 @ subtractions are done, we can fix them up afterwards...
278 mov overdone, #0
279 cmp dividend, divisor
280 subcs dividend, dividend, divisor
281 cmp dividend, divisor, lsr #1
282 subcs dividend, dividend, divisor, lsr #1
283 orrcs overdone, overdone, curbit, ror #1
284 cmp dividend, divisor, lsr #2
285 subcs dividend, dividend, divisor, lsr #2
286 orrcs overdone, overdone, curbit, ror #2
287 cmp dividend, divisor, lsr #3
288 subcs dividend, dividend, divisor, lsr #3
289 orrcs overdone, overdone, curbit, ror #3
290 mov ip, curbit
291 cmp dividend, #0 @ Early termination?
292 movnes curbit, curbit, lsr #4 @ No, any more bits to do?
293 movne divisor, divisor, lsr #4
294 bne 3b
295
296 @ Any subtractions that we should not have done will be recorded in
297 @ the top three bits of "overdone". Exactly which were not needed
298 @ are governed by the position of the bit, stored in ip.
299 @ If we terminated early, because dividend became zero,
300 @ then none of the below will match, since the bit in ip will not be
301 @ in the bottom nibble.
302 ands overdone, overdone, #0xe0000000
303 beq Lgot_result_modsi3
304 tst overdone, ip, ror #3
305 addne dividend, dividend, divisor, lsr #3
306 tst overdone, ip, ror #2
307 addne dividend, dividend, divisor, lsr #2
308 tst overdone, ip, ror #1
309 addne dividend, dividend, divisor, lsr #1
310Lgot_result_modsi3:
311 ldr ip, [sp], #4
312 cmp ip, #0
313 rsbmi dividend, dividend, #0
314 RET pc, lr
diff --git a/arch/arm26/lib/longlong.h b/arch/arm26/lib/longlong.h
new file mode 100644
index 000000000000..05ec1abd6a2c
--- /dev/null
+++ b/arch/arm26/lib/longlong.h
@@ -0,0 +1,184 @@
1/* longlong.h -- based on code from gcc-2.95.3
2
3 definitions for mixed size 32/64 bit arithmetic.
4 Copyright (C) 1991, 92, 94, 95, 96, 1997, 1998 Free Software Foundation, Inc.
5
6 This definition file is free software; you can redistribute it
7 and/or modify it under the terms of the GNU General Public
8 License as published by the Free Software Foundation; either
9 version 2, or (at your option) any later version.
10
11 This definition file is distributed in the hope that it will be
12 useful, but WITHOUT ANY WARRANTY; without even the implied
13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 See the GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
20
21/* Borrowed from GCC 2.95.3, I Molton 29/07/01 */
22
23#ifndef SI_TYPE_SIZE
24#define SI_TYPE_SIZE 32
25#endif
26
27#define __BITS4 (SI_TYPE_SIZE / 4)
28#define __ll_B (1L << (SI_TYPE_SIZE / 2))
29#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
30#define __ll_highpart(t) ((USItype) (t) / __ll_B)
31
32/* Define auxiliary asm macros.
33
34 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand)
35 multiplies two USItype integers MULTIPLER and MULTIPLICAND,
36 and generates a two-part USItype product in HIGH_PROD and
37 LOW_PROD.
38
39 2) __umulsidi3(a,b) multiplies two USItype integers A and B,
40 and returns a UDItype product. This is just a variant of umul_ppmm.
41
42 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
43 denominator) divides a two-word unsigned integer, composed by the
44 integers HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and
45 places the quotient in QUOTIENT and the remainder in REMAINDER.
46 HIGH_NUMERATOR must be less than DENOMINATOR for correct operation.
47 If, in addition, the most significant bit of DENOMINATOR must be 1,
48 then the pre-processor symbol UDIV_NEEDS_NORMALIZATION is defined to 1.
49
50 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
51 denominator). Like udiv_qrnnd but the numbers are signed. The
52 quotient is rounded towards 0.
53
54 5) count_leading_zeros(count, x) counts the number of zero-bits from
55 the msb to the first non-zero bit. This is the number of steps X
56 needs to be shifted left to set the msb. Undefined for X == 0.
57
58 6) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
59 high_addend_2, low_addend_2) adds two two-word unsigned integers,
60 composed by HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and
61 LOW_ADDEND_2 respectively. The result is placed in HIGH_SUM and
62 LOW_SUM. Overflow (i.e. carry out) is not stored anywhere, and is
63 lost.
64
65 7) sub_ddmmss(high_difference, low_difference, high_minuend,
66 low_minuend, high_subtrahend, low_subtrahend) subtracts two
67 two-word unsigned integers, composed by HIGH_MINUEND_1 and
68 LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and LOW_SUBTRAHEND_2
69 respectively. The result is placed in HIGH_DIFFERENCE and
70 LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
71 and is lost.
72
73 If any of these macros are left undefined for a particular CPU,
74 C macros are used. */
75
76#if defined (__arm__)
77#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
78 __asm__ ("adds %1, %4, %5 \n\
79 adc %0, %2, %3" \
80 : "=r" ((USItype) (sh)), \
81 "=&r" ((USItype) (sl)) \
82 : "%r" ((USItype) (ah)), \
83 "rI" ((USItype) (bh)), \
84 "%r" ((USItype) (al)), \
85 "rI" ((USItype) (bl)))
86#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
87 __asm__ ("subs %1, %4, %5 \n\
88 sbc %0, %2, %3" \
89 : "=r" ((USItype) (sh)), \
90 "=&r" ((USItype) (sl)) \
91 : "r" ((USItype) (ah)), \
92 "rI" ((USItype) (bh)), \
93 "r" ((USItype) (al)), \
94 "rI" ((USItype) (bl)))
95#define umul_ppmm(xh, xl, a, b) \
96{register USItype __t0, __t1, __t2; \
97 __asm__ ("%@ Inlined umul_ppmm \n\
98 mov %2, %5, lsr #16 \n\
99 mov %0, %6, lsr #16 \n\
100 bic %3, %5, %2, lsl #16 \n\
101 bic %4, %6, %0, lsl #16 \n\
102 mul %1, %3, %4 \n\
103 mul %4, %2, %4 \n\
104 mul %3, %0, %3 \n\
105 mul %0, %2, %0 \n\
106 adds %3, %4, %3 \n\
107 addcs %0, %0, #65536 \n\
108 adds %1, %1, %3, lsl #16 \n\
109 adc %0, %0, %3, lsr #16" \
110 : "=&r" ((USItype) (xh)), \
111 "=r" ((USItype) (xl)), \
112 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
113 : "r" ((USItype) (a)), \
114 "r" ((USItype) (b)));}
115#define UMUL_TIME 20
116#define UDIV_TIME 100
117#endif /* __arm__ */
118
119#define __umulsidi3(u, v) \
120 ({DIunion __w; \
121 umul_ppmm (__w.s.high, __w.s.low, u, v); \
122 __w.ll; })
123
124#define __udiv_qrnnd_c(q, r, n1, n0, d) \
125 do { \
126 USItype __d1, __d0, __q1, __q0; \
127 USItype __r1, __r0, __m; \
128 __d1 = __ll_highpart (d); \
129 __d0 = __ll_lowpart (d); \
130 \
131 __r1 = (n1) % __d1; \
132 __q1 = (n1) / __d1; \
133 __m = (USItype) __q1 * __d0; \
134 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
135 if (__r1 < __m) \
136 { \
137 __q1--, __r1 += (d); \
138 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
139 if (__r1 < __m) \
140 __q1--, __r1 += (d); \
141 } \
142 __r1 -= __m; \
143 \
144 __r0 = __r1 % __d1; \
145 __q0 = __r1 / __d1; \
146 __m = (USItype) __q0 * __d0; \
147 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
148 if (__r0 < __m) \
149 { \
150 __q0--, __r0 += (d); \
151 if (__r0 >= (d)) \
152 if (__r0 < __m) \
153 __q0--, __r0 += (d); \
154 } \
155 __r0 -= __m; \
156 \
157 (q) = (USItype) __q1 * __ll_B | __q0; \
158 (r) = __r0; \
159 } while (0)
160
161#define UDIV_NEEDS_NORMALIZATION 1
162#define udiv_qrnnd __udiv_qrnnd_c
163
164extern const UQItype __clz_tab[];
165#define count_leading_zeros(count, x) \
166 do { \
167 USItype __xr = (x); \
168 USItype __a; \
169 \
170 if (SI_TYPE_SIZE <= 32) \
171 { \
172 __a = __xr < ((USItype)1<<2*__BITS4) \
173 ? (__xr < ((USItype)1<<__BITS4) ? 0 : __BITS4) \
174 : (__xr < ((USItype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
175 } \
176 else \
177 { \
178 for (__a = SI_TYPE_SIZE - 8; __a > 0; __a -= 8) \
179 if (((__xr >> __a) & 0xff) != 0) \
180 break; \
181 } \
182 \
183 (count) = SI_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
184 } while (0)
diff --git a/arch/arm26/lib/lshrdi3.c b/arch/arm26/lib/lshrdi3.c
new file mode 100644
index 000000000000..b666f1bad451
--- /dev/null
+++ b/arch/arm26/lib/lshrdi3.c
@@ -0,0 +1,61 @@
1/* More subroutines needed by GCC output code on some machines. */
2/* Compile this one with gcc. */
3/* Copyright (C) 1989, 92-98, 1999 Free Software Foundation, Inc.
4
5This file is part of GNU CC.
6
7GNU CC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12GNU CC is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GNU CC; see the file COPYING. If not, write to
19the Free Software Foundation, 59 Temple Place - Suite 330,
20Boston, MA 02111-1307, USA. */
21
22/* As a special exception, if you link this library with other files,
23 some of which are compiled with GCC, to produce an executable,
24 this library does not by itself cause the resulting executable
25 to be covered by the GNU General Public License.
26 This exception does not however invalidate any other reasons why
27 the executable file might be covered by the GNU General Public License.
28 */
29/* support functions required by the kernel. based on code from gcc-2.95.3 */
30/* I Molton 29/07/01 */
31
32#include "gcclib.h"
33
34DItype
35__lshrdi3 (DItype u, word_type b)
36{
37 DIunion w;
38 word_type bm;
39 DIunion uu;
40
41 if (b == 0)
42 return u;
43
44 uu.ll = u;
45
46 bm = (sizeof (SItype) * BITS_PER_UNIT) - b;
47 if (bm <= 0)
48 {
49 w.s.high = 0;
50 w.s.low = (USItype)uu.s.high >> -bm;
51 }
52 else
53 {
54 USItype carries = (USItype)uu.s.high << bm;
55 w.s.high = (USItype)uu.s.high >> b;
56 w.s.low = ((USItype)uu.s.low >> b) | carries;
57 }
58
59 return w.ll;
60}
61
diff --git a/arch/arm26/lib/memchr.S b/arch/arm26/lib/memchr.S
new file mode 100644
index 000000000000..34e7c14c08ad
--- /dev/null
+++ b/arch/arm26/lib/memchr.S
@@ -0,0 +1,25 @@
1/*
2 * linux/arch/arm26/lib/memchr.S
3 *
4 * Copyright (C) 1995-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * ASM optimised string functions
11 */
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14
15 .text
16 .align 5
17ENTRY(memchr)
181: subs r2, r2, #1
19 bmi 2f
20 ldrb r3, [r0], #1
21 teq r3, r1
22 bne 1b
23 sub r0, r0, #1
242: movne r0, #0
25 RETINSTR(mov,pc,lr)
diff --git a/arch/arm26/lib/memcpy.S b/arch/arm26/lib/memcpy.S
new file mode 100644
index 000000000000..3f719e412069
--- /dev/null
+++ b/arch/arm26/lib/memcpy.S
@@ -0,0 +1,318 @@
1/*
2 * linux/arch/arm26/lib/memcpy.S
3 *
4 * Copyright (C) 1995-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * ASM optimised string functions
11 */
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14
15 .text
16
17#define ENTER \
18 mov ip,sp ;\
19 stmfd sp!,{r4-r9,fp,ip,lr,pc} ;\
20 sub fp,ip,#4
21
22#define EXIT \
23 LOADREGS(ea, fp, {r4 - r9, fp, sp, pc})
24
25#define EXITEQ \
26 LOADREGS(eqea, fp, {r4 - r9, fp, sp, pc})
27
28/*
29 * Prototype: void memcpy(void *to,const void *from,unsigned long n);
30 * ARM3: cant use memcopy here!!!
31 */
32ENTRY(memcpy)
33ENTRY(memmove)
34 ENTER
35 cmp r1, r0
36 bcc 19f
37 subs r2, r2, #4
38 blt 6f
39 ands ip, r0, #3
40 bne 7f
41 ands ip, r1, #3
42 bne 8f
43
441: subs r2, r2, #8
45 blt 5f
46 subs r2, r2, #0x14
47 blt 3f
482: ldmia r1!,{r3 - r9, ip}
49 stmia r0!,{r3 - r9, ip}
50 subs r2, r2, #32
51 bge 2b
52 cmn r2, #16
53 ldmgeia r1!, {r3 - r6}
54 stmgeia r0!, {r3 - r6}
55 subge r2, r2, #0x10
563: adds r2, r2, #0x14
574: ldmgeia r1!, {r3 - r5}
58 stmgeia r0!, {r3 - r5}
59 subges r2, r2, #12
60 bge 4b
615: adds r2, r2, #8
62 blt 6f
63 subs r2, r2, #4
64 ldrlt r3, [r1], #4
65 ldmgeia r1!, {r4, r5}
66 strlt r3, [r0], #4
67 stmgeia r0!, {r4, r5}
68 subge r2, r2, #4
69
706: adds r2, r2, #4
71 EXITEQ
72 cmp r2, #2
73 ldrb r3, [r1], #1
74 ldrgeb r4, [r1], #1
75 ldrgtb r5, [r1], #1
76 strb r3, [r0], #1
77 strgeb r4, [r0], #1
78 strgtb r5, [r0], #1
79 EXIT
80
817: rsb ip, ip, #4
82 cmp ip, #2
83 ldrb r3, [r1], #1
84 ldrgeb r4, [r1], #1
85 ldrgtb r5, [r1], #1
86 strb r3, [r0], #1
87 strgeb r4, [r0], #1
88 strgtb r5, [r0], #1
89 subs r2, r2, ip
90 blt 6b
91 ands ip, r1, #3
92 beq 1b
93
948: bic r1, r1, #3
95 ldr r7, [r1], #4
96 cmp ip, #2
97 bgt 15f
98 beq 11f
99 cmp r2, #12
100 blt 10f
101 sub r2, r2, #12
1029: mov r3, r7, pull #8
103 ldmia r1!, {r4 - r7}
104 orr r3, r3, r4, push #24
105 mov r4, r4, pull #8
106 orr r4, r4, r5, push #24
107 mov r5, r5, pull #8
108 orr r5, r5, r6, push #24
109 mov r6, r6, pull #8
110 orr r6, r6, r7, push #24
111 stmia r0!, {r3 - r6}
112 subs r2, r2, #16
113 bge 9b
114 adds r2, r2, #12
115 blt 100f
11610: mov r3, r7, pull #8
117 ldr r7, [r1], #4
118 subs r2, r2, #4
119 orr r3, r3, r7, push #24
120 str r3, [r0], #4
121 bge 10b
122100: sub r1, r1, #3
123 b 6b
124
12511: cmp r2, #12
126 blt 13f /* */
127 sub r2, r2, #12
12812: mov r3, r7, pull #16
129 ldmia r1!, {r4 - r7}
130 orr r3, r3, r4, push #16
131 mov r4, r4, pull #16
132 orr r4, r4, r5, push #16
133 mov r5, r5, pull #16
134 orr r5, r5, r6, push #16
135 mov r6, r6, pull #16
136 orr r6, r6, r7, push #16
137 stmia r0!, {r3 - r6}
138 subs r2, r2, #16
139 bge 12b
140 adds r2, r2, #12
141 blt 14f
14213: mov r3, r7, pull #16
143 ldr r7, [r1], #4
144 subs r2, r2, #4
145 orr r3, r3, r7, push #16
146 str r3, [r0], #4
147 bge 13b
14814: sub r1, r1, #2
149 b 6b
150
15115: cmp r2, #12
152 blt 17f
153 sub r2, r2, #12
15416: mov r3, r7, pull #24
155 ldmia r1!, {r4 - r7}
156 orr r3, r3, r4, push #8
157 mov r4, r4, pull #24
158 orr r4, r4, r5, push #8
159 mov r5, r5, pull #24
160 orr r5, r5, r6, push #8
161 mov r6, r6, pull #24
162 orr r6, r6, r7, push #8
163 stmia r0!, {r3 - r6}
164 subs r2, r2, #16
165 bge 16b
166 adds r2, r2, #12
167 blt 18f
16817: mov r3, r7, pull #24
169 ldr r7, [r1], #4
170 subs r2, r2, #4
171 orr r3, r3, r7, push #8
172 str r3, [r0], #4
173 bge 17b
17418: sub r1, r1, #1
175 b 6b
176
177
17819: add r1, r1, r2
179 add r0, r0, r2
180 subs r2, r2, #4
181 blt 24f
182 ands ip, r0, #3
183 bne 25f
184 ands ip, r1, #3
185 bne 26f
186
18720: subs r2, r2, #8
188 blt 23f
189 subs r2, r2, #0x14
190 blt 22f
19121: ldmdb r1!, {r3 - r9, ip}
192 stmdb r0!, {r3 - r9, ip}
193 subs r2, r2, #32
194 bge 21b
19522: cmn r2, #16
196 ldmgedb r1!, {r3 - r6}
197 stmgedb r0!, {r3 - r6}
198 subge r2, r2, #16
199 adds r2, r2, #20
200 ldmgedb r1!, {r3 - r5}
201 stmgedb r0!, {r3 - r5}
202 subge r2, r2, #12
20323: adds r2, r2, #8
204 blt 24f
205 subs r2, r2, #4
206 ldrlt r3, [r1, #-4]!
207 ldmgedb r1!, {r4, r5}
208 strlt r3, [r0, #-4]!
209 stmgedb r0!, {r4, r5}
210 subge r2, r2, #4
211
21224: adds r2, r2, #4
213 EXITEQ
214 cmp r2, #2
215 ldrb r3, [r1, #-1]!
216 ldrgeb r4, [r1, #-1]!
217 ldrgtb r5, [r1, #-1]!
218 strb r3, [r0, #-1]!
219 strgeb r4, [r0, #-1]!
220 strgtb r5, [r0, #-1]!
221 EXIT
222
22325: cmp ip, #2
224 ldrb r3, [r1, #-1]!
225 ldrgeb r4, [r1, #-1]!
226 ldrgtb r5, [r1, #-1]!
227 strb r3, [r0, #-1]!
228 strgeb r4, [r0, #-1]!
229 strgtb r5, [r0, #-1]!
230 subs r2, r2, ip
231 blt 24b
232 ands ip, r1, #3
233 beq 20b
234
23526: bic r1, r1, #3
236 ldr r3, [r1], #0
237 cmp ip, #2
238 blt 34f
239 beq 30f
240 cmp r2, #12
241 blt 28f
242 sub r2, r2, #12
24327: mov r7, r3, push #8
244 ldmdb r1!, {r3, r4, r5, r6}
245 orr r7, r7, r6, pull #24
246 mov r6, r6, push #8
247 orr r6, r6, r5, pull #24
248 mov r5, r5, push #8
249 orr r5, r5, r4, pull #24
250 mov r4, r4, push #8
251 orr r4, r4, r3, pull #24
252 stmdb r0!, {r4, r5, r6, r7}
253 subs r2, r2, #16
254 bge 27b
255 adds r2, r2, #12
256 blt 29f
25728: mov ip, r3, push #8
258 ldr r3, [r1, #-4]!
259 subs r2, r2, #4
260 orr ip, ip, r3, pull #24
261 str ip, [r0, #-4]!
262 bge 28b
26329: add r1, r1, #3
264 b 24b
265
26630: cmp r2, #12
267 blt 32f
268 sub r2, r2, #12
26931: mov r7, r3, push #16
270 ldmdb r1!, {r3, r4, r5, r6}
271 orr r7, r7, r6, pull #16
272 mov r6, r6, push #16
273 orr r6, r6, r5, pull #16
274 mov r5, r5, push #16
275 orr r5, r5, r4, pull #16
276 mov r4, r4, push #16
277 orr r4, r4, r3, pull #16
278 stmdb r0!, {r4, r5, r6, r7}
279 subs r2, r2, #16
280 bge 31b
281 adds r2, r2, #12
282 blt 33f
28332: mov ip, r3, push #16
284 ldr r3, [r1, #-4]!
285 subs r2, r2, #4
286 orr ip, ip, r3, pull #16
287 str ip, [r0, #-4]!
288 bge 32b
28933: add r1, r1, #2
290 b 24b
291
29234: cmp r2, #12
293 blt 36f
294 sub r2, r2, #12
29535: mov r7, r3, push #24
296 ldmdb r1!, {r3, r4, r5, r6}
297 orr r7, r7, r6, pull #8
298 mov r6, r6, push #24
299 orr r6, r6, r5, pull #8
300 mov r5, r5, push #24
301 orr r5, r5, r4, pull #8
302 mov r4, r4, push #24
303 orr r4, r4, r3, pull #8
304 stmdb r0!, {r4, r5, r6, r7}
305 subs r2, r2, #16
306 bge 35b
307 adds r2, r2, #12
308 blt 37f
30936: mov ip, r3, push #24
310 ldr r3, [r1, #-4]!
311 subs r2, r2, #4
312 orr ip, ip, r3, pull #8
313 str ip, [r0, #-4]!
314 bge 36b
31537: add r1, r1, #1
316 b 24b
317
318 .align
diff --git a/arch/arm26/lib/memset.S b/arch/arm26/lib/memset.S
new file mode 100644
index 000000000000..aedec10b58f5
--- /dev/null
+++ b/arch/arm26/lib/memset.S
@@ -0,0 +1,80 @@
1/*
2 * linux/arch/arm26/lib/memset.S
3 *
4 * Copyright (C) 1995-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * ASM optimised string functions
11 */
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14
15 .text
16 .align 5
17 .word 0
18
191: subs r2, r2, #4 @ 1 do we have enough
20 blt 5f @ 1 bytes to align with?
21 cmp r3, #2 @ 1
22 strltb r1, [r0], #1 @ 1
23 strleb r1, [r0], #1 @ 1
24 strb r1, [r0], #1 @ 1
25 add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
26/*
27 * The pointer is now aligned and the length is adjusted. Try doing the
28 * memzero again.
29 */
30
31ENTRY(memset)
32 ands r3, r0, #3 @ 1 unaligned?
33 bne 1b @ 1
34/*
35 * we know that the pointer in r0 is aligned to a word boundary.
36 */
37 orr r1, r1, r1, lsl #8
38 orr r1, r1, r1, lsl #16
39 mov r3, r1
40 cmp r2, #16
41 blt 4f
42/*
43 * We need an extra register for this loop - save the return address and
44 * use the LR
45 */
46 str lr, [sp, #-4]!
47 mov ip, r1
48 mov lr, r1
49
502: subs r2, r2, #64
51 stmgeia r0!, {r1, r3, ip, lr} @ 64 bytes at a time.
52 stmgeia r0!, {r1, r3, ip, lr}
53 stmgeia r0!, {r1, r3, ip, lr}
54 stmgeia r0!, {r1, r3, ip, lr}
55 bgt 2b
56 LOADREGS(eqfd, sp!, {pc}) @ Now <64 bytes to go.
57/*
58 * No need to correct the count; we're only testing bits from now on
59 */
60 tst r2, #32
61 stmneia r0!, {r1, r3, ip, lr}
62 stmneia r0!, {r1, r3, ip, lr}
63 tst r2, #16
64 stmneia r0!, {r1, r3, ip, lr}
65 ldr lr, [sp], #4
66
674: tst r2, #8
68 stmneia r0!, {r1, r3}
69 tst r2, #4
70 strne r1, [r0], #4
71/*
72 * When we get here, we've got less than 4 bytes to zero. We
73 * may have an unaligned pointer as well.
74 */
755: tst r2, #2
76 strneb r1, [r0], #1
77 strneb r1, [r0], #1
78 tst r2, #1
79 strneb r1, [r0], #1
80 RETINSTR(mov,pc,lr)
diff --git a/arch/arm26/lib/memzero.S b/arch/arm26/lib/memzero.S
new file mode 100644
index 000000000000..cc5bf6860061
--- /dev/null
+++ b/arch/arm26/lib/memzero.S
@@ -0,0 +1,80 @@
1/*
2 * linux/arch/arm26/lib/memzero.S
3 *
4 * Copyright (C) 1995-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12
13 .text
14 .align 5
15 .word 0
16/*
17 * Align the pointer in r0. r3 contains the number of bytes that we are
18 * mis-aligned by, and r1 is the number of bytes. If r1 < 4, then we
19 * don't bother; we use byte stores instead.
20 */
211: subs r1, r1, #4 @ 1 do we have enough
22 blt 5f @ 1 bytes to align with?
23 cmp r3, #2 @ 1
24 strltb r2, [r0], #1 @ 1
25 strleb r2, [r0], #1 @ 1
26 strb r2, [r0], #1 @ 1
27 add r1, r1, r3 @ 1 (r1 = r1 - (4 - r3))
28/*
29 * The pointer is now aligned and the length is adjusted. Try doing the
30 * memzero again.
31 */
32
33ENTRY(__memzero)
34 mov r2, #0 @ 1
35 ands r3, r0, #3 @ 1 unaligned?
36 bne 1b @ 1
37/*
38 * r3 = 0, and we know that the pointer in r0 is aligned to a word boundary.
39 */
40 cmp r1, #16 @ 1 we can skip this chunk if we
41 blt 4f @ 1 have < 16 bytes
42/*
43 * We need an extra register for this loop - save the return address and
44 * use the LR
45 */
46 str lr, [sp, #-4]! @ 1
47 mov ip, r2 @ 1
48 mov lr, r2 @ 1
49
503: subs r1, r1, #64 @ 1 write 32 bytes out per loop
51 stmgeia r0!, {r2, r3, ip, lr} @ 4
52 stmgeia r0!, {r2, r3, ip, lr} @ 4
53 stmgeia r0!, {r2, r3, ip, lr} @ 4
54 stmgeia r0!, {r2, r3, ip, lr} @ 4
55 bgt 3b @ 1
56 LOADREGS(eqfd, sp!, {pc}) @ 1/2 quick exit
57/*
58 * No need to correct the count; we're only testing bits from now on
59 */
60 tst r1, #32 @ 1
61 stmneia r0!, {r2, r3, ip, lr} @ 4
62 stmneia r0!, {r2, r3, ip, lr} @ 4
63 tst r1, #16 @ 1 16 bytes or more?
64 stmneia r0!, {r2, r3, ip, lr} @ 4
65 ldr lr, [sp], #4 @ 1
66
674: tst r1, #8 @ 1 8 bytes or more?
68 stmneia r0!, {r2, r3} @ 2
69 tst r1, #4 @ 1 4 bytes or more?
70 strne r2, [r0], #4 @ 1
71/*
72 * When we get here, we've got less than 4 bytes to zero. We
73 * may have an unaligned pointer as well.
74 */
755: tst r1, #2 @ 1 2 bytes or more?
76 strneb r2, [r0], #1 @ 1
77 strneb r2, [r0], #1 @ 1
78 tst r1, #1 @ 1 a byte left over
79 strneb r2, [r0], #1 @ 1
80 RETINSTR(mov,pc,lr) @ 1
diff --git a/arch/arm26/lib/muldi3.c b/arch/arm26/lib/muldi3.c
new file mode 100644
index 000000000000..44d611b1cfdb
--- /dev/null
+++ b/arch/arm26/lib/muldi3.c
@@ -0,0 +1,77 @@
1/* More subroutines needed by GCC output code on some machines. */
2/* Compile this one with gcc. */
3/* Copyright (C) 1989, 92-98, 1999 Free Software Foundation, Inc.
4
5This file is part of GNU CC.
6
7GNU CC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12GNU CC is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GNU CC; see the file COPYING. If not, write to
19the Free Software Foundation, 59 Temple Place - Suite 330,
20Boston, MA 02111-1307, USA. */
21
22/* As a special exception, if you link this library with other files,
23 some of which are compiled with GCC, to produce an executable,
24 this library does not by itself cause the resulting executable
25 to be covered by the GNU General Public License.
26 This exception does not however invalidate any other reasons why
27 the executable file might be covered by the GNU General Public License.
28 */
29/* support functions required by the kernel. based on code from gcc-2.95.3 */
30/* I Molton 29/07/01 */
31
32#include "gcclib.h"
33
34#define umul_ppmm(xh, xl, a, b) \
35{register USItype __t0, __t1, __t2; \
36 __asm__ ("%@ Inlined umul_ppmm \n\
37 mov %2, %5, lsr #16 \n\
38 mov %0, %6, lsr #16 \n\
39 bic %3, %5, %2, lsl #16 \n\
40 bic %4, %6, %0, lsl #16 \n\
41 mul %1, %3, %4 \n\
42 mul %4, %2, %4 \n\
43 mul %3, %0, %3 \n\
44 mul %0, %2, %0 \n\
45 adds %3, %4, %3 \n\
46 addcs %0, %0, #65536 \n\
47 adds %1, %1, %3, lsl #16 \n\
48 adc %0, %0, %3, lsr #16" \
49 : "=&r" ((USItype) (xh)), \
50 "=r" ((USItype) (xl)), \
51 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
52 : "r" ((USItype) (a)), \
53 "r" ((USItype) (b)));}
54
55
56#define __umulsidi3(u, v) \
57 ({DIunion __w; \
58 umul_ppmm (__w.s.high, __w.s.low, u, v); \
59 __w.ll; })
60
61
62DItype
63__muldi3 (DItype u, DItype v)
64{
65 DIunion w;
66 DIunion uu, vv;
67
68 uu.ll = u,
69 vv.ll = v;
70
71 w.ll = __umulsidi3 (uu.s.low, vv.s.low);
72 w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
73 + (USItype) uu.s.high * (USItype) vv.s.low);
74
75 return w.ll;
76}
77
diff --git a/arch/arm26/lib/putuser.S b/arch/arm26/lib/putuser.S
new file mode 100644
index 000000000000..87588cbe46ae
--- /dev/null
+++ b/arch/arm26/lib/putuser.S
@@ -0,0 +1,109 @@
1/*
2 * linux/arch/arm26/lib/putuser.S
3 *
4 * Copyright (C) 2001 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Idea from x86 version, (C) Copyright 1998 Linus Torvalds
11 *
12 * These functions have a non-standard call interface to make
13 * them more efficient, especially as they return an error
14 * value in addition to the "real" return value.
15 *
16 * __put_user_X
17 *
18 * Inputs: r0 contains the address
19 * r1, r2 contains the value
20 * Outputs: r0 is the error code
21 * lr corrupted
22 *
23 * No other registers must be altered. (see include/asm-arm/uaccess.h
24 * for specific ASM register usage).
25 *
26 * Note that ADDR_LIMIT is either 0 or 0xc0000000
27 * Note also that it is intended that __put_user_bad is not global.
28 */
29#include <asm/asm_offsets.h>
30#include <asm/thread_info.h>
31#include <asm/errno.h>
32
33 .global __put_user_1
34__put_user_1:
35 bic r2, sp, #0x1f00
36 bic r2, r2, #0x00ff
37 str lr, [sp, #-4]!
38 ldr r2, [r2, #TI_ADDR_LIMIT]
39 sub r2, r2, #1
40 cmp r0, r2
41 bge __put_user_bad
421: cmp r0, #0x02000000
43 strlsbt r1, [r0]
44 strgeb r1, [r0]
45 mov r0, #0
46 ldmfd sp!, {pc}^
47
48 .global __put_user_2
49__put_user_2:
50 bic r2, sp, #0x1f00
51 bic r2, r2, #0x00ff
52 str lr, [sp, #-4]!
53 ldr r2, [r2, #TI_ADDR_LIMIT]
54 sub r2, r2, #2
55 cmp r0, r2
56 bge __put_user_bad
572: cmp r0, #0x02000000
58 strlsbt r1, [r0], #1
59 strgeb r1, [r0], #1
60 mov r1, r1, lsr #8
613: strlsbt r1, [r0]
62 strgeb r1, [r0]
63 mov r0, #0
64 ldmfd sp!, {pc}^
65
66 .global __put_user_4
67__put_user_4:
68 bic r2, sp, #0x1f00
69 bic r2, r2, #0x00ff
70 str lr, [sp, #-4]!
71 ldr r2, [r2, #TI_ADDR_LIMIT]
72 sub r2, r2, #4
73 cmp r0, r2
744: bge __put_user_bad
75 cmp r0, #0x02000000
76 strlst r1, [r0]
77 strge r1, [r0]
78 mov r0, #0
79 ldmfd sp!, {pc}^
80
81 .global __put_user_8
82__put_user_8:
83 bic ip, sp, #0x1f00
84 bic ip, ip, #0x00ff
85 str lr, [sp, #-4]!
86 ldr ip, [ip, #TI_ADDR_LIMIT]
87 sub ip, ip, #8
88 cmp r0, ip
89 bge __put_user_bad
90 cmp r0, #0x02000000
915: strlst r1, [r0], #4
926: strlst r2, [r0]
93 strge r1, [r0], #4
94 strge r2, [r0]
95 mov r0, #0
96 ldmfd sp!, {pc}^
97
98__put_user_bad:
99 mov r0, #-EFAULT
100 mov pc, lr
101
102.section __ex_table, "a"
103 .long 1b, __put_user_bad
104 .long 2b, __put_user_bad
105 .long 3b, __put_user_bad
106 .long 4b, __put_user_bad
107 .long 5b, __put_user_bad
108 .long 6b, __put_user_bad
109.previous
diff --git a/arch/arm26/lib/setbit.S b/arch/arm26/lib/setbit.S
new file mode 100644
index 000000000000..e180c1a1b2f1
--- /dev/null
+++ b/arch/arm26/lib/setbit.S
@@ -0,0 +1,29 @@
1/*
2 * linux/arch/arm26/lib/setbit.S
3 *
4 * Copyright (C) 1995-1996 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12 .text
13
14/*
15 * Purpose : Function to set a bit
16 * Prototype: int set_bit(int bit, void *addr)
17 */
18ENTRY(_set_bit_be)
19 eor r0, r0, #0x18 @ big endian byte ordering
20ENTRY(_set_bit_le)
21 and r2, r0, #7
22 mov r3, #1
23 mov r3, r3, lsl r2
24 save_and_disable_irqs ip, r2
25 ldrb r2, [r1, r0, lsr #3]
26 orr r2, r2, r3
27 strb r2, [r1, r0, lsr #3]
28 restore_irqs ip
29 RETINSTR(mov,pc,lr)
diff --git a/arch/arm26/lib/strchr.S b/arch/arm26/lib/strchr.S
new file mode 100644
index 000000000000..ecfff21aa7c7
--- /dev/null
+++ b/arch/arm26/lib/strchr.S
@@ -0,0 +1,25 @@
1/*
2 * linux/arch/arm26/lib/strchr.S
3 *
4 * Copyright (C) 1995-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * ASM optimised string functions
11 */
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14
15 .text
16 .align 5
17ENTRY(strchr)
181: ldrb r2, [r0], #1
19 teq r2, r1
20 teqne r2, #0
21 bne 1b
22 teq r2, #0
23 moveq r0, #0
24 subne r0, r0, #1
25 RETINSTR(mov,pc,lr)
diff --git a/arch/arm26/lib/strrchr.S b/arch/arm26/lib/strrchr.S
new file mode 100644
index 000000000000..db43b28e78dc
--- /dev/null
+++ b/arch/arm26/lib/strrchr.S
@@ -0,0 +1,25 @@
1/*
2 * linux/arch/arm26/lib/strrchr.S
3 *
4 * Copyright (C) 1995-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * ASM optimised string functions
11 */
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14
15 .text
16 .align 5
17ENTRY(strrchr)
18 mov r3, #0
191: ldrb r2, [r0], #1
20 teq r2, r1
21 subeq r3, r0, #1
22 teq r2, #0
23 bne 1b
24 mov r0, r3
25 RETINSTR(mov,pc,lr)
diff --git a/arch/arm26/lib/testchangebit.S b/arch/arm26/lib/testchangebit.S
new file mode 100644
index 000000000000..17049a2d93a4
--- /dev/null
+++ b/arch/arm26/lib/testchangebit.S
@@ -0,0 +1,29 @@
1/*
2 * linux/arch/arm26/lib/testchangebit.S
3 *
4 * Copyright (C) 1995-1996 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12 .text
13
14ENTRY(_test_and_change_bit_be)
15 eor r0, r0, #0x18 @ big endian byte ordering
16ENTRY(_test_and_change_bit_le)
17 add r1, r1, r0, lsr #3
18 and r3, r0, #7
19 mov r0, #1
20 save_and_disable_irqs ip, r2
21 ldrb r2, [r1]
22 tst r2, r0, lsl r3
23 eor r2, r2, r0, lsl r3
24 strb r2, [r1]
25 restore_irqs ip
26 moveq r0, #0
27 RETINSTR(mov,pc,lr)
28
29
diff --git a/arch/arm26/lib/testclearbit.S b/arch/arm26/lib/testclearbit.S
new file mode 100644
index 000000000000..2506bd743ab4
--- /dev/null
+++ b/arch/arm26/lib/testclearbit.S
@@ -0,0 +1,29 @@
1/*
2 * linux/arch/arm26/lib/testclearbit.S
3 *
4 * Copyright (C) 1995-1996 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12 .text
13
14ENTRY(_test_and_clear_bit_be)
15 eor r0, r0, #0x18 @ big endian byte ordering
16ENTRY(_test_and_clear_bit_le)
17 add r1, r1, r0, lsr #3 @ Get byte offset
18 and r3, r0, #7 @ Get bit offset
19 mov r0, #1
20 save_and_disable_irqs ip, r2
21 ldrb r2, [r1]
22 tst r2, r0, lsl r3
23 bic r2, r2, r0, lsl r3
24 strb r2, [r1]
25 restore_irqs ip
26 moveq r0, #0
27 RETINSTR(mov,pc,lr)
28
29
diff --git a/arch/arm26/lib/testsetbit.S b/arch/arm26/lib/testsetbit.S
new file mode 100644
index 000000000000..f827de64b22d
--- /dev/null
+++ b/arch/arm26/lib/testsetbit.S
@@ -0,0 +1,29 @@
1/*
2 * linux/arch/arm26/lib/testsetbit.S
3 *
4 * Copyright (C) 1995-1996 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12 .text
13
14ENTRY(_test_and_set_bit_be)
15 eor r0, r0, #0x18 @ big endian byte ordering
16ENTRY(_test_and_set_bit_le)
17 add r1, r1, r0, lsr #3 @ Get byte offset
18 and r3, r0, #7 @ Get bit offset
19 mov r0, #1
20 save_and_disable_irqs ip, r2
21 ldrb r2, [r1]
22 tst r2, r0, lsl r3
23 orr r2, r2, r0, lsl r3
24 strb r2, [r1]
25 restore_irqs ip
26 moveq r0, #0
27 RETINSTR(mov,pc,lr)
28
29
diff --git a/arch/arm26/lib/uaccess-kernel.S b/arch/arm26/lib/uaccess-kernel.S
new file mode 100644
index 000000000000..3950a1f6bc99
--- /dev/null
+++ b/arch/arm26/lib/uaccess-kernel.S
@@ -0,0 +1,173 @@
1/*
2 * linux/arch/arm26/lib/uaccess-kernel.S
3 *
4 * Copyright (C) 1998 Russell King
5 *
6 * Note! Some code fragments found in here have a special calling
7 * convention - they are not APCS compliant!
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15
16 .text
17
18//FIXME - surely this can be done in C not asm, removing the problem of keeping C and asm in sync? (this is a struct uaccess_t)
19
20 .globl uaccess_kernel
21uaccess_kernel:
22 .word uaccess_kernel_put_byte
23 .word uaccess_kernel_get_byte
24 .word uaccess_kernel_put_half
25 .word uaccess_kernel_get_half
26 .word uaccess_kernel_put_word
27 .word uaccess_kernel_get_word
28 .word uaccess_kernel_put_dword
29 .word uaccess_kernel_copy
30 .word uaccess_kernel_copy
31 .word uaccess_kernel_clear
32 .word uaccess_kernel_strncpy
33 .word uaccess_kernel_strnlen
34
35@ In : r0 = x, r1 = addr, r2 = error
36@ Out: r2 = error
37uaccess_kernel_put_byte:
38 stmfd sp!, {lr}
39 strb r0, [r1]
40 ldmfd sp!, {pc}^
41
42@ In : r0 = x, r1 = addr, r2 = error
43@ Out: r2 = error
44uaccess_kernel_put_half:
45 stmfd sp!, {lr}
46 strb r0, [r1]
47 mov r0, r0, lsr #8
48 strb r0, [r1, #1]
49 ldmfd sp!, {pc}^
50
51@ In : r0 = x, r1 = addr, r2 = error
52@ Out: r2 = error
53uaccess_kernel_put_word:
54 stmfd sp!, {lr}
55 str r0, [r1]
56 ldmfd sp!, {pc}^
57
58@ In : r0 = x, r1 = addr, r2 = error
59@ Out: r2 = error
60uaccess_kernel_put_dword:
61 stmfd sp!, {lr}
62 str r0, [r1], #4
63 str r0, [r1], #0
64 ldmfd sp!, {pc}^
65
66@ In : r0 = addr, r1 = error
67@ Out: r0 = x, r1 = error
68uaccess_kernel_get_byte:
69 stmfd sp!, {lr}
70 ldrb r0, [r0]
71 ldmfd sp!, {pc}^
72
73@ In : r0 = addr, r1 = error
74@ Out: r0 = x, r1 = error
75uaccess_kernel_get_half:
76 stmfd sp!, {lr}
77 ldr r0, [r0]
78 mov r0, r0, lsl #16
79 mov r0, r0, lsr #16
80 ldmfd sp!, {pc}^
81
82@ In : r0 = addr, r1 = error
83@ Out: r0 = x, r1 = error
84uaccess_kernel_get_word:
85 stmfd sp!, {lr}
86 ldr r0, [r0]
87 ldmfd sp!, {pc}^
88
89
90/* Prototype: int uaccess_kernel_copy(void *to, const char *from, size_t n)
91 * Purpose : copy a block to kernel memory from kernel memory
92 * Params : to - kernel memory
93 * : from - kernel memory
94 * : n - number of bytes to copy
95 * Returns : Number of bytes NOT copied.
96 */
97uaccess_kernel_copy:
98 stmfd sp!, {lr}
99 bl memcpy
100 mov r0, #0
101 ldmfd sp!, {pc}^
102
103/* Prototype: int uaccess_kernel_clear(void *addr, size_t sz)
104 * Purpose : clear some kernel memory
105 * Params : addr - kernel memory address to clear
106 * : sz - number of bytes to clear
107 * Returns : number of bytes NOT cleared
108 */
109uaccess_kernel_clear:
110 stmfd sp!, {lr}
111 mov r2, #0
112 cmp r1, #4
113 blt 2f
114 ands ip, r0, #3
115 beq 1f
116 cmp ip, #1
117 strb r2, [r0], #1
118 strleb r2, [r0], #1
119 strltb r2, [r0], #1
120 rsb ip, ip, #4
121 sub r1, r1, ip @ 7 6 5 4 3 2 1
1221: subs r1, r1, #8 @ -1 -2 -3 -4 -5 -6 -7
123 bmi 2f
124 str r2, [r0], #4
125 str r2, [r0], #4
126 b 1b
1272: adds r1, r1, #4 @ 3 2 1 0 -1 -2 -3
128 strpl r2, [r0], #4
129 tst r1, #2 @ 1x 1x 0x 0x 1x 1x 0x
130 strneb r2, [r0], #1
131 strneb r2, [r0], #1
132 tst r1, #1 @ x1 x0 x1 x0 x1 x0 x1
133 strneb r2, [r0], #1
134 mov r0, #0
135 ldmfd sp!, {pc}^
136
137/* Prototype: size_t uaccess_kernel_strncpy(char *dst, char *src, size_t len)
138 * Purpose : copy a string from kernel memory to kernel memory
139 * Params : dst - kernel memory destination
140 * : src - kernel memory source
141 * : len - maximum length of string
142 * Returns : number of characters copied
143 */
144uaccess_kernel_strncpy:
145 stmfd sp!, {lr}
146 mov ip, r2
1471: subs r2, r2, #1
148 bmi 2f
149 ldrb r3, [r1], #1
150 strb r3, [r0], #1
151 teq r3, #0
152 bne 1b
1532: subs r0, ip, r2
154 ldmfd sp!, {pc}^
155
156/* Prototype: int uaccess_kernel_strlen(char *str, long n)
157 * Purpose : get length of a string in kernel memory
158 * Params : str - address of string in kernel memory
159 * Returns : length of string *including terminator*,
160 * or zero on exception, or n + 1 if too long
161 */
162uaccess_kernel_strnlen:
163 stmfd sp!, {lr}
164 mov r2, r0
1651: ldrb r1, [r0], #1
166 teq r1, #0
167 beq 2f
168 subs r1, r1, #1
169 bne 1b
170 add r0, r0, #1
1712: sub r0, r0, r2
172 ldmfd sp!, {pc}^
173
diff --git a/arch/arm26/lib/uaccess-user.S b/arch/arm26/lib/uaccess-user.S
new file mode 100644
index 000000000000..130b8f28610a
--- /dev/null
+++ b/arch/arm26/lib/uaccess-user.S
@@ -0,0 +1,718 @@
1/*
2 * linux/arch/arm26/lib/uaccess-user.S
3 *
4 * Copyright (C) 1995, 1996,1997,1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Routines to block copy data to/from user memory
11 * These are highly optimised both for the 4k page size
12 * and for various alignments.
13 */
14#include <linux/linkage.h>
15#include <asm/assembler.h>
16#include <asm/errno.h>
17#include <asm/page.h>
18
19 .text
20
21//FIXME - surely this can be done in C not asm, removing the problem of keeping C and asm in sync? (this is a struct uaccess_t)
22 .globl uaccess_user
23uaccess_user:
24 .word uaccess_user_put_byte
25 .word uaccess_user_get_byte
26 .word uaccess_user_put_half
27 .word uaccess_user_get_half
28 .word uaccess_user_put_word
29 .word uaccess_user_get_word
30 .word uaccess_user_put_dword
31 .word uaccess_user_copy_from_user
32 .word uaccess_user_copy_to_user
33 .word uaccess_user_clear_user
34 .word uaccess_user_strncpy_from_user
35 .word uaccess_user_strnlen_user
36
37
38@ In : r0 = x, r1 = addr, r2 = error
39@ Out: r2 = error
40uaccess_user_put_byte:
41 stmfd sp!, {lr}
42USER( strbt r0, [r1])
43 ldmfd sp!, {pc}^
44
45@ In : r0 = x, r1 = addr, r2 = error
46@ Out: r2 = error
47uaccess_user_put_half:
48 stmfd sp!, {lr}
49USER( strbt r0, [r1], #1)
50 mov r0, r0, lsr #8
51USER( strbt r0, [r1])
52 ldmfd sp!, {pc}^
53
54@ In : r0 = x, r1 = addr, r2 = error
55@ Out: r2 = error
56uaccess_user_put_word:
57 stmfd sp!, {lr}
58USER( strt r0, [r1])
59 ldmfd sp!, {pc}^
60
61@ In : r0 = x, r1 = addr, r2 = error
62@ Out: r2 = error
63uaccess_user_put_dword:
64 stmfd sp!, {lr}
65USER( strt r0, [r1], #4)
66USER( strt r0, [r1], #0)
67 ldmfd sp!, {pc}^
68
699001: mov r2, #-EFAULT
70 ldmfd sp!, {pc}^
71
72
73@ In : r0 = addr, r1 = error
74@ Out: r0 = x, r1 = error
75uaccess_user_get_byte:
76 stmfd sp!, {lr}
77USER( ldrbt r0, [r0])
78 ldmfd sp!, {pc}^
79
80@ In : r0 = addr, r1 = error
81@ Out: r0 = x, r1 = error
82uaccess_user_get_half:
83 stmfd sp!, {lr}
84USER( ldrt r0, [r0])
85 mov r0, r0, lsl #16
86 mov r0, r0, lsr #16
87 ldmfd sp!, {pc}^
88
89@ In : r0 = addr, r1 = error
90@ Out: r0 = x, r1 = error
91uaccess_user_get_word:
92 stmfd sp!, {lr}
93USER( ldrt r0, [r0])
94 ldmfd sp!, {pc}^
95
969001: mov r1, #-EFAULT
97 ldmfd sp!, {pc}^
98
99/* Prototype: int uaccess_user_copy_to_user(void *to, const char *from, size_t n)
100 * Purpose : copy a block to user memory from kernel memory
101 * Params : to - user memory
102 * : from - kernel memory
103 * : n - number of bytes to copy
104 * Returns : Number of bytes NOT copied.
105 */
106
107.c2u_dest_not_aligned:
108 rsb ip, ip, #4
109 cmp ip, #2
110 ldrb r3, [r1], #1
111USER( strbt r3, [r0], #1) @ May fault
112 ldrgeb r3, [r1], #1
113USER( strgebt r3, [r0], #1) @ May fault
114 ldrgtb r3, [r1], #1
115USER( strgtbt r3, [r0], #1) @ May fault
116 sub r2, r2, ip
117 b .c2u_dest_aligned
118
119ENTRY(uaccess_user_copy_to_user)
120 stmfd sp!, {r2, r4 - r7, lr}
121 cmp r2, #4
122 blt .c2u_not_enough
123 ands ip, r0, #3
124 bne .c2u_dest_not_aligned
125.c2u_dest_aligned:
126
127 ands ip, r1, #3
128 bne .c2u_src_not_aligned
129/*
130 * Seeing as there has to be at least 8 bytes to copy, we can
131 * copy one word, and force a user-mode page fault...
132 */
133
134.c2u_0fupi: subs r2, r2, #4
135 addmi ip, r2, #4
136 bmi .c2u_0nowords
137 ldr r3, [r1], #4
138USER( strt r3, [r0], #4) @ May fault
139 mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction
140 rsb ip, ip, #0
141 movs ip, ip, lsr #32 - PAGE_SHIFT
142 beq .c2u_0fupi
143/*
144 * ip = max no. of bytes to copy before needing another "strt" insn
145 */
146 cmp r2, ip
147 movlt ip, r2
148 sub r2, r2, ip
149 subs ip, ip, #32
150 blt .c2u_0rem8lp
151
152.c2u_0cpy8lp: ldmia r1!, {r3 - r6}
153 stmia r0!, {r3 - r6} @ Shouldnt fault
154 ldmia r1!, {r3 - r6}
155 stmia r0!, {r3 - r6} @ Shouldnt fault
156 subs ip, ip, #32
157 bpl .c2u_0cpy8lp
158.c2u_0rem8lp: cmn ip, #16
159 ldmgeia r1!, {r3 - r6}
160 stmgeia r0!, {r3 - r6} @ Shouldnt fault
161 tst ip, #8
162 ldmneia r1!, {r3 - r4}
163 stmneia r0!, {r3 - r4} @ Shouldnt fault
164 tst ip, #4
165 ldrne r3, [r1], #4
166 strnet r3, [r0], #4 @ Shouldnt fault
167 ands ip, ip, #3
168 beq .c2u_0fupi
169.c2u_0nowords: teq ip, #0
170 beq .c2u_finished
171.c2u_nowords: cmp ip, #2
172 ldrb r3, [r1], #1
173USER( strbt r3, [r0], #1) @ May fault
174 ldrgeb r3, [r1], #1
175USER( strgebt r3, [r0], #1) @ May fault
176 ldrgtb r3, [r1], #1
177USER( strgtbt r3, [r0], #1) @ May fault
178 b .c2u_finished
179
180.c2u_not_enough:
181 movs ip, r2
182 bne .c2u_nowords
183.c2u_finished: mov r0, #0
184 LOADREGS(fd,sp!,{r2, r4 - r7, pc})
185
186.c2u_src_not_aligned:
187 bic r1, r1, #3
188 ldr r7, [r1], #4
189 cmp ip, #2
190 bgt .c2u_3fupi
191 beq .c2u_2fupi
192.c2u_1fupi: subs r2, r2, #4
193 addmi ip, r2, #4
194 bmi .c2u_1nowords
195 mov r3, r7, pull #8
196 ldr r7, [r1], #4
197 orr r3, r3, r7, push #24
198USER( strt r3, [r0], #4) @ May fault
199 mov ip, r0, lsl #32 - PAGE_SHIFT
200 rsb ip, ip, #0
201 movs ip, ip, lsr #32 - PAGE_SHIFT
202 beq .c2u_1fupi
203 cmp r2, ip
204 movlt ip, r2
205 sub r2, r2, ip
206 subs ip, ip, #16
207 blt .c2u_1rem8lp
208
209.c2u_1cpy8lp: mov r3, r7, pull #8
210 ldmia r1!, {r4 - r7}
211 orr r3, r3, r4, push #24
212 mov r4, r4, pull #8
213 orr r4, r4, r5, push #24
214 mov r5, r5, pull #8
215 orr r5, r5, r6, push #24
216 mov r6, r6, pull #8
217 orr r6, r6, r7, push #24
218 stmia r0!, {r3 - r6} @ Shouldnt fault
219 subs ip, ip, #16
220 bpl .c2u_1cpy8lp
221.c2u_1rem8lp: tst ip, #8
222 movne r3, r7, pull #8
223 ldmneia r1!, {r4, r7}
224 orrne r3, r3, r4, push #24
225 movne r4, r4, pull #8
226 orrne r4, r4, r7, push #24
227 stmneia r0!, {r3 - r4} @ Shouldnt fault
228 tst ip, #4
229 movne r3, r7, pull #8
230 ldrne r7, [r1], #4
231 orrne r3, r3, r7, push #24
232 strnet r3, [r0], #4 @ Shouldnt fault
233 ands ip, ip, #3
234 beq .c2u_1fupi
235.c2u_1nowords: mov r3, r7, lsr #byte(1)
236 teq ip, #0
237 beq .c2u_finished
238 cmp ip, #2
239USER( strbt r3, [r0], #1) @ May fault
240 movge r3, r7, lsr #byte(2)
241USER( strgebt r3, [r0], #1) @ May fault
242 movgt r3, r7, lsr #byte(3)
243USER( strgtbt r3, [r0], #1) @ May fault
244 b .c2u_finished
245
246.c2u_2fupi: subs r2, r2, #4
247 addmi ip, r2, #4
248 bmi .c2u_2nowords
249 mov r3, r7, pull #16
250 ldr r7, [r1], #4
251 orr r3, r3, r7, push #16
252USER( strt r3, [r0], #4) @ May fault
253 mov ip, r0, lsl #32 - PAGE_SHIFT
254 rsb ip, ip, #0
255 movs ip, ip, lsr #32 - PAGE_SHIFT
256 beq .c2u_2fupi
257 cmp r2, ip
258 movlt ip, r2
259 sub r2, r2, ip
260 subs ip, ip, #16
261 blt .c2u_2rem8lp
262
263.c2u_2cpy8lp: mov r3, r7, pull #16
264 ldmia r1!, {r4 - r7}
265 orr r3, r3, r4, push #16
266 mov r4, r4, pull #16
267 orr r4, r4, r5, push #16
268 mov r5, r5, pull #16
269 orr r5, r5, r6, push #16
270 mov r6, r6, pull #16
271 orr r6, r6, r7, push #16
272 stmia r0!, {r3 - r6} @ Shouldnt fault
273 subs ip, ip, #16
274 bpl .c2u_2cpy8lp
275.c2u_2rem8lp: tst ip, #8
276 movne r3, r7, pull #16
277 ldmneia r1!, {r4, r7}
278 orrne r3, r3, r4, push #16
279 movne r4, r4, pull #16
280 orrne r4, r4, r7, push #16
281 stmneia r0!, {r3 - r4} @ Shouldnt fault
282 tst ip, #4
283 movne r3, r7, pull #16
284 ldrne r7, [r1], #4
285 orrne r3, r3, r7, push #16
286 strnet r3, [r0], #4 @ Shouldnt fault
287 ands ip, ip, #3
288 beq .c2u_2fupi
289.c2u_2nowords: mov r3, r7, lsr #byte(2)
290 teq ip, #0
291 beq .c2u_finished
292 cmp ip, #2
293USER( strbt r3, [r0], #1) @ May fault
294 movge r3, r7, lsr #byte(3)
295USER( strgebt r3, [r0], #1) @ May fault
296 ldrgtb r3, [r1], #0
297USER( strgtbt r3, [r0], #1) @ May fault
298 b .c2u_finished
299
300.c2u_3fupi: subs r2, r2, #4
301 addmi ip, r2, #4
302 bmi .c2u_3nowords
303 mov r3, r7, pull #24
304 ldr r7, [r1], #4
305 orr r3, r3, r7, push #8
306USER( strt r3, [r0], #4) @ May fault
307 mov ip, r0, lsl #32 - PAGE_SHIFT
308 rsb ip, ip, #0
309 movs ip, ip, lsr #32 - PAGE_SHIFT
310 beq .c2u_3fupi
311 cmp r2, ip
312 movlt ip, r2
313 sub r2, r2, ip
314 subs ip, ip, #16
315 blt .c2u_3rem8lp
316
317.c2u_3cpy8lp: mov r3, r7, pull #24
318 ldmia r1!, {r4 - r7}
319 orr r3, r3, r4, push #8
320 mov r4, r4, pull #24
321 orr r4, r4, r5, push #8
322 mov r5, r5, pull #24
323 orr r5, r5, r6, push #8
324 mov r6, r6, pull #24
325 orr r6, r6, r7, push #8
326 stmia r0!, {r3 - r6} @ Shouldnt fault
327 subs ip, ip, #16
328 bpl .c2u_3cpy8lp
329.c2u_3rem8lp: tst ip, #8
330 movne r3, r7, pull #24
331 ldmneia r1!, {r4, r7}
332 orrne r3, r3, r4, push #8
333 movne r4, r4, pull #24
334 orrne r4, r4, r7, push #8
335 stmneia r0!, {r3 - r4} @ Shouldnt fault
336 tst ip, #4
337 movne r3, r7, pull #24
338 ldrne r7, [r1], #4
339 orrne r3, r3, r7, push #8
340 strnet r3, [r0], #4 @ Shouldnt fault
341 ands ip, ip, #3
342 beq .c2u_3fupi
343.c2u_3nowords: mov r3, r7, lsr #byte(3)
344 teq ip, #0
345 beq .c2u_finished
346 cmp ip, #2
347USER( strbt r3, [r0], #1) @ May fault
348 ldrgeb r3, [r1], #1
349USER( strgebt r3, [r0], #1) @ May fault
350 ldrgtb r3, [r1], #0
351USER( strgtbt r3, [r0], #1) @ May fault
352 b .c2u_finished
353
354 .section .fixup,"ax"
355 .align 0
3569001: LOADREGS(fd,sp!, {r0, r4 - r7, pc})
357 .previous
358
359/* Prototype: unsigned long uaccess_user_copy_from_user(void *to,const void *from,unsigned long n);
360 * Purpose : copy a block from user memory to kernel memory
361 * Params : to - kernel memory
362 * : from - user memory
363 * : n - number of bytes to copy
364 * Returns : Number of bytes NOT copied.
365 */
366.cfu_dest_not_aligned:
367 rsb ip, ip, #4
368 cmp ip, #2
369USER( ldrbt r3, [r1], #1) @ May fault
370 strb r3, [r0], #1
371USER( ldrgebt r3, [r1], #1) @ May fault
372 strgeb r3, [r0], #1
373USER( ldrgtbt r3, [r1], #1) @ May fault
374 strgtb r3, [r0], #1
375 sub r2, r2, ip
376 b .cfu_dest_aligned
377
378ENTRY(uaccess_user_copy_from_user)
379 stmfd sp!, {r0, r2, r4 - r7, lr}
380 cmp r2, #4
381 blt .cfu_not_enough
382 ands ip, r0, #3
383 bne .cfu_dest_not_aligned
384.cfu_dest_aligned:
385 ands ip, r1, #3
386 bne .cfu_src_not_aligned
387/*
388 * Seeing as there has to be at least 8 bytes to copy, we can
389 * copy one word, and force a user-mode page fault...
390 */
391
392.cfu_0fupi: subs r2, r2, #4
393 addmi ip, r2, #4
394 bmi .cfu_0nowords
395USER( ldrt r3, [r1], #4)
396 str r3, [r0], #4
397 mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction
398 rsb ip, ip, #0
399 movs ip, ip, lsr #32 - PAGE_SHIFT
400 beq .cfu_0fupi
401/*
402 * ip = max no. of bytes to copy before needing another "strt" insn
403 */
404 cmp r2, ip
405 movlt ip, r2
406 sub r2, r2, ip
407 subs ip, ip, #32
408 blt .cfu_0rem8lp
409
410.cfu_0cpy8lp: ldmia r1!, {r3 - r6} @ Shouldnt fault
411 stmia r0!, {r3 - r6}
412 ldmia r1!, {r3 - r6} @ Shouldnt fault
413 stmia r0!, {r3 - r6}
414 subs ip, ip, #32
415 bpl .cfu_0cpy8lp
416.cfu_0rem8lp: cmn ip, #16
417 ldmgeia r1!, {r3 - r6} @ Shouldnt fault
418 stmgeia r0!, {r3 - r6}
419 tst ip, #8
420 ldmneia r1!, {r3 - r4} @ Shouldnt fault
421 stmneia r0!, {r3 - r4}
422 tst ip, #4
423 ldrnet r3, [r1], #4 @ Shouldnt fault
424 strne r3, [r0], #4
425 ands ip, ip, #3
426 beq .cfu_0fupi
427.cfu_0nowords: teq ip, #0
428 beq .cfu_finished
429.cfu_nowords: cmp ip, #2
430USER( ldrbt r3, [r1], #1) @ May fault
431 strb r3, [r0], #1
432USER( ldrgebt r3, [r1], #1) @ May fault
433 strgeb r3, [r0], #1
434USER( ldrgtbt r3, [r1], #1) @ May fault
435 strgtb r3, [r0], #1
436 b .cfu_finished
437
438.cfu_not_enough:
439 movs ip, r2
440 bne .cfu_nowords
441.cfu_finished: mov r0, #0
442 add sp, sp, #8
443 LOADREGS(fd,sp!,{r4 - r7, pc})
444
445.cfu_src_not_aligned:
446 bic r1, r1, #3
447USER( ldrt r7, [r1], #4) @ May fault
448 cmp ip, #2
449 bgt .cfu_3fupi
450 beq .cfu_2fupi
451.cfu_1fupi: subs r2, r2, #4
452 addmi ip, r2, #4
453 bmi .cfu_1nowords
454 mov r3, r7, pull #8
455USER( ldrt r7, [r1], #4) @ May fault
456 orr r3, r3, r7, push #24
457 str r3, [r0], #4
458 mov ip, r1, lsl #32 - PAGE_SHIFT
459 rsb ip, ip, #0
460 movs ip, ip, lsr #32 - PAGE_SHIFT
461 beq .cfu_1fupi
462 cmp r2, ip
463 movlt ip, r2
464 sub r2, r2, ip
465 subs ip, ip, #16
466 blt .cfu_1rem8lp
467
468.cfu_1cpy8lp: mov r3, r7, pull #8
469 ldmia r1!, {r4 - r7} @ Shouldnt fault
470 orr r3, r3, r4, push #24
471 mov r4, r4, pull #8
472 orr r4, r4, r5, push #24
473 mov r5, r5, pull #8
474 orr r5, r5, r6, push #24
475 mov r6, r6, pull #8
476 orr r6, r6, r7, push #24
477 stmia r0!, {r3 - r6}
478 subs ip, ip, #16
479 bpl .cfu_1cpy8lp
480.cfu_1rem8lp: tst ip, #8
481 movne r3, r7, pull #8
482 ldmneia r1!, {r4, r7} @ Shouldnt fault
483 orrne r3, r3, r4, push #24
484 movne r4, r4, pull #8
485 orrne r4, r4, r7, push #24
486 stmneia r0!, {r3 - r4}
487 tst ip, #4
488 movne r3, r7, pull #8
489USER( ldrnet r7, [r1], #4) @ May fault
490 orrne r3, r3, r7, push #24
491 strne r3, [r0], #4
492 ands ip, ip, #3
493 beq .cfu_1fupi
494.cfu_1nowords: mov r3, r7, lsr #byte(1)
495 teq ip, #0
496 beq .cfu_finished
497 cmp ip, #2
498 strb r3, [r0], #1
499 movge r3, r7, lsr #byte(2)
500 strgeb r3, [r0], #1
501 movgt r3, r7, lsr #byte(3)
502 strgtb r3, [r0], #1
503 b .cfu_finished
504
505.cfu_2fupi: subs r2, r2, #4
506 addmi ip, r2, #4
507 bmi .cfu_2nowords
508 mov r3, r7, pull #16
509USER( ldrt r7, [r1], #4) @ May fault
510 orr r3, r3, r7, push #16
511 str r3, [r0], #4
512 mov ip, r1, lsl #32 - PAGE_SHIFT
513 rsb ip, ip, #0
514 movs ip, ip, lsr #32 - PAGE_SHIFT
515 beq .cfu_2fupi
516 cmp r2, ip
517 movlt ip, r2
518 sub r2, r2, ip
519 subs ip, ip, #16
520 blt .cfu_2rem8lp
521
522.cfu_2cpy8lp: mov r3, r7, pull #16
523 ldmia r1!, {r4 - r7} @ Shouldnt fault
524 orr r3, r3, r4, push #16
525 mov r4, r4, pull #16
526 orr r4, r4, r5, push #16
527 mov r5, r5, pull #16
528 orr r5, r5, r6, push #16
529 mov r6, r6, pull #16
530 orr r6, r6, r7, push #16
531 stmia r0!, {r3 - r6}
532 subs ip, ip, #16
533 bpl .cfu_2cpy8lp
534.cfu_2rem8lp: tst ip, #8
535 movne r3, r7, pull #16
536 ldmneia r1!, {r4, r7} @ Shouldnt fault
537 orrne r3, r3, r4, push #16
538 movne r4, r4, pull #16
539 orrne r4, r4, r7, push #16
540 stmneia r0!, {r3 - r4}
541 tst ip, #4
542 movne r3, r7, pull #16
543USER( ldrnet r7, [r1], #4) @ May fault
544 orrne r3, r3, r7, push #16
545 strne r3, [r0], #4
546 ands ip, ip, #3
547 beq .cfu_2fupi
548.cfu_2nowords: mov r3, r7, lsr #byte(2)
549 teq ip, #0
550 beq .cfu_finished
551 cmp ip, #2
552 strb r3, [r0], #1
553 movge r3, r7, lsr #byte(3)
554 strgeb r3, [r0], #1
555USER( ldrgtbt r3, [r1], #0) @ May fault
556 strgtb r3, [r0], #1
557 b .cfu_finished
558
559.cfu_3fupi: subs r2, r2, #4
560 addmi ip, r2, #4
561 bmi .cfu_3nowords
562 mov r3, r7, pull #24
563USER( ldrt r7, [r1], #4) @ May fault
564 orr r3, r3, r7, push #8
565 str r3, [r0], #4
566 mov ip, r1, lsl #32 - PAGE_SHIFT
567 rsb ip, ip, #0
568 movs ip, ip, lsr #32 - PAGE_SHIFT
569 beq .cfu_3fupi
570 cmp r2, ip
571 movlt ip, r2
572 sub r2, r2, ip
573 subs ip, ip, #16
574 blt .cfu_3rem8lp
575
576.cfu_3cpy8lp: mov r3, r7, pull #24
577 ldmia r1!, {r4 - r7} @ Shouldnt fault
578 orr r3, r3, r4, push #8
579 mov r4, r4, pull #24
580 orr r4, r4, r5, push #8
581 mov r5, r5, pull #24
582 orr r5, r5, r6, push #8
583 mov r6, r6, pull #24
584 orr r6, r6, r7, push #8
585 stmia r0!, {r3 - r6}
586 subs ip, ip, #16
587 bpl .cfu_3cpy8lp
588.cfu_3rem8lp: tst ip, #8
589 movne r3, r7, pull #24
590 ldmneia r1!, {r4, r7} @ Shouldnt fault
591 orrne r3, r3, r4, push #8
592 movne r4, r4, pull #24
593 orrne r4, r4, r7, push #8
594 stmneia r0!, {r3 - r4}
595 tst ip, #4
596 movne r3, r7, pull #24
597USER( ldrnet r7, [r1], #4) @ May fault
598 orrne r3, r3, r7, push #8
599 strne r3, [r0], #4
600 ands ip, ip, #3
601 beq .cfu_3fupi
602.cfu_3nowords: mov r3, r7, lsr #byte(3)
603 teq ip, #0
604 beq .cfu_finished
605 cmp ip, #2
606 strb r3, [r0], #1
607USER( ldrgebt r3, [r1], #1) @ May fault
608 strgeb r3, [r0], #1
609USER( ldrgtbt r3, [r1], #1) @ May fault
610 strgtb r3, [r0], #1
611 b .cfu_finished
612
613 .section .fixup,"ax"
614 .align 0
615 /*
616 * We took an exception. r0 contains a pointer to
617 * the byte not copied.
618 */
6199001: ldr r2, [sp], #4 @ void *to
620 sub r2, r0, r2 @ bytes copied
621 ldr r1, [sp], #4 @ unsigned long count
622 subs r4, r1, r2 @ bytes left to copy
623 movne r1, r4
624 blne __memzero
625 mov r0, r4
626 LOADREGS(fd,sp!, {r4 - r7, pc})
627 .previous
628
629/* Prototype: int uaccess_user_clear_user(void *addr, size_t sz)
630 * Purpose : clear some user memory
631 * Params : addr - user memory address to clear
632 * : sz - number of bytes to clear
633 * Returns : number of bytes NOT cleared
634 */
635ENTRY(uaccess_user_clear_user)
636 stmfd sp!, {r1, lr}
637 mov r2, #0
638 cmp r1, #4
639 blt 2f
640 ands ip, r0, #3
641 beq 1f
642 cmp ip, #2
643USER( strbt r2, [r0], #1)
644USER( strlebt r2, [r0], #1)
645USER( strltbt r2, [r0], #1)
646 rsb ip, ip, #4
647 sub r1, r1, ip @ 7 6 5 4 3 2 1
6481: subs r1, r1, #8 @ -1 -2 -3 -4 -5 -6 -7
649USER( strplt r2, [r0], #4)
650USER( strplt r2, [r0], #4)
651 bpl 1b
652 adds r1, r1, #4 @ 3 2 1 0 -1 -2 -3
653USER( strplt r2, [r0], #4)
6542: tst r1, #2 @ 1x 1x 0x 0x 1x 1x 0x
655USER( strnebt r2, [r0], #1)
656USER( strnebt r2, [r0], #1)
657 tst r1, #1 @ x1 x0 x1 x0 x1 x0 x1
658USER( strnebt r2, [r0], #1)
659 mov r0, #0
660 LOADREGS(fd,sp!, {r1, pc})
661
662 .section .fixup,"ax"
663 .align 0
6649001: LOADREGS(fd,sp!, {r0, pc})
665 .previous
666
667/*
668 * Copy a string from user space to kernel space.
669 * r0 = dst, r1 = src, r2 = byte length
670 * returns the number of characters copied (strlen of copied string),
671 * -EFAULT on exception, or "len" if we fill the whole buffer
672 */
673ENTRY(uaccess_user_strncpy_from_user)
674 save_lr
675 mov ip, r1
6761: subs r2, r2, #1
677USER( ldrplbt r3, [r1], #1)
678 bmi 2f
679 strb r3, [r0], #1
680 teq r3, #0
681 bne 1b
682 sub r1, r1, #1 @ take NUL character out of count
6832: sub r0, r1, ip
684 restore_pc
685
686 .section .fixup,"ax"
687 .align 0
6889001: mov r3, #0
689 strb r3, [r0, #0] @ null terminate
690 mov r0, #-EFAULT
691 restore_pc
692 .previous
693
694/* Prototype: unsigned long uaccess_user_strnlen_user(const char *str, long n)
695 * Purpose : get length of a string in user memory
696 * Params : str - address of string in user memory
697 * Returns : length of string *including terminator*
698 * or zero on exception, or n + 1 if too long
699 */
700ENTRY(uaccess_user_strnlen_user)
701 save_lr
702 mov r2, r0
7031:
704USER( ldrbt r3, [r0], #1)
705 teq r3, #0
706 beq 2f
707 subs r1, r1, #1
708 bne 1b
709 add r0, r0, #1
7102: sub r0, r0, r2
711 restore_pc
712
713 .section .fixup,"ax"
714 .align 0
7159001: mov r0, #0
716 restore_pc
717 .previous
718
diff --git a/arch/arm26/lib/ucmpdi2.c b/arch/arm26/lib/ucmpdi2.c
new file mode 100644
index 000000000000..6c6ae63efa02
--- /dev/null
+++ b/arch/arm26/lib/ucmpdi2.c
@@ -0,0 +1,51 @@
1/* More subroutines needed by GCC output code on some machines. */
2/* Compile this one with gcc. */
3/* Copyright (C) 1989, 92-98, 1999 Free Software Foundation, Inc.
4
5This file is part of GNU CC.
6
7GNU CC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12GNU CC is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GNU CC; see the file COPYING. If not, write to
19the Free Software Foundation, 59 Temple Place - Suite 330,
20Boston, MA 02111-1307, USA. */
21
22/* As a special exception, if you link this library with other files,
23 some of which are compiled with GCC, to produce an executable,
24 this library does not by itself cause the resulting executable
25 to be covered by the GNU General Public License.
26 This exception does not however invalidate any other reasons why
27 the executable file might be covered by the GNU General Public License.
28 */
29/* support functions required by the kernel. based on code from gcc-2.95.3 */
30/* I Molton 29/07/01 */
31
32#include "gcclib.h"
33
34word_type
35__ucmpdi2 (DItype a, DItype b)
36{
37 DIunion au, bu;
38
39 au.ll = a, bu.ll = b;
40
41 if ((USItype) au.s.high < (USItype) bu.s.high)
42 return 0;
43 else if ((USItype) au.s.high > (USItype) bu.s.high)
44 return 2;
45 if ((USItype) au.s.low < (USItype) bu.s.low)
46 return 0;
47 else if ((USItype) au.s.low > (USItype) bu.s.low)
48 return 2;
49 return 1;
50}
51
diff --git a/arch/arm26/lib/udivdi3.c b/arch/arm26/lib/udivdi3.c
new file mode 100644
index 000000000000..d25195f673f4
--- /dev/null
+++ b/arch/arm26/lib/udivdi3.c
@@ -0,0 +1,242 @@
1/* More subroutines needed by GCC output code on some machines. */
2/* Compile this one with gcc. */
3/* Copyright (C) 1989, 92-98, 1999 Free Software Foundation, Inc.
4
5This file is part of GNU CC.
6
7GNU CC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12GNU CC is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GNU CC; see the file COPYING. If not, write to
19the Free Software Foundation, 59 Temple Place - Suite 330,
20Boston, MA 02111-1307, USA. */
21
22/* As a special exception, if you link this library with other files,
23 some of which are compiled with GCC, to produce an executable,
24 this library does not by itself cause the resulting executable
25 to be covered by the GNU General Public License.
26 This exception does not however invalidate any other reasons why
27 the executable file might be covered by the GNU General Public License.
28 */
29/* support functions required by the kernel. based on code from gcc-2.95.3 */
30/* I Molton 29/07/01 */
31
32#include "gcclib.h"
33#include "longlong.h"
34
35static const UQItype __clz_tab[] =
36{
37 0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
38 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
39 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
40 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
41 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
42 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
43 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
44 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
45};
46
47UDItype
48__udivmoddi4 (UDItype n, UDItype d, UDItype *rp)
49{
50 DIunion ww;
51 DIunion nn, dd;
52 DIunion rr;
53 USItype d0, d1, n0, n1, n2;
54 USItype q0, q1;
55 USItype b, bm;
56
57 nn.ll = n;
58 dd.ll = d;
59
60 d0 = dd.s.low;
61 d1 = dd.s.high;
62 n0 = nn.s.low;
63 n1 = nn.s.high;
64
65 if (d1 == 0)
66 {
67 if (d0 > n1)
68 {
69 /* 0q = nn / 0D */
70
71 count_leading_zeros (bm, d0);
72
73 if (bm != 0)
74 {
75 /* Normalize, i.e. make the most significant bit of the
76 denominator set. */
77
78 d0 = d0 << bm;
79 n1 = (n1 << bm) | (n0 >> (SI_TYPE_SIZE - bm));
80 n0 = n0 << bm;
81 }
82
83 udiv_qrnnd (q0, n0, n1, n0, d0);
84 q1 = 0;
85
86 /* Remainder in n0 >> bm. */
87 }
88 else
89 {
90 /* qq = NN / 0d */
91
92 if (d0 == 0)
93 d0 = 1 / d0; /* Divide intentionally by zero. */
94
95 count_leading_zeros (bm, d0);
96
97 if (bm == 0)
98 {
99 /* From (n1 >= d0) /\ (the most significant bit of d0 is set),
100 conclude (the most significant bit of n1 is set) /\ (the
101 leading quotient digit q1 = 1).
102
103 This special case is necessary, not an optimization.
104 (Shifts counts of SI_TYPE_SIZE are undefined.) */
105
106 n1 -= d0;
107 q1 = 1;
108 }
109 else
110 {
111 /* Normalize. */
112
113 b = SI_TYPE_SIZE - bm;
114
115 d0 = d0 << bm;
116 n2 = n1 >> b;
117 n1 = (n1 << bm) | (n0 >> b);
118 n0 = n0 << bm;
119
120 udiv_qrnnd (q1, n1, n2, n1, d0);
121 }
122
123 /* n1 != d0... */
124
125 udiv_qrnnd (q0, n0, n1, n0, d0);
126
127 /* Remainder in n0 >> bm. */
128 }
129
130 if (rp != 0)
131 {
132 rr.s.low = n0 >> bm;
133 rr.s.high = 0;
134 *rp = rr.ll;
135 }
136 }
137 else
138 {
139 if (d1 > n1)
140 {
141 /* 00 = nn / DD */
142
143 q0 = 0;
144 q1 = 0;
145
146 /* Remainder in n1n0. */
147 if (rp != 0)
148 {
149 rr.s.low = n0;
150 rr.s.high = n1;
151 *rp = rr.ll;
152 }
153 }
154 else
155 {
156 /* 0q = NN / dd */
157
158 count_leading_zeros (bm, d1);
159 if (bm == 0)
160 {
161 /* From (n1 >= d1) /\ (the most significant bit of d1 is set),
162 conclude (the most significant bit of n1 is set) /\ (the
163 quotient digit q0 = 0 or 1).
164
165 This special case is necessary, not an optimization. */
166
167 /* The condition on the next line takes advantage of that
168 n1 >= d1 (true due to program flow). */
169 if (n1 > d1 || n0 >= d0)
170 {
171 q0 = 1;
172 sub_ddmmss (n1, n0, n1, n0, d1, d0);
173 }
174 else
175 q0 = 0;
176
177 q1 = 0;
178
179 if (rp != 0)
180 {
181 rr.s.low = n0;
182 rr.s.high = n1;
183 *rp = rr.ll;
184 }
185 }
186 else
187 {
188 USItype m1, m0;
189 /* Normalize. */
190
191 b = SI_TYPE_SIZE - bm;
192
193 d1 = (d1 << bm) | (d0 >> b);
194 d0 = d0 << bm;
195 n2 = n1 >> b;
196 n1 = (n1 << bm) | (n0 >> b);
197 n0 = n0 << bm;
198
199 udiv_qrnnd (q0, n1, n2, n1, d1);
200 umul_ppmm (m1, m0, q0, d0);
201
202 if (m1 > n1 || (m1 == n1 && m0 > n0))
203 {
204 q0--;
205 sub_ddmmss (m1, m0, m1, m0, d1, d0);
206 }
207
208 q1 = 0;
209
210 /* Remainder in (n1n0 - m1m0) >> bm. */
211 if (rp != 0)
212 {
213 sub_ddmmss (n1, n0, n1, n0, m1, m0);
214 rr.s.low = (n1 << b) | (n0 >> bm);
215 rr.s.high = n1 >> bm;
216 *rp = rr.ll;
217 }
218 }
219 }
220 }
221
222 ww.s.low = q0;
223 ww.s.high = q1;
224 return ww.ll;
225}
226
227UDItype
228__udivdi3 (UDItype n, UDItype d)
229{
230 return __udivmoddi4 (n, d, (UDItype *) 0);
231}
232
233UDItype
234__umoddi3 (UDItype u, UDItype v)
235{
236 UDItype w;
237
238 (void) __udivmoddi4 (u ,v, &w);
239
240 return w;
241}
242
diff --git a/arch/arm26/machine/Makefile b/arch/arm26/machine/Makefile
new file mode 100644
index 000000000000..86ea97cc07fc
--- /dev/null
+++ b/arch/arm26/machine/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y := dma.o irq.o latches.o
8
diff --git a/arch/arm26/machine/dma.c b/arch/arm26/machine/dma.c
new file mode 100644
index 000000000000..cbc7c61d5b32
--- /dev/null
+++ b/arch/arm26/machine/dma.c
@@ -0,0 +1,215 @@
1/*
2 * linux/arch/arm26/kernel/dma.c
3 *
4 * Copyright (C) 1998-1999 Dave Gilbert / Russell King
5 * Copyright (C) 2003 Ian Molton
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * DMA functions specific to Archimedes and A5000 architecture
12 */
13#include <linux/config.h>
14#include <linux/sched.h>
15#include <linux/init.h>
16
17#include <asm/dma.h>
18#include <asm/fiq.h>
19#include <asm/irq.h>
20#include <asm/io.h>
21#include <asm/hardware.h>
22#include <asm/mach-types.h>
23
24#define DPRINTK(x...) printk(KERN_DEBUG x)
25
26#if defined(CONFIG_BLK_DEV_FD1772) || defined(CONFIG_BLK_DEV_FD1772_MODULE)
27
28extern unsigned char fdc1772_dma_read, fdc1772_dma_read_end;
29extern unsigned char fdc1772_dma_write, fdc1772_dma_write_end;
30extern void fdc1772_setupdma(unsigned int count,unsigned int addr);
31
32static void arc_floppy_data_enable_dma(dmach_t channel, dma_t *dma)
33{
34 DPRINTK("arc_floppy_data_enable_dma\n");
35
36 if (dma->using_sg)
37 BUG();
38
39 switch (dma->dma_mode) {
40 case DMA_MODE_READ: { /* read */
41 unsigned long flags;
42 DPRINTK("enable_dma fdc1772 data read\n");
43 local_save_flags_cli(flags);
44 clf();
45
46 memcpy ((void *)0x1c, (void *)&fdc1772_dma_read,
47 &fdc1772_dma_read_end - &fdc1772_dma_read);
48 fdc1772_setupdma(dma->buf.length, dma->buf.__address); /* Sets data pointer up */
49 enable_fiq(FIQ_FLOPPYDATA);
50 local_irq_restore(flags);
51 }
52 break;
53
54 case DMA_MODE_WRITE: { /* write */
55 unsigned long flags;
56 DPRINTK("enable_dma fdc1772 data write\n");
57 local_save_flags_cli(flags);
58 clf();
59 memcpy ((void *)0x1c, (void *)&fdc1772_dma_write,
60 &fdc1772_dma_write_end - &fdc1772_dma_write);
61 fdc1772_setupdma(dma->buf.length, dma->buf.__address); /* Sets data pointer up */
62 enable_fiq(FIQ_FLOPPYDATA);
63
64 local_irq_restore(flags);
65 }
66 break;
67 default:
68 printk ("enable_dma: dma%d not initialised\n", channel);
69 }
70}
71
72static int arc_floppy_data_get_dma_residue(dmach_t channel, dma_t *dma)
73{
74 extern unsigned int fdc1772_bytestogo;
75
76 /* 10/1/1999 DAG - I presume its the number of bytes left? */
77 return fdc1772_bytestogo;
78}
79
80static void arc_floppy_cmdend_enable_dma(dmach_t channel, dma_t *dma)
81{
82 /* Need to build a branch at the FIQ address */
83 extern void fdc1772_comendhandler(void);
84 unsigned long flags;
85
86 DPRINTK("arc_floppy_cmdend_enable_dma\n");
87 /*printk("enable_dma fdc1772 command end FIQ\n");*/
88 save_flags(flags);
89 clf();
90
91 /* B fdc1772_comendhandler */
92 *((unsigned int *)0x1c)=0xea000000 |
93 (((unsigned int)fdc1772_comendhandler-(0x1c+8))/4);
94
95 local_irq_restore(flags);
96}
97
98static int arc_floppy_cmdend_get_dma_residue(dmach_t channel, dma_t *dma)
99{
100 /* 10/1/1999 DAG - Presume whether there is an outstanding command? */
101 extern unsigned int fdc1772_fdc_int_done;
102
103 /* Explicit! If the int done is 0 then 1 int to go */
104 return (fdc1772_fdc_int_done==0)?1:0;
105}
106
107static void arc_disable_dma(dmach_t channel, dma_t *dma)
108{
109 disable_fiq(dma->dma_irq);
110}
111
112static struct dma_ops arc_floppy_data_dma_ops = {
113 .type = "FIQDMA",
114 .enable = arc_floppy_data_enable_dma,
115 .disable = arc_disable_dma,
116 .residue = arc_floppy_data_get_dma_residue,
117};
118
119static struct dma_ops arc_floppy_cmdend_dma_ops = {
120 .type = "FIQCMD",
121 .enable = arc_floppy_cmdend_enable_dma,
122 .disable = arc_disable_dma,
123 .residue = arc_floppy_cmdend_get_dma_residue,
124};
125#endif
126
127#ifdef CONFIG_ARCH_A5K
128static struct fiq_handler fh = {
129 .name = "floppydata"
130};
131
132static int a5k_floppy_get_dma_residue(dmach_t channel, dma_t *dma)
133{
134 struct pt_regs regs;
135 get_fiq_regs(&regs);
136 return regs.ARM_r9;
137}
138
139static void a5k_floppy_enable_dma(dmach_t channel, dma_t *dma)
140{
141 struct pt_regs regs;
142 void *fiqhandler_start;
143 unsigned int fiqhandler_length;
144 extern void floppy_fiqsetup(unsigned long len, unsigned long addr,
145 unsigned long port);
146
147 if (dma->using_sg)
148 BUG();
149
150 if (dma->dma_mode == DMA_MODE_READ) {
151 extern unsigned char floppy_fiqin_start, floppy_fiqin_end;
152 fiqhandler_start = &floppy_fiqin_start;
153 fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start;
154 } else {
155 extern unsigned char floppy_fiqout_start, floppy_fiqout_end;
156 fiqhandler_start = &floppy_fiqout_start;
157 fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start;
158 }
159 if (claim_fiq(&fh)) {
160 printk("floppydma: couldn't claim FIQ.\n");
161 return;
162 }
163 memcpy((void *)0x1c, fiqhandler_start, fiqhandler_length);
164 regs.ARM_r9 = dma->buf.length;
165 regs.ARM_r10 = (unsigned long)dma->buf.__address;
166 regs.ARM_fp = FLOPPYDMA_BASE;
167 set_fiq_regs(&regs);
168 enable_fiq(dma->dma_irq);
169}
170
171static void a5k_floppy_disable_dma(dmach_t channel, dma_t *dma)
172{
173 disable_fiq(dma->dma_irq);
174 release_fiq(&fh);
175}
176
177static struct dma_ops a5k_floppy_dma_ops = {
178 .type = "FIQDMA",
179 .enable = a5k_floppy_enable_dma,
180 .disable = a5k_floppy_disable_dma,
181 .residue = a5k_floppy_get_dma_residue,
182};
183#endif
184
185/*
186 * This is virtual DMA - we don't need anything here
187 */
188static void sound_enable_disable_dma(dmach_t channel, dma_t *dma)
189{
190}
191
192static struct dma_ops sound_dma_ops = {
193 .type = "VIRTUAL",
194 .enable = sound_enable_disable_dma,
195 .disable = sound_enable_disable_dma,
196};
197
198void __init arch_dma_init(dma_t *dma)
199{
200#if defined(CONFIG_BLK_DEV_FD1772) || defined(CONFIG_BLK_DEV_FD1772_MODULE)
201 if (machine_is_archimedes()) {
202 dma[DMA_VIRTUAL_FLOPPY0].dma_irq = FIQ_FLOPPYDATA;
203 dma[DMA_VIRTUAL_FLOPPY0].d_ops = &arc_floppy_data_dma_ops;
204 dma[DMA_VIRTUAL_FLOPPY1].dma_irq = 1;
205 dma[DMA_VIRTUAL_FLOPPY1].d_ops = &arc_floppy_cmdend_dma_ops;
206 }
207#endif
208#ifdef CONFIG_ARCH_A5K
209 if (machine_is_a5k()) {
210 dma[DMA_VIRTUAL_FLOPPY0].dma_irq = FIQ_FLOPPYDATA;
211 dma[DMA_VIRTUAL_FLOPPY0].d_ops = &a5k_floppy_dma_ops;
212 }
213#endif
214 dma[DMA_VIRTUAL_SOUND].d_ops = &sound_dma_ops;
215}
diff --git a/arch/arm26/machine/irq.c b/arch/arm26/machine/irq.c
new file mode 100644
index 000000000000..4361863f7ed2
--- /dev/null
+++ b/arch/arm26/machine/irq.c
@@ -0,0 +1,165 @@
1/*
2 * linux/arch/arm26/mach-arc/irq.c
3 *
4 * Copyright (C) 1996 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Changelog:
11 * 24-09-1996 RMK Created
12 * 10-10-1996 RMK Brought up to date with arch-sa110eval
13 * 22-10-1996 RMK Changed interrupt numbers & uses new inb/outb macros
14 * 11-01-1998 RMK Added mask_and_ack_irq
15 * 22-08-1998 RMK Restructured IRQ routines
16 * 08-09-2002 IM Brought up to date for 2.5
17 * 01-06-2003 JMA Removed arc_fiq_chip
18 */
19#include <linux/config.h>
20#include <linux/init.h>
21
22#include <asm/irq.h>
23#include <asm/irqchip.h>
24#include <asm/ioc.h>
25#include <asm/io.h>
26#include <asm/system.h>
27
28extern void init_FIQ(void);
29
30#define a_clf() clf()
31#define a_stf() stf()
32
33static void arc_ack_irq_a(unsigned int irq)
34{
35 unsigned int val, mask;
36
37 mask = 1 << irq;
38 a_clf();
39 val = ioc_readb(IOC_IRQMASKA);
40 ioc_writeb(val & ~mask, IOC_IRQMASKA);
41 ioc_writeb(mask, IOC_IRQCLRA);
42 a_stf();
43}
44
45static void arc_mask_irq_a(unsigned int irq)
46{
47 unsigned int val, mask;
48
49 mask = 1 << irq;
50 a_clf();
51 val = ioc_readb(IOC_IRQMASKA);
52 ioc_writeb(val & ~mask, IOC_IRQMASKA);
53 a_stf();
54}
55
56static void arc_unmask_irq_a(unsigned int irq)
57{
58 unsigned int val, mask;
59
60 mask = 1 << irq;
61 a_clf();
62 val = ioc_readb(IOC_IRQMASKA);
63 ioc_writeb(val | mask, IOC_IRQMASKA);
64 a_stf();
65}
66
67static struct irqchip arc_a_chip = {
68 .ack = arc_ack_irq_a,
69 .mask = arc_mask_irq_a,
70 .unmask = arc_unmask_irq_a,
71};
72
73static void arc_mask_irq_b(unsigned int irq)
74{
75 unsigned int val, mask;
76 mask = 1 << (irq & 7);
77 val = ioc_readb(IOC_IRQMASKB);
78 ioc_writeb(val & ~mask, IOC_IRQMASKB);
79}
80
81static void arc_unmask_irq_b(unsigned int irq)
82{
83 unsigned int val, mask;
84
85 mask = 1 << (irq & 7);
86 val = ioc_readb(IOC_IRQMASKB);
87 ioc_writeb(val | mask, IOC_IRQMASKB);
88}
89
90static struct irqchip arc_b_chip = {
91 .ack = arc_mask_irq_b,
92 .mask = arc_mask_irq_b,
93 .unmask = arc_unmask_irq_b,
94};
95
96/* FIXME - JMA none of these functions are used in arm26 currently
97static void arc_mask_irq_fiq(unsigned int irq)
98{
99 unsigned int val, mask;
100
101 mask = 1 << (irq & 7);
102 val = ioc_readb(IOC_FIQMASK);
103 ioc_writeb(val & ~mask, IOC_FIQMASK);
104}
105
106static void arc_unmask_irq_fiq(unsigned int irq)
107{
108 unsigned int val, mask;
109
110 mask = 1 << (irq & 7);
111 val = ioc_readb(IOC_FIQMASK);
112 ioc_writeb(val | mask, IOC_FIQMASK);
113}
114
115static struct irqchip arc_fiq_chip = {
116 .ack = arc_mask_irq_fiq,
117 .mask = arc_mask_irq_fiq,
118 .unmask = arc_unmask_irq_fiq,
119};
120*/
121
122void __init arc_init_irq(void)
123{
124 unsigned int irq, flags;
125
126 /* Disable all IOC interrupt sources */
127 ioc_writeb(0, IOC_IRQMASKA);
128 ioc_writeb(0, IOC_IRQMASKB);
129 ioc_writeb(0, IOC_FIQMASK);
130
131 for (irq = 0; irq < NR_IRQS; irq++) {
132 flags = IRQF_VALID;
133
134 if (irq <= 6 || (irq >= 9 && irq <= 15))
135 flags |= IRQF_PROBE;
136
137 if (irq == IRQ_KEYBOARDTX)
138 flags |= IRQF_NOAUTOEN;
139
140 switch (irq) {
141 case 0 ... 7:
142 set_irq_chip(irq, &arc_a_chip);
143 set_irq_handler(irq, do_level_IRQ);
144 set_irq_flags(irq, flags);
145 break;
146
147 case 8 ... 15:
148 set_irq_chip(irq, &arc_b_chip);
149 set_irq_handler(irq, do_level_IRQ);
150 set_irq_flags(irq, flags);
151
152/* case 64 ... 72:
153 set_irq_chip(irq, &arc_fiq_chip);
154 set_irq_flags(irq, flags);
155 break;
156*/
157
158 }
159 }
160
161 irq_desc[IRQ_KEYBOARDTX].noautoenable = 1;
162
163 init_FIQ();
164}
165
diff --git a/arch/arm26/machine/latches.c b/arch/arm26/machine/latches.c
new file mode 100644
index 000000000000..94f05d2a3b2b
--- /dev/null
+++ b/arch/arm26/machine/latches.c
@@ -0,0 +1,72 @@
1/*
2 * linux/arch/arm26/kernel/latches.c
3 *
4 * Copyright (C) David Alan Gilbert 1995/1996,2000
5 * Copyright (C) Ian Molton 2003
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Support for the latches on the old Archimedes which control the floppy,
12 * hard disc and printer
13 */
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/sched.h>
18
19#include <asm/io.h>
20#include <asm/hardware.h>
21#include <asm/mach-types.h>
22#include <asm/oldlatches.h>
23
24static unsigned char latch_a_copy;
25static unsigned char latch_b_copy;
26
27/* newval=(oldval & ~mask)|newdata */
28void oldlatch_aupdate(unsigned char mask,unsigned char newdata)
29{
30 unsigned long flags;
31
32 BUG_ON(!machine_is_archimedes());
33
34 local_irq_save(flags); //FIXME: was local_save_flags
35 latch_a_copy = (latch_a_copy & ~mask) | newdata;
36 __raw_writeb(latch_a_copy, LATCHA_BASE);
37 local_irq_restore(flags);
38
39 printk("Latch: A = 0x%02x\n", latch_a_copy);
40}
41
42
43/* newval=(oldval & ~mask)|newdata */
44void oldlatch_bupdate(unsigned char mask,unsigned char newdata)
45{
46 unsigned long flags;
47
48 BUG_ON(!machine_is_archimedes());
49
50
51 local_irq_save(flags);//FIXME: was local_save_flags
52 latch_b_copy = (latch_b_copy & ~mask) | newdata;
53 __raw_writeb(latch_b_copy, LATCHB_BASE);
54 local_irq_restore(flags);
55
56 printk("Latch: B = 0x%02x\n", latch_b_copy);
57}
58
59static int __init oldlatch_init(void)
60{
61 if (machine_is_archimedes()) {
62 oldlatch_aupdate(0xff, 0xff);
63 /* Thats no FDC reset...*/
64 oldlatch_bupdate(0xff, LATCHB_FDCRESET);
65 }
66 return 0;
67}
68
69arch_initcall(oldlatch_init);
70
71EXPORT_SYMBOL(oldlatch_aupdate);
72EXPORT_SYMBOL(oldlatch_bupdate);
diff --git a/arch/arm26/mm/Makefile b/arch/arm26/mm/Makefile
new file mode 100644
index 000000000000..a8fb166d5c6d
--- /dev/null
+++ b/arch/arm26/mm/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for the linux arm26-specific parts of the memory manager.
3#
4
5obj-y := init.o extable.o proc-funcs.o memc.o fault.o \
6 small_page.o
diff --git a/arch/arm26/mm/extable.c b/arch/arm26/mm/extable.c
new file mode 100644
index 000000000000..2d9f5b5a78d6
--- /dev/null
+++ b/arch/arm26/mm/extable.c
@@ -0,0 +1,25 @@
1/*
2 * linux/arch/arm26/mm/extable.c
3 */
4
5#include <linux/config.h>
6#include <linux/module.h>
7#include <asm/uaccess.h>
8
9int fixup_exception(struct pt_regs *regs)
10{
11 const struct exception_table_entry *fixup;
12
13 fixup = search_exception_tables(instruction_pointer(regs));
14
15 /*
16 * The kernel runs in SVC mode - make sure we keep running in SVC mode
17 * by frobbing the PSR appropriately (PSR and PC are in the same reg.
18 * on ARM26)
19 */
20 if (fixup)
21 regs->ARM_pc = fixup->fixup | PSR_I_BIT | MODE_SVC26;
22
23 return fixup != NULL;
24}
25
diff --git a/arch/arm26/mm/fault.c b/arch/arm26/mm/fault.c
new file mode 100644
index 000000000000..dacca8bb7744
--- /dev/null
+++ b/arch/arm26/mm/fault.c
@@ -0,0 +1,318 @@
1/*
2 * linux/arch/arm26/mm/fault.c
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 * Modifications for ARM processor (c) 1995-2001 Russell King
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/config.h>
12#include <linux/signal.h>
13#include <linux/sched.h>
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/string.h>
17#include <linux/types.h>
18#include <linux/ptrace.h>
19#include <linux/mman.h>
20#include <linux/mm.h>
21#include <linux/interrupt.h>
22#include <linux/proc_fs.h>
23#include <linux/init.h>
24
25#include <asm/system.h>
26#include <asm/pgtable.h>
27#include <asm/uaccess.h> //FIXME this header may be bogusly included
28
29#include "fault.h"
30
31#define FAULT_CODE_LDRSTRPOST 0x80
32#define FAULT_CODE_LDRSTRPRE 0x40
33#define FAULT_CODE_LDRSTRREG 0x20
34#define FAULT_CODE_LDMSTM 0x10
35#define FAULT_CODE_LDCSTC 0x08
36#define FAULT_CODE_PREFETCH 0x04
37#define FAULT_CODE_WRITE 0x02
38#define FAULT_CODE_FORCECOW 0x01
39
40#define DO_COW(m) ((m) & (FAULT_CODE_WRITE|FAULT_CODE_FORCECOW))
41#define READ_FAULT(m) (!((m) & FAULT_CODE_WRITE))
42#define DEBUG
43/*
44 * This is useful to dump out the page tables associated with
45 * 'addr' in mm 'mm'.
46 */
47void show_pte(struct mm_struct *mm, unsigned long addr)
48{
49 pgd_t *pgd;
50
51 if (!mm)
52 mm = &init_mm;
53
54 printk(KERN_ALERT "pgd = %p\n", mm->pgd);
55 pgd = pgd_offset(mm, addr);
56 printk(KERN_ALERT "[%08lx] *pgd=%08lx", addr, pgd_val(*pgd));
57
58 do {
59 pmd_t *pmd;
60 pte_t *pte;
61
62 pmd = pmd_offset(pgd, addr);
63
64 if (pmd_none(*pmd))
65 break;
66
67 if (pmd_bad(*pmd)) {
68 printk("(bad)");
69 break;
70 }
71
72 /* We must not map this if we have highmem enabled */
73 /* FIXME */
74 pte = pte_offset_map(pmd, addr);
75 printk(", *pte=%08lx", pte_val(*pte));
76 pte_unmap(pte);
77 } while(0);
78
79 printk("\n");
80}
81
82/*
83 * Oops. The kernel tried to access some page that wasn't present.
84 */
85static void
86__do_kernel_fault(struct mm_struct *mm, unsigned long addr, unsigned int fsr,
87 struct pt_regs *regs)
88{
89 /*
90 * Are we prepared to handle this kernel fault?
91 */
92 if (fixup_exception(regs))
93 return;
94
95 /*
96 * No handler, we'll have to terminate things with extreme prejudice.
97 */
98 bust_spinlocks(1);
99 printk(KERN_ALERT
100 "Unable to handle kernel %s at virtual address %08lx\n",
101 (addr < PAGE_SIZE) ? "NULL pointer dereference" :
102 "paging request", addr);
103
104 show_pte(mm, addr);
105 die("Oops", regs, fsr);
106 bust_spinlocks(0);
107 do_exit(SIGKILL);
108}
109
110/*
111 * Something tried to access memory that isn't in our memory map..
112 * User mode accesses just cause a SIGSEGV
113 */
114static void
115__do_user_fault(struct task_struct *tsk, unsigned long addr,
116 unsigned int fsr, int code, struct pt_regs *regs)
117{
118 struct siginfo si;
119
120#ifdef CONFIG_DEBUG_USER
121 printk("%s: unhandled page fault at 0x%08lx, code 0x%03x\n",
122 tsk->comm, addr, fsr);
123 show_pte(tsk->mm, addr);
124 show_regs(regs);
125 //dump_backtrace(regs, tsk); // FIXME ARM32 dropped this - why?
126 while(1); //FIXME - hack to stop debug going nutso
127#endif
128
129 tsk->thread.address = addr;
130 tsk->thread.error_code = fsr;
131 tsk->thread.trap_no = 14;
132 si.si_signo = SIGSEGV;
133 si.si_errno = 0;
134 si.si_code = code;
135 si.si_addr = (void *)addr;
136 force_sig_info(SIGSEGV, &si, tsk);
137}
138
139static int
140__do_page_fault(struct mm_struct *mm, unsigned long addr, unsigned int fsr,
141 struct task_struct *tsk)
142{
143 struct vm_area_struct *vma;
144 int fault, mask;
145
146 vma = find_vma(mm, addr);
147 fault = -2; /* bad map area */
148 if (!vma)
149 goto out;
150 if (vma->vm_start > addr)
151 goto check_stack;
152
153 /*
154 * Ok, we have a good vm_area for this
155 * memory access, so we can handle it.
156 */
157good_area:
158 if (READ_FAULT(fsr)) /* read? */
159 mask = VM_READ|VM_EXEC;
160 else
161 mask = VM_WRITE;
162
163 fault = -1; /* bad access type */
164 if (!(vma->vm_flags & mask))
165 goto out;
166
167 /*
168 * If for any reason at all we couldn't handle
169 * the fault, make sure we exit gracefully rather
170 * than endlessly redo the fault.
171 */
172survive:
173 fault = handle_mm_fault(mm, vma, addr & PAGE_MASK, DO_COW(fsr));
174
175 /*
176 * Handle the "normal" cases first - successful and sigbus
177 */
178 switch (fault) {
179 case 2:
180 tsk->maj_flt++;
181 return fault;
182 case 1:
183 tsk->min_flt++;
184 case 0:
185 return fault;
186 }
187
188 fault = -3; /* out of memory */
189 if (tsk->pid != 1)
190 goto out;
191
192 /*
193 * If we are out of memory for pid1,
194 * sleep for a while and retry
195 */
196 yield();
197 goto survive;
198
199check_stack:
200 if (vma->vm_flags & VM_GROWSDOWN && !expand_stack(vma, addr))
201 goto good_area;
202out:
203 return fault;
204}
205
206int do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
207{
208 struct task_struct *tsk;
209 struct mm_struct *mm;
210 int fault;
211
212 tsk = current;
213 mm = tsk->mm;
214
215 /*
216 * If we're in an interrupt or have no user
217 * context, we must not take the fault..
218 */
219 if (in_interrupt() || !mm)
220 goto no_context;
221
222 down_read(&mm->mmap_sem);
223 fault = __do_page_fault(mm, addr, fsr, tsk);
224 up_read(&mm->mmap_sem);
225
226 /*
227 * Handle the "normal" case first
228 */
229 if (fault > 0)
230 return 0;
231
232 /*
233 * We had some memory, but were unable to
234 * successfully fix up this page fault.
235 */
236 if (fault == 0){
237 goto do_sigbus;
238 }
239
240 /*
241 * If we are in kernel mode at this point, we
242 * have no context to handle this fault with.
243 * FIXME - is this test right?
244 */
245 if (!user_mode(regs)){
246 goto no_context;
247 }
248
249 if (fault == -3) {
250 /*
251 * We ran out of memory, or some other thing happened to
252 * us that made us unable to handle the page fault gracefully.
253 */
254 printk("VM: killing process %s\n", tsk->comm);
255 do_exit(SIGKILL);
256 }
257 else{
258 __do_user_fault(tsk, addr, fsr, fault == -1 ? SEGV_ACCERR : SEGV_MAPERR, regs);
259 }
260
261 return 0;
262
263
264/*
265 * We ran out of memory, or some other thing happened to us that made
266 * us unable to handle the page fault gracefully.
267 */
268do_sigbus:
269 /*
270 * Send a sigbus, regardless of whether we were in kernel
271 * or user mode.
272 */
273 tsk->thread.address = addr; //FIXME - need other bits setting?
274 tsk->thread.error_code = fsr;
275 tsk->thread.trap_no = 14;
276 force_sig(SIGBUS, tsk);
277#ifdef CONFIG_DEBUG_USER
278 printk(KERN_DEBUG "%s: sigbus at 0x%08lx, pc=0x%08lx\n",
279 current->comm, addr, instruction_pointer(regs));
280#endif
281
282 /* Kernel mode? Handle exceptions or die */
283 if (user_mode(regs))
284 return 0;
285
286no_context:
287 __do_kernel_fault(mm, addr, fsr, regs);
288 return 0;
289}
290
291/*
292 * Handle a data abort. Note that we have to handle a range of addresses
293 * on ARM2/3 for ldm. If both pages are zero-mapped, then we have to force
294 * a copy-on-write. However, on the second page, we always force COW.
295 */
296asmlinkage void
297do_DataAbort(unsigned long min_addr, unsigned long max_addr, int mode, struct pt_regs *regs)
298{
299 do_page_fault(min_addr, mode, regs);
300
301 if ((min_addr ^ max_addr) >> PAGE_SHIFT){
302 do_page_fault(max_addr, mode | FAULT_CODE_FORCECOW, regs);
303 }
304}
305
306asmlinkage int
307do_PrefetchAbort(unsigned long addr, struct pt_regs *regs)
308{
309#if 0
310 if (the memc mapping for this page exists) {
311 printk ("Page in, but got abort (undefined instruction?)\n");
312 return 0;
313 }
314#endif
315 do_page_fault(addr, FAULT_CODE_PREFETCH, regs);
316 return 1;
317}
318
diff --git a/arch/arm26/mm/fault.h b/arch/arm26/mm/fault.h
new file mode 100644
index 000000000000..4442d00d86ac
--- /dev/null
+++ b/arch/arm26/mm/fault.h
@@ -0,0 +1,5 @@
1void show_pte(struct mm_struct *mm, unsigned long addr);
2
3int do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs);
4
5unsigned long search_extable(unsigned long addr); //FIXME - is it right?
diff --git a/arch/arm26/mm/init.c b/arch/arm26/mm/init.c
new file mode 100644
index 000000000000..1f09a9d0fb83
--- /dev/null
+++ b/arch/arm26/mm/init.c
@@ -0,0 +1,412 @@
1/*
2 * linux/arch/arm26/mm/init.c
3 *
4 * Copyright (C) 1995-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/config.h>
11#include <linux/signal.h>
12#include <linux/sched.h>
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/string.h>
16#include <linux/types.h>
17#include <linux/ptrace.h>
18#include <linux/mman.h>
19#include <linux/mm.h>
20#include <linux/swap.h>
21#include <linux/smp.h>
22#include <linux/init.h>
23#include <linux/initrd.h>
24#include <linux/bootmem.h>
25#include <linux/blkdev.h>
26
27#include <asm/segment.h>
28#include <asm/mach-types.h>
29#include <asm/dma.h>
30#include <asm/hardware.h>
31#include <asm/setup.h>
32#include <asm/tlb.h>
33
34#include <asm/map.h>
35
36
37#define TABLE_SIZE PTRS_PER_PTE * sizeof(pte_t))
38
39struct mmu_gather mmu_gathers[NR_CPUS];
40
41extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
42extern char _stext, _text, _etext, _end, __init_begin, __init_end;
43#ifdef CONFIG_XIP_KERNEL
44extern char _endtext, _sdata;
45#endif
46extern unsigned long phys_initrd_start;
47extern unsigned long phys_initrd_size;
48
49/*
50 * The sole use of this is to pass memory configuration
51 * data from paging_init to mem_init.
52 */
53static struct meminfo meminfo __initdata = { 0, };
54
55/*
56 * empty_zero_page is a special page that is used for
57 * zero-initialized data and COW.
58 */
59struct page *empty_zero_page;
60
61void show_mem(void)
62{
63 int free = 0, total = 0, reserved = 0;
64 int shared = 0, cached = 0, slab = 0;
65 struct page *page, *end;
66
67 printk("Mem-info:\n");
68 show_free_areas();
69 printk("Free swap: %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
70
71
72 page = NODE_MEM_MAP(0);
73 end = page + NODE_DATA(0)->node_spanned_pages;
74
75 do {
76 total++;
77 if (PageReserved(page))
78 reserved++;
79 else if (PageSwapCache(page))
80 cached++;
81 else if (PageSlab(page))
82 slab++;
83 else if (!page_count(page))
84 free++;
85 else
86 shared += page_count(page) - 1;
87 page++;
88 } while (page < end);
89
90 printk("%d pages of RAM\n", total);
91 printk("%d free pages\n", free);
92 printk("%d reserved pages\n", reserved);
93 printk("%d slab pages\n", slab);
94 printk("%d pages shared\n", shared);
95 printk("%d pages swap cached\n", cached);
96}
97
98struct node_info {
99 unsigned int start;
100 unsigned int end;
101 int bootmap_pages;
102};
103
104#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
105#define PFN_UP(x) (PAGE_ALIGN(x) >> PAGE_SHIFT)
106#define PFN_SIZE(x) ((x) >> PAGE_SHIFT)
107#define PFN_RANGE(s,e) PFN_SIZE(PAGE_ALIGN((unsigned long)(e)) - \
108 (((unsigned long)(s)) & PAGE_MASK))
109
110/*
111 * FIXME: We really want to avoid allocating the bootmap bitmap
112 * over the top of the initrd. Hopefully, this is located towards
113 * the start of a bank, so if we allocate the bootmap bitmap at
114 * the end, we won't clash.
115 */
116static unsigned int __init
117find_bootmap_pfn(struct meminfo *mi, unsigned int bootmap_pages)
118{
119 unsigned int start_pfn, bootmap_pfn;
120 unsigned int start, end;
121
122 start_pfn = PFN_UP((unsigned long)&_end);
123 bootmap_pfn = 0;
124
125 /* ARM26 machines only have one node */
126 if (mi->bank->node != 0)
127 BUG();
128
129 start = PFN_UP(mi->bank->start);
130 end = PFN_DOWN(mi->bank->size + mi->bank->start);
131
132 if (start < start_pfn)
133 start = start_pfn;
134
135 if (end <= start)
136 BUG();
137
138 if (end - start >= bootmap_pages)
139 bootmap_pfn = start;
140 else
141 BUG();
142
143 return bootmap_pfn;
144}
145
146/*
147 * Scan the memory info structure and pull out:
148 * - the end of memory
149 * - the number of nodes
150 * - the pfn range of each node
151 * - the number of bootmem bitmap pages
152 */
153static void __init
154find_memend_and_nodes(struct meminfo *mi, struct node_info *np)
155{
156 unsigned int memend_pfn = 0;
157
158 nodes_clear(node_online_map);
159 node_set_online(0);
160
161 np->bootmap_pages = 0;
162
163 if (mi->bank->size == 0) {
164 BUG();
165 }
166
167 /*
168 * Get the start and end pfns for this bank
169 */
170 np->start = PFN_UP(mi->bank->start);
171 np->end = PFN_DOWN(mi->bank->start + mi->bank->size);
172
173 if (memend_pfn < np->end)
174 memend_pfn = np->end;
175
176 /*
177 * Calculate the number of pages we require to
178 * store the bootmem bitmaps.
179 */
180 np->bootmap_pages = bootmem_bootmap_pages(np->end - np->start);
181
182 /*
183 * This doesn't seem to be used by the Linux memory
184 * manager any more. If we can get rid of it, we
185 * also get rid of some of the stuff above as well.
186 */
187 max_low_pfn = memend_pfn - PFN_DOWN(PHYS_OFFSET);
188 max_pfn = memend_pfn - PFN_DOWN(PHYS_OFFSET);
189 mi->end = memend_pfn << PAGE_SHIFT;
190
191}
192
193/*
194 * Initialise the bootmem allocator for all nodes. This is called
195 * early during the architecture specific initialisation.
196 */
197void __init bootmem_init(struct meminfo *mi)
198{
199 struct node_info node_info;
200 unsigned int bootmap_pfn;
201 pg_data_t *pgdat = NODE_DATA(0);
202
203 find_memend_and_nodes(mi, &node_info);
204
205 bootmap_pfn = find_bootmap_pfn(mi, node_info.bootmap_pages);
206
207 /*
208 * Note that node 0 must always have some pages.
209 */
210 if (node_info.end == 0)
211 BUG();
212
213 /*
214 * Initialise the bootmem allocator.
215 */
216 init_bootmem_node(pgdat, bootmap_pfn, node_info.start, node_info.end);
217
218 /*
219 * Register all available RAM in this node with the bootmem allocator.
220 */
221 free_bootmem_node(pgdat, mi->bank->start, mi->bank->size);
222
223 /*
224 * Register the kernel text and data with bootmem.
225 * Note: with XIP we dont register .text since
226 * its in ROM.
227 */
228#ifdef CONFIG_XIP_KERNEL
229 reserve_bootmem_node(pgdat, __pa(&_sdata), &_end - &_sdata);
230#else
231 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext);
232#endif
233
234 /*
235 * And don't forget to reserve the allocator bitmap,
236 * which will be freed later.
237 */
238 reserve_bootmem_node(pgdat, bootmap_pfn << PAGE_SHIFT,
239 node_info.bootmap_pages << PAGE_SHIFT);
240
241 /*
242 * These should likewise go elsewhere. They pre-reserve
243 * the screen memory region at the start of main system
244 * memory. FIXME - screen RAM is not 512K!
245 */
246 reserve_bootmem_node(pgdat, 0x02000000, 0x00080000);
247
248#ifdef CONFIG_BLK_DEV_INITRD
249 initrd_start = phys_initrd_start;
250 initrd_end = initrd_start + phys_initrd_size;
251
252 /* Achimedes machines only have one node, so initrd is in node 0 */
253#ifdef CONFIG_XIP_KERNEL
254 /* Only reserve initrd space if it is in RAM */
255 if(initrd_start && initrd_start < 0x03000000){
256#else
257 if(initrd_start){
258#endif
259 reserve_bootmem_node(pgdat, __pa(initrd_start),
260 initrd_end - initrd_start);
261 }
262#endif /* CONFIG_BLK_DEV_INITRD */
263
264
265}
266
267/*
268 * paging_init() sets up the page tables, initialises the zone memory
269 * maps, and sets up the zero page, bad page and bad page tables.
270 */
271void __init paging_init(struct meminfo *mi)
272{
273 void *zero_page;
274 unsigned long zone_size[MAX_NR_ZONES];
275 unsigned long zhole_size[MAX_NR_ZONES];
276 struct bootmem_data *bdata;
277 pg_data_t *pgdat;
278 int i;
279
280 memcpy(&meminfo, mi, sizeof(meminfo));
281
282 /*
283 * allocate the zero page. Note that we count on this going ok.
284 */
285 zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
286
287 /*
288 * initialise the page tables.
289 */
290 memtable_init(mi);
291 flush_tlb_all();
292
293 /*
294 * initialise the zones in node 0 (archimedes have only 1 node)
295 */
296
297 for (i = 0; i < MAX_NR_ZONES; i++) {
298 zone_size[i] = 0;
299 zhole_size[i] = 0;
300 }
301
302 pgdat = NODE_DATA(0);
303 bdata = pgdat->bdata;
304 zone_size[0] = bdata->node_low_pfn -
305 (bdata->node_boot_start >> PAGE_SHIFT);
306 if (!zone_size[0])
307 BUG();
308 pgdat->node_mem_map = NULL;
309 free_area_init_node(0, pgdat, zone_size,
310 bdata->node_boot_start >> PAGE_SHIFT, zhole_size);
311
312 /*
313 * finish off the bad pages once
314 * the mem_map is initialised
315 */
316 memzero(zero_page, PAGE_SIZE);
317 empty_zero_page = virt_to_page(zero_page);
318}
319
320static inline void free_area(unsigned long addr, unsigned long end, char *s)
321{
322 unsigned int size = (end - addr) >> 10;
323
324 for (; addr < end; addr += PAGE_SIZE) {
325 struct page *page = virt_to_page(addr);
326 ClearPageReserved(page);
327 set_page_count(page, 1);
328 free_page(addr);
329 totalram_pages++;
330 }
331
332 if (size && s)
333 printk(KERN_INFO "Freeing %s memory: %dK\n", s, size);
334}
335
336/*
337 * mem_init() marks the free areas in the mem_map and tells us how much
338 * memory is free. This is done after various parts of the system have
339 * claimed their memory after the kernel image.
340 */
341void __init mem_init(void)
342{
343 unsigned int codepages, datapages, initpages;
344 pg_data_t *pgdat = NODE_DATA(0);
345 extern int sysctl_overcommit_memory;
346
347
348 /* Note: data pages includes BSS */
349#ifdef CONFIG_XIP_KERNEL
350 codepages = &_endtext - &_text;
351 datapages = &_end - &_sdata;
352#else
353 codepages = &_etext - &_text;
354 datapages = &_end - &_etext;
355#endif
356 initpages = &__init_end - &__init_begin;
357
358 high_memory = (void *)__va(meminfo.end);
359 max_mapnr = virt_to_page(high_memory) - mem_map;
360
361 /* this will put all unused low memory onto the freelists */
362 if (pgdat->node_spanned_pages != 0)
363 totalram_pages += free_all_bootmem_node(pgdat);
364
365 num_physpages = meminfo.bank[0].size >> PAGE_SHIFT;
366
367 printk(KERN_INFO "Memory: %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
368 printk(KERN_NOTICE "Memory: %luKB available (%dK code, "
369 "%dK data, %dK init)\n",
370 (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
371 codepages >> 10, datapages >> 10, initpages >> 10);
372
373 /*
374 * Turn on overcommit on tiny machines
375 */
376 if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
377 sysctl_overcommit_memory = OVERCOMMIT_ALWAYS;
378 printk("Turning on overcommit\n");
379 }
380}
381
382void free_initmem(void){
383#ifndef CONFIG_XIP_KERNEL
384 free_area((unsigned long)(&__init_begin),
385 (unsigned long)(&__init_end),
386 "init");
387#endif
388}
389
390#ifdef CONFIG_BLK_DEV_INITRD
391
392static int keep_initrd;
393
394void free_initrd_mem(unsigned long start, unsigned long end)
395{
396#ifdef CONFIG_XIP_KERNEL
397 /* Only bin initrd if it is in RAM... */
398 if(!keep_initrd && start < 0x03000000)
399#else
400 if (!keep_initrd)
401#endif
402 free_area(start, end, "initrd");
403}
404
405static int __init keepinitrd_setup(char *__unused)
406{
407 keep_initrd = 1;
408 return 1;
409}
410
411__setup("keepinitrd", keepinitrd_setup);
412#endif
diff --git a/arch/arm26/mm/memc.c b/arch/arm26/mm/memc.c
new file mode 100644
index 000000000000..8e8a2bb2487d
--- /dev/null
+++ b/arch/arm26/mm/memc.c
@@ -0,0 +1,202 @@
1/*
2 * linux/arch/arm26/mm/memc.c
3 *
4 * Copyright (C) 1998-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Page table sludge for older ARM processor architectures.
11 */
12#include <linux/sched.h>
13#include <linux/mm.h>
14#include <linux/init.h>
15#include <linux/bootmem.h>
16
17#include <asm/pgtable.h>
18#include <asm/pgalloc.h>
19#include <asm/page.h>
20#include <asm/memory.h>
21#include <asm/hardware.h>
22
23#include <asm/map.h>
24
25#define MEMC_TABLE_SIZE (256*sizeof(unsigned long))
26
27kmem_cache_t *pte_cache, *pgd_cache;
28int page_nr;
29
30/*
31 * Allocate space for a page table and a MEMC table.
32 * Note that we place the MEMC
33 * table before the page directory. This means we can
34 * easily get to both tightly-associated data structures
35 * with a single pointer.
36 */
37static inline pgd_t *alloc_pgd_table(void)
38{
39 void *pg2k = kmem_cache_alloc(pgd_cache, GFP_KERNEL);
40
41 if (pg2k)
42 pg2k += MEMC_TABLE_SIZE;
43
44 return (pgd_t *)pg2k;
45}
46
47/*
48 * Free a page table. this function is the counterpart to get_pgd_slow
49 * below, not alloc_pgd_table above.
50 */
51void free_pgd_slow(pgd_t *pgd)
52{
53 unsigned long tbl = (unsigned long)pgd;
54
55 tbl -= MEMC_TABLE_SIZE;
56
57 kmem_cache_free(pgd_cache, (void *)tbl);
58}
59
60/*
61 * Allocate a new pgd and fill it in ready for use
62 *
63 * A new tasks pgd is completely empty (all pages !present) except for:
64 *
65 * o The machine vectors at virtual address 0x0
66 * o The vmalloc region at the top of address space
67 *
68 */
69#define FIRST_KERNEL_PGD_NR (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD)
70
71pgd_t *get_pgd_slow(struct mm_struct *mm)
72{
73 pgd_t *new_pgd, *init_pgd;
74 pmd_t *new_pmd, *init_pmd;
75 pte_t *new_pte, *init_pte;
76
77 new_pgd = alloc_pgd_table();
78 if (!new_pgd)
79 goto no_pgd;
80
81 /*
82 * This lock is here just to satisfy pmd_alloc and pte_lock
83 * FIXME: I bet we could avoid taking it pretty much altogether
84 */
85 spin_lock(&mm->page_table_lock);
86
87 /*
88 * On ARM, first page must always be allocated since it contains
89 * the machine vectors.
90 */
91 new_pmd = pmd_alloc(mm, new_pgd, 0);
92 if (!new_pmd)
93 goto no_pmd;
94
95 new_pte = pte_alloc_kernel(mm, new_pmd, 0);
96 if (!new_pte)
97 goto no_pte;
98
99 init_pgd = pgd_offset(&init_mm, 0);
100 init_pmd = pmd_offset(init_pgd, 0);
101 init_pte = pte_offset(init_pmd, 0);
102
103 set_pte(new_pte, *init_pte);
104
105 /*
106 * the page table entries are zeroed
107 * when the table is created. (see the cache_ctor functions below)
108 * Now we need to plonk the kernel (vmalloc) area at the end of
109 * the address space. We copy this from the init thread, just like
110 * the init_pte we copied above...
111 */
112 memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR,
113 (PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t));
114
115 spin_unlock(&mm->page_table_lock);
116
117 /* update MEMC tables */
118 cpu_memc_update_all(new_pgd);
119 return new_pgd;
120
121no_pte:
122 spin_unlock(&mm->page_table_lock);
123 pmd_free(new_pmd);
124 free_pgd_slow(new_pgd);
125 return NULL;
126
127no_pmd:
128 spin_unlock(&mm->page_table_lock);
129 free_pgd_slow(new_pgd);
130 return NULL;
131
132no_pgd:
133 return NULL;
134}
135
136/*
137 * No special code is required here.
138 */
139void setup_mm_for_reboot(char mode)
140{
141}
142
143/*
144 * This contains the code to setup the memory map on an ARM2/ARM250/ARM3
145 * o swapper_pg_dir = 0x0207d000
146 * o kernel proper starts at 0x0208000
147 * o create (allocate) a pte to contain the machine vectors
148 * o populate the pte (points to 0x02078000) (FIXME - is it zeroed?)
149 * o populate the init tasks page directory (pgd) with the new pte
150 * o zero the rest of the init tasks pgdir (FIXME - what about vmalloc?!)
151 */
152void __init memtable_init(struct meminfo *mi)
153{
154 pte_t *pte;
155 int i;
156
157 page_nr = max_low_pfn;
158
159 pte = alloc_bootmem_low_pages(PTRS_PER_PTE * sizeof(pte_t));
160 pte[0] = mk_pte_phys(PAGE_OFFSET + SCREEN_SIZE, PAGE_READONLY);
161 pmd_populate(&init_mm, pmd_offset(swapper_pg_dir, 0), pte);
162
163 for (i = 1; i < PTRS_PER_PGD; i++)
164 pgd_val(swapper_pg_dir[i]) = 0;
165}
166
167void __init iotable_init(struct map_desc *io_desc)
168{
169 /* nothing to do */
170}
171
172/*
173 * We never have holes in the memmap
174 */
175void __init create_memmap_holes(struct meminfo *mi)
176{
177}
178
179static void pte_cache_ctor(void *pte, kmem_cache_t *cache, unsigned long flags)
180{
181 memzero(pte, sizeof(pte_t) * PTRS_PER_PTE);
182}
183
184static void pgd_cache_ctor(void *pgd, kmem_cache_t *cache, unsigned long flags)
185{
186 memzero(pgd + MEMC_TABLE_SIZE, USER_PTRS_PER_PGD * sizeof(pgd_t));
187}
188
189void __init pgtable_cache_init(void)
190{
191 pte_cache = kmem_cache_create("pte-cache",
192 sizeof(pte_t) * PTRS_PER_PTE,
193 0, 0, pte_cache_ctor, NULL);
194 if (!pte_cache)
195 BUG();
196
197 pgd_cache = kmem_cache_create("pgd-cache", MEMC_TABLE_SIZE +
198 sizeof(pgd_t) * PTRS_PER_PGD,
199 0, 0, pgd_cache_ctor, NULL);
200 if (!pgd_cache)
201 BUG();
202}
diff --git a/arch/arm26/mm/proc-funcs.S b/arch/arm26/mm/proc-funcs.S
new file mode 100644
index 000000000000..c3d4cd3f457e
--- /dev/null
+++ b/arch/arm26/mm/proc-funcs.S
@@ -0,0 +1,359 @@
1/*
2 * linux/arch/arm26/mm/proc-arm2,3.S
3 *
4 * Copyright (C) 1997-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * MMU functions for ARM2,3
11 *
12 * These are the low level assembler for performing cache
13 * and memory functions on ARM2, ARM250 and ARM3 processors.
14 */
15#include <linux/linkage.h>
16#include <asm/assembler.h>
17#include <asm/asm_offsets.h>
18#include <asm/procinfo.h>
19#include <asm/ptrace.h>
20
21/*
22 * MEMC workhorse code. It's both a horse which things it's a pig.
23 */
24/*
25 * Function: cpu_memc_update_entry(pgd_t *pgd, unsigned long phys_pte, unsigned long addr)
26 * Params : pgd Page tables/MEMC mapping
27 * : phys_pte physical address, or PTE
28 * : addr virtual address
29 */
30ENTRY(cpu_memc_update_entry)
31 tst r1, #PAGE_PRESENT @ is the page present
32 orreq r1, r1, #PAGE_OLD | PAGE_CLEAN
33 moveq r2, #0x01f00000
34 mov r3, r1, lsr #13 @ convert to physical page nr
35 and r3, r3, #0x3fc
36 adr ip, memc_phys_table_32
37 ldr r3, [ip, r3]
38 tst r1, #PAGE_OLD | PAGE_NOT_USER
39 biceq r3, r3, #0x200
40 tsteq r1, #PAGE_READONLY | PAGE_CLEAN
41 biceq r3, r3, #0x300
42 mov r2, r2, lsr #15 @ virtual -> nr
43 orr r3, r3, r2, lsl #15
44 and r2, r2, #0x300
45 orr r3, r3, r2, lsl #2
46 and r2, r3, #255
47 sub r0, r0, #256 * 4
48 str r3, [r0, r2, lsl #2]
49 strb r3, [r3]
50 movs pc, lr
51/*
52 * Params : r0 = preserved
53 * : r1 = memc table base (preserved)
54 * : r2 = page table entry
55 * : r3 = preserved
56 * : r4 = unused
57 * : r5 = memc physical address translation table
58 * : ip = virtual address (preserved)
59 */
60update_pte:
61 mov r4, r2, lsr #13
62 and r4, r4, #0x3fc
63 ldr r4, [r5, r4] @ covert to MEMC page
64
65 tst r2, #PAGE_OLD | PAGE_NOT_USER @ check for MEMC read
66 biceq r4, r4, #0x200
67 tsteq r2, #PAGE_READONLY | PAGE_CLEAN @ check for MEMC write
68 biceq r4, r4, #0x300
69
70 orr r4, r4, ip
71 and r2, ip, #0x01800000
72 orr r4, r4, r2, lsr #13
73
74 and r2, r4, #255
75 str r4, [r1, r2, lsl #2]
76 movs pc, lr
77
78/*
79 * Params : r0 = preserved
80 * : r1 = memc table base (preserved)
81 * : r2 = page table base
82 * : r3 = preserved
83 * : r4 = unused
84 * : r5 = memc physical address translation table
85 * : ip = virtual address (updated)
86 */
87update_pte_table:
88 stmfd sp!, {r0, lr}
89 bic r0, r2, #3
901: ldr r2, [r0], #4 @ get entry
91 tst r2, #PAGE_PRESENT @ page present
92 blne update_pte @ process pte
93 add ip, ip, #32768 @ increment virt addr
94 ldr r2, [r0], #4 @ get entry
95 tst r2, #PAGE_PRESENT @ page present
96 blne update_pte @ process pte
97 add ip, ip, #32768 @ increment virt addr
98 ldr r2, [r0], #4 @ get entry
99 tst r2, #PAGE_PRESENT @ page present
100 blne update_pte @ process pte
101 add ip, ip, #32768 @ increment virt addr
102 ldr r2, [r0], #4 @ get entry
103 tst r2, #PAGE_PRESENT @ page present
104 blne update_pte @ process pte
105 add ip, ip, #32768 @ increment virt addr
106 tst ip, #32768 * 31 @ finished?
107 bne 1b
108 ldmfd sp!, {r0, pc}^
109
110/*
111 * Function: cpu_memc_update_all(pgd_t *pgd)
112 * Params : pgd Page tables/MEMC mapping
113 * Notes : this is optimised for 32k pages
114 */
115ENTRY(cpu_memc_update_all)
116 stmfd sp!, {r4, r5, lr}
117 bl clear_tables
118 sub r1, r0, #256 * 4 @ start of MEMC tables
119 adr r5, memc_phys_table_32 @ Convert to logical page number
120 mov ip, #0 @ virtual address
1211: ldmia r0!, {r2, r3} @ load two pgd entries
122 tst r2, #PAGE_PRESENT @ is pgd entry present?
123 addeq ip, ip, #1048576 @FIXME - PAGE_PRESENT is for PTEs technically...
124 blne update_pte_table
125 mov r2, r3
126 tst r2, #PAGE_PRESENT @ is pgd entry present?
127 addeq ip, ip, #1048576
128 blne update_pte_table
129 teq ip, #32 * 1048576
130 bne 1b
131 ldmfd sp!, {r4, r5, pc}^
132
133/*
134 * Build the table to map from physical page number to memc page number
135 */
136 .type memc_phys_table_32, #object
137memc_phys_table_32:
138 .irp b7, 0x00, 0x80
139 .irp b6, 0x00, 0x02
140 .irp b5, 0x00, 0x04
141 .irp b4, 0x00, 0x01
142
143 .irp b3, 0x00, 0x40
144 .irp b2, 0x00, 0x20
145 .irp b1, 0x00, 0x10
146 .irp b0, 0x00, 0x08
147 .long 0x03800300 + \b7 + \b6 + \b5 + \b4 + \b3 + \b2 + \b1 + \b0
148 .endr
149 .endr
150 .endr
151 .endr
152
153 .endr
154 .endr
155 .endr
156 .endr
157 .size memc_phys_table_32, . - memc_phys_table_32
158
159/*
160 * helper for cpu_memc_update_all, this clears out all
161 * mappings, setting them close to the top of memory,
162 * and inaccessible (0x01f00000).
163 * Params : r0 = page table pointer
164 */
165clear_tables: ldr r1, _arm3_set_pgd - 4
166 ldr r2, [r1]
167 sub r1, r0, #256 * 4 @ start of MEMC tables
168 add r2, r1, r2, lsl #2 @ end of tables
169 mov r3, #0x03f00000 @ Default mapping (null mapping)
170 orr r3, r3, #0x00000f00
171 orr r4, r3, #1
172 orr r5, r3, #2
173 orr ip, r3, #3
1741: stmia r1!, {r3, r4, r5, ip}
175 add r3, r3, #4
176 add r4, r4, #4
177 add r5, r5, #4
178 add ip, ip, #4
179 stmia r1!, {r3, r4, r5, ip}
180 add r3, r3, #4
181 add r4, r4, #4
182 add r5, r5, #4
183 add ip, ip, #4
184 teq r1, r2
185 bne 1b
186 mov pc, lr
187
188/*
189 * Function: *_set_pgd(pgd_t *pgd)
190 * Params : pgd New page tables/MEMC mapping
191 * Purpose : update MEMC hardware with new mapping
192 */
193 .word page_nr @ extern - declared in mm-memc.c
194_arm3_set_pgd: mcr p15, 0, r1, c1, c0, 0 @ flush cache
195_arm2_set_pgd: stmfd sp!, {lr}
196 ldr r1, _arm3_set_pgd - 4
197 ldr r2, [r1]
198 sub r0, r0, #256 * 4 @ start of MEMC tables
199 add r1, r0, r2, lsl #2 @ end of tables
2001: ldmia r0!, {r2, r3, ip, lr}
201 strb r2, [r2]
202 strb r3, [r3]
203 strb ip, [ip]
204 strb lr, [lr]
205 ldmia r0!, {r2, r3, ip, lr}
206 strb r2, [r2]
207 strb r3, [r3]
208 strb ip, [ip]
209 strb lr, [lr]
210 teq r0, r1
211 bne 1b
212 ldmfd sp!, {pc}^
213
214/*
215 * Function: *_proc_init (void)
216 * Purpose : Initialise the cache control registers
217 */
218_arm3_proc_init:
219 mov r0, #0x001f0000
220 orr r0, r0, #0x0000ff00
221 orr r0, r0, #0x000000ff
222 mcr p15, 0, r0, c3, c0 @ ARM3 Cacheable
223 mcr p15, 0, r0, c4, c0 @ ARM3 Updateable
224 mov r0, #0
225 mcr p15, 0, r0, c5, c0 @ ARM3 Disruptive
226 mcr p15, 0, r0, c1, c0 @ ARM3 Flush
227 mov r0, #3
228 mcr p15, 0, r0, c2, c0 @ ARM3 Control
229_arm2_proc_init:
230 movs pc, lr
231
232/*
233 * Function: *_proc_fin (void)
234 * Purpose : Finalise processor (disable caches)
235 */
236_arm3_proc_fin: mov r0, #2
237 mcr p15, 0, r0, c2, c0
238_arm2_proc_fin: orrs pc, lr, #PSR_I_BIT|PSR_F_BIT
239
240/*
241 * Function: *_xchg_1 (int new, volatile void *ptr)
242 * Params : new New value to store at...
243 * : ptr pointer to byte-wide location
244 * Purpose : Performs an exchange operation
245 * Returns : Original byte data at 'ptr'
246 */
247_arm2_xchg_1: mov r2, pc
248 orr r2, r2, #PSR_I_BIT
249 teqp r2, #0
250 ldrb r2, [r1]
251 strb r0, [r1]
252 mov r0, r2
253 movs pc, lr
254
255_arm3_xchg_1: swpb r0, r0, [r1]
256 movs pc, lr
257
258/*
259 * Function: *_xchg_4 (int new, volatile void *ptr)
260 * Params : new New value to store at...
261 * : ptr pointer to word-wide location
262 * Purpose : Performs an exchange operation
263 * Returns : Original word data at 'ptr'
264 */
265_arm2_xchg_4: mov r2, pc
266 orr r2, r2, #PSR_I_BIT
267 teqp r2, #0
268 ldr r2, [r1]
269 str r0, [r1]
270 mov r0, r2
271 movs pc, lr
272
273_arm3_xchg_4: swp r0, r0, [r1]
274 movs pc, lr
275
276_arm2_3_check_bugs:
277 bics pc, lr, #PSR_F_BIT @ Clear FIQ disable bit
278
279armvlsi_name: .asciz "ARM/VLSI"
280_arm2_name: .asciz "ARM 2"
281_arm250_name: .asciz "ARM 250"
282_arm3_name: .asciz "ARM 3"
283
284 .section ".init.text", #alloc, #execinstr
285/*
286 * Purpose : Function pointers used to access above functions - all calls
287 * come through these
288 */
289 .globl arm2_processor_functions
290arm2_processor_functions:
291 .word _arm2_3_check_bugs
292 .word _arm2_proc_init
293 .word _arm2_proc_fin
294 .word _arm2_set_pgd
295 .word _arm2_xchg_1
296 .word _arm2_xchg_4
297
298cpu_arm2_info:
299 .long armvlsi_name
300 .long _arm2_name
301
302 .globl arm250_processor_functions
303arm250_processor_functions:
304 .word _arm2_3_check_bugs
305 .word _arm2_proc_init
306 .word _arm2_proc_fin
307 .word _arm2_set_pgd
308 .word _arm3_xchg_1
309 .word _arm3_xchg_4
310
311cpu_arm250_info:
312 .long armvlsi_name
313 .long _arm250_name
314
315 .globl arm3_processor_functions
316arm3_processor_functions:
317 .word _arm2_3_check_bugs
318 .word _arm3_proc_init
319 .word _arm3_proc_fin
320 .word _arm3_set_pgd
321 .word _arm3_xchg_1
322 .word _arm3_xchg_4
323
324cpu_arm3_info:
325 .long armvlsi_name
326 .long _arm3_name
327
328arm2_arch_name: .asciz "armv1"
329arm3_arch_name: .asciz "armv2"
330arm2_elf_name: .asciz "v1"
331arm3_elf_name: .asciz "v2"
332 .align
333
334 .section ".proc.info", #alloc, #execinstr
335
336 .long 0x41560200
337 .long 0xfffffff0
338 .long arm2_arch_name
339 .long arm2_elf_name
340 .long 0
341 .long cpu_arm2_info
342 .long arm2_processor_functions
343
344 .long 0x41560250
345 .long 0xfffffff0
346 .long arm3_arch_name
347 .long arm3_elf_name
348 .long 0
349 .long cpu_arm250_info
350 .long arm250_processor_functions
351
352 .long 0x41560300
353 .long 0xfffffff0
354 .long arm3_arch_name
355 .long arm3_elf_name
356 .long 0
357 .long cpu_arm3_info
358 .long arm3_processor_functions
359
diff --git a/arch/arm26/mm/small_page.c b/arch/arm26/mm/small_page.c
new file mode 100644
index 000000000000..77be86cca789
--- /dev/null
+++ b/arch/arm26/mm/small_page.c
@@ -0,0 +1,194 @@
1/*
2 * linux/arch/arm26/mm/small_page.c
3 *
4 * Copyright (C) 1996 Russell King
5 * Copyright (C) 2003 Ian Molton
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Changelog:
12 * 26/01/1996 RMK Cleaned up various areas to make little more generic
13 * 07/02/1999 RMK Support added for 16K and 32K page sizes
14 * containing 8K blocks
15 * 23/05/2004 IM Fixed to use struct page->lru (thanks wli)
16 *
17 */
18#include <linux/signal.h>
19#include <linux/sched.h>
20#include <linux/kernel.h>
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/types.h>
24#include <linux/ptrace.h>
25#include <linux/mman.h>
26#include <linux/mm.h>
27#include <linux/swap.h>
28#include <linux/smp.h>
29#include <linux/bitops.h>
30
31#include <asm/pgtable.h>
32
33#define PEDANTIC
34
35/*
36 * Requirement:
37 * We need to be able to allocate naturally aligned memory of finer
38 * granularity than the page size. This is typically used for the
39 * second level page tables on 32-bit ARMs.
40 *
41 * FIXME - this comment is *out of date*
42 * Theory:
43 * We "misuse" the Linux memory management system. We use alloc_page
44 * to allocate a page and then mark it as reserved. The Linux memory
45 * management system will then ignore the "offset", "next_hash" and
46 * "pprev_hash" entries in the mem_map for this page.
47 *
48 * We then use a bitstring in the "offset" field to mark which segments
49 * of the page are in use, and manipulate this as required during the
50 * allocation and freeing of these small pages.
51 *
52 * We also maintain a queue of pages being used for this purpose using
53 * the "next_hash" and "pprev_hash" entries of mem_map;
54 */
55
56struct order {
57 struct list_head queue;
58 unsigned int mask; /* (1 << shift) - 1 */
59 unsigned int shift; /* (1 << shift) size of page */
60 unsigned int block_mask; /* nr_blocks - 1 */
61 unsigned int all_used; /* (1 << nr_blocks) - 1 */
62};
63
64
65static struct order orders[] = {
66#if PAGE_SIZE == 32768
67 { LIST_HEAD_INIT(orders[0].queue), 2047, 11, 15, 0x0000ffff },
68 { LIST_HEAD_INIT(orders[1].queue), 8191, 13, 3, 0x0000000f }
69#else
70#error unsupported page size (ARGH!)
71#endif
72};
73
74#define USED_MAP(pg) ((pg)->index)
75#define TEST_AND_CLEAR_USED(pg,off) (test_and_clear_bit(off, &USED_MAP(pg)))
76#define SET_USED(pg,off) (set_bit(off, &USED_MAP(pg)))
77
78static DEFINE_SPINLOCK(small_page_lock);
79
80static unsigned long __get_small_page(int priority, struct order *order)
81{
82 unsigned long flags;
83 struct page *page;
84 int offset;
85
86 do {
87 spin_lock_irqsave(&small_page_lock, flags);
88
89 if (list_empty(&order->queue))
90 goto need_new_page;
91
92 page = list_entry(order->queue.next, struct page, lru);
93again:
94#ifdef PEDANTIC
95 if (USED_MAP(page) & ~order->all_used)
96 PAGE_BUG(page);
97#endif
98 offset = ffz(USED_MAP(page));
99 SET_USED(page, offset);
100 if (USED_MAP(page) == order->all_used)
101 list_del_init(&page->lru);
102 spin_unlock_irqrestore(&small_page_lock, flags);
103
104 return (unsigned long) page_address(page) + (offset << order->shift);
105
106need_new_page:
107 spin_unlock_irqrestore(&small_page_lock, flags);
108 page = alloc_page(priority);
109 spin_lock_irqsave(&small_page_lock, flags);
110
111 if (list_empty(&order->queue)) {
112 if (!page)
113 goto no_page;
114 SetPageReserved(page);
115 USED_MAP(page) = 0;
116 list_add(&page->lru, &order->queue);
117 goto again;
118 }
119
120 spin_unlock_irqrestore(&small_page_lock, flags);
121 __free_page(page);
122 } while (1);
123
124no_page:
125 spin_unlock_irqrestore(&small_page_lock, flags);
126 return 0;
127}
128
129static void __free_small_page(unsigned long spage, struct order *order)
130{
131 unsigned long flags;
132 struct page *page;
133
134 if (virt_addr_valid(spage)) {
135 page = virt_to_page(spage);
136
137 /*
138 * The container-page must be marked Reserved
139 */
140 if (!PageReserved(page) || spage & order->mask)
141 goto non_small;
142
143#ifdef PEDANTIC
144 if (USED_MAP(page) & ~order->all_used)
145 PAGE_BUG(page);
146#endif
147
148 spage = spage >> order->shift;
149 spage &= order->block_mask;
150
151 /*
152 * the following must be atomic wrt get_page
153 */
154 spin_lock_irqsave(&small_page_lock, flags);
155
156 if (USED_MAP(page) == order->all_used)
157 list_add(&page->lru, &order->queue);
158
159 if (!TEST_AND_CLEAR_USED(page, spage))
160 goto already_free;
161
162 if (USED_MAP(page) == 0)
163 goto free_page;
164
165 spin_unlock_irqrestore(&small_page_lock, flags);
166 }
167 return;
168
169free_page:
170 /*
171 * unlink the page from the small page queue and free it
172 */
173 list_del_init(&page->lru);
174 spin_unlock_irqrestore(&small_page_lock, flags);
175 ClearPageReserved(page);
176 __free_page(page);
177 return;
178
179non_small:
180 printk("Trying to free non-small page from %p\n", __builtin_return_address(0));
181 return;
182already_free:
183 printk("Trying to free free small page from %p\n", __builtin_return_address(0));
184}
185
186unsigned long get_page_8k(int priority)
187{
188 return __get_small_page(priority, orders+1);
189}
190
191void free_page_8k(unsigned long spage)
192{
193 __free_small_page(spage, orders+1);
194}
diff --git a/arch/arm26/nwfpe/ARM-gcc.h b/arch/arm26/nwfpe/ARM-gcc.h
new file mode 100644
index 000000000000..e6598470b076
--- /dev/null
+++ b/arch/arm26/nwfpe/ARM-gcc.h
@@ -0,0 +1,120 @@
1/*
2-------------------------------------------------------------------------------
3The macro `BITS64' can be defined to indicate that 64-bit integer types are
4supported by the compiler.
5-------------------------------------------------------------------------------
6*/
7#define BITS64
8
9/*
10-------------------------------------------------------------------------------
11Each of the following `typedef's defines the most convenient type that holds
12integers of at least as many bits as specified. For example, `uint8' should
13be the most convenient type that can hold unsigned integers of as many as
148 bits. The `flag' type must be able to hold either a 0 or 1. For most
15implementations of C, `flag', `uint8', and `int8' should all be `typedef'ed
16to the same as `int'.
17-------------------------------------------------------------------------------
18*/
19typedef char flag;
20typedef unsigned char uint8;
21typedef signed char int8;
22typedef int uint16;
23typedef int int16;
24typedef unsigned int uint32;
25typedef signed int int32;
26#ifdef BITS64
27typedef unsigned long long int bits64;
28typedef signed long long int sbits64;
29#endif
30
31/*
32-------------------------------------------------------------------------------
33Each of the following `typedef's defines a type that holds integers
34of _exactly_ the number of bits specified. For instance, for most
35implementation of C, `bits16' and `sbits16' should be `typedef'ed to
36`unsigned short int' and `signed short int' (or `short int'), respectively.
37-------------------------------------------------------------------------------
38*/
39typedef unsigned char bits8;
40typedef signed char sbits8;
41typedef unsigned short int bits16;
42typedef signed short int sbits16;
43typedef unsigned int bits32;
44typedef signed int sbits32;
45#ifdef BITS64
46typedef unsigned long long int uint64;
47typedef signed long long int int64;
48#endif
49
50#ifdef BITS64
51/*
52-------------------------------------------------------------------------------
53The `LIT64' macro takes as its argument a textual integer literal and if
54necessary ``marks'' the literal as having a 64-bit integer type. For
55example, the Gnu C Compiler (`gcc') requires that 64-bit literals be
56appended with the letters `LL' standing for `long long', which is `gcc's
57name for the 64-bit integer type. Some compilers may allow `LIT64' to be
58defined as the identity macro: `#define LIT64( a ) a'.
59-------------------------------------------------------------------------------
60*/
61#define LIT64( a ) a##LL
62#endif
63
64/*
65-------------------------------------------------------------------------------
66The macro `INLINE' can be used before functions that should be inlined. If
67a compiler does not support explicit inlining, this macro should be defined
68to be `static'.
69-------------------------------------------------------------------------------
70*/
71#define INLINE extern __inline__
72
73
74/* For use as a GCC soft-float library we need some special function names. */
75
76#ifdef __LIBFLOAT__
77
78/* Some 32-bit ops can be mapped straight across by just changing the name. */
79#define float32_add __addsf3
80#define float32_sub __subsf3
81#define float32_mul __mulsf3
82#define float32_div __divsf3
83#define int32_to_float32 __floatsisf
84#define float32_to_int32_round_to_zero __fixsfsi
85#define float32_to_uint32_round_to_zero __fixunssfsi
86
87/* These ones go through the glue code. To avoid namespace pollution
88 we rename the internal functions too. */
89#define float32_eq ___float32_eq
90#define float32_le ___float32_le
91#define float32_lt ___float32_lt
92
93/* All the 64-bit ops have to go through the glue, so we pull the same
94 trick. */
95#define float64_add ___float64_add
96#define float64_sub ___float64_sub
97#define float64_mul ___float64_mul
98#define float64_div ___float64_div
99#define int32_to_float64 ___int32_to_float64
100#define float64_to_int32_round_to_zero ___float64_to_int32_round_to_zero
101#define float64_to_uint32_round_to_zero ___float64_to_uint32_round_to_zero
102#define float64_to_float32 ___float64_to_float32
103#define float32_to_float64 ___float32_to_float64
104#define float64_eq ___float64_eq
105#define float64_le ___float64_le
106#define float64_lt ___float64_lt
107
108#if 0
109#define float64_add __adddf3
110#define float64_sub __subdf3
111#define float64_mul __muldf3
112#define float64_div __divdf3
113#define int32_to_float64 __floatsidf
114#define float64_to_int32_round_to_zero __fixdfsi
115#define float64_to_uint32_round_to_zero __fixunsdfsi
116#define float64_to_float32 __truncdfsf2
117#define float32_to_float64 __extendsfdf2
118#endif
119
120#endif
diff --git a/arch/arm26/nwfpe/ChangeLog b/arch/arm26/nwfpe/ChangeLog
new file mode 100644
index 000000000000..0c580f764baf
--- /dev/null
+++ b/arch/arm26/nwfpe/ChangeLog
@@ -0,0 +1,83 @@
12002-01-19 Russell King <rmk@arm.linux.org.uk>
2
3 * fpa11.h - Add documentation
4 - remove userRegisters pointer from this structure.
5 - add new method to obtain integer register values.
6 * softfloat.c - Remove float128
7 * softfloat.h - Remove float128
8 * softfloat-specialize - Remove float128
9
10 * The FPA11 structure is not a kernel-specific data structure.
11 It is used by users of ptrace to examine the values of the
12 floating point registers. Therefore, any changes to the
13 FPA11 structure (size or position of elements contained
14 within) have to be well thought out.
15
16 * Since 128-bit float requires the FPA11 structure to change
17 size, it has been removed. 128-bit float is currently unused,
18 and needs various things to be re-worked so that we won't
19 overflow the available space in the task structure.
20
21 * The changes are designed to break any patch that goes on top
22 of this code, so that the authors properly review their changes.
23
241999-08-19 Scott Bambrough <scottb@netwinder.org>
25
26 * fpmodule.c - Changed version number to 0.95
27 * fpa11.h - modified FPA11, FPREG structures
28 * fpa11.c - Changes due to FPA11, FPREG structure alterations.
29 * fpa11_cpdo.c - Changes due to FPA11, FPREG structure alterations.
30 * fpa11_cpdt.c - Changes due to FPA11, FPREG structure alterations.
31 * fpa11_cprt.c - Changes due to FPA11, FPREG structure alterations.
32 * single_cpdo.c - Changes due to FPA11, FPREG structure alterations.
33 * double_cpdo.c - Changes due to FPA11, FPREG structure alterations.
34 * extended_cpdo.c - Changes due to FPA11, FPREG structure alterations.
35
36 * I discovered several bugs. First and worst is that the kernel
37 passes in a pointer to the FPE's state area. This is defined
38 as a struct user_fp (see user.h). This pointer was cast to a
39 FPA11*. Unfortunately FPA11 and user_fp are of different sizes;
40 user_fp is smaller. This meant that the FPE scribbled on things
41 below its area, which is bad, as the area is in the thread_struct
42 embedded in the process task structure. Thus we were scribbling
43 over one of the most important structures in the entire OS.
44
45 * user_fp and FPA11 have now been harmonized. Most of the changes
46 in the above code were dereferencing problems due to moving the
47 register type out of FPREG, and getting rid of the union variable
48 fpvalue.
49
50 * Second I noticed resetFPA11 was not always being called for a
51 task. This should happen on the first floating point exception
52 that occurs. It is controlled by init_flag in FPA11. The
53 comment in the code beside init_flag state the kernel guarantees
54 this to be zero. Not so. I found that the kernel recycles task
55 structures, and that recycled ones may not have init_flag zeroed.
56 I couldn't even find anything that guarantees it is zeroed when
57 when the task structure is initially allocated. In any case
58 I now initialize the entire FPE state in the thread structure to
59 zero when allocated and recycled. See alloc_task_struct() and
60 flush_thread() in arch/arm/process.c. The change to
61 alloc_task_struct() may not be necessary, but I left it in for
62 completeness (better safe than sorry).
63
641998-11-23 Scott Bambrough <scottb@netwinder.org>
65
66 * README.FPE - fix typo in description of lfm/sfm instructions
67 * NOTES - Added file to describe known bugs/problems
68 * fpmodule.c - Changed version number to 0.94
69
701998-11-20 Scott Bambrough <scottb@netwinder.org>
71
72 * README.FPE - fix description of URD, NRM instructions
73 * TODO - remove URD, NRM instructions from TODO list
74 * single_cpdo.c - implement URD, NRM
75 * double_cpdo.c - implement URD, NRM
76 * extended_cpdo.c - implement URD, NRM
77
781998-11-19 Scott Bambrough <scottb@netwinder.org>
79
80 * ChangeLog - Added this file to track changes made.
81 * fpa11.c - added code to initialize register types to typeNone
82 * fpa11_cpdt.c - fixed bug in storeExtended (typeExtended changed to
83 typeDouble in switch statement)
diff --git a/arch/arm26/nwfpe/Makefile b/arch/arm26/nwfpe/Makefile
new file mode 100644
index 000000000000..b39d34dff054
--- /dev/null
+++ b/arch/arm26/nwfpe/Makefile
@@ -0,0 +1,15 @@
1#
2# Copyright (C) 1998, 1999, 2001 Philip Blundell
3#
4
5obj-y :=
6obj-m :=
7obj-n :=
8
9obj-$(CONFIG_FPE_NWFPE) += nwfpe.o
10
11nwfpe-objs := fpa11.o fpa11_cpdo.o fpa11_cpdt.o fpa11_cprt.o \
12 fpmodule.o fpopcode.o softfloat.o \
13 single_cpdo.o double_cpdo.o extended_cpdo.o \
14 entry.o
15
diff --git a/arch/arm26/nwfpe/double_cpdo.c b/arch/arm26/nwfpe/double_cpdo.c
new file mode 100644
index 000000000000..7f4fef0216c7
--- /dev/null
+++ b/arch/arm26/nwfpe/double_cpdo.c
@@ -0,0 +1,288 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "fpa11.h"
23#include "softfloat.h"
24#include "fpopcode.h"
25
26float64 float64_exp(float64 Fm);
27float64 float64_ln(float64 Fm);
28float64 float64_sin(float64 rFm);
29float64 float64_cos(float64 rFm);
30float64 float64_arcsin(float64 rFm);
31float64 float64_arctan(float64 rFm);
32float64 float64_log(float64 rFm);
33float64 float64_tan(float64 rFm);
34float64 float64_arccos(float64 rFm);
35float64 float64_pow(float64 rFn,float64 rFm);
36float64 float64_pol(float64 rFn,float64 rFm);
37
38unsigned int DoubleCPDO(const unsigned int opcode)
39{
40 FPA11 *fpa11 = GET_FPA11();
41 float64 rFm, rFn = 0; //FIXME - should be zero?
42 unsigned int Fd, Fm, Fn, nRc = 1;
43
44 //printk("DoubleCPDO(0x%08x)\n",opcode);
45
46 Fm = getFm(opcode);
47 if (CONSTANT_FM(opcode))
48 {
49 rFm = getDoubleConstant(Fm);
50 }
51 else
52 {
53 switch (fpa11->fType[Fm])
54 {
55 case typeSingle:
56 rFm = float32_to_float64(fpa11->fpreg[Fm].fSingle);
57 break;
58
59 case typeDouble:
60 rFm = fpa11->fpreg[Fm].fDouble;
61 break;
62
63 case typeExtended:
64 // !! patb
65 //printk("not implemented! why not?\n");
66 //!! ScottB
67 // should never get here, if extended involved
68 // then other operand should be promoted then
69 // ExtendedCPDO called.
70 break;
71
72 default: return 0;
73 }
74 }
75
76 if (!MONADIC_INSTRUCTION(opcode))
77 {
78 Fn = getFn(opcode);
79 switch (fpa11->fType[Fn])
80 {
81 case typeSingle:
82 rFn = float32_to_float64(fpa11->fpreg[Fn].fSingle);
83 break;
84
85 case typeDouble:
86 rFn = fpa11->fpreg[Fn].fDouble;
87 break;
88
89 default: return 0;
90 }
91 }
92
93 Fd = getFd(opcode);
94 /* !! this switch isn't optimized; better (opcode & MASK_ARITHMETIC_OPCODE)>>24, sort of */
95 switch (opcode & MASK_ARITHMETIC_OPCODE)
96 {
97 /* dyadic opcodes */
98 case ADF_CODE:
99 fpa11->fpreg[Fd].fDouble = float64_add(rFn,rFm);
100 break;
101
102 case MUF_CODE:
103 case FML_CODE:
104 fpa11->fpreg[Fd].fDouble = float64_mul(rFn,rFm);
105 break;
106
107 case SUF_CODE:
108 fpa11->fpreg[Fd].fDouble = float64_sub(rFn,rFm);
109 break;
110
111 case RSF_CODE:
112 fpa11->fpreg[Fd].fDouble = float64_sub(rFm,rFn);
113 break;
114
115 case DVF_CODE:
116 case FDV_CODE:
117 fpa11->fpreg[Fd].fDouble = float64_div(rFn,rFm);
118 break;
119
120 case RDF_CODE:
121 case FRD_CODE:
122 fpa11->fpreg[Fd].fDouble = float64_div(rFm,rFn);
123 break;
124
125#if 0
126 case POW_CODE:
127 fpa11->fpreg[Fd].fDouble = float64_pow(rFn,rFm);
128 break;
129
130 case RPW_CODE:
131 fpa11->fpreg[Fd].fDouble = float64_pow(rFm,rFn);
132 break;
133#endif
134
135 case RMF_CODE:
136 fpa11->fpreg[Fd].fDouble = float64_rem(rFn,rFm);
137 break;
138
139#if 0
140 case POL_CODE:
141 fpa11->fpreg[Fd].fDouble = float64_pol(rFn,rFm);
142 break;
143#endif
144
145 /* monadic opcodes */
146 case MVF_CODE:
147 fpa11->fpreg[Fd].fDouble = rFm;
148 break;
149
150 case MNF_CODE:
151 {
152 unsigned int *p = (unsigned int*)&rFm;
153 p[1] ^= 0x80000000;
154 fpa11->fpreg[Fd].fDouble = rFm;
155 }
156 break;
157
158 case ABS_CODE:
159 {
160 unsigned int *p = (unsigned int*)&rFm;
161 p[1] &= 0x7fffffff;
162 fpa11->fpreg[Fd].fDouble = rFm;
163 }
164 break;
165
166 case RND_CODE:
167 case URD_CODE:
168 fpa11->fpreg[Fd].fDouble = float64_round_to_int(rFm);
169 break;
170
171 case SQT_CODE:
172 fpa11->fpreg[Fd].fDouble = float64_sqrt(rFm);
173 break;
174
175#if 0
176 case LOG_CODE:
177 fpa11->fpreg[Fd].fDouble = float64_log(rFm);
178 break;
179
180 case LGN_CODE:
181 fpa11->fpreg[Fd].fDouble = float64_ln(rFm);
182 break;
183
184 case EXP_CODE:
185 fpa11->fpreg[Fd].fDouble = float64_exp(rFm);
186 break;
187
188 case SIN_CODE:
189 fpa11->fpreg[Fd].fDouble = float64_sin(rFm);
190 break;
191
192 case COS_CODE:
193 fpa11->fpreg[Fd].fDouble = float64_cos(rFm);
194 break;
195
196 case TAN_CODE:
197 fpa11->fpreg[Fd].fDouble = float64_tan(rFm);
198 break;
199
200 case ASN_CODE:
201 fpa11->fpreg[Fd].fDouble = float64_arcsin(rFm);
202 break;
203
204 case ACS_CODE:
205 fpa11->fpreg[Fd].fDouble = float64_arccos(rFm);
206 break;
207
208 case ATN_CODE:
209 fpa11->fpreg[Fd].fDouble = float64_arctan(rFm);
210 break;
211#endif
212
213 case NRM_CODE:
214 break;
215
216 default:
217 {
218 nRc = 0;
219 }
220 }
221
222 if (0 != nRc) fpa11->fType[Fd] = typeDouble;
223 return nRc;
224}
225
226#if 0
227float64 float64_exp(float64 rFm)
228{
229 return rFm;
230//series
231}
232
233float64 float64_ln(float64 rFm)
234{
235 return rFm;
236//series
237}
238
239float64 float64_sin(float64 rFm)
240{
241 return rFm;
242//series
243}
244
245float64 float64_cos(float64 rFm)
246{
247 return rFm;
248 //series
249}
250
251#if 0
252float64 float64_arcsin(float64 rFm)
253{
254//series
255}
256
257float64 float64_arctan(float64 rFm)
258{
259 //series
260}
261#endif
262
263float64 float64_log(float64 rFm)
264{
265 return float64_div(float64_ln(rFm),getDoubleConstant(7));
266}
267
268float64 float64_tan(float64 rFm)
269{
270 return float64_div(float64_sin(rFm),float64_cos(rFm));
271}
272
273float64 float64_arccos(float64 rFm)
274{
275return rFm;
276 //return float64_sub(halfPi,float64_arcsin(rFm));
277}
278
279float64 float64_pow(float64 rFn,float64 rFm)
280{
281 return float64_exp(float64_mul(rFm,float64_ln(rFn)));
282}
283
284float64 float64_pol(float64 rFn,float64 rFm)
285{
286 return float64_arctan(float64_div(rFn,rFm));
287}
288#endif
diff --git a/arch/arm26/nwfpe/entry.S b/arch/arm26/nwfpe/entry.S
new file mode 100644
index 000000000000..7d6dfaad80c2
--- /dev/null
+++ b/arch/arm26/nwfpe/entry.S
@@ -0,0 +1,114 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998
4 (c) Philip Blundell 1998-1999
5
6 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21*/
22
23#include <asm/asm_offsets.h>
24
25/* This is the kernel's entry point into the floating point emulator.
26It is called from the kernel with code similar to this:
27
28 mov fp, #0
29 teqp pc, #PSR_I_BIT | MODE_SVC
30 ldr r4, .LC2
31 ldr pc, [r4] @ Call FP module USR entry point
32
33The kernel expects the emulator to return via one of two possible
34points of return it passes to the emulator. The emulator, if
35successful in its emulation, jumps to ret_from_exception and the
36kernel takes care of returning control from the trap to the user code.
37If the emulator is unable to emulate the instruction, it returns to
38fpundefinstr and the kernel halts the user program with a core dump.
39
40This routine does four things:
41
421) It saves SP into a variable called userRegisters. The kernel has
43created a struct pt_regs on the stack and saved the user registers
44into it. See /usr/include/asm/proc/ptrace.h for details. The
45emulator code uses userRegisters as the base of an array of words from
46which the contents of the registers can be extracted.
47
482) It locates the FP emulator work area within the TSS structure and
49points `fpa11' to it.
50
513) It calls EmulateAll to emulate a floating point instruction.
52EmulateAll returns 1 if the emulation was successful, or 0 if not.
53
544) If an instruction has been emulated successfully, it looks ahead at
55the next instruction. If it is a floating point instruction, it
56executes the instruction, without returning to user space. In this
57way it repeatedly looks ahead and executes floating point instructions
58until it encounters a non floating point instruction, at which time it
59returns via _fpreturn.
60
61This is done to reduce the effect of the trap overhead on each
62floating point instructions. GCC attempts to group floating point
63instructions to allow the emulator to spread the cost of the trap over
64several floating point instructions. */
65
66 .globl nwfpe_enter
67nwfpe_enter:
68 mov sl, sp
69 bl FPA11_CheckInit @ check to see if we are initialised
70
71 ldr r5, [sp, #60] @ get contents of PC
72 bic r5, r5, #0xfc000003
73 ldr r0, [r5, #-4] @ get actual instruction into r0
74 bl EmulateAll @ emulate the instruction
751: cmp r0, #0 @ was emulation successful
76 beq fpundefinstr @ no, return failure
77
78next:
79.Lx1: ldrt r6, [r5], #4 @ get the next instruction and
80 @ increment PC
81
82 and r2, r6, #0x0F000000 @ test for FP insns
83 teq r2, #0x0C000000
84 teqne r2, #0x0D000000
85 teqne r2, #0x0E000000
86 bne ret_from_exception @ return ok if not a fp insn
87
88 ldr r9, [sp, #60] @ get new condition codes
89 and r9, r9, #0xfc000003
90 orr r7, r5, r9
91 str r7, [sp, #60] @ update PC copy in regs
92
93 mov r0, r6 @ save a copy
94 mov r1, r9 @ fetch the condition codes
95 bl checkCondition @ check the condition
96 cmp r0, #0 @ r0 = 0 ==> condition failed
97
98 @ if condition code failed to match, next insn
99 beq next @ get the next instruction;
100
101 mov r0, r6 @ prepare for EmulateAll()
102 adr lr, 1b
103 orr lr, lr, #3
104 b EmulateAll @ if r0 != 0, goto EmulateAll
105
106.Lret: b ret_from_exception @ let the user eat segfaults
107
108 @ We need to be prepared for the instruction at .Lx1 to fault.
109 @ Emit the appropriate exception gunk to fix things up.
110 .section __ex_table,"a"
111 .align 3
112 .long .Lx1
113 ldr lr, [lr, $(.Lret - .Lx1)/4]
114 .previous
diff --git a/arch/arm26/nwfpe/extended_cpdo.c b/arch/arm26/nwfpe/extended_cpdo.c
new file mode 100644
index 000000000000..331407596d91
--- /dev/null
+++ b/arch/arm26/nwfpe/extended_cpdo.c
@@ -0,0 +1,273 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "fpa11.h"
23#include "softfloat.h"
24#include "fpopcode.h"
25
26floatx80 floatx80_exp(floatx80 Fm);
27floatx80 floatx80_ln(floatx80 Fm);
28floatx80 floatx80_sin(floatx80 rFm);
29floatx80 floatx80_cos(floatx80 rFm);
30floatx80 floatx80_arcsin(floatx80 rFm);
31floatx80 floatx80_arctan(floatx80 rFm);
32floatx80 floatx80_log(floatx80 rFm);
33floatx80 floatx80_tan(floatx80 rFm);
34floatx80 floatx80_arccos(floatx80 rFm);
35floatx80 floatx80_pow(floatx80 rFn,floatx80 rFm);
36floatx80 floatx80_pol(floatx80 rFn,floatx80 rFm);
37
38unsigned int ExtendedCPDO(const unsigned int opcode)
39{
40 FPA11 *fpa11 = GET_FPA11();
41 floatx80 rFm, rFn;
42 unsigned int Fd, Fm, Fn, nRc = 1;
43
44 //printk("ExtendedCPDO(0x%08x)\n",opcode);
45
46 Fm = getFm(opcode);
47 if (CONSTANT_FM(opcode))
48 {
49 rFm = getExtendedConstant(Fm);
50 }
51 else
52 {
53 switch (fpa11->fType[Fm])
54 {
55 case typeSingle:
56 rFm = float32_to_floatx80(fpa11->fpreg[Fm].fSingle);
57 break;
58
59 case typeDouble:
60 rFm = float64_to_floatx80(fpa11->fpreg[Fm].fDouble);
61 break;
62
63 case typeExtended:
64 rFm = fpa11->fpreg[Fm].fExtended;
65 break;
66
67 default: return 0;
68 }
69 }
70
71 if (!MONADIC_INSTRUCTION(opcode))
72 {
73 Fn = getFn(opcode);
74 switch (fpa11->fType[Fn])
75 {
76 case typeSingle:
77 rFn = float32_to_floatx80(fpa11->fpreg[Fn].fSingle);
78 break;
79
80 case typeDouble:
81 rFn = float64_to_floatx80(fpa11->fpreg[Fn].fDouble);
82 break;
83
84 case typeExtended:
85 rFn = fpa11->fpreg[Fn].fExtended;
86 break;
87
88 default: return 0;
89 }
90 }
91
92 Fd = getFd(opcode);
93 switch (opcode & MASK_ARITHMETIC_OPCODE)
94 {
95 /* dyadic opcodes */
96 case ADF_CODE:
97 fpa11->fpreg[Fd].fExtended = floatx80_add(rFn,rFm);
98 break;
99
100 case MUF_CODE:
101 case FML_CODE:
102 fpa11->fpreg[Fd].fExtended = floatx80_mul(rFn,rFm);
103 break;
104
105 case SUF_CODE:
106 fpa11->fpreg[Fd].fExtended = floatx80_sub(rFn,rFm);
107 break;
108
109 case RSF_CODE:
110 fpa11->fpreg[Fd].fExtended = floatx80_sub(rFm,rFn);
111 break;
112
113 case DVF_CODE:
114 case FDV_CODE:
115 fpa11->fpreg[Fd].fExtended = floatx80_div(rFn,rFm);
116 break;
117
118 case RDF_CODE:
119 case FRD_CODE:
120 fpa11->fpreg[Fd].fExtended = floatx80_div(rFm,rFn);
121 break;
122
123#if 0
124 case POW_CODE:
125 fpa11->fpreg[Fd].fExtended = floatx80_pow(rFn,rFm);
126 break;
127
128 case RPW_CODE:
129 fpa11->fpreg[Fd].fExtended = floatx80_pow(rFm,rFn);
130 break;
131#endif
132
133 case RMF_CODE:
134 fpa11->fpreg[Fd].fExtended = floatx80_rem(rFn,rFm);
135 break;
136
137#if 0
138 case POL_CODE:
139 fpa11->fpreg[Fd].fExtended = floatx80_pol(rFn,rFm);
140 break;
141#endif
142
143 /* monadic opcodes */
144 case MVF_CODE:
145 fpa11->fpreg[Fd].fExtended = rFm;
146 break;
147
148 case MNF_CODE:
149 rFm.high ^= 0x8000;
150 fpa11->fpreg[Fd].fExtended = rFm;
151 break;
152
153 case ABS_CODE:
154 rFm.high &= 0x7fff;
155 fpa11->fpreg[Fd].fExtended = rFm;
156 break;
157
158 case RND_CODE:
159 case URD_CODE:
160 fpa11->fpreg[Fd].fExtended = floatx80_round_to_int(rFm);
161 break;
162
163 case SQT_CODE:
164 fpa11->fpreg[Fd].fExtended = floatx80_sqrt(rFm);
165 break;
166
167#if 0
168 case LOG_CODE:
169 fpa11->fpreg[Fd].fExtended = floatx80_log(rFm);
170 break;
171
172 case LGN_CODE:
173 fpa11->fpreg[Fd].fExtended = floatx80_ln(rFm);
174 break;
175
176 case EXP_CODE:
177 fpa11->fpreg[Fd].fExtended = floatx80_exp(rFm);
178 break;
179
180 case SIN_CODE:
181 fpa11->fpreg[Fd].fExtended = floatx80_sin(rFm);
182 break;
183
184 case COS_CODE:
185 fpa11->fpreg[Fd].fExtended = floatx80_cos(rFm);
186 break;
187
188 case TAN_CODE:
189 fpa11->fpreg[Fd].fExtended = floatx80_tan(rFm);
190 break;
191
192 case ASN_CODE:
193 fpa11->fpreg[Fd].fExtended = floatx80_arcsin(rFm);
194 break;
195
196 case ACS_CODE:
197 fpa11->fpreg[Fd].fExtended = floatx80_arccos(rFm);
198 break;
199
200 case ATN_CODE:
201 fpa11->fpreg[Fd].fExtended = floatx80_arctan(rFm);
202 break;
203#endif
204
205 case NRM_CODE:
206 break;
207
208 default:
209 {
210 nRc = 0;
211 }
212 }
213
214 if (0 != nRc) fpa11->fType[Fd] = typeExtended;
215 return nRc;
216}
217
218#if 0
219floatx80 floatx80_exp(floatx80 Fm)
220{
221//series
222}
223
224floatx80 floatx80_ln(floatx80 Fm)
225{
226//series
227}
228
229floatx80 floatx80_sin(floatx80 rFm)
230{
231//series
232}
233
234floatx80 floatx80_cos(floatx80 rFm)
235{
236//series
237}
238
239floatx80 floatx80_arcsin(floatx80 rFm)
240{
241//series
242}
243
244floatx80 floatx80_arctan(floatx80 rFm)
245{
246 //series
247}
248
249floatx80 floatx80_log(floatx80 rFm)
250{
251 return floatx80_div(floatx80_ln(rFm),getExtendedConstant(7));
252}
253
254floatx80 floatx80_tan(floatx80 rFm)
255{
256 return floatx80_div(floatx80_sin(rFm),floatx80_cos(rFm));
257}
258
259floatx80 floatx80_arccos(floatx80 rFm)
260{
261 //return floatx80_sub(halfPi,floatx80_arcsin(rFm));
262}
263
264floatx80 floatx80_pow(floatx80 rFn,floatx80 rFm)
265{
266 return floatx80_exp(floatx80_mul(rFm,floatx80_ln(rFn)));
267}
268
269floatx80 floatx80_pol(floatx80 rFn,floatx80 rFm)
270{
271 return floatx80_arctan(floatx80_div(rFn,rFm));
272}
273#endif
diff --git a/arch/arm26/nwfpe/fpa11.c b/arch/arm26/nwfpe/fpa11.c
new file mode 100644
index 000000000000..e954540a9464
--- /dev/null
+++ b/arch/arm26/nwfpe/fpa11.c
@@ -0,0 +1,221 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "fpa11.h"
23#include "fpopcode.h"
24
25#include "fpmodule.h"
26#include "fpmodule.inl"
27
28#include <linux/compiler.h>
29#include <asm/system.h>
30
31/* forward declarations */
32unsigned int EmulateCPDO(const unsigned int);
33unsigned int EmulateCPDT(const unsigned int);
34unsigned int EmulateCPRT(const unsigned int);
35
36/* Reset the FPA11 chip. Called to initialize and reset the emulator. */
37void resetFPA11(void)
38{
39 int i;
40 FPA11 *fpa11 = GET_FPA11();
41
42 /* initialize the register type array */
43 for (i=0;i<=7;i++)
44 {
45 fpa11->fType[i] = typeNone;
46 }
47
48 /* FPSR: set system id to FP_EMULATOR, set AC, clear all other bits */
49 fpa11->fpsr = FP_EMULATOR | BIT_AC;
50
51 /* FPCR: set SB, AB and DA bits, clear all others */
52#if MAINTAIN_FPCR
53 fpa11->fpcr = MASK_RESET;
54#endif
55}
56
57void SetRoundingMode(const unsigned int opcode)
58{
59#if MAINTAIN_FPCR
60 FPA11 *fpa11 = GET_FPA11();
61 fpa11->fpcr &= ~MASK_ROUNDING_MODE;
62#endif
63 switch (opcode & MASK_ROUNDING_MODE)
64 {
65 default:
66 case ROUND_TO_NEAREST:
67 float_rounding_mode = float_round_nearest_even;
68#if MAINTAIN_FPCR
69 fpa11->fpcr |= ROUND_TO_NEAREST;
70#endif
71 break;
72
73 case ROUND_TO_PLUS_INFINITY:
74 float_rounding_mode = float_round_up;
75#if MAINTAIN_FPCR
76 fpa11->fpcr |= ROUND_TO_PLUS_INFINITY;
77#endif
78 break;
79
80 case ROUND_TO_MINUS_INFINITY:
81 float_rounding_mode = float_round_down;
82#if MAINTAIN_FPCR
83 fpa11->fpcr |= ROUND_TO_MINUS_INFINITY;
84#endif
85 break;
86
87 case ROUND_TO_ZERO:
88 float_rounding_mode = float_round_to_zero;
89#if MAINTAIN_FPCR
90 fpa11->fpcr |= ROUND_TO_ZERO;
91#endif
92 break;
93 }
94}
95
96void SetRoundingPrecision(const unsigned int opcode)
97{
98#if MAINTAIN_FPCR
99 FPA11 *fpa11 = GET_FPA11();
100 fpa11->fpcr &= ~MASK_ROUNDING_PRECISION;
101#endif
102 switch (opcode & MASK_ROUNDING_PRECISION)
103 {
104 case ROUND_SINGLE:
105 floatx80_rounding_precision = 32;
106#if MAINTAIN_FPCR
107 fpa11->fpcr |= ROUND_SINGLE;
108#endif
109 break;
110
111 case ROUND_DOUBLE:
112 floatx80_rounding_precision = 64;
113#if MAINTAIN_FPCR
114 fpa11->fpcr |= ROUND_DOUBLE;
115#endif
116 break;
117
118 case ROUND_EXTENDED:
119 floatx80_rounding_precision = 80;
120#if MAINTAIN_FPCR
121 fpa11->fpcr |= ROUND_EXTENDED;
122#endif
123 break;
124
125 default: floatx80_rounding_precision = 80;
126 }
127}
128
129void FPA11_CheckInit(void)
130{
131 FPA11 *fpa11 = GET_FPA11();
132 if (unlikely(fpa11->initflag == 0))
133 {
134 resetFPA11();
135 SetRoundingMode(ROUND_TO_NEAREST);
136 SetRoundingPrecision(ROUND_EXTENDED);
137 fpa11->initflag = 1;
138 }
139}
140
141/* Emulate the instruction in the opcode. */
142unsigned int EmulateAll(unsigned int opcode)
143{
144 unsigned int nRc = 1, code;
145
146 code = opcode & 0x00000f00;
147 if (code == 0x00000100 || code == 0x00000200)
148 {
149 /* For coprocessor 1 or 2 (FPA11) */
150 code = opcode & 0x0e000000;
151 if (code == 0x0e000000)
152 {
153 if (opcode & 0x00000010)
154 {
155 /* Emulate conversion opcodes. */
156 /* Emulate register transfer opcodes. */
157 /* Emulate comparison opcodes. */
158 nRc = EmulateCPRT(opcode);
159 }
160 else
161 {
162 /* Emulate monadic arithmetic opcodes. */
163 /* Emulate dyadic arithmetic opcodes. */
164 nRc = EmulateCPDO(opcode);
165 }
166 }
167 else if (code == 0x0c000000)
168 {
169 /* Emulate load/store opcodes. */
170 /* Emulate load/store multiple opcodes. */
171 nRc = EmulateCPDT(opcode);
172 }
173 else
174 {
175 /* Invalid instruction detected. Return FALSE. */
176 nRc = 0;
177 }
178 }
179
180 return(nRc);
181}
182
183#if 0
184unsigned int EmulateAll1(unsigned int opcode)
185{
186 switch ((opcode >> 24) & 0xf)
187 {
188 case 0xc:
189 case 0xd:
190 if ((opcode >> 20) & 0x1)
191 {
192 switch ((opcode >> 8) & 0xf)
193 {
194 case 0x1: return PerformLDF(opcode); break;
195 case 0x2: return PerformLFM(opcode); break;
196 default: return 0;
197 }
198 }
199 else
200 {
201 switch ((opcode >> 8) & 0xf)
202 {
203 case 0x1: return PerformSTF(opcode); break;
204 case 0x2: return PerformSFM(opcode); break;
205 default: return 0;
206 }
207 }
208 break;
209
210 case 0xe:
211 if (opcode & 0x10)
212 return EmulateCPDO(opcode);
213 else
214 return EmulateCPRT(opcode);
215 break;
216
217 default: return 0;
218 }
219}
220#endif
221
diff --git a/arch/arm26/nwfpe/fpa11.h b/arch/arm26/nwfpe/fpa11.h
new file mode 100644
index 000000000000..be09902a211d
--- /dev/null
+++ b/arch/arm26/nwfpe/fpa11.h
@@ -0,0 +1,87 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.com, 1998-1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __FPA11_H__
23#define __FPA11_H__
24
25#define GET_FPA11() ((FPA11 *)(&current_thread_info()->fpstate))
26
27/*
28 * The processes registers are always at the very top of the 8K
29 * stack+task struct. Use the same method as 'current' uses to
30 * reach them.
31 */
32register unsigned int *user_registers asm("sl");
33
34#define GET_USERREG() (user_registers)
35
36#include <linux/thread_info.h>
37
38/* includes */
39#include "fpsr.h" /* FP control and status register definitions */
40#include "softfloat.h"
41
42#define typeNone 0x00
43#define typeSingle 0x01
44#define typeDouble 0x02
45#define typeExtended 0x03
46
47/*
48 * This must be no more and no less than 12 bytes.
49 */
50typedef union tagFPREG {
51 floatx80 fExtended;
52 float64 fDouble;
53 float32 fSingle;
54} FPREG;
55
56/*
57 * FPA11 device model.
58 *
59 * This structure is exported to user space. Do not re-order.
60 * Only add new stuff to the end, and do not change the size of
61 * any element. Elements of this structure are used by user
62 * space, and must match struct user_fp in include/asm-arm/user.h.
63 * We include the byte offsets below for documentation purposes.
64 *
65 * The size of this structure and FPREG are checked by fpmodule.c
66 * on initialisation. If the rules have been broken, NWFPE will
67 * not initialise.
68 */
69typedef struct tagFPA11 {
70/* 0 */ FPREG fpreg[8]; /* 8 floating point registers */
71/* 96 */ FPSR fpsr; /* floating point status register */
72/* 100 */ FPCR fpcr; /* floating point control register */
73/* 104 */ unsigned char fType[8]; /* type of floating point value held in
74 floating point registers. One of none
75 single, double or extended. */
76/* 112 */ int initflag; /* this is special. The kernel guarantees
77 to set it to 0 when a thread is launched,
78 so we can use it to detect whether this
79 instance of the emulator needs to be
80 initialised. */
81} FPA11;
82
83extern void resetFPA11(void);
84extern void SetRoundingMode(const unsigned int);
85extern void SetRoundingPrecision(const unsigned int);
86
87#endif
diff --git a/arch/arm26/nwfpe/fpa11.inl b/arch/arm26/nwfpe/fpa11.inl
new file mode 100644
index 000000000000..1c45cba2de66
--- /dev/null
+++ b/arch/arm26/nwfpe/fpa11.inl
@@ -0,0 +1,51 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "fpa11.h"
23
24/* Read and write floating point status register */
25extern __inline__ unsigned int readFPSR(void)
26{
27 FPA11 *fpa11 = GET_FPA11();
28 return(fpa11->fpsr);
29}
30
31extern __inline__ void writeFPSR(FPSR reg)
32{
33 FPA11 *fpa11 = GET_FPA11();
34 /* the sysid byte in the status register is readonly */
35 fpa11->fpsr = (fpa11->fpsr & MASK_SYSID) | (reg & ~MASK_SYSID);
36}
37
38/* Read and write floating point control register */
39extern __inline__ FPCR readFPCR(void)
40{
41 FPA11 *fpa11 = GET_FPA11();
42 /* clear SB, AB and DA bits before returning FPCR */
43 return(fpa11->fpcr & ~MASK_RFC);
44}
45
46extern __inline__ void writeFPCR(FPCR reg)
47{
48 FPA11 *fpa11 = GET_FPA11();
49 fpa11->fpcr &= ~MASK_WFC; /* clear SB, AB and DA bits */
50 fpa11->fpcr |= (reg & MASK_WFC); /* write SB, AB and DA bits */
51}
diff --git a/arch/arm26/nwfpe/fpa11_cpdo.c b/arch/arm26/nwfpe/fpa11_cpdo.c
new file mode 100644
index 000000000000..343a6b9fd520
--- /dev/null
+++ b/arch/arm26/nwfpe/fpa11_cpdo.c
@@ -0,0 +1,117 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "fpa11.h"
23#include "fpopcode.h"
24
25unsigned int SingleCPDO(const unsigned int opcode);
26unsigned int DoubleCPDO(const unsigned int opcode);
27unsigned int ExtendedCPDO(const unsigned int opcode);
28
29unsigned int EmulateCPDO(const unsigned int opcode)
30{
31 FPA11 *fpa11 = GET_FPA11();
32 unsigned int Fd, nType, nDest, nRc = 1;
33
34 //printk("EmulateCPDO(0x%08x)\n",opcode);
35
36 /* Get the destination size. If not valid let Linux perform
37 an invalid instruction trap. */
38 nDest = getDestinationSize(opcode);
39 if (typeNone == nDest) return 0;
40
41 SetRoundingMode(opcode);
42
43 /* Compare the size of the operands in Fn and Fm.
44 Choose the largest size and perform operations in that size,
45 in order to make use of all the precision of the operands.
46 If Fm is a constant, we just grab a constant of a size
47 matching the size of the operand in Fn. */
48 if (MONADIC_INSTRUCTION(opcode))
49 nType = nDest;
50 else
51 nType = fpa11->fType[getFn(opcode)];
52
53 if (!CONSTANT_FM(opcode))
54 {
55 register unsigned int Fm = getFm(opcode);
56 if (nType < fpa11->fType[Fm])
57 {
58 nType = fpa11->fType[Fm];
59 }
60 }
61
62 switch (nType)
63 {
64 case typeSingle : nRc = SingleCPDO(opcode); break;
65 case typeDouble : nRc = DoubleCPDO(opcode); break;
66 case typeExtended : nRc = ExtendedCPDO(opcode); break;
67 default : nRc = 0;
68 }
69
70 /* If the operation succeeded, check to see if the result in the
71 destination register is the correct size. If not force it
72 to be. */
73 Fd = getFd(opcode);
74 nType = fpa11->fType[Fd];
75 if ((0 != nRc) && (nDest != nType))
76 {
77 switch (nDest)
78 {
79 case typeSingle:
80 {
81 if (typeDouble == nType)
82 fpa11->fpreg[Fd].fSingle =
83 float64_to_float32(fpa11->fpreg[Fd].fDouble);
84 else
85 fpa11->fpreg[Fd].fSingle =
86 floatx80_to_float32(fpa11->fpreg[Fd].fExtended);
87 }
88 break;
89
90 case typeDouble:
91 {
92 if (typeSingle == nType)
93 fpa11->fpreg[Fd].fDouble =
94 float32_to_float64(fpa11->fpreg[Fd].fSingle);
95 else
96 fpa11->fpreg[Fd].fDouble =
97 floatx80_to_float64(fpa11->fpreg[Fd].fExtended);
98 }
99 break;
100
101 case typeExtended:
102 {
103 if (typeSingle == nType)
104 fpa11->fpreg[Fd].fExtended =
105 float32_to_floatx80(fpa11->fpreg[Fd].fSingle);
106 else
107 fpa11->fpreg[Fd].fExtended =
108 float64_to_floatx80(fpa11->fpreg[Fd].fDouble);
109 }
110 break;
111 }
112
113 fpa11->fType[Fd] = nDest;
114 }
115
116 return nRc;
117}
diff --git a/arch/arm26/nwfpe/fpa11_cpdt.c b/arch/arm26/nwfpe/fpa11_cpdt.c
new file mode 100644
index 000000000000..e12db7c51a76
--- /dev/null
+++ b/arch/arm26/nwfpe/fpa11_cpdt.c
@@ -0,0 +1,368 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.com, 1998-1999
4 (c) Philip Blundell, 1998
5
6 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21*/
22
23#include "fpa11.h"
24#include "softfloat.h"
25#include "fpopcode.h"
26#include "fpmodule.h"
27#include "fpmodule.inl"
28
29#include <asm/uaccess.h>
30
31static inline
32void loadSingle(const unsigned int Fn,const unsigned int *pMem)
33{
34 FPA11 *fpa11 = GET_FPA11();
35 fpa11->fType[Fn] = typeSingle;
36 get_user(fpa11->fpreg[Fn].fSingle, pMem);
37}
38
39static inline
40void loadDouble(const unsigned int Fn,const unsigned int *pMem)
41{
42 FPA11 *fpa11 = GET_FPA11();
43 unsigned int *p;
44 p = (unsigned int*)&fpa11->fpreg[Fn].fDouble;
45 fpa11->fType[Fn] = typeDouble;
46 get_user(p[0], &pMem[1]);
47 get_user(p[1], &pMem[0]); /* sign & exponent */
48}
49
50static inline
51void loadExtended(const unsigned int Fn,const unsigned int *pMem)
52{
53 FPA11 *fpa11 = GET_FPA11();
54 unsigned int *p;
55 p = (unsigned int*)&fpa11->fpreg[Fn].fExtended;
56 fpa11->fType[Fn] = typeExtended;
57 get_user(p[0], &pMem[0]); /* sign & exponent */
58 get_user(p[1], &pMem[2]); /* ls bits */
59 get_user(p[2], &pMem[1]); /* ms bits */
60}
61
62static inline
63void loadMultiple(const unsigned int Fn,const unsigned int *pMem)
64{
65 FPA11 *fpa11 = GET_FPA11();
66 register unsigned int *p;
67 unsigned long x;
68
69 p = (unsigned int*)&(fpa11->fpreg[Fn]);
70 get_user(x, &pMem[0]);
71 fpa11->fType[Fn] = (x >> 14) & 0x00000003;
72
73 switch (fpa11->fType[Fn])
74 {
75 case typeSingle:
76 case typeDouble:
77 {
78 get_user(p[0], &pMem[2]); /* Single */
79 get_user(p[1], &pMem[1]); /* double msw */
80 p[2] = 0; /* empty */
81 }
82 break;
83
84 case typeExtended:
85 {
86 get_user(p[1], &pMem[2]);
87 get_user(p[2], &pMem[1]); /* msw */
88 p[0] = (x & 0x80003fff);
89 }
90 break;
91 }
92}
93
94static inline
95void storeSingle(const unsigned int Fn,unsigned int *pMem)
96{
97 FPA11 *fpa11 = GET_FPA11();
98 union
99 {
100 float32 f;
101 unsigned int i[1];
102 } val;
103
104 switch (fpa11->fType[Fn])
105 {
106 case typeDouble:
107 val.f = float64_to_float32(fpa11->fpreg[Fn].fDouble);
108 break;
109
110 case typeExtended:
111 val.f = floatx80_to_float32(fpa11->fpreg[Fn].fExtended);
112 break;
113
114 default: val.f = fpa11->fpreg[Fn].fSingle;
115 }
116
117 put_user(val.i[0], pMem);
118}
119
120static inline
121void storeDouble(const unsigned int Fn,unsigned int *pMem)
122{
123 FPA11 *fpa11 = GET_FPA11();
124 union
125 {
126 float64 f;
127 unsigned int i[2];
128 } val;
129
130 switch (fpa11->fType[Fn])
131 {
132 case typeSingle:
133 val.f = float32_to_float64(fpa11->fpreg[Fn].fSingle);
134 break;
135
136 case typeExtended:
137 val.f = floatx80_to_float64(fpa11->fpreg[Fn].fExtended);
138 break;
139
140 default: val.f = fpa11->fpreg[Fn].fDouble;
141 }
142
143 put_user(val.i[1], &pMem[0]); /* msw */
144 put_user(val.i[0], &pMem[1]); /* lsw */
145}
146
147static inline
148void storeExtended(const unsigned int Fn,unsigned int *pMem)
149{
150 FPA11 *fpa11 = GET_FPA11();
151 union
152 {
153 floatx80 f;
154 unsigned int i[3];
155 } val;
156
157 switch (fpa11->fType[Fn])
158 {
159 case typeSingle:
160 val.f = float32_to_floatx80(fpa11->fpreg[Fn].fSingle);
161 break;
162
163 case typeDouble:
164 val.f = float64_to_floatx80(fpa11->fpreg[Fn].fDouble);
165 break;
166
167 default: val.f = fpa11->fpreg[Fn].fExtended;
168 }
169
170 put_user(val.i[0], &pMem[0]); /* sign & exp */
171 put_user(val.i[1], &pMem[2]);
172 put_user(val.i[2], &pMem[1]); /* msw */
173}
174
175static inline
176void storeMultiple(const unsigned int Fn,unsigned int *pMem)
177{
178 FPA11 *fpa11 = GET_FPA11();
179 register unsigned int nType, *p;
180
181 p = (unsigned int*)&(fpa11->fpreg[Fn]);
182 nType = fpa11->fType[Fn];
183
184 switch (nType)
185 {
186 case typeSingle:
187 case typeDouble:
188 {
189 put_user(p[0], &pMem[2]); /* single */
190 put_user(p[1], &pMem[1]); /* double msw */
191 put_user(nType << 14, &pMem[0]);
192 }
193 break;
194
195 case typeExtended:
196 {
197 put_user(p[2], &pMem[1]); /* msw */
198 put_user(p[1], &pMem[2]);
199 put_user((p[0] & 0x80003fff) | (nType << 14), &pMem[0]);
200 }
201 break;
202 }
203}
204
205unsigned int PerformLDF(const unsigned int opcode)
206{
207 unsigned int *pBase, *pAddress, *pFinal, nRc = 1,
208 write_back = WRITE_BACK(opcode);
209
210 //printk("PerformLDF(0x%08x), Fd = 0x%08x\n",opcode,getFd(opcode));
211
212 pBase = (unsigned int*)readRegister(getRn(opcode));
213 if (REG_PC == getRn(opcode))
214 {
215 pBase += 2;
216 write_back = 0;
217 }
218
219 pFinal = pBase;
220 if (BIT_UP_SET(opcode))
221 pFinal += getOffset(opcode);
222 else
223 pFinal -= getOffset(opcode);
224
225 if (PREINDEXED(opcode)) pAddress = pFinal; else pAddress = pBase;
226
227 switch (opcode & MASK_TRANSFER_LENGTH)
228 {
229 case TRANSFER_SINGLE : loadSingle(getFd(opcode),pAddress); break;
230 case TRANSFER_DOUBLE : loadDouble(getFd(opcode),pAddress); break;
231 case TRANSFER_EXTENDED: loadExtended(getFd(opcode),pAddress); break;
232 default: nRc = 0;
233 }
234
235 if (write_back) writeRegister(getRn(opcode),(unsigned int)pFinal);
236 return nRc;
237}
238
239unsigned int PerformSTF(const unsigned int opcode)
240{
241 unsigned int *pBase, *pAddress, *pFinal, nRc = 1,
242 write_back = WRITE_BACK(opcode);
243
244 //printk("PerformSTF(0x%08x), Fd = 0x%08x\n",opcode,getFd(opcode));
245 SetRoundingMode(ROUND_TO_NEAREST);
246
247 pBase = (unsigned int*)readRegister(getRn(opcode));
248 if (REG_PC == getRn(opcode))
249 {
250 pBase += 2;
251 write_back = 0;
252 }
253
254 pFinal = pBase;
255 if (BIT_UP_SET(opcode))
256 pFinal += getOffset(opcode);
257 else
258 pFinal -= getOffset(opcode);
259
260 if (PREINDEXED(opcode)) pAddress = pFinal; else pAddress = pBase;
261
262 switch (opcode & MASK_TRANSFER_LENGTH)
263 {
264 case TRANSFER_SINGLE : storeSingle(getFd(opcode),pAddress); break;
265 case TRANSFER_DOUBLE : storeDouble(getFd(opcode),pAddress); break;
266 case TRANSFER_EXTENDED: storeExtended(getFd(opcode),pAddress); break;
267 default: nRc = 0;
268 }
269
270 if (write_back) writeRegister(getRn(opcode),(unsigned int)pFinal);
271 return nRc;
272}
273
274unsigned int PerformLFM(const unsigned int opcode)
275{
276 unsigned int i, Fd, *pBase, *pAddress, *pFinal,
277 write_back = WRITE_BACK(opcode);
278
279 pBase = (unsigned int*)readRegister(getRn(opcode));
280 if (REG_PC == getRn(opcode))
281 {
282 pBase += 2;
283 write_back = 0;
284 }
285
286 pFinal = pBase;
287 if (BIT_UP_SET(opcode))
288 pFinal += getOffset(opcode);
289 else
290 pFinal -= getOffset(opcode);
291
292 if (PREINDEXED(opcode)) pAddress = pFinal; else pAddress = pBase;
293
294 Fd = getFd(opcode);
295 for (i=getRegisterCount(opcode);i>0;i--)
296 {
297 loadMultiple(Fd,pAddress);
298 pAddress += 3; Fd++;
299 if (Fd == 8) Fd = 0;
300 }
301
302 if (write_back) writeRegister(getRn(opcode),(unsigned int)pFinal);
303 return 1;
304}
305
306unsigned int PerformSFM(const unsigned int opcode)
307{
308 unsigned int i, Fd, *pBase, *pAddress, *pFinal,
309 write_back = WRITE_BACK(opcode);
310
311 pBase = (unsigned int*)readRegister(getRn(opcode));
312 if (REG_PC == getRn(opcode))
313 {
314 pBase += 2;
315 write_back = 0;
316 }
317
318 pFinal = pBase;
319 if (BIT_UP_SET(opcode))
320 pFinal += getOffset(opcode);
321 else
322 pFinal -= getOffset(opcode);
323
324 if (PREINDEXED(opcode)) pAddress = pFinal; else pAddress = pBase;
325
326 Fd = getFd(opcode);
327 for (i=getRegisterCount(opcode);i>0;i--)
328 {
329 storeMultiple(Fd,pAddress);
330 pAddress += 3; Fd++;
331 if (Fd == 8) Fd = 0;
332 }
333
334 if (write_back) writeRegister(getRn(opcode),(unsigned int)pFinal);
335 return 1;
336}
337
338#if 1
339unsigned int EmulateCPDT(const unsigned int opcode)
340{
341 unsigned int nRc = 0;
342
343 //printk("EmulateCPDT(0x%08x)\n",opcode);
344
345 if (LDF_OP(opcode))
346 {
347 nRc = PerformLDF(opcode);
348 }
349 else if (LFM_OP(opcode))
350 {
351 nRc = PerformLFM(opcode);
352 }
353 else if (STF_OP(opcode))
354 {
355 nRc = PerformSTF(opcode);
356 }
357 else if (SFM_OP(opcode))
358 {
359 nRc = PerformSFM(opcode);
360 }
361 else
362 {
363 nRc = 0;
364 }
365
366 return nRc;
367}
368#endif
diff --git a/arch/arm26/nwfpe/fpa11_cprt.c b/arch/arm26/nwfpe/fpa11_cprt.c
new file mode 100644
index 000000000000..a201076c1f14
--- /dev/null
+++ b/arch/arm26/nwfpe/fpa11_cprt.c
@@ -0,0 +1,289 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4 (c) Philip Blundell, 1999
5
6 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21*/
22
23#include "fpa11.h"
24#include "milieu.h"
25#include "softfloat.h"
26#include "fpopcode.h"
27#include "fpa11.inl"
28#include "fpmodule.h"
29#include "fpmodule.inl"
30
31extern flag floatx80_is_nan(floatx80);
32extern flag float64_is_nan( float64);
33extern flag float32_is_nan( float32);
34
35void SetRoundingMode(const unsigned int opcode);
36
37unsigned int PerformFLT(const unsigned int opcode);
38unsigned int PerformFIX(const unsigned int opcode);
39
40static unsigned int
41PerformComparison(const unsigned int opcode);
42
43unsigned int EmulateCPRT(const unsigned int opcode)
44{
45 unsigned int nRc = 1;
46
47 //printk("EmulateCPRT(0x%08x)\n",opcode);
48
49 if (opcode & 0x800000)
50 {
51 /* This is some variant of a comparison (PerformComparison will
52 sort out which one). Since most of the other CPRT
53 instructions are oddball cases of some sort or other it makes
54 sense to pull this out into a fast path. */
55 return PerformComparison(opcode);
56 }
57
58 /* Hint to GCC that we'd like a jump table rather than a load of CMPs */
59 switch ((opcode & 0x700000) >> 20)
60 {
61 case FLT_CODE >> 20: nRc = PerformFLT(opcode); break;
62 case FIX_CODE >> 20: nRc = PerformFIX(opcode); break;
63
64 case WFS_CODE >> 20: writeFPSR(readRegister(getRd(opcode))); break;
65 case RFS_CODE >> 20: writeRegister(getRd(opcode),readFPSR()); break;
66
67#if 0 /* We currently have no use for the FPCR, so there's no point
68 in emulating it. */
69 case WFC_CODE >> 20: writeFPCR(readRegister(getRd(opcode)));
70 case RFC_CODE >> 20: writeRegister(getRd(opcode),readFPCR()); break;
71#endif
72
73 default: nRc = 0;
74 }
75
76 return nRc;
77}
78
79unsigned int PerformFLT(const unsigned int opcode)
80{
81 FPA11 *fpa11 = GET_FPA11();
82
83 unsigned int nRc = 1;
84 SetRoundingMode(opcode);
85
86 switch (opcode & MASK_ROUNDING_PRECISION)
87 {
88 case ROUND_SINGLE:
89 {
90 fpa11->fType[getFn(opcode)] = typeSingle;
91 fpa11->fpreg[getFn(opcode)].fSingle =
92 int32_to_float32(readRegister(getRd(opcode)));
93 }
94 break;
95
96 case ROUND_DOUBLE:
97 {
98 fpa11->fType[getFn(opcode)] = typeDouble;
99 fpa11->fpreg[getFn(opcode)].fDouble =
100 int32_to_float64(readRegister(getRd(opcode)));
101 }
102 break;
103
104 case ROUND_EXTENDED:
105 {
106 fpa11->fType[getFn(opcode)] = typeExtended;
107 fpa11->fpreg[getFn(opcode)].fExtended =
108 int32_to_floatx80(readRegister(getRd(opcode)));
109 }
110 break;
111
112 default: nRc = 0;
113 }
114
115 return nRc;
116}
117
118unsigned int PerformFIX(const unsigned int opcode)
119{
120 FPA11 *fpa11 = GET_FPA11();
121 unsigned int nRc = 1;
122 unsigned int Fn = getFm(opcode);
123
124 SetRoundingMode(opcode);
125
126 switch (fpa11->fType[Fn])
127 {
128 case typeSingle:
129 {
130 writeRegister(getRd(opcode),
131 float32_to_int32(fpa11->fpreg[Fn].fSingle));
132 }
133 break;
134
135 case typeDouble:
136 {
137 writeRegister(getRd(opcode),
138 float64_to_int32(fpa11->fpreg[Fn].fDouble));
139 }
140 break;
141
142 case typeExtended:
143 {
144 writeRegister(getRd(opcode),
145 floatx80_to_int32(fpa11->fpreg[Fn].fExtended));
146 }
147 break;
148
149 default: nRc = 0;
150 }
151
152 return nRc;
153}
154
155
156static unsigned int __inline__
157PerformComparisonOperation(floatx80 Fn, floatx80 Fm)
158{
159 unsigned int flags = 0;
160
161 /* test for less than condition */
162 if (floatx80_lt(Fn,Fm))
163 {
164 flags |= CC_NEGATIVE;
165 }
166
167 /* test for equal condition */
168 if (floatx80_eq(Fn,Fm))
169 {
170 flags |= CC_ZERO;
171 }
172
173 /* test for greater than or equal condition */
174 if (floatx80_lt(Fm,Fn))
175 {
176 flags |= CC_CARRY;
177 }
178
179 writeConditionCodes(flags);
180 return 1;
181}
182
183/* This instruction sets the flags N, Z, C, V in the FPSR. */
184
185static unsigned int PerformComparison(const unsigned int opcode)
186{
187 FPA11 *fpa11 = GET_FPA11();
188 unsigned int Fn, Fm;
189 floatx80 rFn, rFm;
190 int e_flag = opcode & 0x400000; /* 1 if CxFE */
191 int n_flag = opcode & 0x200000; /* 1 if CNxx */
192 unsigned int flags = 0;
193
194 //printk("PerformComparison(0x%08x)\n",opcode);
195
196 Fn = getFn(opcode);
197 Fm = getFm(opcode);
198
199 /* Check for unordered condition and convert all operands to 80-bit
200 format.
201 ?? Might be some mileage in avoiding this conversion if possible.
202 Eg, if both operands are 32-bit, detect this and do a 32-bit
203 comparison (cheaper than an 80-bit one). */
204 switch (fpa11->fType[Fn])
205 {
206 case typeSingle:
207 //printk("single.\n");
208 if (float32_is_nan(fpa11->fpreg[Fn].fSingle))
209 goto unordered;
210 rFn = float32_to_floatx80(fpa11->fpreg[Fn].fSingle);
211 break;
212
213 case typeDouble:
214 //printk("double.\n");
215 if (float64_is_nan(fpa11->fpreg[Fn].fDouble))
216 goto unordered;
217 rFn = float64_to_floatx80(fpa11->fpreg[Fn].fDouble);
218 break;
219
220 case typeExtended:
221 //printk("extended.\n");
222 if (floatx80_is_nan(fpa11->fpreg[Fn].fExtended))
223 goto unordered;
224 rFn = fpa11->fpreg[Fn].fExtended;
225 break;
226
227 default: return 0;
228 }
229
230 if (CONSTANT_FM(opcode))
231 {
232 //printk("Fm is a constant: #%d.\n",Fm);
233 rFm = getExtendedConstant(Fm);
234 if (floatx80_is_nan(rFm))
235 goto unordered;
236 }
237 else
238 {
239 //printk("Fm = r%d which contains a ",Fm);
240 switch (fpa11->fType[Fm])
241 {
242 case typeSingle:
243 //printk("single.\n");
244 if (float32_is_nan(fpa11->fpreg[Fm].fSingle))
245 goto unordered;
246 rFm = float32_to_floatx80(fpa11->fpreg[Fm].fSingle);
247 break;
248
249 case typeDouble:
250 //printk("double.\n");
251 if (float64_is_nan(fpa11->fpreg[Fm].fDouble))
252 goto unordered;
253 rFm = float64_to_floatx80(fpa11->fpreg[Fm].fDouble);
254 break;
255
256 case typeExtended:
257 //printk("extended.\n");
258 if (floatx80_is_nan(fpa11->fpreg[Fm].fExtended))
259 goto unordered;
260 rFm = fpa11->fpreg[Fm].fExtended;
261 break;
262
263 default: return 0;
264 }
265 }
266
267 if (n_flag)
268 {
269 rFm.high ^= 0x8000;
270 }
271
272 return PerformComparisonOperation(rFn,rFm);
273
274 unordered:
275 /* ?? The FPA data sheet is pretty vague about this, in particular
276 about whether the non-E comparisons can ever raise exceptions.
277 This implementation is based on a combination of what it says in
278 the data sheet, observation of how the Acorn emulator actually
279 behaves (and how programs expect it to) and guesswork. */
280 flags |= CC_OVERFLOW;
281 flags &= ~(CC_ZERO | CC_NEGATIVE);
282
283 if (BIT_AC & readFPSR()) flags |= CC_CARRY;
284
285 if (e_flag) float_raise(float_flag_invalid);
286
287 writeConditionCodes(flags);
288 return 1;
289}
diff --git a/arch/arm26/nwfpe/fpmodule.c b/arch/arm26/nwfpe/fpmodule.c
new file mode 100644
index 000000000000..528fa710aa34
--- /dev/null
+++ b/arch/arm26/nwfpe/fpmodule.c
@@ -0,0 +1,182 @@
1
2/*
3 NetWinder Floating Point Emulator
4 (c) Rebel.com, 1998-1999
5 (c) Philip Blundell, 1998-1999
6
7 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22*/
23
24#include "fpa11.h"
25
26#include <linux/module.h>
27#include <linux/version.h>
28#include <linux/config.h>
29
30/* XXX */
31#include <linux/errno.h>
32#include <linux/types.h>
33#include <linux/kernel.h>
34#include <linux/signal.h>
35#include <linux/sched.h>
36#include <linux/init.h>
37/* XXX */
38
39#include "softfloat.h"
40#include "fpopcode.h"
41#include "fpmodule.h"
42#include "fpa11.inl"
43
44/* kernel symbols required for signal handling */
45typedef struct task_struct* PTASK;
46
47#ifdef MODULE
48void fp_send_sig(unsigned long sig, PTASK p, int priv);
49#if LINUX_VERSION_CODE > 0x20115
50MODULE_AUTHOR("Scott Bambrough <scottb@rebel.com>");
51MODULE_DESCRIPTION("NWFPE floating point emulator");
52#endif
53
54#else
55#define fp_send_sig send_sig
56#define kern_fp_enter fp_enter
57
58extern char fpe_type[];
59#endif
60
61/* kernel function prototypes required */
62void fp_setup(void);
63
64/* external declarations for saved kernel symbols */
65extern void (*kern_fp_enter)(void);
66
67/* Original value of fp_enter from kernel before patched by fpe_init. */
68static void (*orig_fp_enter)(void);
69
70/* forward declarations */
71extern void nwfpe_enter(void);
72
73#ifdef MODULE
74/*
75 * Return 0 if we can be unloaded. This can only happen if
76 * kern_fp_enter is still pointing at nwfpe_enter
77 */
78static int fpe_unload(void)
79{
80 return (kern_fp_enter == nwfpe_enter) ? 0 : 1;
81}
82#endif
83
84static int __init fpe_init(void)
85{
86 if (sizeof(FPA11) > sizeof(union fp_state)) {
87 printk(KERN_ERR "nwfpe: bad structure size\n");
88 return -EINVAL;
89 }
90
91 if (sizeof(FPREG) != 12) {
92 printk(KERN_ERR "nwfpe: bad register size\n");
93 return -EINVAL;
94 }
95
96#ifdef MODULE
97 if (!mod_member_present(&__this_module, can_unload))
98 return -EINVAL;
99 __this_module.can_unload = fpe_unload;
100#else
101 if (fpe_type[0] && strcmp(fpe_type, "nwfpe"))
102 return 0;
103#endif
104
105 /* Display title, version and copyright information. */
106 printk(KERN_WARNING "NetWinder Floating Point Emulator V0.95 "
107 "(c) 1998-1999 Rebel.com\n");
108
109 /* Save pointer to the old FP handler and then patch ourselves in */
110 orig_fp_enter = kern_fp_enter;
111 kern_fp_enter = nwfpe_enter;
112
113 return 0;
114}
115
116static void __exit fpe_exit(void)
117{
118 /* Restore the values we saved earlier. */
119 kern_fp_enter = orig_fp_enter;
120}
121
122/*
123ScottB: November 4, 1998
124
125Moved this function out of softfloat-specialize into fpmodule.c.
126This effectively isolates all the changes required for integrating with the
127Linux kernel into fpmodule.c. Porting to NetBSD should only require modifying
128fpmodule.c to integrate with the NetBSD kernel (I hope!).
129
130[1/1/99: Not quite true any more unfortunately. There is Linux-specific
131code to access data in user space in some other source files at the
132moment (grep for get_user / put_user calls). --philb]
133
134float_exception_flags is a global variable in SoftFloat.
135
136This function is called by the SoftFloat routines to raise a floating
137point exception. We check the trap enable byte in the FPSR, and raise
138a SIGFPE exception if necessary. If not the relevant bits in the
139cumulative exceptions flag byte are set and we return.
140*/
141
142void float_raise(signed char flags)
143{
144 register unsigned int fpsr, cumulativeTraps;
145
146#ifdef CONFIG_DEBUG_USER
147 printk(KERN_DEBUG "NWFPE: %s[%d] takes exception %08x at %p from %08x\n",
148 current->comm, current->pid, flags,
149 __builtin_return_address(0), GET_USERREG()[15]);
150#endif
151
152 /* Keep SoftFloat exception flags up to date. */
153 float_exception_flags |= flags;
154
155 /* Read fpsr and initialize the cumulativeTraps. */
156 fpsr = readFPSR();
157 cumulativeTraps = 0;
158
159 /* For each type of exception, the cumulative trap exception bit is only
160 set if the corresponding trap enable bit is not set. */
161 if ((!(fpsr & BIT_IXE)) && (flags & BIT_IXC))
162 cumulativeTraps |= BIT_IXC;
163 if ((!(fpsr & BIT_UFE)) && (flags & BIT_UFC))
164 cumulativeTraps |= BIT_UFC;
165 if ((!(fpsr & BIT_OFE)) && (flags & BIT_OFC))
166 cumulativeTraps |= BIT_OFC;
167 if ((!(fpsr & BIT_DZE)) && (flags & BIT_DZC))
168 cumulativeTraps |= BIT_DZC;
169 if ((!(fpsr & BIT_IOE)) && (flags & BIT_IOC))
170 cumulativeTraps |= BIT_IOC;
171
172 /* Set the cumulative exceptions flags. */
173 if (cumulativeTraps)
174 writeFPSR(fpsr | cumulativeTraps);
175
176 /* Raise an exception if necessary. */
177 if (fpsr & (flags << 16))
178 fp_send_sig(SIGFPE, current, 1);
179}
180
181module_init(fpe_init);
182module_exit(fpe_exit);
diff --git a/arch/arm26/nwfpe/fpmodule.h b/arch/arm26/nwfpe/fpmodule.h
new file mode 100644
index 000000000000..ef71aab46a32
--- /dev/null
+++ b/arch/arm26/nwfpe/fpmodule.h
@@ -0,0 +1,47 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.com, 1998-1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __FPMODULE_H__
23#define __FPMODULE_H__
24
25#include <linux/config.h>
26
27#define REG_ORIG_R0 16
28#define REG_CPSR 15
29#define REG_PC 15
30#define REG_LR 14
31#define REG_SP 13
32#define REG_IP 12
33#define REG_FP 11
34#define REG_R10 10
35#define REG_R9 9
36#define REG_R9 9
37#define REG_R8 8
38#define REG_R7 7
39#define REG_R6 6
40#define REG_R5 5
41#define REG_R4 4
42#define REG_R3 3
43#define REG_R2 2
44#define REG_R1 1
45#define REG_R0 0
46
47#endif
diff --git a/arch/arm26/nwfpe/fpmodule.inl b/arch/arm26/nwfpe/fpmodule.inl
new file mode 100644
index 000000000000..ef228378ffaf
--- /dev/null
+++ b/arch/arm26/nwfpe/fpmodule.inl
@@ -0,0 +1,84 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22extern __inline__
23unsigned int readRegister(const unsigned int nReg)
24{
25 /* Note: The CPU thinks it has dealt with the current instruction. As
26 a result the program counter has been advanced to the next
27 instruction, and points 4 bytes beyond the actual instruction
28 that caused the invalid instruction trap to occur. We adjust
29 for this in this routine. LDF/STF instructions with Rn = PC
30 depend on the PC being correct, as they use PC+8 in their
31 address calculations. */
32 unsigned int *userRegisters = GET_USERREG();
33 unsigned int val = userRegisters[nReg];
34 if (REG_PC == nReg) val -= 4;
35 return val;
36}
37
38extern __inline__
39void writeRegister(const unsigned int nReg, const unsigned int val)
40{
41 unsigned int *userRegisters = GET_USERREG();
42 userRegisters[nReg] = val;
43}
44
45extern __inline__
46unsigned int readCPSR(void)
47{
48 return(readRegister(REG_CPSR));
49}
50
51extern __inline__
52void writeCPSR(const unsigned int val)
53{
54 writeRegister(REG_CPSR,val);
55}
56
57extern __inline__
58unsigned int readConditionCodes(void)
59{
60#ifdef __FPEM_TEST__
61 return(0);
62#else
63 return(readCPSR() & CC_MASK);
64#endif
65}
66
67extern __inline__
68void writeConditionCodes(const unsigned int val)
69{
70 unsigned int *userRegisters = GET_USERREG();
71 unsigned int rval;
72 /*
73 * Operate directly on userRegisters since
74 * the CPSR may be the PC register itself.
75 */
76 rval = userRegisters[REG_CPSR] & ~CC_MASK;
77 userRegisters[REG_CPSR] = rval | (val & CC_MASK);
78}
79
80extern __inline__
81unsigned int readMemoryInt(unsigned int *pMem)
82{
83 return *pMem;
84}
diff --git a/arch/arm26/nwfpe/fpopcode.c b/arch/arm26/nwfpe/fpopcode.c
new file mode 100644
index 000000000000..d81ddd188322
--- /dev/null
+++ b/arch/arm26/nwfpe/fpopcode.c
@@ -0,0 +1,148 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "fpa11.h"
23#include "softfloat.h"
24#include "fpopcode.h"
25#include "fpsr.h"
26#include "fpmodule.h"
27#include "fpmodule.inl"
28
29const floatx80 floatx80Constant[] = {
30 { 0x0000, 0x0000000000000000ULL}, /* extended 0.0 */
31 { 0x3fff, 0x8000000000000000ULL}, /* extended 1.0 */
32 { 0x4000, 0x8000000000000000ULL}, /* extended 2.0 */
33 { 0x4000, 0xc000000000000000ULL}, /* extended 3.0 */
34 { 0x4001, 0x8000000000000000ULL}, /* extended 4.0 */
35 { 0x4001, 0xa000000000000000ULL}, /* extended 5.0 */
36 { 0x3ffe, 0x8000000000000000ULL}, /* extended 0.5 */
37 { 0x4002, 0xa000000000000000ULL} /* extended 10.0 */
38};
39
40const float64 float64Constant[] = {
41 0x0000000000000000ULL, /* double 0.0 */
42 0x3ff0000000000000ULL, /* double 1.0 */
43 0x4000000000000000ULL, /* double 2.0 */
44 0x4008000000000000ULL, /* double 3.0 */
45 0x4010000000000000ULL, /* double 4.0 */
46 0x4014000000000000ULL, /* double 5.0 */
47 0x3fe0000000000000ULL, /* double 0.5 */
48 0x4024000000000000ULL /* double 10.0 */
49};
50
51const float32 float32Constant[] = {
52 0x00000000, /* single 0.0 */
53 0x3f800000, /* single 1.0 */
54 0x40000000, /* single 2.0 */
55 0x40400000, /* single 3.0 */
56 0x40800000, /* single 4.0 */
57 0x40a00000, /* single 5.0 */
58 0x3f000000, /* single 0.5 */
59 0x41200000 /* single 10.0 */
60};
61
62unsigned int getTransferLength(const unsigned int opcode)
63{
64 unsigned int nRc;
65
66 switch (opcode & MASK_TRANSFER_LENGTH)
67 {
68 case 0x00000000: nRc = 1; break; /* single precision */
69 case 0x00008000: nRc = 2; break; /* double precision */
70 case 0x00400000: nRc = 3; break; /* extended precision */
71 default: nRc = 0;
72 }
73
74 return(nRc);
75}
76
77unsigned int getRegisterCount(const unsigned int opcode)
78{
79 unsigned int nRc;
80
81 switch (opcode & MASK_REGISTER_COUNT)
82 {
83 case 0x00000000: nRc = 4; break;
84 case 0x00008000: nRc = 1; break;
85 case 0x00400000: nRc = 2; break;
86 case 0x00408000: nRc = 3; break;
87 default: nRc = 0;
88 }
89
90 return(nRc);
91}
92
93unsigned int getRoundingPrecision(const unsigned int opcode)
94{
95 unsigned int nRc;
96
97 switch (opcode & MASK_ROUNDING_PRECISION)
98 {
99 case 0x00000000: nRc = 1; break;
100 case 0x00000080: nRc = 2; break;
101 case 0x00080000: nRc = 3; break;
102 default: nRc = 0;
103 }
104
105 return(nRc);
106}
107
108unsigned int getDestinationSize(const unsigned int opcode)
109{
110 unsigned int nRc;
111
112 switch (opcode & MASK_DESTINATION_SIZE)
113 {
114 case 0x00000000: nRc = typeSingle; break;
115 case 0x00000080: nRc = typeDouble; break;
116 case 0x00080000: nRc = typeExtended; break;
117 default: nRc = typeNone;
118 }
119
120 return(nRc);
121}
122
123/* condition code lookup table
124 index into the table is test code: EQ, NE, ... LT, GT, AL, NV
125 bit position in short is condition code: NZCV */
126static const unsigned short aCC[16] = {
127 0xF0F0, // EQ == Z set
128 0x0F0F, // NE
129 0xCCCC, // CS == C set
130 0x3333, // CC
131 0xFF00, // MI == N set
132 0x00FF, // PL
133 0xAAAA, // VS == V set
134 0x5555, // VC
135 0x0C0C, // HI == C set && Z clear
136 0xF3F3, // LS == C clear || Z set
137 0xAA55, // GE == (N==V)
138 0x55AA, // LT == (N!=V)
139 0x0A05, // GT == (!Z && (N==V))
140 0xF5FA, // LE == (Z || (N!=V))
141 0xFFFF, // AL always
142 0 // NV
143};
144
145unsigned int checkCondition(const unsigned int opcode, const unsigned int ccodes)
146{
147 return (aCC[opcode>>28] >> (ccodes>>28)) & 1;
148}
diff --git a/arch/arm26/nwfpe/fpopcode.h b/arch/arm26/nwfpe/fpopcode.h
new file mode 100644
index 000000000000..13c7419262ab
--- /dev/null
+++ b/arch/arm26/nwfpe/fpopcode.h
@@ -0,0 +1,390 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __FPOPCODE_H__
23#define __FPOPCODE_H__
24
25/*
26ARM Floating Point Instruction Classes
27| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
28|c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
29|c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|0|1| o f f s e t | CPDT
30| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
31|c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
32|c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
33|c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
34| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
35
36CPDT data transfer instructions
37 LDF, STF, LFM, SFM
38
39CPDO dyadic arithmetic instructions
40 ADF, MUF, SUF, RSF, DVF, RDF,
41 POW, RPW, RMF, FML, FDV, FRD, POL
42
43CPDO monadic arithmetic instructions
44 MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
45 SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
46
47CPRT joint arithmetic/data transfer instructions
48 FIX (arithmetic followed by load/store)
49 FLT (load/store followed by arithmetic)
50 CMF, CNF CMFE, CNFE (comparisons)
51 WFS, RFS (write/read floating point status register)
52 WFC, RFC (write/read floating point control register)
53
54cond condition codes
55P pre/post index bit: 0 = postindex, 1 = preindex
56U up/down bit: 0 = stack grows down, 1 = stack grows up
57W write back bit: 1 = update base register (Rn)
58L load/store bit: 0 = store, 1 = load
59Rn base register
60Rd destination/source register
61Fd floating point destination register
62Fn floating point source register
63Fm floating point source register or floating point constant
64
65uv transfer length (TABLE 1)
66wx register count (TABLE 2)
67abcd arithmetic opcode (TABLES 3 & 4)
68ef destination size (rounding precision) (TABLE 5)
69gh rounding mode (TABLE 6)
70j dyadic/monadic bit: 0 = dyadic, 1 = monadic
71i constant bit: 1 = constant (TABLE 6)
72*/
73
74/*
75TABLE 1
76+-------------------------+---+---+---------+---------+
77| Precision | u | v | FPSR.EP | length |
78+-------------------------+---+---+---------+---------+
79| Single | 0 ü 0 | x | 1 words |
80| Double | 1 ü 1 | x | 2 words |
81| Extended | 1 ü 1 | x | 3 words |
82| Packed decimal | 1 ü 1 | 0 | 3 words |
83| Expanded packed decimal | 1 ü 1 | 1 | 4 words |
84+-------------------------+---+---+---------+---------+
85Note: x = don't care
86*/
87
88/*
89TABLE 2
90+---+---+---------------------------------+
91| w | x | Number of registers to transfer |
92+---+---+---------------------------------+
93| 0 ü 1 | 1 |
94| 1 ü 0 | 2 |
95| 1 ü 1 | 3 |
96| 0 ü 0 | 4 |
97+---+---+---------------------------------+
98*/
99
100/*
101TABLE 3: Dyadic Floating Point Opcodes
102+---+---+---+---+----------+-----------------------+-----------------------+
103| a | b | c | d | Mnemonic | Description | Operation |
104+---+---+---+---+----------+-----------------------+-----------------------+
105| 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm |
106| 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm |
107| 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm |
108| 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn |
109| 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm |
110| 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn |
111| 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm |
112| 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn |
113| 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) |
114| 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm |
115| 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm |
116| 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn |
117| 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) |
118| 1 | 1 | 0 | 1 | | undefined instruction | trap |
119| 1 | 1 | 1 | 0 | | undefined instruction | trap |
120| 1 | 1 | 1 | 1 | | undefined instruction | trap |
121+---+---+---+---+----------+-----------------------+-----------------------+
122Note: POW, RPW, POL are deprecated, and are available for backwards
123 compatibility only.
124*/
125
126/*
127TABLE 4: Monadic Floating Point Opcodes
128+---+---+---+---+----------+-----------------------+-----------------------+
129| a | b | c | d | Mnemonic | Description | Operation |
130+---+---+---+---+----------+-----------------------+-----------------------+
131| 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm |
132| 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm |
133| 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) |
134| 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |
135| 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) |
136| 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) |
137| 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) |
138| 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm |
139| 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) |
140| 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) |
141| 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) |
142| 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) |
143| 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) |
144| 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) |
145| 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |
146| 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) |
147+---+---+---+---+----------+-----------------------+-----------------------+
148Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
149 available for backwards compatibility only.
150*/
151
152/*
153TABLE 5
154+-------------------------+---+---+
155| Rounding Precision | e | f |
156+-------------------------+---+---+
157| IEEE Single precision | 0 ü 0 |
158| IEEE Double precision | 0 ü 1 |
159| IEEE Extended precision | 1 ü 0 |
160| undefined (trap) | 1 ü 1 |
161+-------------------------+---+---+
162*/
163
164/*
165TABLE 5
166+---------------------------------+---+---+
167| Rounding Mode | g | h |
168+---------------------------------+---+---+
169| Round to nearest (default) | 0 ü 0 |
170| Round toward plus infinity | 0 ü 1 |
171| Round toward negative infinity | 1 ü 0 |
172| Round toward zero | 1 ü 1 |
173+---------------------------------+---+---+
174*/
175
176/*
177===
178=== Definitions for load and store instructions
179===
180*/
181
182/* bit masks */
183#define BIT_PREINDEX 0x01000000
184#define BIT_UP 0x00800000
185#define BIT_WRITE_BACK 0x00200000
186#define BIT_LOAD 0x00100000
187
188/* masks for load/store */
189#define MASK_CPDT 0x0c000000 /* data processing opcode */
190#define MASK_OFFSET 0x000000ff
191#define MASK_TRANSFER_LENGTH 0x00408000
192#define MASK_REGISTER_COUNT MASK_TRANSFER_LENGTH
193#define MASK_COPROCESSOR 0x00000f00
194
195/* Tests for transfer length */
196#define TRANSFER_SINGLE 0x00000000
197#define TRANSFER_DOUBLE 0x00008000
198#define TRANSFER_EXTENDED 0x00400000
199#define TRANSFER_PACKED MASK_TRANSFER_LENGTH
200
201/* Get the coprocessor number from the opcode. */
202#define getCoprocessorNumber(opcode) ((opcode & MASK_COPROCESSOR) >> 8)
203
204/* Get the offset from the opcode. */
205#define getOffset(opcode) (opcode & MASK_OFFSET)
206
207/* Tests for specific data transfer load/store opcodes. */
208#define TEST_OPCODE(opcode,mask) (((opcode) & (mask)) == (mask))
209
210#define LOAD_OP(opcode) TEST_OPCODE((opcode),MASK_CPDT | BIT_LOAD)
211#define STORE_OP(opcode) ((opcode & (MASK_CPDT | BIT_LOAD)) == MASK_CPDT)
212
213#define LDF_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1))
214#define LFM_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 2))
215#define STF_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 1))
216#define SFM_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 2))
217
218#define PREINDEXED(opcode) ((opcode & BIT_PREINDEX) != 0)
219#define POSTINDEXED(opcode) ((opcode & BIT_PREINDEX) == 0)
220#define BIT_UP_SET(opcode) ((opcode & BIT_UP) != 0)
221#define BIT_UP_CLEAR(opcode) ((opcode & BIT_DOWN) == 0)
222#define WRITE_BACK(opcode) ((opcode & BIT_WRITE_BACK) != 0)
223#define LOAD(opcode) ((opcode & BIT_LOAD) != 0)
224#define STORE(opcode) ((opcode & BIT_LOAD) == 0)
225
226/*
227===
228=== Definitions for arithmetic instructions
229===
230*/
231/* bit masks */
232#define BIT_MONADIC 0x00008000
233#define BIT_CONSTANT 0x00000008
234
235#define CONSTANT_FM(opcode) ((opcode & BIT_CONSTANT) != 0)
236#define MONADIC_INSTRUCTION(opcode) ((opcode & BIT_MONADIC) != 0)
237
238/* instruction identification masks */
239#define MASK_CPDO 0x0e000000 /* arithmetic opcode */
240#define MASK_ARITHMETIC_OPCODE 0x00f08000
241#define MASK_DESTINATION_SIZE 0x00080080
242
243/* dyadic arithmetic opcodes. */
244#define ADF_CODE 0x00000000
245#define MUF_CODE 0x00100000
246#define SUF_CODE 0x00200000
247#define RSF_CODE 0x00300000
248#define DVF_CODE 0x00400000
249#define RDF_CODE 0x00500000
250#define POW_CODE 0x00600000
251#define RPW_CODE 0x00700000
252#define RMF_CODE 0x00800000
253#define FML_CODE 0x00900000
254#define FDV_CODE 0x00a00000
255#define FRD_CODE 0x00b00000
256#define POL_CODE 0x00c00000
257/* 0x00d00000 is an invalid dyadic arithmetic opcode */
258/* 0x00e00000 is an invalid dyadic arithmetic opcode */
259/* 0x00f00000 is an invalid dyadic arithmetic opcode */
260
261/* monadic arithmetic opcodes. */
262#define MVF_CODE 0x00008000
263#define MNF_CODE 0x00108000
264#define ABS_CODE 0x00208000
265#define RND_CODE 0x00308000
266#define SQT_CODE 0x00408000
267#define LOG_CODE 0x00508000
268#define LGN_CODE 0x00608000
269#define EXP_CODE 0x00708000
270#define SIN_CODE 0x00808000
271#define COS_CODE 0x00908000
272#define TAN_CODE 0x00a08000
273#define ASN_CODE 0x00b08000
274#define ACS_CODE 0x00c08000
275#define ATN_CODE 0x00d08000
276#define URD_CODE 0x00e08000
277#define NRM_CODE 0x00f08000
278
279/*
280===
281=== Definitions for register transfer and comparison instructions
282===
283*/
284
285#define MASK_CPRT 0x0e000010 /* register transfer opcode */
286#define MASK_CPRT_CODE 0x00f00000
287#define FLT_CODE 0x00000000
288#define FIX_CODE 0x00100000
289#define WFS_CODE 0x00200000
290#define RFS_CODE 0x00300000
291#define WFC_CODE 0x00400000
292#define RFC_CODE 0x00500000
293#define CMF_CODE 0x00900000
294#define CNF_CODE 0x00b00000
295#define CMFE_CODE 0x00d00000
296#define CNFE_CODE 0x00f00000
297
298/*
299===
300=== Common definitions
301===
302*/
303
304/* register masks */
305#define MASK_Rd 0x0000f000
306#define MASK_Rn 0x000f0000
307#define MASK_Fd 0x00007000
308#define MASK_Fm 0x00000007
309#define MASK_Fn 0x00070000
310
311/* condition code masks */
312#define CC_MASK 0xf0000000
313#define CC_NEGATIVE 0x80000000
314#define CC_ZERO 0x40000000
315#define CC_CARRY 0x20000000
316#define CC_OVERFLOW 0x10000000
317#define CC_EQ 0x00000000
318#define CC_NE 0x10000000
319#define CC_CS 0x20000000
320#define CC_HS CC_CS
321#define CC_CC 0x30000000
322#define CC_LO CC_CC
323#define CC_MI 0x40000000
324#define CC_PL 0x50000000
325#define CC_VS 0x60000000
326#define CC_VC 0x70000000
327#define CC_HI 0x80000000
328#define CC_LS 0x90000000
329#define CC_GE 0xa0000000
330#define CC_LT 0xb0000000
331#define CC_GT 0xc0000000
332#define CC_LE 0xd0000000
333#define CC_AL 0xe0000000
334#define CC_NV 0xf0000000
335
336/* rounding masks/values */
337#define MASK_ROUNDING_MODE 0x00000060
338#define ROUND_TO_NEAREST 0x00000000
339#define ROUND_TO_PLUS_INFINITY 0x00000020
340#define ROUND_TO_MINUS_INFINITY 0x00000040
341#define ROUND_TO_ZERO 0x00000060
342
343#define MASK_ROUNDING_PRECISION 0x00080080
344#define ROUND_SINGLE 0x00000000
345#define ROUND_DOUBLE 0x00000080
346#define ROUND_EXTENDED 0x00080000
347
348/* Get the condition code from the opcode. */
349#define getCondition(opcode) (opcode >> 28)
350
351/* Get the source register from the opcode. */
352#define getRn(opcode) ((opcode & MASK_Rn) >> 16)
353
354/* Get the destination floating point register from the opcode. */
355#define getFd(opcode) ((opcode & MASK_Fd) >> 12)
356
357/* Get the first source floating point register from the opcode. */
358#define getFn(opcode) ((opcode & MASK_Fn) >> 16)
359
360/* Get the second source floating point register from the opcode. */
361#define getFm(opcode) (opcode & MASK_Fm)
362
363/* Get the destination register from the opcode. */
364#define getRd(opcode) ((opcode & MASK_Rd) >> 12)
365
366/* Get the rounding mode from the opcode. */
367#define getRoundingMode(opcode) ((opcode & MASK_ROUNDING_MODE) >> 5)
368
369static inline const floatx80 getExtendedConstant(const unsigned int nIndex)
370{
371 extern const floatx80 floatx80Constant[];
372 return floatx80Constant[nIndex];
373}
374
375static inline const float64 getDoubleConstant(const unsigned int nIndex)
376{
377 extern const float64 float64Constant[];
378 return float64Constant[nIndex];
379}
380
381static inline const float32 getSingleConstant(const unsigned int nIndex)
382{
383 extern const float32 float32Constant[];
384 return float32Constant[nIndex];
385}
386
387extern unsigned int getRegisterCount(const unsigned int opcode);
388extern unsigned int getDestinationSize(const unsigned int opcode);
389
390#endif
diff --git a/arch/arm26/nwfpe/fpsr.h b/arch/arm26/nwfpe/fpsr.h
new file mode 100644
index 000000000000..6dafb0f5243c
--- /dev/null
+++ b/arch/arm26/nwfpe/fpsr.h
@@ -0,0 +1,108 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.com, 1998-1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __FPSR_H__
23#define __FPSR_H__
24
25/*
26The FPSR is a 32 bit register consisting of 4 parts, each exactly
27one byte.
28
29 SYSTEM ID
30 EXCEPTION TRAP ENABLE BYTE
31 SYSTEM CONTROL BYTE
32 CUMULATIVE EXCEPTION FLAGS BYTE
33
34The FPCR is a 32 bit register consisting of bit flags.
35*/
36
37/* SYSTEM ID
38------------
39Note: the system id byte is read only */
40
41typedef unsigned int FPSR; /* type for floating point status register */
42typedef unsigned int FPCR; /* type for floating point control register */
43
44#define MASK_SYSID 0xff000000
45#define BIT_HARDWARE 0x80000000
46#define FP_EMULATOR 0x01000000 /* System ID for emulator */
47#define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */
48
49/* EXCEPTION TRAP ENABLE BYTE
50----------------------------- */
51
52#define MASK_TRAP_ENABLE 0x00ff0000
53#define MASK_TRAP_ENABLE_STRICT 0x001f0000
54#define BIT_IXE 0x00100000 /* inexact exception enable */
55#define BIT_UFE 0x00080000 /* underflow exception enable */
56#define BIT_OFE 0x00040000 /* overflow exception enable */
57#define BIT_DZE 0x00020000 /* divide by zero exception enable */
58#define BIT_IOE 0x00010000 /* invalid operation exception enable */
59
60/* SYSTEM CONTROL BYTE
61---------------------- */
62
63#define MASK_SYSTEM_CONTROL 0x0000ff00
64#define MASK_TRAP_STRICT 0x00001f00
65
66#define BIT_AC 0x00001000 /* use alternative C-flag definition
67 for compares */
68#define BIT_EP 0x00000800 /* use expanded packed decimal format */
69#define BIT_SO 0x00000400 /* select synchronous operation of FPA */
70#define BIT_NE 0x00000200 /* NaN exception bit */
71#define BIT_ND 0x00000100 /* no denormalized numbers bit */
72
73/* CUMULATIVE EXCEPTION FLAGS BYTE
74---------------------------------- */
75
76#define MASK_EXCEPTION_FLAGS 0x000000ff
77#define MASK_EXCEPTION_FLAGS_STRICT 0x0000001f
78
79#define BIT_IXC 0x00000010 /* inexact exception flag */
80#define BIT_UFC 0x00000008 /* underflow exception flag */
81#define BIT_OFC 0x00000004 /* overfloat exception flag */
82#define BIT_DZC 0x00000002 /* divide by zero exception flag */
83#define BIT_IOC 0x00000001 /* invalid operation exception flag */
84
85/* Floating Point Control Register
86----------------------------------*/
87
88#define BIT_RU 0x80000000 /* rounded up bit */
89#define BIT_IE 0x10000000 /* inexact bit */
90#define BIT_MO 0x08000000 /* mantissa overflow bit */
91#define BIT_EO 0x04000000 /* exponent overflow bit */
92#define BIT_SB 0x00000800 /* store bounce */
93#define BIT_AB 0x00000400 /* arithmetic bounce */
94#define BIT_RE 0x00000200 /* rounding exception */
95#define BIT_DA 0x00000100 /* disable FPA */
96
97#define MASK_OP 0x00f08010 /* AU operation code */
98#define MASK_PR 0x00080080 /* AU precision */
99#define MASK_S1 0x00070000 /* AU source register 1 */
100#define MASK_S2 0x00000007 /* AU source register 2 */
101#define MASK_DS 0x00007000 /* AU destination register */
102#define MASK_RM 0x00000060 /* AU rounding mode */
103#define MASK_ALU 0x9cfff2ff /* only ALU can write these bits */
104#define MASK_RESET 0x00000d00 /* bits set on reset, all others cleared */
105#define MASK_WFC MASK_RESET
106#define MASK_RFC ~MASK_RESET
107
108#endif
diff --git a/arch/arm26/nwfpe/milieu.h b/arch/arm26/nwfpe/milieu.h
new file mode 100644
index 000000000000..a3892ab2dca4
--- /dev/null
+++ b/arch/arm26/nwfpe/milieu.h
@@ -0,0 +1,48 @@
1
2/*
3===============================================================================
4
5This C header file is part of the SoftFloat IEC/IEEE Floating-point
6Arithmetic Package, Release 2.
7
8Written by John R. Hauser. This work was made possible in part by the
9International Computer Science Institute, located at Suite 600, 1947 Center
10Street, Berkeley, California 94704. Funding was partially provided by the
11National Science Foundation under grant MIP-9311980. The original version
12of this code was written as part of a project to build a fixed-point vector
13processor in collaboration with the University of California at Berkeley,
14overseen by Profs. Nelson Morgan and John Wawrzynek. More information
15is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
16arithmetic/softfloat.html'.
17
18THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
19has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
20TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
21PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
22AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
23
24Derivative works are acceptable, even for commercial purposes, so long as
25(1) they include prominent notice that the work is derivative, and (2) they
26include prominent notice akin to these three paragraphs for those parts of
27this code that are retained.
28
29===============================================================================
30*/
31
32/*
33-------------------------------------------------------------------------------
34Include common integer types and flags.
35-------------------------------------------------------------------------------
36*/
37#include "ARM-gcc.h"
38
39/*
40-------------------------------------------------------------------------------
41Symbolic Boolean literals.
42-------------------------------------------------------------------------------
43*/
44enum {
45 FALSE = 0,
46 TRUE = 1
47};
48
diff --git a/arch/arm26/nwfpe/single_cpdo.c b/arch/arm26/nwfpe/single_cpdo.c
new file mode 100644
index 000000000000..5cdcddbb8999
--- /dev/null
+++ b/arch/arm26/nwfpe/single_cpdo.c
@@ -0,0 +1,255 @@
1/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4
5 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "fpa11.h"
23#include "softfloat.h"
24#include "fpopcode.h"
25
26float32 float32_exp(float32 Fm);
27float32 float32_ln(float32 Fm);
28float32 float32_sin(float32 rFm);
29float32 float32_cos(float32 rFm);
30float32 float32_arcsin(float32 rFm);
31float32 float32_arctan(float32 rFm);
32float32 float32_log(float32 rFm);
33float32 float32_tan(float32 rFm);
34float32 float32_arccos(float32 rFm);
35float32 float32_pow(float32 rFn,float32 rFm);
36float32 float32_pol(float32 rFn,float32 rFm);
37
38unsigned int SingleCPDO(const unsigned int opcode)
39{
40 FPA11 *fpa11 = GET_FPA11();
41 float32 rFm, rFn = 0; //FIXME - should be zero?
42 unsigned int Fd, Fm, Fn, nRc = 1;
43
44 Fm = getFm(opcode);
45 if (CONSTANT_FM(opcode))
46 {
47 rFm = getSingleConstant(Fm);
48 }
49 else
50 {
51 switch (fpa11->fType[Fm])
52 {
53 case typeSingle:
54 rFm = fpa11->fpreg[Fm].fSingle;
55 break;
56
57 default: return 0;
58 }
59 }
60
61 if (!MONADIC_INSTRUCTION(opcode))
62 {
63 Fn = getFn(opcode);
64 switch (fpa11->fType[Fn])
65 {
66 case typeSingle:
67 rFn = fpa11->fpreg[Fn].fSingle;
68 break;
69
70 default: return 0;
71 }
72 }
73
74 Fd = getFd(opcode);
75 switch (opcode & MASK_ARITHMETIC_OPCODE)
76 {
77 /* dyadic opcodes */
78 case ADF_CODE:
79 fpa11->fpreg[Fd].fSingle = float32_add(rFn,rFm);
80 break;
81
82 case MUF_CODE:
83 case FML_CODE:
84 fpa11->fpreg[Fd].fSingle = float32_mul(rFn,rFm);
85 break;
86
87 case SUF_CODE:
88 fpa11->fpreg[Fd].fSingle = float32_sub(rFn,rFm);
89 break;
90
91 case RSF_CODE:
92 fpa11->fpreg[Fd].fSingle = float32_sub(rFm,rFn);
93 break;
94
95 case DVF_CODE:
96 case FDV_CODE:
97 fpa11->fpreg[Fd].fSingle = float32_div(rFn,rFm);
98 break;
99
100 case RDF_CODE:
101 case FRD_CODE:
102 fpa11->fpreg[Fd].fSingle = float32_div(rFm,rFn);
103 break;
104
105#if 0
106 case POW_CODE:
107 fpa11->fpreg[Fd].fSingle = float32_pow(rFn,rFm);
108 break;
109
110 case RPW_CODE:
111 fpa11->fpreg[Fd].fSingle = float32_pow(rFm,rFn);
112 break;
113#endif
114
115 case RMF_CODE:
116 fpa11->fpreg[Fd].fSingle = float32_rem(rFn,rFm);
117 break;
118
119#if 0
120 case POL_CODE:
121 fpa11->fpreg[Fd].fSingle = float32_pol(rFn,rFm);
122 break;
123#endif
124
125 /* monadic opcodes */
126 case MVF_CODE:
127 fpa11->fpreg[Fd].fSingle = rFm;
128 break;
129
130 case MNF_CODE:
131 rFm ^= 0x80000000;
132 fpa11->fpreg[Fd].fSingle = rFm;
133 break;
134
135 case ABS_CODE:
136 rFm &= 0x7fffffff;
137 fpa11->fpreg[Fd].fSingle = rFm;
138 break;
139
140 case RND_CODE:
141 case URD_CODE:
142 fpa11->fpreg[Fd].fSingle = float32_round_to_int(rFm);
143 break;
144
145 case SQT_CODE:
146 fpa11->fpreg[Fd].fSingle = float32_sqrt(rFm);
147 break;
148
149#if 0
150 case LOG_CODE:
151 fpa11->fpreg[Fd].fSingle = float32_log(rFm);
152 break;
153
154 case LGN_CODE:
155 fpa11->fpreg[Fd].fSingle = float32_ln(rFm);
156 break;
157
158 case EXP_CODE:
159 fpa11->fpreg[Fd].fSingle = float32_exp(rFm);
160 break;
161
162 case SIN_CODE:
163 fpa11->fpreg[Fd].fSingle = float32_sin(rFm);
164 break;
165
166 case COS_CODE:
167 fpa11->fpreg[Fd].fSingle = float32_cos(rFm);
168 break;
169
170 case TAN_CODE:
171 fpa11->fpreg[Fd].fSingle = float32_tan(rFm);
172 break;
173
174 case ASN_CODE:
175 fpa11->fpreg[Fd].fSingle = float32_arcsin(rFm);
176 break;
177
178 case ACS_CODE:
179 fpa11->fpreg[Fd].fSingle = float32_arccos(rFm);
180 break;
181
182 case ATN_CODE:
183 fpa11->fpreg[Fd].fSingle = float32_arctan(rFm);
184 break;
185#endif
186
187 case NRM_CODE:
188 break;
189
190 default:
191 {
192 nRc = 0;
193 }
194 }
195
196 if (0 != nRc) fpa11->fType[Fd] = typeSingle;
197 return nRc;
198}
199
200#if 0
201float32 float32_exp(float32 Fm)
202{
203//series
204}
205
206float32 float32_ln(float32 Fm)
207{
208//series
209}
210
211float32 float32_sin(float32 rFm)
212{
213//series
214}
215
216float32 float32_cos(float32 rFm)
217{
218//series
219}
220
221float32 float32_arcsin(float32 rFm)
222{
223//series
224}
225
226float32 float32_arctan(float32 rFm)
227{
228 //series
229}
230
231float32 float32_arccos(float32 rFm)
232{
233 //return float32_sub(halfPi,float32_arcsin(rFm));
234}
235
236float32 float32_log(float32 rFm)
237{
238 return float32_div(float32_ln(rFm),getSingleConstant(7));
239}
240
241float32 float32_tan(float32 rFm)
242{
243 return float32_div(float32_sin(rFm),float32_cos(rFm));
244}
245
246float32 float32_pow(float32 rFn,float32 rFm)
247{
248 return float32_exp(float32_mul(rFm,float32_ln(rFn)));
249}
250
251float32 float32_pol(float32 rFn,float32 rFm)
252{
253 return float32_arctan(float32_div(rFn,rFm));
254}
255#endif
diff --git a/arch/arm26/nwfpe/softfloat-macros b/arch/arm26/nwfpe/softfloat-macros
new file mode 100644
index 000000000000..5469989f2c5e
--- /dev/null
+++ b/arch/arm26/nwfpe/softfloat-macros
@@ -0,0 +1,740 @@
1
2/*
3===============================================================================
4
5This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
6Arithmetic Package, Release 2.
7
8Written by John R. Hauser. This work was made possible in part by the
9International Computer Science Institute, located at Suite 600, 1947 Center
10Street, Berkeley, California 94704. Funding was partially provided by the
11National Science Foundation under grant MIP-9311980. The original version
12of this code was written as part of a project to build a fixed-point vector
13processor in collaboration with the University of California at Berkeley,
14overseen by Profs. Nelson Morgan and John Wawrzynek. More information
15is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
16arithmetic/softfloat.html'.
17
18THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
19has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
20TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
21PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
22AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
23
24Derivative works are acceptable, even for commercial purposes, so long as
25(1) they include prominent notice that the work is derivative, and (2) they
26include prominent notice akin to these three paragraphs for those parts of
27this code that are retained.
28
29===============================================================================
30*/
31
32/*
33-------------------------------------------------------------------------------
34Shifts `a' right by the number of bits given in `count'. If any nonzero
35bits are shifted off, they are ``jammed'' into the least significant bit of
36the result by setting the least significant bit to 1. The value of `count'
37can be arbitrarily large; in particular, if `count' is greater than 32, the
38result will be either 0 or 1, depending on whether `a' is zero or nonzero.
39The result is stored in the location pointed to by `zPtr'.
40-------------------------------------------------------------------------------
41*/
42INLINE void shift32RightJamming( bits32 a, int16 count, bits32 *zPtr )
43{
44 bits32 z;
45 if ( count == 0 ) {
46 z = a;
47 }
48 else if ( count < 32 ) {
49 z = ( a>>count ) | ( ( a<<( ( - count ) & 31 ) ) != 0 );
50 }
51 else {
52 z = ( a != 0 );
53 }
54 *zPtr = z;
55}
56
57/*
58-------------------------------------------------------------------------------
59Shifts `a' right by the number of bits given in `count'. If any nonzero
60bits are shifted off, they are ``jammed'' into the least significant bit of
61the result by setting the least significant bit to 1. The value of `count'
62can be arbitrarily large; in particular, if `count' is greater than 64, the
63result will be either 0 or 1, depending on whether `a' is zero or nonzero.
64The result is stored in the location pointed to by `zPtr'.
65-------------------------------------------------------------------------------
66*/
67INLINE void shift64RightJamming( bits64 a, int16 count, bits64 *zPtr )
68{
69 bits64 z;
70
71 __asm__("@shift64RightJamming -- start");
72 if ( count == 0 ) {
73 z = a;
74 }
75 else if ( count < 64 ) {
76 z = ( a>>count ) | ( ( a<<( ( - count ) & 63 ) ) != 0 );
77 }
78 else {
79 z = ( a != 0 );
80 }
81 __asm__("@shift64RightJamming -- end");
82 *zPtr = z;
83}
84
85/*
86-------------------------------------------------------------------------------
87Shifts the 128-bit value formed by concatenating `a0' and `a1' right by 64
88_plus_ the number of bits given in `count'. The shifted result is at most
8964 nonzero bits; this is stored at the location pointed to by `z0Ptr'. The
90bits shifted off form a second 64-bit result as follows: The _last_ bit
91shifted off is the most-significant bit of the extra result, and the other
9263 bits of the extra result are all zero if and only if _all_but_the_last_
93bits shifted off were all zero. This extra result is stored in the location
94pointed to by `z1Ptr'. The value of `count' can be arbitrarily large.
95 (This routine makes more sense if `a0' and `a1' are considered to form a
96fixed-point value with binary point between `a0' and `a1'. This fixed-point
97value is shifted right by the number of bits given in `count', and the
98integer part of the result is returned at the location pointed to by
99`z0Ptr'. The fractional part of the result may be slightly corrupted as
100described above, and is returned at the location pointed to by `z1Ptr'.)
101-------------------------------------------------------------------------------
102*/
103INLINE void
104 shift64ExtraRightJamming(
105 bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
106{
107 bits64 z0, z1;
108 int8 negCount = ( - count ) & 63;
109
110 if ( count == 0 ) {
111 z1 = a1;
112 z0 = a0;
113 }
114 else if ( count < 64 ) {
115 z1 = ( a0<<negCount ) | ( a1 != 0 );
116 z0 = a0>>count;
117 }
118 else {
119 if ( count == 64 ) {
120 z1 = a0 | ( a1 != 0 );
121 }
122 else {
123 z1 = ( ( a0 | a1 ) != 0 );
124 }
125 z0 = 0;
126 }
127 *z1Ptr = z1;
128 *z0Ptr = z0;
129
130}
131
132/*
133-------------------------------------------------------------------------------
134Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
135number of bits given in `count'. Any bits shifted off are lost. The value
136of `count' can be arbitrarily large; in particular, if `count' is greater
137than 128, the result will be 0. The result is broken into two 64-bit pieces
138which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
139-------------------------------------------------------------------------------
140*/
141INLINE void
142 shift128Right(
143 bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
144{
145 bits64 z0, z1;
146 int8 negCount = ( - count ) & 63;
147
148 if ( count == 0 ) {
149 z1 = a1;
150 z0 = a0;
151 }
152 else if ( count < 64 ) {
153 z1 = ( a0<<negCount ) | ( a1>>count );
154 z0 = a0>>count;
155 }
156 else {
157 z1 = ( count < 64 ) ? ( a0>>( count & 63 ) ) : 0;
158 z0 = 0;
159 }
160 *z1Ptr = z1;
161 *z0Ptr = z0;
162
163}
164
165/*
166-------------------------------------------------------------------------------
167Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
168number of bits given in `count'. If any nonzero bits are shifted off, they
169are ``jammed'' into the least significant bit of the result by setting the
170least significant bit to 1. The value of `count' can be arbitrarily large;
171in particular, if `count' is greater than 128, the result will be either 0
172or 1, depending on whether the concatenation of `a0' and `a1' is zero or
173nonzero. The result is broken into two 64-bit pieces which are stored at
174the locations pointed to by `z0Ptr' and `z1Ptr'.
175-------------------------------------------------------------------------------
176*/
177INLINE void
178 shift128RightJamming(
179 bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
180{
181 bits64 z0, z1;
182 int8 negCount = ( - count ) & 63;
183
184 if ( count == 0 ) {
185 z1 = a1;
186 z0 = a0;
187 }
188 else if ( count < 64 ) {
189 z1 = ( a0<<negCount ) | ( a1>>count ) | ( ( a1<<negCount ) != 0 );
190 z0 = a0>>count;
191 }
192 else {
193 if ( count == 64 ) {
194 z1 = a0 | ( a1 != 0 );
195 }
196 else if ( count < 128 ) {
197 z1 = ( a0>>( count & 63 ) ) | ( ( ( a0<<negCount ) | a1 ) != 0 );
198 }
199 else {
200 z1 = ( ( a0 | a1 ) != 0 );
201 }
202 z0 = 0;
203 }
204 *z1Ptr = z1;
205 *z0Ptr = z0;
206
207}
208
209/*
210-------------------------------------------------------------------------------
211Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' right
212by 64 _plus_ the number of bits given in `count'. The shifted result is
213at most 128 nonzero bits; these are broken into two 64-bit pieces which are
214stored at the locations pointed to by `z0Ptr' and `z1Ptr'. The bits shifted
215off form a third 64-bit result as follows: The _last_ bit shifted off is
216the most-significant bit of the extra result, and the other 63 bits of the
217extra result are all zero if and only if _all_but_the_last_ bits shifted off
218were all zero. This extra result is stored in the location pointed to by
219`z2Ptr'. The value of `count' can be arbitrarily large.
220 (This routine makes more sense if `a0', `a1', and `a2' are considered
221to form a fixed-point value with binary point between `a1' and `a2'. This
222fixed-point value is shifted right by the number of bits given in `count',
223and the integer part of the result is returned at the locations pointed to
224by `z0Ptr' and `z1Ptr'. The fractional part of the result may be slightly
225corrupted as described above, and is returned at the location pointed to by
226`z2Ptr'.)
227-------------------------------------------------------------------------------
228*/
229INLINE void
230 shift128ExtraRightJamming(
231 bits64 a0,
232 bits64 a1,
233 bits64 a2,
234 int16 count,
235 bits64 *z0Ptr,
236 bits64 *z1Ptr,
237 bits64 *z2Ptr
238 )
239{
240 bits64 z0, z1, z2;
241 int8 negCount = ( - count ) & 63;
242
243 if ( count == 0 ) {
244 z2 = a2;
245 z1 = a1;
246 z0 = a0;
247 }
248 else {
249 if ( count < 64 ) {
250 z2 = a1<<negCount;
251 z1 = ( a0<<negCount ) | ( a1>>count );
252 z0 = a0>>count;
253 }
254 else {
255 if ( count == 64 ) {
256 z2 = a1;
257 z1 = a0;
258 }
259 else {
260 a2 |= a1;
261 if ( count < 128 ) {
262 z2 = a0<<negCount;
263 z1 = a0>>( count & 63 );
264 }
265 else {
266 z2 = ( count == 128 ) ? a0 : ( a0 != 0 );
267 z1 = 0;
268 }
269 }
270 z0 = 0;
271 }
272 z2 |= ( a2 != 0 );
273 }
274 *z2Ptr = z2;
275 *z1Ptr = z1;
276 *z0Ptr = z0;
277
278}
279
280/*
281-------------------------------------------------------------------------------
282Shifts the 128-bit value formed by concatenating `a0' and `a1' left by the
283number of bits given in `count'. Any bits shifted off are lost. The value
284of `count' must be less than 64. The result is broken into two 64-bit
285pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
286-------------------------------------------------------------------------------
287*/
288INLINE void
289 shortShift128Left(
290 bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )
291{
292
293 *z1Ptr = a1<<count;
294 *z0Ptr =
295 ( count == 0 ) ? a0 : ( a0<<count ) | ( a1>>( ( - count ) & 63 ) );
296
297}
298
299/*
300-------------------------------------------------------------------------------
301Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' left
302by the number of bits given in `count'. Any bits shifted off are lost.
303The value of `count' must be less than 64. The result is broken into three
30464-bit pieces which are stored at the locations pointed to by `z0Ptr',
305`z1Ptr', and `z2Ptr'.
306-------------------------------------------------------------------------------
307*/
308INLINE void
309 shortShift192Left(
310 bits64 a0,
311 bits64 a1,
312 bits64 a2,
313 int16 count,
314 bits64 *z0Ptr,
315 bits64 *z1Ptr,
316 bits64 *z2Ptr
317 )
318{
319 bits64 z0, z1, z2;
320 int8 negCount;
321
322 z2 = a2<<count;
323 z1 = a1<<count;
324 z0 = a0<<count;
325 if ( 0 < count ) {
326 negCount = ( ( - count ) & 63 );
327 z1 |= a2>>negCount;
328 z0 |= a1>>negCount;
329 }
330 *z2Ptr = z2;
331 *z1Ptr = z1;
332 *z0Ptr = z0;
333
334}
335
336/*
337-------------------------------------------------------------------------------
338Adds the 128-bit value formed by concatenating `a0' and `a1' to the 128-bit
339value formed by concatenating `b0' and `b1'. Addition is modulo 2^128, so
340any carry out is lost. The result is broken into two 64-bit pieces which
341are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
342-------------------------------------------------------------------------------
343*/
344INLINE void
345 add128(
346 bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )
347{
348 bits64 z1;
349
350 z1 = a1 + b1;
351 *z1Ptr = z1;
352 *z0Ptr = a0 + b0 + ( z1 < a1 );
353
354}
355
356/*
357-------------------------------------------------------------------------------
358Adds the 192-bit value formed by concatenating `a0', `a1', and `a2' to the
359192-bit value formed by concatenating `b0', `b1', and `b2'. Addition is
360modulo 2^192, so any carry out is lost. The result is broken into three
36164-bit pieces which are stored at the locations pointed to by `z0Ptr',
362`z1Ptr', and `z2Ptr'.
363-------------------------------------------------------------------------------
364*/
365INLINE void
366 add192(
367 bits64 a0,
368 bits64 a1,
369 bits64 a2,
370 bits64 b0,
371 bits64 b1,
372 bits64 b2,
373 bits64 *z0Ptr,
374 bits64 *z1Ptr,
375 bits64 *z2Ptr
376 )
377{
378 bits64 z0, z1, z2;
379 int8 carry0, carry1;
380
381 z2 = a2 + b2;
382 carry1 = ( z2 < a2 );
383 z1 = a1 + b1;
384 carry0 = ( z1 < a1 );
385 z0 = a0 + b0;
386 z1 += carry1;
387 z0 += ( z1 < carry1 );
388 z0 += carry0;
389 *z2Ptr = z2;
390 *z1Ptr = z1;
391 *z0Ptr = z0;
392
393}
394
395/*
396-------------------------------------------------------------------------------
397Subtracts the 128-bit value formed by concatenating `b0' and `b1' from the
398128-bit value formed by concatenating `a0' and `a1'. Subtraction is modulo
3992^128, so any borrow out (carry out) is lost. The result is broken into two
40064-bit pieces which are stored at the locations pointed to by `z0Ptr' and
401`z1Ptr'.
402-------------------------------------------------------------------------------
403*/
404INLINE void
405 sub128(
406 bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )
407{
408
409 *z1Ptr = a1 - b1;
410 *z0Ptr = a0 - b0 - ( a1 < b1 );
411
412}
413
414/*
415-------------------------------------------------------------------------------
416Subtracts the 192-bit value formed by concatenating `b0', `b1', and `b2'
417from the 192-bit value formed by concatenating `a0', `a1', and `a2'.
418Subtraction is modulo 2^192, so any borrow out (carry out) is lost. The
419result is broken into three 64-bit pieces which are stored at the locations
420pointed to by `z0Ptr', `z1Ptr', and `z2Ptr'.
421-------------------------------------------------------------------------------
422*/
423INLINE void
424 sub192(
425 bits64 a0,
426 bits64 a1,
427 bits64 a2,
428 bits64 b0,
429 bits64 b1,
430 bits64 b2,
431 bits64 *z0Ptr,
432 bits64 *z1Ptr,
433 bits64 *z2Ptr
434 )
435{
436 bits64 z0, z1, z2;
437 int8 borrow0, borrow1;
438
439 z2 = a2 - b2;
440 borrow1 = ( a2 < b2 );
441 z1 = a1 - b1;
442 borrow0 = ( a1 < b1 );
443 z0 = a0 - b0;
444 z0 -= ( z1 < borrow1 );
445 z1 -= borrow1;
446 z0 -= borrow0;
447 *z2Ptr = z2;
448 *z1Ptr = z1;
449 *z0Ptr = z0;
450
451}
452
453/*
454-------------------------------------------------------------------------------
455Multiplies `a' by `b' to obtain a 128-bit product. The product is broken
456into two 64-bit pieces which are stored at the locations pointed to by
457`z0Ptr' and `z1Ptr'.
458-------------------------------------------------------------------------------
459*/
460INLINE void mul64To128( bits64 a, bits64 b, bits64 *z0Ptr, bits64 *z1Ptr )
461{
462 bits32 aHigh, aLow, bHigh, bLow;
463 bits64 z0, zMiddleA, zMiddleB, z1;
464
465 aLow = a;
466 aHigh = a>>32;
467 bLow = b;
468 bHigh = b>>32;
469 z1 = ( (bits64) aLow ) * bLow;
470 zMiddleA = ( (bits64) aLow ) * bHigh;
471 zMiddleB = ( (bits64) aHigh ) * bLow;
472 z0 = ( (bits64) aHigh ) * bHigh;
473 zMiddleA += zMiddleB;
474 z0 += ( ( (bits64) ( zMiddleA < zMiddleB ) )<<32 ) + ( zMiddleA>>32 );
475 zMiddleA <<= 32;
476 z1 += zMiddleA;
477 z0 += ( z1 < zMiddleA );
478 *z1Ptr = z1;
479 *z0Ptr = z0;
480
481}
482
483/*
484-------------------------------------------------------------------------------
485Multiplies the 128-bit value formed by concatenating `a0' and `a1' by `b' to
486obtain a 192-bit product. The product is broken into three 64-bit pieces
487which are stored at the locations pointed to by `z0Ptr', `z1Ptr', and
488`z2Ptr'.
489-------------------------------------------------------------------------------
490*/
491INLINE void
492 mul128By64To192(
493 bits64 a0,
494 bits64 a1,
495 bits64 b,
496 bits64 *z0Ptr,
497 bits64 *z1Ptr,
498 bits64 *z2Ptr
499 )
500{
501 bits64 z0, z1, z2, more1;
502
503 mul64To128( a1, b, &z1, &z2 );
504 mul64To128( a0, b, &z0, &more1 );
505 add128( z0, more1, 0, z1, &z0, &z1 );
506 *z2Ptr = z2;
507 *z1Ptr = z1;
508 *z0Ptr = z0;
509
510}
511
512/*
513-------------------------------------------------------------------------------
514Multiplies the 128-bit value formed by concatenating `a0' and `a1' to the
515128-bit value formed by concatenating `b0' and `b1' to obtain a 256-bit
516product. The product is broken into four 64-bit pieces which are stored at
517the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'.
518-------------------------------------------------------------------------------
519*/
520INLINE void
521 mul128To256(
522 bits64 a0,
523 bits64 a1,
524 bits64 b0,
525 bits64 b1,
526 bits64 *z0Ptr,
527 bits64 *z1Ptr,
528 bits64 *z2Ptr,
529 bits64 *z3Ptr
530 )
531{
532 bits64 z0, z1, z2, z3;
533 bits64 more1, more2;
534
535 mul64To128( a1, b1, &z2, &z3 );
536 mul64To128( a1, b0, &z1, &more2 );
537 add128( z1, more2, 0, z2, &z1, &z2 );
538 mul64To128( a0, b0, &z0, &more1 );
539 add128( z0, more1, 0, z1, &z0, &z1 );
540 mul64To128( a0, b1, &more1, &more2 );
541 add128( more1, more2, 0, z2, &more1, &z2 );
542 add128( z0, z1, 0, more1, &z0, &z1 );
543 *z3Ptr = z3;
544 *z2Ptr = z2;
545 *z1Ptr = z1;
546 *z0Ptr = z0;
547
548}
549
550/*
551-------------------------------------------------------------------------------
552Returns an approximation to the 64-bit integer quotient obtained by dividing
553`b' into the 128-bit value formed by concatenating `a0' and `a1'. The
554divisor `b' must be at least 2^63. If q is the exact quotient truncated
555toward zero, the approximation returned lies between q and q + 2 inclusive.
556If the exact quotient q is larger than 64 bits, the maximum positive 64-bit
557unsigned integer is returned.
558-------------------------------------------------------------------------------
559*/
560static bits64 estimateDiv128To64( bits64 a0, bits64 a1, bits64 b )
561{
562 bits64 b0, b1;
563 bits64 rem0, rem1, term0, term1;
564 bits64 z;
565 if ( b <= a0 ) return LIT64( 0xFFFFFFFFFFFFFFFF );
566 b0 = b>>32;
567 z = ( b0<<32 <= a0 ) ? LIT64( 0xFFFFFFFF00000000 ) : ( a0 / b0 )<<32;
568 mul64To128( b, z, &term0, &term1 );
569 sub128( a0, a1, term0, term1, &rem0, &rem1 );
570 while ( ( (sbits64) rem0 ) < 0 ) {
571 z -= LIT64( 0x100000000 );
572 b1 = b<<32;
573 add128( rem0, rem1, b0, b1, &rem0, &rem1 );
574 }
575 rem0 = ( rem0<<32 ) | ( rem1>>32 );
576 z |= ( b0<<32 <= rem0 ) ? 0xFFFFFFFF : rem0 / b0;
577 return z;
578
579}
580
581/*
582-------------------------------------------------------------------------------
583Returns an approximation to the square root of the 32-bit significand given
584by `a'. Considered as an integer, `a' must be at least 2^31. If bit 0 of
585`aExp' (the least significant bit) is 1, the integer returned approximates
5862^31*sqrt(`a'/2^31), where `a' is considered an integer. If bit 0 of `aExp'
587is 0, the integer returned approximates 2^31*sqrt(`a'/2^30). In either
588case, the approximation returned lies strictly within +/-2 of the exact
589value.
590-------------------------------------------------------------------------------
591*/
592static bits32 estimateSqrt32( int16 aExp, bits32 a )
593{
594 static const bits16 sqrtOddAdjustments[] = {
595 0x0004, 0x0022, 0x005D, 0x00B1, 0x011D, 0x019F, 0x0236, 0x02E0,
596 0x039C, 0x0468, 0x0545, 0x0631, 0x072B, 0x0832, 0x0946, 0x0A67
597 };
598 static const bits16 sqrtEvenAdjustments[] = {
599 0x0A2D, 0x08AF, 0x075A, 0x0629, 0x051A, 0x0429, 0x0356, 0x029E,
600 0x0200, 0x0179, 0x0109, 0x00AF, 0x0068, 0x0034, 0x0012, 0x0002
601 };
602 int8 index;
603 bits32 z;
604
605 index = ( a>>27 ) & 15;
606 if ( aExp & 1 ) {
607 z = 0x4000 + ( a>>17 ) - sqrtOddAdjustments[ index ];
608 z = ( ( a / z )<<14 ) + ( z<<15 );
609 a >>= 1;
610 }
611 else {
612 z = 0x8000 + ( a>>17 ) - sqrtEvenAdjustments[ index ];
613 z = a / z + z;
614 z = ( 0x20000 <= z ) ? 0xFFFF8000 : ( z<<15 );
615 if ( z <= a ) return (bits32) ( ( (sbits32) a )>>1 );
616 }
617 return ( (bits32) ( ( ( (bits64) a )<<31 ) / z ) ) + ( z>>1 );
618
619}
620
621/*
622-------------------------------------------------------------------------------
623Returns the number of leading 0 bits before the most-significant 1 bit
624of `a'. If `a' is zero, 32 is returned.
625-------------------------------------------------------------------------------
626*/
627static int8 countLeadingZeros32( bits32 a )
628{
629 static const int8 countLeadingZerosHigh[] = {
630 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
631 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
632 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
633 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
634 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
635 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
636 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
637 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
638 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
639 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
640 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
641 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
642 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
643 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
644 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
645 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
646 };
647 int8 shiftCount;
648
649 shiftCount = 0;
650 if ( a < 0x10000 ) {
651 shiftCount += 16;
652 a <<= 16;
653 }
654 if ( a < 0x1000000 ) {
655 shiftCount += 8;
656 a <<= 8;
657 }
658 shiftCount += countLeadingZerosHigh[ a>>24 ];
659 return shiftCount;
660
661}
662
663/*
664-------------------------------------------------------------------------------
665Returns the number of leading 0 bits before the most-significant 1 bit
666of `a'. If `a' is zero, 64 is returned.
667-------------------------------------------------------------------------------
668*/
669static int8 countLeadingZeros64( bits64 a )
670{
671 int8 shiftCount;
672
673 shiftCount = 0;
674 if ( a < ( (bits64) 1 )<<32 ) {
675 shiftCount += 32;
676 }
677 else {
678 a >>= 32;
679 }
680 shiftCount += countLeadingZeros32( a );
681 return shiftCount;
682
683}
684
685/*
686-------------------------------------------------------------------------------
687Returns 1 if the 128-bit value formed by concatenating `a0' and `a1'
688is equal to the 128-bit value formed by concatenating `b0' and `b1'.
689Otherwise, returns 0.
690-------------------------------------------------------------------------------
691*/
692INLINE flag eq128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
693{
694
695 return ( a0 == b0 ) && ( a1 == b1 );
696
697}
698
699/*
700-------------------------------------------------------------------------------
701Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less
702than or equal to the 128-bit value formed by concatenating `b0' and `b1'.
703Otherwise, returns 0.
704-------------------------------------------------------------------------------
705*/
706INLINE flag le128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
707{
708
709 return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 <= b1 ) );
710
711}
712
713/*
714-------------------------------------------------------------------------------
715Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less
716than the 128-bit value formed by concatenating `b0' and `b1'. Otherwise,
717returns 0.
718-------------------------------------------------------------------------------
719*/
720INLINE flag lt128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
721{
722
723 return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 < b1 ) );
724
725}
726
727/*
728-------------------------------------------------------------------------------
729Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is
730not equal to the 128-bit value formed by concatenating `b0' and `b1'.
731Otherwise, returns 0.
732-------------------------------------------------------------------------------
733*/
734INLINE flag ne128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )
735{
736
737 return ( a0 != b0 ) || ( a1 != b1 );
738
739}
740
diff --git a/arch/arm26/nwfpe/softfloat-specialize b/arch/arm26/nwfpe/softfloat-specialize
new file mode 100644
index 000000000000..acf409144763
--- /dev/null
+++ b/arch/arm26/nwfpe/softfloat-specialize
@@ -0,0 +1,366 @@
1
2/*
3===============================================================================
4
5This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
6Arithmetic Package, Release 2.
7
8Written by John R. Hauser. This work was made possible in part by the
9International Computer Science Institute, located at Suite 600, 1947 Center
10Street, Berkeley, California 94704. Funding was partially provided by the
11National Science Foundation under grant MIP-9311980. The original version
12of this code was written as part of a project to build a fixed-point vector
13processor in collaboration with the University of California at Berkeley,
14overseen by Profs. Nelson Morgan and John Wawrzynek. More information
15is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
16arithmetic/softfloat.html'.
17
18THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
19has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
20TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
21PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
22AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
23
24Derivative works are acceptable, even for commercial purposes, so long as
25(1) they include prominent notice that the work is derivative, and (2) they
26include prominent notice akin to these three paragraphs for those parts of
27this code that are retained.
28
29===============================================================================
30*/
31
32/*
33-------------------------------------------------------------------------------
34Underflow tininess-detection mode, statically initialized to default value.
35(The declaration in `softfloat.h' must match the `int8' type here.)
36-------------------------------------------------------------------------------
37*/
38int8 float_detect_tininess = float_tininess_after_rounding;
39
40/*
41-------------------------------------------------------------------------------
42Raises the exceptions specified by `flags'. Floating-point traps can be
43defined here if desired. It is currently not possible for such a trap to
44substitute a result value. If traps are not implemented, this routine
45should be simply `float_exception_flags |= flags;'.
46
47ScottB: November 4, 1998
48Moved this function out of softfloat-specialize into fpmodule.c.
49This effectively isolates all the changes required for integrating with the
50Linux kernel into fpmodule.c. Porting to NetBSD should only require modifying
51fpmodule.c to integrate with the NetBSD kernel (I hope!).
52-------------------------------------------------------------------------------
53void float_raise( int8 flags )
54{
55 float_exception_flags |= flags;
56}
57*/
58
59/*
60-------------------------------------------------------------------------------
61Internal canonical NaN format.
62-------------------------------------------------------------------------------
63*/
64typedef struct {
65 flag sign;
66 bits64 high, low;
67} commonNaNT;
68
69/*
70-------------------------------------------------------------------------------
71The pattern for a default generated single-precision NaN.
72-------------------------------------------------------------------------------
73*/
74#define float32_default_nan 0xFFFFFFFF
75
76/*
77-------------------------------------------------------------------------------
78Returns 1 if the single-precision floating-point value `a' is a NaN;
79otherwise returns 0.
80-------------------------------------------------------------------------------
81*/
82flag float32_is_nan( float32 a )
83{
84
85 return ( 0xFF000000 < (bits32) ( a<<1 ) );
86
87}
88
89/*
90-------------------------------------------------------------------------------
91Returns 1 if the single-precision floating-point value `a' is a signaling
92NaN; otherwise returns 0.
93-------------------------------------------------------------------------------
94*/
95flag float32_is_signaling_nan( float32 a )
96{
97
98 return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
99
100}
101
102/*
103-------------------------------------------------------------------------------
104Returns the result of converting the single-precision floating-point NaN
105`a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
106exception is raised.
107-------------------------------------------------------------------------------
108*/
109static commonNaNT float32ToCommonNaN( float32 a )
110{
111 commonNaNT z;
112
113 if ( float32_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
114 z.sign = a>>31;
115 z.low = 0;
116 z.high = ( (bits64) a )<<41;
117 return z;
118
119}
120
121/*
122-------------------------------------------------------------------------------
123Returns the result of converting the canonical NaN `a' to the single-
124precision floating-point format.
125-------------------------------------------------------------------------------
126*/
127static float32 commonNaNToFloat32( commonNaNT a )
128{
129
130 return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>41 );
131
132}
133
134/*
135-------------------------------------------------------------------------------
136Takes two single-precision floating-point values `a' and `b', one of which
137is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
138signaling NaN, the invalid exception is raised.
139-------------------------------------------------------------------------------
140*/
141static float32 propagateFloat32NaN( float32 a, float32 b )
142{
143 flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
144
145 aIsNaN = float32_is_nan( a );
146 aIsSignalingNaN = float32_is_signaling_nan( a );
147 bIsNaN = float32_is_nan( b );
148 bIsSignalingNaN = float32_is_signaling_nan( b );
149 a |= 0x00400000;
150 b |= 0x00400000;
151 if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
152 if ( aIsNaN ) {
153 return ( aIsSignalingNaN & bIsNaN ) ? b : a;
154 }
155 else {
156 return b;
157 }
158
159}
160
161/*
162-------------------------------------------------------------------------------
163The pattern for a default generated double-precision NaN.
164-------------------------------------------------------------------------------
165*/
166#define float64_default_nan LIT64( 0xFFFFFFFFFFFFFFFF )
167
168/*
169-------------------------------------------------------------------------------
170Returns 1 if the double-precision floating-point value `a' is a NaN;
171otherwise returns 0.
172-------------------------------------------------------------------------------
173*/
174flag float64_is_nan( float64 a )
175{
176
177 return ( LIT64( 0xFFE0000000000000 ) < (bits64) ( a<<1 ) );
178
179}
180
181/*
182-------------------------------------------------------------------------------
183Returns 1 if the double-precision floating-point value `a' is a signaling
184NaN; otherwise returns 0.
185-------------------------------------------------------------------------------
186*/
187flag float64_is_signaling_nan( float64 a )
188{
189
190 return
191 ( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
192 && ( a & LIT64( 0x0007FFFFFFFFFFFF ) );
193
194}
195
196/*
197-------------------------------------------------------------------------------
198Returns the result of converting the double-precision floating-point NaN
199`a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
200exception is raised.
201-------------------------------------------------------------------------------
202*/
203static commonNaNT float64ToCommonNaN( float64 a )
204{
205 commonNaNT z;
206
207 if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
208 z.sign = a>>63;
209 z.low = 0;
210 z.high = a<<12;
211 return z;
212
213}
214
215/*
216-------------------------------------------------------------------------------
217Returns the result of converting the canonical NaN `a' to the double-
218precision floating-point format.
219-------------------------------------------------------------------------------
220*/
221static float64 commonNaNToFloat64( commonNaNT a )
222{
223
224 return
225 ( ( (bits64) a.sign )<<63 )
226 | LIT64( 0x7FF8000000000000 )
227 | ( a.high>>12 );
228
229}
230
231/*
232-------------------------------------------------------------------------------
233Takes two double-precision floating-point values `a' and `b', one of which
234is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
235signaling NaN, the invalid exception is raised.
236-------------------------------------------------------------------------------
237*/
238static float64 propagateFloat64NaN( float64 a, float64 b )
239{
240 flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
241
242 aIsNaN = float64_is_nan( a );
243 aIsSignalingNaN = float64_is_signaling_nan( a );
244 bIsNaN = float64_is_nan( b );
245 bIsSignalingNaN = float64_is_signaling_nan( b );
246 a |= LIT64( 0x0008000000000000 );
247 b |= LIT64( 0x0008000000000000 );
248 if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
249 if ( aIsNaN ) {
250 return ( aIsSignalingNaN & bIsNaN ) ? b : a;
251 }
252 else {
253 return b;
254 }
255
256}
257
258#ifdef FLOATX80
259
260/*
261-------------------------------------------------------------------------------
262The pattern for a default generated extended double-precision NaN. The
263`high' and `low' values hold the most- and least-significant bits,
264respectively.
265-------------------------------------------------------------------------------
266*/
267#define floatx80_default_nan_high 0xFFFF
268#define floatx80_default_nan_low LIT64( 0xFFFFFFFFFFFFFFFF )
269
270/*
271-------------------------------------------------------------------------------
272Returns 1 if the extended double-precision floating-point value `a' is a
273NaN; otherwise returns 0.
274-------------------------------------------------------------------------------
275*/
276flag floatx80_is_nan( floatx80 a )
277{
278
279 return ( ( a.high & 0x7FFF ) == 0x7FFF ) && (bits64) ( a.low<<1 );
280
281}
282
283/*
284-------------------------------------------------------------------------------
285Returns 1 if the extended double-precision floating-point value `a' is a
286signaling NaN; otherwise returns 0.
287-------------------------------------------------------------------------------
288*/
289flag floatx80_is_signaling_nan( floatx80 a )
290{
291 //register int lr;
292 bits64 aLow;
293
294 //__asm__("mov %0, lr" : : "g" (lr));
295 //fp_printk("floatx80_is_signalling_nan() called from 0x%08x\n",lr);
296 aLow = a.low & ~ LIT64( 0x4000000000000000 );
297 return
298 ( ( a.high & 0x7FFF ) == 0x7FFF )
299 && (bits64) ( aLow<<1 )
300 && ( a.low == aLow );
301
302}
303
304/*
305-------------------------------------------------------------------------------
306Returns the result of converting the extended double-precision floating-
307point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the
308invalid exception is raised.
309-------------------------------------------------------------------------------
310*/
311static commonNaNT floatx80ToCommonNaN( floatx80 a )
312{
313 commonNaNT z;
314
315 if ( floatx80_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
316 z.sign = a.high>>15;
317 z.low = 0;
318 z.high = a.low<<1;
319 return z;
320
321}
322
323/*
324-------------------------------------------------------------------------------
325Returns the result of converting the canonical NaN `a' to the extended
326double-precision floating-point format.
327-------------------------------------------------------------------------------
328*/
329static floatx80 commonNaNToFloatx80( commonNaNT a )
330{
331 floatx80 z;
332
333 z.low = LIT64( 0xC000000000000000 ) | ( a.high>>1 );
334 z.high = ( ( (bits16) a.sign )<<15 ) | 0x7FFF;
335 return z;
336
337}
338
339/*
340-------------------------------------------------------------------------------
341Takes two extended double-precision floating-point values `a' and `b', one
342of which is a NaN, and returns the appropriate NaN result. If either `a' or
343`b' is a signaling NaN, the invalid exception is raised.
344-------------------------------------------------------------------------------
345*/
346static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b )
347{
348 flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
349
350 aIsNaN = floatx80_is_nan( a );
351 aIsSignalingNaN = floatx80_is_signaling_nan( a );
352 bIsNaN = floatx80_is_nan( b );
353 bIsSignalingNaN = floatx80_is_signaling_nan( b );
354 a.low |= LIT64( 0xC000000000000000 );
355 b.low |= LIT64( 0xC000000000000000 );
356 if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
357 if ( aIsNaN ) {
358 return ( aIsSignalingNaN & bIsNaN ) ? b : a;
359 }
360 else {
361 return b;
362 }
363
364}
365
366#endif
diff --git a/arch/arm26/nwfpe/softfloat.c b/arch/arm26/nwfpe/softfloat.c
new file mode 100644
index 000000000000..26c1b916e527
--- /dev/null
+++ b/arch/arm26/nwfpe/softfloat.c
@@ -0,0 +1,3439 @@
1/*
2===============================================================================
3
4This C source file is part of the SoftFloat IEC/IEEE Floating-point
5Arithmetic Package, Release 2.
6
7Written by John R. Hauser. This work was made possible in part by the
8International Computer Science Institute, located at Suite 600, 1947 Center
9Street, Berkeley, California 94704. Funding was partially provided by the
10National Science Foundation under grant MIP-9311980. The original version
11of this code was written as part of a project to build a fixed-point vector
12processor in collaboration with the University of California at Berkeley,
13overseen by Profs. Nelson Morgan and John Wawrzynek. More information
14is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
15arithmetic/softfloat.html'.
16
17THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
18has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
19TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
20PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
21AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
22
23Derivative works are acceptable, even for commercial purposes, so long as
24(1) they include prominent notice that the work is derivative, and (2) they
25include prominent notice akin to these three paragraphs for those parts of
26this code that are retained.
27
28===============================================================================
29*/
30
31#include "fpa11.h"
32#include "milieu.h"
33#include "softfloat.h"
34
35/*
36-------------------------------------------------------------------------------
37Floating-point rounding mode, extended double-precision rounding precision,
38and exception flags.
39-------------------------------------------------------------------------------
40*/
41int8 float_rounding_mode = float_round_nearest_even;
42int8 floatx80_rounding_precision = 80;
43int8 float_exception_flags;
44
45/*
46-------------------------------------------------------------------------------
47Primitive arithmetic functions, including multi-word arithmetic, and
48division and square root approximations. (Can be specialized to target if
49desired.)
50-------------------------------------------------------------------------------
51*/
52#include "softfloat-macros"
53
54/*
55-------------------------------------------------------------------------------
56Functions and definitions to determine: (1) whether tininess for underflow
57is detected before or after rounding by default, (2) what (if anything)
58happens when exceptions are raised, (3) how signaling NaNs are distinguished
59from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs
60are propagated from function inputs to output. These details are target-
61specific.
62-------------------------------------------------------------------------------
63*/
64#include "softfloat-specialize"
65
66/*
67-------------------------------------------------------------------------------
68Takes a 64-bit fixed-point value `absZ' with binary point between bits 6
69and 7, and returns the properly rounded 32-bit integer corresponding to the
70input. If `zSign' is nonzero, the input is negated before being converted
71to an integer. Bit 63 of `absZ' must be zero. Ordinarily, the fixed-point
72input is simply rounded to an integer, with the inexact exception raised if
73the input cannot be represented exactly as an integer. If the fixed-point
74input is too large, however, the invalid exception is raised and the largest
75positive or negative integer is returned.
76-------------------------------------------------------------------------------
77*/
78static int32 roundAndPackInt32( flag zSign, bits64 absZ )
79{
80 int8 roundingMode;
81 flag roundNearestEven;
82 int8 roundIncrement, roundBits;
83 int32 z;
84
85 roundingMode = float_rounding_mode;
86 roundNearestEven = ( roundingMode == float_round_nearest_even );
87 roundIncrement = 0x40;
88 if ( ! roundNearestEven ) {
89 if ( roundingMode == float_round_to_zero ) {
90 roundIncrement = 0;
91 }
92 else {
93 roundIncrement = 0x7F;
94 if ( zSign ) {
95 if ( roundingMode == float_round_up ) roundIncrement = 0;
96 }
97 else {
98 if ( roundingMode == float_round_down ) roundIncrement = 0;
99 }
100 }
101 }
102 roundBits = absZ & 0x7F;
103 absZ = ( absZ + roundIncrement )>>7;
104 absZ &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );
105 z = absZ;
106 if ( zSign ) z = - z;
107 if ( ( absZ>>32 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) {
108 float_exception_flags |= float_flag_invalid;
109 return zSign ? 0x80000000 : 0x7FFFFFFF;
110 }
111 if ( roundBits ) float_exception_flags |= float_flag_inexact;
112 return z;
113
114}
115
116/*
117-------------------------------------------------------------------------------
118Returns the fraction bits of the single-precision floating-point value `a'.
119-------------------------------------------------------------------------------
120*/
121INLINE bits32 extractFloat32Frac( float32 a )
122{
123
124 return a & 0x007FFFFF;
125
126}
127
128/*
129-------------------------------------------------------------------------------
130Returns the exponent bits of the single-precision floating-point value `a'.
131-------------------------------------------------------------------------------
132*/
133INLINE int16 extractFloat32Exp( float32 a )
134{
135
136 return ( a>>23 ) & 0xFF;
137
138}
139
140/*
141-------------------------------------------------------------------------------
142Returns the sign bit of the single-precision floating-point value `a'.
143-------------------------------------------------------------------------------
144*/
145INLINE flag extractFloat32Sign( float32 a )
146{
147
148 return a>>31;
149
150}
151
152/*
153-------------------------------------------------------------------------------
154Normalizes the subnormal single-precision floating-point value represented
155by the denormalized significand `aSig'. The normalized exponent and
156significand are stored at the locations pointed to by `zExpPtr' and
157`zSigPtr', respectively.
158-------------------------------------------------------------------------------
159*/
160static void
161 normalizeFloat32Subnormal( bits32 aSig, int16 *zExpPtr, bits32 *zSigPtr )
162{
163 int8 shiftCount;
164
165 shiftCount = countLeadingZeros32( aSig ) - 8;
166 *zSigPtr = aSig<<shiftCount;
167 *zExpPtr = 1 - shiftCount;
168
169}
170
171/*
172-------------------------------------------------------------------------------
173Packs the sign `zSign', exponent `zExp', and significand `zSig' into a
174single-precision floating-point value, returning the result. After being
175shifted into the proper positions, the three fields are simply added
176together to form the result. This means that any integer portion of `zSig'
177will be added into the exponent. Since a properly normalized significand
178will have an integer portion equal to 1, the `zExp' input should be 1 less
179than the desired result exponent whenever `zSig' is a complete, normalized
180significand.
181-------------------------------------------------------------------------------
182*/
183INLINE float32 packFloat32( flag zSign, int16 zExp, bits32 zSig )
184{
185#if 0
186 float32 f;
187 __asm__("@ packFloat32; \n\
188 mov %0, %1, asl #31; \n\
189 orr %0, %2, asl #23; \n\
190 orr %0, %3"
191 : /* no outputs */
192 : "g" (f), "g" (zSign), "g" (zExp), "g" (zSig)
193 : "cc");
194 return f;
195#else
196 return ( ( (bits32) zSign )<<31 ) + ( ( (bits32) zExp )<<23 ) + zSig;
197#endif
198}
199
200/*
201-------------------------------------------------------------------------------
202Takes an abstract floating-point value having sign `zSign', exponent `zExp',
203and significand `zSig', and returns the proper single-precision floating-
204point value corresponding to the abstract input. Ordinarily, the abstract
205value is simply rounded and packed into the single-precision format, with
206the inexact exception raised if the abstract input cannot be represented
207exactly. If the abstract value is too large, however, the overflow and
208inexact exceptions are raised and an infinity or maximal finite value is
209returned. If the abstract value is too small, the input value is rounded to
210a subnormal number, and the underflow and inexact exceptions are raised if
211the abstract input cannot be represented exactly as a subnormal single-
212precision floating-point number.
213 The input significand `zSig' has its binary point between bits 30
214and 29, which is 7 bits to the left of the usual location. This shifted
215significand must be normalized or smaller. If `zSig' is not normalized,
216`zExp' must be 0; in that case, the result returned is a subnormal number,
217and it must not require rounding. In the usual case that `zSig' is
218normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.
219The handling of underflow and overflow follows the IEC/IEEE Standard for
220Binary Floating-point Arithmetic.
221-------------------------------------------------------------------------------
222*/
223static float32 roundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )
224{
225 int8 roundingMode;
226 flag roundNearestEven;
227 int8 roundIncrement, roundBits;
228 flag isTiny;
229
230 roundingMode = float_rounding_mode;
231 roundNearestEven = ( roundingMode == float_round_nearest_even );
232 roundIncrement = 0x40;
233 if ( ! roundNearestEven ) {
234 if ( roundingMode == float_round_to_zero ) {
235 roundIncrement = 0;
236 }
237 else {
238 roundIncrement = 0x7F;
239 if ( zSign ) {
240 if ( roundingMode == float_round_up ) roundIncrement = 0;
241 }
242 else {
243 if ( roundingMode == float_round_down ) roundIncrement = 0;
244 }
245 }
246 }
247 roundBits = zSig & 0x7F;
248 if ( 0xFD <= (bits16) zExp ) {
249 if ( ( 0xFD < zExp )
250 || ( ( zExp == 0xFD )
251 && ( (sbits32) ( zSig + roundIncrement ) < 0 ) )
252 ) {
253 float_raise( float_flag_overflow | float_flag_inexact );
254 return packFloat32( zSign, 0xFF, 0 ) - ( roundIncrement == 0 );
255 }
256 if ( zExp < 0 ) {
257 isTiny =
258 ( float_detect_tininess == float_tininess_before_rounding )
259 || ( zExp < -1 )
260 || ( zSig + roundIncrement < 0x80000000 );
261 shift32RightJamming( zSig, - zExp, &zSig );
262 zExp = 0;
263 roundBits = zSig & 0x7F;
264 if ( isTiny && roundBits ) float_raise( float_flag_underflow );
265 }
266 }
267 if ( roundBits ) float_exception_flags |= float_flag_inexact;
268 zSig = ( zSig + roundIncrement )>>7;
269 zSig &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );
270 if ( zSig == 0 ) zExp = 0;
271 return packFloat32( zSign, zExp, zSig );
272
273}
274
275/*
276-------------------------------------------------------------------------------
277Takes an abstract floating-point value having sign `zSign', exponent `zExp',
278and significand `zSig', and returns the proper single-precision floating-
279point value corresponding to the abstract input. This routine is just like
280`roundAndPackFloat32' except that `zSig' does not have to be normalized in
281any way. In all cases, `zExp' must be 1 less than the ``true'' floating-
282point exponent.
283-------------------------------------------------------------------------------
284*/
285static float32
286 normalizeRoundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )
287{
288 int8 shiftCount;
289
290 shiftCount = countLeadingZeros32( zSig ) - 1;
291 return roundAndPackFloat32( zSign, zExp - shiftCount, zSig<<shiftCount );
292
293}
294
295/*
296-------------------------------------------------------------------------------
297Returns the fraction bits of the double-precision floating-point value `a'.
298-------------------------------------------------------------------------------
299*/
300INLINE bits64 extractFloat64Frac( float64 a )
301{
302
303 return a & LIT64( 0x000FFFFFFFFFFFFF );
304
305}
306
307/*
308-------------------------------------------------------------------------------
309Returns the exponent bits of the double-precision floating-point value `a'.
310-------------------------------------------------------------------------------
311*/
312INLINE int16 extractFloat64Exp( float64 a )
313{
314
315 return ( a>>52 ) & 0x7FF;
316
317}
318
319/*
320-------------------------------------------------------------------------------
321Returns the sign bit of the double-precision floating-point value `a'.
322-------------------------------------------------------------------------------
323*/
324INLINE flag extractFloat64Sign( float64 a )
325{
326
327 return a>>63;
328
329}
330
331/*
332-------------------------------------------------------------------------------
333Normalizes the subnormal double-precision floating-point value represented
334by the denormalized significand `aSig'. The normalized exponent and
335significand are stored at the locations pointed to by `zExpPtr' and
336`zSigPtr', respectively.
337-------------------------------------------------------------------------------
338*/
339static void
340 normalizeFloat64Subnormal( bits64 aSig, int16 *zExpPtr, bits64 *zSigPtr )
341{
342 int8 shiftCount;
343
344 shiftCount = countLeadingZeros64( aSig ) - 11;
345 *zSigPtr = aSig<<shiftCount;
346 *zExpPtr = 1 - shiftCount;
347
348}
349
350/*
351-------------------------------------------------------------------------------
352Packs the sign `zSign', exponent `zExp', and significand `zSig' into a
353double-precision floating-point value, returning the result. After being
354shifted into the proper positions, the three fields are simply added
355together to form the result. This means that any integer portion of `zSig'
356will be added into the exponent. Since a properly normalized significand
357will have an integer portion equal to 1, the `zExp' input should be 1 less
358than the desired result exponent whenever `zSig' is a complete, normalized
359significand.
360-------------------------------------------------------------------------------
361*/
362INLINE float64 packFloat64( flag zSign, int16 zExp, bits64 zSig )
363{
364
365 return ( ( (bits64) zSign )<<63 ) + ( ( (bits64) zExp )<<52 ) + zSig;
366
367}
368
369/*
370-------------------------------------------------------------------------------
371Takes an abstract floating-point value having sign `zSign', exponent `zExp',
372and significand `zSig', and returns the proper double-precision floating-
373point value corresponding to the abstract input. Ordinarily, the abstract
374value is simply rounded and packed into the double-precision format, with
375the inexact exception raised if the abstract input cannot be represented
376exactly. If the abstract value is too large, however, the overflow and
377inexact exceptions are raised and an infinity or maximal finite value is
378returned. If the abstract value is too small, the input value is rounded to
379a subnormal number, and the underflow and inexact exceptions are raised if
380the abstract input cannot be represented exactly as a subnormal double-
381precision floating-point number.
382 The input significand `zSig' has its binary point between bits 62
383and 61, which is 10 bits to the left of the usual location. This shifted
384significand must be normalized or smaller. If `zSig' is not normalized,
385`zExp' must be 0; in that case, the result returned is a subnormal number,
386and it must not require rounding. In the usual case that `zSig' is
387normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.
388The handling of underflow and overflow follows the IEC/IEEE Standard for
389Binary Floating-point Arithmetic.
390-------------------------------------------------------------------------------
391*/
392static float64 roundAndPackFloat64( flag zSign, int16 zExp, bits64 zSig )
393{
394 int8 roundingMode;
395 flag roundNearestEven;
396 int16 roundIncrement, roundBits;
397 flag isTiny;
398
399 roundingMode = float_rounding_mode;
400 roundNearestEven = ( roundingMode == float_round_nearest_even );
401 roundIncrement = 0x200;
402 if ( ! roundNearestEven ) {
403 if ( roundingMode == float_round_to_zero ) {
404 roundIncrement = 0;
405 }
406 else {
407 roundIncrement = 0x3FF;
408 if ( zSign ) {
409 if ( roundingMode == float_round_up ) roundIncrement = 0;
410 }
411 else {
412 if ( roundingMode == float_round_down ) roundIncrement = 0;
413 }
414 }
415 }
416 roundBits = zSig & 0x3FF;
417 if ( 0x7FD <= (bits16) zExp ) {
418 if ( ( 0x7FD < zExp )
419 || ( ( zExp == 0x7FD )
420 && ( (sbits64) ( zSig + roundIncrement ) < 0 ) )
421 ) {
422 //register int lr = __builtin_return_address(0);
423 //printk("roundAndPackFloat64 called from 0x%08x\n",lr);
424 float_raise( float_flag_overflow | float_flag_inexact );
425 return packFloat64( zSign, 0x7FF, 0 ) - ( roundIncrement == 0 );
426 }
427 if ( zExp < 0 ) {
428 isTiny =
429 ( float_detect_tininess == float_tininess_before_rounding )
430 || ( zExp < -1 )
431 || ( zSig + roundIncrement < LIT64( 0x8000000000000000 ) );
432 shift64RightJamming( zSig, - zExp, &zSig );
433 zExp = 0;
434 roundBits = zSig & 0x3FF;
435 if ( isTiny && roundBits ) float_raise( float_flag_underflow );
436 }
437 }
438 if ( roundBits ) float_exception_flags |= float_flag_inexact;
439 zSig = ( zSig + roundIncrement )>>10;
440 zSig &= ~ ( ( ( roundBits ^ 0x200 ) == 0 ) & roundNearestEven );
441 if ( zSig == 0 ) zExp = 0;
442 return packFloat64( zSign, zExp, zSig );
443
444}
445
446/*
447-------------------------------------------------------------------------------
448Takes an abstract floating-point value having sign `zSign', exponent `zExp',
449and significand `zSig', and returns the proper double-precision floating-
450point value corresponding to the abstract input. This routine is just like
451`roundAndPackFloat64' except that `zSig' does not have to be normalized in
452any way. In all cases, `zExp' must be 1 less than the ``true'' floating-
453point exponent.
454-------------------------------------------------------------------------------
455*/
456static float64
457 normalizeRoundAndPackFloat64( flag zSign, int16 zExp, bits64 zSig )
458{
459 int8 shiftCount;
460
461 shiftCount = countLeadingZeros64( zSig ) - 1;
462 return roundAndPackFloat64( zSign, zExp - shiftCount, zSig<<shiftCount );
463
464}
465
466#ifdef FLOATX80
467
468/*
469-------------------------------------------------------------------------------
470Returns the fraction bits of the extended double-precision floating-point
471value `a'.
472-------------------------------------------------------------------------------
473*/
474INLINE bits64 extractFloatx80Frac( floatx80 a )
475{
476
477 return a.low;
478
479}
480
481/*
482-------------------------------------------------------------------------------
483Returns the exponent bits of the extended double-precision floating-point
484value `a'.
485-------------------------------------------------------------------------------
486*/
487INLINE int32 extractFloatx80Exp( floatx80 a )
488{
489
490 return a.high & 0x7FFF;
491
492}
493
494/*
495-------------------------------------------------------------------------------
496Returns the sign bit of the extended double-precision floating-point value
497`a'.
498-------------------------------------------------------------------------------
499*/
500INLINE flag extractFloatx80Sign( floatx80 a )
501{
502
503 return a.high>>15;
504
505}
506
507/*
508-------------------------------------------------------------------------------
509Normalizes the subnormal extended double-precision floating-point value
510represented by the denormalized significand `aSig'. The normalized exponent
511and significand are stored at the locations pointed to by `zExpPtr' and
512`zSigPtr', respectively.
513-------------------------------------------------------------------------------
514*/
515static void
516 normalizeFloatx80Subnormal( bits64 aSig, int32 *zExpPtr, bits64 *zSigPtr )
517{
518 int8 shiftCount;
519
520 shiftCount = countLeadingZeros64( aSig );
521 *zSigPtr = aSig<<shiftCount;
522 *zExpPtr = 1 - shiftCount;
523
524}
525
526/*
527-------------------------------------------------------------------------------
528Packs the sign `zSign', exponent `zExp', and significand `zSig' into an
529extended double-precision floating-point value, returning the result.
530-------------------------------------------------------------------------------
531*/
532INLINE floatx80 packFloatx80( flag zSign, int32 zExp, bits64 zSig )
533{
534 floatx80 z;
535
536 z.low = zSig;
537 z.high = ( ( (bits16) zSign )<<15 ) + zExp;
538 return z;
539
540}
541
542/*
543-------------------------------------------------------------------------------
544Takes an abstract floating-point value having sign `zSign', exponent `zExp',
545and extended significand formed by the concatenation of `zSig0' and `zSig1',
546and returns the proper extended double-precision floating-point value
547corresponding to the abstract input. Ordinarily, the abstract value is
548rounded and packed into the extended double-precision format, with the
549inexact exception raised if the abstract input cannot be represented
550exactly. If the abstract value is too large, however, the overflow and
551inexact exceptions are raised and an infinity or maximal finite value is
552returned. If the abstract value is too small, the input value is rounded to
553a subnormal number, and the underflow and inexact exceptions are raised if
554the abstract input cannot be represented exactly as a subnormal extended
555double-precision floating-point number.
556 If `roundingPrecision' is 32 or 64, the result is rounded to the same
557number of bits as single or double precision, respectively. Otherwise, the
558result is rounded to the full precision of the extended double-precision
559format.
560 The input significand must be normalized or smaller. If the input
561significand is not normalized, `zExp' must be 0; in that case, the result
562returned is a subnormal number, and it must not require rounding. The
563handling of underflow and overflow follows the IEC/IEEE Standard for Binary
564Floating-point Arithmetic.
565-------------------------------------------------------------------------------
566*/
567static floatx80
568 roundAndPackFloatx80(
569 int8 roundingPrecision, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1
570 )
571{
572 int8 roundingMode;
573 flag roundNearestEven, increment, isTiny;
574 int64 roundIncrement, roundMask, roundBits;
575
576 roundingMode = float_rounding_mode;
577 roundNearestEven = ( roundingMode == float_round_nearest_even );
578 if ( roundingPrecision == 80 ) goto precision80;
579 if ( roundingPrecision == 64 ) {
580 roundIncrement = LIT64( 0x0000000000000400 );
581 roundMask = LIT64( 0x00000000000007FF );
582 }
583 else if ( roundingPrecision == 32 ) {
584 roundIncrement = LIT64( 0x0000008000000000 );
585 roundMask = LIT64( 0x000000FFFFFFFFFF );
586 }
587 else {
588 goto precision80;
589 }
590 zSig0 |= ( zSig1 != 0 );
591 if ( ! roundNearestEven ) {
592 if ( roundingMode == float_round_to_zero ) {
593 roundIncrement = 0;
594 }
595 else {
596 roundIncrement = roundMask;
597 if ( zSign ) {
598 if ( roundingMode == float_round_up ) roundIncrement = 0;
599 }
600 else {
601 if ( roundingMode == float_round_down ) roundIncrement = 0;
602 }
603 }
604 }
605 roundBits = zSig0 & roundMask;
606 if ( 0x7FFD <= (bits32) ( zExp - 1 ) ) {
607 if ( ( 0x7FFE < zExp )
608 || ( ( zExp == 0x7FFE ) && ( zSig0 + roundIncrement < zSig0 ) )
609 ) {
610 goto overflow;
611 }
612 if ( zExp <= 0 ) {
613 isTiny =
614 ( float_detect_tininess == float_tininess_before_rounding )
615 || ( zExp < 0 )
616 || ( zSig0 <= zSig0 + roundIncrement );
617 shift64RightJamming( zSig0, 1 - zExp, &zSig0 );
618 zExp = 0;
619 roundBits = zSig0 & roundMask;
620 if ( isTiny && roundBits ) float_raise( float_flag_underflow );
621 if ( roundBits ) float_exception_flags |= float_flag_inexact;
622 zSig0 += roundIncrement;
623 if ( (sbits64) zSig0 < 0 ) zExp = 1;
624 roundIncrement = roundMask + 1;
625 if ( roundNearestEven && ( roundBits<<1 == roundIncrement ) ) {
626 roundMask |= roundIncrement;
627 }
628 zSig0 &= ~ roundMask;
629 return packFloatx80( zSign, zExp, zSig0 );
630 }
631 }
632 if ( roundBits ) float_exception_flags |= float_flag_inexact;
633 zSig0 += roundIncrement;
634 if ( zSig0 < roundIncrement ) {
635 ++zExp;
636 zSig0 = LIT64( 0x8000000000000000 );
637 }
638 roundIncrement = roundMask + 1;
639 if ( roundNearestEven && ( roundBits<<1 == roundIncrement ) ) {
640 roundMask |= roundIncrement;
641 }
642 zSig0 &= ~ roundMask;
643 if ( zSig0 == 0 ) zExp = 0;
644 return packFloatx80( zSign, zExp, zSig0 );
645 precision80:
646 increment = ( (sbits64) zSig1 < 0 );
647 if ( ! roundNearestEven ) {
648 if ( roundingMode == float_round_to_zero ) {
649 increment = 0;
650 }
651 else {
652 if ( zSign ) {
653 increment = ( roundingMode == float_round_down ) && zSig1;
654 }
655 else {
656 increment = ( roundingMode == float_round_up ) && zSig1;
657 }
658 }
659 }
660 if ( 0x7FFD <= (bits32) ( zExp - 1 ) ) {
661 if ( ( 0x7FFE < zExp )
662 || ( ( zExp == 0x7FFE )
663 && ( zSig0 == LIT64( 0xFFFFFFFFFFFFFFFF ) )
664 && increment
665 )
666 ) {
667 roundMask = 0;
668 overflow:
669 float_raise( float_flag_overflow | float_flag_inexact );
670 if ( ( roundingMode == float_round_to_zero )
671 || ( zSign && ( roundingMode == float_round_up ) )
672 || ( ! zSign && ( roundingMode == float_round_down ) )
673 ) {
674 return packFloatx80( zSign, 0x7FFE, ~ roundMask );
675 }
676 return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
677 }
678 if ( zExp <= 0 ) {
679 isTiny =
680 ( float_detect_tininess == float_tininess_before_rounding )
681 || ( zExp < 0 )
682 || ! increment
683 || ( zSig0 < LIT64( 0xFFFFFFFFFFFFFFFF ) );
684 shift64ExtraRightJamming( zSig0, zSig1, 1 - zExp, &zSig0, &zSig1 );
685 zExp = 0;
686 if ( isTiny && zSig1 ) float_raise( float_flag_underflow );
687 if ( zSig1 ) float_exception_flags |= float_flag_inexact;
688 if ( roundNearestEven ) {
689 increment = ( (sbits64) zSig1 < 0 );
690 }
691 else {
692 if ( zSign ) {
693 increment = ( roundingMode == float_round_down ) && zSig1;
694 }
695 else {
696 increment = ( roundingMode == float_round_up ) && zSig1;
697 }
698 }
699 if ( increment ) {
700 ++zSig0;
701 zSig0 &= ~ ( ( zSig1 + zSig1 == 0 ) & roundNearestEven );
702 if ( (sbits64) zSig0 < 0 ) zExp = 1;
703 }
704 return packFloatx80( zSign, zExp, zSig0 );
705 }
706 }
707 if ( zSig1 ) float_exception_flags |= float_flag_inexact;
708 if ( increment ) {
709 ++zSig0;
710 if ( zSig0 == 0 ) {
711 ++zExp;
712 zSig0 = LIT64( 0x8000000000000000 );
713 }
714 else {
715 zSig0 &= ~ ( ( zSig1 + zSig1 == 0 ) & roundNearestEven );
716 }
717 }
718 else {
719 if ( zSig0 == 0 ) zExp = 0;
720 }
721
722 return packFloatx80( zSign, zExp, zSig0 );
723}
724
725/*
726-------------------------------------------------------------------------------
727Takes an abstract floating-point value having sign `zSign', exponent
728`zExp', and significand formed by the concatenation of `zSig0' and `zSig1',
729and returns the proper extended double-precision floating-point value
730corresponding to the abstract input. This routine is just like
731`roundAndPackFloatx80' except that the input significand does not have to be
732normalized.
733-------------------------------------------------------------------------------
734*/
735static floatx80
736 normalizeRoundAndPackFloatx80(
737 int8 roundingPrecision, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1
738 )
739{
740 int8 shiftCount;
741
742 if ( zSig0 == 0 ) {
743 zSig0 = zSig1;
744 zSig1 = 0;
745 zExp -= 64;
746 }
747 shiftCount = countLeadingZeros64( zSig0 );
748 shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 );
749 zExp -= shiftCount;
750 return
751 roundAndPackFloatx80( roundingPrecision, zSign, zExp, zSig0, zSig1 );
752
753}
754
755#endif
756
757/*
758-------------------------------------------------------------------------------
759Returns the result of converting the 32-bit two's complement integer `a' to
760the single-precision floating-point format. The conversion is performed
761according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
762-------------------------------------------------------------------------------
763*/
764float32 int32_to_float32( int32 a )
765{
766 flag zSign;
767
768 if ( a == 0 ) return 0;
769 if ( a == 0x80000000 ) return packFloat32( 1, 0x9E, 0 );
770 zSign = ( a < 0 );
771 return normalizeRoundAndPackFloat32( zSign, 0x9C, zSign ? - a : a );
772
773}
774
775/*
776-------------------------------------------------------------------------------
777Returns the result of converting the 32-bit two's complement integer `a' to
778the double-precision floating-point format. The conversion is performed
779according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
780-------------------------------------------------------------------------------
781*/
782float64 int32_to_float64( int32 a )
783{
784 flag aSign;
785 uint32 absA;
786 int8 shiftCount;
787 bits64 zSig;
788
789 if ( a == 0 ) return 0;
790 aSign = ( a < 0 );
791 absA = aSign ? - a : a;
792 shiftCount = countLeadingZeros32( absA ) + 21;
793 zSig = absA;
794 return packFloat64( aSign, 0x432 - shiftCount, zSig<<shiftCount );
795
796}
797
798#ifdef FLOATX80
799
800/*
801-------------------------------------------------------------------------------
802Returns the result of converting the 32-bit two's complement integer `a'
803to the extended double-precision floating-point format. The conversion
804is performed according to the IEC/IEEE Standard for Binary Floating-point
805Arithmetic.
806-------------------------------------------------------------------------------
807*/
808floatx80 int32_to_floatx80( int32 a )
809{
810 flag zSign;
811 uint32 absA;
812 int8 shiftCount;
813 bits64 zSig;
814
815 if ( a == 0 ) return packFloatx80( 0, 0, 0 );
816 zSign = ( a < 0 );
817 absA = zSign ? - a : a;
818 shiftCount = countLeadingZeros32( absA ) + 32;
819 zSig = absA;
820 return packFloatx80( zSign, 0x403E - shiftCount, zSig<<shiftCount );
821
822}
823
824#endif
825
826/*
827-------------------------------------------------------------------------------
828Returns the result of converting the single-precision floating-point value
829`a' to the 32-bit two's complement integer format. The conversion is
830performed according to the IEC/IEEE Standard for Binary Floating-point
831Arithmetic---which means in particular that the conversion is rounded
832according to the current rounding mode. If `a' is a NaN, the largest
833positive integer is returned. Otherwise, if the conversion overflows, the
834largest integer with the same sign as `a' is returned.
835-------------------------------------------------------------------------------
836*/
837int32 float32_to_int32( float32 a )
838{
839 flag aSign;
840 int16 aExp, shiftCount;
841 bits32 aSig;
842 bits64 zSig;
843
844 aSig = extractFloat32Frac( a );
845 aExp = extractFloat32Exp( a );
846 aSign = extractFloat32Sign( a );
847 if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;
848 if ( aExp ) aSig |= 0x00800000;
849 shiftCount = 0xAF - aExp;
850 zSig = aSig;
851 zSig <<= 32;
852 if ( 0 < shiftCount ) shift64RightJamming( zSig, shiftCount, &zSig );
853 return roundAndPackInt32( aSign, zSig );
854
855}
856
857/*
858-------------------------------------------------------------------------------
859Returns the result of converting the single-precision floating-point value
860`a' to the 32-bit two's complement integer format. The conversion is
861performed according to the IEC/IEEE Standard for Binary Floating-point
862Arithmetic, except that the conversion is always rounded toward zero. If
863`a' is a NaN, the largest positive integer is returned. Otherwise, if the
864conversion overflows, the largest integer with the same sign as `a' is
865returned.
866-------------------------------------------------------------------------------
867*/
868int32 float32_to_int32_round_to_zero( float32 a )
869{
870 flag aSign;
871 int16 aExp, shiftCount;
872 bits32 aSig;
873 int32 z;
874
875 aSig = extractFloat32Frac( a );
876 aExp = extractFloat32Exp( a );
877 aSign = extractFloat32Sign( a );
878 shiftCount = aExp - 0x9E;
879 if ( 0 <= shiftCount ) {
880 if ( a == 0xCF000000 ) return 0x80000000;
881 float_raise( float_flag_invalid );
882 if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) return 0x7FFFFFFF;
883 return 0x80000000;
884 }
885 else if ( aExp <= 0x7E ) {
886 if ( aExp | aSig ) float_exception_flags |= float_flag_inexact;
887 return 0;
888 }
889 aSig = ( aSig | 0x00800000 )<<8;
890 z = aSig>>( - shiftCount );
891 if ( (bits32) ( aSig<<( shiftCount & 31 ) ) ) {
892 float_exception_flags |= float_flag_inexact;
893 }
894 return aSign ? - z : z;
895
896}
897
898/*
899-------------------------------------------------------------------------------
900Returns the result of converting the single-precision floating-point value
901`a' to the double-precision floating-point format. The conversion is
902performed according to the IEC/IEEE Standard for Binary Floating-point
903Arithmetic.
904-------------------------------------------------------------------------------
905*/
906float64 float32_to_float64( float32 a )
907{
908 flag aSign;
909 int16 aExp;
910 bits32 aSig;
911
912 aSig = extractFloat32Frac( a );
913 aExp = extractFloat32Exp( a );
914 aSign = extractFloat32Sign( a );
915 if ( aExp == 0xFF ) {
916 if ( aSig ) return commonNaNToFloat64( float32ToCommonNaN( a ) );
917 return packFloat64( aSign, 0x7FF, 0 );
918 }
919 if ( aExp == 0 ) {
920 if ( aSig == 0 ) return packFloat64( aSign, 0, 0 );
921 normalizeFloat32Subnormal( aSig, &aExp, &aSig );
922 --aExp;
923 }
924 return packFloat64( aSign, aExp + 0x380, ( (bits64) aSig )<<29 );
925
926}
927
928#ifdef FLOATX80
929
930/*
931-------------------------------------------------------------------------------
932Returns the result of converting the single-precision floating-point value
933`a' to the extended double-precision floating-point format. The conversion
934is performed according to the IEC/IEEE Standard for Binary Floating-point
935Arithmetic.
936-------------------------------------------------------------------------------
937*/
938floatx80 float32_to_floatx80( float32 a )
939{
940 flag aSign;
941 int16 aExp;
942 bits32 aSig;
943
944 aSig = extractFloat32Frac( a );
945 aExp = extractFloat32Exp( a );
946 aSign = extractFloat32Sign( a );
947 if ( aExp == 0xFF ) {
948 if ( aSig ) return commonNaNToFloatx80( float32ToCommonNaN( a ) );
949 return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
950 }
951 if ( aExp == 0 ) {
952 if ( aSig == 0 ) return packFloatx80( aSign, 0, 0 );
953 normalizeFloat32Subnormal( aSig, &aExp, &aSig );
954 }
955 aSig |= 0x00800000;
956 return packFloatx80( aSign, aExp + 0x3F80, ( (bits64) aSig )<<40 );
957
958}
959
960#endif
961
962/*
963-------------------------------------------------------------------------------
964Rounds the single-precision floating-point value `a' to an integer, and
965returns the result as a single-precision floating-point value. The
966operation is performed according to the IEC/IEEE Standard for Binary
967Floating-point Arithmetic.
968-------------------------------------------------------------------------------
969*/
970float32 float32_round_to_int( float32 a )
971{
972 flag aSign;
973 int16 aExp;
974 bits32 lastBitMask, roundBitsMask;
975 int8 roundingMode;
976 float32 z;
977
978 aExp = extractFloat32Exp( a );
979 if ( 0x96 <= aExp ) {
980 if ( ( aExp == 0xFF ) && extractFloat32Frac( a ) ) {
981 return propagateFloat32NaN( a, a );
982 }
983 return a;
984 }
985 if ( aExp <= 0x7E ) {
986 if ( (bits32) ( a<<1 ) == 0 ) return a;
987 float_exception_flags |= float_flag_inexact;
988 aSign = extractFloat32Sign( a );
989 switch ( float_rounding_mode ) {
990 case float_round_nearest_even:
991 if ( ( aExp == 0x7E ) && extractFloat32Frac( a ) ) {
992 return packFloat32( aSign, 0x7F, 0 );
993 }
994 break;
995 case float_round_down:
996 return aSign ? 0xBF800000 : 0;
997 case float_round_up:
998 return aSign ? 0x80000000 : 0x3F800000;
999 }
1000 return packFloat32( aSign, 0, 0 );
1001 }
1002 lastBitMask = 1;
1003 lastBitMask <<= 0x96 - aExp;
1004 roundBitsMask = lastBitMask - 1;
1005 z = a;
1006 roundingMode = float_rounding_mode;
1007 if ( roundingMode == float_round_nearest_even ) {
1008 z += lastBitMask>>1;
1009 if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask;
1010 }
1011 else if ( roundingMode != float_round_to_zero ) {
1012 if ( extractFloat32Sign( z ) ^ ( roundingMode == float_round_up ) ) {
1013 z += roundBitsMask;
1014 }
1015 }
1016 z &= ~ roundBitsMask;
1017 if ( z != a ) float_exception_flags |= float_flag_inexact;
1018 return z;
1019
1020}
1021
1022/*
1023-------------------------------------------------------------------------------
1024Returns the result of adding the absolute values of the single-precision
1025floating-point values `a' and `b'. If `zSign' is true, the sum is negated
1026before being returned. `zSign' is ignored if the result is a NaN. The
1027addition is performed according to the IEC/IEEE Standard for Binary
1028Floating-point Arithmetic.
1029-------------------------------------------------------------------------------
1030*/
1031static float32 addFloat32Sigs( float32 a, float32 b, flag zSign )
1032{
1033 int16 aExp, bExp, zExp;
1034 bits32 aSig, bSig, zSig;
1035 int16 expDiff;
1036
1037 aSig = extractFloat32Frac( a );
1038 aExp = extractFloat32Exp( a );
1039 bSig = extractFloat32Frac( b );
1040 bExp = extractFloat32Exp( b );
1041 expDiff = aExp - bExp;
1042 aSig <<= 6;
1043 bSig <<= 6;
1044 if ( 0 < expDiff ) {
1045 if ( aExp == 0xFF ) {
1046 if ( aSig ) return propagateFloat32NaN( a, b );
1047 return a;
1048 }
1049 if ( bExp == 0 ) {
1050 --expDiff;
1051 }
1052 else {
1053 bSig |= 0x20000000;
1054 }
1055 shift32RightJamming( bSig, expDiff, &bSig );
1056 zExp = aExp;
1057 }
1058 else if ( expDiff < 0 ) {
1059 if ( bExp == 0xFF ) {
1060 if ( bSig ) return propagateFloat32NaN( a, b );
1061 return packFloat32( zSign, 0xFF, 0 );
1062 }
1063 if ( aExp == 0 ) {
1064 ++expDiff;
1065 }
1066 else {
1067 aSig |= 0x20000000;
1068 }
1069 shift32RightJamming( aSig, - expDiff, &aSig );
1070 zExp = bExp;
1071 }
1072 else {
1073 if ( aExp == 0xFF ) {
1074 if ( aSig | bSig ) return propagateFloat32NaN( a, b );
1075 return a;
1076 }
1077 if ( aExp == 0 ) return packFloat32( zSign, 0, ( aSig + bSig )>>6 );
1078 zSig = 0x40000000 + aSig + bSig;
1079 zExp = aExp;
1080 goto roundAndPack;
1081 }
1082 aSig |= 0x20000000;
1083 zSig = ( aSig + bSig )<<1;
1084 --zExp;
1085 if ( (sbits32) zSig < 0 ) {
1086 zSig = aSig + bSig;
1087 ++zExp;
1088 }
1089 roundAndPack:
1090 return roundAndPackFloat32( zSign, zExp, zSig );
1091
1092}
1093
1094/*
1095-------------------------------------------------------------------------------
1096Returns the result of subtracting the absolute values of the single-
1097precision floating-point values `a' and `b'. If `zSign' is true, the
1098difference is negated before being returned. `zSign' is ignored if the
1099result is a NaN. The subtraction is performed according to the IEC/IEEE
1100Standard for Binary Floating-point Arithmetic.
1101-------------------------------------------------------------------------------
1102*/
1103static float32 subFloat32Sigs( float32 a, float32 b, flag zSign )
1104{
1105 int16 aExp, bExp, zExp;
1106 bits32 aSig, bSig, zSig;
1107 int16 expDiff;
1108
1109 aSig = extractFloat32Frac( a );
1110 aExp = extractFloat32Exp( a );
1111 bSig = extractFloat32Frac( b );
1112 bExp = extractFloat32Exp( b );
1113 expDiff = aExp - bExp;
1114 aSig <<= 7;
1115 bSig <<= 7;
1116 if ( 0 < expDiff ) goto aExpBigger;
1117 if ( expDiff < 0 ) goto bExpBigger;
1118 if ( aExp == 0xFF ) {
1119 if ( aSig | bSig ) return propagateFloat32NaN( a, b );
1120 float_raise( float_flag_invalid );
1121 return float32_default_nan;
1122 }
1123 if ( aExp == 0 ) {
1124 aExp = 1;
1125 bExp = 1;
1126 }
1127 if ( bSig < aSig ) goto aBigger;
1128 if ( aSig < bSig ) goto bBigger;
1129 return packFloat32( float_rounding_mode == float_round_down, 0, 0 );
1130 bExpBigger:
1131 if ( bExp == 0xFF ) {
1132 if ( bSig ) return propagateFloat32NaN( a, b );
1133 return packFloat32( zSign ^ 1, 0xFF, 0 );
1134 }
1135 if ( aExp == 0 ) {
1136 ++expDiff;
1137 }
1138 else {
1139 aSig |= 0x40000000;
1140 }
1141 shift32RightJamming( aSig, - expDiff, &aSig );
1142 bSig |= 0x40000000;
1143 bBigger:
1144 zSig = bSig - aSig;
1145 zExp = bExp;
1146 zSign ^= 1;
1147 goto normalizeRoundAndPack;
1148 aExpBigger:
1149 if ( aExp == 0xFF ) {
1150 if ( aSig ) return propagateFloat32NaN( a, b );
1151 return a;
1152 }
1153 if ( bExp == 0 ) {
1154 --expDiff;
1155 }
1156 else {
1157 bSig |= 0x40000000;
1158 }
1159 shift32RightJamming( bSig, expDiff, &bSig );
1160 aSig |= 0x40000000;
1161 aBigger:
1162 zSig = aSig - bSig;
1163 zExp = aExp;
1164 normalizeRoundAndPack:
1165 --zExp;
1166 return normalizeRoundAndPackFloat32( zSign, zExp, zSig );
1167
1168}
1169
1170/*
1171-------------------------------------------------------------------------------
1172Returns the result of adding the single-precision floating-point values `a'
1173and `b'. The operation is performed according to the IEC/IEEE Standard for
1174Binary Floating-point Arithmetic.
1175-------------------------------------------------------------------------------
1176*/
1177float32 float32_add( float32 a, float32 b )
1178{
1179 flag aSign, bSign;
1180
1181 aSign = extractFloat32Sign( a );
1182 bSign = extractFloat32Sign( b );
1183 if ( aSign == bSign ) {
1184 return addFloat32Sigs( a, b, aSign );
1185 }
1186 else {
1187 return subFloat32Sigs( a, b, aSign );
1188 }
1189
1190}
1191
1192/*
1193-------------------------------------------------------------------------------
1194Returns the result of subtracting the single-precision floating-point values
1195`a' and `b'. The operation is performed according to the IEC/IEEE Standard
1196for Binary Floating-point Arithmetic.
1197-------------------------------------------------------------------------------
1198*/
1199float32 float32_sub( float32 a, float32 b )
1200{
1201 flag aSign, bSign;
1202
1203 aSign = extractFloat32Sign( a );
1204 bSign = extractFloat32Sign( b );
1205 if ( aSign == bSign ) {
1206 return subFloat32Sigs( a, b, aSign );
1207 }
1208 else {
1209 return addFloat32Sigs( a, b, aSign );
1210 }
1211
1212}
1213
1214/*
1215-------------------------------------------------------------------------------
1216Returns the result of multiplying the single-precision floating-point values
1217`a' and `b'. The operation is performed according to the IEC/IEEE Standard
1218for Binary Floating-point Arithmetic.
1219-------------------------------------------------------------------------------
1220*/
1221float32 float32_mul( float32 a, float32 b )
1222{
1223 flag aSign, bSign, zSign;
1224 int16 aExp, bExp, zExp;
1225 bits32 aSig, bSig;
1226 bits64 zSig64;
1227 bits32 zSig;
1228
1229 aSig = extractFloat32Frac( a );
1230 aExp = extractFloat32Exp( a );
1231 aSign = extractFloat32Sign( a );
1232 bSig = extractFloat32Frac( b );
1233 bExp = extractFloat32Exp( b );
1234 bSign = extractFloat32Sign( b );
1235 zSign = aSign ^ bSign;
1236 if ( aExp == 0xFF ) {
1237 if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {
1238 return propagateFloat32NaN( a, b );
1239 }
1240 if ( ( bExp | bSig ) == 0 ) {
1241 float_raise( float_flag_invalid );
1242 return float32_default_nan;
1243 }
1244 return packFloat32( zSign, 0xFF, 0 );
1245 }
1246 if ( bExp == 0xFF ) {
1247 if ( bSig ) return propagateFloat32NaN( a, b );
1248 if ( ( aExp | aSig ) == 0 ) {
1249 float_raise( float_flag_invalid );
1250 return float32_default_nan;
1251 }
1252 return packFloat32( zSign, 0xFF, 0 );
1253 }
1254 if ( aExp == 0 ) {
1255 if ( aSig == 0 ) return packFloat32( zSign, 0, 0 );
1256 normalizeFloat32Subnormal( aSig, &aExp, &aSig );
1257 }
1258 if ( bExp == 0 ) {
1259 if ( bSig == 0 ) return packFloat32( zSign, 0, 0 );
1260 normalizeFloat32Subnormal( bSig, &bExp, &bSig );
1261 }
1262 zExp = aExp + bExp - 0x7F;
1263 aSig = ( aSig | 0x00800000 )<<7;
1264 bSig = ( bSig | 0x00800000 )<<8;
1265 shift64RightJamming( ( (bits64) aSig ) * bSig, 32, &zSig64 );
1266 zSig = zSig64;
1267 if ( 0 <= (sbits32) ( zSig<<1 ) ) {
1268 zSig <<= 1;
1269 --zExp;
1270 }
1271 return roundAndPackFloat32( zSign, zExp, zSig );
1272
1273}
1274
1275/*
1276-------------------------------------------------------------------------------
1277Returns the result of dividing the single-precision floating-point value `a'
1278by the corresponding value `b'. The operation is performed according to the
1279IEC/IEEE Standard for Binary Floating-point Arithmetic.
1280-------------------------------------------------------------------------------
1281*/
1282float32 float32_div( float32 a, float32 b )
1283{
1284 flag aSign, bSign, zSign;
1285 int16 aExp, bExp, zExp;
1286 bits32 aSig, bSig, zSig;
1287
1288 aSig = extractFloat32Frac( a );
1289 aExp = extractFloat32Exp( a );
1290 aSign = extractFloat32Sign( a );
1291 bSig = extractFloat32Frac( b );
1292 bExp = extractFloat32Exp( b );
1293 bSign = extractFloat32Sign( b );
1294 zSign = aSign ^ bSign;
1295 if ( aExp == 0xFF ) {
1296 if ( aSig ) return propagateFloat32NaN( a, b );
1297 if ( bExp == 0xFF ) {
1298 if ( bSig ) return propagateFloat32NaN( a, b );
1299 float_raise( float_flag_invalid );
1300 return float32_default_nan;
1301 }
1302 return packFloat32( zSign, 0xFF, 0 );
1303 }
1304 if ( bExp == 0xFF ) {
1305 if ( bSig ) return propagateFloat32NaN( a, b );
1306 return packFloat32( zSign, 0, 0 );
1307 }
1308 if ( bExp == 0 ) {
1309 if ( bSig == 0 ) {
1310 if ( ( aExp | aSig ) == 0 ) {
1311 float_raise( float_flag_invalid );
1312 return float32_default_nan;
1313 }
1314 float_raise( float_flag_divbyzero );
1315 return packFloat32( zSign, 0xFF, 0 );
1316 }
1317 normalizeFloat32Subnormal( bSig, &bExp, &bSig );
1318 }
1319 if ( aExp == 0 ) {
1320 if ( aSig == 0 ) return packFloat32( zSign, 0, 0 );
1321 normalizeFloat32Subnormal( aSig, &aExp, &aSig );
1322 }
1323 zExp = aExp - bExp + 0x7D;
1324 aSig = ( aSig | 0x00800000 )<<7;
1325 bSig = ( bSig | 0x00800000 )<<8;
1326 if ( bSig <= ( aSig + aSig ) ) {
1327 aSig >>= 1;
1328 ++zExp;
1329 }
1330 zSig = ( ( (bits64) aSig )<<32 ) / bSig;
1331 if ( ( zSig & 0x3F ) == 0 ) {
1332 zSig |= ( ( (bits64) bSig ) * zSig != ( (bits64) aSig )<<32 );
1333 }
1334 return roundAndPackFloat32( zSign, zExp, zSig );
1335
1336}
1337
1338/*
1339-------------------------------------------------------------------------------
1340Returns the remainder of the single-precision floating-point value `a'
1341with respect to the corresponding value `b'. The operation is performed
1342according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
1343-------------------------------------------------------------------------------
1344*/
1345float32 float32_rem( float32 a, float32 b )
1346{
1347 flag aSign, bSign, zSign;
1348 int16 aExp, bExp, expDiff;
1349 bits32 aSig, bSig;
1350 bits32 q;
1351 bits64 aSig64, bSig64, q64;
1352 bits32 alternateASig;
1353 sbits32 sigMean;
1354
1355 aSig = extractFloat32Frac( a );
1356 aExp = extractFloat32Exp( a );
1357 aSign = extractFloat32Sign( a );
1358 bSig = extractFloat32Frac( b );
1359 bExp = extractFloat32Exp( b );
1360 bSign = extractFloat32Sign( b );
1361 if ( aExp == 0xFF ) {
1362 if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {
1363 return propagateFloat32NaN( a, b );
1364 }
1365 float_raise( float_flag_invalid );
1366 return float32_default_nan;
1367 }
1368 if ( bExp == 0xFF ) {
1369 if ( bSig ) return propagateFloat32NaN( a, b );
1370 return a;
1371 }
1372 if ( bExp == 0 ) {
1373 if ( bSig == 0 ) {
1374 float_raise( float_flag_invalid );
1375 return float32_default_nan;
1376 }
1377 normalizeFloat32Subnormal( bSig, &bExp, &bSig );
1378 }
1379 if ( aExp == 0 ) {
1380 if ( aSig == 0 ) return a;
1381 normalizeFloat32Subnormal( aSig, &aExp, &aSig );
1382 }
1383 expDiff = aExp - bExp;
1384 aSig |= 0x00800000;
1385 bSig |= 0x00800000;
1386 if ( expDiff < 32 ) {
1387 aSig <<= 8;
1388 bSig <<= 8;
1389 if ( expDiff < 0 ) {
1390 if ( expDiff < -1 ) return a;
1391 aSig >>= 1;
1392 }
1393 q = ( bSig <= aSig );
1394 if ( q ) aSig -= bSig;
1395 if ( 0 < expDiff ) {
1396 q = ( ( (bits64) aSig )<<32 ) / bSig;
1397 q >>= 32 - expDiff;
1398 bSig >>= 2;
1399 aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q;
1400 }
1401 else {
1402 aSig >>= 2;
1403 bSig >>= 2;
1404 }
1405 }
1406 else {
1407 if ( bSig <= aSig ) aSig -= bSig;
1408 aSig64 = ( (bits64) aSig )<<40;
1409 bSig64 = ( (bits64) bSig )<<40;
1410 expDiff -= 64;
1411 while ( 0 < expDiff ) {
1412 q64 = estimateDiv128To64( aSig64, 0, bSig64 );
1413 q64 = ( 2 < q64 ) ? q64 - 2 : 0;
1414 aSig64 = - ( ( bSig * q64 )<<38 );
1415 expDiff -= 62;
1416 }
1417 expDiff += 64;
1418 q64 = estimateDiv128To64( aSig64, 0, bSig64 );
1419 q64 = ( 2 < q64 ) ? q64 - 2 : 0;
1420 q = q64>>( 64 - expDiff );
1421 bSig <<= 6;
1422 aSig = ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q;
1423 }
1424 do {
1425 alternateASig = aSig;
1426 ++q;
1427 aSig -= bSig;
1428 } while ( 0 <= (sbits32) aSig );
1429 sigMean = aSig + alternateASig;
1430 if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) {
1431 aSig = alternateASig;
1432 }
1433 zSign = ( (sbits32) aSig < 0 );
1434 if ( zSign ) aSig = - aSig;
1435 return normalizeRoundAndPackFloat32( aSign ^ zSign, bExp, aSig );
1436
1437}
1438
1439/*
1440-------------------------------------------------------------------------------
1441Returns the square root of the single-precision floating-point value `a'.
1442The operation is performed according to the IEC/IEEE Standard for Binary
1443Floating-point Arithmetic.
1444-------------------------------------------------------------------------------
1445*/
1446float32 float32_sqrt( float32 a )
1447{
1448 flag aSign;
1449 int16 aExp, zExp;
1450 bits32 aSig, zSig;
1451 bits64 rem, term;
1452
1453 aSig = extractFloat32Frac( a );
1454 aExp = extractFloat32Exp( a );
1455 aSign = extractFloat32Sign( a );
1456 if ( aExp == 0xFF ) {
1457 if ( aSig ) return propagateFloat32NaN( a, 0 );
1458 if ( ! aSign ) return a;
1459 float_raise( float_flag_invalid );
1460 return float32_default_nan;
1461 }
1462 if ( aSign ) {
1463 if ( ( aExp | aSig ) == 0 ) return a;
1464 float_raise( float_flag_invalid );
1465 return float32_default_nan;
1466 }
1467 if ( aExp == 0 ) {
1468 if ( aSig == 0 ) return 0;
1469 normalizeFloat32Subnormal( aSig, &aExp, &aSig );
1470 }
1471 zExp = ( ( aExp - 0x7F )>>1 ) + 0x7E;
1472 aSig = ( aSig | 0x00800000 )<<8;
1473 zSig = estimateSqrt32( aExp, aSig ) + 2;
1474 if ( ( zSig & 0x7F ) <= 5 ) {
1475 if ( zSig < 2 ) {
1476 zSig = 0xFFFFFFFF;
1477 }
1478 else {
1479 aSig >>= aExp & 1;
1480 term = ( (bits64) zSig ) * zSig;
1481 rem = ( ( (bits64) aSig )<<32 ) - term;
1482 while ( (sbits64) rem < 0 ) {
1483 --zSig;
1484 rem += ( ( (bits64) zSig )<<1 ) | 1;
1485 }
1486 zSig |= ( rem != 0 );
1487 }
1488 }
1489 shift32RightJamming( zSig, 1, &zSig );
1490 return roundAndPackFloat32( 0, zExp, zSig );
1491
1492}
1493
1494/*
1495-------------------------------------------------------------------------------
1496Returns 1 if the single-precision floating-point value `a' is equal to the
1497corresponding value `b', and 0 otherwise. The comparison is performed
1498according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
1499-------------------------------------------------------------------------------
1500*/
1501flag float32_eq( float32 a, float32 b )
1502{
1503
1504 if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
1505 || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
1506 ) {
1507 if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
1508 float_raise( float_flag_invalid );
1509 }
1510 return 0;
1511 }
1512 return ( a == b ) || ( (bits32) ( ( a | b )<<1 ) == 0 );
1513
1514}
1515
1516/*
1517-------------------------------------------------------------------------------
1518Returns 1 if the single-precision floating-point value `a' is less than or
1519equal to the corresponding value `b', and 0 otherwise. The comparison is
1520performed according to the IEC/IEEE Standard for Binary Floating-point
1521Arithmetic.
1522-------------------------------------------------------------------------------
1523*/
1524flag float32_le( float32 a, float32 b )
1525{
1526 flag aSign, bSign;
1527
1528 if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
1529 || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
1530 ) {
1531 float_raise( float_flag_invalid );
1532 return 0;
1533 }
1534 aSign = extractFloat32Sign( a );
1535 bSign = extractFloat32Sign( b );
1536 if ( aSign != bSign ) return aSign || ( (bits32) ( ( a | b )<<1 ) == 0 );
1537 return ( a == b ) || ( aSign ^ ( a < b ) );
1538
1539}
1540
1541/*
1542-------------------------------------------------------------------------------
1543Returns 1 if the single-precision floating-point value `a' is less than
1544the corresponding value `b', and 0 otherwise. The comparison is performed
1545according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
1546-------------------------------------------------------------------------------
1547*/
1548flag float32_lt( float32 a, float32 b )
1549{
1550 flag aSign, bSign;
1551
1552 if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
1553 || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
1554 ) {
1555 float_raise( float_flag_invalid );
1556 return 0;
1557 }
1558 aSign = extractFloat32Sign( a );
1559 bSign = extractFloat32Sign( b );
1560 if ( aSign != bSign ) return aSign && ( (bits32) ( ( a | b )<<1 ) != 0 );
1561 return ( a != b ) && ( aSign ^ ( a < b ) );
1562
1563}
1564
1565/*
1566-------------------------------------------------------------------------------
1567Returns 1 if the single-precision floating-point value `a' is equal to the
1568corresponding value `b', and 0 otherwise. The invalid exception is raised
1569if either operand is a NaN. Otherwise, the comparison is performed
1570according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
1571-------------------------------------------------------------------------------
1572*/
1573flag float32_eq_signaling( float32 a, float32 b )
1574{
1575
1576 if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
1577 || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
1578 ) {
1579 float_raise( float_flag_invalid );
1580 return 0;
1581 }
1582 return ( a == b ) || ( (bits32) ( ( a | b )<<1 ) == 0 );
1583
1584}
1585
1586/*
1587-------------------------------------------------------------------------------
1588Returns 1 if the single-precision floating-point value `a' is less than or
1589equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not
1590cause an exception. Otherwise, the comparison is performed according to the
1591IEC/IEEE Standard for Binary Floating-point Arithmetic.
1592-------------------------------------------------------------------------------
1593*/
1594flag float32_le_quiet( float32 a, float32 b )
1595{
1596 flag aSign, bSign;
1597 //int16 aExp, bExp;
1598
1599 if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
1600 || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
1601 ) {
1602 if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
1603 float_raise( float_flag_invalid );
1604 }
1605 return 0;
1606 }
1607 aSign = extractFloat32Sign( a );
1608 bSign = extractFloat32Sign( b );
1609 if ( aSign != bSign ) return aSign || ( (bits32) ( ( a | b )<<1 ) == 0 );
1610 return ( a == b ) || ( aSign ^ ( a < b ) );
1611
1612}
1613
1614/*
1615-------------------------------------------------------------------------------
1616Returns 1 if the single-precision floating-point value `a' is less than
1617the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
1618exception. Otherwise, the comparison is performed according to the IEC/IEEE
1619Standard for Binary Floating-point Arithmetic.
1620-------------------------------------------------------------------------------
1621*/
1622flag float32_lt_quiet( float32 a, float32 b )
1623{
1624 flag aSign, bSign;
1625
1626 if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
1627 || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
1628 ) {
1629 if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
1630 float_raise( float_flag_invalid );
1631 }
1632 return 0;
1633 }
1634 aSign = extractFloat32Sign( a );
1635 bSign = extractFloat32Sign( b );
1636 if ( aSign != bSign ) return aSign && ( (bits32) ( ( a | b )<<1 ) != 0 );
1637 return ( a != b ) && ( aSign ^ ( a < b ) );
1638
1639}
1640
1641/*
1642-------------------------------------------------------------------------------
1643Returns the result of converting the double-precision floating-point value
1644`a' to the 32-bit two's complement integer format. The conversion is
1645performed according to the IEC/IEEE Standard for Binary Floating-point
1646Arithmetic---which means in particular that the conversion is rounded
1647according to the current rounding mode. If `a' is a NaN, the largest
1648positive integer is returned. Otherwise, if the conversion overflows, the
1649largest integer with the same sign as `a' is returned.
1650-------------------------------------------------------------------------------
1651*/
1652int32 float64_to_int32( float64 a )
1653{
1654 flag aSign;
1655 int16 aExp, shiftCount;
1656 bits64 aSig;
1657
1658 aSig = extractFloat64Frac( a );
1659 aExp = extractFloat64Exp( a );
1660 aSign = extractFloat64Sign( a );
1661 if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;
1662 if ( aExp ) aSig |= LIT64( 0x0010000000000000 );
1663 shiftCount = 0x42C - aExp;
1664 if ( 0 < shiftCount ) shift64RightJamming( aSig, shiftCount, &aSig );
1665 return roundAndPackInt32( aSign, aSig );
1666
1667}
1668
1669/*
1670-------------------------------------------------------------------------------
1671Returns the result of converting the double-precision floating-point value
1672`a' to the 32-bit two's complement integer format. The conversion is
1673performed according to the IEC/IEEE Standard for Binary Floating-point
1674Arithmetic, except that the conversion is always rounded toward zero. If
1675`a' is a NaN, the largest positive integer is returned. Otherwise, if the
1676conversion overflows, the largest integer with the same sign as `a' is
1677returned.
1678-------------------------------------------------------------------------------
1679*/
1680int32 float64_to_int32_round_to_zero( float64 a )
1681{
1682 flag aSign;
1683 int16 aExp, shiftCount;
1684 bits64 aSig, savedASig;
1685 int32 z;
1686
1687 aSig = extractFloat64Frac( a );
1688 aExp = extractFloat64Exp( a );
1689 aSign = extractFloat64Sign( a );
1690 shiftCount = 0x433 - aExp;
1691 if ( shiftCount < 21 ) {
1692 if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;
1693 goto invalid;
1694 }
1695 else if ( 52 < shiftCount ) {
1696 if ( aExp || aSig ) float_exception_flags |= float_flag_inexact;
1697 return 0;
1698 }
1699 aSig |= LIT64( 0x0010000000000000 );
1700 savedASig = aSig;
1701 aSig >>= shiftCount;
1702 z = aSig;
1703 if ( aSign ) z = - z;
1704 if ( ( z < 0 ) ^ aSign ) {
1705 invalid:
1706 float_exception_flags |= float_flag_invalid;
1707 return aSign ? 0x80000000 : 0x7FFFFFFF;
1708 }
1709 if ( ( aSig<<shiftCount ) != savedASig ) {
1710 float_exception_flags |= float_flag_inexact;
1711 }
1712 return z;
1713
1714}
1715
1716/*
1717-------------------------------------------------------------------------------
1718Returns the result of converting the double-precision floating-point value
1719`a' to the 32-bit two's complement unsigned integer format. The conversion
1720is performed according to the IEC/IEEE Standard for Binary Floating-point
1721Arithmetic---which means in particular that the conversion is rounded
1722according to the current rounding mode. If `a' is a NaN, the largest
1723positive integer is returned. Otherwise, if the conversion overflows, the
1724largest positive integer is returned.
1725-------------------------------------------------------------------------------
1726*/
1727int32 float64_to_uint32( float64 a )
1728{
1729 flag aSign;
1730 int16 aExp, shiftCount;
1731 bits64 aSig;
1732
1733 aSig = extractFloat64Frac( a );
1734 aExp = extractFloat64Exp( a );
1735 aSign = 0; //extractFloat64Sign( a );
1736 //if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;
1737 if ( aExp ) aSig |= LIT64( 0x0010000000000000 );
1738 shiftCount = 0x42C - aExp;
1739 if ( 0 < shiftCount ) shift64RightJamming( aSig, shiftCount, &aSig );
1740 return roundAndPackInt32( aSign, aSig );
1741}
1742
1743/*
1744-------------------------------------------------------------------------------
1745Returns the result of converting the double-precision floating-point value
1746`a' to the 32-bit two's complement integer format. The conversion is
1747performed according to the IEC/IEEE Standard for Binary Floating-point
1748Arithmetic, except that the conversion is always rounded toward zero. If
1749`a' is a NaN, the largest positive integer is returned. Otherwise, if the
1750conversion overflows, the largest positive integer is returned.
1751-------------------------------------------------------------------------------
1752*/
1753int32 float64_to_uint32_round_to_zero( float64 a )
1754{
1755 flag aSign;
1756 int16 aExp, shiftCount;
1757 bits64 aSig, savedASig;
1758 int32 z;
1759
1760 aSig = extractFloat64Frac( a );
1761 aExp = extractFloat64Exp( a );
1762 aSign = extractFloat64Sign( a );
1763 shiftCount = 0x433 - aExp;
1764 if ( shiftCount < 21 ) {
1765 if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;
1766 goto invalid;
1767 }
1768 else if ( 52 < shiftCount ) {
1769 if ( aExp || aSig ) float_exception_flags |= float_flag_inexact;
1770 return 0;
1771 }
1772 aSig |= LIT64( 0x0010000000000000 );
1773 savedASig = aSig;
1774 aSig >>= shiftCount;
1775 z = aSig;
1776 if ( aSign ) z = - z;
1777 if ( ( z < 0 ) ^ aSign ) {
1778 invalid:
1779 float_exception_flags |= float_flag_invalid;
1780 return aSign ? 0x80000000 : 0x7FFFFFFF;
1781 }
1782 if ( ( aSig<<shiftCount ) != savedASig ) {
1783 float_exception_flags |= float_flag_inexact;
1784 }
1785 return z;
1786}
1787
1788/*
1789-------------------------------------------------------------------------------
1790Returns the result of converting the double-precision floating-point value
1791`a' to the single-precision floating-point format. The conversion is
1792performed according to the IEC/IEEE Standard for Binary Floating-point
1793Arithmetic.
1794-------------------------------------------------------------------------------
1795*/
1796float32 float64_to_float32( float64 a )
1797{
1798 flag aSign;
1799 int16 aExp;
1800 bits64 aSig;
1801 bits32 zSig;
1802
1803 aSig = extractFloat64Frac( a );
1804 aExp = extractFloat64Exp( a );
1805 aSign = extractFloat64Sign( a );
1806 if ( aExp == 0x7FF ) {
1807 if ( aSig ) return commonNaNToFloat32( float64ToCommonNaN( a ) );
1808 return packFloat32( aSign, 0xFF, 0 );
1809 }
1810 shift64RightJamming( aSig, 22, &aSig );
1811 zSig = aSig;
1812 if ( aExp || zSig ) {
1813 zSig |= 0x40000000;
1814 aExp -= 0x381;
1815 }
1816 return roundAndPackFloat32( aSign, aExp, zSig );
1817
1818}
1819
1820#ifdef FLOATX80
1821
1822/*
1823-------------------------------------------------------------------------------
1824Returns the result of converting the double-precision floating-point value
1825`a' to the extended double-precision floating-point format. The conversion
1826is performed according to the IEC/IEEE Standard for Binary Floating-point
1827Arithmetic.
1828-------------------------------------------------------------------------------
1829*/
1830floatx80 float64_to_floatx80( float64 a )
1831{
1832 flag aSign;
1833 int16 aExp;
1834 bits64 aSig;
1835
1836 aSig = extractFloat64Frac( a );
1837 aExp = extractFloat64Exp( a );
1838 aSign = extractFloat64Sign( a );
1839 if ( aExp == 0x7FF ) {
1840 if ( aSig ) return commonNaNToFloatx80( float64ToCommonNaN( a ) );
1841 return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
1842 }
1843 if ( aExp == 0 ) {
1844 if ( aSig == 0 ) return packFloatx80( aSign, 0, 0 );
1845 normalizeFloat64Subnormal( aSig, &aExp, &aSig );
1846 }
1847 return
1848 packFloatx80(
1849 aSign, aExp + 0x3C00, ( aSig | LIT64( 0x0010000000000000 ) )<<11 );
1850
1851}
1852
1853#endif
1854
1855/*
1856-------------------------------------------------------------------------------
1857Rounds the double-precision floating-point value `a' to an integer, and
1858returns the result as a double-precision floating-point value. The
1859operation is performed according to the IEC/IEEE Standard for Binary
1860Floating-point Arithmetic.
1861-------------------------------------------------------------------------------
1862*/
1863float64 float64_round_to_int( float64 a )
1864{
1865 flag aSign;
1866 int16 aExp;
1867 bits64 lastBitMask, roundBitsMask;
1868 int8 roundingMode;
1869 float64 z;
1870
1871 aExp = extractFloat64Exp( a );
1872 if ( 0x433 <= aExp ) {
1873 if ( ( aExp == 0x7FF ) && extractFloat64Frac( a ) ) {
1874 return propagateFloat64NaN( a, a );
1875 }
1876 return a;
1877 }
1878 if ( aExp <= 0x3FE ) {
1879 if ( (bits64) ( a<<1 ) == 0 ) return a;
1880 float_exception_flags |= float_flag_inexact;
1881 aSign = extractFloat64Sign( a );
1882 switch ( float_rounding_mode ) {
1883 case float_round_nearest_even:
1884 if ( ( aExp == 0x3FE ) && extractFloat64Frac( a ) ) {
1885 return packFloat64( aSign, 0x3FF, 0 );
1886 }
1887 break;
1888 case float_round_down:
1889 return aSign ? LIT64( 0xBFF0000000000000 ) : 0;
1890 case float_round_up:
1891 return
1892 aSign ? LIT64( 0x8000000000000000 ) : LIT64( 0x3FF0000000000000 );
1893 }
1894 return packFloat64( aSign, 0, 0 );
1895 }
1896 lastBitMask = 1;
1897 lastBitMask <<= 0x433 - aExp;
1898 roundBitsMask = lastBitMask - 1;
1899 z = a;
1900 roundingMode = float_rounding_mode;
1901 if ( roundingMode == float_round_nearest_even ) {
1902 z += lastBitMask>>1;
1903 if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask;
1904 }
1905 else if ( roundingMode != float_round_to_zero ) {
1906 if ( extractFloat64Sign( z ) ^ ( roundingMode == float_round_up ) ) {
1907 z += roundBitsMask;
1908 }
1909 }
1910 z &= ~ roundBitsMask;
1911 if ( z != a ) float_exception_flags |= float_flag_inexact;
1912 return z;
1913
1914}
1915
1916/*
1917-------------------------------------------------------------------------------
1918Returns the result of adding the absolute values of the double-precision
1919floating-point values `a' and `b'. If `zSign' is true, the sum is negated
1920before being returned. `zSign' is ignored if the result is a NaN. The
1921addition is performed according to the IEC/IEEE Standard for Binary
1922Floating-point Arithmetic.
1923-------------------------------------------------------------------------------
1924*/
1925static float64 addFloat64Sigs( float64 a, float64 b, flag zSign )
1926{
1927 int16 aExp, bExp, zExp;
1928 bits64 aSig, bSig, zSig;
1929 int16 expDiff;
1930
1931 aSig = extractFloat64Frac( a );
1932 aExp = extractFloat64Exp( a );
1933 bSig = extractFloat64Frac( b );
1934 bExp = extractFloat64Exp( b );
1935 expDiff = aExp - bExp;
1936 aSig <<= 9;
1937 bSig <<= 9;
1938 if ( 0 < expDiff ) {
1939 if ( aExp == 0x7FF ) {
1940 if ( aSig ) return propagateFloat64NaN( a, b );
1941 return a;
1942 }
1943 if ( bExp == 0 ) {
1944 --expDiff;
1945 }
1946 else {
1947 bSig |= LIT64( 0x2000000000000000 );
1948 }
1949 shift64RightJamming( bSig, expDiff, &bSig );
1950 zExp = aExp;
1951 }
1952 else if ( expDiff < 0 ) {
1953 if ( bExp == 0x7FF ) {
1954 if ( bSig ) return propagateFloat64NaN( a, b );
1955 return packFloat64( zSign, 0x7FF, 0 );
1956 }
1957 if ( aExp == 0 ) {
1958 ++expDiff;
1959 }
1960 else {
1961 aSig |= LIT64( 0x2000000000000000 );
1962 }
1963 shift64RightJamming( aSig, - expDiff, &aSig );
1964 zExp = bExp;
1965 }
1966 else {
1967 if ( aExp == 0x7FF ) {
1968 if ( aSig | bSig ) return propagateFloat64NaN( a, b );
1969 return a;
1970 }
1971 if ( aExp == 0 ) return packFloat64( zSign, 0, ( aSig + bSig )>>9 );
1972 zSig = LIT64( 0x4000000000000000 ) + aSig + bSig;
1973 zExp = aExp;
1974 goto roundAndPack;
1975 }
1976 aSig |= LIT64( 0x2000000000000000 );
1977 zSig = ( aSig + bSig )<<1;
1978 --zExp;
1979 if ( (sbits64) zSig < 0 ) {
1980 zSig = aSig + bSig;
1981 ++zExp;
1982 }
1983 roundAndPack:
1984 return roundAndPackFloat64( zSign, zExp, zSig );
1985
1986}
1987
1988/*
1989-------------------------------------------------------------------------------
1990Returns the result of subtracting the absolute values of the double-
1991precision floating-point values `a' and `b'. If `zSign' is true, the
1992difference is negated before being returned. `zSign' is ignored if the
1993result is a NaN. The subtraction is performed according to the IEC/IEEE
1994Standard for Binary Floating-point Arithmetic.
1995-------------------------------------------------------------------------------
1996*/
1997static float64 subFloat64Sigs( float64 a, float64 b, flag zSign )
1998{
1999 int16 aExp, bExp, zExp;
2000 bits64 aSig, bSig, zSig;
2001 int16 expDiff;
2002
2003 aSig = extractFloat64Frac( a );
2004 aExp = extractFloat64Exp( a );
2005 bSig = extractFloat64Frac( b );
2006 bExp = extractFloat64Exp( b );
2007 expDiff = aExp - bExp;
2008 aSig <<= 10;
2009 bSig <<= 10;
2010 if ( 0 < expDiff ) goto aExpBigger;
2011 if ( expDiff < 0 ) goto bExpBigger;
2012 if ( aExp == 0x7FF ) {
2013 if ( aSig | bSig ) return propagateFloat64NaN( a, b );
2014 float_raise( float_flag_invalid );
2015 return float64_default_nan;
2016 }
2017 if ( aExp == 0 ) {
2018 aExp = 1;
2019 bExp = 1;
2020 }
2021 if ( bSig < aSig ) goto aBigger;
2022 if ( aSig < bSig ) goto bBigger;
2023 return packFloat64( float_rounding_mode == float_round_down, 0, 0 );
2024 bExpBigger:
2025 if ( bExp == 0x7FF ) {
2026 if ( bSig ) return propagateFloat64NaN( a, b );
2027 return packFloat64( zSign ^ 1, 0x7FF, 0 );
2028 }
2029 if ( aExp == 0 ) {
2030 ++expDiff;
2031 }
2032 else {
2033 aSig |= LIT64( 0x4000000000000000 );
2034 }
2035 shift64RightJamming( aSig, - expDiff, &aSig );
2036 bSig |= LIT64( 0x4000000000000000 );
2037 bBigger:
2038 zSig = bSig - aSig;
2039 zExp = bExp;
2040 zSign ^= 1;
2041 goto normalizeRoundAndPack;
2042 aExpBigger:
2043 if ( aExp == 0x7FF ) {
2044 if ( aSig ) return propagateFloat64NaN( a, b );
2045 return a;
2046 }
2047 if ( bExp == 0 ) {
2048 --expDiff;
2049 }
2050 else {
2051 bSig |= LIT64( 0x4000000000000000 );
2052 }
2053 shift64RightJamming( bSig, expDiff, &bSig );
2054 aSig |= LIT64( 0x4000000000000000 );
2055 aBigger:
2056 zSig = aSig - bSig;
2057 zExp = aExp;
2058 normalizeRoundAndPack:
2059 --zExp;
2060 return normalizeRoundAndPackFloat64( zSign, zExp, zSig );
2061
2062}
2063
2064/*
2065-------------------------------------------------------------------------------
2066Returns the result of adding the double-precision floating-point values `a'
2067and `b'. The operation is performed according to the IEC/IEEE Standard for
2068Binary Floating-point Arithmetic.
2069-------------------------------------------------------------------------------
2070*/
2071float64 float64_add( float64 a, float64 b )
2072{
2073 flag aSign, bSign;
2074
2075 aSign = extractFloat64Sign( a );
2076 bSign = extractFloat64Sign( b );
2077 if ( aSign == bSign ) {
2078 return addFloat64Sigs( a, b, aSign );
2079 }
2080 else {
2081 return subFloat64Sigs( a, b, aSign );
2082 }
2083
2084}
2085
2086/*
2087-------------------------------------------------------------------------------
2088Returns the result of subtracting the double-precision floating-point values
2089`a' and `b'. The operation is performed according to the IEC/IEEE Standard
2090for Binary Floating-point Arithmetic.
2091-------------------------------------------------------------------------------
2092*/
2093float64 float64_sub( float64 a, float64 b )
2094{
2095 flag aSign, bSign;
2096
2097 aSign = extractFloat64Sign( a );
2098 bSign = extractFloat64Sign( b );
2099 if ( aSign == bSign ) {
2100 return subFloat64Sigs( a, b, aSign );
2101 }
2102 else {
2103 return addFloat64Sigs( a, b, aSign );
2104 }
2105
2106}
2107
2108/*
2109-------------------------------------------------------------------------------
2110Returns the result of multiplying the double-precision floating-point values
2111`a' and `b'. The operation is performed according to the IEC/IEEE Standard
2112for Binary Floating-point Arithmetic.
2113-------------------------------------------------------------------------------
2114*/
2115float64 float64_mul( float64 a, float64 b )
2116{
2117 flag aSign, bSign, zSign;
2118 int16 aExp, bExp, zExp;
2119 bits64 aSig, bSig, zSig0, zSig1;
2120
2121 aSig = extractFloat64Frac( a );
2122 aExp = extractFloat64Exp( a );
2123 aSign = extractFloat64Sign( a );
2124 bSig = extractFloat64Frac( b );
2125 bExp = extractFloat64Exp( b );
2126 bSign = extractFloat64Sign( b );
2127 zSign = aSign ^ bSign;
2128 if ( aExp == 0x7FF ) {
2129 if ( aSig || ( ( bExp == 0x7FF ) && bSig ) ) {
2130 return propagateFloat64NaN( a, b );
2131 }
2132 if ( ( bExp | bSig ) == 0 ) {
2133 float_raise( float_flag_invalid );
2134 return float64_default_nan;
2135 }
2136 return packFloat64( zSign, 0x7FF, 0 );
2137 }
2138 if ( bExp == 0x7FF ) {
2139 if ( bSig ) return propagateFloat64NaN( a, b );
2140 if ( ( aExp | aSig ) == 0 ) {
2141 float_raise( float_flag_invalid );
2142 return float64_default_nan;
2143 }
2144 return packFloat64( zSign, 0x7FF, 0 );
2145 }
2146 if ( aExp == 0 ) {
2147 if ( aSig == 0 ) return packFloat64( zSign, 0, 0 );
2148 normalizeFloat64Subnormal( aSig, &aExp, &aSig );
2149 }
2150 if ( bExp == 0 ) {
2151 if ( bSig == 0 ) return packFloat64( zSign, 0, 0 );
2152 normalizeFloat64Subnormal( bSig, &bExp, &bSig );
2153 }
2154 zExp = aExp + bExp - 0x3FF;
2155 aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<10;
2156 bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11;
2157 mul64To128( aSig, bSig, &zSig0, &zSig1 );
2158 zSig0 |= ( zSig1 != 0 );
2159 if ( 0 <= (sbits64) ( zSig0<<1 ) ) {
2160 zSig0 <<= 1;
2161 --zExp;
2162 }
2163 return roundAndPackFloat64( zSign, zExp, zSig0 );
2164
2165}
2166
2167/*
2168-------------------------------------------------------------------------------
2169Returns the result of dividing the double-precision floating-point value `a'
2170by the corresponding value `b'. The operation is performed according to
2171the IEC/IEEE Standard for Binary Floating-point Arithmetic.
2172-------------------------------------------------------------------------------
2173*/
2174float64 float64_div( float64 a, float64 b )
2175{
2176 flag aSign, bSign, zSign;
2177 int16 aExp, bExp, zExp;
2178 bits64 aSig, bSig, zSig;
2179 bits64 rem0, rem1;
2180 bits64 term0, term1;
2181
2182 aSig = extractFloat64Frac( a );
2183 aExp = extractFloat64Exp( a );
2184 aSign = extractFloat64Sign( a );
2185 bSig = extractFloat64Frac( b );
2186 bExp = extractFloat64Exp( b );
2187 bSign = extractFloat64Sign( b );
2188 zSign = aSign ^ bSign;
2189 if ( aExp == 0x7FF ) {
2190 if ( aSig ) return propagateFloat64NaN( a, b );
2191 if ( bExp == 0x7FF ) {
2192 if ( bSig ) return propagateFloat64NaN( a, b );
2193 float_raise( float_flag_invalid );
2194 return float64_default_nan;
2195 }
2196 return packFloat64( zSign, 0x7FF, 0 );
2197 }
2198 if ( bExp == 0x7FF ) {
2199 if ( bSig ) return propagateFloat64NaN( a, b );
2200 return packFloat64( zSign, 0, 0 );
2201 }
2202 if ( bExp == 0 ) {
2203 if ( bSig == 0 ) {
2204 if ( ( aExp | aSig ) == 0 ) {
2205 float_raise( float_flag_invalid );
2206 return float64_default_nan;
2207 }
2208 float_raise( float_flag_divbyzero );
2209 return packFloat64( zSign, 0x7FF, 0 );
2210 }
2211 normalizeFloat64Subnormal( bSig, &bExp, &bSig );
2212 }
2213 if ( aExp == 0 ) {
2214 if ( aSig == 0 ) return packFloat64( zSign, 0, 0 );
2215 normalizeFloat64Subnormal( aSig, &aExp, &aSig );
2216 }
2217 zExp = aExp - bExp + 0x3FD;
2218 aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<10;
2219 bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11;
2220 if ( bSig <= ( aSig + aSig ) ) {
2221 aSig >>= 1;
2222 ++zExp;
2223 }
2224 zSig = estimateDiv128To64( aSig, 0, bSig );
2225 if ( ( zSig & 0x1FF ) <= 2 ) {
2226 mul64To128( bSig, zSig, &term0, &term1 );
2227 sub128( aSig, 0, term0, term1, &rem0, &rem1 );
2228 while ( (sbits64) rem0 < 0 ) {
2229 --zSig;
2230 add128( rem0, rem1, 0, bSig, &rem0, &rem1 );
2231 }
2232 zSig |= ( rem1 != 0 );
2233 }
2234 return roundAndPackFloat64( zSign, zExp, zSig );
2235
2236}
2237
2238/*
2239-------------------------------------------------------------------------------
2240Returns the remainder of the double-precision floating-point value `a'
2241with respect to the corresponding value `b'. The operation is performed
2242according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
2243-------------------------------------------------------------------------------
2244*/
2245float64 float64_rem( float64 a, float64 b )
2246{
2247 flag aSign, bSign, zSign;
2248 int16 aExp, bExp, expDiff;
2249 bits64 aSig, bSig;
2250 bits64 q, alternateASig;
2251 sbits64 sigMean;
2252
2253 aSig = extractFloat64Frac( a );
2254 aExp = extractFloat64Exp( a );
2255 aSign = extractFloat64Sign( a );
2256 bSig = extractFloat64Frac( b );
2257 bExp = extractFloat64Exp( b );
2258 bSign = extractFloat64Sign( b );
2259 if ( aExp == 0x7FF ) {
2260 if ( aSig || ( ( bExp == 0x7FF ) && bSig ) ) {
2261 return propagateFloat64NaN( a, b );
2262 }
2263 float_raise( float_flag_invalid );
2264 return float64_default_nan;
2265 }
2266 if ( bExp == 0x7FF ) {
2267 if ( bSig ) return propagateFloat64NaN( a, b );
2268 return a;
2269 }
2270 if ( bExp == 0 ) {
2271 if ( bSig == 0 ) {
2272 float_raise( float_flag_invalid );
2273 return float64_default_nan;
2274 }
2275 normalizeFloat64Subnormal( bSig, &bExp, &bSig );
2276 }
2277 if ( aExp == 0 ) {
2278 if ( aSig == 0 ) return a;
2279 normalizeFloat64Subnormal( aSig, &aExp, &aSig );
2280 }
2281 expDiff = aExp - bExp;
2282 aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<11;
2283 bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11;
2284 if ( expDiff < 0 ) {
2285 if ( expDiff < -1 ) return a;
2286 aSig >>= 1;
2287 }
2288 q = ( bSig <= aSig );
2289 if ( q ) aSig -= bSig;
2290 expDiff -= 64;
2291 while ( 0 < expDiff ) {
2292 q = estimateDiv128To64( aSig, 0, bSig );
2293 q = ( 2 < q ) ? q - 2 : 0;
2294 aSig = - ( ( bSig>>2 ) * q );
2295 expDiff -= 62;
2296 }
2297 expDiff += 64;
2298 if ( 0 < expDiff ) {
2299 q = estimateDiv128To64( aSig, 0, bSig );
2300 q = ( 2 < q ) ? q - 2 : 0;
2301 q >>= 64 - expDiff;
2302 bSig >>= 2;
2303 aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q;
2304 }
2305 else {
2306 aSig >>= 2;
2307 bSig >>= 2;
2308 }
2309 do {
2310 alternateASig = aSig;
2311 ++q;
2312 aSig -= bSig;
2313 } while ( 0 <= (sbits64) aSig );
2314 sigMean = aSig + alternateASig;
2315 if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) {
2316 aSig = alternateASig;
2317 }
2318 zSign = ( (sbits64) aSig < 0 );
2319 if ( zSign ) aSig = - aSig;
2320 return normalizeRoundAndPackFloat64( aSign ^ zSign, bExp, aSig );
2321
2322}
2323
2324/*
2325-------------------------------------------------------------------------------
2326Returns the square root of the double-precision floating-point value `a'.
2327The operation is performed according to the IEC/IEEE Standard for Binary
2328Floating-point Arithmetic.
2329-------------------------------------------------------------------------------
2330*/
2331float64 float64_sqrt( float64 a )
2332{
2333 flag aSign;
2334 int16 aExp, zExp;
2335 bits64 aSig, zSig;
2336 bits64 rem0, rem1, term0, term1; //, shiftedRem;
2337 //float64 z;
2338
2339 aSig = extractFloat64Frac( a );
2340 aExp = extractFloat64Exp( a );
2341 aSign = extractFloat64Sign( a );
2342 if ( aExp == 0x7FF ) {
2343 if ( aSig ) return propagateFloat64NaN( a, a );
2344 if ( ! aSign ) return a;
2345 float_raise( float_flag_invalid );
2346 return float64_default_nan;
2347 }
2348 if ( aSign ) {
2349 if ( ( aExp | aSig ) == 0 ) return a;
2350 float_raise( float_flag_invalid );
2351 return float64_default_nan;
2352 }
2353 if ( aExp == 0 ) {
2354 if ( aSig == 0 ) return 0;
2355 normalizeFloat64Subnormal( aSig, &aExp, &aSig );
2356 }
2357 zExp = ( ( aExp - 0x3FF )>>1 ) + 0x3FE;
2358 aSig |= LIT64( 0x0010000000000000 );
2359 zSig = estimateSqrt32( aExp, aSig>>21 );
2360 zSig <<= 31;
2361 aSig <<= 9 - ( aExp & 1 );
2362 zSig = estimateDiv128To64( aSig, 0, zSig ) + zSig + 2;
2363 if ( ( zSig & 0x3FF ) <= 5 ) {
2364 if ( zSig < 2 ) {
2365 zSig = LIT64( 0xFFFFFFFFFFFFFFFF );
2366 }
2367 else {
2368 aSig <<= 2;
2369 mul64To128( zSig, zSig, &term0, &term1 );
2370 sub128( aSig, 0, term0, term1, &rem0, &rem1 );
2371 while ( (sbits64) rem0 < 0 ) {
2372 --zSig;
2373 shortShift128Left( 0, zSig, 1, &term0, &term1 );
2374 term1 |= 1;
2375 add128( rem0, rem1, term0, term1, &rem0, &rem1 );
2376 }
2377 zSig |= ( ( rem0 | rem1 ) != 0 );
2378 }
2379 }
2380 shift64RightJamming( zSig, 1, &zSig );
2381 return roundAndPackFloat64( 0, zExp, zSig );
2382
2383}
2384
2385/*
2386-------------------------------------------------------------------------------
2387Returns 1 if the double-precision floating-point value `a' is equal to the
2388corresponding value `b', and 0 otherwise. The comparison is performed
2389according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
2390-------------------------------------------------------------------------------
2391*/
2392flag float64_eq( float64 a, float64 b )
2393{
2394
2395 if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
2396 || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
2397 ) {
2398 if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
2399 float_raise( float_flag_invalid );
2400 }
2401 return 0;
2402 }
2403 return ( a == b ) || ( (bits64) ( ( a | b )<<1 ) == 0 );
2404
2405}
2406
2407/*
2408-------------------------------------------------------------------------------
2409Returns 1 if the double-precision floating-point value `a' is less than or
2410equal to the corresponding value `b', and 0 otherwise. The comparison is
2411performed according to the IEC/IEEE Standard for Binary Floating-point
2412Arithmetic.
2413-------------------------------------------------------------------------------
2414*/
2415flag float64_le( float64 a, float64 b )
2416{
2417 flag aSign, bSign;
2418
2419 if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
2420 || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
2421 ) {
2422 float_raise( float_flag_invalid );
2423 return 0;
2424 }
2425 aSign = extractFloat64Sign( a );
2426 bSign = extractFloat64Sign( b );
2427 if ( aSign != bSign ) return aSign || ( (bits64) ( ( a | b )<<1 ) == 0 );
2428 return ( a == b ) || ( aSign ^ ( a < b ) );
2429
2430}
2431
2432/*
2433-------------------------------------------------------------------------------
2434Returns 1 if the double-precision floating-point value `a' is less than
2435the corresponding value `b', and 0 otherwise. The comparison is performed
2436according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
2437-------------------------------------------------------------------------------
2438*/
2439flag float64_lt( float64 a, float64 b )
2440{
2441 flag aSign, bSign;
2442
2443 if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
2444 || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
2445 ) {
2446 float_raise( float_flag_invalid );
2447 return 0;
2448 }
2449 aSign = extractFloat64Sign( a );
2450 bSign = extractFloat64Sign( b );
2451 if ( aSign != bSign ) return aSign && ( (bits64) ( ( a | b )<<1 ) != 0 );
2452 return ( a != b ) && ( aSign ^ ( a < b ) );
2453
2454}
2455
2456/*
2457-------------------------------------------------------------------------------
2458Returns 1 if the double-precision floating-point value `a' is equal to the
2459corresponding value `b', and 0 otherwise. The invalid exception is raised
2460if either operand is a NaN. Otherwise, the comparison is performed
2461according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
2462-------------------------------------------------------------------------------
2463*/
2464flag float64_eq_signaling( float64 a, float64 b )
2465{
2466
2467 if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
2468 || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
2469 ) {
2470 float_raise( float_flag_invalid );
2471 return 0;
2472 }
2473 return ( a == b ) || ( (bits64) ( ( a | b )<<1 ) == 0 );
2474
2475}
2476
2477/*
2478-------------------------------------------------------------------------------
2479Returns 1 if the double-precision floating-point value `a' is less than or
2480equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not
2481cause an exception. Otherwise, the comparison is performed according to the
2482IEC/IEEE Standard for Binary Floating-point Arithmetic.
2483-------------------------------------------------------------------------------
2484*/
2485flag float64_le_quiet( float64 a, float64 b )
2486{
2487 flag aSign, bSign;
2488 //int16 aExp, bExp;
2489
2490 if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
2491 || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
2492 ) {
2493 if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
2494 float_raise( float_flag_invalid );
2495 }
2496 return 0;
2497 }
2498 aSign = extractFloat64Sign( a );
2499 bSign = extractFloat64Sign( b );
2500 if ( aSign != bSign ) return aSign || ( (bits64) ( ( a | b )<<1 ) == 0 );
2501 return ( a == b ) || ( aSign ^ ( a < b ) );
2502
2503}
2504
2505/*
2506-------------------------------------------------------------------------------
2507Returns 1 if the double-precision floating-point value `a' is less than
2508the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
2509exception. Otherwise, the comparison is performed according to the IEC/IEEE
2510Standard for Binary Floating-point Arithmetic.
2511-------------------------------------------------------------------------------
2512*/
2513flag float64_lt_quiet( float64 a, float64 b )
2514{
2515 flag aSign, bSign;
2516
2517 if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
2518 || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
2519 ) {
2520 if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
2521 float_raise( float_flag_invalid );
2522 }
2523 return 0;
2524 }
2525 aSign = extractFloat64Sign( a );
2526 bSign = extractFloat64Sign( b );
2527 if ( aSign != bSign ) return aSign && ( (bits64) ( ( a | b )<<1 ) != 0 );
2528 return ( a != b ) && ( aSign ^ ( a < b ) );
2529
2530}
2531
2532#ifdef FLOATX80
2533
2534/*
2535-------------------------------------------------------------------------------
2536Returns the result of converting the extended double-precision floating-
2537point value `a' to the 32-bit two's complement integer format. The
2538conversion is performed according to the IEC/IEEE Standard for Binary
2539Floating-point Arithmetic---which means in particular that the conversion
2540is rounded according to the current rounding mode. If `a' is a NaN, the
2541largest positive integer is returned. Otherwise, if the conversion
2542overflows, the largest integer with the same sign as `a' is returned.
2543-------------------------------------------------------------------------------
2544*/
2545int32 floatx80_to_int32( floatx80 a )
2546{
2547 flag aSign;
2548 int32 aExp, shiftCount;
2549 bits64 aSig;
2550
2551 aSig = extractFloatx80Frac( a );
2552 aExp = extractFloatx80Exp( a );
2553 aSign = extractFloatx80Sign( a );
2554 if ( ( aExp == 0x7FFF ) && (bits64) ( aSig<<1 ) ) aSign = 0;
2555 shiftCount = 0x4037 - aExp;
2556 if ( shiftCount <= 0 ) shiftCount = 1;
2557 shift64RightJamming( aSig, shiftCount, &aSig );
2558 return roundAndPackInt32( aSign, aSig );
2559
2560}
2561
2562/*
2563-------------------------------------------------------------------------------
2564Returns the result of converting the extended double-precision floating-
2565point value `a' to the 32-bit two's complement integer format. The
2566conversion is performed according to the IEC/IEEE Standard for Binary
2567Floating-point Arithmetic, except that the conversion is always rounded
2568toward zero. If `a' is a NaN, the largest positive integer is returned.
2569Otherwise, if the conversion overflows, the largest integer with the same
2570sign as `a' is returned.
2571-------------------------------------------------------------------------------
2572*/
2573int32 floatx80_to_int32_round_to_zero( floatx80 a )
2574{
2575 flag aSign;
2576 int32 aExp, shiftCount;
2577 bits64 aSig, savedASig;
2578 int32 z;
2579
2580 aSig = extractFloatx80Frac( a );
2581 aExp = extractFloatx80Exp( a );
2582 aSign = extractFloatx80Sign( a );
2583 shiftCount = 0x403E - aExp;
2584 if ( shiftCount < 32 ) {
2585 if ( ( aExp == 0x7FFF ) && (bits64) ( aSig<<1 ) ) aSign = 0;
2586 goto invalid;
2587 }
2588 else if ( 63 < shiftCount ) {
2589 if ( aExp || aSig ) float_exception_flags |= float_flag_inexact;
2590 return 0;
2591 }
2592 savedASig = aSig;
2593 aSig >>= shiftCount;
2594 z = aSig;
2595 if ( aSign ) z = - z;
2596 if ( ( z < 0 ) ^ aSign ) {
2597 invalid:
2598 float_exception_flags |= float_flag_invalid;
2599 return aSign ? 0x80000000 : 0x7FFFFFFF;
2600 }
2601 if ( ( aSig<<shiftCount ) != savedASig ) {
2602 float_exception_flags |= float_flag_inexact;
2603 }
2604 return z;
2605
2606}
2607
2608/*
2609-------------------------------------------------------------------------------
2610Returns the result of converting the extended double-precision floating-
2611point value `a' to the single-precision floating-point format. The
2612conversion is performed according to the IEC/IEEE Standard for Binary
2613Floating-point Arithmetic.
2614-------------------------------------------------------------------------------
2615*/
2616float32 floatx80_to_float32( floatx80 a )
2617{
2618 flag aSign;
2619 int32 aExp;
2620 bits64 aSig;
2621
2622 aSig = extractFloatx80Frac( a );
2623 aExp = extractFloatx80Exp( a );
2624 aSign = extractFloatx80Sign( a );
2625 if ( aExp == 0x7FFF ) {
2626 if ( (bits64) ( aSig<<1 ) ) {
2627 return commonNaNToFloat32( floatx80ToCommonNaN( a ) );
2628 }
2629 return packFloat32( aSign, 0xFF, 0 );
2630 }
2631 shift64RightJamming( aSig, 33, &aSig );
2632 if ( aExp || aSig ) aExp -= 0x3F81;
2633 return roundAndPackFloat32( aSign, aExp, aSig );
2634
2635}
2636
2637/*
2638-------------------------------------------------------------------------------
2639Returns the result of converting the extended double-precision floating-
2640point value `a' to the double-precision floating-point format. The
2641conversion is performed according to the IEC/IEEE Standard for Binary
2642Floating-point Arithmetic.
2643-------------------------------------------------------------------------------
2644*/
2645float64 floatx80_to_float64( floatx80 a )
2646{
2647 flag aSign;
2648 int32 aExp;
2649 bits64 aSig, zSig;
2650
2651 aSig = extractFloatx80Frac( a );
2652 aExp = extractFloatx80Exp( a );
2653 aSign = extractFloatx80Sign( a );
2654 if ( aExp == 0x7FFF ) {
2655 if ( (bits64) ( aSig<<1 ) ) {
2656 return commonNaNToFloat64( floatx80ToCommonNaN( a ) );
2657 }
2658 return packFloat64( aSign, 0x7FF, 0 );
2659 }
2660 shift64RightJamming( aSig, 1, &zSig );
2661 if ( aExp || aSig ) aExp -= 0x3C01;
2662 return roundAndPackFloat64( aSign, aExp, zSig );
2663
2664}
2665
2666/*
2667-------------------------------------------------------------------------------
2668Rounds the extended double-precision floating-point value `a' to an integer,
2669and returns the result as an extended quadruple-precision floating-point
2670value. The operation is performed according to the IEC/IEEE Standard for
2671Binary Floating-point Arithmetic.
2672-------------------------------------------------------------------------------
2673*/
2674floatx80 floatx80_round_to_int( floatx80 a )
2675{
2676 flag aSign;
2677 int32 aExp;
2678 bits64 lastBitMask, roundBitsMask;
2679 int8 roundingMode;
2680 floatx80 z;
2681
2682 aExp = extractFloatx80Exp( a );
2683 if ( 0x403E <= aExp ) {
2684 if ( ( aExp == 0x7FFF ) && (bits64) ( extractFloatx80Frac( a )<<1 ) ) {
2685 return propagateFloatx80NaN( a, a );
2686 }
2687 return a;
2688 }
2689 if ( aExp <= 0x3FFE ) {
2690 if ( ( aExp == 0 )
2691 && ( (bits64) ( extractFloatx80Frac( a )<<1 ) == 0 ) ) {
2692 return a;
2693 }
2694 float_exception_flags |= float_flag_inexact;
2695 aSign = extractFloatx80Sign( a );
2696 switch ( float_rounding_mode ) {
2697 case float_round_nearest_even:
2698 if ( ( aExp == 0x3FFE ) && (bits64) ( extractFloatx80Frac( a )<<1 )
2699 ) {
2700 return
2701 packFloatx80( aSign, 0x3FFF, LIT64( 0x8000000000000000 ) );
2702 }
2703 break;
2704 case float_round_down:
2705 return
2706 aSign ?
2707 packFloatx80( 1, 0x3FFF, LIT64( 0x8000000000000000 ) )
2708 : packFloatx80( 0, 0, 0 );
2709 case float_round_up:
2710 return
2711 aSign ? packFloatx80( 1, 0, 0 )
2712 : packFloatx80( 0, 0x3FFF, LIT64( 0x8000000000000000 ) );
2713 }
2714 return packFloatx80( aSign, 0, 0 );
2715 }
2716 lastBitMask = 1;
2717 lastBitMask <<= 0x403E - aExp;
2718 roundBitsMask = lastBitMask - 1;
2719 z = a;
2720 roundingMode = float_rounding_mode;
2721 if ( roundingMode == float_round_nearest_even ) {
2722 z.low += lastBitMask>>1;
2723 if ( ( z.low & roundBitsMask ) == 0 ) z.low &= ~ lastBitMask;
2724 }
2725 else if ( roundingMode != float_round_to_zero ) {
2726 if ( extractFloatx80Sign( z ) ^ ( roundingMode == float_round_up ) ) {
2727 z.low += roundBitsMask;
2728 }
2729 }
2730 z.low &= ~ roundBitsMask;
2731 if ( z.low == 0 ) {
2732 ++z.high;
2733 z.low = LIT64( 0x8000000000000000 );
2734 }
2735 if ( z.low != a.low ) float_exception_flags |= float_flag_inexact;
2736 return z;
2737
2738}
2739
2740/*
2741-------------------------------------------------------------------------------
2742Returns the result of adding the absolute values of the extended double-
2743precision floating-point values `a' and `b'. If `zSign' is true, the sum is
2744negated before being returned. `zSign' is ignored if the result is a NaN.
2745The addition is performed according to the IEC/IEEE Standard for Binary
2746Floating-point Arithmetic.
2747-------------------------------------------------------------------------------
2748*/
2749static floatx80 addFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )
2750{
2751 int32 aExp, bExp, zExp;
2752 bits64 aSig, bSig, zSig0, zSig1;
2753 int32 expDiff;
2754
2755 aSig = extractFloatx80Frac( a );
2756 aExp = extractFloatx80Exp( a );
2757 bSig = extractFloatx80Frac( b );
2758 bExp = extractFloatx80Exp( b );
2759 expDiff = aExp - bExp;
2760 if ( 0 < expDiff ) {
2761 if ( aExp == 0x7FFF ) {
2762 if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );
2763 return a;
2764 }
2765 if ( bExp == 0 ) --expDiff;
2766 shift64ExtraRightJamming( bSig, 0, expDiff, &bSig, &zSig1 );
2767 zExp = aExp;
2768 }
2769 else if ( expDiff < 0 ) {
2770 if ( bExp == 0x7FFF ) {
2771 if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
2772 return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
2773 }
2774 if ( aExp == 0 ) ++expDiff;
2775 shift64ExtraRightJamming( aSig, 0, - expDiff, &aSig, &zSig1 );
2776 zExp = bExp;
2777 }
2778 else {
2779 if ( aExp == 0x7FFF ) {
2780 if ( (bits64) ( ( aSig | bSig )<<1 ) ) {
2781 return propagateFloatx80NaN( a, b );
2782 }
2783 return a;
2784 }
2785 zSig1 = 0;
2786 zSig0 = aSig + bSig;
2787 if ( aExp == 0 ) {
2788 normalizeFloatx80Subnormal( zSig0, &zExp, &zSig0 );
2789 goto roundAndPack;
2790 }
2791 zExp = aExp;
2792 goto shiftRight1;
2793 }
2794
2795 zSig0 = aSig + bSig;
2796
2797 if ( (sbits64) zSig0 < 0 ) goto roundAndPack;
2798 shiftRight1:
2799 shift64ExtraRightJamming( zSig0, zSig1, 1, &zSig0, &zSig1 );
2800 zSig0 |= LIT64( 0x8000000000000000 );
2801 ++zExp;
2802 roundAndPack:
2803 return
2804 roundAndPackFloatx80(
2805 floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
2806
2807}
2808
2809/*
2810-------------------------------------------------------------------------------
2811Returns the result of subtracting the absolute values of the extended
2812double-precision floating-point values `a' and `b'. If `zSign' is true,
2813the difference is negated before being returned. `zSign' is ignored if the
2814result is a NaN. The subtraction is performed according to the IEC/IEEE
2815Standard for Binary Floating-point Arithmetic.
2816-------------------------------------------------------------------------------
2817*/
2818static floatx80 subFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )
2819{
2820 int32 aExp, bExp, zExp;
2821 bits64 aSig, bSig, zSig0, zSig1;
2822 int32 expDiff;
2823 floatx80 z;
2824
2825 aSig = extractFloatx80Frac( a );
2826 aExp = extractFloatx80Exp( a );
2827 bSig = extractFloatx80Frac( b );
2828 bExp = extractFloatx80Exp( b );
2829 expDiff = aExp - bExp;
2830 if ( 0 < expDiff ) goto aExpBigger;
2831 if ( expDiff < 0 ) goto bExpBigger;
2832 if ( aExp == 0x7FFF ) {
2833 if ( (bits64) ( ( aSig | bSig )<<1 ) ) {
2834 return propagateFloatx80NaN( a, b );
2835 }
2836 float_raise( float_flag_invalid );
2837 z.low = floatx80_default_nan_low;
2838 z.high = floatx80_default_nan_high;
2839 return z;
2840 }
2841 if ( aExp == 0 ) {
2842 aExp = 1;
2843 bExp = 1;
2844 }
2845 zSig1 = 0;
2846 if ( bSig < aSig ) goto aBigger;
2847 if ( aSig < bSig ) goto bBigger;
2848 return packFloatx80( float_rounding_mode == float_round_down, 0, 0 );
2849 bExpBigger:
2850 if ( bExp == 0x7FFF ) {
2851 if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
2852 return packFloatx80( zSign ^ 1, 0x7FFF, LIT64( 0x8000000000000000 ) );
2853 }
2854 if ( aExp == 0 ) ++expDiff;
2855 shift128RightJamming( aSig, 0, - expDiff, &aSig, &zSig1 );
2856 bBigger:
2857 sub128( bSig, 0, aSig, zSig1, &zSig0, &zSig1 );
2858 zExp = bExp;
2859 zSign ^= 1;
2860 goto normalizeRoundAndPack;
2861 aExpBigger:
2862 if ( aExp == 0x7FFF ) {
2863 if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );
2864 return a;
2865 }
2866 if ( bExp == 0 ) --expDiff;
2867 shift128RightJamming( bSig, 0, expDiff, &bSig, &zSig1 );
2868 aBigger:
2869 sub128( aSig, 0, bSig, zSig1, &zSig0, &zSig1 );
2870 zExp = aExp;
2871 normalizeRoundAndPack:
2872 return
2873 normalizeRoundAndPackFloatx80(
2874 floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
2875
2876}
2877
2878/*
2879-------------------------------------------------------------------------------
2880Returns the result of adding the extended double-precision floating-point
2881values `a' and `b'. The operation is performed according to the IEC/IEEE
2882Standard for Binary Floating-point Arithmetic.
2883-------------------------------------------------------------------------------
2884*/
2885floatx80 floatx80_add( floatx80 a, floatx80 b )
2886{
2887 flag aSign, bSign;
2888
2889 aSign = extractFloatx80Sign( a );
2890 bSign = extractFloatx80Sign( b );
2891 if ( aSign == bSign ) {
2892 return addFloatx80Sigs( a, b, aSign );
2893 }
2894 else {
2895 return subFloatx80Sigs( a, b, aSign );
2896 }
2897
2898}
2899
2900/*
2901-------------------------------------------------------------------------------
2902Returns the result of subtracting the extended double-precision floating-
2903point values `a' and `b'. The operation is performed according to the
2904IEC/IEEE Standard for Binary Floating-point Arithmetic.
2905-------------------------------------------------------------------------------
2906*/
2907floatx80 floatx80_sub( floatx80 a, floatx80 b )
2908{
2909 flag aSign, bSign;
2910
2911 aSign = extractFloatx80Sign( a );
2912 bSign = extractFloatx80Sign( b );
2913 if ( aSign == bSign ) {
2914 return subFloatx80Sigs( a, b, aSign );
2915 }
2916 else {
2917 return addFloatx80Sigs( a, b, aSign );
2918 }
2919
2920}
2921
2922/*
2923-------------------------------------------------------------------------------
2924Returns the result of multiplying the extended double-precision floating-
2925point values `a' and `b'. The operation is performed according to the
2926IEC/IEEE Standard for Binary Floating-point Arithmetic.
2927-------------------------------------------------------------------------------
2928*/
2929floatx80 floatx80_mul( floatx80 a, floatx80 b )
2930{
2931 flag aSign, bSign, zSign;
2932 int32 aExp, bExp, zExp;
2933 bits64 aSig, bSig, zSig0, zSig1;
2934 floatx80 z;
2935
2936 aSig = extractFloatx80Frac( a );
2937 aExp = extractFloatx80Exp( a );
2938 aSign = extractFloatx80Sign( a );
2939 bSig = extractFloatx80Frac( b );
2940 bExp = extractFloatx80Exp( b );
2941 bSign = extractFloatx80Sign( b );
2942 zSign = aSign ^ bSign;
2943 if ( aExp == 0x7FFF ) {
2944 if ( (bits64) ( aSig<<1 )
2945 || ( ( bExp == 0x7FFF ) && (bits64) ( bSig<<1 ) ) ) {
2946 return propagateFloatx80NaN( a, b );
2947 }
2948 if ( ( bExp | bSig ) == 0 ) goto invalid;
2949 return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
2950 }
2951 if ( bExp == 0x7FFF ) {
2952 if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
2953 if ( ( aExp | aSig ) == 0 ) {
2954 invalid:
2955 float_raise( float_flag_invalid );
2956 z.low = floatx80_default_nan_low;
2957 z.high = floatx80_default_nan_high;
2958 return z;
2959 }
2960 return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
2961 }
2962 if ( aExp == 0 ) {
2963 if ( aSig == 0 ) return packFloatx80( zSign, 0, 0 );
2964 normalizeFloatx80Subnormal( aSig, &aExp, &aSig );
2965 }
2966 if ( bExp == 0 ) {
2967 if ( bSig == 0 ) return packFloatx80( zSign, 0, 0 );
2968 normalizeFloatx80Subnormal( bSig, &bExp, &bSig );
2969 }
2970 zExp = aExp + bExp - 0x3FFE;
2971 mul64To128( aSig, bSig, &zSig0, &zSig1 );
2972 if ( 0 < (sbits64) zSig0 ) {
2973 shortShift128Left( zSig0, zSig1, 1, &zSig0, &zSig1 );
2974 --zExp;
2975 }
2976 return
2977 roundAndPackFloatx80(
2978 floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
2979
2980}
2981
2982/*
2983-------------------------------------------------------------------------------
2984Returns the result of dividing the extended double-precision floating-point
2985value `a' by the corresponding value `b'. The operation is performed
2986according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
2987-------------------------------------------------------------------------------
2988*/
2989floatx80 floatx80_div( floatx80 a, floatx80 b )
2990{
2991 flag aSign, bSign, zSign;
2992 int32 aExp, bExp, zExp;
2993 bits64 aSig, bSig, zSig0, zSig1;
2994 bits64 rem0, rem1, rem2, term0, term1, term2;
2995 floatx80 z;
2996
2997 aSig = extractFloatx80Frac( a );
2998 aExp = extractFloatx80Exp( a );
2999 aSign = extractFloatx80Sign( a );
3000 bSig = extractFloatx80Frac( b );
3001 bExp = extractFloatx80Exp( b );
3002 bSign = extractFloatx80Sign( b );
3003 zSign = aSign ^ bSign;
3004 if ( aExp == 0x7FFF ) {
3005 if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );
3006 if ( bExp == 0x7FFF ) {
3007 if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
3008 goto invalid;
3009 }
3010 return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
3011 }
3012 if ( bExp == 0x7FFF ) {
3013 if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
3014 return packFloatx80( zSign, 0, 0 );
3015 }
3016 if ( bExp == 0 ) {
3017 if ( bSig == 0 ) {
3018 if ( ( aExp | aSig ) == 0 ) {
3019 invalid:
3020 float_raise( float_flag_invalid );
3021 z.low = floatx80_default_nan_low;
3022 z.high = floatx80_default_nan_high;
3023 return z;
3024 }
3025 float_raise( float_flag_divbyzero );
3026 return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
3027 }
3028 normalizeFloatx80Subnormal( bSig, &bExp, &bSig );
3029 }
3030 if ( aExp == 0 ) {
3031 if ( aSig == 0 ) return packFloatx80( zSign, 0, 0 );
3032 normalizeFloatx80Subnormal( aSig, &aExp, &aSig );
3033 }
3034 zExp = aExp - bExp + 0x3FFE;
3035 rem1 = 0;
3036 if ( bSig <= aSig ) {
3037 shift128Right( aSig, 0, 1, &aSig, &rem1 );
3038 ++zExp;
3039 }
3040 zSig0 = estimateDiv128To64( aSig, rem1, bSig );
3041 mul64To128( bSig, zSig0, &term0, &term1 );
3042 sub128( aSig, rem1, term0, term1, &rem0, &rem1 );
3043 while ( (sbits64) rem0 < 0 ) {
3044 --zSig0;
3045 add128( rem0, rem1, 0, bSig, &rem0, &rem1 );
3046 }
3047 zSig1 = estimateDiv128To64( rem1, 0, bSig );
3048 if ( (bits64) ( zSig1<<1 ) <= 8 ) {
3049 mul64To128( bSig, zSig1, &term1, &term2 );
3050 sub128( rem1, 0, term1, term2, &rem1, &rem2 );
3051 while ( (sbits64) rem1 < 0 ) {
3052 --zSig1;
3053 add128( rem1, rem2, 0, bSig, &rem1, &rem2 );
3054 }
3055 zSig1 |= ( ( rem1 | rem2 ) != 0 );
3056 }
3057 return
3058 roundAndPackFloatx80(
3059 floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
3060
3061}
3062
3063/*
3064-------------------------------------------------------------------------------
3065Returns the remainder of the extended double-precision floating-point value
3066`a' with respect to the corresponding value `b'. The operation is performed
3067according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
3068-------------------------------------------------------------------------------
3069*/
3070floatx80 floatx80_rem( floatx80 a, floatx80 b )
3071{
3072 flag aSign, bSign, zSign;
3073 int32 aExp, bExp, expDiff;
3074 bits64 aSig0, aSig1, bSig;
3075 bits64 q, term0, term1, alternateASig0, alternateASig1;
3076 floatx80 z;
3077
3078 aSig0 = extractFloatx80Frac( a );
3079 aExp = extractFloatx80Exp( a );
3080 aSign = extractFloatx80Sign( a );
3081 bSig = extractFloatx80Frac( b );
3082 bExp = extractFloatx80Exp( b );
3083 bSign = extractFloatx80Sign( b );
3084 if ( aExp == 0x7FFF ) {
3085 if ( (bits64) ( aSig0<<1 )
3086 || ( ( bExp == 0x7FFF ) && (bits64) ( bSig<<1 ) ) ) {
3087 return propagateFloatx80NaN( a, b );
3088 }
3089 goto invalid;
3090 }
3091 if ( bExp == 0x7FFF ) {
3092 if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
3093 return a;
3094 }
3095 if ( bExp == 0 ) {
3096 if ( bSig == 0 ) {
3097 invalid:
3098 float_raise( float_flag_invalid );
3099 z.low = floatx80_default_nan_low;
3100 z.high = floatx80_default_nan_high;
3101 return z;
3102 }
3103 normalizeFloatx80Subnormal( bSig, &bExp, &bSig );
3104 }
3105 if ( aExp == 0 ) {
3106 if ( (bits64) ( aSig0<<1 ) == 0 ) return a;
3107 normalizeFloatx80Subnormal( aSig0, &aExp, &aSig0 );
3108 }
3109 bSig |= LIT64( 0x8000000000000000 );
3110 zSign = aSign;
3111 expDiff = aExp - bExp;
3112 aSig1 = 0;
3113 if ( expDiff < 0 ) {
3114 if ( expDiff < -1 ) return a;
3115 shift128Right( aSig0, 0, 1, &aSig0, &aSig1 );
3116 expDiff = 0;
3117 }
3118 q = ( bSig <= aSig0 );
3119 if ( q ) aSig0 -= bSig;
3120 expDiff -= 64;
3121 while ( 0 < expDiff ) {
3122 q = estimateDiv128To64( aSig0, aSig1, bSig );
3123 q = ( 2 < q ) ? q - 2 : 0;
3124 mul64To128( bSig, q, &term0, &term1 );
3125 sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );
3126 shortShift128Left( aSig0, aSig1, 62, &aSig0, &aSig1 );
3127 expDiff -= 62;
3128 }
3129 expDiff += 64;
3130 if ( 0 < expDiff ) {
3131 q = estimateDiv128To64( aSig0, aSig1, bSig );
3132 q = ( 2 < q ) ? q - 2 : 0;
3133 q >>= 64 - expDiff;
3134 mul64To128( bSig, q<<( 64 - expDiff ), &term0, &term1 );
3135 sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );
3136 shortShift128Left( 0, bSig, 64 - expDiff, &term0, &term1 );
3137 while ( le128( term0, term1, aSig0, aSig1 ) ) {
3138 ++q;
3139 sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );
3140 }
3141 }
3142 else {
3143 term1 = 0;
3144 term0 = bSig;
3145 }
3146 sub128( term0, term1, aSig0, aSig1, &alternateASig0, &alternateASig1 );
3147 if ( lt128( alternateASig0, alternateASig1, aSig0, aSig1 )
3148 || ( eq128( alternateASig0, alternateASig1, aSig0, aSig1 )
3149 && ( q & 1 ) )
3150 ) {
3151 aSig0 = alternateASig0;
3152 aSig1 = alternateASig1;
3153 zSign = ! zSign;
3154 }
3155 return
3156 normalizeRoundAndPackFloatx80(
3157 80, zSign, bExp + expDiff, aSig0, aSig1 );
3158
3159}
3160
3161/*
3162-------------------------------------------------------------------------------
3163Returns the square root of the extended double-precision floating-point
3164value `a'. The operation is performed according to the IEC/IEEE Standard
3165for Binary Floating-point Arithmetic.
3166-------------------------------------------------------------------------------
3167*/
3168floatx80 floatx80_sqrt( floatx80 a )
3169{
3170 flag aSign;
3171 int32 aExp, zExp;
3172 bits64 aSig0, aSig1, zSig0, zSig1;
3173 bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3;
3174 bits64 shiftedRem0, shiftedRem1;
3175 floatx80 z;
3176
3177 aSig0 = extractFloatx80Frac( a );
3178 aExp = extractFloatx80Exp( a );
3179 aSign = extractFloatx80Sign( a );
3180 if ( aExp == 0x7FFF ) {
3181 if ( (bits64) ( aSig0<<1 ) ) return propagateFloatx80NaN( a, a );
3182 if ( ! aSign ) return a;
3183 goto invalid;
3184 }
3185 if ( aSign ) {
3186 if ( ( aExp | aSig0 ) == 0 ) return a;
3187 invalid:
3188 float_raise( float_flag_invalid );
3189 z.low = floatx80_default_nan_low;
3190 z.high = floatx80_default_nan_high;
3191 return z;
3192 }
3193 if ( aExp == 0 ) {
3194 if ( aSig0 == 0 ) return packFloatx80( 0, 0, 0 );
3195 normalizeFloatx80Subnormal( aSig0, &aExp, &aSig0 );
3196 }
3197 zExp = ( ( aExp - 0x3FFF )>>1 ) + 0x3FFF;
3198 zSig0 = estimateSqrt32( aExp, aSig0>>32 );
3199 zSig0 <<= 31;
3200 aSig1 = 0;
3201 shift128Right( aSig0, 0, ( aExp & 1 ) + 2, &aSig0, &aSig1 );
3202 zSig0 = estimateDiv128To64( aSig0, aSig1, zSig0 ) + zSig0 + 4;
3203 if ( 0 <= (sbits64) zSig0 ) zSig0 = LIT64( 0xFFFFFFFFFFFFFFFF );
3204 shortShift128Left( aSig0, aSig1, 2, &aSig0, &aSig1 );
3205 mul64To128( zSig0, zSig0, &term0, &term1 );
3206 sub128( aSig0, aSig1, term0, term1, &rem0, &rem1 );
3207 while ( (sbits64) rem0 < 0 ) {
3208 --zSig0;
3209 shortShift128Left( 0, zSig0, 1, &term0, &term1 );
3210 term1 |= 1;
3211 add128( rem0, rem1, term0, term1, &rem0, &rem1 );
3212 }
3213 shortShift128Left( rem0, rem1, 63, &shiftedRem0, &shiftedRem1 );
3214 zSig1 = estimateDiv128To64( shiftedRem0, shiftedRem1, zSig0 );
3215 if ( (bits64) ( zSig1<<1 ) <= 10 ) {
3216 if ( zSig1 == 0 ) zSig1 = 1;
3217 mul64To128( zSig0, zSig1, &term1, &term2 );
3218 shortShift128Left( term1, term2, 1, &term1, &term2 );
3219 sub128( rem1, 0, term1, term2, &rem1, &rem2 );
3220 mul64To128( zSig1, zSig1, &term2, &term3 );
3221 sub192( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 );
3222 while ( (sbits64) rem1 < 0 ) {
3223 --zSig1;
3224 shortShift192Left( 0, zSig0, zSig1, 1, &term1, &term2, &term3 );
3225 term3 |= 1;
3226 add192(
3227 rem1, rem2, rem3, term1, term2, term3, &rem1, &rem2, &rem3 );
3228 }
3229 zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );
3230 }
3231 return
3232 roundAndPackFloatx80(
3233 floatx80_rounding_precision, 0, zExp, zSig0, zSig1 );
3234
3235}
3236
3237/*
3238-------------------------------------------------------------------------------
3239Returns 1 if the extended double-precision floating-point value `a' is
3240equal to the corresponding value `b', and 0 otherwise. The comparison is
3241performed according to the IEC/IEEE Standard for Binary Floating-point
3242Arithmetic.
3243-------------------------------------------------------------------------------
3244*/
3245flag floatx80_eq( floatx80 a, floatx80 b )
3246{
3247
3248 if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )
3249 && (bits64) ( extractFloatx80Frac( a )<<1 ) )
3250 || ( ( extractFloatx80Exp( b ) == 0x7FFF )
3251 && (bits64) ( extractFloatx80Frac( b )<<1 ) )
3252 ) {
3253 if ( floatx80_is_signaling_nan( a )
3254 || floatx80_is_signaling_nan( b ) ) {
3255 float_raise( float_flag_invalid );
3256 }
3257 return 0;
3258 }
3259 return
3260 ( a.low == b.low )
3261 && ( ( a.high == b.high )
3262 || ( ( a.low == 0 )
3263 && ( (bits16) ( ( a.high | b.high )<<1 ) == 0 ) )
3264 );
3265
3266}
3267
3268/*
3269-------------------------------------------------------------------------------
3270Returns 1 if the extended double-precision floating-point value `a' is
3271less than or equal to the corresponding value `b', and 0 otherwise. The
3272comparison is performed according to the IEC/IEEE Standard for Binary
3273Floating-point Arithmetic.
3274-------------------------------------------------------------------------------
3275*/
3276flag floatx80_le( floatx80 a, floatx80 b )
3277{
3278 flag aSign, bSign;
3279
3280 if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )
3281 && (bits64) ( extractFloatx80Frac( a )<<1 ) )
3282 || ( ( extractFloatx80Exp( b ) == 0x7FFF )
3283 && (bits64) ( extractFloatx80Frac( b )<<1 ) )
3284 ) {
3285 float_raise( float_flag_invalid );
3286 return 0;
3287 }
3288 aSign = extractFloatx80Sign( a );
3289 bSign = extractFloatx80Sign( b );
3290 if ( aSign != bSign ) {
3291 return
3292 aSign
3293 || ( ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
3294 == 0 );
3295 }
3296 return
3297 aSign ? le128( b.high, b.low, a.high, a.low )
3298 : le128( a.high, a.low, b.high, b.low );
3299
3300}
3301
3302/*
3303-------------------------------------------------------------------------------
3304Returns 1 if the extended double-precision floating-point value `a' is
3305less than the corresponding value `b', and 0 otherwise. The comparison
3306is performed according to the IEC/IEEE Standard for Binary Floating-point
3307Arithmetic.
3308-------------------------------------------------------------------------------
3309*/
3310flag floatx80_lt( floatx80 a, floatx80 b )
3311{
3312 flag aSign, bSign;
3313
3314 if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )
3315 && (bits64) ( extractFloatx80Frac( a )<<1 ) )
3316 || ( ( extractFloatx80Exp( b ) == 0x7FFF )
3317 && (bits64) ( extractFloatx80Frac( b )<<1 ) )
3318 ) {
3319 float_raise( float_flag_invalid );
3320 return 0;
3321 }
3322 aSign = extractFloatx80Sign( a );
3323 bSign = extractFloatx80Sign( b );
3324 if ( aSign != bSign ) {
3325 return
3326 aSign
3327 && ( ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
3328 != 0 );
3329 }
3330 return
3331 aSign ? lt128( b.high, b.low, a.high, a.low )
3332 : lt128( a.high, a.low, b.high, b.low );
3333
3334}
3335
3336/*
3337-------------------------------------------------------------------------------
3338Returns 1 if the extended double-precision floating-point value `a' is equal
3339to the corresponding value `b', and 0 otherwise. The invalid exception is
3340raised if either operand is a NaN. Otherwise, the comparison is performed
3341according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
3342-------------------------------------------------------------------------------
3343*/
3344flag floatx80_eq_signaling( floatx80 a, floatx80 b )
3345{
3346
3347 if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )
3348 && (bits64) ( extractFloatx80Frac( a )<<1 ) )
3349 || ( ( extractFloatx80Exp( b ) == 0x7FFF )
3350 && (bits64) ( extractFloatx80Frac( b )<<1 ) )
3351 ) {
3352 float_raise( float_flag_invalid );
3353 return 0;
3354 }
3355 return
3356 ( a.low == b.low )
3357 && ( ( a.high == b.high )
3358 || ( ( a.low == 0 )
3359 && ( (bits16) ( ( a.high | b.high )<<1 ) == 0 ) )
3360 );
3361
3362}
3363
3364/*
3365-------------------------------------------------------------------------------
3366Returns 1 if the extended double-precision floating-point value `a' is less
3367than or equal to the corresponding value `b', and 0 otherwise. Quiet NaNs
3368do not cause an exception. Otherwise, the comparison is performed according
3369to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
3370-------------------------------------------------------------------------------
3371*/
3372flag floatx80_le_quiet( floatx80 a, floatx80 b )
3373{
3374 flag aSign, bSign;
3375
3376 if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )
3377 && (bits64) ( extractFloatx80Frac( a )<<1 ) )
3378 || ( ( extractFloatx80Exp( b ) == 0x7FFF )
3379 && (bits64) ( extractFloatx80Frac( b )<<1 ) )
3380 ) {
3381 if ( floatx80_is_signaling_nan( a )
3382 || floatx80_is_signaling_nan( b ) ) {
3383 float_raise( float_flag_invalid );
3384 }
3385 return 0;
3386 }
3387 aSign = extractFloatx80Sign( a );
3388 bSign = extractFloatx80Sign( b );
3389 if ( aSign != bSign ) {
3390 return
3391 aSign
3392 || ( ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
3393 == 0 );
3394 }
3395 return
3396 aSign ? le128( b.high, b.low, a.high, a.low )
3397 : le128( a.high, a.low, b.high, b.low );
3398
3399}
3400
3401/*
3402-------------------------------------------------------------------------------
3403Returns 1 if the extended double-precision floating-point value `a' is less
3404than the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause
3405an exception. Otherwise, the comparison is performed according to the
3406IEC/IEEE Standard for Binary Floating-point Arithmetic.
3407-------------------------------------------------------------------------------
3408*/
3409flag floatx80_lt_quiet( floatx80 a, floatx80 b )
3410{
3411 flag aSign, bSign;
3412
3413 if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )
3414 && (bits64) ( extractFloatx80Frac( a )<<1 ) )
3415 || ( ( extractFloatx80Exp( b ) == 0x7FFF )
3416 && (bits64) ( extractFloatx80Frac( b )<<1 ) )
3417 ) {
3418 if ( floatx80_is_signaling_nan( a )
3419 || floatx80_is_signaling_nan( b ) ) {
3420 float_raise( float_flag_invalid );
3421 }
3422 return 0;
3423 }
3424 aSign = extractFloatx80Sign( a );
3425 bSign = extractFloatx80Sign( b );
3426 if ( aSign != bSign ) {
3427 return
3428 aSign
3429 && ( ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
3430 != 0 );
3431 }
3432 return
3433 aSign ? lt128( b.high, b.low, a.high, a.low )
3434 : lt128( a.high, a.low, b.high, b.low );
3435
3436}
3437
3438#endif
3439
diff --git a/arch/arm26/nwfpe/softfloat.h b/arch/arm26/nwfpe/softfloat.h
new file mode 100644
index 000000000000..22c2193a4997
--- /dev/null
+++ b/arch/arm26/nwfpe/softfloat.h
@@ -0,0 +1,232 @@
1
2/*
3===============================================================================
4
5This C header file is part of the SoftFloat IEC/IEEE Floating-point
6Arithmetic Package, Release 2.
7
8Written by John R. Hauser. This work was made possible in part by the
9International Computer Science Institute, located at Suite 600, 1947 Center
10Street, Berkeley, California 94704. Funding was partially provided by the
11National Science Foundation under grant MIP-9311980. The original version
12of this code was written as part of a project to build a fixed-point vector
13processor in collaboration with the University of California at Berkeley,
14overseen by Profs. Nelson Morgan and John Wawrzynek. More information
15is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
16arithmetic/softfloat.html'.
17
18THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
19has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
20TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
21PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
22AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
23
24Derivative works are acceptable, even for commercial purposes, so long as
25(1) they include prominent notice that the work is derivative, and (2) they
26include prominent notice akin to these three paragraphs for those parts of
27this code that are retained.
28
29===============================================================================
30*/
31
32#ifndef __SOFTFLOAT_H__
33#define __SOFTFLOAT_H__
34
35/*
36-------------------------------------------------------------------------------
37The macro `FLOATX80' must be defined to enable the extended double-precision
38floating-point format `floatx80'. If this macro is not defined, the
39`floatx80' type will not be defined, and none of the functions that either
40input or output the `floatx80' type will be defined.
41-------------------------------------------------------------------------------
42*/
43#define FLOATX80
44
45/*
46-------------------------------------------------------------------------------
47Software IEC/IEEE floating-point types.
48-------------------------------------------------------------------------------
49*/
50typedef unsigned long int float32;
51typedef unsigned long long float64;
52typedef struct {
53 unsigned short high;
54 unsigned long long low;
55} floatx80;
56
57/*
58-------------------------------------------------------------------------------
59Software IEC/IEEE floating-point underflow tininess-detection mode.
60-------------------------------------------------------------------------------
61*/
62extern signed char float_detect_tininess;
63enum {
64 float_tininess_after_rounding = 0,
65 float_tininess_before_rounding = 1
66};
67
68/*
69-------------------------------------------------------------------------------
70Software IEC/IEEE floating-point rounding mode.
71-------------------------------------------------------------------------------
72*/
73extern signed char float_rounding_mode;
74enum {
75 float_round_nearest_even = 0,
76 float_round_to_zero = 1,
77 float_round_down = 2,
78 float_round_up = 3
79};
80
81/*
82-------------------------------------------------------------------------------
83Software IEC/IEEE floating-point exception flags.
84-------------------------------------------------------------------------------
85extern signed char float_exception_flags;
86enum {
87 float_flag_inexact = 1,
88 float_flag_underflow = 2,
89 float_flag_overflow = 4,
90 float_flag_divbyzero = 8,
91 float_flag_invalid = 16
92};
93
94ScottB: November 4, 1998
95Changed the enumeration to match the bit order in the FPA11.
96*/
97
98extern signed char float_exception_flags;
99enum {
100 float_flag_invalid = 1,
101 float_flag_divbyzero = 2,
102 float_flag_overflow = 4,
103 float_flag_underflow = 8,
104 float_flag_inexact = 16
105};
106
107/*
108-------------------------------------------------------------------------------
109Routine to raise any or all of the software IEC/IEEE floating-point
110exception flags.
111-------------------------------------------------------------------------------
112*/
113void float_raise( signed char );
114
115/*
116-------------------------------------------------------------------------------
117Software IEC/IEEE integer-to-floating-point conversion routines.
118-------------------------------------------------------------------------------
119*/
120float32 int32_to_float32( signed int );
121float64 int32_to_float64( signed int );
122#ifdef FLOATX80
123floatx80 int32_to_floatx80( signed int );
124#endif
125
126/*
127-------------------------------------------------------------------------------
128Software IEC/IEEE single-precision conversion routines.
129-------------------------------------------------------------------------------
130*/
131signed int float32_to_int32( float32 );
132signed int float32_to_int32_round_to_zero( float32 );
133float64 float32_to_float64( float32 );
134#ifdef FLOATX80
135floatx80 float32_to_floatx80( float32 );
136#endif
137
138/*
139-------------------------------------------------------------------------------
140Software IEC/IEEE single-precision operations.
141-------------------------------------------------------------------------------
142*/
143float32 float32_round_to_int( float32 );
144float32 float32_add( float32, float32 );
145float32 float32_sub( float32, float32 );
146float32 float32_mul( float32, float32 );
147float32 float32_div( float32, float32 );
148float32 float32_rem( float32, float32 );
149float32 float32_sqrt( float32 );
150char float32_eq( float32, float32 );
151char float32_le( float32, float32 );
152char float32_lt( float32, float32 );
153char float32_eq_signaling( float32, float32 );
154char float32_le_quiet( float32, float32 );
155char float32_lt_quiet( float32, float32 );
156char float32_is_signaling_nan( float32 );
157
158/*
159-------------------------------------------------------------------------------
160Software IEC/IEEE double-precision conversion routines.
161-------------------------------------------------------------------------------
162*/
163signed int float64_to_int32( float64 );
164signed int float64_to_int32_round_to_zero( float64 );
165float32 float64_to_float32( float64 );
166#ifdef FLOATX80
167floatx80 float64_to_floatx80( float64 );
168#endif
169
170/*
171-------------------------------------------------------------------------------
172Software IEC/IEEE double-precision operations.
173-------------------------------------------------------------------------------
174*/
175float64 float64_round_to_int( float64 );
176float64 float64_add( float64, float64 );
177float64 float64_sub( float64, float64 );
178float64 float64_mul( float64, float64 );
179float64 float64_div( float64, float64 );
180float64 float64_rem( float64, float64 );
181float64 float64_sqrt( float64 );
182char float64_eq( float64, float64 );
183char float64_le( float64, float64 );
184char float64_lt( float64, float64 );
185char float64_eq_signaling( float64, float64 );
186char float64_le_quiet( float64, float64 );
187char float64_lt_quiet( float64, float64 );
188char float64_is_signaling_nan( float64 );
189
190#ifdef FLOATX80
191
192/*
193-------------------------------------------------------------------------------
194Software IEC/IEEE extended double-precision conversion routines.
195-------------------------------------------------------------------------------
196*/
197signed int floatx80_to_int32( floatx80 );
198signed int floatx80_to_int32_round_to_zero( floatx80 );
199float32 floatx80_to_float32( floatx80 );
200float64 floatx80_to_float64( floatx80 );
201
202/*
203-------------------------------------------------------------------------------
204Software IEC/IEEE extended double-precision rounding precision. Valid
205values are 32, 64, and 80.
206-------------------------------------------------------------------------------
207*/
208extern signed char floatx80_rounding_precision;
209
210/*
211-------------------------------------------------------------------------------
212Software IEC/IEEE extended double-precision operations.
213-------------------------------------------------------------------------------
214*/
215floatx80 floatx80_round_to_int( floatx80 );
216floatx80 floatx80_add( floatx80, floatx80 );
217floatx80 floatx80_sub( floatx80, floatx80 );
218floatx80 floatx80_mul( floatx80, floatx80 );
219floatx80 floatx80_div( floatx80, floatx80 );
220floatx80 floatx80_rem( floatx80, floatx80 );
221floatx80 floatx80_sqrt( floatx80 );
222char floatx80_eq( floatx80, floatx80 );
223char floatx80_le( floatx80, floatx80 );
224char floatx80_lt( floatx80, floatx80 );
225char floatx80_eq_signaling( floatx80, floatx80 );
226char floatx80_le_quiet( floatx80, floatx80 );
227char floatx80_lt_quiet( floatx80, floatx80 );
228char floatx80_is_signaling_nan( floatx80 );
229
230#endif
231
232#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 18:09:33 -0500