diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
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committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/arm26/machine/irq.c |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'arch/arm26/machine/irq.c')
-rw-r--r-- | arch/arm26/machine/irq.c | 165 |
1 files changed, 165 insertions, 0 deletions
diff --git a/arch/arm26/machine/irq.c b/arch/arm26/machine/irq.c new file mode 100644 index 000000000000..4361863f7ed2 --- /dev/null +++ b/arch/arm26/machine/irq.c | |||
@@ -0,0 +1,165 @@ | |||
1 | /* | ||
2 | * linux/arch/arm26/mach-arc/irq.c | ||
3 | * | ||
4 | * Copyright (C) 1996 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * Changelog: | ||
11 | * 24-09-1996 RMK Created | ||
12 | * 10-10-1996 RMK Brought up to date with arch-sa110eval | ||
13 | * 22-10-1996 RMK Changed interrupt numbers & uses new inb/outb macros | ||
14 | * 11-01-1998 RMK Added mask_and_ack_irq | ||
15 | * 22-08-1998 RMK Restructured IRQ routines | ||
16 | * 08-09-2002 IM Brought up to date for 2.5 | ||
17 | * 01-06-2003 JMA Removed arc_fiq_chip | ||
18 | */ | ||
19 | #include <linux/config.h> | ||
20 | #include <linux/init.h> | ||
21 | |||
22 | #include <asm/irq.h> | ||
23 | #include <asm/irqchip.h> | ||
24 | #include <asm/ioc.h> | ||
25 | #include <asm/io.h> | ||
26 | #include <asm/system.h> | ||
27 | |||
28 | extern void init_FIQ(void); | ||
29 | |||
30 | #define a_clf() clf() | ||
31 | #define a_stf() stf() | ||
32 | |||
33 | static void arc_ack_irq_a(unsigned int irq) | ||
34 | { | ||
35 | unsigned int val, mask; | ||
36 | |||
37 | mask = 1 << irq; | ||
38 | a_clf(); | ||
39 | val = ioc_readb(IOC_IRQMASKA); | ||
40 | ioc_writeb(val & ~mask, IOC_IRQMASKA); | ||
41 | ioc_writeb(mask, IOC_IRQCLRA); | ||
42 | a_stf(); | ||
43 | } | ||
44 | |||
45 | static void arc_mask_irq_a(unsigned int irq) | ||
46 | { | ||
47 | unsigned int val, mask; | ||
48 | |||
49 | mask = 1 << irq; | ||
50 | a_clf(); | ||
51 | val = ioc_readb(IOC_IRQMASKA); | ||
52 | ioc_writeb(val & ~mask, IOC_IRQMASKA); | ||
53 | a_stf(); | ||
54 | } | ||
55 | |||
56 | static void arc_unmask_irq_a(unsigned int irq) | ||
57 | { | ||
58 | unsigned int val, mask; | ||
59 | |||
60 | mask = 1 << irq; | ||
61 | a_clf(); | ||
62 | val = ioc_readb(IOC_IRQMASKA); | ||
63 | ioc_writeb(val | mask, IOC_IRQMASKA); | ||
64 | a_stf(); | ||
65 | } | ||
66 | |||
67 | static struct irqchip arc_a_chip = { | ||
68 | .ack = arc_ack_irq_a, | ||
69 | .mask = arc_mask_irq_a, | ||
70 | .unmask = arc_unmask_irq_a, | ||
71 | }; | ||
72 | |||
73 | static void arc_mask_irq_b(unsigned int irq) | ||
74 | { | ||
75 | unsigned int val, mask; | ||
76 | mask = 1 << (irq & 7); | ||
77 | val = ioc_readb(IOC_IRQMASKB); | ||
78 | ioc_writeb(val & ~mask, IOC_IRQMASKB); | ||
79 | } | ||
80 | |||
81 | static void arc_unmask_irq_b(unsigned int irq) | ||
82 | { | ||
83 | unsigned int val, mask; | ||
84 | |||
85 | mask = 1 << (irq & 7); | ||
86 | val = ioc_readb(IOC_IRQMASKB); | ||
87 | ioc_writeb(val | mask, IOC_IRQMASKB); | ||
88 | } | ||
89 | |||
90 | static struct irqchip arc_b_chip = { | ||
91 | .ack = arc_mask_irq_b, | ||
92 | .mask = arc_mask_irq_b, | ||
93 | .unmask = arc_unmask_irq_b, | ||
94 | }; | ||
95 | |||
96 | /* FIXME - JMA none of these functions are used in arm26 currently | ||
97 | static void arc_mask_irq_fiq(unsigned int irq) | ||
98 | { | ||
99 | unsigned int val, mask; | ||
100 | |||
101 | mask = 1 << (irq & 7); | ||
102 | val = ioc_readb(IOC_FIQMASK); | ||
103 | ioc_writeb(val & ~mask, IOC_FIQMASK); | ||
104 | } | ||
105 | |||
106 | static void arc_unmask_irq_fiq(unsigned int irq) | ||
107 | { | ||
108 | unsigned int val, mask; | ||
109 | |||
110 | mask = 1 << (irq & 7); | ||
111 | val = ioc_readb(IOC_FIQMASK); | ||
112 | ioc_writeb(val | mask, IOC_FIQMASK); | ||
113 | } | ||
114 | |||
115 | static struct irqchip arc_fiq_chip = { | ||
116 | .ack = arc_mask_irq_fiq, | ||
117 | .mask = arc_mask_irq_fiq, | ||
118 | .unmask = arc_unmask_irq_fiq, | ||
119 | }; | ||
120 | */ | ||
121 | |||
122 | void __init arc_init_irq(void) | ||
123 | { | ||
124 | unsigned int irq, flags; | ||
125 | |||
126 | /* Disable all IOC interrupt sources */ | ||
127 | ioc_writeb(0, IOC_IRQMASKA); | ||
128 | ioc_writeb(0, IOC_IRQMASKB); | ||
129 | ioc_writeb(0, IOC_FIQMASK); | ||
130 | |||
131 | for (irq = 0; irq < NR_IRQS; irq++) { | ||
132 | flags = IRQF_VALID; | ||
133 | |||
134 | if (irq <= 6 || (irq >= 9 && irq <= 15)) | ||
135 | flags |= IRQF_PROBE; | ||
136 | |||
137 | if (irq == IRQ_KEYBOARDTX) | ||
138 | flags |= IRQF_NOAUTOEN; | ||
139 | |||
140 | switch (irq) { | ||
141 | case 0 ... 7: | ||
142 | set_irq_chip(irq, &arc_a_chip); | ||
143 | set_irq_handler(irq, do_level_IRQ); | ||
144 | set_irq_flags(irq, flags); | ||
145 | break; | ||
146 | |||
147 | case 8 ... 15: | ||
148 | set_irq_chip(irq, &arc_b_chip); | ||
149 | set_irq_handler(irq, do_level_IRQ); | ||
150 | set_irq_flags(irq, flags); | ||
151 | |||
152 | /* case 64 ... 72: | ||
153 | set_irq_chip(irq, &arc_fiq_chip); | ||
154 | set_irq_flags(irq, flags); | ||
155 | break; | ||
156 | */ | ||
157 | |||
158 | } | ||
159 | } | ||
160 | |||
161 | irq_desc[IRQ_KEYBOARDTX].noautoenable = 1; | ||
162 | |||
163 | init_FIQ(); | ||
164 | } | ||
165 | |||