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authorCatalin Marinas <catalin.marinas@arm.com>2007-09-25 10:22:24 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-01-26 09:41:28 -0500
commit25ebee020bd34d1f4c5678538204f0b10bf9f6d5 (patch)
treeb9b04ddf0b9916922a3cba47a7f64f44cd0b28ff /arch/arm/vfp
parentc98929c07a01c9ec2e1e5253456acc7168da8b66 (diff)
[ARM] 4583/1: ARMv7: Add VFPv3 support
This patch adds the support for VFPv3 (the kernel currently supports VFPv2). The main difference is 32 double registers (compared to 16). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/vfp')
-rw-r--r--arch/arm/vfp/vfp.h4
-rw-r--r--arch/arm/vfp/vfphw.S22
-rw-r--r--arch/arm/vfp/vfpinstr.h6
3 files changed, 25 insertions, 7 deletions
diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h
index 791d0238c68f..c85860bad585 100644
--- a/arch/arm/vfp/vfp.h
+++ b/arch/arm/vfp/vfp.h
@@ -265,7 +265,11 @@ struct vfp_double {
265 * which returns (double)0.0. This is useful for the compare with 265 * which returns (double)0.0. This is useful for the compare with
266 * zero instructions. 266 * zero instructions.
267 */ 267 */
268#ifdef CONFIG_VFPv3
269#define VFP_REG_ZERO 32
270#else
268#define VFP_REG_ZERO 16 271#define VFP_REG_ZERO 16
272#endif
269extern u64 vfp_get_double(unsigned int reg); 273extern u64 vfp_get_double(unsigned int reg);
270extern void vfp_put_double(u64 val, unsigned int reg); 274extern void vfp_put_double(u64 val, unsigned int reg);
271 275
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index 53d9f8e8fac3..353f9e5c7919 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -99,12 +99,12 @@ vfp_support_entry:
99 DBGSTR1 "save old state %p", r4 99 DBGSTR1 "save old state %p", r4
100 cmp r4, #0 100 cmp r4, #0
101 beq no_old_VFP_process 101 beq no_old_VFP_process
102 VFPFSTMIA r4, r5 @ save the working registers
102 VFPFMRX r5, FPSCR @ current status 103 VFPFMRX r5, FPSCR @ current status
103 tst r1, #FPEXC_EX @ is there additional state to save? 104 tst r1, #FPEXC_EX @ is there additional state to save?
104 VFPFMRX r6, FPINST, NE @ FPINST (only if FPEXC.EX is set) 105 VFPFMRX r6, FPINST, NE @ FPINST (only if FPEXC.EX is set)
105 tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read? 106 tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read?
106 VFPFMRX r8, FPINST2, NE @ FPINST2 if needed (and present) 107 VFPFMRX r8, FPINST2, NE @ FPINST2 if needed (and present)
107 VFPFSTMIA r4 @ save the working registers
108 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 108 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
109 @ and point r4 at the word at the 109 @ and point r4 at the word at the
110 @ start of the register dump 110 @ start of the register dump
@@ -114,7 +114,7 @@ no_old_VFP_process:
114 DBGSTR1 "load state %p", r10 114 DBGSTR1 "load state %p", r10
115 str r10, [r3, r11, lsl #2] @ update the last_VFP_context pointer 115 str r10, [r3, r11, lsl #2] @ update the last_VFP_context pointer
116 @ Load the saved state back into the VFP 116 @ Load the saved state back into the VFP
117 VFPFLDMIA r10 @ reload the working registers while 117 VFPFLDMIA r10, r5 @ reload the working registers while
118 @ FPEXC is in a safe state 118 @ FPEXC is in a safe state
119 ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 119 ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
120 tst r1, #FPEXC_EX @ is there additional state to restore? 120 tst r1, #FPEXC_EX @ is there additional state to restore?
@@ -174,12 +174,12 @@ vfp_save_state:
174 @ r0 - save location 174 @ r0 - save location
175 @ r1 - FPEXC 175 @ r1 - FPEXC
176 DBGSTR1 "save VFP state %p", r0 176 DBGSTR1 "save VFP state %p", r0
177 VFPFSTMIA r0, r2 @ save the working registers
177 VFPFMRX r2, FPSCR @ current status 178 VFPFMRX r2, FPSCR @ current status
178 tst r1, #FPEXC_EX @ is there additional state to save? 179 tst r1, #FPEXC_EX @ is there additional state to save?
179 VFPFMRX r3, FPINST, NE @ FPINST (only if FPEXC.EX is set) 180 VFPFMRX r3, FPINST, NE @ FPINST (only if FPEXC.EX is set)
180 tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read? 181 tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read?
181 VFPFMRX r12, FPINST2, NE @ FPINST2 if needed (and present) 182 VFPFMRX r12, FPINST2, NE @ FPINST2 if needed (and present)
182 VFPFSTMIA r0 @ save the working registers
183 stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 183 stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
184 mov pc, lr 184 mov pc, lr
185#endif 185#endif
@@ -217,8 +217,15 @@ vfp_get_double:
217 fmrrd r0, r1, d\dr 217 fmrrd r0, r1, d\dr
218 mov pc, lr 218 mov pc, lr
219 .endr 219 .endr
220#ifdef CONFIG_VFPv3
221 @ d16 - d31 registers
222 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
223 mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
224 mov pc, lr
225 .endr
226#endif
220 227
221 @ virtual register 16 for compare with zero 228 @ virtual register 16 (or 32 if VFPv3) for compare with zero
222 mov r0, #0 229 mov r0, #0
223 mov r1, #0 230 mov r1, #0
224 mov pc, lr 231 mov pc, lr
@@ -231,3 +238,10 @@ vfp_put_double:
231 fmdrr d\dr, r0, r1 238 fmdrr d\dr, r0, r1
232 mov pc, lr 239 mov pc, lr
233 .endr 240 .endr
241#ifdef CONFIG_VFPv3
242 @ d16 - d31 registers
243 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
244 mcrr p11, 3, r1, r2, c\dr @ fmdrr r1, r2, d\dr
245 mov pc, lr
246 .endr
247#endif
diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h
index 7f343a4beca0..15b95b5ab97e 100644
--- a/arch/arm/vfp/vfpinstr.h
+++ b/arch/arm/vfp/vfpinstr.h
@@ -52,11 +52,11 @@
52#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) 52#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
53 53
54#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22) 54#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22)
55#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12) 55#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18)
56#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5) 56#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5)
57#define vfp_get_dm(inst) ((inst & 0x0000000f)) 57#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1)
58#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) 58#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
59#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16) 59#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3)
60 60
61#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00) 61#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
62 62