Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 3761/1: fix armv4t breakage after adding thumb interworking to userspace helpers
  [ARM] Add Integrator support for glibc outb() and friends
  [ARM] Move prototype for register_isa_ports to asm/io.h
  [ARM] Arrange for isa.c to use named initialisers
  [ARM] 3741/1: remove sa1111.c build warning on non-sa1100 systems
  [ARM] 3760/1: This patch adds timeouts while working with SSP registers. Such timeouts were en
  [ARM] 3758/1: Preserve signalling NaNs in conversion
  [ARM] 3749/3: Correct VFP single/double conversion emulation
  [ARM] 3748/3: Correct error check in vfp_raise_exceptions

4 files changed, 55 insertions, 22 deletions

diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h
index 4b97950984e9..5fbdf81a8aaf 100644
--- a/arch/arm/vfp/vfp.h
+++ b/arch/arm/vfp/vfp.h
@@ -353,3 +353,11 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand);
  * A special flag to tell the normalisation code not to normalise.
  */
 #define VFP_NAN_FLAG    0x100
+
+/*
+ * A bit pattern used to indicate the initial (unset) value of the
+ * exception mask, in case nothing handles an instruction.  This
+ * doesn't include the NAN flag, which get masked out before
+ * we check for an error.
+ */
+#define VFP_EXCEPTION_ERROR     ((u32)-1 & ~VFP_NAN_FLAG)
diff --git a/arch/arm/vfp/vfpdouble.c b/arch/arm/vfp/vfpdouble.c
index 009038c8113e..04bd3425b29b 100644
--- a/arch/arm/vfp/vfpdouble.c
+++ b/arch/arm/vfp/vfpdouble.c
@@ -465,7 +465,7 @@ static u32 vfp_double_fcvts(int sd, int unused, int dm, u32 fpscr)
          */
         if (tm & (VFP_INFINITY|VFP_NAN)) {
                 vsd.exponent = 255;
-                if (tm & VFP_NAN)
+                if (tm == VFP_QNAN)
                         vsd.significand |= VFP_SINGLE_SIGNIFICAND_QNAN;
                 goto pack_nan;
         } else if (tm & VFP_ZERO)
@@ -1127,7 +1127,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
 {
         u32 op = inst & FOP_MASK;
         u32 exceptions = 0;
-        unsigned int dd = vfp_get_dd(inst);
+        unsigned int dest;
         unsigned int dn = vfp_get_dn(inst);
         unsigned int dm = vfp_get_dm(inst);
         unsigned int vecitr, veclen, vecstride;
@@ -1137,10 +1137,20 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
         vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2;
 
         /*
+         * fcvtds takes an sN register number as destination, not dN.
+         * It also always operates on scalars.
+         */
+        if ((inst & FEXT_MASK) == FEXT_FCVT) {
+                veclen = 0;
+                dest = vfp_get_sd(inst);
+        } else
+                dest = vfp_get_dd(inst);
+
+        /*
          * If destination bank is zero, vector length is always '1'.
          * ARM DDI0100F C5.1.3, C5.3.2.
          */
-        if (FREG_BANK(dd) == 0)
+        if (FREG_BANK(dest) == 0)
                 veclen = 0;
 
         pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride,
@@ -1153,16 +1163,20 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
         for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) {
                 u32 except;
 
-                if (op == FOP_EXT)
+                if (op == FOP_EXT && (inst & FEXT_MASK) == FEXT_FCVT)
+                        pr_debug("VFP: itr%d (s%u) = op[%u] (d%u)\n",
+                                 vecitr >> FPSCR_LENGTH_BIT,
+                                 dest, dn, dm);
+                else if (op == FOP_EXT)
                         pr_debug("VFP: itr%d (d%u) = op[%u] (d%u)\n",
                                  vecitr >> FPSCR_LENGTH_BIT,
-                                 dd, dn, dm);
+                                 dest, dn, dm);
                 else
                         pr_debug("VFP: itr%d (d%u) = (d%u) op[%u] (d%u)\n",
                                  vecitr >> FPSCR_LENGTH_BIT,
-                                 dd, dn, FOP_TO_IDX(op), dm);
+                                 dest, dn, FOP_TO_IDX(op), dm);
 
-                except = fop(dd, dn, dm, fpscr);
+                except = fop(dest, dn, dm, fpscr);
                 pr_debug("VFP: itr%d: exceptions=%08x\n",
                          vecitr >> FPSCR_LENGTH_BIT, except);
 
@@ -1180,7 +1194,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
                  * we encounter an exception.  We continue.
                  */
 
-                dd = FREG_BANK(dd) + ((FREG_IDX(dd) + vecstride) & 6);
+                dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 6);
                 dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6);
                 if (FREG_BANK(dm) != 0)
                         dm = FREG_BANK(dm) + ((FREG_IDX(dm) + vecstride) & 6);
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 9d265d5e748c..4178f6cc3d37 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -131,7 +131,7 @@ static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_
 
         pr_debug("VFP: raising exceptions %08x\n", exceptions);
 
-        if (exceptions == (u32)-1) {
+        if (exceptions == VFP_EXCEPTION_ERROR) {
                 vfp_panic("unhandled bounce");
                 vfp_raise_sigfpe(0, regs);
                 return;
@@ -170,7 +170,7 @@ static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_
  */
 static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs)
 {
-        u32 exceptions = (u32)-1;
+        u32 exceptions = VFP_EXCEPTION_ERROR;
 
         pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr);
 
diff --git a/arch/arm/vfp/vfpsingle.c b/arch/arm/vfp/vfpsingle.c
index dae2c2f46052..78d7cac5f36b 100644
--- a/arch/arm/vfp/vfpsingle.c
+++ b/arch/arm/vfp/vfpsingle.c
@@ -506,7 +506,7 @@ static u32 vfp_single_fcvtd(int dd, int unused, s32 m, u32 fpscr)
          */
         if (tm & (VFP_INFINITY|VFP_NAN)) {
                 vdd.exponent = 2047;
-                if (tm & VFP_NAN)
+                if (tm == VFP_QNAN)
                         vdd.significand |= VFP_DOUBLE_SIGNIFICAND_QNAN;
                 goto pack_nan;
         } else if (tm & VFP_ZERO)
@@ -514,10 +514,6 @@ static u32 vfp_single_fcvtd(int dd, int unused, s32 m, u32 fpscr)
         else
                 vdd.exponent = vsm.exponent + (1023 - 127);
 
-        /*
-         * Technically, if bit 0 of dd is set, this is an invalid
-         * instruction.  However, we ignore this for efficiency.
-         */
         return vfp_double_normaliseround(dd, &vdd, fpscr, exceptions, "fcvtd");
 
  pack_nan:
@@ -1174,7 +1170,7 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
 {
         u32 op = inst & FOP_MASK;
         u32 exceptions = 0;
-        unsigned int sd = vfp_get_sd(inst);
+        unsigned int dest;
         unsigned int sn = vfp_get_sn(inst);
         unsigned int sm = vfp_get_sm(inst);
         unsigned int vecitr, veclen, vecstride;
@@ -1184,10 +1180,22 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
         vecstride = 1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK);
 
         /*
+         * fcvtsd takes a dN register number as destination, not sN.
+         * Technically, if bit 0 of dd is set, this is an invalid
+         * instruction.  However, we ignore this for efficiency.
+         * It also only operates on scalars.
+         */
+        if ((inst & FEXT_MASK) == FEXT_FCVT) {
+                veclen = 0;
+                dest = vfp_get_dd(inst);
+        } else
+                dest = vfp_get_sd(inst);
+
+        /*
          * If destination bank is zero, vector length is always '1'.
          * ARM DDI0100F C5.1.3, C5.3.2.
          */
-        if (FREG_BANK(sd) == 0)
+        if (FREG_BANK(dest) == 0)
                 veclen = 0;
 
         pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride,
@@ -1201,15 +1209,18 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
                 s32 m = vfp_get_float(sm);
                 u32 except;
 
-                if (op == FOP_EXT)
+                if (op == FOP_EXT && (inst & FEXT_MASK) == FEXT_FCVT)
+                        pr_debug("VFP: itr%d (d%u) = op[%u] (s%u=%08x)\n",
+                                 vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m);
+                else if (op == FOP_EXT)
                         pr_debug("VFP: itr%d (s%u) = op[%u] (s%u=%08x)\n",
-                                 vecitr >> FPSCR_LENGTH_BIT, sd, sn, sm, m);
+                                 vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m);
                 else
                         pr_debug("VFP: itr%d (s%u) = (s%u) op[%u] (s%u=%08x)\n",
-                                 vecitr >> FPSCR_LENGTH_BIT, sd, sn,
+                                 vecitr >> FPSCR_LENGTH_BIT, dest, sn,
                                  FOP_TO_IDX(op), sm, m);
 
-                except = fop(sd, sn, m, fpscr);
+                except = fop(dest, sn, m, fpscr);
                 pr_debug("VFP: itr%d: exceptions=%08x\n",
                          vecitr >> FPSCR_LENGTH_BIT, except);
 
@@ -1227,7 +1238,7 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
                  * we encounter an exception.  We continue.
                  */
 
-                sd = FREG_BANK(sd) + ((FREG_IDX(sd) + vecstride) & 7);
+                dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 7);
                 sn = FREG_BANK(sn) + ((FREG_IDX(sn) + vecstride) & 7);
                 if (FREG_BANK(sm) != 0)
                         sm = FREG_BANK(sm) + ((FREG_IDX(sm) + vecstride) & 7);