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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-06-21 08:51:41 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-22 05:24:24 -0400
commit1a6be26d5b1a86f66ef60e5b73bae64d50873724 (patch)
treec56cc8ed28d9d9dc062043a0a7862e1692908770 /arch/arm/vfp
parentd6551e884cf66de072b81f8b6d23259462c40baf (diff)
[ARM] Enable VFP to be built when non-VFP capable CPUs are selected
Since we pass flags to the compiler to control code generation based on the least capable selected CPU, if we want to include VFP support, we must tweak the assembler flags to allow the VFP instructions. Moreover, we must not use the mrrc/mcrr versions since these will not be recognised by the assembler. We do not convert all instructions to the VFP-equivalent (yet) since binutils appears to barf on "fmrx rn, fpinst" and doesn't provide any other way (other than using the mrc equivalent) to encode this instruction - which is rather a problem when you have a VFP implementation which requires these instructions. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/vfp')
-rw-r--r--arch/arm/vfp/Makefile5
-rw-r--r--arch/arm/vfp/vfphw.S4
2 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/vfp/Makefile b/arch/arm/vfp/Makefile
index afabac31dd1d..7e136e77971a 100644
--- a/arch/arm/vfp/Makefile
+++ b/arch/arm/vfp/Makefile
@@ -7,6 +7,9 @@
7# EXTRA_CFLAGS := -DDEBUG 7# EXTRA_CFLAGS := -DDEBUG
8# EXTRA_AFLAGS := -DDEBUG 8# EXTRA_AFLAGS := -DDEBUG
9 9
10AFLAGS :=$(AFLAGS:-msoft-float=-Wa,-mfpu=softvfp+vfp)
11LDFLAGS +=--no-warn-mismatch
12
10obj-y += vfp.o 13obj-y += vfp.o
11 14
12vfp-$(CONFIG_VFP) += entry.o vfpmodule.o vfphw.o vfpsingle.o vfpdouble.o 15vfp-$(CONFIG_VFP) += vfpmodule.o entry.o vfphw.o vfpsingle.o vfpdouble.o
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index a3f65b47aea9..eb683cd77163 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -192,7 +192,7 @@ vfp_get_double:
192 add pc, pc, r0, lsl #3 192 add pc, pc, r0, lsl #3
193 mov r0, r0 193 mov r0, r0
194 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 194 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
195 mrrc p11, 1, r0, r1, c\dr @ fmrrd r0, r1, d\dr 195 fmrrd r0, r1, d\dr
196 mov pc, lr 196 mov pc, lr
197 .endr 197 .endr
198 198
@@ -206,6 +206,6 @@ vfp_put_double:
206 add pc, pc, r0, lsl #3 206 add pc, pc, r0, lsl #3
207 mov r0, r0 207 mov r0, r0
208 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 208 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
209 mcrr p11, 1, r1, r2, c\dr @ fmdrr r1, r2, d\dr 209 fmdrr d\dr, r1, r2
210 mov pc, lr 210 mov pc, lr
211 .endr 211 .endr