diff options
author | Hans J. Koch <hjk@linutronix.de> | 2010-09-17 12:13:56 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2010-09-17 15:55:07 -0400 |
commit | 83ef3338a2ae5d5bd9f5f6803b900b8067660054 (patch) | |
tree | a759da3a601d092889321cf49b9f003726147be1 /arch/arm/plat-tcc/include | |
parent | 509344b8b4d365b7ff3bce97198d83a57b7c3f31 (diff) |
ARM: Introduce plat-tcc
This patch introduces support for the tcc platform by creating an
arch/arm/plat-tcc and arch/arm/mach-tcc8k directories and adding
basic include files plus Kconfig and Makefile.
Signed-off-by: "Hans J. Koch" <hjk@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/plat-tcc/include')
-rw-r--r-- | arch/arm/plat-tcc/include/mach/debug-macro.S | 33 | ||||
-rw-r--r-- | arch/arm/plat-tcc/include/mach/entry-macro.S | 68 | ||||
-rw-r--r-- | arch/arm/plat-tcc/include/mach/hardware.h | 43 | ||||
-rw-r--r-- | arch/arm/plat-tcc/include/mach/memory.h | 18 | ||||
-rw-r--r-- | arch/arm/plat-tcc/include/mach/system.h | 31 | ||||
-rw-r--r-- | arch/arm/plat-tcc/include/mach/tcc8k-regs.h | 796 | ||||
-rw-r--r-- | arch/arm/plat-tcc/include/mach/uncompress.h | 34 | ||||
-rw-r--r-- | arch/arm/plat-tcc/include/mach/vmalloc.h | 10 |
8 files changed, 1033 insertions, 0 deletions
diff --git a/arch/arm/plat-tcc/include/mach/debug-macro.S b/arch/arm/plat-tcc/include/mach/debug-macro.S new file mode 100644 index 000000000000..97537845df64 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/debug-macro.S | |||
@@ -0,0 +1,33 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1994-1999 Russell King | ||
3 | * Copyright (C) 2008-2009 Telechips | ||
4 | * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | .macro addruart,rx,tmp | ||
13 | mrc p15, 0, \rx, c1, c0 | ||
14 | tst \rx, #1 @ MMU enabled? | ||
15 | moveq \rx, #0x90000000 @ physical base address | ||
16 | movne \rx, #0xF1000000 @ virtual base | ||
17 | orr \rx, \rx, #0x00007000 @ UART0 | ||
18 | .endm | ||
19 | |||
20 | .macro senduart,rd,rx | ||
21 | strb \rd, [\rx, #0x44] | ||
22 | .endm | ||
23 | |||
24 | .macro waituart,rd,rx | ||
25 | .endm | ||
26 | |||
27 | .macro busyuart,rd,rx | ||
28 | 1001: | ||
29 | ldr \rd, [\rx, #0x14] | ||
30 | tst \rd, #0x20 | ||
31 | |||
32 | beq 1001b | ||
33 | .endm | ||
diff --git a/arch/arm/plat-tcc/include/mach/entry-macro.S b/arch/arm/plat-tcc/include/mach/entry-macro.S new file mode 100644 index 000000000000..748f401e4b6d --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/entry-macro.S | |||
@@ -0,0 +1,68 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-tcc83x/entry-macro.S | ||
3 | * | ||
4 | * Author : <linux@telechips.com> | ||
5 | * Created: June 10, 2008 | ||
6 | * Description: Low-level IRQ helper macros for Telechips-based platforms | ||
7 | * | ||
8 | * Copyright (C) 2008-2009 Telechips | ||
9 | * | ||
10 | * This file is licensed under the terms of the GNU General Public | ||
11 | * License version 2. This program is licensed "as is" without any | ||
12 | * warranty of any kind, whether express or implied. | ||
13 | */ | ||
14 | |||
15 | #include <mach/hardware.h> | ||
16 | #include <mach/irqs.h> | ||
17 | |||
18 | .macro disable_fiq | ||
19 | .endm | ||
20 | |||
21 | .macro get_irqnr_preamble, base, tmp | ||
22 | .endm | ||
23 | |||
24 | .macro arch_ret_to_user, tmp1, tmp2 | ||
25 | .endm | ||
26 | |||
27 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
28 | |||
29 | ldr \base, =0xF2003000 @ base address of PIC registers | ||
30 | |||
31 | @@ read MREQ register of PIC0 | ||
32 | |||
33 | mov \irqnr, #0 | ||
34 | ldr \irqstat, [\base, #0x00000014 ] @ lower 32 interrupts | ||
35 | cmp \irqstat, #0 | ||
36 | bne 1001f | ||
37 | |||
38 | @@ read MREQ register of PIC1 | ||
39 | |||
40 | ldr \irqstat, [\base, #0x00000094] @ upper 32 interrupts | ||
41 | cmp \irqstat, #0 | ||
42 | beq 1002f | ||
43 | mov \irqnr, #0x20 | ||
44 | |||
45 | 1001: | ||
46 | movs \tmp, \irqstat, lsl #16 | ||
47 | movne \irqstat, \tmp | ||
48 | addeq \irqnr, \irqnr, #16 | ||
49 | |||
50 | movs \tmp, \irqstat, lsl #8 | ||
51 | movne \irqstat, \tmp | ||
52 | addeq \irqnr, \irqnr, #8 | ||
53 | |||
54 | movs \tmp, \irqstat, lsl #4 | ||
55 | movne \irqstat, \tmp | ||
56 | addeq \irqnr, \irqnr, #4 | ||
57 | |||
58 | movs \tmp, \irqstat, lsl #2 | ||
59 | movne \irqstat, \tmp | ||
60 | addeq \irqnr, \irqnr, #2 | ||
61 | |||
62 | movs \tmp, \irqstat, lsl #1 | ||
63 | addeq \irqnr, \irqnr, #1 | ||
64 | orrs \base, \base, #1 | ||
65 | 1002: | ||
66 | @@ exit here, Z flag unset if IRQ | ||
67 | |||
68 | .endm | ||
diff --git a/arch/arm/plat-tcc/include/mach/hardware.h b/arch/arm/plat-tcc/include/mach/hardware.h new file mode 100644 index 000000000000..e70d126ccaf3 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/hardware.h | |||
@@ -0,0 +1,43 @@ | |||
1 | /* | ||
2 | * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> | ||
3 | * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com> | ||
4 | * and Dirk Behme <dirk.behme@de.bosch.com> | ||
5 | * Rewritten by: <linux@telechips.com> | ||
6 | * Description: Hardware definitions for TCC8300 processors and boards | ||
7 | * | ||
8 | * Copyright (C) 2001 RidgeRun, Inc. | ||
9 | * Copyright (C) 2008-2009 Telechips | ||
10 | * | ||
11 | * Modifications for mainline (C) 2009 Hans J. Koch <hjk@linutronix.de> | ||
12 | * | ||
13 | * Licensed under the terms of the GNU Pulic License version 2. | ||
14 | */ | ||
15 | |||
16 | #ifndef __ASM_ARCH_TCC_HARDWARE_H | ||
17 | #define __ASM_ARCH_TCC_HARDWARE_H | ||
18 | |||
19 | #include <asm/sizes.h> | ||
20 | #ifndef __ASSEMBLER__ | ||
21 | #include <asm/types.h> | ||
22 | #endif | ||
23 | #include <mach/io.h> | ||
24 | |||
25 | /* | ||
26 | * ---------------------------------------------------------------------------- | ||
27 | * Clocks | ||
28 | * ---------------------------------------------------------------------------- | ||
29 | */ | ||
30 | #define CLKGEN_REG_BASE 0xfffece00 | ||
31 | #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) | ||
32 | #define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) | ||
33 | #define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) | ||
34 | #define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) | ||
35 | #define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) | ||
36 | #define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) | ||
37 | #define ARM_SYSST (CLKGEN_REG_BASE + 0x18) | ||
38 | #define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) | ||
39 | |||
40 | /* DPLL control registers */ | ||
41 | #define DPLL_CTL 0xfffecf00 | ||
42 | |||
43 | #endif /* __ASM_ARCH_TCC_HARDWARE_H */ | ||
diff --git a/arch/arm/plat-tcc/include/mach/memory.h b/arch/arm/plat-tcc/include/mach/memory.h new file mode 100644 index 000000000000..cd91ba8a670b --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/memory.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1999 ARM Limited | ||
3 | * Copyright (C) 2000 RidgeRun, Inc. | ||
4 | * Copyright (C) 2008-2009 Telechips | ||
5 | * Copyright (C) 2010 Hans J. Koch <hjk@linutronix.de> | ||
6 | * | ||
7 | * Licensed under the terms of the GPL v2. | ||
8 | */ | ||
9 | |||
10 | #ifndef __ASM_ARCH_MEMORY_H | ||
11 | #define __ASM_ARCH_MEMORY_H | ||
12 | |||
13 | /* | ||
14 | * Physical DRAM offset. | ||
15 | */ | ||
16 | #define PHYS_OFFSET UL(0x20000000) | ||
17 | |||
18 | #endif | ||
diff --git a/arch/arm/plat-tcc/include/mach/system.h b/arch/arm/plat-tcc/include/mach/system.h new file mode 100644 index 000000000000..909e6035d843 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/system.h | |||
@@ -0,0 +1,31 @@ | |||
1 | /* | ||
2 | * Author: <linux@telechips.com> | ||
3 | * Created: June 10, 2008 | ||
4 | * Description: LINUX SYSTEM FUNCTIONS for TCC83x | ||
5 | * | ||
6 | * Copyright (C) 2008-2009 Telechips | ||
7 | * | ||
8 | * Licensed under the terms of the GPL v2. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_ARCH_SYSTEM_H | ||
13 | #define __ASM_ARCH_SYSTEM_H | ||
14 | #include <linux/clk.h> | ||
15 | |||
16 | #include <asm/mach-types.h> | ||
17 | #include <mach/hardware.h> | ||
18 | |||
19 | extern void plat_tcc_reboot(void); | ||
20 | |||
21 | static inline void arch_idle(void) | ||
22 | { | ||
23 | cpu_do_idle(); | ||
24 | } | ||
25 | |||
26 | static inline void arch_reset(char mode, const char *cmd) | ||
27 | { | ||
28 | plat_tcc_reboot(); | ||
29 | } | ||
30 | |||
31 | #endif | ||
diff --git a/arch/arm/plat-tcc/include/mach/tcc8k-regs.h b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h new file mode 100644 index 000000000000..f3243ebea463 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h | |||
@@ -0,0 +1,796 @@ | |||
1 | /* | ||
2 | * Telechips TCC8000 register definitions | ||
3 | * | ||
4 | * (C) 2009 Hans J. Koch <hjk@linutronix.de> | ||
5 | * | ||
6 | * Licensed under the terms of the GPLv2. | ||
7 | */ | ||
8 | |||
9 | #ifndef TCC8K_REGS_H | ||
10 | #define TCC8K_REGS_H | ||
11 | |||
12 | #include <linux/types.h> | ||
13 | |||
14 | #define EXT_SDRAM_BASE 0x20000000 | ||
15 | #define INT_SRAM_BASE 0x30000000 | ||
16 | #define INT_SRAM_SIZE SZ_32K | ||
17 | #define CS0_BASE 0x40000000 | ||
18 | #define CS1_BASE 0x50000000 | ||
19 | #define CS1_SIZE SZ_64K | ||
20 | #define CS2_BASE 0x60000000 | ||
21 | #define CS3_BASE 0x70000000 | ||
22 | #define AHB_PERI_BASE 0x80000000 | ||
23 | #define AHB_PERI_SIZE SZ_64K | ||
24 | #define APB0_PERI_BASE 0x90000000 | ||
25 | #define APB0_PERI_SIZE SZ_128K | ||
26 | #define APB1_PERI_BASE 0x98000000 | ||
27 | #define APB1_PERI_SIZE SZ_128K | ||
28 | #define DATA_TCM_BASE 0xa0000000 | ||
29 | #define DATA_TCM_SIZE SZ_8K | ||
30 | #define EXT_MEM_CTRL_BASE 0xf0000000 | ||
31 | #define EXT_MEM_CTRL_SIZE SZ_4K | ||
32 | |||
33 | #define CS1_BASE_VIRT 0xf7000000 | ||
34 | #define AHB_PERI_BASE_VIRT 0xf4000000 | ||
35 | #define APB0_PERI_BASE_VIRT 0xf1000000 | ||
36 | #define APB1_PERI_BASE_VIRT 0xf2000000 | ||
37 | #define EXT_MEM_CTRL_BASE_VIRT 0xf3000000 | ||
38 | #define INT_SRAM_BASE_VIRT 0xf5000000 | ||
39 | #define DATA_TCM_BASE_VIRT 0xf6000000 | ||
40 | |||
41 | #define __REG(x) (*((volatile u32 *)(x))) | ||
42 | |||
43 | /* USB Device Controller Registers */ | ||
44 | #define UDC_BASE (AHB_PERI_BASE_VIRT + 0x8000) | ||
45 | #define UDC_BASE_PHYS (AHB_PERI_BASE + 0x8000) | ||
46 | |||
47 | #define UDC_IR_OFFS 0x00 | ||
48 | #define UDC_EIR_OFFS 0x04 | ||
49 | #define UDC_EIER_OFFS 0x08 | ||
50 | #define UDC_FAR_OFFS 0x0c | ||
51 | #define UDC_FNR_OFFS 0x10 | ||
52 | #define UDC_EDR_OFFS 0x14 | ||
53 | #define UDC_RT_OFFS 0x18 | ||
54 | #define UDC_SSR_OFFS 0x1c | ||
55 | #define UDC_SCR_OFFS 0x20 | ||
56 | #define UDC_EP0SR_OFFS 0x24 | ||
57 | #define UDC_EP0CR_OFFS 0x28 | ||
58 | |||
59 | #define UDC_ESR_OFFS 0x2c | ||
60 | #define UDC_ECR_OFFS 0x30 | ||
61 | #define UDC_BRCR_OFFS 0x34 | ||
62 | #define UDC_BWCR_OFFS 0x38 | ||
63 | #define UDC_MPR_OFFS 0x3c | ||
64 | #define UDC_DCR_OFFS 0x40 | ||
65 | #define UDC_DTCR_OFFS 0x44 | ||
66 | #define UDC_DFCR_OFFS 0x48 | ||
67 | #define UDC_DTTCR1_OFFS 0x4c | ||
68 | #define UDC_DTTCR2_OFFS 0x50 | ||
69 | #define UDC_ESR2_OFFS 0x54 | ||
70 | |||
71 | #define UDC_SCR2_OFFS 0x58 | ||
72 | #define UDC_EP0BUF_OFFS 0x60 | ||
73 | #define UDC_EP1BUF_OFFS 0x64 | ||
74 | #define UDC_EP2BUF_OFFS 0x68 | ||
75 | #define UDC_EP3BUF_OFFS 0x6c | ||
76 | #define UDC_PLICR_OFFS 0xa0 | ||
77 | #define UDC_PCR_OFFS 0xa4 | ||
78 | |||
79 | #define UDC_UPCR0_OFFS 0xc8 | ||
80 | #define UDC_UPCR1_OFFS 0xcc | ||
81 | #define UDC_UPCR2_OFFS 0xd0 | ||
82 | #define UDC_UPCR3_OFFS 0xd4 | ||
83 | |||
84 | /* Bits in UDC_EIR */ | ||
85 | #define UDC_EIR_EP0I (1 << 0) | ||
86 | #define UDC_EIR_EP1I (1 << 1) | ||
87 | #define UDC_EIR_EP2I (1 << 2) | ||
88 | #define UDC_EIR_EP3I (1 << 3) | ||
89 | #define UDC_EIR_EPI_MASK 0x0f | ||
90 | |||
91 | /* Bits in UDC_EIER */ | ||
92 | #define UDC_EIER_EP0IE (1 << 0) | ||
93 | #define UDC_EIER_EP1IE (1 << 1) | ||
94 | #define UDC_EIER_EP2IE (1 << 2) | ||
95 | #define UDC_EIER_EP3IE (1 << 3) | ||
96 | |||
97 | /* Bits in UDC_FNR */ | ||
98 | #define UDC_FNR_FN_MASK 0x7ff | ||
99 | #define UDC_FNR_SM (1 << 13) | ||
100 | #define UDC_FNR_FTL (1 << 14) | ||
101 | |||
102 | /* Bits in UDC_SSR */ | ||
103 | #define UDC_SSR_HFRES (1 << 0) | ||
104 | #define UDC_SSR_HFSUSP (1 << 1) | ||
105 | #define UDC_SSR_HFRM (1 << 2) | ||
106 | #define UDC_SSR_SDE (1 << 3) | ||
107 | #define UDC_SSR_HSP (1 << 4) | ||
108 | #define UDC_SSR_DM (1 << 5) | ||
109 | #define UDC_SSR_DP (1 << 6) | ||
110 | #define UDC_SSR_TBM (1 << 7) | ||
111 | #define UDC_SSR_VBON (1 << 8) | ||
112 | #define UDC_SSR_VBOFF (1 << 9) | ||
113 | #define UDC_SSR_EOERR (1 << 10) | ||
114 | #define UDC_SSR_DCERR (1 << 11) | ||
115 | #define UDC_SSR_TCERR (1 << 12) | ||
116 | #define UDC_SSR_BSERR (1 << 13) | ||
117 | #define UDC_SSR_TMERR (1 << 14) | ||
118 | #define UDC_SSR_BAERR (1 << 15) | ||
119 | |||
120 | /* Bits in UDC_SCR */ | ||
121 | #define UDC_SCR_HRESE (1 << 0) | ||
122 | #define UDC_SCR_HSSPE (1 << 1) | ||
123 | #define UDC_SCR_RRDE (1 << 5) | ||
124 | #define UDC_SCR_SPDEN (1 << 6) | ||
125 | #define UDC_SCR_DIEN (1 << 12) | ||
126 | |||
127 | /* Bits in UDC_EP0SR */ | ||
128 | #define UDC_EP0SR_RSR (1 << 0) | ||
129 | #define UDC_EP0SR_TST (1 << 1) | ||
130 | #define UDC_EP0SR_SHT (1 << 4) | ||
131 | #define UDC_EP0SR_LWO (1 << 6) | ||
132 | |||
133 | /* Bits in UDC_EP0CR */ | ||
134 | #define UDC_EP0CR_ESS (1 << 1) | ||
135 | |||
136 | /* Bits in UDC_ESR */ | ||
137 | #define UDC_ESR_RPS (1 << 0) | ||
138 | #define UDC_ESR_TPS (1 << 1) | ||
139 | #define UDC_ESR_LWO (1 << 4) | ||
140 | #define UDC_ESR_FFS (1 << 6) | ||
141 | |||
142 | /* Bits in UDC_ECR */ | ||
143 | #define UDC_ECR_ESS (1 << 1) | ||
144 | #define UDC_ECR_CDP (1 << 2) | ||
145 | |||
146 | #define UDC_ECR_FLUSH (1 << 6) | ||
147 | #define UDC_ECR_DUEN (1 << 7) | ||
148 | |||
149 | /* Bits in UDC_UPCR0 */ | ||
150 | #define UDC_UPCR0_VBD (1 << 1) | ||
151 | #define UDC_UPCR0_VBDS (1 << 6) | ||
152 | #define UDC_UPCR0_RCD_12 (0x0 << 9) | ||
153 | #define UDC_UPCR0_RCD_24 (0x1 << 9) | ||
154 | #define UDC_UPCR0_RCD_48 (0x2 << 9) | ||
155 | #define UDC_UPCR0_RCS_EXT (0x1 << 11) | ||
156 | #define UDC_UPCR0_RCS_XTAL (0x0 << 11) | ||
157 | |||
158 | /* Bits in UDC_UPCR1 */ | ||
159 | #define UDC_UPCR1_CDT(x) ((x) << 0) | ||
160 | #define UDC_UPCR1_OTGT(x) ((x) << 3) | ||
161 | #define UDC_UPCR1_SQRXT(x) ((x) << 8) | ||
162 | #define UDC_UPCR1_TXFSLST(x) ((x) << 12) | ||
163 | |||
164 | /* Bits in UDC_UPCR2 */ | ||
165 | #define UDC_UPCR2_TP (1 << 0) | ||
166 | #define UDC_UPCR2_TXRT(x) ((x) << 2) | ||
167 | #define UDC_UPCR2_TXVRT(x) ((x) << 5) | ||
168 | #define UDC_UPCR2_OPMODE(x) ((x) << 9) | ||
169 | #define UDC_UPCR2_XCVRSEL(x) ((x) << 12) | ||
170 | #define UDC_UPCR2_TM (1 << 14) | ||
171 | |||
172 | /* USB Host Controller registers */ | ||
173 | #define USBH0_BASE (AHB_PERI_BASE_VIRT + 0xb000) | ||
174 | #define USBH1_BASE (AHB_PERI_BASE_VIRT + 0xb800) | ||
175 | |||
176 | #define OHCI_INT_ENABLE_OFFS 0x10 | ||
177 | |||
178 | #define RH_DESCRIPTOR_A_OFFS 0x48 | ||
179 | #define RH_DESCRIPTOR_B_OFFS 0x4c | ||
180 | |||
181 | #define USBHTCFG0_OFFS 0x100 | ||
182 | #define USBHHCFG0_OFFS 0x104 | ||
183 | #define USBHHCFG1_OFFS 0x104 | ||
184 | |||
185 | /* DMA controller registers */ | ||
186 | #define DMAC0_BASE (AHB_PERI_BASE + 0x4000) | ||
187 | #define DMAC1_BASE (AHB_PERI_BASE + 0xa000) | ||
188 | #define DMAC2_BASE (AHB_PERI_BASE + 0x4800) | ||
189 | #define DMAC3_BASE (AHB_PERI_BASE + 0xa800) | ||
190 | |||
191 | #define DMAC_CH_OFFSET(ch) (ch * 0x30) | ||
192 | |||
193 | #define ST_SADR_OFFS 0x00 | ||
194 | #define SPARAM_OFFS 0x04 | ||
195 | #define C_SADR_OFFS 0x0c | ||
196 | #define ST_DADR_OFFS 0x10 | ||
197 | #define DPARAM_OFFS 0x14 | ||
198 | #define C_DADR_OFFS 0x1c | ||
199 | #define HCOUNT_OFFS 0x20 | ||
200 | #define CHCTRL_OFFS 0x24 | ||
201 | #define RPTCTRL_OFFS 0x28 | ||
202 | #define EXTREQ_A_OFFS 0x2c | ||
203 | |||
204 | /* Bits in CHCTRL register */ | ||
205 | #define CHCTRL_EN (1 << 0) | ||
206 | |||
207 | #define CHCTRL_IEN (1 << 2) | ||
208 | #define CHCTRL_FLAG (1 << 3) | ||
209 | #define CHCTRL_WSIZE8 (0 << 4) | ||
210 | #define CHCTRL_WSIZE16 (1 << 4) | ||
211 | #define CHCTRL_WSIZE32 (2 << 4) | ||
212 | |||
213 | #define CHCTRL_BSIZE1 (0 << 6) | ||
214 | #define CHCTRL_BSIZE2 (1 << 6) | ||
215 | #define CHCTRL_BSIZE4 (2 << 6) | ||
216 | #define CHCTRL_BSIZE8 (3 << 6) | ||
217 | |||
218 | #define CHCTRL_TYPE_SINGLE_E (0 << 8) | ||
219 | #define CHCTRL_TYPE_HW (1 << 8) | ||
220 | #define CHCTRL_TYPE_SW (2 << 8) | ||
221 | #define CHCTRL_TYPE_SINGLE_L (3 << 8) | ||
222 | |||
223 | #define CHCTRL_BST (1 << 10) | ||
224 | |||
225 | /* Use DMA controller 0, channel 2 for USB */ | ||
226 | #define USB_DMA_BASE (DMAC0_BASE + DMAC_CH_OFFSET(2)) | ||
227 | |||
228 | /* NAND flash controller registers */ | ||
229 | #define NFC_BASE (AHB_PERI_BASE_VIRT + 0xd000) | ||
230 | #define NFC_BASE_PHYS (AHB_PERI_BASE + 0xd000) | ||
231 | |||
232 | #define NFC_CMD_OFFS 0x00 | ||
233 | #define NFC_LADDR_OFFS 0x04 | ||
234 | #define NFC_BADDR_OFFS 0x08 | ||
235 | #define NFC_SADDR_OFFS 0x0c | ||
236 | #define NFC_WDATA_OFFS 0x10 | ||
237 | #define NFC_LDATA_OFFS 0x20 | ||
238 | #define NFC_SDATA_OFFS 0x40 | ||
239 | #define NFC_CTRL_OFFS 0x50 | ||
240 | #define NFC_PSTART_OFFS 0x54 | ||
241 | #define NFC_RSTART_OFFS 0x58 | ||
242 | #define NFC_DSIZE_OFFS 0x5c | ||
243 | #define NFC_IREQ_OFFS 0x60 | ||
244 | #define NFC_RST_OFFS 0x64 | ||
245 | #define NFC_CTRL1_OFFS 0x68 | ||
246 | #define NFC_MDATA_OFFS 0x70 | ||
247 | |||
248 | #define NFC_WDATA_PHYS_ADDR (NFC_BASE_PHYS + NFC_WDATA_OFFS) | ||
249 | |||
250 | /* Bits in NFC_CTRL */ | ||
251 | #define NFC_CTRL_BHLD_MASK (0xf << 0) | ||
252 | #define NFC_CTRL_BPW_MASK (0xf << 4) | ||
253 | #define NFC_CTRL_BSTP_MASK (0xf << 8) | ||
254 | #define NFC_CTRL_CADDR_MASK (0x7 << 12) | ||
255 | #define NFC_CTRL_CADDR_1 (0x0 << 12) | ||
256 | #define NFC_CTRL_CADDR_2 (0x1 << 12) | ||
257 | #define NFC_CTRL_CADDR_3 (0x2 << 12) | ||
258 | #define NFC_CTRL_CADDR_4 (0x3 << 12) | ||
259 | #define NFC_CTRL_CADDR_5 (0x4 << 12) | ||
260 | #define NFC_CTRL_MSK (1 << 15) | ||
261 | #define NFC_CTRL_PSIZE256 (0 << 16) | ||
262 | #define NFC_CTRL_PSIZE512 (1 << 16) | ||
263 | #define NFC_CTRL_PSIZE1024 (2 << 16) | ||
264 | #define NFC_CTRL_PSIZE2048 (3 << 16) | ||
265 | #define NFC_CTRL_PSIZE4096 (4 << 16) | ||
266 | #define NFC_CTRL_PSIZE_MASK (7 << 16) | ||
267 | #define NFC_CTRL_BSIZE1 (0 << 19) | ||
268 | #define NFC_CTRL_BSIZE2 (1 << 19) | ||
269 | #define NFC_CTRL_BSIZE4 (2 << 19) | ||
270 | #define NFC_CTRL_BSIZE8 (3 << 19) | ||
271 | #define NFC_CTRL_BSIZE_MASK (3 << 19) | ||
272 | #define NFC_CTRL_RDY (1 << 21) | ||
273 | #define NFC_CTRL_CS0SEL (1 << 22) | ||
274 | #define NFC_CTRL_CS1SEL (1 << 23) | ||
275 | #define NFC_CTRL_CS2SEL (1 << 24) | ||
276 | #define NFC_CTRL_CS3SEL (1 << 25) | ||
277 | #define NFC_CTRL_CSMASK (0xf << 22) | ||
278 | #define NFC_CTRL_BW (1 << 26) | ||
279 | #define NFC_CTRL_FS (1 << 27) | ||
280 | #define NFC_CTRL_DEN (1 << 28) | ||
281 | #define NFC_CTRL_READ_IEN (1 << 29) | ||
282 | #define NFC_CTRL_PROG_IEN (1 << 30) | ||
283 | #define NFC_CTRL_RDY_IEN (1 << 31) | ||
284 | |||
285 | /* Bits in NFC_IREQ */ | ||
286 | #define NFC_IREQ_IRQ0 (1 << 0) | ||
287 | #define NFC_IREQ_IRQ1 (1 << 1) | ||
288 | #define NFC_IREQ_IRQ2 (1 << 2) | ||
289 | |||
290 | #define NFC_IREQ_FLAG0 (1 << 4) | ||
291 | #define NFC_IREQ_FLAG1 (1 << 5) | ||
292 | #define NFC_IREQ_FLAG2 (1 << 6) | ||
293 | |||
294 | /* MMC controller registers */ | ||
295 | #define MMC0_BASE (AHB_PERI_BASE_VIRT + 0xe000) | ||
296 | #define MMC1_BASE (AHB_PERI_BASE_VIRT + 0xe800) | ||
297 | |||
298 | /* UART base addresses */ | ||
299 | |||
300 | #define UART0_BASE (APB0_PERI_BASE_VIRT + 0x07000) | ||
301 | #define UART0_BASE_PHYS (APB0_PERI_BASE + 0x07000) | ||
302 | #define UART1_BASE (APB0_PERI_BASE_VIRT + 0x08000) | ||
303 | #define UART1_BASE_PHYS (APB0_PERI_BASE + 0x08000) | ||
304 | #define UART2_BASE (APB0_PERI_BASE_VIRT + 0x09000) | ||
305 | #define UART2_BASE_PHYS (APB0_PERI_BASE + 0x09000) | ||
306 | #define UART3_BASE (APB0_PERI_BASE_VIRT + 0x0a000) | ||
307 | #define UART3_BASE_PHYS (APB0_PERI_BASE + 0x0a000) | ||
308 | #define UART4_BASE (APB0_PERI_BASE_VIRT + 0x15000) | ||
309 | #define UART4_BASE_PHYS (APB0_PERI_BASE + 0x15000) | ||
310 | |||
311 | #define UART_BASE UART0_BASE | ||
312 | #define UART_BASE_PHYS UART0_BASE_PHYS | ||
313 | |||
314 | /* ECC controller */ | ||
315 | #define ECC_CTR_BASE (APB0_PERI_BASE_VIRT + 0xd000) | ||
316 | |||
317 | #define ECC_CTRL_OFFS 0x00 | ||
318 | #define ECC_BASE_OFFS 0x04 | ||
319 | #define ECC_MASK_OFFS 0x08 | ||
320 | #define ECC_CLEAR_OFFS 0x0c | ||
321 | #define ECC4_0_OFFS 0x10 | ||
322 | #define ECC4_1_OFFS 0x14 | ||
323 | |||
324 | #define ECC_EADDR0_OFFS 0x50 | ||
325 | |||
326 | #define ECC_ERRNUM_OFFS 0x90 | ||
327 | #define ECC_IREQ_OFFS 0x94 | ||
328 | |||
329 | /* Bits in ECC_CTRL */ | ||
330 | #define ECC_CTRL_ECC4_DIEN (1 << 28) | ||
331 | #define ECC_CTRL_ECC8_DIEN (1 << 29) | ||
332 | #define ECC_CTRL_ECC12_DIEN (1 << 30) | ||
333 | #define ECC_CTRL_ECC_DISABLE 0x0 | ||
334 | #define ECC_CTRL_ECC_SLC_ENC 0x8 | ||
335 | #define ECC_CTRL_ECC_SLC_DEC 0x9 | ||
336 | #define ECC_CTRL_ECC4_ENC 0xa | ||
337 | #define ECC_CTRL_ECC4_DEC 0xb | ||
338 | #define ECC_CTRL_ECC8_ENC 0xc | ||
339 | #define ECC_CTRL_ECC8_DEC 0xd | ||
340 | #define ECC_CTRL_ECC12_ENC 0xe | ||
341 | #define ECC_CTRL_ECC12_DEC 0xf | ||
342 | |||
343 | /* Bits in ECC_IREQ */ | ||
344 | #define ECC_IREQ_E4DI (1 << 4) | ||
345 | |||
346 | #define ECC_IREQ_E4DF (1 << 20) | ||
347 | #define ECC_IREQ_E4EF (1 << 21) | ||
348 | |||
349 | /* Interrupt controller */ | ||
350 | |||
351 | #define PIC0_BASE (APB1_PERI_BASE_VIRT + 0x3000) | ||
352 | #define PIC0_BASE_PHYS (APB1_PERI_BASE + 0x3000) | ||
353 | |||
354 | #define PIC0_IEN_OFFS 0x00 | ||
355 | #define PIC0_CREQ_OFFS 0x04 | ||
356 | #define PIC0_IREQ_OFFS 0x08 | ||
357 | #define PIC0_IRQSEL_OFFS 0x0c | ||
358 | #define PIC0_SRC_OFFS 0x10 | ||
359 | #define PIC0_MREQ_OFFS 0x14 | ||
360 | #define PIC0_TSTREQ_OFFS 0x18 | ||
361 | #define PIC0_POL_OFFS 0x1c | ||
362 | #define PIC0_IRQ_OFFS 0x20 | ||
363 | #define PIC0_FIQ_OFFS 0x24 | ||
364 | #define PIC0_MIRQ_OFFS 0x28 | ||
365 | #define PIC0_MFIQ_OFFS 0x2c | ||
366 | #define PIC0_TMODE_OFFS 0x30 | ||
367 | #define PIC0_SYNC_OFFS 0x34 | ||
368 | #define PIC0_WKUP_OFFS 0x38 | ||
369 | #define PIC0_TMODEA_OFFS 0x3c | ||
370 | #define PIC0_INTOEN_OFFS 0x40 | ||
371 | #define PIC0_MEN0_OFFS 0x44 | ||
372 | #define PIC0_MEN_OFFS 0x48 | ||
373 | |||
374 | #define PIC0_IEN __REG(PIC0_BASE + PIC0_IEN_OFFS) | ||
375 | #define PIC0_IEN_PHYS __REG(PIC0_BASE_PHYS + PIC0_IEN_OFFS) | ||
376 | #define PIC0_CREQ __REG(PIC0_BASE + PIC0_CREQ_OFFS) | ||
377 | #define PIC0_CREQ_PHYS __REG(PIC0_BASE_PHYS + PIC0_CREQ_OFFS) | ||
378 | #define PIC0_IREQ __REG(PIC0_BASE + PIC0_IREQ_OFFS) | ||
379 | #define PIC0_IRQSEL __REG(PIC0_BASE + PIC0_IRQSEL_OFFS) | ||
380 | #define PIC0_IRQSEL_PHYS __REG(PIC0_BASE_PHYS + PIC0_IRQSEL_OFFS) | ||
381 | #define PIC0_SRC __REG(PIC0_BASE + PIC0_SRC_OFFS) | ||
382 | #define PIC0_MREQ __REG(PIC0_BASE + PIC0_MREQ_OFFS) | ||
383 | #define PIC0_TSTREQ __REG(PIC0_BASE + PIC0_TSTREQ_OFFS) | ||
384 | #define PIC0_POL __REG(PIC0_BASE + PIC0_POL_OFFS) | ||
385 | #define PIC0_IRQ __REG(PIC0_BASE + PIC0_IRQ_OFFS) | ||
386 | #define PIC0_FIQ __REG(PIC0_BASE + PIC0_FIQ_OFFS) | ||
387 | #define PIC0_MIRQ __REG(PIC0_BASE + PIC0_MIRQ_OFFS) | ||
388 | #define PIC0_MFIQ __REG(PIC0_BASE + PIC0_MFIQ_OFFS) | ||
389 | #define PIC0_TMODE __REG(PIC0_BASE + PIC0_TMODE_OFFS) | ||
390 | #define PIC0_TMODE_PHYS __REG(PIC0_BASE_PHYS + PIC0_TMODE_OFFS) | ||
391 | #define PIC0_SYNC __REG(PIC0_BASE + PIC0_SYNC_OFFS) | ||
392 | #define PIC0_WKUP __REG(PIC0_BASE + PIC0_WKUP_OFFS) | ||
393 | #define PIC0_TMODEA __REG(PIC0_BASE + PIC0_TMODEA_OFFS) | ||
394 | #define PIC0_INTOEN __REG(PIC0_BASE + PIC0_INTOEN_OFFS) | ||
395 | #define PIC0_MEN0 __REG(PIC0_BASE + PIC0_MEN0_OFFS) | ||
396 | #define PIC0_MEN __REG(PIC0_BASE + PIC0_MEN_OFFS) | ||
397 | |||
398 | #define PIC1_BASE (APB1_PERI_BASE_VIRT + 0x3080) | ||
399 | |||
400 | #define PIC1_IEN_OFFS 0x00 | ||
401 | #define PIC1_CREQ_OFFS 0x04 | ||
402 | #define PIC1_IREQ_OFFS 0x08 | ||
403 | #define PIC1_IRQSEL_OFFS 0x0c | ||
404 | #define PIC1_SRC_OFFS 0x10 | ||
405 | #define PIC1_MREQ_OFFS 0x14 | ||
406 | #define PIC1_TSTREQ_OFFS 0x18 | ||
407 | #define PIC1_POL_OFFS 0x1c | ||
408 | #define PIC1_IRQ_OFFS 0x20 | ||
409 | #define PIC1_FIQ_OFFS 0x24 | ||
410 | #define PIC1_MIRQ_OFFS 0x28 | ||
411 | #define PIC1_MFIQ_OFFS 0x2c | ||
412 | #define PIC1_TMODE_OFFS 0x30 | ||
413 | #define PIC1_SYNC_OFFS 0x34 | ||
414 | #define PIC1_WKUP_OFFS 0x38 | ||
415 | #define PIC1_TMODEA_OFFS 0x3c | ||
416 | #define PIC1_INTOEN_OFFS 0x40 | ||
417 | #define PIC1_MEN1_OFFS 0x44 | ||
418 | #define PIC1_MEN_OFFS 0x48 | ||
419 | |||
420 | #define PIC1_IEN __REG(PIC1_BASE + PIC1_IEN_OFFS) | ||
421 | #define PIC1_CREQ __REG(PIC1_BASE + PIC1_CREQ_OFFS) | ||
422 | #define PIC1_IREQ __REG(PIC1_BASE + PIC1_IREQ_OFFS) | ||
423 | #define PIC1_IRQSEL __REG(PIC1_BASE + PIC1_IRQSEL_OFFS) | ||
424 | #define PIC1_SRC __REG(PIC1_BASE + PIC1_SRC_OFFS) | ||
425 | #define PIC1_MREQ __REG(PIC1_BASE + PIC1_MREQ_OFFS) | ||
426 | #define PIC1_TSTREQ __REG(PIC1_BASE + PIC1_TSTREQ_OFFS) | ||
427 | #define PIC1_POL __REG(PIC1_BASE + PIC1_POL_OFFS) | ||
428 | #define PIC1_IRQ __REG(PIC1_BASE + PIC1_IRQ_OFFS) | ||
429 | #define PIC1_FIQ __REG(PIC1_BASE + PIC1_FIQ_OFFS) | ||
430 | #define PIC1_MIRQ __REG(PIC1_BASE + PIC1_MIRQ_OFFS) | ||
431 | #define PIC1_MFIQ __REG(PIC1_BASE + PIC1_MFIQ_OFFS) | ||
432 | #define PIC1_TMODE __REG(PIC1_BASE + PIC1_TMODE_OFFS) | ||
433 | #define PIC1_SYNC __REG(PIC1_BASE + PIC1_SYNC_OFFS) | ||
434 | #define PIC1_WKUP __REG(PIC1_BASE + PIC1_WKUP_OFFS) | ||
435 | #define PIC1_TMODEA __REG(PIC1_BASE + PIC1_TMODEA_OFFS) | ||
436 | #define PIC1_INTOEN __REG(PIC1_BASE + PIC1_INTOEN_OFFS) | ||
437 | #define PIC1_MEN1 __REG(PIC1_BASE + PIC1_MEN1_OFFS) | ||
438 | #define PIC1_MEN __REG(PIC1_BASE + PIC1_MEN_OFFS) | ||
439 | |||
440 | /* Timer registers */ | ||
441 | #define TIMER_BASE (APB1_PERI_BASE_VIRT + 0x4000) | ||
442 | #define TIMER_BASE_PHYS (APB1_PERI_BASE + 0x4000) | ||
443 | |||
444 | #define TWDCFG_OFFS 0x70 | ||
445 | |||
446 | #define TC32EN_OFFS 0x80 | ||
447 | #define TC32LDV_OFFS 0x84 | ||
448 | #define TC32CMP0_OFFS 0x88 | ||
449 | #define TC32CMP1_OFFS 0x8c | ||
450 | #define TC32PCNT_OFFS 0x90 | ||
451 | #define TC32MCNT_OFFS 0x94 | ||
452 | #define TC32IRQ_OFFS 0x98 | ||
453 | |||
454 | /* Bits in TC32EN */ | ||
455 | #define TC32EN_PRESCALE_MASK 0x00ffffff | ||
456 | #define TC32EN_ENABLE (1 << 24) | ||
457 | #define TC32EN_LOADZERO (1 << 25) | ||
458 | #define TC32EN_STOPMODE (1 << 26) | ||
459 | #define TC32EN_LDM0 (1 << 28) | ||
460 | #define TC32EN_LDM1 (1 << 29) | ||
461 | |||
462 | /* Bits in TC32IRQ */ | ||
463 | #define TC32IRQ_MSTAT_MASK 0x0000001f | ||
464 | #define TC32IRQ_RSTAT_MASK (0x1f << 8) | ||
465 | #define TC32IRQ_IRQEN0 (1 << 16) | ||
466 | #define TC32IRQ_IRQEN1 (1 << 17) | ||
467 | #define TC32IRQ_IRQEN2 (1 << 18) | ||
468 | #define TC32IRQ_IRQEN3 (1 << 19) | ||
469 | #define TC32IRQ_IRQEN4 (1 << 20) | ||
470 | #define TC32IRQ_RSYNC (1 << 30) | ||
471 | #define TC32IRQ_IRQCLR (1 << 31) | ||
472 | |||
473 | /* GPIO registers */ | ||
474 | #define GPIOPD_BASE (APB1_PERI_BASE_VIRT + 0x5000) | ||
475 | |||
476 | #define GPIOPD_DAT_OFFS 0x00 | ||
477 | #define GPIOPD_DOE_OFFS 0x04 | ||
478 | #define GPIOPD_FS0_OFFS 0x08 | ||
479 | #define GPIOPD_FS1_OFFS 0x0c | ||
480 | #define GPIOPD_FS2_OFFS 0x10 | ||
481 | #define GPIOPD_RPU_OFFS 0x30 | ||
482 | #define GPIOPD_RPD_OFFS 0x34 | ||
483 | #define GPIOPD_DV0_OFFS 0x38 | ||
484 | #define GPIOPD_DV1_OFFS 0x3c | ||
485 | |||
486 | #define GPIOPS_BASE (APB1_PERI_BASE_VIRT + 0x5000) | ||
487 | |||
488 | #define GPIOPS_DAT_OFFS 0x40 | ||
489 | #define GPIOPS_DOE_OFFS 0x44 | ||
490 | #define GPIOPS_FS0_OFFS 0x48 | ||
491 | #define GPIOPS_FS1_OFFS 0x4c | ||
492 | #define GPIOPS_FS2_OFFS 0x50 | ||
493 | #define GPIOPS_FS3_OFFS 0x54 | ||
494 | #define GPIOPS_RPU_OFFS 0x70 | ||
495 | #define GPIOPS_RPD_OFFS 0x74 | ||
496 | #define GPIOPS_DV0_OFFS 0x78 | ||
497 | #define GPIOPS_DV1_OFFS 0x7c | ||
498 | |||
499 | #define GPIOPS_FS1_SDH0_BITS 0x000000ff | ||
500 | #define GPIOPS_FS1_SDH1_BITS 0x0000ff00 | ||
501 | |||
502 | #define GPIOPU_BASE (APB1_PERI_BASE_VIRT + 0x5000) | ||
503 | |||
504 | #define GPIOPU_DAT_OFFS 0x80 | ||
505 | #define GPIOPU_DOE_OFFS 0x84 | ||
506 | #define GPIOPU_FS0_OFFS 0x88 | ||
507 | #define GPIOPU_FS1_OFFS 0x8c | ||
508 | #define GPIOPU_FS2_OFFS 0x90 | ||
509 | #define GPIOPU_RPU_OFFS 0xb0 | ||
510 | #define GPIOPU_RPD_OFFS 0xb4 | ||
511 | #define GPIOPU_DV0_OFFS 0xb8 | ||
512 | #define GPIOPU_DV1_OFFS 0xbc | ||
513 | |||
514 | #define GPIOPU_FS0_TXD0 (1 << 0) | ||
515 | #define GPIOPU_FS0_RXD0 (1 << 1) | ||
516 | #define GPIOPU_FS0_CTS0 (1 << 2) | ||
517 | #define GPIOPU_FS0_RTS0 (1 << 3) | ||
518 | #define GPIOPU_FS0_TXD1 (1 << 4) | ||
519 | #define GPIOPU_FS0_RXD1 (1 << 5) | ||
520 | #define GPIOPU_FS0_CTS1 (1 << 6) | ||
521 | #define GPIOPU_FS0_RTS1 (1 << 7) | ||
522 | #define GPIOPU_FS0_TXD2 (1 << 8) | ||
523 | #define GPIOPU_FS0_RXD2 (1 << 9) | ||
524 | #define GPIOPU_FS0_CTS2 (1 << 10) | ||
525 | #define GPIOPU_FS0_RTS2 (1 << 11) | ||
526 | #define GPIOPU_FS0_TXD3 (1 << 12) | ||
527 | #define GPIOPU_FS0_RXD3 (1 << 13) | ||
528 | #define GPIOPU_FS0_CTS3 (1 << 14) | ||
529 | #define GPIOPU_FS0_RTS3 (1 << 15) | ||
530 | #define GPIOPU_FS0_TXD4 (1 << 16) | ||
531 | #define GPIOPU_FS0_RXD4 (1 << 17) | ||
532 | #define GPIOPU_FS0_CTS4 (1 << 18) | ||
533 | #define GPIOPU_FS0_RTS4 (1 << 19) | ||
534 | |||
535 | #define GPIOFC_BASE (APB1_PERI_BASE_VIRT + 0x5000) | ||
536 | |||
537 | #define GPIOFC_DAT_OFFS 0xc0 | ||
538 | #define GPIOFC_DOE_OFFS 0xc4 | ||
539 | #define GPIOFC_FS0_OFFS 0xc8 | ||
540 | #define GPIOFC_FS1_OFFS 0xcc | ||
541 | #define GPIOFC_FS2_OFFS 0xd0 | ||
542 | #define GPIOFC_FS3_OFFS 0xd4 | ||
543 | #define GPIOFC_RPU_OFFS 0xf0 | ||
544 | #define GPIOFC_RPD_OFFS 0xf4 | ||
545 | #define GPIOFC_DV0_OFFS 0xf8 | ||
546 | #define GPIOFC_DV1_OFFS 0xfc | ||
547 | |||
548 | #define GPIOFD_BASE (APB1_PERI_BASE_VIRT + 0x5000) | ||
549 | |||
550 | #define GPIOFD_DAT_OFFS 0x100 | ||
551 | #define GPIOFD_DOE_OFFS 0x104 | ||
552 | #define GPIOFD_FS0_OFFS 0x108 | ||
553 | #define GPIOFD_FS1_OFFS 0x10c | ||
554 | #define GPIOFD_FS2_OFFS 0x110 | ||
555 | #define GPIOFD_RPU_OFFS 0x130 | ||
556 | #define GPIOFD_RPD_OFFS 0x134 | ||
557 | #define GPIOFD_DV0_OFFS 0x138 | ||
558 | #define GPIOFD_DV1_OFFS 0x13c | ||
559 | |||
560 | #define GPIOLC_BASE (APB1_PERI_BASE_VIRT + 0x5000) | ||
561 | |||
562 | #define GPIOLC_DAT_OFFS 0x140 | ||
563 | #define GPIOLC_DOE_OFFS 0x144 | ||
564 | #define GPIOLC_FS0_OFFS 0x148 | ||
565 | #define GPIOLC_FS1_OFFS 0x14c | ||
566 | #define GPIOLC_RPU_OFFS 0x170 | ||
567 | #define GPIOLC_RPD_OFFS 0x174 | ||
568 | #define GPIOLC_DV0_OFFS 0x178 | ||
569 | #define GPIOLC_DV1_OFFS 0x17c | ||
570 | |||
571 | #define GPIOLD_BASE (APB1_PERI_BASE_VIRT + 0x5000) | ||
572 | |||
573 | #define GPIOLD_DAT_OFFS 0x180 | ||
574 | #define GPIOLD_DOE_OFFS 0x184 | ||
575 | #define GPIOLD_FS0_OFFS 0x188 | ||
576 | #define GPIOLD_FS1_OFFS 0x18c | ||
577 | #define GPIOLD_FS2_OFFS 0x190 | ||
578 | #define GPIOLD_RPU_OFFS 0x1b0 | ||
579 | #define GPIOLD_RPD_OFFS 0x1b4 | ||
580 | #define GPIOLD_DV0_OFFS 0x1b8 | ||
581 | #define GPIOLD_DV1_OFFS 0x1bc | ||
582 | |||
583 | #define GPIOAD_BASE (APB1_PERI_BASE_VIRT + 0x5000) | ||
584 | |||
585 | #define GPIOAD_DAT_OFFS 0x1c0 | ||
586 | #define GPIOAD_DOE_OFFS 0x1c4 | ||
587 | #define GPIOAD_FS0_OFFS 0x1c8 | ||
588 | #define GPIOAD_RPU_OFFS 0x1f0 | ||
589 | #define GPIOAD_RPD_OFFS 0x1f4 | ||
590 | #define GPIOAD_DV0_OFFS 0x1f8 | ||
591 | #define GPIOAD_DV1_OFFS 0x1fc | ||
592 | |||
593 | #define GPIOXC_BASE (APB1_PERI_BASE_VIRT + 0x5000) | ||
594 | |||
595 | #define GPIOXC_DAT_OFFS 0x200 | ||
596 | #define GPIOXC_DOE_OFFS 0x204 | ||
597 | #define GPIOXC_FS0_OFFS 0x208 | ||
598 | #define GPIOXC_RPU_OFFS 0x230 | ||
599 | #define GPIOXC_RPD_OFFS 0x234 | ||
600 | #define GPIOXC_DV0_OFFS 0x238 | ||
601 | #define GPIOXC_DV1_OFFS 0x23c | ||
602 | |||
603 | #define GPIOXC_FS0 __REG(GPIOXC_BASE + GPIOXC_FS0_OFFS) | ||
604 | |||
605 | #define GPIOXC_FS0_CS0 (1 << 26) | ||
606 | #define GPIOXC_FS0_CS1 (1 << 27) | ||
607 | |||
608 | #define GPIOXD_BASE (APB1_PERI_BASE_VIRT + 0x5000) | ||
609 | |||
610 | #define GPIOXD_DAT_OFFS 0x240 | ||
611 | #define GPIOXD_FS0_OFFS 0x248 | ||
612 | #define GPIOXD_RPU_OFFS 0x270 | ||
613 | #define GPIOXD_RPD_OFFS 0x274 | ||
614 | #define GPIOXD_DV0_OFFS 0x278 | ||
615 | #define GPIOXD_DV1_OFFS 0x27c | ||
616 | |||
617 | #define GPIOPK_BASE (APB1_PERI_BASE_VIRT + 0x1c000) | ||
618 | |||
619 | #define GPIOPK_RST_OFFS 0x008 | ||
620 | #define GPIOPK_DAT_OFFS 0x100 | ||
621 | #define GPIOPK_DOE_OFFS 0x104 | ||
622 | #define GPIOPK_FS0_OFFS 0x108 | ||
623 | #define GPIOPK_FS1_OFFS 0x10c | ||
624 | #define GPIOPK_FS2_OFFS 0x110 | ||
625 | #define GPIOPK_IRQST_OFFS 0x210 | ||
626 | #define GPIOPK_IRQEN_OFFS 0x214 | ||
627 | #define GPIOPK_IRQPOL_OFFS 0x218 | ||
628 | #define GPIOPK_IRQTM0_OFFS 0x21c | ||
629 | #define GPIOPK_IRQTM1_OFFS 0x220 | ||
630 | #define GPIOPK_CTL_OFFS 0x22c | ||
631 | |||
632 | #define PMGPIO_BASE (APB1_PERI_BASE_VIRT + 0x10000) | ||
633 | #define BACKUP_RAM_BASE PMGPIO_BASE | ||
634 | |||
635 | #define PMGPIO_DAT_OFFS 0x800 | ||
636 | #define PMGPIO_DOE_OFFS 0x804 | ||
637 | #define PMGPIO_FS0_OFFS 0x808 | ||
638 | #define PMGPIO_RPU_OFFS 0x810 | ||
639 | #define PMGPIO_RPD_OFFS 0x814 | ||
640 | #define PMGPIO_DV0_OFFS 0x818 | ||
641 | #define PMGPIO_DV1_OFFS 0x81c | ||
642 | #define PMGPIO_EE0_OFFS 0x820 | ||
643 | #define PMGPIO_EE1_OFFS 0x824 | ||
644 | #define PMGPIO_CTL_OFFS 0x828 | ||
645 | #define PMGPIO_DI_OFFS 0x82c | ||
646 | #define PMGPIO_STR_OFFS 0x830 | ||
647 | #define PMGPIO_STF_OFFS 0x834 | ||
648 | #define PMGPIO_POL_OFFS 0x838 | ||
649 | #define PMGPIO_APB_OFFS 0x800 | ||
650 | |||
651 | /* Clock controller registers */ | ||
652 | #define CKC_BASE (APB1_PERI_BASE_VIRT + 0x6000) | ||
653 | #define CKC_BASE_PHYS (APB1_PERI_BASE + 0x6000) | ||
654 | |||
655 | #define CLKCTRL_OFFS 0x00 | ||
656 | #define PLL0CFG_OFFS 0x04 | ||
657 | #define PLL1CFG_OFFS 0x08 | ||
658 | #define CLKDIVC0_OFFS 0x0c | ||
659 | |||
660 | #define BCLKCTR0_OFFS 0x14 | ||
661 | #define SWRESET0_OFFS 0x18 | ||
662 | |||
663 | #define BCLKCTR1_OFFS 0x60 | ||
664 | #define SWRESET1_OFFS 0x64 | ||
665 | #define PWDCTL_OFFS 0x68 | ||
666 | #define PLL2CFG_OFFS 0x6c | ||
667 | #define CLKDIVC1_OFFS 0x70 | ||
668 | |||
669 | #define ACLKREF_OFFS 0x80 | ||
670 | #define ACLKI2C_OFFS 0x84 | ||
671 | #define ACLKSPI0_OFFS 0x88 | ||
672 | #define ACLKSPI1_OFFS 0x8c | ||
673 | #define ACLKUART0_OFFS 0x90 | ||
674 | #define ACLKUART1_OFFS 0x94 | ||
675 | #define ACLKUART2_OFFS 0x98 | ||
676 | #define ACLKUART3_OFFS 0x9c | ||
677 | #define ACLKUART4_OFFS 0xa0 | ||
678 | #define ACLKTCT_OFFS 0xa4 | ||
679 | #define ACLKTCX_OFFS 0xa8 | ||
680 | #define ACLKTCZ_OFFS 0xac | ||
681 | #define ACLKADC_OFFS 0xb0 | ||
682 | #define ACLKDAI0_OFFS 0xb4 | ||
683 | #define ACLKDAI1_OFFS 0xb8 | ||
684 | #define ACLKLCD_OFFS 0xbc | ||
685 | #define ACLKSPDIF_OFFS 0xc0 | ||
686 | #define ACLKUSBH_OFFS 0xc4 | ||
687 | #define ACLKSDH0_OFFS 0xc8 | ||
688 | #define ACLKSDH1_OFFS 0xcc | ||
689 | #define ACLKC3DEC_OFFS 0xd0 | ||
690 | #define ACLKEXT_OFFS 0xd4 | ||
691 | #define ACLKCAN0_OFFS 0xd8 | ||
692 | #define ACLKCAN1_OFFS 0xdc | ||
693 | #define ACLKGSB0_OFFS 0xe0 | ||
694 | #define ACLKGSB1_OFFS 0xe4 | ||
695 | #define ACLKGSB2_OFFS 0xe8 | ||
696 | #define ACLKGSB3_OFFS 0xec | ||
697 | |||
698 | #define PLLxCFG_PD (1 << 31) | ||
699 | |||
700 | /* CLKCTRL bits */ | ||
701 | #define CLKCTRL_XE (1 << 31) | ||
702 | |||
703 | /* CLKDIVCx bits */ | ||
704 | #define CLKDIVC0_XTE (1 << 7) | ||
705 | #define CLKDIVC0_XE (1 << 15) | ||
706 | #define CLKDIVC0_P1E (1 << 23) | ||
707 | #define CLKDIVC0_P0E (1 << 31) | ||
708 | |||
709 | #define CLKDIVC1_P2E (1 << 7) | ||
710 | |||
711 | /* BCLKCTR0 clock bits */ | ||
712 | #define BCLKCTR0_USBD (1 << 4) | ||
713 | #define BCLKCTR0_ECC (1 << 9) | ||
714 | #define BCLKCTR0_USBH0 (1 << 11) | ||
715 | #define BCLKCTR0_NFC (1 << 16) | ||
716 | |||
717 | /* BCLKCTR1 clock bits */ | ||
718 | #define BCLKCTR1_USBH1 (1 << 20) | ||
719 | |||
720 | /* SWRESET0 bits */ | ||
721 | #define SWRESET0_USBD (1 << 4) | ||
722 | #define SWRESET0_USBH0 (1 << 11) | ||
723 | |||
724 | /* SWRESET1 bits */ | ||
725 | #define SWRESET1_USBH1 (1 << 20) | ||
726 | |||
727 | /* System clock sources */ | ||
728 | enum root_clks { | ||
729 | CLK_SRC_PLL0 = 0, | ||
730 | CLK_SRC_PLL1, | ||
731 | CLK_SRC_PLL0DIV, | ||
732 | CLK_SRC_PLL1DIV, | ||
733 | CLK_SRC_XI, | ||
734 | CLK_SRC_XIDIV, | ||
735 | CLK_SRC_XTI, | ||
736 | CLK_SRC_XTIDIV, | ||
737 | CLK_SRC_PLL2, | ||
738 | CLK_SRC_PLL2DIV, | ||
739 | CLK_SRC_PK0, | ||
740 | CLK_SRC_PK1, | ||
741 | CLK_SRC_PK2, | ||
742 | CLK_SRC_PK3, | ||
743 | CLK_SRC_PK4, | ||
744 | CLK_SRC_48MHZ | ||
745 | }; | ||
746 | |||
747 | #define CLK_SRC_MASK 0xf | ||
748 | |||
749 | /* Bits in ACLK* registers */ | ||
750 | #define ACLK_EN (1 << 28) | ||
751 | #define ACLK_SEL_SHIFT 24 | ||
752 | #define ACLK_SEL_MASK 0x0f000000 | ||
753 | #define ACLK_DIV_MASK 0x00000fff | ||
754 | |||
755 | /* System configuration registers */ | ||
756 | |||
757 | #define SCFG_BASE (APB1_PERI_BASE_VIRT + 0x13000) | ||
758 | |||
759 | #define BMI_OFFS 0x00 | ||
760 | #define AHBCON0_OFFS 0x04 | ||
761 | #define APBPWE_OFFS 0x08 | ||
762 | #define DTCMWAIT_OFFS 0x0c | ||
763 | #define ECCSEL_OFFS 0x10 | ||
764 | #define AHBCON1_OFFS 0x14 | ||
765 | #define SDHCFG_OFFS 0x18 | ||
766 | #define REMAP_OFFS 0x20 | ||
767 | #define LCDSIAE_OFFS 0x24 | ||
768 | #define XMCCFG_OFFS 0xe0 | ||
769 | #define IMCCFG_OFFS 0xe4 | ||
770 | |||
771 | /* Values for ECCSEL */ | ||
772 | #define ECCSEL_EXTMEM 0x0 | ||
773 | #define ECCSEL_DTCM 0x1 | ||
774 | #define ECCSEL_INT_SRAM 0x2 | ||
775 | #define ECCSEL_AHB 0x3 | ||
776 | |||
777 | /* Bits in XMCCFG */ | ||
778 | #define XMCCFG_NFCE (1 << 1) | ||
779 | #define XMCCFG_FDXD (1 << 2) | ||
780 | |||
781 | /* External memory controller registers */ | ||
782 | |||
783 | #define EMC_BASE EXT_MEM_CTRL_BASE | ||
784 | |||
785 | #define SDCFG_OFFS 0x00 | ||
786 | #define SDFSM_OFFS 0x04 | ||
787 | #define MCFG_OFFS 0x08 | ||
788 | |||
789 | #define CSCFG0_OFFS 0x10 | ||
790 | #define CSCFG1_OFFS 0x14 | ||
791 | #define CSCFG2_OFFS 0x18 | ||
792 | #define CSCFG3_OFFS 0x1c | ||
793 | |||
794 | #define MCFG_SDEN (1 << 4) | ||
795 | |||
796 | #endif /* TCC8K_REGS_H */ | ||
diff --git a/arch/arm/plat-tcc/include/mach/uncompress.h b/arch/arm/plat-tcc/include/mach/uncompress.h new file mode 100644 index 000000000000..7a3e33a27a30 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/uncompress.h | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de> | ||
3 | * | ||
4 | * This file is licensed under the terms of the GPL version 2. | ||
5 | */ | ||
6 | |||
7 | #include <linux/serial_reg.h> | ||
8 | #include <linux/types.h> | ||
9 | |||
10 | #include <mach/tcc8k-regs.h> | ||
11 | |||
12 | unsigned int system_rev; | ||
13 | |||
14 | #define ID_MASK 0x7fff | ||
15 | |||
16 | static void putc(int c) | ||
17 | { | ||
18 | u32 *uart_lsr = (u32 *)(UART_BASE_PHYS + (UART_LSR << 2)); | ||
19 | u32 *uart_tx = (u32 *)(UART_BASE_PHYS + (UART_TX << 2)); | ||
20 | |||
21 | while (!(*uart_lsr & UART_LSR_THRE)) | ||
22 | barrier(); | ||
23 | *uart_tx = c; | ||
24 | } | ||
25 | |||
26 | static inline void flush(void) | ||
27 | { | ||
28 | } | ||
29 | |||
30 | /* | ||
31 | * nothing to do | ||
32 | */ | ||
33 | #define arch_decomp_setup() | ||
34 | #define arch_decomp_wdog() | ||
diff --git a/arch/arm/plat-tcc/include/mach/vmalloc.h b/arch/arm/plat-tcc/include/mach/vmalloc.h new file mode 100644 index 000000000000..99414d9c2b94 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/vmalloc.h | |||
@@ -0,0 +1,10 @@ | |||
1 | /* | ||
2 | * Author: <linux@telechips.com> | ||
3 | * Created: June 10, 2008 | ||
4 | * | ||
5 | * Copyright (C) 2000 Russell King. | ||
6 | * Copyright (C) 2008-2009 Telechips | ||
7 | * | ||
8 | * Licensed under the terms of the GPL v2. | ||
9 | */ | ||
10 | #define VMALLOC_END 0xf0000000UL | ||