[ARM] 5532/1: Freescale STMP: register definitions [3/3]

Replace HW_zzz register access macros by regular __raw_readl/__raw_writel calls Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
author: dmitry pervushin <dpervushin@embeddedalley.com> 2009-05-31 08:32:11 -0400
committer: Russell King <rmk+kernel@arm.linux.org.uk> 2009-05-31 08:55:56 -0400
commit: 98f420b23a62e0c9df78c5851860d47bf1bc87dd (patch)
tree: b7e88059454d2410b1a2107c17a748a03d366fdf /arch/arm/plat-stmp3xxx/timer.c
parent: 3f52326a85666c1cb0210eb5556ef3d483933cfc (diff)
1 files changed, 64 insertions, 47 deletions
diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c
index 7d872f0aee70..063c7bc0e740 100644
--- a/arch/arm/plat-stmp3xxx/timer.c
+++ b/arch/arm/plat-stmp3xxx/timer.c
@@ -26,6 +26,7 @@
 #include <asm/mach/time.h>
 #include <mach/stmp3xxx.h>
+#include <mach/platform.h>
 #include <mach/regs-timrot.h>
 static irqreturn_t
@@ -33,13 +34,22 @@ stmp3xxx_timer_interrupt(int irq, void *dev_id)
 {
        struct clock_event_device *c = dev_id;
-        if (HW_TIMROT_TIMCTRLn_RD(0) & (1<<15)) {
+        /* timer 0 */
-                HW_TIMROT_TIMCTRLn_CLR(0, (1<<15));
+        if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) &
+                        BM_TIMROT_TIMCTRLn_IRQ) {
+                stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
+                                REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
                c->event_handler(c);
-        } else if (HW_TIMROT_TIMCTRLn_RD(1) & (1<<15)) {
+        }
-                HW_TIMROT_TIMCTRLn_CLR(1, (1<<15));
-                HW_TIMROT_TIMCTRLn_CLR(1, BM_TIMROT_TIMCTRLn_IRQ_EN);
+        /* timer 1 */
-                HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF);
+        else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1)
+                        & BM_TIMROT_TIMCTRLn_IRQ) {
+                stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
+                                REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+                stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN,
+                                REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+                __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
        }
        return IRQ_HANDLED;
@@ -47,14 +57,16 @@ stmp3xxx_timer_interrupt(int irq, void *dev_id)
 static cycle_t stmp3xxx_clock_read(struct clocksource *cs)
 {
-        return ~((HW_TIMROT_TIMCOUNTn_RD(1) & 0xFFFF0000) >> 16);
+        return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1)
+                                & 0xFFFF0000) >> 16);
 }
 static int
 stmp3xxx_timrot_set_next_event(unsigned long delta,
                struct clock_event_device *dev)
 {
-        HW_TIMROT_TIMCOUNTn_WR(0, delta); /* reload */
+        /* reload the timer */
+        __raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
        return 0;
 }
@@ -102,25 +114,29 @@ static void __init stmp3xxx_init_timer(void)
        ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
        ckevt_timrot.cpumask = cpumask_of(0);
-        HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST |
+        stmp3xxx_reset_block(REGS_TIMROT_BASE, false);
-                                BM_TIMROT_ROTCTRL_CLKGATE);
-        HW_TIMROT_TIMCOUNTn_WR(0, 0);
+        /* clear two timers */
-        HW_TIMROT_TIMCOUNTn_WR(1, 0);
+        __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
+        __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
-        HW_TIMROT_TIMCTRLn_WR(0,
-                              (BF_TIMROT_TIMCTRLn_SELECT(8) |  /* 32 kHz */
+        /* configure them */
-                               BF_TIMROT_TIMCTRLn_PRESCALE(0) |
+        __raw_writel(
-                               BM_TIMROT_TIMCTRLn_RELOAD |
+                (8 << BP_TIMROT_TIMCTRLn_SELECT) |  /* 32 kHz */
-                               BM_TIMROT_TIMCTRLn_UPDATE |
+                BM_TIMROT_TIMCTRLn_RELOAD |
-                               BM_TIMROT_TIMCTRLn_IRQ_EN));
+                BM_TIMROT_TIMCTRLn_UPDATE |
-        HW_TIMROT_TIMCTRLn_WR(1,
+                BM_TIMROT_TIMCTRLn_IRQ_EN,
-                              (BF_TIMROT_TIMCTRLn_SELECT(8) |  /* 32 kHz */
+                        REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
-                               BF_TIMROT_TIMCTRLn_PRESCALE(0) |
+        __raw_writel(
-                               BM_TIMROT_TIMCTRLn_RELOAD |
+                (8 << BP_TIMROT_TIMCTRLn_SELECT) |  /* 32 kHz */
-                               BM_TIMROT_TIMCTRLn_UPDATE));
+                BM_TIMROT_TIMCTRLn_RELOAD |
+                BM_TIMROT_TIMCTRLn_UPDATE |
-        HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1);
+                BM_TIMROT_TIMCTRLn_IRQ_EN,
-        HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */
+                        REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+        __raw_writel(CLOCK_TICK_RATE / HZ - 1,
+                        REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
+        __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
        setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
@@ -132,30 +148,31 @@ static void __init stmp3xxx_init_timer(void)
 void stmp3xxx_suspend_timer(void)
 {
-        HW_TIMROT_TIMCTRLn_CLR(0, BM_TIMROT_TIMCTRLn_IRQ_EN);
+        stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ,
-        HW_TIMROT_TIMCTRLn_CLR(0, (1<<15));
+                        REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
-        HW_TIMROT_ROTCTRL_SET(BM_TIMROT_ROTCTRL_CLKGATE);
+        stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE,
+                        REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
 }
 void stmp3xxx_resume_timer(void)
 {
-        HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST |
+        stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE,
-                                BM_TIMROT_ROTCTRL_CLKGATE);
+                        REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
+        __raw_writel(
+                8 << BP_TIMROT_TIMCTRLn_SELECT |  /* 32 kHz */
-        HW_TIMROT_TIMCTRLn_WR(0,
+                BM_TIMROT_TIMCTRLn_RELOAD |
-                              (BF_TIMROT_TIMCTRLn_SELECT(8) |  /* 32 kHz */
+                BM_TIMROT_TIMCTRLn_UPDATE |
-                               BF_TIMROT_TIMCTRLn_PRESCALE(0) |
+                BM_TIMROT_TIMCTRLn_IRQ_EN,
-                               BM_TIMROT_TIMCTRLn_UPDATE |
+                        REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
-                               BM_TIMROT_TIMCTRLn_IRQ_EN));
+        __raw_writel(
-        HW_TIMROT_TIMCTRLn_WR(1,
+                8 << BP_TIMROT_TIMCTRLn_SELECT |  /* 32 kHz */
-                              (BF_TIMROT_TIMCTRLn_SELECT(8) |  /* 32 kHz */
+                BM_TIMROT_TIMCTRLn_RELOAD |
-                               BF_TIMROT_TIMCTRLn_PRESCALE(0) |
+                BM_TIMROT_TIMCTRLn_UPDATE |
-                               BM_TIMROT_TIMCTRLn_RELOAD |
+                BM_TIMROT_TIMCTRLn_IRQ_EN,
-                               BM_TIMROT_TIMCTRLn_UPDATE));
+                        REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+        __raw_writel(CLOCK_TICK_RATE / HZ - 1,
-        HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1);
+                        REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
-        HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */
+        __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
 }
 #else
author	dmitry pervushin <dpervushin@embeddedalley.com>	2009-05-31 08:32:11 -0400
committer	Russell King <rmk+kernel@arm.linux.org.uk>	2009-05-31 08:55:56 -0400
commit	98f420b23a62e0c9df78c5851860d47bf1bc87dd (patch)
tree	b7e88059454d2410b1a2107c17a748a03d366fdf /arch/arm/plat-stmp3xxx/timer.c
parent	3f52326a85666c1cb0210eb5556ef3d483933cfc (diff)

diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c index 7d872f0aee70..063c7bc0e740 100644 --- a/arch/arm/plat-stmp3xxx/timer.c +++ b/arch/arm/plat-stmp3xxx/timer.c
@@ -26,6 +26,7 @@
26		26
27	#include <asm/mach/time.h>	27	#include <asm/mach/time.h>
28	#include <mach/stmp3xxx.h>	28	#include <mach/stmp3xxx.h>
		29	#include <mach/platform.h>
29	#include <mach/regs-timrot.h>	30	#include <mach/regs-timrot.h>
30		31
31	static irqreturn_t	32	static irqreturn_t
@@ -33,13 +34,22 @@ stmp3xxx_timer_interrupt(int irq, void *dev_id)
33	{	34	{
34	struct clock_event_device *c = dev_id;	35	struct clock_event_device *c = dev_id;
35		36
36	if (HW_TIMROT_TIMCTRLn_RD(0) & (1<<15)) {	37	/* timer 0 */
37	HW_TIMROT_TIMCTRLn_CLR(0, (1<<15));	38	if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) &
		39	BM_TIMROT_TIMCTRLn_IRQ) {
		40	stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
		41	REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
38	c->event_handler(c);	42	c->event_handler(c);
39	} else if (HW_TIMROT_TIMCTRLn_RD(1) & (1<<15)) {	43	}
40	HW_TIMROT_TIMCTRLn_CLR(1, (1<<15));	44
41	HW_TIMROT_TIMCTRLn_CLR(1, BM_TIMROT_TIMCTRLn_IRQ_EN);	45	/* timer 1 */
42	HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF);	46	else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1)
		47	& BM_TIMROT_TIMCTRLn_IRQ) {
		48	stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
		49	REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
		50	stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN,
		51	REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
		52	__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
43	}	53	}
44		54
45	return IRQ_HANDLED;	55	return IRQ_HANDLED;
@@ -47,14 +57,16 @@ stmp3xxx_timer_interrupt(int irq, void *dev_id)
47		57
48	static cycle_t stmp3xxx_clock_read(struct clocksource *cs)	58	static cycle_t stmp3xxx_clock_read(struct clocksource *cs)
49	{	59	{
50	return ~((HW_TIMROT_TIMCOUNTn_RD(1) & 0xFFFF0000) >> 16);	60	return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1)
		61	& 0xFFFF0000) >> 16);
51	}	62	}
52		63
53	static int	64	static int
54	stmp3xxx_timrot_set_next_event(unsigned long delta,	65	stmp3xxx_timrot_set_next_event(unsigned long delta,
55	struct clock_event_device *dev)	66	struct clock_event_device *dev)
56	{	67	{
57	HW_TIMROT_TIMCOUNTn_WR(0, delta); /* reload */	68	/* reload the timer */
		69	__raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
58	return 0;	70	return 0;
59	}	71	}
60		72
@@ -102,25 +114,29 @@ static void __init stmp3xxx_init_timer(void)
102	ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);	114	ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
103	ckevt_timrot.cpumask = cpumask_of(0);	115	ckevt_timrot.cpumask = cpumask_of(0);
104		116
105	HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST \|	117	stmp3xxx_reset_block(REGS_TIMROT_BASE, false);
106	BM_TIMROT_ROTCTRL_CLKGATE);	118
107	HW_TIMROT_TIMCOUNTn_WR(0, 0);	119	/* clear two timers */
108	HW_TIMROT_TIMCOUNTn_WR(1, 0);	120	__raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
109		121	__raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
110	HW_TIMROT_TIMCTRLn_WR(0,	122
111	(BF_TIMROT_TIMCTRLn_SELECT(8) \| /* 32 kHz */	123	/* configure them */
112	BF_TIMROT_TIMCTRLn_PRESCALE(0) \|	124	__raw_writel(
113	BM_TIMROT_TIMCTRLn_RELOAD \|	125	(8 << BP_TIMROT_TIMCTRLn_SELECT) \| /* 32 kHz */
114	BM_TIMROT_TIMCTRLn_UPDATE \|	126	BM_TIMROT_TIMCTRLn_RELOAD \|
115	BM_TIMROT_TIMCTRLn_IRQ_EN));	127	BM_TIMROT_TIMCTRLn_UPDATE \|
116	HW_TIMROT_TIMCTRLn_WR(1,	128	BM_TIMROT_TIMCTRLn_IRQ_EN,
117	(BF_TIMROT_TIMCTRLn_SELECT(8) \| /* 32 kHz */	129	REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
118	BF_TIMROT_TIMCTRLn_PRESCALE(0) \|	130	__raw_writel(
119	BM_TIMROT_TIMCTRLn_RELOAD \|	131	(8 << BP_TIMROT_TIMCTRLn_SELECT) \| /* 32 kHz */
120	BM_TIMROT_TIMCTRLn_UPDATE));	132	BM_TIMROT_TIMCTRLn_RELOAD \|
121		133	BM_TIMROT_TIMCTRLn_UPDATE \|
122	HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1);	134	BM_TIMROT_TIMCTRLn_IRQ_EN,
123	HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */	135	REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
		136
		137	__raw_writel(CLOCK_TICK_RATE / HZ - 1,
		138	REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
		139	__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
124		140
125	setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);	141	setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
126		142
@@ -132,30 +148,31 @@ static void __init stmp3xxx_init_timer(void)
132		148
133	void stmp3xxx_suspend_timer(void)	149	void stmp3xxx_suspend_timer(void)
134	{	150	{
135	HW_TIMROT_TIMCTRLn_CLR(0, BM_TIMROT_TIMCTRLn_IRQ_EN);	151	stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN \| BM_TIMROT_TIMCTRLn_IRQ,
136	HW_TIMROT_TIMCTRLn_CLR(0, (1<<15));	152	REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
137	HW_TIMROT_ROTCTRL_SET(BM_TIMROT_ROTCTRL_CLKGATE);	153	stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE,
		154	REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
138	}	155	}
139		156
140	void stmp3xxx_resume_timer(void)	157	void stmp3xxx_resume_timer(void)
141	{	158	{
142	HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST \|	159	stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST \| BM_TIMROT_ROTCTRL_CLKGATE,
143	BM_TIMROT_ROTCTRL_CLKGATE);	160	REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
144		161	__raw_writel(
145		162	8 << BP_TIMROT_TIMCTRLn_SELECT \| /* 32 kHz */
146	HW_TIMROT_TIMCTRLn_WR(0,	163	BM_TIMROT_TIMCTRLn_RELOAD \|
147	(BF_TIMROT_TIMCTRLn_SELECT(8) \| /* 32 kHz */	164	BM_TIMROT_TIMCTRLn_UPDATE \|
148	BF_TIMROT_TIMCTRLn_PRESCALE(0) \|	165	BM_TIMROT_TIMCTRLn_IRQ_EN,
149	BM_TIMROT_TIMCTRLn_UPDATE \|	166	REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
150	BM_TIMROT_TIMCTRLn_IRQ_EN));	167	__raw_writel(
151	HW_TIMROT_TIMCTRLn_WR(1,	168	8 << BP_TIMROT_TIMCTRLn_SELECT \| /* 32 kHz */
152	(BF_TIMROT_TIMCTRLn_SELECT(8) \| /* 32 kHz */	169	BM_TIMROT_TIMCTRLn_RELOAD \|
153	BF_TIMROT_TIMCTRLn_PRESCALE(0) \|	170	BM_TIMROT_TIMCTRLn_UPDATE \|
154	BM_TIMROT_TIMCTRLn_RELOAD \|	171	BM_TIMROT_TIMCTRLn_IRQ_EN,
155	BM_TIMROT_TIMCTRLn_UPDATE));	172	REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
156		173	__raw_writel(CLOCK_TICK_RATE / HZ - 1,
157	HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1);	174	REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
158	HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */	175	__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
159	}	176	}
160		177
161	#else	178	#else