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authordmitry pervushin <dpervushin@embeddedalley.com>2009-05-31 08:32:11 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-05-31 08:55:56 -0400
commit98f420b23a62e0c9df78c5851860d47bf1bc87dd (patch)
treeb7e88059454d2410b1a2107c17a748a03d366fdf /arch/arm/plat-stmp3xxx/irq.c
parent3f52326a85666c1cb0210eb5556ef3d483933cfc (diff)
[ARM] 5532/1: Freescale STMP: register definitions [3/3]
Replace HW_zzz register access macros by regular __raw_readl/__raw_writel calls Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/plat-stmp3xxx/irq.c')
-rw-r--r--arch/arm/plat-stmp3xxx/irq.c22
1 files changed, 7 insertions, 15 deletions
diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c
index cb3659096681..20de4e0401ef 100644
--- a/arch/arm/plat-stmp3xxx/irq.c
+++ b/arch/arm/plat-stmp3xxx/irq.c
@@ -22,21 +22,15 @@
22#include <linux/sysdev.h> 22#include <linux/sysdev.h>
23 23
24#include <mach/stmp3xxx.h> 24#include <mach/stmp3xxx.h>
25#include <mach/platform.h>
25#include <mach/regs-icoll.h> 26#include <mach/regs-icoll.h>
26 27
27void __init stmp3xxx_init_irq(struct irq_chip *chip) 28void __init stmp3xxx_init_irq(struct irq_chip *chip)
28{ 29{
29 unsigned int i; 30 unsigned int i, lv;
30 31
31 /* Reset the interrupt controller */ 32 /* Reset the interrupt controller */
32 HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_CLKGATE); 33 stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true);
33 udelay(10);
34 HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST);
35 udelay(10);
36 HW_ICOLL_CTRL_SET(BM_ICOLL_CTRL_SFTRST);
37 while (!(HW_ICOLL_CTRL_RD() & BM_ICOLL_CTRL_CLKGATE))
38 continue;
39 HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST | BM_ICOLL_CTRL_CLKGATE);
40 34
41 /* Disable all interrupts initially */ 35 /* Disable all interrupts initially */
42 for (i = 0; i < NR_REAL_IRQS; i++) { 36 for (i = 0; i < NR_REAL_IRQS; i++) {
@@ -47,13 +41,11 @@ void __init stmp3xxx_init_irq(struct irq_chip *chip)
47 } 41 }
48 42
49 /* Ensure vector is cleared */ 43 /* Ensure vector is cleared */
50 HW_ICOLL_LEVELACK_WR(1); 44 for (lv = 0; lv < 4; lv++)
51 HW_ICOLL_LEVELACK_WR(2); 45 __raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
52 HW_ICOLL_LEVELACK_WR(4); 46 __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
53 HW_ICOLL_LEVELACK_WR(8);
54 47
55 HW_ICOLL_VECTOR_WR(0);
56 /* Barrier */ 48 /* Barrier */
57 (void) HW_ICOLL_STAT_RD(); 49 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
58} 50}
59 51