diff options
author | dmitry pervushin <dpervushin@embeddedalley.com> | 2009-05-31 08:32:11 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-05-31 08:55:56 -0400 |
commit | 98f420b23a62e0c9df78c5851860d47bf1bc87dd (patch) | |
tree | b7e88059454d2410b1a2107c17a748a03d366fdf /arch/arm/plat-stmp3xxx/dma.c | |
parent | 3f52326a85666c1cb0210eb5556ef3d483933cfc (diff) |
[ARM] 5532/1: Freescale STMP: register definitions [3/3]
Replace HW_zzz register access macros by regular __raw_readl/__raw_writel calls
Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/plat-stmp3xxx/dma.c')
-rw-r--r-- | arch/arm/plat-stmp3xxx/dma.c | 137 |
1 files changed, 69 insertions, 68 deletions
diff --git a/arch/arm/plat-stmp3xxx/dma.c b/arch/arm/plat-stmp3xxx/dma.c index cf42de05e568..d2f497764dce 100644 --- a/arch/arm/plat-stmp3xxx/dma.c +++ b/arch/arm/plat-stmp3xxx/dma.c | |||
@@ -23,6 +23,7 @@ | |||
23 | 23 | ||
24 | #include <asm/page.h> | 24 | #include <asm/page.h> |
25 | 25 | ||
26 | #include <mach/platform.h> | ||
26 | #include <mach/dma.h> | 27 | #include <mach/dma.h> |
27 | #include <mach/regs-apbx.h> | 28 | #include <mach/regs-apbx.h> |
28 | #include <mach/regs-apbh.h> | 29 | #include <mach/regs-apbh.h> |
@@ -35,16 +36,6 @@ static struct stmp3xxx_dma_user { | |||
35 | const char *name; | 36 | const char *name; |
36 | } channels[MAX_DMA_CHANNELS]; | 37 | } channels[MAX_DMA_CHANNELS]; |
37 | 38 | ||
38 | static inline int dmach(int ch) | ||
39 | { | ||
40 | return ch % 16; | ||
41 | } | ||
42 | |||
43 | static inline int dmabus(int ch) | ||
44 | { | ||
45 | return ch / 16; | ||
46 | } | ||
47 | |||
48 | #define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS) | 39 | #define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS) |
49 | #define IS_USED(ch) (channels[ch].inuse) | 40 | #define IS_USED(ch) (channels[ch].inuse) |
50 | 41 | ||
@@ -101,17 +92,19 @@ int stmp3xxx_dma_read_semaphore(int channel) | |||
101 | { | 92 | { |
102 | int sem = -1; | 93 | int sem = -1; |
103 | 94 | ||
104 | switch (dmabus(channel)) { | 95 | switch (STMP3XXX_DMA_BUS(channel)) { |
105 | case STMP3XXX_BUS_APBH: | 96 | case STMP3XXX_BUS_APBH: |
106 | sem = | 97 | sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA + |
107 | (HW_APBH_CHn_SEMA_RD(dmach(channel)) & | 98 | STMP3XXX_DMA_CHANNEL(channel) * 0x70); |
108 | BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE; | 99 | sem &= BM_APBH_CHn_SEMA_PHORE; |
100 | sem >>= BP_APBH_CHn_SEMA_PHORE; | ||
109 | break; | 101 | break; |
110 | 102 | ||
111 | case STMP3XXX_BUS_APBX: | 103 | case STMP3XXX_BUS_APBX: |
112 | sem = | 104 | sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA + |
113 | (HW_APBX_CHn_SEMA_RD(dmach(channel)) & | 105 | STMP3XXX_DMA_CHANNEL(channel) * 0x70); |
114 | BM_APBX_CHn_SEMA_PHORE) >> BP_APBX_CHn_SEMA_PHORE; | 106 | sem &= BM_APBX_CHn_SEMA_PHORE; |
107 | sem >>= BP_APBX_CHn_SEMA_PHORE; | ||
115 | break; | 108 | break; |
116 | default: | 109 | default: |
117 | BUG(); | 110 | BUG(); |
@@ -189,39 +182,44 @@ EXPORT_SYMBOL(stmp3xxx_dma_free_command); | |||
189 | void stmp3xxx_dma_go(int channel, | 182 | void stmp3xxx_dma_go(int channel, |
190 | struct stmp3xxx_dma_descriptor *head, u32 semaphore) | 183 | struct stmp3xxx_dma_descriptor *head, u32 semaphore) |
191 | { | 184 | { |
192 | int ch = dmach(channel); | 185 | int ch = STMP3XXX_DMA_CHANNEL(channel); |
186 | void __iomem *c, *s; | ||
193 | 187 | ||
194 | switch (dmabus(channel)) { | 188 | switch (STMP3XXX_DMA_BUS(channel)) { |
195 | case STMP3XXX_BUS_APBH: | 189 | case STMP3XXX_BUS_APBH: |
196 | /* Set next command */ | 190 | c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch; |
197 | HW_APBH_CHn_NXTCMDAR_WR(ch, head->handle); | 191 | s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch; |
198 | /* Set counting semaphore (kicks off transfer). Assumes | ||
199 | peripheral has been set up correctly */ | ||
200 | HW_APBH_CHn_SEMA_WR(ch, semaphore); | ||
201 | break; | 192 | break; |
202 | 193 | ||
203 | case STMP3XXX_BUS_APBX: | 194 | case STMP3XXX_BUS_APBX: |
204 | /* Set next command */ | 195 | c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch; |
205 | HW_APBX_CHn_NXTCMDAR_WR(ch, head->handle); | 196 | s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch; |
206 | /* Set counting semaphore (kicks off transfer). Assumes | ||
207 | peripheral has been set up correctly */ | ||
208 | HW_APBX_CHn_SEMA_WR(ch, semaphore); | ||
209 | break; | 197 | break; |
198 | |||
199 | default: | ||
200 | return; | ||
210 | } | 201 | } |
202 | |||
203 | /* Set next command */ | ||
204 | __raw_writel(head->handle, c); | ||
205 | /* Set counting semaphore (kicks off transfer). Assumes | ||
206 | peripheral has been set up correctly */ | ||
207 | __raw_writel(semaphore, s); | ||
211 | } | 208 | } |
212 | EXPORT_SYMBOL(stmp3xxx_dma_go); | 209 | EXPORT_SYMBOL(stmp3xxx_dma_go); |
213 | 210 | ||
214 | int stmp3xxx_dma_running(int channel) | 211 | int stmp3xxx_dma_running(int channel) |
215 | { | 212 | { |
216 | switch (dmabus(channel)) { | 213 | switch (STMP3XXX_DMA_BUS(channel)) { |
217 | case STMP3XXX_BUS_APBH: | 214 | case STMP3XXX_BUS_APBH: |
218 | return HW_APBH_CHn_SEMA_RD(dmach(channel)) & | 215 | return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA + |
219 | BM_APBH_CHn_SEMA_PHORE; | 216 | 0x70 * STMP3XXX_DMA_CHANNEL(channel))) & |
217 | BM_APBH_CHn_SEMA_PHORE; | ||
220 | 218 | ||
221 | case STMP3XXX_BUS_APBX: | 219 | case STMP3XXX_BUS_APBX: |
222 | return HW_APBX_CHn_SEMA_RD(dmach(channel)) & | 220 | return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA + |
223 | BM_APBX_CHn_SEMA_PHORE; | 221 | 0x70 * STMP3XXX_DMA_CHANNEL(channel))) & |
224 | 222 | BM_APBX_CHn_SEMA_PHORE; | |
225 | default: | 223 | default: |
226 | BUG(); | 224 | BUG(); |
227 | return 0; | 225 | return 0; |
@@ -238,7 +236,7 @@ void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain) | |||
238 | 236 | ||
239 | for (i = 0; i < chain->total_count; i++) | 237 | for (i = 0; i < chain->total_count; i++) |
240 | stmp3xxx_dma_free_command( | 238 | stmp3xxx_dma_free_command( |
241 | STMP3xxx_DMA(chain->channel, chain->bus), | 239 | STMP3XXX_DMA(chain->channel, chain->bus), |
242 | &chain->chain[i]); | 240 | &chain->chain[i]); |
243 | } | 241 | } |
244 | EXPORT_SYMBOL(stmp3xxx_dma_free_chain); | 242 | EXPORT_SYMBOL(stmp3xxx_dma_free_chain); |
@@ -291,16 +289,15 @@ int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain, | |||
291 | chain->free_count = items; | 289 | chain->free_count = items; |
292 | chain->active_count = 0; | 290 | chain->active_count = 0; |
293 | chain->cooked_count = 0; | 291 | chain->cooked_count = 0; |
294 | chain->bus = dmabus(ch); | 292 | chain->bus = STMP3XXX_DMA_BUS(ch); |
295 | chain->channel = dmach(ch); | 293 | chain->channel = STMP3XXX_DMA_CHANNEL(ch); |
296 | return err; | 294 | return err; |
297 | } | 295 | } |
298 | EXPORT_SYMBOL(stmp3xxx_dma_make_chain); | 296 | EXPORT_SYMBOL(stmp3xxx_dma_make_chain); |
299 | 297 | ||
300 | void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain) | 298 | void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain) |
301 | { | 299 | { |
302 | BUG_ON(stmp3xxx_dma_running(STMP3xxx_DMA(chain->channel, chain->bus)) > | 300 | BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus))); |
303 | 0); | ||
304 | chain->free_index = 0; | 301 | chain->free_index = 0; |
305 | chain->active_index = 0; | 302 | chain->active_index = 0; |
306 | chain->cooked_index = 0; | 303 | chain->cooked_index = 0; |
@@ -325,6 +322,8 @@ EXPORT_SYMBOL(stmp37xx_circ_advance_free); | |||
325 | void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain, | 322 | void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain, |
326 | unsigned count) | 323 | unsigned count) |
327 | { | 324 | { |
325 | void __iomem *c; | ||
326 | u32 mask_clr, mask; | ||
328 | BUG_ON(chain->free_count < count); | 327 | BUG_ON(chain->free_count < count); |
329 | 328 | ||
330 | chain->free_count -= count; | 329 | chain->free_count -= count; |
@@ -334,26 +333,24 @@ void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain, | |||
334 | 333 | ||
335 | switch (chain->bus) { | 334 | switch (chain->bus) { |
336 | case STMP3XXX_BUS_APBH: | 335 | case STMP3XXX_BUS_APBH: |
337 | /* Set counting semaphore (kicks off transfer). Assumes | 336 | c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel; |
338 | peripheral has been set up correctly */ | 337 | mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA; |
339 | HW_APBH_CHn_SEMA_CLR(chain->channel, | 338 | mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA); |
340 | BM_APBH_CHn_SEMA_INCREMENT_SEMA); | ||
341 | HW_APBH_CHn_SEMA_SET(chain->channel, | ||
342 | BF_APBH_CHn_SEMA_INCREMENT_SEMA(count)); | ||
343 | break; | 339 | break; |
344 | |||
345 | case STMP3XXX_BUS_APBX: | 340 | case STMP3XXX_BUS_APBX: |
346 | /* Set counting semaphore (kicks off transfer). Assumes | 341 | c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel; |
347 | peripheral has been set up correctly */ | 342 | mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA; |
348 | HW_APBX_CHn_SEMA_CLR(chain->channel, | 343 | mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA); |
349 | BM_APBX_CHn_SEMA_INCREMENT_SEMA); | ||
350 | HW_APBX_CHn_SEMA_SET(chain->channel, | ||
351 | BF_APBX_CHn_SEMA_INCREMENT_SEMA(count)); | ||
352 | break; | 344 | break; |
353 | |||
354 | default: | 345 | default: |
355 | BUG(); | 346 | BUG(); |
347 | return; | ||
356 | } | 348 | } |
349 | |||
350 | /* Set counting semaphore (kicks off transfer). Assumes | ||
351 | peripheral has been set up correctly */ | ||
352 | stmp3xxx_clearl(mask_clr, c); | ||
353 | stmp3xxx_setl(mask, c); | ||
357 | } | 354 | } |
358 | EXPORT_SYMBOL(stmp37xx_circ_advance_active); | 355 | EXPORT_SYMBOL(stmp37xx_circ_advance_active); |
359 | 356 | ||
@@ -362,7 +359,7 @@ unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain) | |||
362 | unsigned cooked; | 359 | unsigned cooked; |
363 | 360 | ||
364 | cooked = chain->active_count - | 361 | cooked = chain->active_count - |
365 | stmp3xxx_dma_read_semaphore(STMP3xxx_DMA(chain->channel, chain->bus)); | 362 | stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus)); |
366 | 363 | ||
367 | chain->active_count -= cooked; | 364 | chain->active_count -= cooked; |
368 | chain->active_index += cooked; | 365 | chain->active_index += cooked; |
@@ -383,38 +380,41 @@ void stmp3xxx_dma_set_alt_target(int channel, int function) | |||
383 | #else | 380 | #else |
384 | #error wrong arch | 381 | #error wrong arch |
385 | #endif | 382 | #endif |
386 | int shift = dmach(channel) * bits; | 383 | int shift = STMP3XXX_DMA_CHANNEL(channel) * bits; |
387 | unsigned mask = (1<<bits) - 1; | 384 | unsigned mask = (1<<bits) - 1; |
385 | void __iomem *c; | ||
388 | 386 | ||
389 | BUG_ON(function < 0 || function >= (1<<bits)); | 387 | BUG_ON(function < 0 || function >= (1<<bits)); |
390 | pr_debug("%s: channel = %d, using mask %x, " | 388 | pr_debug("%s: channel = %d, using mask %x, " |
391 | "shift = %d\n", __func__, channel, mask, shift); | 389 | "shift = %d\n", __func__, channel, mask, shift); |
392 | 390 | ||
393 | switch (dmabus(channel)) { | 391 | switch (STMP3XXX_DMA_BUS(channel)) { |
394 | case STMP3XXX_BUS_APBH: | 392 | case STMP3XXX_BUS_APBH: |
395 | HW_APBH_DEVSEL_CLR(mask<<shift); | 393 | c = REGS_APBH_BASE + HW_APBH_DEVSEL; |
396 | HW_APBH_DEVSEL_SET(function<<shift); | ||
397 | break; | 394 | break; |
398 | case STMP3XXX_BUS_APBX: | 395 | case STMP3XXX_BUS_APBX: |
399 | HW_APBX_DEVSEL_CLR(mask<<shift); | 396 | c = REGS_APBX_BASE + HW_APBX_DEVSEL; |
400 | HW_APBX_DEVSEL_SET(function<<shift); | ||
401 | break; | 397 | break; |
402 | default: | 398 | default: |
403 | BUG(); | 399 | BUG(); |
404 | } | 400 | } |
401 | stmp3xxx_clearl(mask << shift, c); | ||
402 | stmp3xxx_setl(mask << shift, c); | ||
405 | } | 403 | } |
406 | EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target); | 404 | EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target); |
407 | 405 | ||
408 | void stmp3xxx_dma_suspend(void) | 406 | void stmp3xxx_dma_suspend(void) |
409 | { | 407 | { |
410 | HW_APBH_CTRL0_SET(BM_APBH_CTRL0_CLKGATE); | 408 | stmp3xxx_setl(BM_APBH_CTRL0_CLKGATE, REGS_APBH_BASE + HW_APBH_CTRL0); |
411 | HW_APBX_CTRL0_SET(BM_APBX_CTRL0_CLKGATE); | 409 | stmp3xxx_setl(BM_APBX_CTRL0_CLKGATE, REGS_APBX_BASE + HW_APBX_CTRL0); |
412 | } | 410 | } |
413 | 411 | ||
414 | void stmp3xxx_dma_resume(void) | 412 | void stmp3xxx_dma_resume(void) |
415 | { | 413 | { |
416 | HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST); | 414 | stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST, |
417 | HW_APBX_CTRL0_CLR(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST); | 415 | REGS_APBH_BASE + HW_APBH_CTRL0); |
416 | stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST, | ||
417 | REGS_APBX_BASE + HW_APBX_CTRL0); | ||
418 | } | 418 | } |
419 | 419 | ||
420 | #ifdef CONFIG_CPU_FREQ | 420 | #ifdef CONFIG_CPU_FREQ |
@@ -452,11 +452,12 @@ static struct dma_notifier_block dma_cpufreq_nb = { | |||
452 | 452 | ||
453 | void __init stmp3xxx_dma_init(void) | 453 | void __init stmp3xxx_dma_init(void) |
454 | { | 454 | { |
455 | HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST); | 455 | stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST, |
456 | HW_APBX_CTRL0_CLR(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST); | 456 | REGS_APBH_BASE + HW_APBH_CTRL0); |
457 | stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST, | ||
458 | REGS_APBX_BASE + HW_APBX_CTRL0); | ||
457 | #ifdef CONFIG_CPU_FREQ | 459 | #ifdef CONFIG_CPU_FREQ |
458 | cpufreq_register_notifier(&dma_cpufreq_nb.nb, | 460 | cpufreq_register_notifier(&dma_cpufreq_nb.nb, |
459 | CPUFREQ_TRANSITION_NOTIFIER); | 461 | CPUFREQ_TRANSITION_NOTIFIER); |
460 | #endif /* CONFIG_CPU_FREQ */ | 462 | #endif /* CONFIG_CPU_FREQ */ |
461 | |||
462 | } | 463 | } |