diff options
author | dmitry pervushin <dpervushin@embeddedalley.com> | 2009-05-31 08:32:11 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-05-31 08:55:56 -0400 |
commit | 98f420b23a62e0c9df78c5851860d47bf1bc87dd (patch) | |
tree | b7e88059454d2410b1a2107c17a748a03d366fdf /arch/arm/plat-stmp3xxx/clock.c | |
parent | 3f52326a85666c1cb0210eb5556ef3d483933cfc (diff) |
[ARM] 5532/1: Freescale STMP: register definitions [3/3]
Replace HW_zzz register access macros by regular __raw_readl/__raw_writel calls
Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/plat-stmp3xxx/clock.c')
-rw-r--r-- | arch/arm/plat-stmp3xxx/clock.c | 167 |
1 files changed, 95 insertions, 72 deletions
diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c index 9a1d46b470cd..5d2f19a09e44 100644 --- a/arch/arm/plat-stmp3xxx/clock.c +++ b/arch/arm/plat-stmp3xxx/clock.c | |||
@@ -15,6 +15,7 @@ | |||
15 | * http://www.opensource.org/licenses/gpl-license.html | 15 | * http://www.opensource.org/licenses/gpl-license.html |
16 | * http://www.gnu.org/copyleft/gpl.html | 16 | * http://www.gnu.org/copyleft/gpl.html |
17 | */ | 17 | */ |
18 | #define DEBUG | ||
18 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
19 | #include <linux/module.h> | 20 | #include <linux/module.h> |
20 | #include <linux/init.h> | 21 | #include <linux/init.h> |
@@ -27,6 +28,7 @@ | |||
27 | 28 | ||
28 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
29 | #include <asm/clkdev.h> | 30 | #include <asm/clkdev.h> |
31 | #include <mach/platform.h> | ||
30 | #include <mach/regs-clkctrl.h> | 32 | #include <mach/regs-clkctrl.h> |
31 | 33 | ||
32 | #include "clock.h" | 34 | #include "clock.h" |
@@ -187,8 +189,8 @@ static long lcdif_get_rate(struct clk *clk) | |||
187 | div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; | 189 | div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; |
188 | if (div) { | 190 | if (div) { |
189 | rate /= div; | 191 | rate /= div; |
190 | div = (HW_CLKCTRL_FRAC_RD() & BM_CLKCTRL_FRAC_PIXFRAC) >> | 192 | div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) & |
191 | BP_CLKCTRL_FRAC_PIXFRAC; | 193 | BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC; |
192 | rate /= div; | 194 | rate /= div; |
193 | } | 195 | } |
194 | clk->rate = rate; | 196 | clk->rate = rate; |
@@ -263,15 +265,19 @@ static int lcdif_set_rate(struct clk *clk, u32 rate) | |||
263 | lowest_result / 1000, lowest_result % 1000); | 265 | lowest_result / 1000, lowest_result % 1000); |
264 | 266 | ||
265 | /* Program ref_pix phase fractional divider */ | 267 | /* Program ref_pix phase fractional divider */ |
266 | HW_CLKCTRL_FRAC_WR((HW_CLKCTRL_FRAC_RD() & ~BM_CLKCTRL_FRAC_PIXFRAC) | | 268 | reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); |
267 | BF_CLKCTRL_FRAC_PIXFRAC(lowest_fracdiv)); | 269 | reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC; |
270 | reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC); | ||
271 | __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); | ||
272 | |||
268 | /* Ungate PFD */ | 273 | /* Ungate PFD */ |
269 | HW_CLKCTRL_FRAC_CLR(BM_CLKCTRL_FRAC_CLKGATEPIX); | 274 | stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX, |
275 | REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); | ||
270 | 276 | ||
271 | /* Program pix divider */ | 277 | /* Program pix divider */ |
272 | reg_val = __raw_readl(clk->scale_reg); | 278 | reg_val = __raw_readl(clk->scale_reg); |
273 | reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE); | 279 | reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE); |
274 | reg_val |= BF_CLKCTRL_PIX_DIV(lowest_div); | 280 | reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV); |
275 | __raw_writel(reg_val, clk->scale_reg); | 281 | __raw_writel(reg_val, clk->scale_reg); |
276 | 282 | ||
277 | /* Wait for divider update */ | 283 | /* Wait for divider update */ |
@@ -287,7 +293,9 @@ static int lcdif_set_rate(struct clk *clk, u32 rate) | |||
287 | } | 293 | } |
288 | 294 | ||
289 | /* Switch to ref_pix source */ | 295 | /* Switch to ref_pix source */ |
290 | HW_CLKCTRL_CLKSEQ_CLR(BM_CLKCTRL_CLKSEQ_BYPASS_PIX); | 296 | reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ); |
297 | reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX; | ||
298 | __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ); | ||
291 | 299 | ||
292 | out: | 300 | out: |
293 | return ret; | 301 | return ret; |
@@ -296,6 +304,8 @@ out: | |||
296 | 304 | ||
297 | static int cpu_set_rate(struct clk *clk, u32 rate) | 305 | static int cpu_set_rate(struct clk *clk, u32 rate) |
298 | { | 306 | { |
307 | u32 reg_val; | ||
308 | |||
299 | if (rate < 24000) | 309 | if (rate < 24000) |
300 | return -EINVAL; | 310 | return -EINVAL; |
301 | else if (rate == 24000) { | 311 | else if (rate == 24000) { |
@@ -344,7 +354,12 @@ static int cpu_set_rate(struct clk *clk, u32 rate) | |||
344 | __raw_writel(1<<7, clk->scale_reg + 8); | 354 | __raw_writel(1<<7, clk->scale_reg + 8); |
345 | /* write clkctrl_cpu */ | 355 | /* write clkctrl_cpu */ |
346 | clk->saved_div = clkctrl_cpu; | 356 | clk->saved_div = clkctrl_cpu; |
347 | HW_CLKCTRL_CPU_WR((HW_CLKCTRL_CPU_RD() & ~0x3f) | clkctrl_cpu); | 357 | |
358 | reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); | ||
359 | reg_val &= ~0x3F; | ||
360 | reg_val |= clkctrl_cpu; | ||
361 | __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); | ||
362 | |||
348 | for (i = 10000; i; i--) | 363 | for (i = 10000; i; i--) |
349 | if (!clk_is_busy(clk)) | 364 | if (!clk_is_busy(clk)) |
350 | break; | 365 | break; |
@@ -364,7 +379,7 @@ static long cpu_get_rate(struct clk *clk) | |||
364 | long rate = clk->parent->rate * 18; | 379 | long rate = clk->parent->rate * 18; |
365 | 380 | ||
366 | rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; | 381 | rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; |
367 | rate /= HW_CLKCTRL_CPU_RD() & 0x3f; | 382 | rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f; |
368 | rate = ((rate + 9) / 10) * 10; | 383 | rate = ((rate + 9) / 10) * 10; |
369 | clk->rate = rate; | 384 | clk->rate = rate; |
370 | 385 | ||
@@ -411,7 +426,7 @@ static long emi_get_rate(struct clk *clk) | |||
411 | long rate = clk->parent->rate * 18; | 426 | long rate = clk->parent->rate * 18; |
412 | 427 | ||
413 | rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; | 428 | rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; |
414 | rate /= HW_CLKCTRL_EMI_RD() & 0x3f; | 429 | rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f; |
415 | clk->rate = rate; | 430 | clk->rate = rate; |
416 | 431 | ||
417 | return rate; | 432 | return rate; |
@@ -427,44 +442,52 @@ static int clkseq_set_parent(struct clk *clk, struct clk *parent) | |||
427 | shift = 4; | 442 | shift = 4; |
428 | 443 | ||
429 | if (clk->bypass_reg) { | 444 | if (clk->bypass_reg) { |
430 | u32 hbus_mask = BM_CLKCTRL_HBUS_DIV_FRAC_EN | | 445 | #ifdef CONFIG_ARCH_STMP378X |
431 | BM_CLKCTRL_HBUS_DIV; | 446 | u32 hbus_val, cpu_val; |
432 | 447 | ||
433 | if (clk == &cpu_clk && shift == 4) { | 448 | if (clk == &cpu_clk && shift == 4) { |
434 | u32 hbus_val = HW_CLKCTRL_HBUS_RD(); | 449 | hbus_val = __raw_readl(REGS_CLKCTRL_BASE + |
435 | u32 cpu_val = HW_CLKCTRL_CPU_RD(); | 450 | HW_CLKCTRL_HBUS); |
436 | hbus_val &= ~hbus_mask; | 451 | cpu_val = __raw_readl(REGS_CLKCTRL_BASE + |
437 | hbus_val |= 1; | 452 | HW_CLKCTRL_CPU); |
453 | |||
454 | hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | | ||
455 | BM_CLKCTRL_HBUS_DIV); | ||
438 | clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU; | 456 | clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU; |
439 | cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; | 457 | cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; |
440 | cpu_val |= 1; | 458 | cpu_val |= 1; |
441 | __raw_writel(1 << clk->bypass_shift, | 459 | |
442 | clk->bypass_reg + shift); | ||
443 | if (machine_is_stmp378x()) { | 460 | if (machine_is_stmp378x()) { |
444 | HW_CLKCTRL_HBUS_WR(hbus_val); | 461 | __raw_writel(hbus_val, |
445 | HW_CLKCTRL_CPU_WR(cpu_val); | 462 | REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); |
463 | __raw_writel(cpu_val, | ||
464 | REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); | ||
446 | hclk.rate = 0; | 465 | hclk.rate = 0; |
447 | } | 466 | } |
448 | } else if (clk == &cpu_clk && shift == 8) { | 467 | } else if (clk == &cpu_clk && shift == 8) { |
449 | u32 hbus_val = HW_CLKCTRL_HBUS_RD(); | 468 | hbus_val = __raw_readl(REGS_CLKCTRL_BASE + |
450 | u32 cpu_val = HW_CLKCTRL_CPU_RD(); | 469 | HW_CLKCTRL_HBUS); |
451 | hbus_val &= ~hbus_mask; | 470 | cpu_val = __raw_readl(REGS_CLKCTRL_BASE + |
471 | HW_CLKCTRL_CPU); | ||
472 | hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | | ||
473 | BM_CLKCTRL_HBUS_DIV); | ||
452 | hbus_val |= 2; | 474 | hbus_val |= 2; |
453 | cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; | 475 | cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; |
454 | if (clk->saved_div) | 476 | if (clk->saved_div) |
455 | cpu_val |= clk->saved_div; | 477 | cpu_val |= clk->saved_div; |
456 | else | 478 | else |
457 | cpu_val |= 2; | 479 | cpu_val |= 2; |
480 | |||
458 | if (machine_is_stmp378x()) { | 481 | if (machine_is_stmp378x()) { |
459 | HW_CLKCTRL_HBUS_WR(hbus_val); | 482 | __raw_writel(hbus_val, |
460 | HW_CLKCTRL_CPU_WR(cpu_val); | 483 | REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); |
484 | __raw_writel(cpu_val, | ||
485 | REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); | ||
461 | hclk.rate = 0; | 486 | hclk.rate = 0; |
462 | } | 487 | } |
463 | __raw_writel(1 << clk->bypass_shift, | 488 | } |
464 | clk->bypass_reg + shift); | 489 | #endif |
465 | } else | 490 | __raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift); |
466 | __raw_writel(1 << clk->bypass_shift, | ||
467 | clk->bypass_reg + shift); | ||
468 | 491 | ||
469 | ret = 0; | 492 | ret = 0; |
470 | } | 493 | } |
@@ -640,7 +663,7 @@ static struct clk osc_24M = { | |||
640 | 663 | ||
641 | static struct clk pll_clk = { | 664 | static struct clk pll_clk = { |
642 | .parent = &osc_24M, | 665 | .parent = &osc_24M, |
643 | .enable_reg = HW_CLKCTRL_PLLCTRL0_ADDR, | 666 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0, |
644 | .enable_shift = 16, | 667 | .enable_shift = 16, |
645 | .enable_wait = 10, | 668 | .enable_wait = 10, |
646 | .flags = FIXED_RATE | ENABLED, | 669 | .flags = FIXED_RATE | ENABLED, |
@@ -650,11 +673,11 @@ static struct clk pll_clk = { | |||
650 | 673 | ||
651 | static struct clk cpu_clk = { | 674 | static struct clk cpu_clk = { |
652 | .parent = &pll_clk, | 675 | .parent = &pll_clk, |
653 | .scale_reg = HW_CLKCTRL_FRAC_ADDR, | 676 | .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, |
654 | .scale_shift = 0, | 677 | .scale_shift = 0, |
655 | .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, | 678 | .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, |
656 | .bypass_shift = 7, | 679 | .bypass_shift = 7, |
657 | .busy_reg = HW_CLKCTRL_CPU_ADDR, | 680 | .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU, |
658 | .busy_bit = 28, | 681 | .busy_bit = 28, |
659 | .flags = RATE_PROPAGATES | ENABLED, | 682 | .flags = RATE_PROPAGATES | ENABLED, |
660 | .ops = &cpu_ops, | 683 | .ops = &cpu_ops, |
@@ -662,10 +685,10 @@ static struct clk cpu_clk = { | |||
662 | 685 | ||
663 | static struct clk io_clk = { | 686 | static struct clk io_clk = { |
664 | .parent = &pll_clk, | 687 | .parent = &pll_clk, |
665 | .enable_reg = HW_CLKCTRL_FRAC_ADDR, | 688 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, |
666 | .enable_shift = 31, | 689 | .enable_shift = 31, |
667 | .enable_negate = 1, | 690 | .enable_negate = 1, |
668 | .scale_reg = HW_CLKCTRL_FRAC_ADDR, | 691 | .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, |
669 | .scale_shift = 24, | 692 | .scale_shift = 24, |
670 | .flags = RATE_PROPAGATES | ENABLED, | 693 | .flags = RATE_PROPAGATES | ENABLED, |
671 | .ops = &io_ops, | 694 | .ops = &io_ops, |
@@ -673,10 +696,10 @@ static struct clk io_clk = { | |||
673 | 696 | ||
674 | static struct clk hclk = { | 697 | static struct clk hclk = { |
675 | .parent = &cpu_clk, | 698 | .parent = &cpu_clk, |
676 | .scale_reg = HW_CLKCTRL_HBUS_ADDR, | 699 | .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS, |
677 | .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, | 700 | .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, |
678 | .bypass_shift = 7, | 701 | .bypass_shift = 7, |
679 | .busy_reg = HW_CLKCTRL_HBUS_ADDR, | 702 | .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS, |
680 | .busy_bit = 29, | 703 | .busy_bit = 29, |
681 | .flags = RATE_PROPAGATES | ENABLED, | 704 | .flags = RATE_PROPAGATES | ENABLED, |
682 | .ops = &hbus_ops, | 705 | .ops = &hbus_ops, |
@@ -684,8 +707,8 @@ static struct clk hclk = { | |||
684 | 707 | ||
685 | static struct clk xclk = { | 708 | static struct clk xclk = { |
686 | .parent = &osc_24M, | 709 | .parent = &osc_24M, |
687 | .scale_reg = HW_CLKCTRL_XBUS_ADDR, | 710 | .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS, |
688 | .busy_reg = HW_CLKCTRL_XBUS_ADDR, | 711 | .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS, |
689 | .busy_bit = 31, | 712 | .busy_bit = 31, |
690 | .flags = RATE_PROPAGATES | ENABLED, | 713 | .flags = RATE_PROPAGATES | ENABLED, |
691 | .ops = &xbus_ops, | 714 | .ops = &xbus_ops, |
@@ -693,7 +716,7 @@ static struct clk xclk = { | |||
693 | 716 | ||
694 | static struct clk uart_clk = { | 717 | static struct clk uart_clk = { |
695 | .parent = &xclk, | 718 | .parent = &xclk, |
696 | .enable_reg = HW_CLKCTRL_XTAL_ADDR, | 719 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, |
697 | .enable_shift = 31, | 720 | .enable_shift = 31, |
698 | .enable_negate = 1, | 721 | .enable_negate = 1, |
699 | .flags = ENABLED, | 722 | .flags = ENABLED, |
@@ -702,7 +725,7 @@ static struct clk uart_clk = { | |||
702 | 725 | ||
703 | static struct clk audio_clk = { | 726 | static struct clk audio_clk = { |
704 | .parent = &xclk, | 727 | .parent = &xclk, |
705 | .enable_reg = HW_CLKCTRL_XTAL_ADDR, | 728 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, |
706 | .enable_shift = 30, | 729 | .enable_shift = 30, |
707 | .enable_negate = 1, | 730 | .enable_negate = 1, |
708 | .ops = &min_ops, | 731 | .ops = &min_ops, |
@@ -710,7 +733,7 @@ static struct clk audio_clk = { | |||
710 | 733 | ||
711 | static struct clk pwm_clk = { | 734 | static struct clk pwm_clk = { |
712 | .parent = &xclk, | 735 | .parent = &xclk, |
713 | .enable_reg = HW_CLKCTRL_XTAL_ADDR, | 736 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, |
714 | .enable_shift = 29, | 737 | .enable_shift = 29, |
715 | .enable_negate = 1, | 738 | .enable_negate = 1, |
716 | .ops = &min_ops, | 739 | .ops = &min_ops, |
@@ -718,7 +741,7 @@ static struct clk pwm_clk = { | |||
718 | 741 | ||
719 | static struct clk dri_clk = { | 742 | static struct clk dri_clk = { |
720 | .parent = &xclk, | 743 | .parent = &xclk, |
721 | .enable_reg = HW_CLKCTRL_XTAL_ADDR, | 744 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, |
722 | .enable_shift = 28, | 745 | .enable_shift = 28, |
723 | .enable_negate = 1, | 746 | .enable_negate = 1, |
724 | .ops = &min_ops, | 747 | .ops = &min_ops, |
@@ -726,7 +749,7 @@ static struct clk dri_clk = { | |||
726 | 749 | ||
727 | static struct clk digctl_clk = { | 750 | static struct clk digctl_clk = { |
728 | .parent = &xclk, | 751 | .parent = &xclk, |
729 | .enable_reg = HW_CLKCTRL_XTAL_ADDR, | 752 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, |
730 | .enable_shift = 27, | 753 | .enable_shift = 27, |
731 | .enable_negate = 1, | 754 | .enable_negate = 1, |
732 | .ops = &min_ops, | 755 | .ops = &min_ops, |
@@ -734,7 +757,7 @@ static struct clk digctl_clk = { | |||
734 | 757 | ||
735 | static struct clk timer_clk = { | 758 | static struct clk timer_clk = { |
736 | .parent = &xclk, | 759 | .parent = &xclk, |
737 | .enable_reg = HW_CLKCTRL_XTAL_ADDR, | 760 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, |
738 | .enable_shift = 26, | 761 | .enable_shift = 26, |
739 | .enable_negate = 1, | 762 | .enable_negate = 1, |
740 | .flags = ENABLED, | 763 | .flags = ENABLED, |
@@ -743,13 +766,13 @@ static struct clk timer_clk = { | |||
743 | 766 | ||
744 | static struct clk lcdif_clk = { | 767 | static struct clk lcdif_clk = { |
745 | .parent = &pll_clk, | 768 | .parent = &pll_clk, |
746 | .scale_reg = HW_CLKCTRL_PIX_ADDR, | 769 | .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, |
747 | .busy_reg = HW_CLKCTRL_PIX_ADDR, | 770 | .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, |
748 | .busy_bit = 29, | 771 | .busy_bit = 29, |
749 | .enable_reg = HW_CLKCTRL_PIX_ADDR, | 772 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, |
750 | .enable_shift = 31, | 773 | .enable_shift = 31, |
751 | .enable_negate = 1, | 774 | .enable_negate = 1, |
752 | .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, | 775 | .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, |
753 | .bypass_shift = 1, | 776 | .bypass_shift = 1, |
754 | .flags = NEEDS_SET_PARENT, | 777 | .flags = NEEDS_SET_PARENT, |
755 | .ops = &lcdif_ops, | 778 | .ops = &lcdif_ops, |
@@ -757,12 +780,12 @@ static struct clk lcdif_clk = { | |||
757 | 780 | ||
758 | static struct clk ssp_clk = { | 781 | static struct clk ssp_clk = { |
759 | .parent = &io_clk, | 782 | .parent = &io_clk, |
760 | .scale_reg = HW_CLKCTRL_SSP_ADDR, | 783 | .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, |
761 | .busy_reg = HW_CLKCTRL_SSP_ADDR, | 784 | .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, |
762 | .busy_bit = 29, | 785 | .busy_bit = 29, |
763 | .enable_reg = HW_CLKCTRL_SSP_ADDR, | 786 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, |
764 | .enable_shift = 31, | 787 | .enable_shift = 31, |
765 | .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, | 788 | .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, |
766 | .bypass_shift = 5, | 789 | .bypass_shift = 5, |
767 | .enable_negate = 1, | 790 | .enable_negate = 1, |
768 | .flags = NEEDS_SET_PARENT, | 791 | .flags = NEEDS_SET_PARENT, |
@@ -771,13 +794,13 @@ static struct clk ssp_clk = { | |||
771 | 794 | ||
772 | static struct clk gpmi_clk = { | 795 | static struct clk gpmi_clk = { |
773 | .parent = &io_clk, | 796 | .parent = &io_clk, |
774 | .scale_reg = HW_CLKCTRL_GPMI_ADDR, | 797 | .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, |
775 | .busy_reg = HW_CLKCTRL_GPMI_ADDR, | 798 | .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, |
776 | .busy_bit = 29, | 799 | .busy_bit = 29, |
777 | .enable_reg = HW_CLKCTRL_GPMI_ADDR, | 800 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, |
778 | .enable_shift = 31, | 801 | .enable_shift = 31, |
779 | .enable_negate = 1, | 802 | .enable_negate = 1, |
780 | .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, | 803 | .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, |
781 | .bypass_shift = 4, | 804 | .bypass_shift = 4, |
782 | .flags = NEEDS_SET_PARENT, | 805 | .flags = NEEDS_SET_PARENT, |
783 | .ops = &std_ops, | 806 | .ops = &std_ops, |
@@ -785,7 +808,7 @@ static struct clk gpmi_clk = { | |||
785 | 808 | ||
786 | static struct clk spdif_clk = { | 809 | static struct clk spdif_clk = { |
787 | .parent = &pll_clk, | 810 | .parent = &pll_clk, |
788 | .enable_reg = HW_CLKCTRL_SPDIF_ADDR, | 811 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF, |
789 | .enable_shift = 31, | 812 | .enable_shift = 31, |
790 | .enable_negate = 1, | 813 | .enable_negate = 1, |
791 | .ops = &min_ops, | 814 | .ops = &min_ops, |
@@ -793,14 +816,14 @@ static struct clk spdif_clk = { | |||
793 | 816 | ||
794 | static struct clk emi_clk = { | 817 | static struct clk emi_clk = { |
795 | .parent = &pll_clk, | 818 | .parent = &pll_clk, |
796 | .enable_reg = HW_CLKCTRL_EMI_ADDR, | 819 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI, |
797 | .enable_shift = 31, | 820 | .enable_shift = 31, |
798 | .enable_negate = 1, | 821 | .enable_negate = 1, |
799 | .scale_reg = HW_CLKCTRL_FRAC_ADDR, | 822 | .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, |
800 | .scale_shift = 8, | 823 | .scale_shift = 8, |
801 | .busy_reg = HW_CLKCTRL_EMI_ADDR, | 824 | .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI, |
802 | .busy_bit = 28, | 825 | .busy_bit = 28, |
803 | .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, | 826 | .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, |
804 | .bypass_shift = 6, | 827 | .bypass_shift = 6, |
805 | .flags = ENABLED, | 828 | .flags = ENABLED, |
806 | .ops = &emi_ops, | 829 | .ops = &emi_ops, |
@@ -808,37 +831,37 @@ static struct clk emi_clk = { | |||
808 | 831 | ||
809 | static struct clk ir_clk = { | 832 | static struct clk ir_clk = { |
810 | .parent = &io_clk, | 833 | .parent = &io_clk, |
811 | .enable_reg = HW_CLKCTRL_IR_ADDR, | 834 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR, |
812 | .enable_shift = 31, | 835 | .enable_shift = 31, |
813 | .enable_negate = 1, | 836 | .enable_negate = 1, |
814 | .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, | 837 | .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, |
815 | .bypass_shift = 3, | 838 | .bypass_shift = 3, |
816 | .ops = &min_ops, | 839 | .ops = &min_ops, |
817 | }; | 840 | }; |
818 | 841 | ||
819 | static struct clk saif_clk = { | 842 | static struct clk saif_clk = { |
820 | .parent = &pll_clk, | 843 | .parent = &pll_clk, |
821 | .scale_reg = HW_CLKCTRL_SAIF_ADDR, | 844 | .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, |
822 | .busy_reg = HW_CLKCTRL_SAIF_ADDR, | 845 | .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, |
823 | .busy_bit = 29, | 846 | .busy_bit = 29, |
824 | .enable_reg = HW_CLKCTRL_SAIF_ADDR, | 847 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, |
825 | .enable_shift = 31, | 848 | .enable_shift = 31, |
826 | .enable_negate = 1, | 849 | .enable_negate = 1, |
827 | .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, | 850 | .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, |
828 | .bypass_shift = 0, | 851 | .bypass_shift = 0, |
829 | .ops = &std_ops, | 852 | .ops = &std_ops, |
830 | }; | 853 | }; |
831 | 854 | ||
832 | static struct clk usb_clk = { | 855 | static struct clk usb_clk = { |
833 | .parent = &pll_clk, | 856 | .parent = &pll_clk, |
834 | .enable_reg = HW_CLKCTRL_PLLCTRL0_ADDR, | 857 | .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0, |
835 | .enable_shift = 18, | 858 | .enable_shift = 18, |
836 | .enable_negate = 1, | 859 | .enable_negate = 1, |
837 | .ops = &min_ops, | 860 | .ops = &min_ops, |
838 | }; | 861 | }; |
839 | 862 | ||
840 | /* list of all the clocks */ | 863 | /* list of all the clocks */ |
841 | static __initdata struct clk_lookup onchip_clks[] = { | 864 | static struct clk_lookup onchip_clks[] = { |
842 | { | 865 | { |
843 | .con_id = "osc_24M", | 866 | .con_id = "osc_24M", |
844 | .clk = &osc_24M, | 867 | .clk = &osc_24M, |