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authorArnd Bergmann <arnd@arndb.de>2014-07-26 06:01:10 -0400
committerArnd Bergmann <arnd@arndb.de>2014-07-26 06:01:27 -0400
commit96bda115ec552ff75319f85828f6c333d101b401 (patch)
treee30895f65413fdf8fd91c026faad1a3fb54b0653 /arch/arm/plat-samsung
parent8e5655cd4f7e140ceb24705f913406e9f56b7d54 (diff)
parentf1ff47454bb2fe0d5644f981679d1bea532816fd (diff)
Merge tag 's5pv210-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
Merge "Samsung S5PV210 DT support for v3.17" from Kukjin Kim: - support common clock framework for s5pv210 clock - add generic PHY driver on s5pv210 to support it via DT - add dt support for s5pv210-goni, smdkc110, smdkv210 and torbreck boards - remove board files from mach-s5pv210 and unused codes - enable multiplatform for s5pv210 * tag 's5pv210-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: clk: samsung: s5pv210: Remove legacy board support ARM: SAMSUNG: Remove remaining legacy code gpio: samsung: Remove legacy support of S5PV210 ARM: S5PV210: Enable multi-platform build support cpufreq: s5pv210: Make the driver multiplatform aware ARM: S5PV210: Register cpufreq platform device ARM: S5PV210: move debug-macro.S into the common space ARM: S5PV210: Untie PM support from legacy code ARM: S5PV210: Remove support for board files ARM: dts: Add Device tree for s5pc110/s5pv210 boards ARM: dts: Add Device tree for s5pv210 SoC ARM: S5PV210: Add board file for boot using Device Tree phy: Add support for S5PV210 to the Exynos USB 2.0 PHY driver clk: samsung: Add S5PV210 Audio Subsystem clock driver ARM: SAMSUNG: Remove legacy clock code serial: samsung: Remove support for legacy clock code cpufreq: s3c24xx: Remove some dead code ARM: S5PV210: Migrate clock handling to Common Clock Framework clk: samsung: Add clock driver for S5PV210 and compatible SoCs Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/plat-samsung')
-rw-r--r--arch/arm/plat-samsung/Kconfig143
-rw-r--r--arch/arm/plat-samsung/Makefile15
-rw-r--r--arch/arm/plat-samsung/clock-clksrc.c212
-rw-r--r--arch/arm/plat-samsung/clock.c539
-rw-r--r--arch/arm/plat-samsung/cpu.c3
-rw-r--r--arch/arm/plat-samsung/devs.c330
-rw-r--r--arch/arm/plat-samsung/include/plat/camport.h28
-rw-r--r--arch/arm/plat-samsung/include/plat/clock-clksrc.h83
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h152
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu-freq-core.h3
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h13
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h42
-rw-r--r--arch/arm/plat-samsung/include/plat/fb-core.h15
-rw-r--r--arch/arm/plat-samsung/include/plat/fb.h22
-rw-r--r--arch/arm/plat-samsung/include/plat/fimc-core.h51
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg.h64
-rw-r--r--arch/arm/plat-samsung/include/plat/hdmi.h16
-rw-r--r--arch/arm/plat-samsung/include/plat/irqs.h72
-rw-r--r--arch/arm/plat-samsung/include/plat/mfc.h35
-rw-r--r--arch/arm/plat-samsung/include/plat/pll.h323
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p-clock.h65
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h47
-rw-r--r--arch/arm/plat-samsung/include/plat/tv-core.h44
-rw-r--r--arch/arm/plat-samsung/init.c1
-rw-r--r--arch/arm/plat-samsung/pm-gpio.c4
-rw-r--r--arch/arm/plat-samsung/s5p-clock.c294
-rw-r--r--arch/arm/plat-samsung/s5p-dev-mfc.c81
-rw-r--r--arch/arm/plat-samsung/s5p-dev-uart.c88
-rw-r--r--arch/arm/plat-samsung/s5p-irq-eint.c221
-rw-r--r--arch/arm/plat-samsung/s5p-irq-gpioint.c218
-rw-r--r--arch/arm/plat-samsung/s5p-irq-pm.c92
-rw-r--r--arch/arm/plat-samsung/s5p-irq.c31
-rw-r--r--arch/arm/plat-samsung/s5p-pm.c40
-rw-r--r--arch/arm/plat-samsung/s5p-sleep.S45
34 files changed, 14 insertions, 3418 deletions
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 1c629c2c270f..1091b0a3729a 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -6,30 +6,16 @@
6 6
7config PLAT_SAMSUNG 7config PLAT_SAMSUNG
8 bool 8 bool
9 depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P || ARCH_EXYNOS 9 depends on PLAT_S3C24XX || ARCH_S3C64XX || ARCH_EXYNOS || ARCH_S5PV210
10 default y 10 default y
11 select GENERIC_IRQ_CHIP 11 select GENERIC_IRQ_CHIP
12 select NO_IOPORT_MAP 12 select NO_IOPORT_MAP
13 help 13 help
14 Base platform code for all Samsung SoC based systems 14 Base platform code for all Samsung SoC based systems
15 15
16config PLAT_S5P
17 bool
18 depends on ARCH_S5PV210
19 default y
20 select ARCH_REQUIRE_GPIOLIB
21 select ARM_VIC
22 select NO_IOPORT_MAP
23 select PLAT_SAMSUNG
24 select S3C_GPIO_TRACK
25 select S5P_GPIO_DRVSTR
26 select SAMSUNG_CLKSRC if !COMMON_CLK
27 help
28 Base platform code for Samsung's S5P series SoC.
29
30config SAMSUNG_PM 16config SAMSUNG_PM
31 bool 17 bool
32 depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || S5P_PM) 18 depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX)
33 default y 19 default y
34 help 20 help
35 Base platform power management code for samsung code 21 Base platform power management code for samsung code
@@ -65,48 +51,6 @@ config SAMSUNG_ATAGS
65 51
66if SAMSUNG_ATAGS 52if SAMSUNG_ATAGS
67 53
68# clock options
69
70config SAMSUNG_CLOCK
71 bool
72 default y if !COMMON_CLK
73
74config SAMSUNG_CLKSRC
75 bool
76 help
77 Select the clock code for the clksrc implementation
78 used by newer systems such as the S3C64XX.
79
80config S5P_CLOCK
81 def_bool ARCH_S5PV210
82 help
83 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
84
85# options for IRQ support
86
87config S5P_IRQ
88 def_bool ARCH_S5PV210
89 help
90 Support common interrupt part for ARCH_S5P SoCs
91
92config S5P_EXT_INT
93 bool
94 help
95 Use the external interrupts (other than GPIO interrupts.)
96
97config S5P_GPIO_INT
98 bool
99 help
100 Common code for the GPIO interrupts (other than external interrupts.)
101
102# options for gpio configuration support
103
104config S5P_GPIO_DRVSTR
105 bool
106 help
107 Internal configuration to get and set correct GPIO driver strength
108 helper
109
110config SAMSUNG_GPIO_EXTRA 54config SAMSUNG_GPIO_EXTRA
111 int "Number of additional GPIO pins" 55 int "Number of additional GPIO pins"
112 default 128 if SAMSUNG_GPIO_EXTRA128 56 default 128 if SAMSUNG_GPIO_EXTRA128
@@ -138,12 +82,6 @@ config S3C_GPIO_TRACK
138 Internal configuration option to enable the s3c specific gpio 82 Internal configuration option to enable the s3c specific gpio
139 chip tracking if the platform requires it. 83 chip tracking if the platform requires it.
140 84
141# uart options
142
143config S5P_DEV_UART
144 def_bool y
145 depends on ARCH_S5PV210
146
147# ADC driver 85# ADC driver
148 86
149config S3C_ADC 87config S3C_ADC
@@ -301,66 +239,6 @@ config SAMSUNG_DEV_BACKLIGHT
301 help 239 help
302 Compile in platform device definition LCD backlight with PWM Timer 240 Compile in platform device definition LCD backlight with PWM Timer
303 241
304config S5P_DEV_CSIS0
305 bool
306 help
307 Compile in platform device definitions for MIPI-CSIS channel 0
308
309config S5P_DEV_CSIS1
310 bool
311 help
312 Compile in platform device definitions for MIPI-CSIS channel 1
313
314config S5P_DEV_FIMC0
315 bool
316 help
317 Compile in platform device definitions for FIMC controller 0
318
319config S5P_DEV_FIMC1
320 bool
321 help
322 Compile in platform device definitions for FIMC controller 1
323
324config S5P_DEV_FIMC2
325 bool
326 help
327 Compile in platform device definitions for FIMC controller 2
328
329config S5P_DEV_FIMC3
330 bool
331 help
332 Compile in platform device definitions for FIMC controller 3
333
334config S5P_DEV_FIMD0
335 bool
336 help
337 Compile in platform device definitions for FIMD controller 0
338
339config S5P_DEV_G2D
340 bool
341 help
342 Compile in platform device definitions for G2D device
343
344config S5P_DEV_I2C_HDMIPHY
345 bool
346 help
347 Compile in platform device definitions for I2C HDMIPHY controller
348
349config S5P_DEV_JPEG
350 bool
351 help
352 Compile in platform device definitions for JPEG codec
353
354config S5P_DEV_ONENAND
355 bool
356 help
357 Compile in platform device definition for OneNAND controller
358
359config S5P_DEV_TV
360 bool
361 help
362 Compile in platform device definition for TV interface
363
364config S3C24XX_PWM 242config S3C24XX_PWM
365 bool "PWM device support" 243 bool "PWM device support"
366 select PWM 244 select PWM
@@ -381,12 +259,6 @@ config S3C_DMA
381 help 259 help
382 Internal configuration for S3C DMA core 260 Internal configuration for S3C DMA core
383 261
384config S5P_IRQ_PM
385 bool
386 default y if S5P_PM
387 help
388 Legacy IRQ power management for S5P platforms
389
390config SAMSUNG_PM_GPIO 262config SAMSUNG_PM_GPIO
391 bool 263 bool
392 default y if GPIO_SAMSUNG && PM 264 default y if GPIO_SAMSUNG && PM
@@ -469,17 +341,6 @@ config SAMSUNG_WDT_RESET
469 Compile support for system restart by triggering watchdog reset. 341 Compile support for system restart by triggering watchdog reset.
470 Used on SoCs that do not provide dedicated reset control. 342 Used on SoCs that do not provide dedicated reset control.
471 343
472config S5P_PM
473 bool
474 help
475 Common code for power management support on S5P and newer SoCs
476
477config S5P_SLEEP
478 bool
479 help
480 Internal config node to apply common S5P sleep management code.
481 Can be selected by S5P and newer SoCs with similar sleep procedure.
482
483config DEBUG_S3C_UART 344config DEBUG_S3C_UART
484 depends on PLAT_SAMSUNG 345 depends on PLAT_SAMSUNG
485 int 346 int
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 5e5beaa9ae15..5fe175017f07 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -5,7 +5,6 @@
5# Licensed under GPLv2 5# Licensed under GPLv2
6 6
7ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include 7ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include
8ccflags-$(CONFIG_ARCH_EXYNOS) += -I$(srctree)/arch/arm/mach-exynos/include
9 8
10obj-y := 9obj-y :=
11obj-m := 10obj-m :=
@@ -16,15 +15,6 @@ obj- :=
16 15
17obj-y += init.o cpu.o 16obj-y += init.o cpu.o
18 17
19obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o
20
21obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
22obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o
23
24obj-$(CONFIG_S5P_IRQ) += s5p-irq.o
25obj-$(CONFIG_S5P_EXT_INT) += s5p-irq-eint.o
26obj-$(CONFIG_S5P_GPIO_INT) += s5p-irq-gpioint.o
27
28# ADC 18# ADC
29 19
30obj-$(CONFIG_S3C_ADC) += adc.o 20obj-$(CONFIG_S3C_ADC) += adc.o
@@ -36,7 +26,6 @@ obj-$(CONFIG_SAMSUNG_ATAGS) += platformdata.o
36obj-$(CONFIG_SAMSUNG_ATAGS) += devs.o 26obj-$(CONFIG_SAMSUNG_ATAGS) += devs.o
37obj-$(CONFIG_SAMSUNG_ATAGS) += dev-uart.o 27obj-$(CONFIG_SAMSUNG_ATAGS) += dev-uart.o
38obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o 28obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o
39obj-$(CONFIG_S5P_DEV_UART) += s5p-dev-uart.o
40 29
41obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o 30obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o
42 31
@@ -58,7 +47,3 @@ obj-$(CONFIG_SAMSUNG_PM_DEBUG) += pm-debug.o
58 47
59obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o 48obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o
60obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o 49obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o
61
62obj-$(CONFIG_S5P_PM) += s5p-pm.o
63obj-$(CONFIG_S5P_IRQ_PM) += s5p-irq-pm.o
64obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o
diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c
deleted file mode 100644
index 786a4107a157..000000000000
--- a/arch/arm/plat-samsung/clock-clksrc.c
+++ /dev/null
@@ -1,212 +0,0 @@
1/* linux/arch/arm/plat-samsung/clock-clksrc.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/device.h>
20#include <linux/io.h>
21
22#include <plat/clock.h>
23#include <plat/clock-clksrc.h>
24#include <plat/cpu-freq.h>
25
26static inline struct clksrc_clk *to_clksrc(struct clk *clk)
27{
28 return container_of(clk, struct clksrc_clk, clk);
29}
30
31static inline u32 bit_mask(u32 shift, u32 nr_bits)
32{
33 u32 mask = 0xffffffff >> (32 - nr_bits);
34
35 return mask << shift;
36}
37
38static unsigned long s3c_getrate_clksrc(struct clk *clk)
39{
40 struct clksrc_clk *sclk = to_clksrc(clk);
41 unsigned long rate = clk_get_rate(clk->parent);
42 u32 clkdiv = __raw_readl(sclk->reg_div.reg);
43 u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
44
45 clkdiv &= mask;
46 clkdiv >>= sclk->reg_div.shift;
47 clkdiv++;
48
49 rate /= clkdiv;
50 return rate;
51}
52
53static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate)
54{
55 struct clksrc_clk *sclk = to_clksrc(clk);
56 void __iomem *reg = sclk->reg_div.reg;
57 unsigned int div;
58 u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
59 u32 val;
60
61 rate = clk_round_rate(clk, rate);
62 div = clk_get_rate(clk->parent) / rate;
63 if (div > (1 << sclk->reg_div.size))
64 return -EINVAL;
65
66 val = __raw_readl(reg);
67 val &= ~mask;
68 val |= (div - 1) << sclk->reg_div.shift;
69 __raw_writel(val, reg);
70
71 return 0;
72}
73
74static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent)
75{
76 struct clksrc_clk *sclk = to_clksrc(clk);
77 struct clksrc_sources *srcs = sclk->sources;
78 u32 clksrc = __raw_readl(sclk->reg_src.reg);
79 u32 mask = bit_mask(sclk->reg_src.shift, sclk->reg_src.size);
80 int src_nr = -1;
81 int ptr;
82
83 for (ptr = 0; ptr < srcs->nr_sources; ptr++)
84 if (srcs->sources[ptr] == parent) {
85 src_nr = ptr;
86 break;
87 }
88
89 if (src_nr >= 0) {
90 clk->parent = parent;
91
92 clksrc &= ~mask;
93 clksrc |= src_nr << sclk->reg_src.shift;
94
95 __raw_writel(clksrc, sclk->reg_src.reg);
96 return 0;
97 }
98
99 return -EINVAL;
100}
101
102static unsigned long s3c_roundrate_clksrc(struct clk *clk,
103 unsigned long rate)
104{
105 struct clksrc_clk *sclk = to_clksrc(clk);
106 unsigned long parent_rate = clk_get_rate(clk->parent);
107 int max_div = 1 << sclk->reg_div.size;
108 int div;
109
110 if (rate >= parent_rate)
111 rate = parent_rate;
112 else {
113 div = parent_rate / rate;
114 if (parent_rate % rate)
115 div++;
116
117 if (div == 0)
118 div = 1;
119 if (div > max_div)
120 div = max_div;
121
122 rate = parent_rate / div;
123 }
124
125 return rate;
126}
127
128/* Clock initialisation code */
129
130void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk, bool announce)
131{
132 struct clksrc_sources *srcs = clk->sources;
133 u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size);
134 u32 clksrc;
135
136 if (!clk->reg_src.reg) {
137 if (!clk->clk.parent)
138 printk(KERN_ERR "%s: no parent clock specified\n",
139 clk->clk.name);
140 return;
141 }
142
143 clksrc = __raw_readl(clk->reg_src.reg);
144 clksrc &= mask;
145 clksrc >>= clk->reg_src.shift;
146
147 if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
148 printk(KERN_ERR "%s: bad source %d\n",
149 clk->clk.name, clksrc);
150 return;
151 }
152
153 clk->clk.parent = srcs->sources[clksrc];
154
155 if (announce)
156 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
157 clk->clk.name, clk->clk.parent->name, clksrc,
158 clk_get_rate(&clk->clk));
159}
160
161static struct clk_ops clksrc_ops = {
162 .set_parent = s3c_setparent_clksrc,
163 .get_rate = s3c_getrate_clksrc,
164 .set_rate = s3c_setrate_clksrc,
165 .round_rate = s3c_roundrate_clksrc,
166};
167
168static struct clk_ops clksrc_ops_nodiv = {
169 .set_parent = s3c_setparent_clksrc,
170};
171
172static struct clk_ops clksrc_ops_nosrc = {
173 .get_rate = s3c_getrate_clksrc,
174 .set_rate = s3c_setrate_clksrc,
175 .round_rate = s3c_roundrate_clksrc,
176};
177
178void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
179{
180 int ret;
181
182 for (; size > 0; size--, clksrc++) {
183 if (!clksrc->reg_div.reg && !clksrc->reg_src.reg)
184 printk(KERN_ERR "%s: clock %s has no registers set\n",
185 __func__, clksrc->clk.name);
186
187 /* fill in the default functions */
188
189 if (!clksrc->clk.ops) {
190 if (!clksrc->reg_div.reg)
191 clksrc->clk.ops = &clksrc_ops_nodiv;
192 else if (!clksrc->reg_src.reg)
193 clksrc->clk.ops = &clksrc_ops_nosrc;
194 else
195 clksrc->clk.ops = &clksrc_ops;
196 }
197
198 /* setup the clocksource, but do not announce it
199 * as it may be re-set by the setup routines
200 * called after the rest of the clocks have been
201 * registered
202 */
203 s3c_set_clksrc(clksrc, false);
204
205 ret = s3c24xx_register_clock(&clksrc->clk);
206
207 if (ret < 0) {
208 printk(KERN_ERR "%s: failed to register %s (%d)\n",
209 __func__, clksrc->clk.name, ret);
210 }
211 }
212}
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
deleted file mode 100644
index d103ac1a52af..000000000000
--- a/arch/arm/plat-samsung/clock.c
+++ /dev/null
@@ -1,539 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/clock.c
2 *
3 * Copyright 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX Core clock control support
7 *
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
9 **
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27*/
28
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/list.h>
33#include <linux/errno.h>
34#include <linux/err.h>
35#include <linux/platform_device.h>
36#include <linux/device.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/clk.h>
40#include <linux/spinlock.h>
41#include <linux/io.h>
42#if defined(CONFIG_DEBUG_FS)
43#include <linux/debugfs.h>
44#endif
45
46#include <asm/irq.h>
47
48#include <plat/cpu-freq.h>
49
50#include <plat/clock.h>
51#include <plat/cpu.h>
52
53#include <linux/serial_core.h>
54#include <linux/serial_s3c.h> /* for s3c24xx_uart_devs */
55
56/* clock information */
57
58static LIST_HEAD(clocks);
59
60/* We originally used an mutex here, but some contexts (see resume)
61 * are calling functions such as clk_set_parent() with IRQs disabled
62 * causing an BUG to be triggered.
63 */
64DEFINE_SPINLOCK(clocks_lock);
65
66/* Global watchdog clock used by arch_wtd_reset() callback */
67struct clk *s3c2410_wdtclk;
68static int __init s3c_wdt_reset_init(void)
69{
70 s3c2410_wdtclk = clk_get(NULL, "watchdog");
71 if (IS_ERR(s3c2410_wdtclk))
72 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
73 return 0;
74}
75arch_initcall(s3c_wdt_reset_init);
76
77/* enable and disable calls for use with the clk struct */
78
79static int clk_null_enable(struct clk *clk, int enable)
80{
81 return 0;
82}
83
84int clk_enable(struct clk *clk)
85{
86 unsigned long flags;
87
88 if (IS_ERR(clk) || clk == NULL)
89 return -EINVAL;
90
91 clk_enable(clk->parent);
92
93 spin_lock_irqsave(&clocks_lock, flags);
94
95 if ((clk->usage++) == 0)
96 (clk->enable)(clk, 1);
97
98 spin_unlock_irqrestore(&clocks_lock, flags);
99 return 0;
100}
101
102void clk_disable(struct clk *clk)
103{
104 unsigned long flags;
105
106 if (IS_ERR(clk) || clk == NULL)
107 return;
108
109 spin_lock_irqsave(&clocks_lock, flags);
110
111 if ((--clk->usage) == 0)
112 (clk->enable)(clk, 0);
113
114 spin_unlock_irqrestore(&clocks_lock, flags);
115 clk_disable(clk->parent);
116}
117
118
119unsigned long clk_get_rate(struct clk *clk)
120{
121 if (IS_ERR_OR_NULL(clk))
122 return 0;
123
124 if (clk->rate != 0)
125 return clk->rate;
126
127 if (clk->ops != NULL && clk->ops->get_rate != NULL)
128 return (clk->ops->get_rate)(clk);
129
130 if (clk->parent != NULL)
131 return clk_get_rate(clk->parent);
132
133 return clk->rate;
134}
135
136long clk_round_rate(struct clk *clk, unsigned long rate)
137{
138 if (!IS_ERR_OR_NULL(clk) && clk->ops && clk->ops->round_rate)
139 return (clk->ops->round_rate)(clk, rate);
140
141 return rate;
142}
143
144int clk_set_rate(struct clk *clk, unsigned long rate)
145{
146 unsigned long flags;
147 int ret;
148
149 if (IS_ERR_OR_NULL(clk))
150 return -EINVAL;
151
152 /* We do not default just do a clk->rate = rate as
153 * the clock may have been made this way by choice.
154 */
155
156 WARN_ON(clk->ops == NULL);
157 WARN_ON(clk->ops && clk->ops->set_rate == NULL);
158
159 if (clk->ops == NULL || clk->ops->set_rate == NULL)
160 return -EINVAL;
161
162 spin_lock_irqsave(&clocks_lock, flags);
163 ret = (clk->ops->set_rate)(clk, rate);
164 spin_unlock_irqrestore(&clocks_lock, flags);
165
166 return ret;
167}
168
169struct clk *clk_get_parent(struct clk *clk)
170{
171 return clk->parent;
172}
173
174int clk_set_parent(struct clk *clk, struct clk *parent)
175{
176 unsigned long flags;
177 int ret = 0;
178
179 if (IS_ERR_OR_NULL(clk) || IS_ERR_OR_NULL(parent))
180 return -EINVAL;
181
182 spin_lock_irqsave(&clocks_lock, flags);
183
184 if (clk->ops && clk->ops->set_parent)
185 ret = (clk->ops->set_parent)(clk, parent);
186
187 spin_unlock_irqrestore(&clocks_lock, flags);
188
189 return ret;
190}
191
192EXPORT_SYMBOL(clk_enable);
193EXPORT_SYMBOL(clk_disable);
194EXPORT_SYMBOL(clk_get_rate);
195EXPORT_SYMBOL(clk_round_rate);
196EXPORT_SYMBOL(clk_set_rate);
197EXPORT_SYMBOL(clk_get_parent);
198EXPORT_SYMBOL(clk_set_parent);
199
200/* base clocks */
201
202int clk_default_setrate(struct clk *clk, unsigned long rate)
203{
204 clk->rate = rate;
205 return 0;
206}
207
208struct clk_ops clk_ops_def_setrate = {
209 .set_rate = clk_default_setrate,
210};
211
212struct clk clk_xtal = {
213 .name = "xtal",
214 .rate = 0,
215 .parent = NULL,
216 .ctrlbit = 0,
217};
218
219struct clk clk_ext = {
220 .name = "ext",
221};
222
223struct clk clk_epll = {
224 .name = "epll",
225};
226
227struct clk clk_mpll = {
228 .name = "mpll",
229 .ops = &clk_ops_def_setrate,
230};
231
232struct clk clk_upll = {
233 .name = "upll",
234 .parent = NULL,
235 .ctrlbit = 0,
236};
237
238struct clk clk_f = {
239 .name = "fclk",
240 .rate = 0,
241 .parent = &clk_mpll,
242 .ctrlbit = 0,
243};
244
245struct clk clk_h = {
246 .name = "hclk",
247 .rate = 0,
248 .parent = NULL,
249 .ctrlbit = 0,
250 .ops = &clk_ops_def_setrate,
251};
252
253struct clk clk_p = {
254 .name = "pclk",
255 .rate = 0,
256 .parent = NULL,
257 .ctrlbit = 0,
258 .ops = &clk_ops_def_setrate,
259};
260
261struct clk clk_usb_bus = {
262 .name = "usb-bus",
263 .rate = 0,
264 .parent = &clk_upll,
265};
266
267
268struct clk s3c24xx_uclk = {
269 .name = "uclk",
270};
271
272/* initialise the clock system */
273
274/**
275 * s3c24xx_register_clock() - register a clock
276 * @clk: The clock to register
277 *
278 * Add the specified clock to the list of clocks known by the system.
279 */
280int s3c24xx_register_clock(struct clk *clk)
281{
282 if (clk->enable == NULL)
283 clk->enable = clk_null_enable;
284
285 /* fill up the clk_lookup structure and register it*/
286 clk->lookup.dev_id = clk->devname;
287 clk->lookup.con_id = clk->name;
288 clk->lookup.clk = clk;
289 clkdev_add(&clk->lookup);
290
291 return 0;
292}
293
294/**
295 * s3c24xx_register_clocks() - register an array of clock pointers
296 * @clks: Pointer to an array of struct clk pointers
297 * @nr_clks: The number of clocks in the @clks array.
298 *
299 * Call s3c24xx_register_clock() for all the clock pointers contained
300 * in the @clks list. Returns the number of failures.
301 */
302int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
303{
304 int fails = 0;
305
306 for (; nr_clks > 0; nr_clks--, clks++) {
307 if (s3c24xx_register_clock(*clks) < 0) {
308 struct clk *clk = *clks;
309 printk(KERN_ERR "%s: failed to register %p: %s\n",
310 __func__, clk, clk->name);
311 fails++;
312 }
313 }
314
315 return fails;
316}
317
318/**
319 * s3c_register_clocks() - register an array of clocks
320 * @clkp: Pointer to the first clock in the array.
321 * @nr_clks: Number of clocks to register.
322 *
323 * Call s3c24xx_register_clock() on the @clkp array given, printing an
324 * error if it fails to register the clock (unlikely).
325 */
326void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
327{
328 int ret;
329
330 for (; nr_clks > 0; nr_clks--, clkp++) {
331 ret = s3c24xx_register_clock(clkp);
332
333 if (ret < 0) {
334 printk(KERN_ERR "Failed to register clock %s (%d)\n",
335 clkp->name, ret);
336 }
337 }
338}
339
340/**
341 * s3c_disable_clocks() - disable an array of clocks
342 * @clkp: Pointer to the first clock in the array.
343 * @nr_clks: Number of clocks to register.
344 *
345 * for internal use only at initialisation time. disable the clocks in the
346 * @clkp array.
347 */
348
349void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
350{
351 for (; nr_clks > 0; nr_clks--, clkp++)
352 (clkp->enable)(clkp, 0);
353}
354
355/* initialise all the clocks */
356
357int __init s3c24xx_register_baseclocks(unsigned long xtal)
358{
359 printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
360
361 clk_xtal.rate = xtal;
362
363 /* register our clocks */
364
365 if (s3c24xx_register_clock(&clk_xtal) < 0)
366 printk(KERN_ERR "failed to register master xtal\n");
367
368 if (s3c24xx_register_clock(&clk_mpll) < 0)
369 printk(KERN_ERR "failed to register mpll clock\n");
370
371 if (s3c24xx_register_clock(&clk_upll) < 0)
372 printk(KERN_ERR "failed to register upll clock\n");
373
374 if (s3c24xx_register_clock(&clk_f) < 0)
375 printk(KERN_ERR "failed to register cpu fclk\n");
376
377 if (s3c24xx_register_clock(&clk_h) < 0)
378 printk(KERN_ERR "failed to register cpu hclk\n");
379
380 if (s3c24xx_register_clock(&clk_p) < 0)
381 printk(KERN_ERR "failed to register cpu pclk\n");
382
383 return 0;
384}
385
386#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
387/* debugfs support to trace clock tree hierarchy and attributes */
388
389static struct dentry *clk_debugfs_root;
390
391static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
392{
393 struct clk *child;
394 const char *state;
395 char buf[255] = { 0 };
396 int n = 0;
397
398 if (c->name)
399 n = snprintf(buf, sizeof(buf) - 1, "%s", c->name);
400
401 if (c->devname)
402 n += snprintf(buf + n, sizeof(buf) - 1 - n, ":%s", c->devname);
403
404 state = (c->usage > 0) ? "on" : "off";
405
406 seq_printf(s, "%*s%-*s %-6s %-3d %-10lu\n",
407 level * 3 + 1, "",
408 50 - level * 3, buf,
409 state, c->usage, clk_get_rate(c));
410
411 list_for_each_entry(child, &clocks, list) {
412 if (child->parent != c)
413 continue;
414
415 clock_tree_show_one(s, child, level + 1);
416 }
417}
418
419static int clock_tree_show(struct seq_file *s, void *data)
420{
421 struct clk *c;
422 unsigned long flags;
423
424 seq_printf(s, " clock state ref rate\n");
425 seq_printf(s, "----------------------------------------------------\n");
426
427 spin_lock_irqsave(&clocks_lock, flags);
428
429 list_for_each_entry(c, &clocks, list)
430 if (c->parent == NULL)
431 clock_tree_show_one(s, c, 0);
432
433 spin_unlock_irqrestore(&clocks_lock, flags);
434 return 0;
435}
436
437static int clock_tree_open(struct inode *inode, struct file *file)
438{
439 return single_open(file, clock_tree_show, inode->i_private);
440}
441
442static const struct file_operations clock_tree_fops = {
443 .open = clock_tree_open,
444 .read = seq_read,
445 .llseek = seq_lseek,
446 .release = single_release,
447};
448
449static int clock_rate_show(void *data, u64 *val)
450{
451 struct clk *c = data;
452 *val = clk_get_rate(c);
453 return 0;
454}
455DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_rate_show, NULL, "%llu\n");
456
457static int clk_debugfs_register_one(struct clk *c)
458{
459 int err;
460 struct dentry *d;
461 struct clk *pa = c->parent;
462 char s[255];
463 char *p = s;
464
465 p += sprintf(p, "%s", c->devname);
466
467 d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
468 if (!d)
469 return -ENOMEM;
470
471 c->dent = d;
472
473 d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage);
474 if (!d) {
475 err = -ENOMEM;
476 goto err_out;
477 }
478
479 d = debugfs_create_file("rate", S_IRUGO, c->dent, c, &clock_rate_fops);
480 if (!d) {
481 err = -ENOMEM;
482 goto err_out;
483 }
484 return 0;
485
486err_out:
487 debugfs_remove_recursive(c->dent);
488 return err;
489}
490
491static int clk_debugfs_register(struct clk *c)
492{
493 int err;
494 struct clk *pa = c->parent;
495
496 if (pa && !pa->dent) {
497 err = clk_debugfs_register(pa);
498 if (err)
499 return err;
500 }
501
502 if (!c->dent) {
503 err = clk_debugfs_register_one(c);
504 if (err)
505 return err;
506 }
507 return 0;
508}
509
510static int __init clk_debugfs_init(void)
511{
512 struct clk *c;
513 struct dentry *d;
514 int err = -ENOMEM;
515
516 d = debugfs_create_dir("clock", NULL);
517 if (!d)
518 return -ENOMEM;
519 clk_debugfs_root = d;
520
521 d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
522 &clock_tree_fops);
523 if (!d)
524 goto err_out;
525
526 list_for_each_entry(c, &clocks, list) {
527 err = clk_debugfs_register(c);
528 if (err)
529 goto err_out;
530 }
531 return 0;
532
533err_out:
534 debugfs_remove_recursive(clk_debugfs_root);
535 return err;
536}
537late_initcall(clk_debugfs_init);
538
539#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c
index 364963a0a344..360618ee39e5 100644
--- a/arch/arm/plat-samsung/cpu.c
+++ b/arch/arm/plat-samsung/cpu.c
@@ -15,8 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/io.h> 16#include <linux/io.h>
17 17
18 18#include <plat/map-base.h>
19#include <mach/map.h>
20#include <plat/cpu.h> 19#include <plat/cpu.h>
21 20
22unsigned long samsung_cpu_id; 21unsigned long samsung_cpu_id;
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index ead4f1c94058..83c7d154bde0 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -53,7 +53,6 @@
53#include <linux/platform_data/ata-samsung_cf.h> 53#include <linux/platform_data/ata-samsung_cf.h>
54#include <plat/fb.h> 54#include <plat/fb.h>
55#include <plat/fb-s3c2410.h> 55#include <plat/fb-s3c2410.h>
56#include <plat/hdmi.h>
57#include <linux/platform_data/hwmon-s3c.h> 56#include <linux/platform_data/hwmon-s3c.h>
58#include <linux/platform_data/i2c-s3c2410.h> 57#include <linux/platform_data/i2c-s3c2410.h>
59#include <plat/keypad.h> 58#include <plat/keypad.h>
@@ -145,23 +144,6 @@ struct platform_device s3c_device_camif = {
145}; 144};
146#endif /* CONFIG_CPU_S3C2440 */ 145#endif /* CONFIG_CPU_S3C2440 */
147 146
148/* ASOC DMA */
149
150#ifdef CONFIG_PLAT_S5P
151static struct resource samsung_asoc_idma_resource = DEFINE_RES_IRQ(IRQ_I2S0);
152
153struct platform_device samsung_asoc_idma = {
154 .name = "samsung-idma",
155 .id = -1,
156 .num_resources = 1,
157 .resource = &samsung_asoc_idma_resource,
158 .dev = {
159 .dma_mask = &samsung_device_dma_mask,
160 .coherent_dma_mask = DMA_BIT_MASK(32),
161 }
162};
163#endif
164
165/* FB */ 147/* FB */
166 148
167#ifdef CONFIG_S3C_DEV_FB 149#ifdef CONFIG_S3C_DEV_FB
@@ -190,151 +172,6 @@ void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
190} 172}
191#endif /* CONFIG_S3C_DEV_FB */ 173#endif /* CONFIG_S3C_DEV_FB */
192 174
193/* FIMC */
194
195#ifdef CONFIG_S5P_DEV_FIMC0
196static struct resource s5p_fimc0_resource[] = {
197 [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
198 [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
199};
200
201struct platform_device s5p_device_fimc0 = {
202 .name = "s5p-fimc",
203 .id = 0,
204 .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
205 .resource = s5p_fimc0_resource,
206 .dev = {
207 .dma_mask = &samsung_device_dma_mask,
208 .coherent_dma_mask = DMA_BIT_MASK(32),
209 },
210};
211
212struct platform_device s5p_device_fimc_md = {
213 .name = "s5p-fimc-md",
214 .id = -1,
215};
216#endif /* CONFIG_S5P_DEV_FIMC0 */
217
218#ifdef CONFIG_S5P_DEV_FIMC1
219static struct resource s5p_fimc1_resource[] = {
220 [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
221 [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
222};
223
224struct platform_device s5p_device_fimc1 = {
225 .name = "s5p-fimc",
226 .id = 1,
227 .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
228 .resource = s5p_fimc1_resource,
229 .dev = {
230 .dma_mask = &samsung_device_dma_mask,
231 .coherent_dma_mask = DMA_BIT_MASK(32),
232 },
233};
234#endif /* CONFIG_S5P_DEV_FIMC1 */
235
236#ifdef CONFIG_S5P_DEV_FIMC2
237static struct resource s5p_fimc2_resource[] = {
238 [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
239 [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
240};
241
242struct platform_device s5p_device_fimc2 = {
243 .name = "s5p-fimc",
244 .id = 2,
245 .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
246 .resource = s5p_fimc2_resource,
247 .dev = {
248 .dma_mask = &samsung_device_dma_mask,
249 .coherent_dma_mask = DMA_BIT_MASK(32),
250 },
251};
252#endif /* CONFIG_S5P_DEV_FIMC2 */
253
254#ifdef CONFIG_S5P_DEV_FIMC3
255static struct resource s5p_fimc3_resource[] = {
256 [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
257 [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
258};
259
260struct platform_device s5p_device_fimc3 = {
261 .name = "s5p-fimc",
262 .id = 3,
263 .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
264 .resource = s5p_fimc3_resource,
265 .dev = {
266 .dma_mask = &samsung_device_dma_mask,
267 .coherent_dma_mask = DMA_BIT_MASK(32),
268 },
269};
270#endif /* CONFIG_S5P_DEV_FIMC3 */
271
272/* G2D */
273
274#ifdef CONFIG_S5P_DEV_G2D
275static struct resource s5p_g2d_resource[] = {
276 [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
277 [1] = DEFINE_RES_IRQ(IRQ_2D),
278};
279
280struct platform_device s5p_device_g2d = {
281 .name = "s5p-g2d",
282 .id = 0,
283 .num_resources = ARRAY_SIZE(s5p_g2d_resource),
284 .resource = s5p_g2d_resource,
285 .dev = {
286 .dma_mask = &samsung_device_dma_mask,
287 .coherent_dma_mask = DMA_BIT_MASK(32),
288 },
289};
290#endif /* CONFIG_S5P_DEV_G2D */
291
292#ifdef CONFIG_S5P_DEV_JPEG
293static struct resource s5p_jpeg_resource[] = {
294 [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
295 [1] = DEFINE_RES_IRQ(IRQ_JPEG),
296};
297
298struct platform_device s5p_device_jpeg = {
299 .name = "s5p-jpeg",
300 .id = 0,
301 .num_resources = ARRAY_SIZE(s5p_jpeg_resource),
302 .resource = s5p_jpeg_resource,
303 .dev = {
304 .dma_mask = &samsung_device_dma_mask,
305 .coherent_dma_mask = DMA_BIT_MASK(32),
306 },
307};
308#endif /* CONFIG_S5P_DEV_JPEG */
309
310/* FIMD0 */
311
312#ifdef CONFIG_S5P_DEV_FIMD0
313static struct resource s5p_fimd0_resource[] = {
314 [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
315 [1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"),
316 [2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"),
317 [3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"),
318};
319
320struct platform_device s5p_device_fimd0 = {
321 .name = "s5p-fb",
322 .id = 0,
323 .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
324 .resource = s5p_fimd0_resource,
325 .dev = {
326 .dma_mask = &samsung_device_dma_mask,
327 .coherent_dma_mask = DMA_BIT_MASK(32),
328 },
329};
330
331void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
332{
333 s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
334 &s5p_device_fimd0);
335}
336#endif /* CONFIG_S5P_DEV_FIMD0 */
337
338/* HWMON */ 175/* HWMON */
339 176
340#ifdef CONFIG_S3C_DEV_HWMON 177#ifdef CONFIG_S3C_DEV_HWMON
@@ -722,60 +559,6 @@ void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
722} 559}
723#endif /* CONFIG_S3C_DEV_I2C7 */ 560#endif /* CONFIG_S3C_DEV_I2C7 */
724 561
725/* I2C HDMIPHY */
726
727#ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
728static struct resource s5p_i2c_resource[] = {
729 [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
730 [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
731};
732
733struct platform_device s5p_device_i2c_hdmiphy = {
734 .name = "s3c2440-hdmiphy-i2c",
735 .id = -1,
736 .num_resources = ARRAY_SIZE(s5p_i2c_resource),
737 .resource = s5p_i2c_resource,
738};
739
740void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
741{
742 struct s3c2410_platform_i2c *npd;
743
744 if (!pd) {
745 pd = &default_i2c_data;
746
747 if (soc_is_s5pv210())
748 pd->bus_num = 3;
749 else
750 pd->bus_num = 0;
751 }
752
753 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
754 &s5p_device_i2c_hdmiphy);
755}
756
757static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
758
759void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
760 struct i2c_board_info *mhl_info, int mhl_bus)
761{
762 struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
763
764 if (soc_is_s5pv210())
765 pd->hdmiphy_bus = 3;
766 else
767 pd->hdmiphy_bus = 0;
768
769 pd->hdmiphy_info = hdmiphy_info;
770 pd->mhl_info = mhl_info;
771 pd->mhl_bus = mhl_bus;
772
773 s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
774 &s5p_device_hdmi);
775}
776
777#endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
778
779/* I2S */ 562/* I2S */
780 563
781#ifdef CONFIG_PLAT_S3C24XX 564#ifdef CONFIG_PLAT_S3C24XX
@@ -879,36 +662,6 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
879} 662}
880#endif /* CONFIG_PLAT_S3C24XX */ 663#endif /* CONFIG_PLAT_S3C24XX */
881 664
882/* MIPI CSIS */
883
884#ifdef CONFIG_S5P_DEV_CSIS0
885static struct resource s5p_mipi_csis0_resource[] = {
886 [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
887 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
888};
889
890struct platform_device s5p_device_mipi_csis0 = {
891 .name = "s5p-mipi-csis",
892 .id = 0,
893 .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
894 .resource = s5p_mipi_csis0_resource,
895};
896#endif /* CONFIG_S5P_DEV_CSIS0 */
897
898#ifdef CONFIG_S5P_DEV_CSIS1
899static struct resource s5p_mipi_csis1_resource[] = {
900 [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
901 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
902};
903
904struct platform_device s5p_device_mipi_csis1 = {
905 .name = "s5p-mipi-csis",
906 .id = 1,
907 .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
908 .resource = s5p_mipi_csis1_resource,
909};
910#endif
911
912/* NAND */ 665/* NAND */
913 666
914#ifdef CONFIG_S3C_DEV_NAND 667#ifdef CONFIG_S3C_DEV_NAND
@@ -1052,43 +805,6 @@ void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
1052} 805}
1053#endif /* CONFIG_S3C64XX_DEV_ONENAND1 */ 806#endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
1054 807
1055#ifdef CONFIG_S5P_DEV_ONENAND
1056static struct resource s5p_onenand_resources[] = {
1057 [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
1058 [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
1059 [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
1060};
1061
1062struct platform_device s5p_device_onenand = {
1063 .name = "s5pc110-onenand",
1064 .id = -1,
1065 .num_resources = ARRAY_SIZE(s5p_onenand_resources),
1066 .resource = s5p_onenand_resources,
1067};
1068#endif /* CONFIG_S5P_DEV_ONENAND */
1069
1070/* PMU */
1071
1072#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
1073static struct resource s5p_pmu_resource[] = {
1074 DEFINE_RES_IRQ(IRQ_PMU)
1075};
1076
1077static struct platform_device s5p_device_pmu = {
1078 .name = "arm-pmu",
1079 .id = -1,
1080 .num_resources = ARRAY_SIZE(s5p_pmu_resource),
1081 .resource = s5p_pmu_resource,
1082};
1083
1084static int __init s5p_pmu_init(void)
1085{
1086 platform_device_register(&s5p_device_pmu);
1087 return 0;
1088}
1089arch_initcall(s5p_pmu_init);
1090#endif /* CONFIG_PLAT_S5P */
1091
1092/* PWM Timer */ 808/* PWM Timer */
1093 809
1094#ifdef CONFIG_SAMSUNG_DEV_PWM 810#ifdef CONFIG_SAMSUNG_DEV_PWM
@@ -1251,52 +967,6 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
1251} 967}
1252#endif /* CONFIG_SAMSUNG_DEV_TS */ 968#endif /* CONFIG_SAMSUNG_DEV_TS */
1253 969
1254/* TV */
1255
1256#ifdef CONFIG_S5P_DEV_TV
1257
1258static struct resource s5p_hdmi_resources[] = {
1259 [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
1260 [1] = DEFINE_RES_IRQ(IRQ_HDMI),
1261};
1262
1263struct platform_device s5p_device_hdmi = {
1264 .name = "s5p-hdmi",
1265 .id = -1,
1266 .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
1267 .resource = s5p_hdmi_resources,
1268};
1269
1270static struct resource s5p_sdo_resources[] = {
1271 [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
1272 [1] = DEFINE_RES_IRQ(IRQ_SDO),
1273};
1274
1275struct platform_device s5p_device_sdo = {
1276 .name = "s5p-sdo",
1277 .id = -1,
1278 .num_resources = ARRAY_SIZE(s5p_sdo_resources),
1279 .resource = s5p_sdo_resources,
1280};
1281
1282static struct resource s5p_mixer_resources[] = {
1283 [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
1284 [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
1285 [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
1286};
1287
1288struct platform_device s5p_device_mixer = {
1289 .name = "s5p-mixer",
1290 .id = -1,
1291 .num_resources = ARRAY_SIZE(s5p_mixer_resources),
1292 .resource = s5p_mixer_resources,
1293 .dev = {
1294 .dma_mask = &samsung_device_dma_mask,
1295 .coherent_dma_mask = DMA_BIT_MASK(32),
1296 }
1297};
1298#endif /* CONFIG_S5P_DEV_TV */
1299
1300/* USB */ 970/* USB */
1301 971
1302#ifdef CONFIG_S3C_DEV_USB_HOST 972#ifdef CONFIG_S3C_DEV_USB_HOST
diff --git a/arch/arm/plat-samsung/include/plat/camport.h b/arch/arm/plat-samsung/include/plat/camport.h
deleted file mode 100644
index a5708bf84b3a..000000000000
--- a/arch/arm/plat-samsung/include/plat/camport.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
3 *
4 * S5P series camera interface helper functions
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __PLAT_SAMSUNG_CAMPORT_H_
12#define __PLAT_SAMSUNG_CAMPORT_H_ __FILE__
13
14enum s5p_camport_id {
15 S5P_CAMPORT_A,
16 S5P_CAMPORT_B,
17};
18
19/*
20 * The helper functions to configure GPIO for the camera parallel bus.
21 * The camera port can be multiplexed with any FIMC entity, even multiple
22 * FIMC entities are allowed to be attached to a single port simultaneously.
23 * These functions are to be used in the board setup code.
24 */
25int s5pv210_fimc_setup_gpio(enum s5p_camport_id id);
26int exynos4_fimc_setup_gpio(enum s5p_camport_id id);
27
28#endif /* __PLAT_SAMSUNG_CAMPORT_H */
diff --git a/arch/arm/plat-samsung/include/plat/clock-clksrc.h b/arch/arm/plat-samsung/include/plat/clock-clksrc.h
deleted file mode 100644
index 50a8ca7c3760..000000000000
--- a/arch/arm/plat-samsung/include/plat/clock-clksrc.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/clock-clksrc.h
2 *
3 * Parts taken from arch/arm/plat-s3c64xx/clock.c
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * Copyright 2009 Ben Dooks <ben-linux@fluff.org>
10 * Copyright 2009 Harald Welte
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17/**
18 * struct clksrc_sources - list of sources for a given clock
19 * @sources: array of pointers to clocks
20 * @nr_sources: The size of @sources
21 */
22struct clksrc_sources {
23 unsigned int nr_sources;
24 struct clk **sources;
25};
26
27/**
28 * struct clksrc_reg - register definition for clock control bits
29 * @reg: pointer to the register in virtual memory.
30 * @shift: the shift in bits to where the bitfield is.
31 * @size: the size in bits of the bitfield.
32 *
33 * This specifies the size and position of the bits we are interested
34 * in within the register specified by @reg.
35 */
36struct clksrc_reg {
37 void __iomem *reg;
38 unsigned short shift;
39 unsigned short size;
40};
41
42/**
43 * struct clksrc_clk - class of clock for newer style samsung devices.
44 * @clk: the standard clock representation
45 * @sources: the sources for this clock
46 * @reg_src: the register definition for selecting the clock's source
47 * @reg_div: the register definition for the clock's output divisor
48 *
49 * This clock implements the features required by the newer SoCs where
50 * the standard clock block provides an input mux and a post-mux divisor
51 * to provide the periperhal's clock.
52 *
53 * The array of @sources provides the mapping of mux position to the
54 * clock, and @reg_src shows the code where to modify to change the mux
55 * position. The @reg_div defines how to change the divider settings on
56 * the output.
57 */
58struct clksrc_clk {
59 struct clk clk;
60 struct clksrc_sources *sources;
61
62 struct clksrc_reg reg_src;
63 struct clksrc_reg reg_div;
64};
65
66/**
67 * s3c_set_clksrc() - setup the clock from the register settings
68 * @clk: The clock to setup.
69 * @announce: true to announce the setting to printk().
70 *
71 * Setup the clock from the current register settings, for when the
72 * kernel boots or if it is resuming from a possibly unknown state.
73 */
74extern void s3c_set_clksrc(struct clksrc_clk *clk, bool announce);
75
76/**
77 * s3c_register_clksrc() register clocks from an array of clksrc clocks
78 * @srcs: The array of clocks to register
79 * @size: The size of the @srcs array.
80 *
81 * Initialise and register the array of clocks described by @srcs.
82 */
83extern void s3c_register_clksrc(struct clksrc_clk *srcs, int size);
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
deleted file mode 100644
index 63239f409807..000000000000
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ /dev/null
@@ -1,152 +0,0 @@
1/* linux/arch/arm/plat-s3c/include/plat/clock.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Written by Ben Dooks, <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_PLAT_CLOCK_H
13#define __ASM_PLAT_CLOCK_H __FILE__
14
15#include <linux/spinlock.h>
16#include <linux/clkdev.h>
17
18struct clk;
19
20/**
21 * struct clk_ops - standard clock operations
22 * @set_rate: set the clock rate, see clk_set_rate().
23 * @get_rate: get the clock rate, see clk_get_rate().
24 * @round_rate: round a given clock rate, see clk_round_rate().
25 * @set_parent: set the clock's parent, see clk_set_parent().
26 *
27 * Group the common clock implementations together so that we
28 * don't have to keep setting the same fields again. We leave
29 * enable in struct clk.
30 *
31 * Adding an extra layer of indirection into the process should
32 * not be a problem as it is unlikely these operations are going
33 * to need to be called quickly.
34 */
35struct clk_ops {
36 int (*set_rate)(struct clk *c, unsigned long rate);
37 unsigned long (*get_rate)(struct clk *c);
38 unsigned long (*round_rate)(struct clk *c, unsigned long rate);
39 int (*set_parent)(struct clk *c, struct clk *parent);
40};
41
42struct clk {
43 struct list_head list;
44 struct module *owner;
45 struct clk *parent;
46 const char *name;
47 const char *devname;
48 int id;
49 int usage;
50 unsigned long rate;
51 unsigned long ctrlbit;
52
53 struct clk_ops *ops;
54 int (*enable)(struct clk *, int enable);
55 struct clk_lookup lookup;
56#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
57 struct dentry *dent; /* For visible tree hierarchy */
58#endif
59};
60
61/* other clocks which may be registered by board support */
62
63extern struct clk s3c24xx_dclk0;
64extern struct clk s3c24xx_dclk1;
65extern struct clk s3c24xx_clkout0;
66extern struct clk s3c24xx_clkout1;
67extern struct clk s3c24xx_uclk;
68
69extern struct clk clk_usb_bus;
70
71/* core clock support */
72
73extern struct clk clk_f;
74extern struct clk clk_h;
75extern struct clk clk_p;
76extern struct clk clk_mpll;
77extern struct clk clk_upll;
78extern struct clk clk_epll;
79extern struct clk clk_xtal;
80extern struct clk clk_ext;
81
82/* S3C2443/S3C2416 specific clocks */
83extern struct clksrc_clk clk_epllref;
84extern struct clksrc_clk clk_esysclk;
85
86/* S3C24XX UART clocks */
87extern struct clk s3c24xx_clk_uart0;
88extern struct clk s3c24xx_clk_uart1;
89extern struct clk s3c24xx_clk_uart2;
90
91/* S3C64XX specific clocks */
92extern struct clk clk_h2;
93extern struct clk clk_27m;
94extern struct clk clk_48m;
95extern struct clk clk_xusbxti;
96
97extern int clk_default_setrate(struct clk *clk, unsigned long rate);
98extern struct clk_ops clk_ops_def_setrate;
99
100/* exports for arch/arm/mach-s3c2410
101 *
102 * Please DO NOT use these outside of arch/arm/mach-s3c2410
103*/
104
105extern spinlock_t clocks_lock;
106
107extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
108
109extern int s3c24xx_register_clock(struct clk *clk);
110extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
111
112extern void s3c_register_clocks(struct clk *clk, int nr_clks);
113extern void s3c_disable_clocks(struct clk *clkp, int nr_clks);
114
115extern int s3c24xx_register_baseclocks(unsigned long xtal);
116
117extern void s5p_register_clocks(unsigned long xtal_freq);
118
119extern void s3c24xx_setup_clocks(unsigned long fclk,
120 unsigned long hclk,
121 unsigned long pclk);
122
123extern void s3c2410_setup_clocks(void);
124extern void s3c2412_setup_clocks(void);
125extern void s3c244x_setup_clocks(void);
126
127/* S3C2410 specific clock functions */
128
129extern int s3c2410_baseclk_add(void);
130
131/* S3C2443/S3C2416 specific clock functions */
132
133typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
134
135extern void s3c2443_common_setup_clocks(pll_fn get_mpll);
136extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
137 unsigned int *divs, int nr_divs,
138 int divmask);
139
140extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
141extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
142extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
143
144/* S3C64XX specific functions and clocks */
145
146extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
147
148/* Global watchdog clock used by arch_wtd_reset() callback */
149
150extern struct clk *s3c2410_wdtclk;
151
152#endif /* __ASM_PLAT_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index 72d4178ad23b..317c52303288 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -140,7 +140,6 @@ struct s3c_cpufreq_config {
140 * any frequency changes. This is really only need by devices like the 140 * any frequency changes. This is really only need by devices like the
141 * S3C2410 where there is no or limited divider between the PLL and the 141 * S3C2410 where there is no or limited divider between the PLL and the
142 * ARMCLK. 142 * ARMCLK.
143 * @resume_clocks: Update the clocks on resume.
144 * @get_iotiming: Get the current IO timing data, mainly for use at start. 143 * @get_iotiming: Get the current IO timing data, mainly for use at start.
145 * @set_iotiming: Update the IO timings from the cached copies calculated 144 * @set_iotiming: Update the IO timings from the cached copies calculated
146 * from the @calc_iotiming entry when changing the frequency. 145 * from the @calc_iotiming entry when changing the frequency.
@@ -169,8 +168,6 @@ struct s3c_cpufreq_info {
169 168
170 /* driver routines */ 169 /* driver routines */
171 170
172 void (*resume_clocks)(void);
173
174 int (*get_iotiming)(struct s3c_cpufreq_config *cfg, 171 int (*get_iotiming)(struct s3c_cpufreq_config *cfg,
175 struct s3c_iotimings *timings); 172 struct s3c_iotimings *timings);
176 173
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index d1d4659025bb..61d14f3a0426 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -47,7 +47,6 @@ IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
47IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK) 47IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
48IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK) 48IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
49IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK) 49IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
50IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
51 50
52#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ 51#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
53 defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \ 52 defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -76,12 +75,6 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
76# define soc_is_s3c64xx() 0 75# define soc_is_s3c64xx() 0
77#endif 76#endif
78 77
79#if defined(CONFIG_CPU_S5PV210)
80# define soc_is_s5pv210() is_samsung_s5pv210()
81#else
82# define soc_is_s5pv210() 0
83#endif
84
85#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } 78#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
86 79
87#ifndef KHZ 80#ifndef KHZ
@@ -117,12 +110,9 @@ extern void s3c_init_cpu(unsigned long idcode,
117 110
118/* core initialisation functions */ 111/* core initialisation functions */
119 112
120extern void s5p_init_irq(u32 *vic, u32 num_vic);
121
122extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); 113extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
123 114
124extern void s3c64xx_init_cpu(void); 115extern void s3c64xx_init_cpu(void);
125extern void s5p_init_cpu(void __iomem *cpuid_addr);
126 116
127extern unsigned int samsung_rev(void); 117extern unsigned int samsung_rev(void);
128 118
@@ -149,8 +139,5 @@ extern struct bus_type s3c2440_subsys;
149extern struct bus_type s3c2442_subsys; 139extern struct bus_type s3c2442_subsys;
150extern struct bus_type s3c2443_subsys; 140extern struct bus_type s3c2443_subsys;
151extern struct bus_type s3c6410_subsys; 141extern struct bus_type s3c6410_subsys;
152extern struct bus_type s5pv210_subsys;
153
154extern void (*s5pc1xx_idle)(void);
155 142
156#endif 143#endif
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 5f5a28d08c2e..e23fed311e5f 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -25,9 +25,6 @@ struct s3c24xx_uart_resources {
25 25
26extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; 26extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
27extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; 27extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
28extern struct s3c24xx_uart_resources s5p_uart_resources[];
29extern struct s3c24xx_uart_resources exynos4_uart_resources[];
30extern struct s3c24xx_uart_resources exynos5_uart_resources[];
31 28
32extern struct platform_device *s3c24xx_uart_devs[]; 29extern struct platform_device *s3c24xx_uart_devs[];
33extern struct platform_device *s3c24xx_uart_src[]; 30extern struct platform_device *s3c24xx_uart_src[];
@@ -75,45 +72,6 @@ extern struct platform_device s3c_device_usb_hsotg;
75extern struct platform_device s3c_device_usb_hsudc; 72extern struct platform_device s3c_device_usb_hsudc;
76extern struct platform_device s3c_device_wdt; 73extern struct platform_device s3c_device_wdt;
77 74
78extern struct platform_device s5p_device_fimc0;
79extern struct platform_device s5p_device_fimc1;
80extern struct platform_device s5p_device_fimc2;
81extern struct platform_device s5p_device_fimc3;
82extern struct platform_device s5p_device_fimc_md;
83extern struct platform_device s5p_device_jpeg;
84extern struct platform_device s5p_device_g2d;
85extern struct platform_device s5p_device_fimd0;
86extern struct platform_device s5p_device_hdmi;
87extern struct platform_device s5p_device_i2c_hdmiphy;
88extern struct platform_device s5p_device_mfc;
89extern struct platform_device s5p_device_mfc_l;
90extern struct platform_device s5p_device_mfc_r;
91extern struct platform_device s5p_device_mipi_csis0;
92extern struct platform_device s5p_device_mipi_csis1;
93extern struct platform_device s5p_device_mixer;
94extern struct platform_device s5p_device_onenand;
95extern struct platform_device s5p_device_sdo;
96
97extern struct platform_device s5pv210_device_ac97;
98extern struct platform_device s5pv210_device_iis0;
99extern struct platform_device s5pv210_device_iis1;
100extern struct platform_device s5pv210_device_iis2;
101extern struct platform_device s5pv210_device_pcm0;
102extern struct platform_device s5pv210_device_pcm1;
103extern struct platform_device s5pv210_device_pcm2;
104extern struct platform_device s5pv210_device_spdif;
105
106extern struct platform_device exynos4_device_ac97;
107extern struct platform_device exynos4_device_ahci;
108extern struct platform_device exynos4_device_i2s0;
109extern struct platform_device exynos4_device_i2s1;
110extern struct platform_device exynos4_device_i2s2;
111extern struct platform_device exynos4_device_ohci;
112extern struct platform_device exynos4_device_pcm0;
113extern struct platform_device exynos4_device_pcm1;
114extern struct platform_device exynos4_device_pcm2;
115extern struct platform_device exynos4_device_spdif;
116
117extern struct platform_device samsung_asoc_idma; 75extern struct platform_device samsung_asoc_idma;
118extern struct platform_device samsung_device_keypad; 76extern struct platform_device samsung_device_keypad;
119extern struct platform_device samsung_device_pwm; 77extern struct platform_device samsung_device_pwm;
diff --git a/arch/arm/plat-samsung/include/plat/fb-core.h b/arch/arm/plat-samsung/include/plat/fb-core.h
index 6abcbf139cee..bca383efcf6d 100644
--- a/arch/arm/plat-samsung/include/plat/fb-core.h
+++ b/arch/arm/plat-samsung/include/plat/fb-core.h
@@ -26,19 +26,4 @@ static inline void s3c_fb_setname(char *name)
26#endif 26#endif
27} 27}
28 28
29/* Re-define device name depending on support. */
30static inline void s5p_fb_setname(int id, char *name)
31{
32 switch (id) {
33#ifdef CONFIG_S5P_DEV_FIMD0
34 case 0:
35 s5p_device_fimd0.name = name;
36 break;
37#endif
38 default:
39 printk(KERN_ERR "%s: invalid device id(%d)\n", __func__, id);
40 break;
41 }
42}
43
44#endif /* __ASM_PLAT_FB_CORE_H */ 29#endif /* __ASM_PLAT_FB_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 5a0e26afb961..b89f8f208515 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -26,32 +26,10 @@
26extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); 26extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
27 27
28/** 28/**
29 * s5p_fimd0_set_platdata() - Setup the FB device with platform data.
30 * @pd: The platform data to set. The data is copied from the passed structure
31 * so the machine data can mark the data __initdata so that any unused
32 * machines will end up dumping their data at runtime.
33 */
34extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
35
36/**
37 * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD 29 * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
38 * 30 *
39 * Initialise the GPIO for an 24bpp LCD display on the RGB interface. 31 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
40 */ 32 */
41extern void s3c64xx_fb_gpio_setup_24bpp(void); 33extern void s3c64xx_fb_gpio_setup_24bpp(void);
42 34
43/**
44 * s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD
45 *
46 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
47 */
48extern void s5pv210_fb_gpio_setup_24bpp(void);
49
50/**
51 * exynos4_fimd0_gpio_setup_24bpp() - Exynos4 setup function for 24bpp LCD0
52 *
53 * Initialise the GPIO for an 24bpp LCD display on the RGB interface 0.
54 */
55extern void exynos4_fimd0_gpio_setup_24bpp(void);
56
57#endif /* __PLAT_S3C_FB_H */ 35#endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/fimc-core.h b/arch/arm/plat-samsung/include/plat/fimc-core.h
deleted file mode 100644
index 1d6cb2b8b094..000000000000
--- a/arch/arm/plat-samsung/include/plat/fimc-core.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * arch/arm/plat-samsung/include/plat/fimc-core.h
3 *
4 * Copyright 2010 Samsung Electronics Co., Ltd.
5 * Sylwester Nawrocki <s.nawrocki@samsung.com>
6 *
7 * Samsung camera interface driver core functions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_PLAT_FIMC_CORE_H
15#define __ASM_PLAT_FIMC_CORE_H __FILE__
16
17/*
18 * These functions are only for use with the core support code, such as
19 * the CPU-specific initialization code.
20 */
21
22/* Re-define device name to differentiate the subsystem in various SoCs. */
23static inline void s3c_fimc_setname(int id, char *name)
24{
25 switch (id) {
26#ifdef CONFIG_S5P_DEV_FIMC0
27 case 0:
28 s5p_device_fimc0.name = name;
29 break;
30#endif
31#ifdef CONFIG_S5P_DEV_FIMC1
32 case 1:
33 s5p_device_fimc1.name = name;
34 break;
35#endif
36#ifdef CONFIG_S5P_DEV_FIMC2
37 case 2:
38 s5p_device_fimc2.name = name;
39 break;
40#endif
41#ifdef CONFIG_S5P_DEV_FIMC3
42 case 3:
43 s5p_device_fimc3.name = name;
44 break;
45#endif
46 default:
47 break;
48 }
49}
50
51#endif /* __ASM_PLAT_FIMC_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index 08740eed050c..b5294eff18b5 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -27,7 +27,6 @@
27#include <linux/types.h> 27#include <linux/types.h>
28 28
29typedef unsigned int __bitwise__ samsung_gpio_pull_t; 29typedef unsigned int __bitwise__ samsung_gpio_pull_t;
30typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
31 30
32/* forward declaration if gpio-core.h hasn't been included */ 31/* forward declaration if gpio-core.h hasn't been included */
33struct samsung_gpio_chip; 32struct samsung_gpio_chip;
@@ -180,67 +179,4 @@ static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size,
180 return s3c_gpio_cfgall_range(pin, size, cfg, S3C_GPIO_PULL_NONE); 179 return s3c_gpio_cfgall_range(pin, size, cfg, S3C_GPIO_PULL_NONE);
181} 180}
182 181
183/* Define values for the drvstr available for each gpio pin.
184 *
185 * These values control the value of the output signal driver strength,
186 * configurable on most pins on the S5P series.
187 */
188#define S5P_GPIO_DRVSTR_LV1 ((__force s5p_gpio_drvstr_t)0x0)
189#define S5P_GPIO_DRVSTR_LV2 ((__force s5p_gpio_drvstr_t)0x2)
190#define S5P_GPIO_DRVSTR_LV3 ((__force s5p_gpio_drvstr_t)0x1)
191#define S5P_GPIO_DRVSTR_LV4 ((__force s5p_gpio_drvstr_t)0x3)
192
193/**
194 * s5c_gpio_get_drvstr() - get the driver streght value of a gpio pin
195 * @pin: The pin number to get the settings for
196 *
197 * Read the driver streght value for the specified pin.
198*/
199extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin);
200
201/**
202 * s3c_gpio_set_drvstr() - set the driver streght value of a gpio pin
203 * @pin: The pin number to configure the driver streght value
204 * @drvstr: The new value of the driver strength
205 *
206 * This function sets the driver strength value for the specified pin.
207 * It will return 0 if successful, or a negative error code if the pin
208 * cannot support the requested setting.
209*/
210extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr);
211
212/**
213 * s5p_register_gpio_interrupt() - register interrupt support for a gpio group
214 * @pin: The pin number from the group to be registered
215 *
216 * This function registers gpio interrupt support for the group that the
217 * specified pin belongs to.
218 *
219 * The total number of gpio pins is quite large ob s5p series. Registering
220 * irq support for all of them would be a resource waste. Because of that the
221 * interrupt support for standard gpio pins is registered dynamically.
222 *
223 * It will return the irq number of the interrupt that has been registered
224 * or -ENOMEM if no more gpio interrupts can be registered. It is allowed
225 * to call this function more than once for the same gpio group (the group
226 * will be registered only once).
227 */
228extern int s5p_register_gpio_interrupt(int pin);
229
230/** s5p_register_gpioint_bank() - add gpio bank for further gpio interrupt
231 * registration (see s5p_register_gpio_interrupt function)
232 * @chain_irq: chained irq number for the gpio int handler for this bank
233 * @start: start gpio group number of this bank
234 * @nr_groups: number of gpio groups handled by this bank
235 *
236 * This functions registers initial information about gpio banks that
237 * can be later used by the s5p_register_gpio_interrupt() function to
238 * enable support for gpio interrupt for particular gpio group.
239 */
240#ifdef CONFIG_S5P_GPIO_INT
241extern int s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups);
242#else
243#define s5p_register_gpioint_bank(chain_irq, start, nr_groups) do { } while (0)
244#endif
245
246#endif /* __PLAT_GPIO_CFG_H */ 182#endif /* __PLAT_GPIO_CFG_H */
diff --git a/arch/arm/plat-samsung/include/plat/hdmi.h b/arch/arm/plat-samsung/include/plat/hdmi.h
deleted file mode 100644
index 331d046ac2c5..000000000000
--- a/arch/arm/plat-samsung/include/plat/hdmi.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __PLAT_SAMSUNG_HDMI_H
11#define __PLAT_SAMSUNG_HDMI_H __FILE__
12
13extern void s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
14 struct i2c_board_info *mhl_info, int mhl_bus);
15
16#endif /* __PLAT_SAMSUNG_HDMI_H */
diff --git a/arch/arm/plat-samsung/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h
deleted file mode 100644
index 039001c0ef05..000000000000
--- a/arch/arm/plat-samsung/include/plat/irqs.h
+++ /dev/null
@@ -1,72 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/irqs.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P Common IRQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_SAMSUNG_IRQS_H
14#define __PLAT_SAMSUNG_IRQS_H __FILE__
15
16/* we keep the first set of CPU IRQs out of the range of
17 * the ISA space, so that the PC104 has them to itself
18 * and we don't end up having to do horrible things to the
19 * standard ISA drivers....
20 *
21 * note, since we're using the VICs, our start must be a
22 * mulitple of 32 to allow the common code to work
23 */
24
25#define S5P_IRQ_OFFSET (32)
26
27#define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET)
28
29#define S5P_VIC0_BASE S5P_IRQ(0)
30#define S5P_VIC1_BASE S5P_IRQ(32)
31#define S5P_VIC2_BASE S5P_IRQ(64)
32#define S5P_VIC3_BASE S5P_IRQ(96)
33
34#define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32))
35
36#define IRQ_VIC0_BASE S5P_VIC0_BASE
37#define IRQ_VIC1_BASE S5P_VIC1_BASE
38#define IRQ_VIC2_BASE S5P_VIC2_BASE
39
40/* VIC based IRQs */
41
42#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
43#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x))
44#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
45#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x))
46
47#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
48 : ((x) - 16 + S5P_EINT_BASE2))
49
50#define EINT_OFFSET(irq) ((irq) < S5P_EINT_BASE2 ? \
51 ((irq) - S5P_EINT_BASE1) : \
52 ((irq) + 16 - S5P_EINT_BASE2))
53
54#define IRQ_EINT_BIT(x) EINT_OFFSET(x)
55
56/* Typically only a few gpio chips require gpio interrupt support.
57 To avoid memory waste irq descriptors are allocated only for
58 S5P_GPIOINT_GROUP_COUNT chips, each with total number of
59 S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
60 to any gpio chip with the s5p_register_gpio_interrupt() function */
61#define S5P_GPIOINT_GROUP_COUNT 4
62#define S5P_GPIOINT_GROUP_SIZE 8
63#define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
64
65/* IRQ types common for all s5p platforms */
66#define S5P_IRQ_TYPE_LEVEL_LOW (0x00)
67#define S5P_IRQ_TYPE_LEVEL_HIGH (0x01)
68#define S5P_IRQ_TYPE_EDGE_FALLING (0x02)
69#define S5P_IRQ_TYPE_EDGE_RISING (0x03)
70#define S5P_IRQ_TYPE_EDGE_BOTH (0x04)
71
72#endif /* __PLAT_SAMSUNG_IRQS_H */
diff --git a/arch/arm/plat-samsung/include/plat/mfc.h b/arch/arm/plat-samsung/include/plat/mfc.h
deleted file mode 100644
index 033654e91e22..000000000000
--- a/arch/arm/plat-samsung/include/plat/mfc.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __PLAT_SAMSUNG_MFC_H
11#define __PLAT_SAMSUNG_MFC_H __FILE__
12
13struct s5p_mfc_dt_meminfo {
14 unsigned long loff;
15 unsigned long lsize;
16 unsigned long roff;
17 unsigned long rsize;
18 char *compatible;
19};
20
21/**
22 * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
23 * @rbase: base address for MFC 'right' memory interface
24 * @rsize: size of the memory reserved for MFC 'right' interface
25 * @lbase: base address for MFC 'left' memory interface
26 * @lsize: size of the memory reserved for MFC 'left' interface
27 *
28 * This function reserves system memory for both MFC device memory
29 * interfaces and registers it to respective struct device entries as
30 * coherent memory.
31 */
32void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
33 phys_addr_t lbase, unsigned int lsize);
34
35#endif /* __PLAT_SAMSUNG_MFC_H */
diff --git a/arch/arm/plat-samsung/include/plat/pll.h b/arch/arm/plat-samsung/include/plat/pll.h
deleted file mode 100644
index 357af7c1c664..000000000000
--- a/arch/arm/plat-samsung/include/plat/pll.h
+++ /dev/null
@@ -1,323 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/pll.h
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * Samsung PLL codes
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18#include <asm/div64.h>
19
20#define S3C24XX_PLL_MDIV_MASK (0xFF)
21#define S3C24XX_PLL_PDIV_MASK (0x1F)
22#define S3C24XX_PLL_SDIV_MASK (0x3)
23#define S3C24XX_PLL_MDIV_SHIFT (12)
24#define S3C24XX_PLL_PDIV_SHIFT (4)
25#define S3C24XX_PLL_SDIV_SHIFT (0)
26
27static inline unsigned int s3c24xx_get_pll(unsigned int pllval,
28 unsigned int baseclk)
29{
30 unsigned int mdiv, pdiv, sdiv;
31 uint64_t fvco;
32
33 mdiv = (pllval >> S3C24XX_PLL_MDIV_SHIFT) & S3C24XX_PLL_MDIV_MASK;
34 pdiv = (pllval >> S3C24XX_PLL_PDIV_SHIFT) & S3C24XX_PLL_PDIV_MASK;
35 sdiv = (pllval >> S3C24XX_PLL_SDIV_SHIFT) & S3C24XX_PLL_SDIV_MASK;
36
37 fvco = (uint64_t)baseclk * (mdiv + 8);
38 do_div(fvco, (pdiv + 2) << sdiv);
39
40 return (unsigned int)fvco;
41}
42
43#define S3C2416_PLL_MDIV_MASK (0x3FF)
44#define S3C2416_PLL_PDIV_MASK (0x3F)
45#define S3C2416_PLL_SDIV_MASK (0x7)
46#define S3C2416_PLL_MDIV_SHIFT (14)
47#define S3C2416_PLL_PDIV_SHIFT (5)
48#define S3C2416_PLL_SDIV_SHIFT (0)
49
50static inline unsigned int s3c2416_get_pll(unsigned int pllval,
51 unsigned int baseclk)
52{
53 unsigned int mdiv, pdiv, sdiv;
54 uint64_t fvco;
55
56 mdiv = (pllval >> S3C2416_PLL_MDIV_SHIFT) & S3C2416_PLL_MDIV_MASK;
57 pdiv = (pllval >> S3C2416_PLL_PDIV_SHIFT) & S3C2416_PLL_PDIV_MASK;
58 sdiv = (pllval >> S3C2416_PLL_SDIV_SHIFT) & S3C2416_PLL_SDIV_MASK;
59
60 fvco = (uint64_t)baseclk * mdiv;
61 do_div(fvco, (pdiv << sdiv));
62
63 return (unsigned int)fvco;
64}
65
66#define S3C6400_PLL_MDIV_MASK (0x3FF)
67#define S3C6400_PLL_PDIV_MASK (0x3F)
68#define S3C6400_PLL_SDIV_MASK (0x7)
69#define S3C6400_PLL_MDIV_SHIFT (16)
70#define S3C6400_PLL_PDIV_SHIFT (8)
71#define S3C6400_PLL_SDIV_SHIFT (0)
72
73static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
74 u32 pllcon)
75{
76 u32 mdiv, pdiv, sdiv;
77 u64 fvco = baseclk;
78
79 mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
80 pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
81 sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
82
83 fvco *= mdiv;
84 do_div(fvco, (pdiv << sdiv));
85
86 return (unsigned long)fvco;
87}
88
89#define PLL6553X_MDIV_MASK (0x7F)
90#define PLL6553X_PDIV_MASK (0x1F)
91#define PLL6553X_SDIV_MASK (0x3)
92#define PLL6553X_KDIV_MASK (0xFFFF)
93#define PLL6553X_MDIV_SHIFT (16)
94#define PLL6553X_PDIV_SHIFT (8)
95#define PLL6553X_SDIV_SHIFT (0)
96
97static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
98 u32 pll_con0, u32 pll_con1)
99{
100 unsigned long result;
101 u32 mdiv, pdiv, sdiv, kdiv;
102 u64 tmp;
103
104 mdiv = (pll_con0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
105 pdiv = (pll_con0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
106 sdiv = (pll_con0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
107 kdiv = pll_con1 & PLL6553X_KDIV_MASK;
108
109 /*
110 * We need to multiple baseclk by mdiv (the integer part) and kdiv
111 * which is in 2^16ths, so shift mdiv up (does not overflow) and
112 * add kdiv before multiplying. The use of tmp is to avoid any
113 * overflows before shifting bac down into result when multipling
114 * by the mdiv and kdiv pair.
115 */
116
117 tmp = baseclk;
118 tmp *= (mdiv << 16) + kdiv;
119 do_div(tmp, (pdiv << sdiv));
120 result = tmp >> 16;
121
122 return result;
123}
124
125#define PLL35XX_MDIV_MASK (0x3FF)
126#define PLL35XX_PDIV_MASK (0x3F)
127#define PLL35XX_SDIV_MASK (0x7)
128#define PLL35XX_MDIV_SHIFT (16)
129#define PLL35XX_PDIV_SHIFT (8)
130#define PLL35XX_SDIV_SHIFT (0)
131
132static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con)
133{
134 u32 mdiv, pdiv, sdiv;
135 u64 fvco = baseclk;
136
137 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
138 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
139 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
140
141 fvco *= mdiv;
142 do_div(fvco, (pdiv << sdiv));
143
144 return (unsigned long)fvco;
145}
146
147#define PLL36XX_KDIV_MASK (0xFFFF)
148#define PLL36XX_MDIV_MASK (0x1FF)
149#define PLL36XX_PDIV_MASK (0x3F)
150#define PLL36XX_SDIV_MASK (0x7)
151#define PLL36XX_MDIV_SHIFT (16)
152#define PLL36XX_PDIV_SHIFT (8)
153#define PLL36XX_SDIV_SHIFT (0)
154
155static inline unsigned long s5p_get_pll36xx(unsigned long baseclk,
156 u32 pll_con0, u32 pll_con1)
157{
158 unsigned long result;
159 u32 mdiv, pdiv, sdiv, kdiv;
160 u64 tmp;
161
162 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
163 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
164 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
165 kdiv = pll_con1 & PLL36XX_KDIV_MASK;
166
167 tmp = baseclk;
168
169 tmp *= (mdiv << 16) + kdiv;
170 do_div(tmp, (pdiv << sdiv));
171 result = tmp >> 16;
172
173 return result;
174}
175
176#define PLL45XX_MDIV_MASK (0x3FF)
177#define PLL45XX_PDIV_MASK (0x3F)
178#define PLL45XX_SDIV_MASK (0x7)
179#define PLL45XX_MDIV_SHIFT (16)
180#define PLL45XX_PDIV_SHIFT (8)
181#define PLL45XX_SDIV_SHIFT (0)
182
183enum pll45xx_type_t {
184 pll_4500,
185 pll_4502,
186 pll_4508
187};
188
189static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
190 enum pll45xx_type_t pll_type)
191{
192 u32 mdiv, pdiv, sdiv;
193 u64 fvco = baseclk;
194
195 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
196 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
197 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
198
199 if (pll_type == pll_4508)
200 sdiv = sdiv - 1;
201
202 fvco *= mdiv;
203 do_div(fvco, (pdiv << sdiv));
204
205 return (unsigned long)fvco;
206}
207
208/* CON0 bit-fields */
209#define PLL46XX_MDIV_MASK (0x1FF)
210#define PLL46XX_PDIV_MASK (0x3F)
211#define PLL46XX_SDIV_MASK (0x7)
212#define PLL46XX_LOCKED_SHIFT (29)
213#define PLL46XX_MDIV_SHIFT (16)
214#define PLL46XX_PDIV_SHIFT (8)
215#define PLL46XX_SDIV_SHIFT (0)
216
217/* CON1 bit-fields */
218#define PLL46XX_MRR_MASK (0x1F)
219#define PLL46XX_MFR_MASK (0x3F)
220#define PLL46XX_KDIV_MASK (0xFFFF)
221#define PLL4650C_KDIV_MASK (0xFFF)
222#define PLL46XX_MRR_SHIFT (24)
223#define PLL46XX_MFR_SHIFT (16)
224#define PLL46XX_KDIV_SHIFT (0)
225
226enum pll46xx_type_t {
227 pll_4600,
228 pll_4650,
229 pll_4650c,
230};
231
232static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
233 u32 pll_con0, u32 pll_con1,
234 enum pll46xx_type_t pll_type)
235{
236 unsigned long result;
237 u32 mdiv, pdiv, sdiv, kdiv;
238 u64 tmp;
239
240 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
241 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
242 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
243 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
244
245 if (pll_type == pll_4650c)
246 kdiv = pll_con1 & PLL4650C_KDIV_MASK;
247 else
248 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
249
250 tmp = baseclk;
251
252 if (pll_type == pll_4600) {
253 tmp *= (mdiv << 16) + kdiv;
254 do_div(tmp, (pdiv << sdiv));
255 result = tmp >> 16;
256 } else {
257 tmp *= (mdiv << 10) + kdiv;
258 do_div(tmp, (pdiv << sdiv));
259 result = tmp >> 10;
260 }
261
262 return result;
263}
264
265#define PLL90XX_MDIV_MASK (0xFF)
266#define PLL90XX_PDIV_MASK (0x3F)
267#define PLL90XX_SDIV_MASK (0x7)
268#define PLL90XX_KDIV_MASK (0xffff)
269#define PLL90XX_LOCKED_SHIFT (29)
270#define PLL90XX_MDIV_SHIFT (16)
271#define PLL90XX_PDIV_SHIFT (8)
272#define PLL90XX_SDIV_SHIFT (0)
273#define PLL90XX_KDIV_SHIFT (0)
274
275static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
276 u32 pll_con, u32 pll_conk)
277{
278 unsigned long result;
279 u32 mdiv, pdiv, sdiv, kdiv;
280 u64 tmp;
281
282 mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK;
283 pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK;
284 sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK;
285 kdiv = pll_conk & PLL90XX_KDIV_MASK;
286
287 /*
288 * We need to multiple baseclk by mdiv (the integer part) and kdiv
289 * which is in 2^16ths, so shift mdiv up (does not overflow) and
290 * add kdiv before multiplying. The use of tmp is to avoid any
291 * overflows before shifting bac down into result when multipling
292 * by the mdiv and kdiv pair.
293 */
294
295 tmp = baseclk;
296 tmp *= (mdiv << 16) + kdiv;
297 do_div(tmp, (pdiv << sdiv));
298 result = tmp >> 16;
299
300 return result;
301}
302
303#define PLL65XX_MDIV_MASK (0x3FF)
304#define PLL65XX_PDIV_MASK (0x3F)
305#define PLL65XX_SDIV_MASK (0x7)
306#define PLL65XX_MDIV_SHIFT (16)
307#define PLL65XX_PDIV_SHIFT (8)
308#define PLL65XX_SDIV_SHIFT (0)
309
310static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con)
311{
312 u32 mdiv, pdiv, sdiv;
313 u64 fvco = baseclk;
314
315 mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
316 pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
317 sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
318
319 fvco *= mdiv;
320 do_div(fvco, (pdiv << sdiv));
321
322 return (unsigned long)fvco;
323}
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
deleted file mode 100644
index acacc4b88a39..000000000000
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ /dev/null
@@ -1,65 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5p-clock.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for s5p clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_S5P_CLOCK_H
14#define __ASM_PLAT_S5P_CLOCK_H __FILE__
15
16#include <linux/clk.h>
17
18#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
19
20#define clk_fin_apll clk_ext_xtal_mux
21#define clk_fin_bpll clk_ext_xtal_mux
22#define clk_fin_cpll clk_ext_xtal_mux
23#define clk_fin_mpll clk_ext_xtal_mux
24#define clk_fin_epll clk_ext_xtal_mux
25#define clk_fin_dpll clk_ext_xtal_mux
26#define clk_fin_vpll clk_ext_xtal_mux
27#define clk_fin_hpll clk_ext_xtal_mux
28
29extern struct clk clk_ext_xtal_mux;
30extern struct clk clk_xusbxti;
31extern struct clk clk_48m;
32extern struct clk s5p_clk_27m;
33extern struct clk clk_fout_apll;
34extern struct clk clk_fout_bpll;
35extern struct clk clk_fout_bpll_div2;
36extern struct clk clk_fout_cpll;
37extern struct clk clk_fout_mpll;
38extern struct clk clk_fout_mpll_div2;
39extern struct clk clk_fout_epll;
40extern struct clk clk_fout_dpll;
41extern struct clk clk_fout_vpll;
42extern struct clk clk_arm;
43extern struct clk clk_vpll;
44
45extern struct clksrc_sources clk_src_apll;
46extern struct clksrc_sources clk_src_bpll;
47extern struct clksrc_sources clk_src_bpll_fout;
48extern struct clksrc_sources clk_src_cpll;
49extern struct clksrc_sources clk_src_mpll;
50extern struct clksrc_sources clk_src_mpll_fout;
51extern struct clksrc_sources clk_src_epll;
52extern struct clksrc_sources clk_src_dpll;
53
54extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
55
56/* Common EPLL operations for S5P platform */
57extern int s5p_epll_enable(struct clk *clk, int enable);
58extern unsigned long s5p_epll_get_rate(struct clk *clk);
59
60/* SPDIF clk operations common for S5PV210/C110 and Exynos4 */
61extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate);
62extern unsigned long s5p_spdif_get_rate(struct clk *clk);
63
64extern struct clk_ops s5p_sclk_spdif_ops;
65#endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index f84b6cbc8745..2787553c3ae2 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -57,14 +57,6 @@ extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
57extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w); 57extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
58extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 58extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
59extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); 59extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
60extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
61extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
62extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
63extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
64extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
65extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
66extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
67extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
68 60
69/* S3C2416 SDHCI setup */ 61/* S3C2416 SDHCI setup */
70 62
@@ -144,45 +136,6 @@ static inline void s3c6400_default_sdhci2(void) { }
144 136
145#endif /* CONFIG_S3C64XX_SETUP_SDHCI */ 137#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
146 138
147/* S5PV210 SDHCI setup */
148
149#ifdef CONFIG_S5PV210_SETUP_SDHCI
150static inline void s5pv210_default_sdhci0(void)
151{
152#ifdef CONFIG_S3C_DEV_HSMMC
153 s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
154#endif
155}
156
157static inline void s5pv210_default_sdhci1(void)
158{
159#ifdef CONFIG_S3C_DEV_HSMMC1
160 s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
161#endif
162}
163
164static inline void s5pv210_default_sdhci2(void)
165{
166#ifdef CONFIG_S3C_DEV_HSMMC2
167 s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
168#endif
169}
170
171static inline void s5pv210_default_sdhci3(void)
172{
173#ifdef CONFIG_S3C_DEV_HSMMC3
174 s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
175#endif
176}
177
178#else
179static inline void s5pv210_default_sdhci0(void) { }
180static inline void s5pv210_default_sdhci1(void) { }
181static inline void s5pv210_default_sdhci2(void) { }
182static inline void s5pv210_default_sdhci3(void) { }
183
184#endif /* CONFIG_S5PV210_SETUP_SDHCI */
185
186static inline void s3c_sdhci_setname(int id, char *name) 139static inline void s3c_sdhci_setname(int id, char *name)
187{ 140{
188 switch (id) { 141 switch (id) {
diff --git a/arch/arm/plat-samsung/include/plat/tv-core.h b/arch/arm/plat-samsung/include/plat/tv-core.h
deleted file mode 100644
index 3bc34f3ce28f..000000000000
--- a/arch/arm/plat-samsung/include/plat/tv-core.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * arch/arm/plat-samsung/include/plat/tv.h
3 *
4 * Copyright 2011 Samsung Electronics Co., Ltd.
5 * Tomasz Stanislawski <t.stanislaws@samsung.com>
6 *
7 * Samsung TV driver core functions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __SAMSUNG_PLAT_TV_H
15#define __SAMSUNG_PLAT_TV_H __FILE__
16
17/*
18 * These functions are only for use with the core support code, such as
19 * the CPU-specific initialization code.
20 */
21
22/* Re-define device name to differentiate the subsystem in various SoCs. */
23static inline void s5p_hdmi_setname(char *name)
24{
25#ifdef CONFIG_S5P_DEV_TV
26 s5p_device_hdmi.name = name;
27#endif
28}
29
30static inline void s5p_mixer_setname(char *name)
31{
32#ifdef CONFIG_S5P_DEV_TV
33 s5p_device_mixer.name = name;
34#endif
35}
36
37static inline void s5p_sdo_setname(char *name)
38{
39#ifdef CONFIG_S5P_DEV_TV
40 s5p_device_sdo.name = name;
41#endif
42}
43
44#endif /* __SAMSUNG_PLAT_TV_H */
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index a1f925f3121f..11fbbc26e49f 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -30,7 +30,6 @@
30 30
31#include <plat/cpu.h> 31#include <plat/cpu.h>
32#include <plat/devs.h> 32#include <plat/devs.h>
33#include <plat/clock.h>
34 33
35static struct cpu_table *cpu; 34static struct cpu_table *cpu;
36 35
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index da268813901b..f6084f641e6f 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -196,7 +196,7 @@ struct samsung_gpio_pm samsung_gpio_pm_2bit = {
196 .resume = samsung_gpio_pm_2bit_resume, 196 .resume = samsung_gpio_pm_2bit_resume,
197}; 197};
198 198
199#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) 199#if defined(CONFIG_ARCH_S3C64XX)
200static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip) 200static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
201{ 201{
202 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); 202 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
@@ -306,7 +306,7 @@ struct samsung_gpio_pm samsung_gpio_pm_4bit = {
306 .save = samsung_gpio_pm_4bit_save, 306 .save = samsung_gpio_pm_4bit_save,
307 .resume = samsung_gpio_pm_4bit_resume, 307 .resume = samsung_gpio_pm_4bit_resume,
308}; 308};
309#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */ 309#endif /* CONFIG_ARCH_S3C64XX */
310 310
311/** 311/**
312 * samsung_pm_save_gpio() - save gpio chip data for suspend 312 * samsung_pm_save_gpio() - save gpio chip data for suspend
diff --git a/arch/arm/plat-samsung/s5p-clock.c b/arch/arm/plat-samsung/s5p-clock.c
deleted file mode 100644
index 48a159911037..000000000000
--- a/arch/arm/plat-samsung/s5p-clock.c
+++ /dev/null
@@ -1,294 +0,0 @@
1/*
2 * Copyright 2009 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * S5P - Common clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/device.h>
20#include <linux/io.h>
21#include <asm/div64.h>
22
23#include <mach/regs-clock.h>
24
25#include <plat/clock.h>
26#include <plat/clock-clksrc.h>
27#include <plat/s5p-clock.h>
28
29/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
30 * clk_ext_xtal_mux.
31*/
32struct clk clk_ext_xtal_mux = {
33 .name = "ext_xtal",
34 .id = -1,
35};
36
37struct clk clk_xusbxti = {
38 .name = "xusbxti",
39 .id = -1,
40 .rate = 24000000,
41};
42
43struct clk s5p_clk_27m = {
44 .name = "clk_27m",
45 .id = -1,
46 .rate = 27000000,
47};
48
49/* 48MHz USB Phy clock output */
50struct clk clk_48m = {
51 .name = "clk_48m",
52 .id = -1,
53 .rate = 48000000,
54};
55
56/* APLL clock output
57 * No need .ctrlbit, this is always on
58*/
59struct clk clk_fout_apll = {
60 .name = "fout_apll",
61 .id = -1,
62};
63
64/* BPLL clock output */
65
66struct clk clk_fout_bpll = {
67 .name = "fout_bpll",
68 .id = -1,
69};
70
71struct clk clk_fout_bpll_div2 = {
72 .name = "fout_bpll_div2",
73 .id = -1,
74};
75
76/* CPLL clock output */
77
78struct clk clk_fout_cpll = {
79 .name = "fout_cpll",
80 .id = -1,
81};
82
83/* MPLL clock output
84 * No need .ctrlbit, this is always on
85*/
86struct clk clk_fout_mpll = {
87 .name = "fout_mpll",
88 .id = -1,
89};
90
91struct clk clk_fout_mpll_div2 = {
92 .name = "fout_mpll_div2",
93 .id = -1,
94};
95
96/* EPLL clock output */
97struct clk clk_fout_epll = {
98 .name = "fout_epll",
99 .id = -1,
100 .ctrlbit = (1 << 31),
101};
102
103/* DPLL clock output */
104struct clk clk_fout_dpll = {
105 .name = "fout_dpll",
106 .id = -1,
107 .ctrlbit = (1 << 31),
108};
109
110/* VPLL clock output */
111struct clk clk_fout_vpll = {
112 .name = "fout_vpll",
113 .id = -1,
114 .ctrlbit = (1 << 31),
115};
116
117/* Possible clock sources for APLL Mux */
118static struct clk *clk_src_apll_list[] = {
119 [0] = &clk_fin_apll,
120 [1] = &clk_fout_apll,
121};
122
123struct clksrc_sources clk_src_apll = {
124 .sources = clk_src_apll_list,
125 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
126};
127
128/* Possible clock sources for BPLL Mux */
129static struct clk *clk_src_bpll_list[] = {
130 [0] = &clk_fin_bpll,
131 [1] = &clk_fout_bpll,
132};
133
134struct clksrc_sources clk_src_bpll = {
135 .sources = clk_src_bpll_list,
136 .nr_sources = ARRAY_SIZE(clk_src_bpll_list),
137};
138
139static struct clk *clk_src_bpll_fout_list[] = {
140 [0] = &clk_fout_bpll_div2,
141 [1] = &clk_fout_bpll,
142};
143
144struct clksrc_sources clk_src_bpll_fout = {
145 .sources = clk_src_bpll_fout_list,
146 .nr_sources = ARRAY_SIZE(clk_src_bpll_fout_list),
147};
148
149/* Possible clock sources for CPLL Mux */
150static struct clk *clk_src_cpll_list[] = {
151 [0] = &clk_fin_cpll,
152 [1] = &clk_fout_cpll,
153};
154
155struct clksrc_sources clk_src_cpll = {
156 .sources = clk_src_cpll_list,
157 .nr_sources = ARRAY_SIZE(clk_src_cpll_list),
158};
159
160/* Possible clock sources for MPLL Mux */
161static struct clk *clk_src_mpll_list[] = {
162 [0] = &clk_fin_mpll,
163 [1] = &clk_fout_mpll,
164};
165
166struct clksrc_sources clk_src_mpll = {
167 .sources = clk_src_mpll_list,
168 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
169};
170
171static struct clk *clk_src_mpll_fout_list[] = {
172 [0] = &clk_fout_mpll_div2,
173 [1] = &clk_fout_mpll,
174};
175
176struct clksrc_sources clk_src_mpll_fout = {
177 .sources = clk_src_mpll_fout_list,
178 .nr_sources = ARRAY_SIZE(clk_src_mpll_fout_list),
179};
180
181/* Possible clock sources for EPLL Mux */
182static struct clk *clk_src_epll_list[] = {
183 [0] = &clk_fin_epll,
184 [1] = &clk_fout_epll,
185};
186
187struct clksrc_sources clk_src_epll = {
188 .sources = clk_src_epll_list,
189 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
190};
191
192/* Possible clock sources for DPLL Mux */
193static struct clk *clk_src_dpll_list[] = {
194 [0] = &clk_fin_dpll,
195 [1] = &clk_fout_dpll,
196};
197
198struct clksrc_sources clk_src_dpll = {
199 .sources = clk_src_dpll_list,
200 .nr_sources = ARRAY_SIZE(clk_src_dpll_list),
201};
202
203struct clk clk_vpll = {
204 .name = "vpll",
205 .id = -1,
206};
207
208int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
209{
210 unsigned int ctrlbit = clk->ctrlbit;
211 u32 con;
212
213 con = __raw_readl(reg);
214 con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
215 __raw_writel(con, reg);
216 return 0;
217}
218
219int s5p_epll_enable(struct clk *clk, int enable)
220{
221 unsigned int ctrlbit = clk->ctrlbit;
222 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
223
224 if (enable)
225 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
226 else
227 __raw_writel(epll_con, S5P_EPLL_CON);
228
229 return 0;
230}
231
232unsigned long s5p_epll_get_rate(struct clk *clk)
233{
234 return clk->rate;
235}
236
237int s5p_spdif_set_rate(struct clk *clk, unsigned long rate)
238{
239 struct clk *pclk;
240 int ret;
241
242 pclk = clk_get_parent(clk);
243 if (IS_ERR(pclk))
244 return -EINVAL;
245
246 ret = pclk->ops->set_rate(pclk, rate);
247 clk_put(pclk);
248
249 return ret;
250}
251
252unsigned long s5p_spdif_get_rate(struct clk *clk)
253{
254 struct clk *pclk;
255 int rate;
256
257 pclk = clk_get_parent(clk);
258 if (IS_ERR(pclk))
259 return -EINVAL;
260
261 rate = pclk->ops->get_rate(pclk);
262 clk_put(pclk);
263
264 return rate;
265}
266
267struct clk_ops s5p_sclk_spdif_ops = {
268 .set_rate = s5p_spdif_set_rate,
269 .get_rate = s5p_spdif_get_rate,
270};
271
272static struct clk *s5p_clks[] __initdata = {
273 &clk_ext_xtal_mux,
274 &clk_48m,
275 &s5p_clk_27m,
276 &clk_fout_apll,
277 &clk_fout_mpll,
278 &clk_fout_epll,
279 &clk_fout_dpll,
280 &clk_fout_vpll,
281 &clk_vpll,
282 &clk_xusbxti,
283};
284
285void __init s5p_register_clocks(unsigned long xtal_freq)
286{
287 int ret;
288
289 clk_ext_xtal_mux.rate = xtal_freq;
290
291 ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
292 if (ret > 0)
293 printk(KERN_ERR "Failed to register s5p clocks\n");
294}
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index 469b86260fe3..0b04b6b0fa30 100644
--- a/arch/arm/plat-samsung/s5p-dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -17,56 +17,16 @@
17#include <linux/of_fdt.h> 17#include <linux/of_fdt.h>
18#include <linux/of.h> 18#include <linux/of.h>
19 19
20#include <plat/mfc.h>
21
22#ifdef CONFIG_SAMSUNG_ATAGS
23#include <mach/map.h>
24#include <mach/irqs.h>
25#include <plat/devs.h>
26
27static struct resource s5p_mfc_resource[] = {
28 [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
29 [1] = DEFINE_RES_IRQ(IRQ_MFC),
30};
31
32struct platform_device s5p_device_mfc = {
33 .name = "s5p-mfc",
34 .id = -1,
35 .num_resources = ARRAY_SIZE(s5p_mfc_resource),
36 .resource = s5p_mfc_resource,
37};
38
39/*
40 * MFC hardware has 2 memory interfaces which are modelled as two separate
41 * platform devices to let dma-mapping distinguish between them.
42 *
43 * MFC parent device (s5p_device_mfc) must be registered before memory
44 * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
45 */
46
47struct platform_device s5p_device_mfc_l = {
48 .name = "s5p-mfc-l",
49 .id = -1,
50 .dev = {
51 .parent = &s5p_device_mfc.dev,
52 .dma_mask = &s5p_device_mfc_l.dev.coherent_dma_mask,
53 .coherent_dma_mask = DMA_BIT_MASK(32),
54 },
55};
56
57struct platform_device s5p_device_mfc_r = {
58 .name = "s5p-mfc-r",
59 .id = -1,
60 .dev = {
61 .parent = &s5p_device_mfc.dev,
62 .dma_mask = &s5p_device_mfc_r.dev.coherent_dma_mask,
63 .coherent_dma_mask = DMA_BIT_MASK(32),
64 },
65};
66#else
67static struct platform_device s5p_device_mfc_l; 20static struct platform_device s5p_device_mfc_l;
68static struct platform_device s5p_device_mfc_r; 21static struct platform_device s5p_device_mfc_r;
69#endif 22
23struct s5p_mfc_dt_meminfo {
24 unsigned long loff;
25 unsigned long lsize;
26 unsigned long roff;
27 unsigned long rsize;
28 char *compatible;
29};
70 30
71struct s5p_mfc_reserved_mem { 31struct s5p_mfc_reserved_mem {
72 phys_addr_t base; 32 phys_addr_t base;
@@ -77,7 +37,7 @@ struct s5p_mfc_reserved_mem {
77static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata; 37static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
78 38
79 39
80void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, 40static void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
81 phys_addr_t lbase, unsigned int lsize) 41 phys_addr_t lbase, unsigned int lsize)
82{ 42{
83 int i; 43 int i;
@@ -100,28 +60,6 @@ void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
100 } 60 }
101} 61}
102 62
103#ifdef CONFIG_SAMSUNG_ATAGS
104static int __init s5p_mfc_memory_init(void)
105{
106 int i;
107
108 for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
109 struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
110 if (!area->base)
111 continue;
112
113 if (dma_declare_coherent_memory(area->dev, area->base,
114 area->base, area->size,
115 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0)
116 printk(KERN_ERR "Failed to declare coherent memory for MFC device (%ld bytes at 0x%08lx)\n",
117 area->size, (unsigned long) area->base);
118 }
119 return 0;
120}
121device_initcall(s5p_mfc_memory_init);
122#endif
123
124#ifdef CONFIG_OF
125int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname, 63int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
126 int depth, void *data) 64 int depth, void *data)
127{ 65{
@@ -154,4 +92,3 @@ int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
154 92
155 return 1; 93 return 1;
156} 94}
157#endif
diff --git a/arch/arm/plat-samsung/s5p-dev-uart.c b/arch/arm/plat-samsung/s5p-dev-uart.c
deleted file mode 100644
index 8c4487af98c8..000000000000
--- a/arch/arm/plat-samsung/s5p-dev-uart.c
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * Copyright (c) 2009,2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * Base S5P UART resource and device definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/ioport.h>
17#include <linux/platform_device.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach/irq.h>
21#include <mach/map.h>
22
23#include <plat/devs.h>
24
25 /* Serial port registrations */
26
27static struct resource s5p_uart0_resource[] = {
28 [0] = DEFINE_RES_MEM(S5P_PA_UART0, S5P_SZ_UART),
29 [1] = DEFINE_RES_IRQ(IRQ_UART0),
30};
31
32static struct resource s5p_uart1_resource[] = {
33 [0] = DEFINE_RES_MEM(S5P_PA_UART1, S5P_SZ_UART),
34 [1] = DEFINE_RES_IRQ(IRQ_UART1),
35};
36
37static struct resource s5p_uart2_resource[] = {
38 [0] = DEFINE_RES_MEM(S5P_PA_UART2, S5P_SZ_UART),
39 [1] = DEFINE_RES_IRQ(IRQ_UART2),
40};
41
42static struct resource s5p_uart3_resource[] = {
43#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
44 [0] = DEFINE_RES_MEM(S5P_PA_UART3, S5P_SZ_UART),
45 [1] = DEFINE_RES_IRQ(IRQ_UART3),
46#endif
47};
48
49static struct resource s5p_uart4_resource[] = {
50#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
51 [0] = DEFINE_RES_MEM(S5P_PA_UART4, S5P_SZ_UART),
52 [1] = DEFINE_RES_IRQ(IRQ_UART4),
53#endif
54};
55
56static struct resource s5p_uart5_resource[] = {
57#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
58 [0] = DEFINE_RES_MEM(S5P_PA_UART5, S5P_SZ_UART),
59 [1] = DEFINE_RES_IRQ(IRQ_UART5),
60#endif
61};
62
63struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
64 [0] = {
65 .resources = s5p_uart0_resource,
66 .nr_resources = ARRAY_SIZE(s5p_uart0_resource),
67 },
68 [1] = {
69 .resources = s5p_uart1_resource,
70 .nr_resources = ARRAY_SIZE(s5p_uart1_resource),
71 },
72 [2] = {
73 .resources = s5p_uart2_resource,
74 .nr_resources = ARRAY_SIZE(s5p_uart2_resource),
75 },
76 [3] = {
77 .resources = s5p_uart3_resource,
78 .nr_resources = ARRAY_SIZE(s5p_uart3_resource),
79 },
80 [4] = {
81 .resources = s5p_uart4_resource,
82 .nr_resources = ARRAY_SIZE(s5p_uart4_resource),
83 },
84 [5] = {
85 .resources = s5p_uart5_resource,
86 .nr_resources = ARRAY_SIZE(s5p_uart5_resource),
87 },
88};
diff --git a/arch/arm/plat-samsung/s5p-irq-eint.c b/arch/arm/plat-samsung/s5p-irq-eint.c
deleted file mode 100644
index ebee4dc11a94..000000000000
--- a/arch/arm/plat-samsung/s5p-irq-eint.c
+++ /dev/null
@@ -1,221 +0,0 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * S5P - IRQ EINT support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/device.h>
17#include <linux/gpio.h>
18#include <linux/irqchip/arm-vic.h>
19#include <linux/of.h>
20
21#include <plat/regs-irqtype.h>
22
23#include <mach/map.h>
24#include <plat/cpu.h>
25#include <plat/pm.h>
26
27#include <plat/gpio-cfg.h>
28#include <mach/regs-gpio.h>
29
30static inline void s5p_irq_eint_mask(struct irq_data *data)
31{
32 u32 mask;
33
34 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
35 mask |= eint_irq_to_bit(data->irq);
36 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
37}
38
39static void s5p_irq_eint_unmask(struct irq_data *data)
40{
41 u32 mask;
42
43 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
44 mask &= ~(eint_irq_to_bit(data->irq));
45 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
46}
47
48static inline void s5p_irq_eint_ack(struct irq_data *data)
49{
50 __raw_writel(eint_irq_to_bit(data->irq),
51 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
52}
53
54static void s5p_irq_eint_maskack(struct irq_data *data)
55{
56 /* compiler should in-line these */
57 s5p_irq_eint_mask(data);
58 s5p_irq_eint_ack(data);
59}
60
61static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type)
62{
63 int offs = EINT_OFFSET(data->irq);
64 int shift;
65 u32 ctrl, mask;
66 u32 newvalue = 0;
67
68 switch (type) {
69 case IRQ_TYPE_EDGE_RISING:
70 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
71 break;
72
73 case IRQ_TYPE_EDGE_FALLING:
74 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
75 break;
76
77 case IRQ_TYPE_EDGE_BOTH:
78 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
79 break;
80
81 case IRQ_TYPE_LEVEL_LOW:
82 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
83 break;
84
85 case IRQ_TYPE_LEVEL_HIGH:
86 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
87 break;
88
89 default:
90 printk(KERN_ERR "No such irq type %d", type);
91 return -EINVAL;
92 }
93
94 shift = (offs & 0x7) * 4;
95 mask = 0x7 << shift;
96
97 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
98 ctrl &= ~mask;
99 ctrl |= newvalue << shift;
100 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
101
102 if ((0 <= offs) && (offs < 8))
103 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
104
105 else if ((8 <= offs) && (offs < 16))
106 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
107
108 else if ((16 <= offs) && (offs < 24))
109 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
110
111 else if ((24 <= offs) && (offs < 32))
112 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
113
114 else
115 printk(KERN_ERR "No such irq number %d", offs);
116
117 return 0;
118}
119
120static struct irq_chip s5p_irq_eint = {
121 .name = "s5p-eint",
122 .irq_mask = s5p_irq_eint_mask,
123 .irq_unmask = s5p_irq_eint_unmask,
124 .irq_mask_ack = s5p_irq_eint_maskack,
125 .irq_ack = s5p_irq_eint_ack,
126 .irq_set_type = s5p_irq_eint_set_type,
127#ifdef CONFIG_PM
128 .irq_set_wake = s3c_irqext_wake,
129#endif
130};
131
132/* s5p_irq_demux_eint
133 *
134 * This function demuxes the IRQ from the group0 external interrupts,
135 * from EINTs 16 to 31. It is designed to be inlined into the specific
136 * handler s5p_irq_demux_eintX_Y.
137 *
138 * Each EINT pend/mask registers handle eight of them.
139 */
140static inline void s5p_irq_demux_eint(unsigned int start)
141{
142 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
143 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
144 unsigned int irq;
145
146 status &= ~mask;
147 status &= 0xff;
148
149 while (status) {
150 irq = fls(status) - 1;
151 generic_handle_irq(irq + start);
152 status &= ~(1 << irq);
153 }
154}
155
156static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
157{
158 s5p_irq_demux_eint(IRQ_EINT(16));
159 s5p_irq_demux_eint(IRQ_EINT(24));
160}
161
162static inline void s5p_irq_vic_eint_mask(struct irq_data *data)
163{
164 void __iomem *base = irq_data_get_irq_chip_data(data);
165
166 s5p_irq_eint_mask(data);
167 writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR);
168}
169
170static void s5p_irq_vic_eint_unmask(struct irq_data *data)
171{
172 void __iomem *base = irq_data_get_irq_chip_data(data);
173
174 s5p_irq_eint_unmask(data);
175 writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE);
176}
177
178static inline void s5p_irq_vic_eint_ack(struct irq_data *data)
179{
180 __raw_writel(eint_irq_to_bit(data->irq),
181 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
182}
183
184static void s5p_irq_vic_eint_maskack(struct irq_data *data)
185{
186 s5p_irq_vic_eint_mask(data);
187 s5p_irq_vic_eint_ack(data);
188}
189
190static struct irq_chip s5p_irq_vic_eint = {
191 .name = "s5p_vic_eint",
192 .irq_mask = s5p_irq_vic_eint_mask,
193 .irq_unmask = s5p_irq_vic_eint_unmask,
194 .irq_mask_ack = s5p_irq_vic_eint_maskack,
195 .irq_ack = s5p_irq_vic_eint_ack,
196 .irq_set_type = s5p_irq_eint_set_type,
197#ifdef CONFIG_PM
198 .irq_set_wake = s3c_irqext_wake,
199#endif
200};
201
202static int __init s5p_init_irq_eint(void)
203{
204 int irq;
205
206 if (of_have_populated_dt())
207 return -ENODEV;
208
209 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
210 irq_set_chip(irq, &s5p_irq_vic_eint);
211
212 for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
213 irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
214 set_irq_flags(irq, IRQF_VALID);
215 }
216
217 irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
218 return 0;
219}
220
221arch_initcall(s5p_init_irq_eint);
diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c
deleted file mode 100644
index fafdb059043a..000000000000
--- a/arch/arm/plat-samsung/s5p-irq-gpioint.c
+++ /dev/null
@@ -1,218 +0,0 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * Author: Kyungmin Park <kyungmin.park@samsung.com>
4 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
5 * Author: Marek Szyprowski <m.szyprowski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/irqchip/chained_irq.h>
18#include <linux/io.h>
19#include <linux/gpio.h>
20#include <linux/slab.h>
21
22#include <mach/map.h>
23#include <plat/gpio-core.h>
24#include <plat/gpio-cfg.h>
25
26#define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
27
28#define CON_OFFSET 0x700
29#define MASK_OFFSET 0x900
30#define PEND_OFFSET 0xA00
31#define REG_OFFSET(x) ((x) << 2)
32
33struct s5p_gpioint_bank {
34 struct list_head list;
35 int start;
36 int nr_groups;
37 int irq;
38 struct samsung_gpio_chip **chips;
39 void (*handler)(unsigned int, struct irq_desc *);
40};
41
42static LIST_HEAD(banks);
43
44static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
45{
46 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
47 struct irq_chip_type *ct = gc->chip_types;
48 unsigned int shift = (d->irq - gc->irq_base) << 2;
49
50 switch (type) {
51 case IRQ_TYPE_EDGE_RISING:
52 type = S5P_IRQ_TYPE_EDGE_RISING;
53 break;
54 case IRQ_TYPE_EDGE_FALLING:
55 type = S5P_IRQ_TYPE_EDGE_FALLING;
56 break;
57 case IRQ_TYPE_EDGE_BOTH:
58 type = S5P_IRQ_TYPE_EDGE_BOTH;
59 break;
60 case IRQ_TYPE_LEVEL_HIGH:
61 type = S5P_IRQ_TYPE_LEVEL_HIGH;
62 break;
63 case IRQ_TYPE_LEVEL_LOW:
64 type = S5P_IRQ_TYPE_LEVEL_LOW;
65 break;
66 case IRQ_TYPE_NONE:
67 default:
68 printk(KERN_WARNING "No irq type\n");
69 return -EINVAL;
70 }
71
72 gc->type_cache &= ~(0x7 << shift);
73 gc->type_cache |= type << shift;
74 writel(gc->type_cache, gc->reg_base + ct->regs.type);
75 return 0;
76}
77
78static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
79{
80 struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
81 int group, pend_offset, mask_offset;
82 unsigned int pend, mask;
83
84 struct irq_chip *chip = irq_get_chip(irq);
85 chained_irq_enter(chip, desc);
86
87 for (group = 0; group < bank->nr_groups; group++) {
88 struct samsung_gpio_chip *chip = bank->chips[group];
89 if (!chip)
90 continue;
91
92 pend_offset = REG_OFFSET(group);
93 pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
94 if (!pend)
95 continue;
96
97 mask_offset = REG_OFFSET(group);
98 mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
99 pend &= ~mask;
100
101 while (pend) {
102 int offset = fls(pend) - 1;
103 int real_irq = chip->irq_base + offset;
104 generic_handle_irq(real_irq);
105 pend &= ~BIT(offset);
106 }
107 }
108 chained_irq_exit(chip, desc);
109}
110
111static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
112{
113 static int used_gpioint_groups = 0;
114 int group = chip->group;
115 struct s5p_gpioint_bank *b, *bank = NULL;
116 struct irq_chip_generic *gc;
117 struct irq_chip_type *ct;
118
119 if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
120 return -ENOMEM;
121
122 list_for_each_entry(b, &banks, list) {
123 if (group >= b->start && group < b->start + b->nr_groups) {
124 bank = b;
125 break;
126 }
127 }
128 if (!bank)
129 return -EINVAL;
130
131 if (!bank->handler) {
132 bank->chips = kzalloc(sizeof(struct samsung_gpio_chip *) *
133 bank->nr_groups, GFP_KERNEL);
134 if (!bank->chips)
135 return -ENOMEM;
136
137 irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
138 irq_set_handler_data(bank->irq, bank);
139 bank->handler = s5p_gpioint_handler;
140 printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
141 bank->irq);
142 }
143
144 /*
145 * chained GPIO irq has been successfully registered, allocate new gpio
146 * int group and assign irq nubmers
147 */
148 chip->irq_base = S5P_GPIOINT_BASE +
149 used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
150 used_gpioint_groups++;
151
152 bank->chips[group - bank->start] = chip;
153
154 gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
155 GPIO_BASE(chip),
156 handle_level_irq);
157 if (!gc)
158 return -ENOMEM;
159 ct = gc->chip_types;
160 ct->chip.irq_ack = irq_gc_ack_set_bit;
161 ct->chip.irq_mask = irq_gc_mask_set_bit;
162 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
163 ct->chip.irq_set_type = s5p_gpioint_set_type,
164 ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
165 ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
166 ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
167 irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
168 IRQ_GC_INIT_MASK_CACHE,
169 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
170 return 0;
171}
172
173int __init s5p_register_gpio_interrupt(int pin)
174{
175 struct samsung_gpio_chip *my_chip = samsung_gpiolib_getchip(pin);
176 int offset, group;
177 int ret;
178
179 if (!my_chip)
180 return -EINVAL;
181
182 offset = pin - my_chip->chip.base;
183 group = my_chip->group;
184
185 /* check if the group has been already registered */
186 if (my_chip->irq_base)
187 goto success;
188
189 /* register gpio group */
190 ret = s5p_gpioint_add(my_chip);
191 if (ret == 0) {
192 my_chip->chip.to_irq = samsung_gpiolib_to_irq;
193 printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
194 group);
195 goto success;
196 }
197 return ret;
198success:
199 my_chip->bitmap_gpio_int |= BIT(offset);
200
201 return my_chip->irq_base + offset;
202}
203
204int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
205{
206 struct s5p_gpioint_bank *bank;
207
208 bank = kzalloc(sizeof(*bank), GFP_KERNEL);
209 if (!bank)
210 return -ENOMEM;
211
212 bank->start = start;
213 bank->nr_groups = nr_groups;
214 bank->irq = chain_irq;
215
216 list_add_tail(&bank->list, &banks);
217 return 0;
218}
diff --git a/arch/arm/plat-samsung/s5p-irq-pm.c b/arch/arm/plat-samsung/s5p-irq-pm.c
deleted file mode 100644
index 52b16943617e..000000000000
--- a/arch/arm/plat-samsung/s5p-irq-pm.c
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Based on arch/arm/plat-s3c24xx/irq-pm.c,
6 * Copyright (c) 2003,2004 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18
19#include <plat/cpu.h>
20#include <plat/irqs.h>
21#include <plat/pm.h>
22#include <mach/map.h>
23
24#include <mach/regs-gpio.h>
25#include <mach/regs-irq.h>
26
27/* state for IRQs over sleep */
28
29/* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM,
30 * as wakeup sources
31 *
32 * set bit to 1 in allow bitfield to enable the wakeup settings on it
33*/
34
35unsigned long s3c_irqwake_intallow = 0x00000006L;
36unsigned long s3c_irqwake_eintallow = 0xffffffffL;
37
38int s3c_irq_wake(struct irq_data *data, unsigned int state)
39{
40 unsigned long irqbit;
41 unsigned int irq_rtc_tic, irq_rtc_alarm;
42
43 irq_rtc_tic = IRQ_RTC_TIC;
44 irq_rtc_alarm = IRQ_RTC_ALARM;
45
46 if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) {
47 irqbit = 1 << (data->irq + 1 - irq_rtc_alarm);
48
49 if (!state)
50 s3c_irqwake_intmask |= irqbit;
51 else
52 s3c_irqwake_intmask &= ~irqbit;
53 } else {
54 return -ENOENT;
55 }
56
57 return 0;
58}
59
60static struct sleep_save eint_save[] = {
61 SAVE_ITEM(S5P_EINT_CON(0)),
62 SAVE_ITEM(S5P_EINT_CON(1)),
63 SAVE_ITEM(S5P_EINT_CON(2)),
64 SAVE_ITEM(S5P_EINT_CON(3)),
65
66 SAVE_ITEM(S5P_EINT_FLTCON(0)),
67 SAVE_ITEM(S5P_EINT_FLTCON(1)),
68 SAVE_ITEM(S5P_EINT_FLTCON(2)),
69 SAVE_ITEM(S5P_EINT_FLTCON(3)),
70 SAVE_ITEM(S5P_EINT_FLTCON(4)),
71 SAVE_ITEM(S5P_EINT_FLTCON(5)),
72 SAVE_ITEM(S5P_EINT_FLTCON(6)),
73 SAVE_ITEM(S5P_EINT_FLTCON(7)),
74
75 SAVE_ITEM(S5P_EINT_MASK(0)),
76 SAVE_ITEM(S5P_EINT_MASK(1)),
77 SAVE_ITEM(S5P_EINT_MASK(2)),
78 SAVE_ITEM(S5P_EINT_MASK(3)),
79};
80
81int s3c24xx_irq_suspend(void)
82{
83 s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save));
84
85 return 0;
86}
87
88void s3c24xx_irq_resume(void)
89{
90 s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save));
91}
92
diff --git a/arch/arm/plat-samsung/s5p-irq.c b/arch/arm/plat-samsung/s5p-irq.c
deleted file mode 100644
index ddfaca9c79d8..000000000000
--- a/arch/arm/plat-samsung/s5p-irq.c
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * S5P - Interrupt handling
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/irqchip/arm-vic.h>
17
18#include <mach/irqs.h>
19#include <mach/map.h>
20#include <plat/cpu.h>
21
22void __init s5p_init_irq(u32 *vic, u32 num_vic)
23{
24#ifdef CONFIG_ARM_VIC
25 int irq;
26
27 /* initialize the VICs */
28 for (irq = 0; irq < num_vic; irq++)
29 vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
30#endif
31}
diff --git a/arch/arm/plat-samsung/s5p-pm.c b/arch/arm/plat-samsung/s5p-pm.c
deleted file mode 100644
index 0747468f0936..000000000000
--- a/arch/arm/plat-samsung/s5p-pm.c
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * S5P Power Manager (Suspend-To-RAM) support
6 *
7 * Based on arch/arm/plat-s3c24xx/pm.c
8 * Copyright (c) 2004,2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/suspend.h>
17#include <plat/pm.h>
18
19#define PFX "s5p pm: "
20
21/* s3c_pm_configure_extint
22 *
23 * configure all external interrupt pins
24*/
25
26void s3c_pm_configure_extint(void)
27{
28 /* nothing here yet */
29}
30
31void s3c_pm_restore_core(void)
32{
33 /* nothing here yet */
34}
35
36void s3c_pm_save_core(void)
37{
38 /* nothing here yet */
39}
40
diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S
deleted file mode 100644
index 25c68ceb9e2b..000000000000
--- a/arch/arm/plat-samsung/s5p-sleep.S
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common S5P Sleep Code
6 * Based on S3C64XX sleep code by:
7 * Ben Dooks, (c) 2008 Simtec Electronics
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/linkage.h>
25
26 .data
27 .align
28
29 /*
30 * sleep magic, to allow the bootloader to check for an valid
31 * image to resume to. Must be the first word before the
32 * s3c_cpu_resume entry.
33 */
34
35 .word 0x2bedf00d
36
37 /*
38 * s3c_cpu_resume
39 *
40 * resume code entry for bootloader to call
41 */
42
43ENTRY(s3c_cpu_resume)
44 b cpu_resume
45ENDPROC(s3c_cpu_resume)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 04:03:42 -0500