diff options
author | Romain Naour <romain.naour@openwide.fr> | 2013-01-09 21:47:04 -0500 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2013-03-05 06:19:54 -0500 |
commit | ad38bdd15d5b97dcb1ffc46ea77c237e30312fbb (patch) | |
tree | 1133a774d4d56c9a05b07cbe3644a3c254ea8ab7 /arch/arm/plat-samsung | |
parent | 6a5a2e3b0dee0e26edeef448d7f097a2109b56bc (diff) |
ARM: SAMSUNG: Remove unused plat-samsung/time.c
Signed-off-by: Naour Romain <romain.naour@openwide.fr>
Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-samsung')
-rw-r--r-- | arch/arm/plat-samsung/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/cpu.h | 4 | ||||
-rw-r--r-- | arch/arm/plat-samsung/time.c | 287 |
3 files changed, 0 insertions, 292 deletions
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index e1244eb79333..a23c460299a1 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile | |||
@@ -12,7 +12,6 @@ obj- := | |||
12 | # Objects we always build independent of SoC choice | 12 | # Objects we always build independent of SoC choice |
13 | 13 | ||
14 | obj-y += init.o cpu.o | 14 | obj-y += init.o cpu.o |
15 | obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o | ||
16 | obj-$(CONFIG_SAMSUNG_HRT) += samsung-time.o | 15 | obj-$(CONFIG_SAMSUNG_HRT) += samsung-time.o |
17 | 16 | ||
18 | obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o | 17 | obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o |
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 100c29606e1e..e126644cadf4 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h | |||
@@ -192,10 +192,6 @@ extern void s3c24xx_init_uartdevs(char *name, | |||
192 | struct s3c24xx_uart_resources *res, | 192 | struct s3c24xx_uart_resources *res, |
193 | struct s3c2410_uartcfg *cfg, int no); | 193 | struct s3c2410_uartcfg *cfg, int no); |
194 | 194 | ||
195 | /* timer for s5pc100 only */ | ||
196 | |||
197 | extern void s3c24xx_timer_init(void); | ||
198 | |||
199 | extern struct syscore_ops s3c2410_pm_syscore_ops; | 195 | extern struct syscore_ops s3c2410_pm_syscore_ops; |
200 | extern struct syscore_ops s3c2412_pm_syscore_ops; | 196 | extern struct syscore_ops s3c2412_pm_syscore_ops; |
201 | extern struct syscore_ops s3c2416_pm_syscore_ops; | 197 | extern struct syscore_ops s3c2416_pm_syscore_ops; |
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c deleted file mode 100644 index 73defd00c3e4..000000000000 --- a/arch/arm/plat-samsung/time.c +++ /dev/null | |||
@@ -1,287 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-samsung/time.c | ||
2 | * | ||
3 | * Copyright (C) 2003-2005 Simtec Electronics | ||
4 | * Ben Dooks, <ben@simtec.co.uk> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | |||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/sched.h> | ||
23 | #include <linux/init.h> | ||
24 | #include <linux/interrupt.h> | ||
25 | #include <linux/irq.h> | ||
26 | #include <linux/err.h> | ||
27 | #include <linux/clk.h> | ||
28 | #include <linux/io.h> | ||
29 | #include <linux/platform_device.h> | ||
30 | #include <linux/syscore_ops.h> | ||
31 | |||
32 | #include <asm/mach-types.h> | ||
33 | |||
34 | #include <asm/irq.h> | ||
35 | #include <mach/map.h> | ||
36 | #include <plat/regs-timer.h> | ||
37 | #include <mach/regs-irq.h> | ||
38 | #include <asm/mach/time.h> | ||
39 | #include <mach/tick.h> | ||
40 | |||
41 | #include <plat/clock.h> | ||
42 | #include <plat/cpu.h> | ||
43 | |||
44 | static unsigned long timer_startval; | ||
45 | static unsigned long timer_usec_ticks; | ||
46 | |||
47 | #ifndef TICK_MAX | ||
48 | #define TICK_MAX (0xffff) | ||
49 | #endif | ||
50 | |||
51 | #define TIMER_USEC_SHIFT 16 | ||
52 | |||
53 | /* we use the shifted arithmetic to work out the ratio of timer ticks | ||
54 | * to usecs, as often the peripheral clock is not a nice even multiple | ||
55 | * of 1MHz. | ||
56 | * | ||
57 | * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok | ||
58 | * for the current HZ value of 200 without producing overflows. | ||
59 | * | ||
60 | * Original patch by Dimitry Andric, updated by Ben Dooks | ||
61 | */ | ||
62 | |||
63 | |||
64 | /* timer_mask_usec_ticks | ||
65 | * | ||
66 | * given a clock and divisor, make the value to pass into timer_ticks_to_usec | ||
67 | * to scale the ticks into usecs | ||
68 | */ | ||
69 | |||
70 | static inline unsigned long | ||
71 | timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk) | ||
72 | { | ||
73 | unsigned long den = pclk / 1000; | ||
74 | |||
75 | return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den; | ||
76 | } | ||
77 | |||
78 | /* timer_ticks_to_usec | ||
79 | * | ||
80 | * convert timer ticks to usec. | ||
81 | */ | ||
82 | |||
83 | static inline unsigned long timer_ticks_to_usec(unsigned long ticks) | ||
84 | { | ||
85 | unsigned long res; | ||
86 | |||
87 | res = ticks * timer_usec_ticks; | ||
88 | res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */ | ||
89 | |||
90 | return res >> TIMER_USEC_SHIFT; | ||
91 | } | ||
92 | |||
93 | /*** | ||
94 | * Returns microsecond since last clock interrupt. Note that interrupts | ||
95 | * will have been disabled by do_gettimeoffset() | ||
96 | * IRQs are disabled before entering here from do_gettimeofday() | ||
97 | */ | ||
98 | |||
99 | static u32 s3c2410_gettimeoffset(void) | ||
100 | { | ||
101 | unsigned long tdone; | ||
102 | unsigned long tval; | ||
103 | |||
104 | /* work out how many ticks have gone since last timer interrupt */ | ||
105 | |||
106 | tval = __raw_readl(S3C2410_TCNTO(4)); | ||
107 | tdone = timer_startval - tval; | ||
108 | |||
109 | /* check to see if there is an interrupt pending */ | ||
110 | |||
111 | if (s3c24xx_ostimer_pending()) { | ||
112 | /* re-read the timer, and try and fix up for the missed | ||
113 | * interrupt. Note, the interrupt may go off before the | ||
114 | * timer has re-loaded from wrapping. | ||
115 | */ | ||
116 | |||
117 | tval = __raw_readl(S3C2410_TCNTO(4)); | ||
118 | tdone = timer_startval - tval; | ||
119 | |||
120 | if (tval != 0) | ||
121 | tdone += timer_startval; | ||
122 | } | ||
123 | |||
124 | return timer_ticks_to_usec(tdone) * 1000; | ||
125 | } | ||
126 | |||
127 | |||
128 | /* | ||
129 | * IRQ handler for the timer | ||
130 | */ | ||
131 | static irqreturn_t | ||
132 | s3c2410_timer_interrupt(int irq, void *dev_id) | ||
133 | { | ||
134 | timer_tick(); | ||
135 | return IRQ_HANDLED; | ||
136 | } | ||
137 | |||
138 | static struct irqaction s3c2410_timer_irq = { | ||
139 | .name = "S3C2410 Timer Tick", | ||
140 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
141 | .handler = s3c2410_timer_interrupt, | ||
142 | }; | ||
143 | |||
144 | #define use_tclk1_12() ( \ | ||
145 | machine_is_bast() || \ | ||
146 | machine_is_vr1000() || \ | ||
147 | machine_is_anubis() || \ | ||
148 | machine_is_osiris()) | ||
149 | |||
150 | static struct clk *tin; | ||
151 | static struct clk *tdiv; | ||
152 | static struct clk *timerclk; | ||
153 | |||
154 | /* | ||
155 | * Set up timer interrupt, and return the current time in seconds. | ||
156 | * | ||
157 | * Currently we only use timer4, as it is the only timer which has no | ||
158 | * other function that can be exploited externally | ||
159 | */ | ||
160 | static void s3c2410_timer_setup (void) | ||
161 | { | ||
162 | unsigned long tcon; | ||
163 | unsigned long tcnt; | ||
164 | unsigned long tcfg1; | ||
165 | unsigned long tcfg0; | ||
166 | |||
167 | tcnt = TICK_MAX; /* default value for tcnt */ | ||
168 | |||
169 | /* configure the system for whichever machine is in use */ | ||
170 | |||
171 | if (use_tclk1_12()) { | ||
172 | /* timer is at 12MHz, scaler is 1 */ | ||
173 | timer_usec_ticks = timer_mask_usec_ticks(1, 12000000); | ||
174 | tcnt = 12000000 / HZ; | ||
175 | |||
176 | tcfg1 = __raw_readl(S3C2410_TCFG1); | ||
177 | tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; | ||
178 | tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1; | ||
179 | __raw_writel(tcfg1, S3C2410_TCFG1); | ||
180 | } else { | ||
181 | unsigned long pclk; | ||
182 | struct clk *tscaler; | ||
183 | |||
184 | /* for the h1940 (and others), we use the pclk from the core | ||
185 | * to generate the timer values. since values around 50 to | ||
186 | * 70MHz are not values we can directly generate the timer | ||
187 | * value from, we need to pre-scale and divide before using it. | ||
188 | * | ||
189 | * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz | ||
190 | * (8.45 ticks per usec) | ||
191 | */ | ||
192 | |||
193 | pclk = clk_get_rate(timerclk); | ||
194 | |||
195 | /* configure clock tick */ | ||
196 | |||
197 | timer_usec_ticks = timer_mask_usec_ticks(6, pclk); | ||
198 | |||
199 | tscaler = clk_get_parent(tdiv); | ||
200 | |||
201 | clk_set_rate(tscaler, pclk / 3); | ||
202 | clk_set_rate(tdiv, pclk / 6); | ||
203 | clk_set_parent(tin, tdiv); | ||
204 | |||
205 | tcnt = clk_get_rate(tin) / HZ; | ||
206 | } | ||
207 | |||
208 | tcon = __raw_readl(S3C2410_TCON); | ||
209 | tcfg0 = __raw_readl(S3C2410_TCFG0); | ||
210 | tcfg1 = __raw_readl(S3C2410_TCFG1); | ||
211 | |||
212 | /* timers reload after counting zero, so reduce the count by 1 */ | ||
213 | |||
214 | tcnt--; | ||
215 | |||
216 | printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n", | ||
217 | tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks); | ||
218 | |||
219 | /* check to see if timer is within 16bit range... */ | ||
220 | if (tcnt > TICK_MAX) { | ||
221 | panic("setup_timer: HZ is too small, cannot configure timer!"); | ||
222 | return; | ||
223 | } | ||
224 | |||
225 | __raw_writel(tcfg1, S3C2410_TCFG1); | ||
226 | __raw_writel(tcfg0, S3C2410_TCFG0); | ||
227 | |||
228 | timer_startval = tcnt; | ||
229 | __raw_writel(tcnt, S3C2410_TCNTB(4)); | ||
230 | |||
231 | /* ensure timer is stopped... */ | ||
232 | |||
233 | tcon &= ~(7<<20); | ||
234 | tcon |= S3C2410_TCON_T4RELOAD; | ||
235 | tcon |= S3C2410_TCON_T4MANUALUPD; | ||
236 | |||
237 | __raw_writel(tcon, S3C2410_TCON); | ||
238 | __raw_writel(tcnt, S3C2410_TCNTB(4)); | ||
239 | __raw_writel(tcnt, S3C2410_TCMPB(4)); | ||
240 | |||
241 | /* start the timer running */ | ||
242 | tcon |= S3C2410_TCON_T4START; | ||
243 | tcon &= ~S3C2410_TCON_T4MANUALUPD; | ||
244 | __raw_writel(tcon, S3C2410_TCON); | ||
245 | } | ||
246 | |||
247 | static void __init s3c2410_timer_resources(void) | ||
248 | { | ||
249 | struct platform_device tmpdev; | ||
250 | |||
251 | tmpdev.dev.bus = &platform_bus_type; | ||
252 | tmpdev.id = 4; | ||
253 | |||
254 | timerclk = clk_get(NULL, "timers"); | ||
255 | if (IS_ERR(timerclk)) | ||
256 | panic("failed to get clock for system timer"); | ||
257 | |||
258 | clk_enable(timerclk); | ||
259 | |||
260 | if (!use_tclk1_12()) { | ||
261 | tmpdev.id = 4; | ||
262 | tmpdev.dev.init_name = "s3c24xx-pwm.4"; | ||
263 | tin = clk_get(&tmpdev.dev, "pwm-tin"); | ||
264 | if (IS_ERR(tin)) | ||
265 | panic("failed to get pwm-tin clock for system timer"); | ||
266 | |||
267 | tdiv = clk_get(&tmpdev.dev, "pwm-tdiv"); | ||
268 | if (IS_ERR(tdiv)) | ||
269 | panic("failed to get pwm-tdiv clock for system timer"); | ||
270 | } | ||
271 | |||
272 | clk_enable(tin); | ||
273 | } | ||
274 | |||
275 | static struct syscore_ops s3c24xx_syscore_ops = { | ||
276 | .resume = s3c2410_timer_setup, | ||
277 | }; | ||
278 | |||
279 | void __init s3c24xx_timer_init(void) | ||
280 | { | ||
281 | arch_gettimeoffset = s3c2410_gettimeoffset; | ||
282 | |||
283 | s3c2410_timer_resources(); | ||
284 | s3c2410_timer_setup(); | ||
285 | setup_irq(IRQ_TIMER4, &s3c2410_timer_irq); | ||
286 | register_syscore_ops(&s3c24xx_syscore_ops); | ||
287 | } | ||