ARM: EXYNOS: Stop using legacy Samsung PM code

Since Exynos SoCs does not follow most of the semantics of older SoCs
when configuring the system to enter sleep, there is no reason to rely
on the legacy Samsung PM core anymore.

This patch adds local Exynos suspend ops and removes all the code left
unnecessary. As a side effect, suspend support on Exynos becomes
multiplatform-friendly.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

1 files changed, 0 insertions, 45 deletions

diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S
index 20764bd5518e..c5001659bdf8 100644
--- a/arch/arm/plat-samsung/s5p-sleep.S
+++ b/arch/arm/plat-samsung/s5p-sleep.S
@@ -23,18 +23,7 @@
 
 #include <linux/linkage.h>
 #include <asm/asm-offsets.h>
-#include <asm/hardware/cache-l2x0.h>
 
-#define CPU_MASK        0xff0ffff0
-#define CPU_CORTEX_A9   0x410fc090
-
-/*
- *       The following code is located into the .data section. This is to
- *       allow l2x0_regs_phys to be accessed with a relative load while we
- *       can't rely on any MMU translation. We could have put l2x0_regs_phys
- *       in the .text section as well, but some setups might insist on it to
- *       be truly read-only. (Reference from: arch/arm/kernel/sleep.S)
- */
         .data
         .align
 
@@ -53,39 +42,5 @@
          */
 
 ENTRY(s3c_cpu_resume)
-#ifdef CONFIG_CACHE_L2X0
-        mrc     p15, 0, r0, c0, c0, 0
-        ldr     r1, =CPU_MASK
-        and     r0, r0, r1
-        ldr     r1, =CPU_CORTEX_A9
-        cmp     r0, r1
-        bne     skip_l2_resume
-        adr     r0, l2x0_regs_phys
-        ldr     r0, [r0]
-        cmp     r0, #0
-        beq     skip_l2_resume
-        ldr     r1, [r0, #L2X0_R_PHY_BASE]
-        ldr     r2, [r1, #L2X0_CTRL]
-        tst     r2, #0x1
-        bne     skip_l2_resume
-        ldr     r2, [r0, #L2X0_R_AUX_CTRL]
-        str     r2, [r1, #L2X0_AUX_CTRL]
-        ldr     r2, [r0, #L2X0_R_TAG_LATENCY]
-        str     r2, [r1, #L2X0_TAG_LATENCY_CTRL]
-        ldr     r2, [r0, #L2X0_R_DATA_LATENCY]
-        str     r2, [r1, #L2X0_DATA_LATENCY_CTRL]
-        ldr     r2, [r0, #L2X0_R_PREFETCH_CTRL]
-        str     r2, [r1, #L2X0_PREFETCH_CTRL]
-        ldr     r2, [r0, #L2X0_R_PWR_CTRL]
-        str     r2, [r1, #L2X0_POWER_CTRL]
-        mov     r2, #1
-        str     r2, [r1, #L2X0_CTRL]
-skip_l2_resume:
-#endif
         b       cpu_resume
 ENDPROC(s3c_cpu_resume)
-#ifdef CONFIG_CACHE_L2X0
-        .globl l2x0_regs_phys
-l2x0_regs_phys:
-        .long   0
-#endif