diff options
author | Inderpal Singh <inderpal.singh@linaro.org> | 2013-04-04 03:01:15 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2013-04-04 03:01:20 -0400 |
commit | d9cdeb814fd6bb1b5eaa49c5848f10ba7acf992a (patch) | |
tree | 13704f870f16b8aed79cf0d186f4cfa0086436fe /arch/arm/plat-samsung/s5p-sleep.S | |
parent | 1fa86dcfea3142522e8fd5f85fbbf79b84063cae (diff) |
ARM: SAMSUNG: check processor type before cache restoration in resume
Only cortex-a9 based samsung platforms have l2x0 cache controller. Hence check
the same before restoring the cache in resume.
This is needed for single kernel image.
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-samsung/s5p-sleep.S')
-rw-r--r-- | arch/arm/plat-samsung/s5p-sleep.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S index bdf6dadf8790..a030e7301da8 100644 --- a/arch/arm/plat-samsung/s5p-sleep.S +++ b/arch/arm/plat-samsung/s5p-sleep.S | |||
@@ -25,6 +25,9 @@ | |||
25 | #include <asm/asm-offsets.h> | 25 | #include <asm/asm-offsets.h> |
26 | #include <asm/hardware/cache-l2x0.h> | 26 | #include <asm/hardware/cache-l2x0.h> |
27 | 27 | ||
28 | #define CPU_MASK 0xff0ffff0 | ||
29 | #define CPU_CORTEX_A9 0x410fc090 | ||
30 | |||
28 | /* | 31 | /* |
29 | * The following code is located into the .data section. This is to | 32 | * The following code is located into the .data section. This is to |
30 | * allow l2x0_regs_phys to be accessed with a relative load while we | 33 | * allow l2x0_regs_phys to be accessed with a relative load while we |
@@ -51,6 +54,12 @@ | |||
51 | 54 | ||
52 | ENTRY(s3c_cpu_resume) | 55 | ENTRY(s3c_cpu_resume) |
53 | #ifdef CONFIG_CACHE_L2X0 | 56 | #ifdef CONFIG_CACHE_L2X0 |
57 | mrc p15, 0, r0, c0, c0, 0 | ||
58 | ldr r1, =CPU_MASK | ||
59 | and r0, r0, r1 | ||
60 | ldr r1, =CPU_CORTEX_A9 | ||
61 | cmp r0, r1 | ||
62 | bne resume_l2on | ||
54 | adr r0, l2x0_regs_phys | 63 | adr r0, l2x0_regs_phys |
55 | ldr r0, [r0] | 64 | ldr r0, [r0] |
56 | ldr r1, [r0, #L2X0_R_PHY_BASE] | 65 | ldr r1, [r0, #L2X0_R_PHY_BASE] |