diff options
author | Ben Dooks <ben-linux@fluff.org> | 2010-02-22 18:38:26 -0500 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2010-02-22 18:38:26 -0500 |
commit | 7f0ff702cdf51472750f4b6042866f1b83a11215 (patch) | |
tree | 15ce32849cfb8ff3c7205e97a5f76051c08058b0 /arch/arm/plat-samsung/include | |
parent | d35b7a829a13b69c4747b69380b504b6544a2375 (diff) | |
parent | 110d85acd479b80dc11b7fa3abef63285da8ea0c (diff) |
ARM: Merge next-samsung-s3c64xx-platdeletion
Merge branch 'next-samsung-s3c64xx-platdeletion' into next-samsung
Conflicts:
arch/arm/mach-s3c64xx/Makefile (fixed)
Diffstat (limited to 'arch/arm/plat-samsung/include')
-rw-r--r-- | arch/arm/plat-samsung/include/plat/clock.h | 1 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/dma-s3c24xx.h | 84 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/sdhci.h | 43 |
3 files changed, 103 insertions, 25 deletions
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index ba9a1cdd3a28..60b62692ac7a 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h | |||
@@ -94,7 +94,6 @@ extern void s3c_register_clocks(struct clk *clk, int nr_clks); | |||
94 | 94 | ||
95 | extern int s3c24xx_register_baseclocks(unsigned long xtal); | 95 | extern int s3c24xx_register_baseclocks(unsigned long xtal); |
96 | 96 | ||
97 | extern void s3c64xx_register_clocks(void); | ||
98 | extern void s5p_register_clocks(unsigned long xtal_freq); | 97 | extern void s5p_register_clocks(unsigned long xtal_freq); |
99 | 98 | ||
100 | extern void s3c24xx_setup_clocks(unsigned long fclk, | 99 | extern void s3c24xx_setup_clocks(unsigned long fclk, |
diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h new file mode 100644 index 000000000000..336d5ac02035 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h | |||
@@ -0,0 +1,84 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h | ||
2 | * | ||
3 | * Copyright (C) 2006 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * Samsung S3C24XX DMA support - per SoC functions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <plat/dma-core.h> | ||
14 | |||
15 | extern struct sysdev_class dma_sysclass; | ||
16 | extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS]; | ||
17 | |||
18 | #define DMA_CH_VALID (1<<31) | ||
19 | #define DMA_CH_NEVER (1<<30) | ||
20 | |||
21 | struct s3c24xx_dma_addr { | ||
22 | unsigned long from; | ||
23 | unsigned long to; | ||
24 | }; | ||
25 | |||
26 | /* struct s3c24xx_dma_map | ||
27 | * | ||
28 | * this holds the mapping information for the channel selected | ||
29 | * to be connected to the specified device | ||
30 | */ | ||
31 | |||
32 | struct s3c24xx_dma_map { | ||
33 | const char *name; | ||
34 | struct s3c24xx_dma_addr hw_addr; | ||
35 | |||
36 | unsigned long channels[S3C_DMA_CHANNELS]; | ||
37 | unsigned long channels_rx[S3C_DMA_CHANNELS]; | ||
38 | }; | ||
39 | |||
40 | struct s3c24xx_dma_selection { | ||
41 | struct s3c24xx_dma_map *map; | ||
42 | unsigned long map_size; | ||
43 | unsigned long dcon_mask; | ||
44 | |||
45 | void (*select)(struct s3c2410_dma_chan *chan, | ||
46 | struct s3c24xx_dma_map *map); | ||
47 | |||
48 | void (*direction)(struct s3c2410_dma_chan *chan, | ||
49 | struct s3c24xx_dma_map *map, | ||
50 | enum s3c2410_dmasrc dir); | ||
51 | }; | ||
52 | |||
53 | extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel); | ||
54 | |||
55 | /* struct s3c24xx_dma_order_ch | ||
56 | * | ||
57 | * channel map for one of the `enum dma_ch` dma channels. the list | ||
58 | * entry contains a set of low-level channel numbers, orred with | ||
59 | * DMA_CH_VALID, which are checked in the order in the array. | ||
60 | */ | ||
61 | |||
62 | struct s3c24xx_dma_order_ch { | ||
63 | unsigned int list[S3C_DMA_CHANNELS]; /* list of channels */ | ||
64 | unsigned int flags; /* flags */ | ||
65 | }; | ||
66 | |||
67 | /* struct s3c24xx_dma_order | ||
68 | * | ||
69 | * information provided by either the core or the board to give the | ||
70 | * dma system a hint on how to allocate channels | ||
71 | */ | ||
72 | |||
73 | struct s3c24xx_dma_order { | ||
74 | struct s3c24xx_dma_order_ch channels[DMACH_MAX]; | ||
75 | }; | ||
76 | |||
77 | extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map); | ||
78 | |||
79 | /* DMA init code, called from the cpu support code */ | ||
80 | |||
81 | extern int s3c2410_dma_init(void); | ||
82 | |||
83 | extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq, | ||
84 | unsigned int stride); | ||
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 53198673b6bd..7d07cd7aa4f2 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h | |||
@@ -78,8 +78,8 @@ extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); | |||
78 | 78 | ||
79 | /* S3C6400 SDHCI setup */ | 79 | /* S3C6400 SDHCI setup */ |
80 | 80 | ||
81 | #ifdef CONFIG_S3C6400_SETUP_SDHCI | 81 | #ifdef CONFIG_S3C64XX_SETUP_SDHCI |
82 | extern char *s3c6400_hsmmc_clksrcs[4]; | 82 | extern char *s3c64xx_hsmmc_clksrcs[4]; |
83 | 83 | ||
84 | #ifdef CONFIG_S3C_DEV_HSMMC | 84 | #ifdef CONFIG_S3C_DEV_HSMMC |
85 | extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, | 85 | extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, |
@@ -89,7 +89,7 @@ extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, | |||
89 | 89 | ||
90 | static inline void s3c6400_default_sdhci0(void) | 90 | static inline void s3c6400_default_sdhci0(void) |
91 | { | 91 | { |
92 | s3c_hsmmc0_def_platdata.clocks = s3c6400_hsmmc_clksrcs; | 92 | s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; |
93 | s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; | 93 | s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; |
94 | s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; | 94 | s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; |
95 | } | 95 | } |
@@ -101,7 +101,7 @@ static inline void s3c6400_default_sdhci0(void) { } | |||
101 | #ifdef CONFIG_S3C_DEV_HSMMC1 | 101 | #ifdef CONFIG_S3C_DEV_HSMMC1 |
102 | static inline void s3c6400_default_sdhci1(void) | 102 | static inline void s3c6400_default_sdhci1(void) |
103 | { | 103 | { |
104 | s3c_hsmmc1_def_platdata.clocks = s3c6400_hsmmc_clksrcs; | 104 | s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; |
105 | s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; | 105 | s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; |
106 | s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; | 106 | s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; |
107 | } | 107 | } |
@@ -112,7 +112,7 @@ static inline void s3c6400_default_sdhci1(void) { } | |||
112 | #ifdef CONFIG_S3C_DEV_HSMMC2 | 112 | #ifdef CONFIG_S3C_DEV_HSMMC2 |
113 | static inline void s3c6400_default_sdhci2(void) | 113 | static inline void s3c6400_default_sdhci2(void) |
114 | { | 114 | { |
115 | s3c_hsmmc2_def_platdata.clocks = s3c6400_hsmmc_clksrcs; | 115 | s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; |
116 | s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; | 116 | s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; |
117 | s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; | 117 | s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; |
118 | } | 118 | } |
@@ -120,27 +120,19 @@ static inline void s3c6400_default_sdhci2(void) | |||
120 | static inline void s3c6400_default_sdhci2(void) { } | 120 | static inline void s3c6400_default_sdhci2(void) { } |
121 | #endif /* CONFIG_S3C_DEV_HSMMC2 */ | 121 | #endif /* CONFIG_S3C_DEV_HSMMC2 */ |
122 | 122 | ||
123 | #else | ||
124 | static inline void s3c6400_default_sdhci0(void) { } | ||
125 | static inline void s3c6400_default_sdhci1(void) { } | ||
126 | #endif /* CONFIG_S3C6400_SETUP_SDHCI */ | ||
127 | |||
128 | /* S3C6410 SDHCI setup */ | 123 | /* S3C6410 SDHCI setup */ |
129 | 124 | ||
130 | #ifdef CONFIG_S3C6410_SETUP_SDHCI | 125 | extern void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev, |
131 | extern char *s3c6410_hsmmc_clksrcs[4]; | 126 | void __iomem *r, |
132 | 127 | struct mmc_ios *ios, | |
133 | extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, | 128 | struct mmc_card *card); |
134 | void __iomem *r, | ||
135 | struct mmc_ios *ios, | ||
136 | struct mmc_card *card); | ||
137 | 129 | ||
138 | #ifdef CONFIG_S3C_DEV_HSMMC | 130 | #ifdef CONFIG_S3C_DEV_HSMMC |
139 | static inline void s3c6410_default_sdhci0(void) | 131 | static inline void s3c6410_default_sdhci0(void) |
140 | { | 132 | { |
141 | s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs; | 133 | s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; |
142 | s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; | 134 | s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; |
143 | s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; | 135 | s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; |
144 | } | 136 | } |
145 | #else | 137 | #else |
146 | static inline void s3c6410_default_sdhci0(void) { } | 138 | static inline void s3c6410_default_sdhci0(void) { } |
@@ -149,9 +141,9 @@ static inline void s3c6410_default_sdhci0(void) { } | |||
149 | #ifdef CONFIG_S3C_DEV_HSMMC1 | 141 | #ifdef CONFIG_S3C_DEV_HSMMC1 |
150 | static inline void s3c6410_default_sdhci1(void) | 142 | static inline void s3c6410_default_sdhci1(void) |
151 | { | 143 | { |
152 | s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs; | 144 | s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; |
153 | s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; | 145 | s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; |
154 | s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; | 146 | s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; |
155 | } | 147 | } |
156 | #else | 148 | #else |
157 | static inline void s3c6410_default_sdhci1(void) { } | 149 | static inline void s3c6410_default_sdhci1(void) { } |
@@ -160,9 +152,9 @@ static inline void s3c6410_default_sdhci1(void) { } | |||
160 | #ifdef CONFIG_S3C_DEV_HSMMC2 | 152 | #ifdef CONFIG_S3C_DEV_HSMMC2 |
161 | static inline void s3c6410_default_sdhci2(void) | 153 | static inline void s3c6410_default_sdhci2(void) |
162 | { | 154 | { |
163 | s3c_hsmmc2_def_platdata.clocks = s3c6410_hsmmc_clksrcs; | 155 | s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; |
164 | s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; | 156 | s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; |
165 | s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; | 157 | s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; |
166 | } | 158 | } |
167 | #else | 159 | #else |
168 | static inline void s3c6410_default_sdhci2(void) { } | 160 | static inline void s3c6410_default_sdhci2(void) { } |
@@ -171,7 +163,10 @@ static inline void s3c6410_default_sdhci2(void) { } | |||
171 | #else | 163 | #else |
172 | static inline void s3c6410_default_sdhci0(void) { } | 164 | static inline void s3c6410_default_sdhci0(void) { } |
173 | static inline void s3c6410_default_sdhci1(void) { } | 165 | static inline void s3c6410_default_sdhci1(void) { } |
174 | #endif /* CONFIG_S3C6410_SETUP_SDHCI */ | 166 | static inline void s3c6400_default_sdhci0(void) { } |
167 | static inline void s3c6400_default_sdhci1(void) { } | ||
168 | |||
169 | #endif /* CONFIG_S3C64XX_SETUP_SDHCI */ | ||
175 | 170 | ||
176 | /* S5PC100 SDHCI setup */ | 171 | /* S5PC100 SDHCI setup */ |
177 | 172 | ||