aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-samsung/clock.c
diff options
context:
space:
mode:
authorThomas Abraham <thomas.ab@samsung.com>2011-06-14 06:12:26 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-07-20 06:11:29 -0400
commite83626f2fd48fa53ece85760c7e0b4ec4a996a91 (patch)
tree8f89557b9e9f1e39314d9eabda7454b34a15b8a1 /arch/arm/plat-samsung/clock.c
parentf86c6660927614fcda257e083569bfb252fcf85e (diff)
ARM: S3C24XX: Add clkdev support
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-samsung/clock.c')
-rw-r--r--arch/arm/plat-samsung/clock.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index e30bd4591a30..aecf9e90d4fc 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -195,7 +195,6 @@ struct clk_ops clk_ops_def_setrate = {
195 195
196struct clk clk_xtal = { 196struct clk clk_xtal = {
197 .name = "xtal", 197 .name = "xtal",
198 .id = -1,
199 .rate = 0, 198 .rate = 0,
200 .parent = NULL, 199 .parent = NULL,
201 .ctrlbit = 0, 200 .ctrlbit = 0,
@@ -203,30 +202,25 @@ struct clk clk_xtal = {
203 202
204struct clk clk_ext = { 203struct clk clk_ext = {
205 .name = "ext", 204 .name = "ext",
206 .id = -1,
207}; 205};
208 206
209struct clk clk_epll = { 207struct clk clk_epll = {
210 .name = "epll", 208 .name = "epll",
211 .id = -1,
212}; 209};
213 210
214struct clk clk_mpll = { 211struct clk clk_mpll = {
215 .name = "mpll", 212 .name = "mpll",
216 .id = -1,
217 .ops = &clk_ops_def_setrate, 213 .ops = &clk_ops_def_setrate,
218}; 214};
219 215
220struct clk clk_upll = { 216struct clk clk_upll = {
221 .name = "upll", 217 .name = "upll",
222 .id = -1,
223 .parent = NULL, 218 .parent = NULL,
224 .ctrlbit = 0, 219 .ctrlbit = 0,
225}; 220};
226 221
227struct clk clk_f = { 222struct clk clk_f = {
228 .name = "fclk", 223 .name = "fclk",
229 .id = -1,
230 .rate = 0, 224 .rate = 0,
231 .parent = &clk_mpll, 225 .parent = &clk_mpll,
232 .ctrlbit = 0, 226 .ctrlbit = 0,
@@ -234,7 +228,6 @@ struct clk clk_f = {
234 228
235struct clk clk_h = { 229struct clk clk_h = {
236 .name = "hclk", 230 .name = "hclk",
237 .id = -1,
238 .rate = 0, 231 .rate = 0,
239 .parent = NULL, 232 .parent = NULL,
240 .ctrlbit = 0, 233 .ctrlbit = 0,
@@ -243,7 +236,6 @@ struct clk clk_h = {
243 236
244struct clk clk_p = { 237struct clk clk_p = {
245 .name = "pclk", 238 .name = "pclk",
246 .id = -1,
247 .rate = 0, 239 .rate = 0,
248 .parent = NULL, 240 .parent = NULL,
249 .ctrlbit = 0, 241 .ctrlbit = 0,
@@ -252,7 +244,6 @@ struct clk clk_p = {
252 244
253struct clk clk_usb_bus = { 245struct clk clk_usb_bus = {
254 .name = "usb-bus", 246 .name = "usb-bus",
255 .id = -1,
256 .rate = 0, 247 .rate = 0,
257 .parent = &clk_upll, 248 .parent = &clk_upll,
258}; 249};
@@ -260,7 +251,6 @@ struct clk clk_usb_bus = {
260 251
261struct clk s3c24xx_uclk = { 252struct clk s3c24xx_uclk = {
262 .name = "uclk", 253 .name = "uclk",
263 .id = -1,
264}; 254};
265 255
266/* initialise the clock system */ 256/* initialise the clock system */