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authorKyungmin Park <kyungmin.park@samsung.com>2009-11-17 02:41:13 -0500
committerBen Dooks <ben-linux@fluff.org>2009-11-30 20:33:13 -0500
commitff916f25b2890403a9e6c02c98391daeb71ae92a (patch)
tree1998e2c0ed6fbadf4147ea10bc719ab223bac107 /arch/arm/plat-s5pc1xx
parent9ebaf2f4e7090a8c3b0c99419924b1e8f99a07a3 (diff)
ARM: S5PC1XX: clocks reimplementation
Clocks hierarchy has been completely reimplemented to match the S5PC100 specification. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s5pc1xx')
-rw-r--r--arch/arm/plat-s5pc1xx/Makefile1
-rw-r--r--arch/arm/plat-s5pc1xx/clock.c728
-rw-r--r--arch/arm/plat-s5pc1xx/cpu.c5
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/s5pc100.h5
-rw-r--r--arch/arm/plat-s5pc1xx/s5pc100-clock.c1531
5 files changed, 1504 insertions, 766 deletions
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
index f1ecb2c37ee2..ebbf36490f4c 100644
--- a/arch/arm/plat-s5pc1xx/Makefile
+++ b/arch/arm/plat-s5pc1xx/Makefile
@@ -14,6 +14,7 @@ obj- :=
14obj-y += dev-uart.o 14obj-y += dev-uart.o
15obj-y += cpu.o 15obj-y += cpu.o
16obj-y += irq.o 16obj-y += irq.o
17obj-y += clock.o
17 18
18# CPU support 19# CPU support
19 20
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c
new file mode 100644
index 000000000000..26c21d849790
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/clock.c
@@ -0,0 +1,728 @@
1/* linux/arch/arm/plat-s5pc1xx/clock.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 *
5 * S5PC1XX Base clock support
6 *
7 * Based on plat-s3c64xx/clock.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/ioport.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <mach/hardware.h>
22#include <mach/map.h>
23
24#include <plat/regs-clock.h>
25#include <plat/devs.h>
26#include <plat/clock.h>
27
28struct clk clk_27m = {
29 .name = "clk_27m",
30 .id = -1,
31 .rate = 27000000,
32};
33
34static int clk_48m_ctrl(struct clk *clk, int enable)
35{
36 unsigned long flags;
37 u32 val;
38
39 /* can't rely on clock lock, this register has other usages */
40 local_irq_save(flags);
41
42 val = __raw_readl(S5PC100_CLKSRC1);
43 if (enable)
44 val |= S5PC100_CLKSRC1_CLK48M_MASK;
45 else
46 val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
47
48 __raw_writel(val, S5PC100_CLKSRC1);
49 local_irq_restore(flags);
50
51 return 0;
52}
53
54struct clk clk_48m = {
55 .name = "clk_48m",
56 .id = -1,
57 .rate = 48000000,
58 .enable = clk_48m_ctrl,
59};
60
61struct clk clk_54m = {
62 .name = "clk_54m",
63 .id = -1,
64 .rate = 54000000,
65};
66
67static int clk_default_setrate(struct clk *clk, unsigned long rate)
68{
69 clk->rate = rate;
70 return 0;
71}
72
73static int clk_dummy_enable(struct clk *clk, int enable)
74{
75 return 0;
76}
77
78struct clk clk_hd0 = {
79 .name = "hclkd0",
80 .id = -1,
81 .rate = 0,
82 .parent = NULL,
83 .ctrlbit = 0,
84 .set_rate = clk_default_setrate,
85 .enable = clk_dummy_enable,
86};
87
88struct clk clk_pd0 = {
89 .name = "pclkd0",
90 .id = -1,
91 .rate = 0,
92 .parent = NULL,
93 .ctrlbit = 0,
94 .set_rate = clk_default_setrate,
95 .enable = clk_dummy_enable,
96};
97
98static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
99{
100 unsigned int ctrlbit = clk->ctrlbit;
101 u32 con;
102
103 con = __raw_readl(reg);
104 if (enable)
105 con |= ctrlbit;
106 else
107 con &= ~ctrlbit;
108 __raw_writel(con, reg);
109
110 return 0;
111}
112
113static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
114{
115 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
116}
117
118static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
119{
120 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
121}
122
123static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
124{
125 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
126}
127
128static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
129{
130 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
131}
132
133static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
134{
135 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
136}
137
138static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
139{
140 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
141}
142
143static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
144{
145 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
146}
147
148static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
149{
150 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
151}
152
153static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
154{
155 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
156}
157
158static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
159{
160 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
161}
162
163int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
164{
165 return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
166}
167
168int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
169{
170 return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
171}
172
173static struct clk s5pc100_init_clocks_disable[] = {
174 {
175 .name = "dsi",
176 .id = -1,
177 .parent = &clk_p,
178 .enable = s5pc100_clk_d11_ctrl,
179 .ctrlbit = S5PC100_CLKGATE_D11_DSI,
180 }, {
181 .name = "csi",
182 .id = -1,
183 .parent = &clk_h,
184 .enable = s5pc100_clk_d11_ctrl,
185 .ctrlbit = S5PC100_CLKGATE_D11_CSI,
186 }, {
187 .name = "ccan",
188 .id = 0,
189 .parent = &clk_p,
190 .enable = s5pc100_clk_d14_ctrl,
191 .ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
192 }, {
193 .name = "ccan",
194 .id = 1,
195 .parent = &clk_p,
196 .enable = s5pc100_clk_d14_ctrl,
197 .ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
198 }, {
199 .name = "keypad",
200 .id = -1,
201 .parent = &clk_p,
202 .enable = s5pc100_clk_d15_ctrl,
203 .ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
204 }, {
205 .name = "hclkd2",
206 .id = -1,
207 .parent = NULL,
208 .enable = s5pc100_clk_d20_ctrl,
209 .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
210 }, {
211 .name = "iis-d2",
212 .id = -1,
213 .parent = NULL,
214 .enable = s5pc100_clk_d20_ctrl,
215 .ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
216 },
217};
218
219static struct clk s5pc100_init_clocks[] = {
220 /* System1 (D0_0) devices */
221 {
222 .name = "intc",
223 .id = -1,
224 .parent = &clk_hd0,
225 .enable = s5pc100_clk_d00_ctrl,
226 .ctrlbit = S5PC100_CLKGATE_D00_INTC,
227 }, {
228 .name = "tzic",
229 .id = -1,
230 .parent = &clk_hd0,
231 .enable = s5pc100_clk_d00_ctrl,
232 .ctrlbit = S5PC100_CLKGATE_D00_TZIC,
233 }, {
234 .name = "cf-ata",
235 .id = -1,
236 .parent = &clk_hd0,
237 .enable = s5pc100_clk_d00_ctrl,
238 .ctrlbit = S5PC100_CLKGATE_D00_CFCON,
239 }, {
240 .name = "mdma",
241 .id = -1,
242 .parent = &clk_hd0,
243 .enable = s5pc100_clk_d00_ctrl,
244 .ctrlbit = S5PC100_CLKGATE_D00_MDMA,
245 }, {
246 .name = "g2d",
247 .id = -1,
248 .parent = &clk_hd0,
249 .enable = s5pc100_clk_d00_ctrl,
250 .ctrlbit = S5PC100_CLKGATE_D00_G2D,
251 }, {
252 .name = "secss",
253 .id = -1,
254 .parent = &clk_hd0,
255 .enable = s5pc100_clk_d00_ctrl,
256 .ctrlbit = S5PC100_CLKGATE_D00_SECSS,
257 }, {
258 .name = "cssys",
259 .id = -1,
260 .parent = &clk_hd0,
261 .enable = s5pc100_clk_d00_ctrl,
262 .ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
263 },
264
265 /* Memory (D0_1) devices */
266 {
267 .name = "dmc",
268 .id = -1,
269 .parent = &clk_hd0,
270 .enable = s5pc100_clk_d01_ctrl,
271 .ctrlbit = S5PC100_CLKGATE_D01_DMC,
272 }, {
273 .name = "sromc",
274 .id = -1,
275 .parent = &clk_hd0,
276 .enable = s5pc100_clk_d01_ctrl,
277 .ctrlbit = S5PC100_CLKGATE_D01_SROMC,
278 }, {
279 .name = "onenand",
280 .id = -1,
281 .parent = &clk_hd0,
282 .enable = s5pc100_clk_d01_ctrl,
283 .ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
284 }, {
285 .name = "nand",
286 .id = -1,
287 .parent = &clk_hd0,
288 .enable = s5pc100_clk_d01_ctrl,
289 .ctrlbit = S5PC100_CLKGATE_D01_NFCON,
290 }, {
291 .name = "intmem",
292 .id = -1,
293 .parent = &clk_hd0,
294 .enable = s5pc100_clk_d01_ctrl,
295 .ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
296 }, {
297 .name = "ebi",
298 .id = -1,
299 .parent = &clk_hd0,
300 .enable = s5pc100_clk_d01_ctrl,
301 .ctrlbit = S5PC100_CLKGATE_D01_EBI,
302 },
303
304 /* System2 (D0_2) devices */
305 {
306 .name = "seckey",
307 .id = -1,
308 .parent = &clk_pd0,
309 .enable = s5pc100_clk_d02_ctrl,
310 .ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
311 }, {
312 .name = "sdm",
313 .id = -1,
314 .parent = &clk_hd0,
315 .enable = s5pc100_clk_d02_ctrl,
316 .ctrlbit = S5PC100_CLKGATE_D02_SDM,
317 },
318
319 /* File (D1_0) devices */
320 {
321 .name = "pdma",
322 .id = 0,
323 .parent = &clk_h,
324 .enable = s5pc100_clk_d10_ctrl,
325 .ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
326 }, {
327 .name = "pdma",
328 .id = 1,
329 .parent = &clk_h,
330 .enable = s5pc100_clk_d10_ctrl,
331 .ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
332 }, {
333 .name = "usb-host",
334 .id = -1,
335 .parent = &clk_h,
336 .enable = s5pc100_clk_d10_ctrl,
337 .ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
338 }, {
339 .name = "otg",
340 .id = -1,
341 .parent = &clk_h,
342 .enable = s5pc100_clk_d10_ctrl,
343 .ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
344 }, {
345 .name = "modem",
346 .id = -1,
347 .parent = &clk_h,
348 .enable = s5pc100_clk_d10_ctrl,
349 .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
350 }, {
351 .name = "hsmmc",
352 .id = 0,
353 .parent = &clk_48m,
354 .enable = s5pc100_clk_d10_ctrl,
355 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
356 }, {
357 .name = "hsmmc",
358 .id = 1,
359 .parent = &clk_48m,
360 .enable = s5pc100_clk_d10_ctrl,
361 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
362 }, {
363 .name = "hsmmc",
364 .id = 2,
365 .parent = &clk_48m,
366 .enable = s5pc100_clk_d10_ctrl,
367 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
368 },
369
370 /* Multimedia1 (D1_1) devices */
371 {
372 .name = "lcd",
373 .id = -1,
374 .parent = &clk_p,
375 .enable = s5pc100_clk_d11_ctrl,
376 .ctrlbit = S5PC100_CLKGATE_D11_LCD,
377 }, {
378 .name = "rotator",
379 .id = -1,
380 .parent = &clk_p,
381 .enable = s5pc100_clk_d11_ctrl,
382 .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
383 }, {
384 .name = "fimc",
385 .id = -1,
386 .parent = &clk_p,
387 .enable = s5pc100_clk_d11_ctrl,
388 .ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
389 }, {
390 .name = "fimc",
391 .id = -1,
392 .parent = &clk_p,
393 .enable = s5pc100_clk_d11_ctrl,
394 .ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
395 }, {
396 .name = "fimc",
397 .id = -1,
398 .parent = &clk_p,
399 .enable = s5pc100_clk_d11_ctrl,
400 .ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
401 }, {
402 .name = "jpeg",
403 .id = -1,
404 .parent = &clk_p,
405 .enable = s5pc100_clk_d11_ctrl,
406 .ctrlbit = S5PC100_CLKGATE_D11_JPEG,
407 }, {
408 .name = "g3d",
409 .id = -1,
410 .parent = &clk_p,
411 .enable = s5pc100_clk_d11_ctrl,
412 .ctrlbit = S5PC100_CLKGATE_D11_G3D,
413 },
414
415 /* Multimedia2 (D1_2) devices */
416 {
417 .name = "tv",
418 .id = -1,
419 .parent = &clk_p,
420 .enable = s5pc100_clk_d12_ctrl,
421 .ctrlbit = S5PC100_CLKGATE_D12_TV,
422 }, {
423 .name = "vp",
424 .id = -1,
425 .parent = &clk_p,
426 .enable = s5pc100_clk_d12_ctrl,
427 .ctrlbit = S5PC100_CLKGATE_D12_VP,
428 }, {
429 .name = "mixer",
430 .id = -1,
431 .parent = &clk_p,
432 .enable = s5pc100_clk_d12_ctrl,
433 .ctrlbit = S5PC100_CLKGATE_D12_MIXER,
434 }, {
435 .name = "hdmi",
436 .id = -1,
437 .parent = &clk_p,
438 .enable = s5pc100_clk_d12_ctrl,
439 .ctrlbit = S5PC100_CLKGATE_D12_HDMI,
440 }, {
441 .name = "mfc",
442 .id = -1,
443 .parent = &clk_p,
444 .enable = s5pc100_clk_d12_ctrl,
445 .ctrlbit = S5PC100_CLKGATE_D12_MFC,
446 },
447
448 /* System (D1_3) devices */
449 {
450 .name = "chipid",
451 .id = -1,
452 .parent = &clk_p,
453 .enable = s5pc100_clk_d13_ctrl,
454 .ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
455 }, {
456 .name = "gpio",
457 .id = -1,
458 .parent = &clk_p,
459 .enable = s5pc100_clk_d13_ctrl,
460 .ctrlbit = S5PC100_CLKGATE_D13_GPIO,
461 }, {
462 .name = "apc",
463 .id = -1,
464 .parent = &clk_p,
465 .enable = s5pc100_clk_d13_ctrl,
466 .ctrlbit = S5PC100_CLKGATE_D13_APC,
467 }, {
468 .name = "iec",
469 .id = -1,
470 .parent = &clk_p,
471 .enable = s5pc100_clk_d13_ctrl,
472 .ctrlbit = S5PC100_CLKGATE_D13_IEC,
473 }, {
474 .name = "timers",
475 .id = -1,
476 .parent = &clk_p,
477 .enable = s5pc100_clk_d13_ctrl,
478 .ctrlbit = S5PC100_CLKGATE_D13_PWM,
479 }, {
480 .name = "systimer",
481 .id = -1,
482 .parent = &clk_p,
483 .enable = s5pc100_clk_d13_ctrl,
484 .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
485 }, {
486 .name = "watchdog",
487 .id = -1,
488 .parent = &clk_p,
489 .enable = s5pc100_clk_d13_ctrl,
490 .ctrlbit = S5PC100_CLKGATE_D13_WDT,
491 }, {
492 .name = "rtc",
493 .id = -1,
494 .parent = &clk_p,
495 .enable = s5pc100_clk_d13_ctrl,
496 .ctrlbit = S5PC100_CLKGATE_D13_RTC,
497 },
498
499 /* Connectivity (D1_4) devices */
500 {
501 .name = "uart",
502 .id = 0,
503 .parent = &clk_p,
504 .enable = s5pc100_clk_d14_ctrl,
505 .ctrlbit = S5PC100_CLKGATE_D14_UART0,
506 }, {
507 .name = "uart",
508 .id = 1,
509 .parent = &clk_p,
510 .enable = s5pc100_clk_d14_ctrl,
511 .ctrlbit = S5PC100_CLKGATE_D14_UART1,
512 }, {
513 .name = "uart",
514 .id = 2,
515 .parent = &clk_p,
516 .enable = s5pc100_clk_d14_ctrl,
517 .ctrlbit = S5PC100_CLKGATE_D14_UART2,
518 }, {
519 .name = "uart",
520 .id = 3,
521 .parent = &clk_p,
522 .enable = s5pc100_clk_d14_ctrl,
523 .ctrlbit = S5PC100_CLKGATE_D14_UART3,
524 }, {
525 .name = "i2c",
526 .id = -1,
527 .parent = &clk_p,
528 .enable = s5pc100_clk_d14_ctrl,
529 .ctrlbit = S5PC100_CLKGATE_D14_IIC,
530 }, {
531 .name = "hdmi-i2c",
532 .id = -1,
533 .parent = &clk_p,
534 .enable = s5pc100_clk_d14_ctrl,
535 .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
536 }, {
537 .name = "spi",
538 .id = 0,
539 .parent = &clk_p,
540 .enable = s5pc100_clk_d14_ctrl,
541 .ctrlbit = S5PC100_CLKGATE_D14_SPI0,
542 }, {
543 .name = "spi",
544 .id = 1,
545 .parent = &clk_p,
546 .enable = s5pc100_clk_d14_ctrl,
547 .ctrlbit = S5PC100_CLKGATE_D14_SPI1,
548 }, {
549 .name = "spi",
550 .id = 2,
551 .parent = &clk_p,
552 .enable = s5pc100_clk_d14_ctrl,
553 .ctrlbit = S5PC100_CLKGATE_D14_SPI2,
554 }, {
555 .name = "irda",
556 .id = -1,
557 .parent = &clk_p,
558 .enable = s5pc100_clk_d14_ctrl,
559 .ctrlbit = S5PC100_CLKGATE_D14_IRDA,
560 }, {
561 .name = "hsitx",
562 .id = -1,
563 .parent = &clk_p,
564 .enable = s5pc100_clk_d14_ctrl,
565 .ctrlbit = S5PC100_CLKGATE_D14_HSITX,
566 }, {
567 .name = "hsirx",
568 .id = -1,
569 .parent = &clk_p,
570 .enable = s5pc100_clk_d14_ctrl,
571 .ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
572 },
573
574 /* Audio (D1_5) devices */
575 {
576 .name = "iis",
577 .id = 0,
578 .parent = &clk_p,
579 .enable = s5pc100_clk_d15_ctrl,
580 .ctrlbit = S5PC100_CLKGATE_D15_IIS0,
581 }, {
582 .name = "iis",
583 .id = 1,
584 .parent = &clk_p,
585 .enable = s5pc100_clk_d15_ctrl,
586 .ctrlbit = S5PC100_CLKGATE_D15_IIS1,
587 }, {
588 .name = "iis",
589 .id = 2,
590 .parent = &clk_p,
591 .enable = s5pc100_clk_d15_ctrl,
592 .ctrlbit = S5PC100_CLKGATE_D15_IIS2,
593 }, {
594 .name = "ac97",
595 .id = -1,
596 .parent = &clk_p,
597 .enable = s5pc100_clk_d15_ctrl,
598 .ctrlbit = S5PC100_CLKGATE_D15_AC97,
599 }, {
600 .name = "pcm",
601 .id = 0,
602 .parent = &clk_p,
603 .enable = s5pc100_clk_d15_ctrl,
604 .ctrlbit = S5PC100_CLKGATE_D15_PCM0,
605 }, {
606 .name = "pcm",
607 .id = 1,
608 .parent = &clk_p,
609 .enable = s5pc100_clk_d15_ctrl,
610 .ctrlbit = S5PC100_CLKGATE_D15_PCM1,
611 }, {
612 .name = "spdif",
613 .id = -1,
614 .parent = &clk_p,
615 .enable = s5pc100_clk_d15_ctrl,
616 .ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
617 }, {
618 .name = "adc",
619 .id = -1,
620 .parent = &clk_p,
621 .enable = s5pc100_clk_d15_ctrl,
622 .ctrlbit = S5PC100_CLKGATE_D15_TSADC,
623 }, {
624 .name = "cg",
625 .id = -1,
626 .parent = &clk_p,
627 .enable = s5pc100_clk_d15_ctrl,
628 .ctrlbit = S5PC100_CLKGATE_D15_CG,
629 },
630
631 /* Audio (D2_0) devices: all disabled */
632
633 /* Special Clocks 0 */
634 {
635 .name = "sclk_hpm",
636 .id = -1,
637 .parent = NULL,
638 .enable = s5pc100_sclk0_ctrl,
639 .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM,
640 }, {
641 .name = "sclk_onenand",
642 .id = -1,
643 .parent = NULL,
644 .enable = s5pc100_sclk0_ctrl,
645 .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
646 }, {
647 .name = "spi_48",
648 .id = 0,
649 .parent = &clk_48m,
650 .enable = s5pc100_sclk0_ctrl,
651 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
652 }, {
653 .name = "spi_48",
654 .id = 1,
655 .parent = &clk_48m,
656 .enable = s5pc100_sclk0_ctrl,
657 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
658 }, {
659 .name = "spi_48",
660 .id = 2,
661 .parent = &clk_48m,
662 .enable = s5pc100_sclk0_ctrl,
663 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
664 }, {
665 .name = "mmc_48",
666 .id = 0,
667 .parent = &clk_48m,
668 .enable = s5pc100_sclk0_ctrl,
669 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
670 }, {
671 .name = "mmc_48",
672 .id = 1,
673 .parent = &clk_48m,
674 .enable = s5pc100_sclk0_ctrl,
675 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
676 }, {
677 .name = "mmc_48",
678 .id = 2,
679 .parent = &clk_48m,
680 .enable = s5pc100_sclk0_ctrl,
681 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
682 },
683 /* Special Clocks 1 */
684};
685
686static struct clk *clks[] __initdata = {
687 &clk_ext,
688 &clk_epll,
689 &clk_27m,
690 &clk_48m,
691 &clk_54m,
692};
693
694void __init s5pc1xx_register_clocks(void)
695{
696 struct clk *clkp;
697 int ret;
698 int ptr;
699 int size;
700
701 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
702
703 clkp = s5pc100_init_clocks;
704 size = ARRAY_SIZE(s5pc100_init_clocks);
705
706 for (ptr = 0; ptr < size; ptr++, clkp++) {
707 ret = s3c24xx_register_clock(clkp);
708 if (ret < 0) {
709 printk(KERN_ERR "Failed to register clock %s (%d)\n",
710 clkp->name, ret);
711 }
712 }
713
714 clkp = s5pc100_init_clocks_disable;
715 size = ARRAY_SIZE(s5pc100_init_clocks_disable);
716
717 for (ptr = 0; ptr < size; ptr++, clkp++) {
718 ret = s3c24xx_register_clock(clkp);
719 if (ret < 0) {
720 printk(KERN_ERR "Failed to register clock %s (%d)\n",
721 clkp->name, ret);
722 }
723
724 (clkp->enable)(clkp, 0);
725 }
726
727 s3c_pwmclk_init();
728}
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c
index 715a7330794d..e8f347218ecb 100644
--- a/arch/arm/plat-s5pc1xx/cpu.c
+++ b/arch/arm/plat-s5pc1xx/cpu.c
@@ -55,6 +55,11 @@ static struct cpu_table cpu_ids[] __initdata = {
55 55
56static struct map_desc s5pc1xx_iodesc[] __initdata = { 56static struct map_desc s5pc1xx_iodesc[] __initdata = {
57 { 57 {
58 .virtual = (unsigned long)S5PC1XX_VA_CLK_OTHER,
59 .pfn = __phys_to_pfn(S5PC1XX_PA_CLK_OTHER),
60 .length = SZ_4K,
61 .type = MT_DEVICE,
62 }, {
58 .virtual = (unsigned long)S5PC1XX_VA_CHIPID, 63 .virtual = (unsigned long)S5PC1XX_VA_CHIPID,
59 .pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID), 64 .pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID),
60 .length = SZ_16, 65 .length = SZ_16,
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
index 45e275131665..2531f34a56f3 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
@@ -35,10 +35,9 @@ extern struct clk clk_hpll;
35extern struct clk clk_hd0; 35extern struct clk clk_hd0;
36extern struct clk clk_pd0; 36extern struct clk clk_pd0;
37extern struct clk clk_54m; 37extern struct clk clk_54m;
38extern struct clk clk_dout_mpll2;
39extern void s5pc1xx_register_clocks(void); 38extern void s5pc1xx_register_clocks(void);
40extern int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable); 39extern int s5pc100_sclk0_ctrl(struct clk *clk, int enable);
41extern int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable); 40extern int s5pc100_sclk1_ctrl(struct clk *clk, int enable);
42 41
43/* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */ 42/* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */
44extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[]; 43extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
index efc868b4c2a6..b436d44510c8 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
@@ -49,6 +49,7 @@ static struct clk clk_ext_xtal_mux = {
49#define clk_fin_hpll clk_ext_xtal_mux 49#define clk_fin_hpll clk_ext_xtal_mux
50 50
51#define clk_fout_mpll clk_mpll 51#define clk_fout_mpll clk_mpll
52#define clk_vclk_54m clk_54m
52 53
53struct clk_sources { 54struct clk_sources {
54 unsigned int nr_sources; 55 unsigned int nr_sources;
@@ -67,746 +68,327 @@ struct clksrc_clk {
67 void __iomem *reg_source; 68 void __iomem *reg_source;
68}; 69};
69 70
70static int clk_default_setrate(struct clk *clk, unsigned long rate) 71/* APLL */
71{ 72static struct clk clk_fout_apll = {
72 clk->rate = rate; 73 .name = "fout_apll",
73 return 1;
74}
75
76struct clk clk_27m = {
77 .name = "clk_27m",
78 .id = -1, 74 .id = -1,
79 .rate = 27000000, 75 .rate = 27000000,
80}; 76};
81 77
82static int clk_48m_ctrl(struct clk *clk, int enable) 78static struct clk *clk_src_apll_list[] = {
83{ 79 [0] = &clk_fin_apll,
84 unsigned long flags; 80 [1] = &clk_fout_apll,
85 u32 val; 81};
86 82
87 /* can't rely on clock lock, this register has other usages */ 83static struct clk_sources clk_src_apll = {
88 local_irq_save(flags); 84 .sources = clk_src_apll_list,
85 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
86};
89 87
90 val = __raw_readl(S5PC100_CLKSRC1); 88static struct clksrc_clk clk_mout_apll = {
91 if (enable) 89 .clk = {
92 val |= S5PC100_CLKSRC1_CLK48M_MASK; 90 .name = "mout_apll",
93 else 91 .id = -1,
94 val &= ~S5PC100_CLKSRC1_CLK48M_MASK; 92 },
93 .shift = S5PC100_CLKSRC0_APLL_SHIFT,
94 .mask = S5PC100_CLKSRC0_APLL_MASK,
95 .sources = &clk_src_apll,
96 .reg_source = S5PC100_CLKSRC0,
97};
95 98
96 __raw_writel(val, S5PC100_CLKSRC1); 99static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk)
97 local_irq_restore(flags); 100{
101 unsigned long rate = clk_get_rate(clk->parent);
102 unsigned int ratio;
98 103
99 return 0; 104 ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_APLL_MASK;
100} 105 ratio >>= S5PC100_CLKDIV0_APLL_SHIFT;
101 106
102struct clk clk_48m = { 107 return rate / (ratio + 1);
103 .name = "clk_48m", 108}
104 .id = -1,
105 .rate = 48000000,
106 .enable = clk_48m_ctrl,
107};
108 109
109struct clk clk_54m = { 110static struct clk clk_dout_apll = {
110 .name = "clk_54m", 111 .name = "dout_apll",
111 .id = -1, 112 .id = -1,
112 .rate = 54000000, 113 .parent = &clk_mout_apll.clk,
114 .get_rate = s5pc100_clk_dout_apll_get_rate,
113}; 115};
114 116
115struct clk clk_hpll = { 117static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk)
116 .name = "hpll", 118{
117 .id = -1, 119 unsigned long rate = clk_get_rate(clk->parent);
118}; 120 unsigned int ratio;
119 121
120struct clk clk_hd0 = { 122 ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_ARM_MASK;
121 .name = "hclkd0", 123 ratio >>= S5PC100_CLKDIV0_ARM_SHIFT;
122 .id = -1,
123 .rate = 0,
124 .parent = NULL,
125 .ctrlbit = 0,
126 .set_rate = clk_default_setrate,
127};
128 124
129struct clk clk_pd0 = { 125 return rate / (ratio + 1);
130 .name = "pclkd0", 126}
131 .id = -1,
132 .rate = 0,
133 .parent = NULL,
134 .ctrlbit = 0,
135 .set_rate = clk_default_setrate,
136};
137 127
138static int s5pc1xx_clk_gate(void __iomem *reg, 128static unsigned long s5pc100_clk_arm_round_rate(struct clk *clk,
139 struct clk *clk, 129 unsigned long rate)
140 int enable)
141{ 130{
142 unsigned int ctrlbit = clk->ctrlbit; 131 unsigned long parent = clk_get_rate(clk->parent);
143 u32 con; 132 u32 div;
144 133
145 con = __raw_readl(reg); 134 if (parent < rate)
135 return rate;
146 136
147 if (enable) 137 div = (parent / rate) - 1;
148 con |= ctrlbit; 138 if (div > S5PC100_CLKDIV0_ARM_MASK)
149 else 139 div = S5PC100_CLKDIV0_ARM_MASK;
150 con &= ~ctrlbit;
151 140
152 __raw_writel(con, reg); 141 return parent / (div + 1);
153 return 0;
154} 142}
155 143
156static int s5pc1xx_clk_d00_ctrl(struct clk *clk, int enable) 144static int s5pc100_clk_arm_set_rate(struct clk *clk, unsigned long rate)
157{ 145{
158 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable); 146 unsigned long parent = clk_get_rate(clk->parent);
159} 147 u32 div;
148 u32 val;
160 149
161static int s5pc1xx_clk_d01_ctrl(struct clk *clk, int enable) 150 if (rate < parent / (S5PC100_CLKDIV0_ARM_MASK + 1))
162{ 151 return -EINVAL;
163 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
164}
165 152
166static int s5pc1xx_clk_d02_ctrl(struct clk *clk, int enable) 153 rate = clk_round_rate(clk, rate);
167{ 154 div = clk_get_rate(clk->parent) / rate;
168 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
169}
170 155
171static int s5pc1xx_clk_d10_ctrl(struct clk *clk, int enable) 156 val = __raw_readl(S5PC100_CLKDIV0);
172{ 157 val &= S5PC100_CLKDIV0_ARM_MASK;
173 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable); 158 val |= (div - 1);
174} 159 __raw_writel(val, S5PC100_CLKDIV0);
175 160
176static int s5pc1xx_clk_d11_ctrl(struct clk *clk, int enable) 161 return 0;
177{
178 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
179} 162}
180 163
181static int s5pc1xx_clk_d12_ctrl(struct clk *clk, int enable) 164static struct clk clk_arm = {
182{ 165 .name = "armclk",
183 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable); 166 .id = -1,
184} 167 .parent = &clk_dout_apll,
168 .get_rate = s5pc100_clk_arm_get_rate,
169 .set_rate = s5pc100_clk_arm_set_rate,
170 .round_rate = s5pc100_clk_arm_round_rate,
171};
185 172
186static int s5pc1xx_clk_d13_ctrl(struct clk *clk, int enable) 173static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk)
187{ 174{
188 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable); 175 unsigned long rate = clk_get_rate(clk->parent);
189} 176 unsigned int ratio;
190 177
191static int s5pc1xx_clk_d14_ctrl(struct clk *clk, int enable) 178 ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_D0_MASK;
192{ 179 ratio >>= S5PC100_CLKDIV0_D0_SHIFT;
193 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
194}
195 180
196static int s5pc1xx_clk_d15_ctrl(struct clk *clk, int enable) 181 return rate / (ratio + 1);
197{
198 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
199} 182}
200 183
201static int s5pc1xx_clk_d20_ctrl(struct clk *clk, int enable) 184static struct clk clk_dout_d0_bus = {
202{ 185 .name = "dout_d0_bus",
203 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable); 186 .id = -1,
204} 187 .parent = &clk_arm,
188 .get_rate = s5pc100_clk_dout_d0_bus_get_rate,
189};
205 190
206int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable) 191static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk)
207{ 192{
208 return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable); 193 unsigned long rate = clk_get_rate(clk->parent);
194 unsigned int ratio;
195
196 ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_PCLKD0_MASK;
197 ratio >>= S5PC100_CLKDIV0_PCLKD0_SHIFT;
198
199 return rate / (ratio + 1);
209} 200}
210 201
211int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable) 202static struct clk clk_dout_pclkd0 = {
203 .name = "dout_pclkd0",
204 .id = -1,
205 .parent = &clk_dout_d0_bus,
206 .get_rate = s5pc100_clk_dout_pclkd0_get_rate,
207};
208
209static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk)
212{ 210{
213 return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable); 211 unsigned long rate = clk_get_rate(clk->parent);
212 unsigned int ratio;
213
214 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_APLL2_MASK;
215 ratio >>= S5PC100_CLKDIV1_APLL2_SHIFT;
216
217 return rate / (ratio + 1);
214} 218}
215 219
216static struct clk init_clocks_disable[] = { 220static struct clk clk_dout_apll2 = {
217 { 221 .name = "dout_apll2",
218 .name = "dsi", 222 .id = -1,
219 .id = -1, 223 .parent = &clk_mout_apll.clk,
220 .parent = &clk_p, 224 .get_rate = s5pc100_clk_dout_apll2_get_rate,
221 .enable = s5pc1xx_clk_d11_ctrl,
222 .ctrlbit = S5PC100_CLKGATE_D11_DSI,
223 }, {
224 .name = "csi",
225 .id = -1,
226 .parent = &clk_h,
227 .enable = s5pc1xx_clk_d11_ctrl,
228 .ctrlbit = S5PC100_CLKGATE_D11_CSI,
229 }, {
230 .name = "ccan0",
231 .id = 0,
232 .parent = &clk_p,
233 .enable = s5pc1xx_clk_d14_ctrl,
234 .ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
235 }, {
236 .name = "ccan1",
237 .id = 1,
238 .parent = &clk_p,
239 .enable = s5pc1xx_clk_d14_ctrl,
240 .ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
241 }, {
242 .name = "keypad",
243 .id = -1,
244 .parent = &clk_p,
245 .enable = s5pc1xx_clk_d15_ctrl,
246 .ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
247 }, {
248 .name = "hclkd2",
249 .id = -1,
250 .parent = NULL,
251 .enable = s5pc1xx_clk_d20_ctrl,
252 .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
253 }, {
254 .name = "iis-d2",
255 .id = -1,
256 .parent = NULL,
257 .enable = s5pc1xx_clk_d20_ctrl,
258 .ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
259 }, {
260 .name = "otg",
261 .id = -1,
262 .parent = &clk_h,
263 .enable = s5pc1xx_clk_d10_ctrl,
264 .ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
265 },
266}; 225};
267 226
268static struct clk init_clocks[] = { 227/* MPLL */
269 /* System1 (D0_0) devices */ 228static struct clk *clk_src_mpll_list[] = {
270 { 229 [0] = &clk_fin_mpll,
271 .name = "intc", 230 [1] = &clk_fout_mpll,
272 .id = -1, 231};
273 .parent = &clk_hd0,
274 .enable = s5pc1xx_clk_d00_ctrl,
275 .ctrlbit = S5PC100_CLKGATE_D00_INTC,
276 }, {
277 .name = "tzic",
278 .id = -1,
279 .parent = &clk_hd0,
280 .enable = s5pc1xx_clk_d00_ctrl,
281 .ctrlbit = S5PC100_CLKGATE_D00_TZIC,
282 }, {
283 .name = "cf-ata",
284 .id = -1,
285 .parent = &clk_hd0,
286 .enable = s5pc1xx_clk_d00_ctrl,
287 .ctrlbit = S5PC100_CLKGATE_D00_CFCON,
288 }, {
289 .name = "mdma",
290 .id = -1,
291 .parent = &clk_hd0,
292 .enable = s5pc1xx_clk_d00_ctrl,
293 .ctrlbit = S5PC100_CLKGATE_D00_MDMA,
294 }, {
295 .name = "g2d",
296 .id = -1,
297 .parent = &clk_hd0,
298 .enable = s5pc1xx_clk_d00_ctrl,
299 .ctrlbit = S5PC100_CLKGATE_D00_G2D,
300 }, {
301 .name = "secss",
302 .id = -1,
303 .parent = &clk_hd0,
304 .enable = s5pc1xx_clk_d00_ctrl,
305 .ctrlbit = S5PC100_CLKGATE_D00_SECSS,
306 }, {
307 .name = "cssys",
308 .id = -1,
309 .parent = &clk_hd0,
310 .enable = s5pc1xx_clk_d00_ctrl,
311 .ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
312 },
313 232
314 /* Memory (D0_1) devices */ 233static struct clk_sources clk_src_mpll = {
315 { 234 .sources = clk_src_mpll_list,
316 .name = "dmc", 235 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
317 .id = -1, 236};
318 .parent = &clk_hd0,
319 .enable = s5pc1xx_clk_d01_ctrl,
320 .ctrlbit = S5PC100_CLKGATE_D01_DMC,
321 }, {
322 .name = "sromc",
323 .id = -1,
324 .parent = &clk_hd0,
325 .enable = s5pc1xx_clk_d01_ctrl,
326 .ctrlbit = S5PC100_CLKGATE_D01_SROMC,
327 }, {
328 .name = "onenand",
329 .id = -1,
330 .parent = &clk_hd0,
331 .enable = s5pc1xx_clk_d01_ctrl,
332 .ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
333 }, {
334 .name = "nand",
335 .id = -1,
336 .parent = &clk_hd0,
337 .enable = s5pc1xx_clk_d01_ctrl,
338 .ctrlbit = S5PC100_CLKGATE_D01_NFCON,
339 }, {
340 .name = "intmem",
341 .id = -1,
342 .parent = &clk_hd0,
343 .enable = s5pc1xx_clk_d01_ctrl,
344 .ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
345 }, {
346 .name = "ebi",
347 .id = -1,
348 .parent = &clk_hd0,
349 .enable = s5pc1xx_clk_d01_ctrl,
350 .ctrlbit = S5PC100_CLKGATE_D01_EBI,
351 },
352 237
353 /* System2 (D0_2) devices */ 238static struct clksrc_clk clk_mout_mpll = {
354 { 239 .clk = {
355 .name = "seckey", 240 .name = "mout_mpll",
356 .id = -1,
357 .parent = &clk_pd0,
358 .enable = s5pc1xx_clk_d02_ctrl,
359 .ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
360 }, {
361 .name = "sdm",
362 .id = -1, 241 .id = -1,
363 .parent = &clk_hd0,
364 .enable = s5pc1xx_clk_d02_ctrl,
365 .ctrlbit = S5PC100_CLKGATE_D02_SDM,
366 }, 242 },
243 .shift = S5PC100_CLKSRC0_MPLL_SHIFT,
244 .mask = S5PC100_CLKSRC0_MPLL_MASK,
245 .sources = &clk_src_mpll,
246 .reg_source = S5PC100_CLKSRC0,
247};
367 248
368 /* File (D1_0) devices */ 249static struct clk *clkset_am_list[] = {
369 { 250 [0] = &clk_mout_mpll.clk,
370 .name = "pdma0", 251 [1] = &clk_dout_apll2,
371 .id = -1, 252};
372 .parent = &clk_h,
373 .enable = s5pc1xx_clk_d10_ctrl,
374 .ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
375 }, {
376 .name = "pdma1",
377 .id = -1,
378 .parent = &clk_h,
379 .enable = s5pc1xx_clk_d10_ctrl,
380 .ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
381 }, {
382 .name = "usb-host",
383 .id = -1,
384 .parent = &clk_h,
385 .enable = s5pc1xx_clk_d10_ctrl,
386 .ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
387 }, {
388 .name = "modem",
389 .id = -1,
390 .parent = &clk_h,
391 .enable = s5pc1xx_clk_d10_ctrl,
392 .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
393 }, {
394 .name = "hsmmc",
395 .id = 0,
396 .parent = &clk_h,
397 .enable = s5pc1xx_clk_d10_ctrl,
398 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
399 }, {
400 .name = "hsmmc",
401 .id = 1,
402 .parent = &clk_h,
403 .enable = s5pc1xx_clk_d10_ctrl,
404 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
405 }, {
406 .name = "hsmmc",
407 .id = 2,
408 .parent = &clk_h,
409 .enable = s5pc1xx_clk_d10_ctrl,
410 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
411 },
412 253
413 /* Multimedia1 (D1_1) devices */ 254static struct clk_sources clk_src_am = {
414 { 255 .sources = clkset_am_list,
415 .name = "lcd", 256 .nr_sources = ARRAY_SIZE(clkset_am_list),
416 .id = -1, 257};
417 .parent = &clk_h,
418 .enable = s5pc1xx_clk_d11_ctrl,
419 .ctrlbit = S5PC100_CLKGATE_D11_LCD,
420 }, {
421 .name = "rotator",
422 .id = -1,
423 .parent = &clk_h,
424 .enable = s5pc1xx_clk_d11_ctrl,
425 .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
426 }, {
427 .name = "fimc",
428 .id = 0,
429 .parent = &clk_h,
430 .enable = s5pc1xx_clk_d11_ctrl,
431 .ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
432 }, {
433 .name = "fimc",
434 .id = 1,
435 .parent = &clk_h,
436 .enable = s5pc1xx_clk_d11_ctrl,
437 .ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
438 }, {
439 .name = "fimc",
440 .id = 2,
441 .parent = &clk_h,
442 .enable = s5pc1xx_clk_d11_ctrl,
443 .ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
444 }, {
445 .name = "jpeg",
446 .id = -1,
447 .parent = &clk_h,
448 .enable = s5pc1xx_clk_d11_ctrl,
449 .ctrlbit = S5PC100_CLKGATE_D11_JPEG,
450 }, {
451 .name = "g3d",
452 .id = -1,
453 .parent = &clk_h,
454 .enable = s5pc1xx_clk_d11_ctrl,
455 .ctrlbit = S5PC100_CLKGATE_D11_G3D,
456 },
457 258
458 /* Multimedia2 (D1_2) devices */ 259static struct clksrc_clk clk_mout_am = {
459 { 260 .clk = {
460 .name = "tv", 261 .name = "mout_am",
461 .id = -1,
462 .parent = &clk_h,
463 .enable = s5pc1xx_clk_d12_ctrl,
464 .ctrlbit = S5PC100_CLKGATE_D12_TV,
465 }, {
466 .name = "vp",
467 .id = -1,
468 .parent = &clk_h,
469 .enable = s5pc1xx_clk_d12_ctrl,
470 .ctrlbit = S5PC100_CLKGATE_D12_VP,
471 }, {
472 .name = "mixer",
473 .id = -1,
474 .parent = &clk_h,
475 .enable = s5pc1xx_clk_d12_ctrl,
476 .ctrlbit = S5PC100_CLKGATE_D12_MIXER,
477 }, {
478 .name = "hdmi",
479 .id = -1,
480 .parent = &clk_h,
481 .enable = s5pc1xx_clk_d12_ctrl,
482 .ctrlbit = S5PC100_CLKGATE_D12_HDMI,
483 }, {
484 .name = "mfc",
485 .id = -1, 262 .id = -1,
486 .parent = &clk_h,
487 .enable = s5pc1xx_clk_d12_ctrl,
488 .ctrlbit = S5PC100_CLKGATE_D12_MFC,
489 }, 263 },
264 .shift = S5PC100_CLKSRC0_AMMUX_SHIFT,
265 .mask = S5PC100_CLKSRC0_AMMUX_MASK,
266 .sources = &clk_src_am,
267 .reg_source = S5PC100_CLKSRC0,
268};
490 269
491 /* System (D1_3) devices */ 270static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk)
492 { 271{
493 .name = "chipid", 272 unsigned long rate = clk_get_rate(clk->parent);
494 .id = -1, 273 unsigned int ratio;
495 .parent = &clk_p,
496 .enable = s5pc1xx_clk_d13_ctrl,
497 .ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
498 }, {
499 .name = "gpio",
500 .id = -1,
501 .parent = &clk_p,
502 .enable = s5pc1xx_clk_d13_ctrl,
503 .ctrlbit = S5PC100_CLKGATE_D13_GPIO,
504 }, {
505 .name = "apc",
506 .id = -1,
507 .parent = &clk_p,
508 .enable = s5pc1xx_clk_d13_ctrl,
509 .ctrlbit = S5PC100_CLKGATE_D13_APC,
510 }, {
511 .name = "iec",
512 .id = -1,
513 .parent = &clk_p,
514 .enable = s5pc1xx_clk_d13_ctrl,
515 .ctrlbit = S5PC100_CLKGATE_D13_IEC,
516 }, {
517 .name = "timers",
518 .id = -1,
519 .parent = &clk_p,
520 .enable = s5pc1xx_clk_d13_ctrl,
521 .ctrlbit = S5PC100_CLKGATE_D13_PWM,
522 }, {
523 .name = "systimer",
524 .id = -1,
525 .parent = &clk_p,
526 .enable = s5pc1xx_clk_d13_ctrl,
527 .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
528 }, {
529 .name = "watchdog",
530 .id = -1,
531 .parent = &clk_p,
532 .enable = s5pc1xx_clk_d13_ctrl,
533 .ctrlbit = S5PC100_CLKGATE_D13_WDT,
534 }, {
535 .name = "rtc",
536 .id = -1,
537 .parent = &clk_p,
538 .enable = s5pc1xx_clk_d13_ctrl,
539 .ctrlbit = S5PC100_CLKGATE_D13_RTC,
540 },
541 274
542 /* Connectivity (D1_4) devices */ 275 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
543 {
544 .name = "uart",
545 .id = 0,
546 .parent = &clk_p,
547 .enable = s5pc1xx_clk_d14_ctrl,
548 .ctrlbit = S5PC100_CLKGATE_D14_UART0,
549 }, {
550 .name = "uart",
551 .id = 1,
552 .parent = &clk_p,
553 .enable = s5pc1xx_clk_d14_ctrl,
554 .ctrlbit = S5PC100_CLKGATE_D14_UART1,
555 }, {
556 .name = "uart",
557 .id = 2,
558 .parent = &clk_p,
559 .enable = s5pc1xx_clk_d14_ctrl,
560 .ctrlbit = S5PC100_CLKGATE_D14_UART2,
561 }, {
562 .name = "uart",
563 .id = 3,
564 .parent = &clk_p,
565 .enable = s5pc1xx_clk_d14_ctrl,
566 .ctrlbit = S5PC100_CLKGATE_D14_UART3,
567 }, {
568 .name = "i2c",
569 .id = -1,
570 .parent = &clk_p,
571 .enable = s5pc1xx_clk_d14_ctrl,
572 .ctrlbit = S5PC100_CLKGATE_D14_IIC,
573 }, {
574 .name = "hdmi-i2c",
575 .id = -1,
576 .parent = &clk_p,
577 .enable = s5pc1xx_clk_d14_ctrl,
578 .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
579 }, {
580 .name = "spi",
581 .id = 0,
582 .parent = &clk_p,
583 .enable = s5pc1xx_clk_d14_ctrl,
584 .ctrlbit = S5PC100_CLKGATE_D14_SPI0,
585 }, {
586 .name = "spi",
587 .id = 1,
588 .parent = &clk_p,
589 .enable = s5pc1xx_clk_d14_ctrl,
590 .ctrlbit = S5PC100_CLKGATE_D14_SPI1,
591 }, {
592 .name = "spi",
593 .id = 2,
594 .parent = &clk_p,
595 .enable = s5pc1xx_clk_d14_ctrl,
596 .ctrlbit = S5PC100_CLKGATE_D14_SPI2,
597 }, {
598 .name = "irda",
599 .id = -1,
600 .parent = &clk_p,
601 .enable = s5pc1xx_clk_d14_ctrl,
602 .ctrlbit = S5PC100_CLKGATE_D14_IRDA,
603 }, {
604 .name = "hsitx",
605 .id = -1,
606 .parent = &clk_p,
607 .enable = s5pc1xx_clk_d14_ctrl,
608 .ctrlbit = S5PC100_CLKGATE_D14_HSITX,
609 }, {
610 .name = "hsirx",
611 .id = -1,
612 .parent = &clk_p,
613 .enable = s5pc1xx_clk_d14_ctrl,
614 .ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
615 },
616 276
617 /* Audio (D1_5) devices */ 277 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_D1_MASK;
618 { 278 ratio >>= S5PC100_CLKDIV1_D1_SHIFT;
619 .name = "iis",
620 .id = 0,
621 .parent = &clk_p,
622 .enable = s5pc1xx_clk_d15_ctrl,
623 .ctrlbit = S5PC100_CLKGATE_D15_IIS0,
624 }, {
625 .name = "iis",
626 .id = 1,
627 .parent = &clk_p,
628 .enable = s5pc1xx_clk_d15_ctrl,
629 .ctrlbit = S5PC100_CLKGATE_D15_IIS1,
630 }, {
631 .name = "iis",
632 .id = 2,
633 .parent = &clk_p,
634 .enable = s5pc1xx_clk_d15_ctrl,
635 .ctrlbit = S5PC100_CLKGATE_D15_IIS2,
636 }, {
637 .name = "ac97",
638 .id = -1,
639 .parent = &clk_p,
640 .enable = s5pc1xx_clk_d15_ctrl,
641 .ctrlbit = S5PC100_CLKGATE_D15_AC97,
642 }, {
643 .name = "pcm",
644 .id = 0,
645 .parent = &clk_p,
646 .enable = s5pc1xx_clk_d15_ctrl,
647 .ctrlbit = S5PC100_CLKGATE_D15_PCM0,
648 }, {
649 .name = "pcm",
650 .id = 1,
651 .parent = &clk_p,
652 .enable = s5pc1xx_clk_d15_ctrl,
653 .ctrlbit = S5PC100_CLKGATE_D15_PCM1,
654 }, {
655 .name = "spdif",
656 .id = -1,
657 .parent = &clk_p,
658 .enable = s5pc1xx_clk_d15_ctrl,
659 .ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
660 }, {
661 .name = "adc",
662 .id = -1,
663 .parent = &clk_p,
664 .enable = s5pc1xx_clk_d15_ctrl,
665 .ctrlbit = S5PC100_CLKGATE_D15_TSADC,
666 }, {
667 .name = "keyif",
668 .id = -1,
669 .parent = &clk_p,
670 .enable = s5pc1xx_clk_d15_ctrl,
671 .ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
672 }, {
673 .name = "cg",
674 .id = -1,
675 .parent = &clk_p,
676 .enable = s5pc1xx_clk_d15_ctrl,
677 .ctrlbit = S5PC100_CLKGATE_D15_CG,
678 },
679 279
680 /* Audio (D2_0) devices: all disabled */ 280 return rate / (ratio + 1);
281}
681 282
682 /* Special Clocks 1 */ 283static struct clk clk_dout_d1_bus = {
683 { 284 .name = "dout_d1_bus",
684 .name = "sclk_hpm", 285 .id = -1,
685 .id = -1, 286 .parent = &clk_mout_am.clk,
686 .parent = NULL, 287 .get_rate = s5pc100_clk_dout_d1_bus_get_rate,
687 .enable = s5pc1xx_sclk0_ctrl, 288};
688 .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM,
689 }, {
690 .name = "sclk_onenand",
691 .id = -1,
692 .parent = NULL,
693 .enable = s5pc1xx_sclk0_ctrl,
694 .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
695 }, {
696 .name = "sclk_spi_48",
697 .id = 0,
698 .parent = &clk_48m,
699 .enable = s5pc1xx_sclk0_ctrl,
700 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
701 }, {
702 .name = "sclk_spi_48",
703 .id = 1,
704 .parent = &clk_48m,
705 .enable = s5pc1xx_sclk0_ctrl,
706 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
707 }, {
708 .name = "sclk_spi_48",
709 .id = 2,
710 .parent = &clk_48m,
711 .enable = s5pc1xx_sclk0_ctrl,
712 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
713 }, {
714 .name = "sclk_mmc_48",
715 .id = 0,
716 .parent = &clk_48m,
717 .enable = s5pc1xx_sclk0_ctrl,
718 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
719 }, {
720 .name = "sclk_mmc_48",
721 .id = 1,
722 .parent = &clk_48m,
723 .enable = s5pc1xx_sclk0_ctrl,
724 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
725 }, {
726 .name = "sclk_mmc_48",
727 .id = 2,
728 .parent = &clk_48m,
729 .enable = s5pc1xx_sclk0_ctrl,
730 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
731 },
732 289
733 /* Special Clocks 2 */ 290static struct clk *clkset_onenand_list[] = {
734 { 291 [0] = &clk_dout_d0_bus,
735 .name = "sclk_tv_54", 292 [1] = &clk_dout_d1_bus,
736 .id = -1, 293};
737 .parent = &clk_54m, 294
738 .enable = s5pc1xx_sclk1_ctrl, 295static struct clk_sources clk_src_onenand = {
739 .ctrlbit = S5PC100_CLKGATE_SCLK1_TV54, 296 .sources = clkset_onenand_list,
740 }, { 297 .nr_sources = ARRAY_SIZE(clkset_onenand_list),
741 .name = "sclk_vdac_54", 298};
742 .id = -1, 299
743 .parent = &clk_54m, 300static struct clksrc_clk clk_mout_onenand = {
744 .enable = s5pc1xx_sclk1_ctrl, 301 .clk = {
745 .ctrlbit = S5PC100_CLKGATE_SCLK1_VDAC54, 302 .name = "mout_onenand",
746 }, {
747 .name = "sclk_spdif",
748 .id = -1, 303 .id = -1,
749 .parent = NULL,
750 .enable = s5pc1xx_sclk1_ctrl,
751 .ctrlbit = S5PC100_CLKGATE_SCLK1_SPDIF,
752 }, 304 },
305 .shift = S5PC100_CLKSRC0_ONENAND_SHIFT,
306 .mask = S5PC100_CLKSRC0_ONENAND_MASK,
307 .sources = &clk_src_onenand,
308 .reg_source = S5PC100_CLKSRC0,
753}; 309};
754 310
755void __init s5pc1xx_register_clocks(void) 311static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk)
756{ 312{
757 struct clk *clkp; 313 unsigned long rate = clk_get_rate(clk->parent);
758 int ret; 314 unsigned int ratio;
759 int ptr;
760 315
761 clkp = init_clocks; 316 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
762 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
763 ret = s3c24xx_register_clock(clkp);
764 if (ret < 0) {
765 printk(KERN_ERR "Failed to register clock %s (%d)\n",
766 clkp->name, ret);
767 }
768 }
769 317
770 clkp = init_clocks_disable; 318 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_PCLKD1_MASK;
771 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { 319 ratio >>= S5PC100_CLKDIV1_PCLKD1_SHIFT;
772 320
773 ret = s3c24xx_register_clock(clkp); 321 return rate / (ratio + 1);
774 if (ret < 0) { 322}
775 printk(KERN_ERR "Failed to register clock %s (%d)\n",
776 clkp->name, ret);
777 }
778 323
779 (clkp->enable)(clkp, 0); 324static struct clk clk_dout_pclkd1 = {
780 } 325 .name = "dout_pclkd1",
326 .id = -1,
327 .parent = &clk_dout_d1_bus,
328 .get_rate = s5pc100_clk_dout_pclkd1_get_rate,
329};
781 330
782 s3c_pwmclk_init(); 331static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk)
332{
333 unsigned long rate = clk_get_rate(clk->parent);
334 unsigned int ratio;
335
336 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
337
338 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
339 ratio >>= S5PC100_CLKDIV1_MPLL2_SHIFT;
340
341 return rate / (ratio + 1);
783} 342}
784static struct clk clk_fout_apll = { 343
785 .name = "fout_apll", 344static struct clk clk_dout_mpll2 = {
345 .name = "dout_mpll2",
786 .id = -1, 346 .id = -1,
347 .parent = &clk_mout_am.clk,
348 .get_rate = s5pc100_clk_dout_mpll2_get_rate,
787}; 349};
788 350
789static struct clk *clk_src_apll_list[] = { 351static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk)
790 [0] = &clk_fin_apll, 352{
791 [1] = &clk_fout_apll, 353 unsigned long rate = clk_get_rate(clk->parent);
792}; 354 unsigned int ratio;
793 355
794static struct clk_sources clk_src_apll = { 356 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
795 .sources = clk_src_apll_list, 357
796 .nr_sources = ARRAY_SIZE(clk_src_apll_list), 358 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_CAM_MASK;
359 ratio >>= S5PC100_CLKDIV1_CAM_SHIFT;
360
361 return rate / (ratio + 1);
362}
363
364static struct clk clk_dout_cam = {
365 .name = "dout_cam",
366 .id = -1,
367 .parent = &clk_dout_mpll2,
368 .get_rate = s5pc100_clk_dout_cam_get_rate,
797}; 369};
798 370
799static struct clksrc_clk clk_mout_apll = { 371static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk)
800 .clk = { 372{
801 .name = "mout_apll", 373 unsigned long rate = clk_get_rate(clk->parent);
802 .id = -1, 374 unsigned int ratio;
803 }, 375
804 .shift = S5PC100_CLKSRC0_APLL_SHIFT, 376 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
805 .mask = S5PC100_CLKSRC0_APLL_MASK, 377
806 .sources = &clk_src_apll, 378 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK;
807 .reg_source = S5PC100_CLKSRC0, 379 ratio >>= S5PC100_CLKDIV1_MPLL_SHIFT;
380
381 return rate / (ratio + 1);
382}
383
384static struct clk clk_dout_mpll = {
385 .name = "dout_mpll",
386 .id = -1,
387 .parent = &clk_mout_am.clk,
388 .get_rate = s5pc100_clk_dout_mpll_get_rate,
808}; 389};
809 390
391/* EPLL */
810static struct clk clk_fout_epll = { 392static struct clk clk_fout_epll = {
811 .name = "fout_epll", 393 .name = "fout_epll",
812 .id = -1, 394 .id = -1,
@@ -833,85 +415,51 @@ static struct clksrc_clk clk_mout_epll = {
833 .reg_source = S5PC100_CLKSRC0, 415 .reg_source = S5PC100_CLKSRC0,
834}; 416};
835 417
836static struct clk *clk_src_mpll_list[] = { 418/* HPLL */
837 [0] = &clk_fin_mpll, 419static struct clk clk_fout_hpll = {
838 [1] = &clk_fout_mpll, 420 .name = "fout_hpll",
421 .id = -1,
839}; 422};
840 423
841static struct clk_sources clk_src_mpll = { 424static struct clk *clk_src_hpll_list[] = {
842 .sources = clk_src_mpll_list, 425 [0] = &clk_27m,
843 .nr_sources = ARRAY_SIZE(clk_src_mpll_list), 426 [1] = &clk_fout_hpll,
844}; 427};
845 428
846static struct clksrc_clk clk_mout_mpll = { 429static struct clk_sources clk_src_hpll = {
847 .clk = { 430 .sources = clk_src_hpll_list,
848 .name = "mout_mpll", 431 .nr_sources = ARRAY_SIZE(clk_src_hpll_list),
432};
433
434static struct clksrc_clk clk_mout_hpll = {
435 .clk = {
436 .name = "mout_hpll",
849 .id = -1, 437 .id = -1,
850 }, 438 },
851 .shift = S5PC100_CLKSRC0_MPLL_SHIFT, 439 .shift = S5PC100_CLKSRC0_HPLL_SHIFT,
852 .mask = S5PC100_CLKSRC0_MPLL_MASK, 440 .mask = S5PC100_CLKSRC0_HPLL_MASK,
853 .sources = &clk_src_mpll, 441 .sources = &clk_src_hpll,
854 .reg_source = S5PC100_CLKSRC0, 442 .reg_source = S5PC100_CLKSRC0,
855}; 443};
856 444
857static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk) 445/* Peripherals */
858{ 446/*
859 unsigned long rate = clk_get_rate(clk->parent); 447 * The peripheral clocks are all controlled via clocksource followed
860 unsigned long clkdiv; 448 * by an optional divider and gate stage. We currently roll this into
861 449 * one clock which hides the intermediate clock from the mux.
862 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); 450 *
863 451 * Note, the JPEG clock can only be an even divider...
864 clkdiv = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK; 452 *
865 rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL_SHIFT) + 1; 453 * The scaler and LCD clocks depend on the S5PC100 version, and also
866 454 * have a common parent divisor so are not included here.
867 return rate; 455 */
868}
869
870static struct clk clk_dout_mpll = {
871 .name = "dout_mpll",
872 .id = -1,
873 .parent = &clk_mout_mpll.clk,
874 .get_rate = s5pc1xx_clk_doutmpll_get_rate,
875};
876
877static unsigned long s5pc1xx_clk_doutmpll2_get_rate(struct clk *clk)
878{
879 unsigned long rate = clk_get_rate(clk->parent);
880 unsigned long clkdiv;
881
882 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
883
884 clkdiv = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
885 rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL2_SHIFT) + 1;
886
887 return rate;
888}
889
890struct clk clk_dout_mpll2 = {
891 .name = "dout_mpll2",
892 .id = -1,
893 .parent = &clk_mout_mpll.clk,
894 .get_rate = s5pc1xx_clk_doutmpll2_get_rate,
895};
896
897static struct clk *clkset_uart_list[] = {
898 &clk_mout_epll.clk,
899 &clk_dout_mpll,
900 NULL,
901 NULL
902};
903
904static struct clk_sources clkset_uart = {
905 .sources = clkset_uart_list,
906 .nr_sources = ARRAY_SIZE(clkset_uart_list),
907};
908 456
909static inline struct clksrc_clk *to_clksrc(struct clk *clk) 457static inline struct clksrc_clk *to_clksrc(struct clk *clk)
910{ 458{
911 return container_of(clk, struct clksrc_clk, clk); 459 return container_of(clk, struct clksrc_clk, clk);
912} 460}
913 461
914static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk) 462static unsigned long s5pc100_getrate_clksrc(struct clk *clk)
915{ 463{
916 struct clksrc_clk *sclk = to_clksrc(clk); 464 struct clksrc_clk *sclk = to_clksrc(clk);
917 unsigned long rate = clk_get_rate(clk->parent); 465 unsigned long rate = clk_get_rate(clk->parent);
@@ -925,7 +473,7 @@ static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk)
925 return rate; 473 return rate;
926} 474}
927 475
928static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate) 476static int s5pc100_setrate_clksrc(struct clk *clk, unsigned long rate)
929{ 477{
930 struct clksrc_clk *sclk = to_clksrc(clk); 478 struct clksrc_clk *sclk = to_clksrc(clk);
931 void __iomem *reg = sclk->reg_divider; 479 void __iomem *reg = sclk->reg_divider;
@@ -938,14 +486,14 @@ static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate)
938 return -EINVAL; 486 return -EINVAL;
939 487
940 val = __raw_readl(reg); 488 val = __raw_readl(reg);
941 val &= ~(0xf << sclk->shift); 489 val &= ~(0xf << sclk->divider_shift);
942 val |= (div - 1) << sclk->shift; 490 val |= (div - 1) << sclk->divider_shift;
943 __raw_writel(val, reg); 491 __raw_writel(val, reg);
944 492
945 return 0; 493 return 0;
946} 494}
947 495
948static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent) 496static int s5pc100_setparent_clksrc(struct clk *clk, struct clk *parent)
949{ 497{
950 struct clksrc_clk *sclk = to_clksrc(clk); 498 struct clksrc_clk *sclk = to_clksrc(clk);
951 struct clk_sources *srcs = sclk->sources; 499 struct clk_sources *srcs = sclk->sources;
@@ -970,7 +518,7 @@ static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent)
970 return -EINVAL; 518 return -EINVAL;
971} 519}
972 520
973static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk, 521static unsigned long s5pc100_roundrate_clksrc(struct clk *clk,
974 unsigned long rate) 522 unsigned long rate)
975{ 523{
976 unsigned long parent_rate = clk_get_rate(clk->parent); 524 unsigned long parent_rate = clk_get_rate(clk->parent);
@@ -992,16 +540,95 @@ static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk,
992 return rate; 540 return rate;
993} 541}
994 542
543static struct clk *clkset_spi_list[] = {
544 &clk_mout_epll.clk,
545 &clk_dout_mpll2,
546 &clk_fin_epll,
547 &clk_mout_hpll.clk,
548};
549
550static struct clk_sources clkset_spi = {
551 .sources = clkset_spi_list,
552 .nr_sources = ARRAY_SIZE(clkset_spi_list),
553};
554
555static struct clksrc_clk clk_spi0 = {
556 .clk = {
557 .name = "spi_bus",
558 .id = 0,
559 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0,
560 .enable = s5pc100_sclk0_ctrl,
561 .set_parent = s5pc100_setparent_clksrc,
562 .get_rate = s5pc100_getrate_clksrc,
563 .set_rate = s5pc100_setrate_clksrc,
564 .round_rate = s5pc100_roundrate_clksrc,
565 },
566 .shift = S5PC100_CLKSRC1_SPI0_SHIFT,
567 .mask = S5PC100_CLKSRC1_SPI0_MASK,
568 .sources = &clkset_spi,
569 .divider_shift = S5PC100_CLKDIV2_SPI0_SHIFT,
570 .reg_divider = S5PC100_CLKDIV2,
571 .reg_source = S5PC100_CLKSRC1,
572};
573
574static struct clksrc_clk clk_spi1 = {
575 .clk = {
576 .name = "spi_bus",
577 .id = 1,
578 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1,
579 .enable = s5pc100_sclk0_ctrl,
580 .set_parent = s5pc100_setparent_clksrc,
581 .get_rate = s5pc100_getrate_clksrc,
582 .set_rate = s5pc100_setrate_clksrc,
583 .round_rate = s5pc100_roundrate_clksrc,
584 },
585 .shift = S5PC100_CLKSRC1_SPI1_SHIFT,
586 .mask = S5PC100_CLKSRC1_SPI1_MASK,
587 .sources = &clkset_spi,
588 .divider_shift = S5PC100_CLKDIV2_SPI1_SHIFT,
589 .reg_divider = S5PC100_CLKDIV2,
590 .reg_source = S5PC100_CLKSRC1,
591};
592
593static struct clksrc_clk clk_spi2 = {
594 .clk = {
595 .name = "spi_bus",
596 .id = 2,
597 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2,
598 .enable = s5pc100_sclk0_ctrl,
599 .set_parent = s5pc100_setparent_clksrc,
600 .get_rate = s5pc100_getrate_clksrc,
601 .set_rate = s5pc100_setrate_clksrc,
602 .round_rate = s5pc100_roundrate_clksrc,
603 },
604 .shift = S5PC100_CLKSRC1_SPI2_SHIFT,
605 .mask = S5PC100_CLKSRC1_SPI2_MASK,
606 .sources = &clkset_spi,
607 .divider_shift = S5PC100_CLKDIV2_SPI2_SHIFT,
608 .reg_divider = S5PC100_CLKDIV2,
609 .reg_source = S5PC100_CLKSRC1,
610};
611
612static struct clk *clkset_uart_list[] = {
613 &clk_mout_epll.clk,
614 &clk_dout_mpll,
615};
616
617static struct clk_sources clkset_uart = {
618 .sources = clkset_uart_list,
619 .nr_sources = ARRAY_SIZE(clkset_uart_list),
620};
621
995static struct clksrc_clk clk_uart_uclk1 = { 622static struct clksrc_clk clk_uart_uclk1 = {
996 .clk = { 623 .clk = {
997 .name = "uclk1", 624 .name = "uclk1",
998 .id = -1, 625 .id = -1,
999 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, 626 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
1000 .enable = s5pc1xx_sclk0_ctrl, 627 .enable = s5pc100_sclk0_ctrl,
1001 .set_parent = s5pc1xx_setparent_clksrc, 628 .set_parent = s5pc100_setparent_clksrc,
1002 .get_rate = s5pc1xx_getrate_clksrc, 629 .get_rate = s5pc100_getrate_clksrc,
1003 .set_rate = s5pc1xx_setrate_clksrc, 630 .set_rate = s5pc100_setrate_clksrc,
1004 .round_rate = s5pc1xx_roundrate_clksrc, 631 .round_rate = s5pc100_roundrate_clksrc,
1005 }, 632 },
1006 .shift = S5PC100_CLKSRC1_UART_SHIFT, 633 .shift = S5PC100_CLKSRC1_UART_SHIFT,
1007 .mask = S5PC100_CLKSRC1_UART_MASK, 634 .mask = S5PC100_CLKSRC1_UART_MASK,
@@ -1011,16 +638,368 @@ static struct clksrc_clk clk_uart_uclk1 = {
1011 .reg_source = S5PC100_CLKSRC1, 638 .reg_source = S5PC100_CLKSRC1,
1012}; 639};
1013 640
641static struct clk clk_iis_cd0 = {
642 .name = "iis_cdclk0",
643 .id = -1,
644};
645
646static struct clk clk_iis_cd1 = {
647 .name = "iis_cdclk1",
648 .id = -1,
649};
650
651static struct clk clk_iis_cd2 = {
652 .name = "iis_cdclk2",
653 .id = -1,
654};
655
656static struct clk clk_pcm_cd0 = {
657 .name = "pcm_cdclk0",
658 .id = -1,
659};
660
661static struct clk clk_pcm_cd1 = {
662 .name = "pcm_cdclk1",
663 .id = -1,
664};
665
666static struct clk *clkset_audio0_list[] = {
667 &clk_mout_epll.clk,
668 &clk_dout_mpll,
669 &clk_fin_epll,
670 &clk_iis_cd0,
671 &clk_pcm_cd0,
672 &clk_mout_hpll.clk,
673};
674
675static struct clk_sources clkset_audio0 = {
676 .sources = clkset_audio0_list,
677 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
678};
679
680static struct clksrc_clk clk_audio0 = {
681 .clk = {
682 .name = "audio-bus",
683 .id = 0,
684 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0,
685 .enable = s5pc100_sclk1_ctrl,
686 .set_parent = s5pc100_setparent_clksrc,
687 .get_rate = s5pc100_getrate_clksrc,
688 .set_rate = s5pc100_setrate_clksrc,
689 .round_rate = s5pc100_roundrate_clksrc,
690 },
691 .shift = S5PC100_CLKSRC3_AUDIO0_SHIFT,
692 .mask = S5PC100_CLKSRC3_AUDIO0_MASK,
693 .sources = &clkset_audio0,
694 .divider_shift = S5PC100_CLKDIV4_AUDIO0_SHIFT,
695 .reg_divider = S5PC100_CLKDIV4,
696 .reg_source = S5PC100_CLKSRC3,
697};
698
699static struct clk *clkset_audio1_list[] = {
700 &clk_mout_epll.clk,
701 &clk_dout_mpll,
702 &clk_fin_epll,
703 &clk_iis_cd1,
704 &clk_pcm_cd1,
705 &clk_mout_hpll.clk,
706};
707
708static struct clk_sources clkset_audio1 = {
709 .sources = clkset_audio1_list,
710 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
711};
712
713static struct clksrc_clk clk_audio1 = {
714 .clk = {
715 .name = "audio-bus",
716 .id = 1,
717 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1,
718 .enable = s5pc100_sclk1_ctrl,
719 .set_parent = s5pc100_setparent_clksrc,
720 .get_rate = s5pc100_getrate_clksrc,
721 .set_rate = s5pc100_setrate_clksrc,
722 .round_rate = s5pc100_roundrate_clksrc,
723 },
724 .shift = S5PC100_CLKSRC3_AUDIO1_SHIFT,
725 .mask = S5PC100_CLKSRC3_AUDIO1_MASK,
726 .sources = &clkset_audio1,
727 .divider_shift = S5PC100_CLKDIV4_AUDIO1_SHIFT,
728 .reg_divider = S5PC100_CLKDIV4,
729 .reg_source = S5PC100_CLKSRC3,
730};
731
732static struct clk *clkset_audio2_list[] = {
733 &clk_mout_epll.clk,
734 &clk_dout_mpll,
735 &clk_fin_epll,
736 &clk_iis_cd2,
737 &clk_mout_hpll.clk,
738};
739
740static struct clk_sources clkset_audio2 = {
741 .sources = clkset_audio2_list,
742 .nr_sources = ARRAY_SIZE(clkset_audio2_list),
743};
744
745static struct clksrc_clk clk_audio2 = {
746 .clk = {
747 .name = "audio-bus",
748 .id = 2,
749 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2,
750 .enable = s5pc100_sclk1_ctrl,
751 .set_parent = s5pc100_setparent_clksrc,
752 .get_rate = s5pc100_getrate_clksrc,
753 .set_rate = s5pc100_setrate_clksrc,
754 .round_rate = s5pc100_roundrate_clksrc,
755 },
756 .shift = S5PC100_CLKSRC3_AUDIO2_SHIFT,
757 .mask = S5PC100_CLKSRC3_AUDIO2_MASK,
758 .sources = &clkset_audio2,
759 .divider_shift = S5PC100_CLKDIV4_AUDIO2_SHIFT,
760 .reg_divider = S5PC100_CLKDIV4,
761 .reg_source = S5PC100_CLKSRC3,
762};
763
764static struct clk *clkset_spdif_list[] = {
765 &clk_audio0.clk,
766 &clk_audio1.clk,
767 &clk_audio2.clk,
768};
769
770static struct clk_sources clkset_spdif = {
771 .sources = clkset_spdif_list,
772 .nr_sources = ARRAY_SIZE(clkset_spdif_list),
773};
774
775static struct clksrc_clk clk_spdif = {
776 .clk = {
777 .name = "spdif",
778 .id = -1,
779 },
780 .shift = S5PC100_CLKSRC3_SPDIF_SHIFT,
781 .mask = S5PC100_CLKSRC3_SPDIF_MASK,
782 .sources = &clkset_spdif,
783 .reg_source = S5PC100_CLKSRC3,
784};
785
786static struct clk *clkset_lcd_fimc_list[] = {
787 &clk_mout_epll.clk,
788 &clk_dout_mpll,
789 &clk_mout_hpll.clk,
790 &clk_vclk_54m,
791};
792
793static struct clk_sources clkset_lcd_fimc = {
794 .sources = clkset_lcd_fimc_list,
795 .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list),
796};
797
798static struct clksrc_clk clk_lcd = {
799 .clk = {
800 .name = "lcd",
801 .id = -1,
802 .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD,
803 .enable = s5pc100_sclk1_ctrl,
804 .set_parent = s5pc100_setparent_clksrc,
805 .get_rate = s5pc100_getrate_clksrc,
806 .set_rate = s5pc100_setrate_clksrc,
807 .round_rate = s5pc100_roundrate_clksrc,
808 },
809 .shift = S5PC100_CLKSRC2_LCD_SHIFT,
810 .mask = S5PC100_CLKSRC2_LCD_MASK,
811 .sources = &clkset_lcd_fimc,
812 .divider_shift = S5PC100_CLKDIV3_LCD_SHIFT,
813 .reg_divider = S5PC100_CLKDIV3,
814 .reg_source = S5PC100_CLKSRC2,
815};
816
817static struct clksrc_clk clk_fimc0 = {
818 .clk = {
819 .name = "fimc",
820 .id = 0,
821 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0,
822 .enable = s5pc100_sclk1_ctrl,
823 .set_parent = s5pc100_setparent_clksrc,
824 .get_rate = s5pc100_getrate_clksrc,
825 .set_rate = s5pc100_setrate_clksrc,
826 .round_rate = s5pc100_roundrate_clksrc,
827 },
828 .shift = S5PC100_CLKSRC2_FIMC0_SHIFT,
829 .mask = S5PC100_CLKSRC2_FIMC0_MASK,
830 .sources = &clkset_lcd_fimc,
831 .divider_shift = S5PC100_CLKDIV3_FIMC0_SHIFT,
832 .reg_divider = S5PC100_CLKDIV3,
833 .reg_source = S5PC100_CLKSRC2,
834};
835
836static struct clksrc_clk clk_fimc1 = {
837 .clk = {
838 .name = "fimc",
839 .id = 1,
840 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1,
841 .enable = s5pc100_sclk1_ctrl,
842 .set_parent = s5pc100_setparent_clksrc,
843 .get_rate = s5pc100_getrate_clksrc,
844 .set_rate = s5pc100_setrate_clksrc,
845 .round_rate = s5pc100_roundrate_clksrc,
846 },
847 .shift = S5PC100_CLKSRC2_FIMC1_SHIFT,
848 .mask = S5PC100_CLKSRC2_FIMC1_MASK,
849 .sources = &clkset_lcd_fimc,
850 .divider_shift = S5PC100_CLKDIV3_FIMC1_SHIFT,
851 .reg_divider = S5PC100_CLKDIV3,
852 .reg_source = S5PC100_CLKSRC2,
853};
854
855static struct clksrc_clk clk_fimc2 = {
856 .clk = {
857 .name = "fimc",
858 .id = 2,
859 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
860 .enable = s5pc100_sclk1_ctrl,
861 .set_parent = s5pc100_setparent_clksrc,
862 .get_rate = s5pc100_getrate_clksrc,
863 .set_rate = s5pc100_setrate_clksrc,
864 .round_rate = s5pc100_roundrate_clksrc,
865 },
866 .shift = S5PC100_CLKSRC2_FIMC2_SHIFT,
867 .mask = S5PC100_CLKSRC2_FIMC2_MASK,
868 .sources = &clkset_lcd_fimc,
869 .divider_shift = S5PC100_CLKDIV3_FIMC2_SHIFT,
870 .reg_divider = S5PC100_CLKDIV3,
871 .reg_source = S5PC100_CLKSRC2,
872};
873
874static struct clk *clkset_mmc_list[] = {
875 &clk_mout_epll.clk,
876 &clk_dout_mpll,
877 &clk_fin_epll,
878 &clk_mout_hpll.clk ,
879};
880
881static struct clk_sources clkset_mmc = {
882 .sources = clkset_mmc_list,
883 .nr_sources = ARRAY_SIZE(clkset_mmc_list),
884};
885
886static struct clksrc_clk clk_mmc0 = {
887 .clk = {
888 .name = "mmc_bus",
889 .id = 0,
890 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
891 .enable = s5pc100_sclk0_ctrl,
892 .set_parent = s5pc100_setparent_clksrc,
893 .get_rate = s5pc100_getrate_clksrc,
894 .set_rate = s5pc100_setrate_clksrc,
895 .round_rate = s5pc100_roundrate_clksrc,
896 },
897 .shift = S5PC100_CLKSRC2_MMC0_SHIFT,
898 .mask = S5PC100_CLKSRC2_MMC0_MASK,
899 .sources = &clkset_mmc,
900 .divider_shift = S5PC100_CLKDIV3_MMC0_SHIFT,
901 .reg_divider = S5PC100_CLKDIV3,
902 .reg_source = S5PC100_CLKSRC2,
903};
904
905static struct clksrc_clk clk_mmc1 = {
906 .clk = {
907 .name = "mmc_bus",
908 .id = 1,
909 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
910 .enable = s5pc100_sclk0_ctrl,
911 .set_parent = s5pc100_setparent_clksrc,
912 .get_rate = s5pc100_getrate_clksrc,
913 .set_rate = s5pc100_setrate_clksrc,
914 .round_rate = s5pc100_roundrate_clksrc,
915 },
916 .shift = S5PC100_CLKSRC2_MMC1_SHIFT,
917 .mask = S5PC100_CLKSRC2_MMC1_MASK,
918 .sources = &clkset_mmc,
919 .divider_shift = S5PC100_CLKDIV3_MMC1_SHIFT,
920 .reg_divider = S5PC100_CLKDIV3,
921 .reg_source = S5PC100_CLKSRC2,
922};
923
924static struct clksrc_clk clk_mmc2 = {
925 .clk = {
926 .name = "mmc_bus",
927 .id = 2,
928 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
929 .enable = s5pc100_sclk0_ctrl,
930 .set_parent = s5pc100_setparent_clksrc,
931 .get_rate = s5pc100_getrate_clksrc,
932 .set_rate = s5pc100_setrate_clksrc,
933 .round_rate = s5pc100_roundrate_clksrc,
934 },
935 .shift = S5PC100_CLKSRC2_MMC2_SHIFT,
936 .mask = S5PC100_CLKSRC2_MMC2_MASK,
937 .sources = &clkset_mmc,
938 .divider_shift = S5PC100_CLKDIV3_MMC2_SHIFT,
939 .reg_divider = S5PC100_CLKDIV3,
940 .reg_source = S5PC100_CLKSRC2,
941};
942
943
944static struct clk *clkset_usbhost_list[] = {
945 &clk_mout_epll.clk,
946 &clk_dout_mpll,
947 &clk_mout_hpll.clk,
948 &clk_48m,
949};
950
951static struct clk_sources clkset_usbhost = {
952 .sources = clkset_usbhost_list,
953 .nr_sources = ARRAY_SIZE(clkset_usbhost_list),
954};
955
956static struct clksrc_clk clk_usbhost = {
957 .clk = {
958 .name = "usbhost",
959 .id = -1,
960 .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
961 .enable = s5pc100_sclk0_ctrl,
962 .set_parent = s5pc100_setparent_clksrc,
963 .get_rate = s5pc100_getrate_clksrc,
964 .set_rate = s5pc100_setrate_clksrc,
965 .round_rate = s5pc100_roundrate_clksrc,
966 },
967 .shift = S5PC100_CLKSRC1_UHOST_SHIFT,
968 .mask = S5PC100_CLKSRC1_UHOST_MASK,
969 .sources = &clkset_usbhost,
970 .divider_shift = S5PC100_CLKDIV2_UHOST_SHIFT,
971 .reg_divider = S5PC100_CLKDIV2,
972 .reg_source = S5PC100_CLKSRC1,
973};
974
1014/* Clock initialisation code */ 975/* Clock initialisation code */
1015 976
1016static struct clksrc_clk *init_parents[] = { 977static struct clksrc_clk *init_parents[] = {
1017 &clk_mout_apll, 978 &clk_mout_apll,
1018 &clk_mout_epll,
1019 &clk_mout_mpll, 979 &clk_mout_mpll,
980 &clk_mout_am,
981 &clk_mout_onenand,
982 &clk_mout_epll,
983 &clk_mout_hpll,
984 &clk_spi0,
985 &clk_spi1,
986 &clk_spi2,
1020 &clk_uart_uclk1, 987 &clk_uart_uclk1,
988 &clk_audio0,
989 &clk_audio1,
990 &clk_audio2,
991 &clk_spdif,
992 &clk_lcd,
993 &clk_fimc0,
994 &clk_fimc1,
995 &clk_fimc2,
996 &clk_mmc0,
997 &clk_mmc1,
998 &clk_mmc2,
999 &clk_usbhost,
1021}; 1000};
1022 1001
1023static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk) 1002static void __init_or_cpufreq s5pc100_set_clksrc(struct clksrc_clk *clk)
1024{ 1003{
1025 struct clk_sources *srcs = clk->sources; 1004 struct clk_sources *srcs = clk->sources;
1026 u32 clksrc = __raw_readl(clk->reg_source); 1005 u32 clksrc = __raw_readl(clk->reg_source);
@@ -1036,9 +1015,9 @@ static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk)
1036 1015
1037 clk->clk.parent = srcs->sources[clksrc]; 1016 clk->clk.parent = srcs->sources[clksrc];
1038 1017
1039 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", 1018 printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n",
1040 clk->clk.name, clk->clk.parent->name, clksrc, 1019 clk->clk.name, clk->clk.parent->name, clksrc,
1041 clk_get_rate(&clk->clk)); 1020 print_mhz(clk_get_rate(&clk->clk)));
1042} 1021}
1043 1022
1044#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 1023#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
@@ -1052,10 +1031,7 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
1052 unsigned long hclk; 1031 unsigned long hclk;
1053 unsigned long pclkd0; 1032 unsigned long pclkd0;
1054 unsigned long pclk; 1033 unsigned long pclk;
1055 unsigned long apll; 1034 unsigned long apll, mpll, epll, hpll;
1056 unsigned long mpll;
1057 unsigned long hpll;
1058 unsigned long epll;
1059 unsigned int ptr; 1035 unsigned int ptr;
1060 u32 clkdiv0, clkdiv1; 1036 u32 clkdiv0, clkdiv1;
1061 1037
@@ -1064,8 +1040,7 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
1064 clkdiv0 = __raw_readl(S5PC100_CLKDIV0); 1040 clkdiv0 = __raw_readl(S5PC100_CLKDIV0);
1065 clkdiv1 = __raw_readl(S5PC100_CLKDIV1); 1041 clkdiv1 = __raw_readl(S5PC100_CLKDIV1);
1066 1042
1067 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", 1043 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1);
1068 __func__, clkdiv0, clkdiv1);
1069 1044
1070 xtal_clk = clk_get(NULL, "xtal"); 1045 xtal_clk = clk_get(NULL, "xtal");
1071 BUG_ON(IS_ERR(xtal_clk)); 1046 BUG_ON(IS_ERR(xtal_clk));
@@ -1080,8 +1055,10 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
1080 epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON)); 1055 epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON));
1081 hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON)); 1056 hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
1082 1057
1083 printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n", 1058 printk(KERN_INFO "S5PC100: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz"
1084 apll, mpll, epll, hpll); 1059 ", Epll=%ld.%03ld Mhz, Hpll=%ld.%03ld Mhz\n",
1060 print_mhz(apll), print_mhz(mpll),
1061 print_mhz(epll), print_mhz(hpll));
1085 1062
1086 armclk = apll / GET_DIV(clkdiv0, S5PC100_CLKDIV0_APLL); 1063 armclk = apll / GET_DIV(clkdiv0, S5PC100_CLKDIV0_APLL);
1087 armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM); 1064 armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM);
@@ -1090,33 +1067,64 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
1090 hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1); 1067 hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1);
1091 pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1); 1068 pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1);
1092 1069
1093 printk(KERN_INFO "S5PC100: ARMCLK=%ld, HCLKD0=%ld, PCLKD0=%ld, HCLK=%ld, PCLK=%ld\n", 1070 printk(KERN_INFO "S5PC100: ARMCLK=%ld.%03ld MHz, HCLKD0=%ld.%03ld MHz,"
1094 armclk, hclkd0, pclkd0, hclk, pclk); 1071 " PCLKD0=%ld.%03ld MHz\n, HCLK=%ld.%03ld MHz,"
1072 " PCLK=%ld.%03ld MHz\n",
1073 print_mhz(armclk), print_mhz(hclkd0),
1074 print_mhz(pclkd0), print_mhz(hclk), print_mhz(pclk));
1095 1075
1096 clk_fout_apll.rate = apll; 1076 clk_fout_apll.rate = apll;
1097 clk_fout_mpll.rate = mpll; 1077 clk_fout_mpll.rate = mpll;
1098 clk_fout_epll.rate = epll; 1078 clk_fout_epll.rate = epll;
1099 clk_fout_apll.rate = apll; 1079 clk_fout_hpll.rate = hpll;
1100 1080
1101 clk_h.rate = hclk; 1081 clk_h.rate = hclk;
1102 clk_p.rate = pclk; 1082 clk_p.rate = pclk;
1083 clk_f.rate = armclk;
1103 1084
1104 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) 1085 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
1105 s5pc1xx_set_clksrc(init_parents[ptr]); 1086 s5pc100_set_clksrc(init_parents[ptr]);
1106} 1087}
1107 1088
1108static struct clk *clks[] __initdata = { 1089static struct clk *clks[] __initdata = {
1109 &clk_ext_xtal_mux, 1090 &clk_ext_xtal_mux,
1110 &clk_mout_epll.clk, 1091 &clk_mout_apll.clk,
1111 &clk_fout_epll, 1092 &clk_dout_apll,
1093 &clk_dout_d0_bus,
1094 &clk_dout_pclkd0,
1095 &clk_dout_apll2,
1112 &clk_mout_mpll.clk, 1096 &clk_mout_mpll.clk,
1097 &clk_mout_am.clk,
1098 &clk_dout_d1_bus,
1099 &clk_mout_onenand.clk,
1100 &clk_dout_pclkd1,
1101 &clk_dout_mpll2,
1102 &clk_dout_cam,
1113 &clk_dout_mpll, 1103 &clk_dout_mpll,
1104 &clk_mout_epll.clk,
1105 &clk_fout_epll,
1106 &clk_iis_cd0,
1107 &clk_iis_cd1,
1108 &clk_iis_cd2,
1109 &clk_pcm_cd0,
1110 &clk_pcm_cd1,
1111 &clk_spi0.clk,
1112 &clk_spi1.clk,
1113 &clk_spi2.clk,
1114 &clk_uart_uclk1.clk, 1114 &clk_uart_uclk1.clk,
1115 &clk_ext, 1115 &clk_audio0.clk,
1116 &clk_epll, 1116 &clk_audio1.clk,
1117 &clk_27m, 1117 &clk_audio2.clk,
1118 &clk_48m, 1118 &clk_spdif.clk,
1119 &clk_54m, 1119 &clk_lcd.clk,
1120 &clk_fimc0.clk,
1121 &clk_fimc1.clk,
1122 &clk_fimc2.clk,
1123 &clk_mmc0.clk,
1124 &clk_mmc1.clk,
1125 &clk_mmc2.clk,
1126 &clk_usbhost.clk,
1127 &clk_arm,
1120}; 1128};
1121 1129
1122void __init s5pc100_register_clocks(void) 1130void __init s5pc100_register_clocks(void)
@@ -1133,7 +1141,4 @@ void __init s5pc100_register_clocks(void)
1133 clkp->name, ret); 1141 clkp->name, ret);
1134 } 1142 }
1135 } 1143 }
1136
1137 clk_mpll.parent = &clk_mout_mpll.clk;
1138 clk_epll.parent = &clk_mout_epll.clk;
1139} 1144}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 09:40:34 -0500