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authorMarek Szyprowski <m.szyprowski@samsung.com>2010-05-20 01:51:11 -0400
committerBen Dooks <ben-linux@fluff.org>2010-05-20 02:28:45 -0400
commita73e3e6f8f5847c00edb9dd7aab19d005a3d6e5c (patch)
tree61cfc338e7e58134f078eb79c35f5a6ab9cb6ea8 /arch/arm/plat-s5pc1xx/include
parent80dfd9556a94fe479fde86370713aafd33b61a0c (diff)
ARM: remove obsolete plat-s5pc1xx directory
This patch removes all obsolete files from plat-s5pc1xx. This directory is no longer needed. S5PC100 SoC is now completely supported in plat-s5p framework. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s5pc1xx/include')
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h44
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/irqs.h198
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/pll.h38
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/regs-clock.h252
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/regs-power.h84
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/s5pc100.h64
6 files changed, 0 insertions, 680 deletions
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h
deleted file mode 100644
index 33ad267e8477..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-eint.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 *
5 * External Interrupt (GPH0 ~ GPH3) control register definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#define S5PC1XX_WKUP_INT_CON0_7 (S5PC1XX_EINT_BASE + 0x0)
13#define S5PC1XX_WKUP_INT_CON8_15 (S5PC1XX_EINT_BASE + 0x4)
14#define S5PC1XX_WKUP_INT_CON16_23 (S5PC1XX_EINT_BASE + 0x8)
15#define S5PC1XX_WKUP_INT_CON24_31 (S5PC1XX_EINT_BASE + 0xC)
16#define S5PC1XX_WKUP_INT_CON(x) (S5PC1XX_WKUP_INT_CON0_7 + (x * 0x4))
17
18#define S5PC1XX_WKUP_INT_FLTCON0_3 (S5PC1XX_EINT_BASE + 0x80)
19#define S5PC1XX_WKUP_INT_FLTCON4_7 (S5PC1XX_EINT_BASE + 0x84)
20#define S5PC1XX_WKUP_INT_FLTCON8_11 (S5PC1XX_EINT_BASE + 0x88)
21#define S5PC1XX_WKUP_INT_FLTCON12_15 (S5PC1XX_EINT_BASE + 0x8C)
22#define S5PC1XX_WKUP_INT_FLTCON16_19 (S5PC1XX_EINT_BASE + 0x90)
23#define S5PC1XX_WKUP_INT_FLTCON20_23 (S5PC1XX_EINT_BASE + 0x94)
24#define S5PC1XX_WKUP_INT_FLTCON24_27 (S5PC1XX_EINT_BASE + 0x98)
25#define S5PC1XX_WKUP_INT_FLTCON28_31 (S5PC1XX_EINT_BASE + 0x9C)
26#define S5PC1XX_WKUP_INT_FLTCON(x) (S5PC1XX_WKUP_INT_FLTCON0_3 + (x * 0x4))
27
28#define S5PC1XX_WKUP_INT_MASK0_7 (S5PC1XX_EINT_BASE + 0x100)
29#define S5PC1XX_WKUP_INT_MASK8_15 (S5PC1XX_EINT_BASE + 0x104)
30#define S5PC1XX_WKUP_INT_MASK16_23 (S5PC1XX_EINT_BASE + 0x108)
31#define S5PC1XX_WKUP_INT_MASK24_31 (S5PC1XX_EINT_BASE + 0x10C)
32#define S5PC1XX_WKUP_INT_MASK(x) (S5PC1XX_WKUP_INT_MASK0_7 + (x * 0x4))
33
34#define S5PC1XX_WKUP_INT_PEND0_7 (S5PC1XX_EINT_BASE + 0x140)
35#define S5PC1XX_WKUP_INT_PEND8_15 (S5PC1XX_EINT_BASE + 0x144)
36#define S5PC1XX_WKUP_INT_PEND16_23 (S5PC1XX_EINT_BASE + 0x148)
37#define S5PC1XX_WKUP_INT_PEND24_31 (S5PC1XX_EINT_BASE + 0x14C)
38#define S5PC1XX_WKUP_INT_PEND(x) (S5PC1XX_WKUP_INT_PEND0_7 + (x * 0x4))
39
40#define S5PC1XX_WKUP_INT_LOWLEV (0x00)
41#define S5PC1XX_WKUP_INT_HILEV (0x01)
42#define S5PC1XX_WKUP_INT_FALLEDGE (0x02)
43#define S5PC1XX_WKUP_INT_RISEEDGE (0x03)
44#define S5PC1XX_WKUP_INT_BOTHEDGE (0x04)
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
deleted file mode 100644
index 409c804315e8..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h
+++ /dev/null
@@ -1,198 +0,0 @@
1/* linux/arch/arm/plat-s5pc1xx/include/plat/irqs.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC1XX - Common IRQ support
7 *
8 * Based on plat-s3c64xx/include/plat/irqs.h
9 */
10
11#ifndef __ASM_PLAT_S5PC1XX_IRQS_H
12#define __ASM_PLAT_S5PC1XX_IRQS_H __FILE__
13
14/* we keep the first set of CPU IRQs out of the range of
15 * the ISA space, so that the PC104 has them to itself
16 * and we don't end up having to do horrible things to the
17 * standard ISA drivers....
18 *
19 * note, since we're using the VICs, our start must be a
20 * mulitple of 32 to allow the common code to work
21 */
22
23#define S3C_IRQ_OFFSET (32)
24
25#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
26
27#define S3C_VIC0_BASE S3C_IRQ(0)
28#define S3C_VIC1_BASE S3C_IRQ(32)
29#define S3C_VIC2_BASE S3C_IRQ(64)
30
31/* UART interrupts, each UART has 4 intterupts per channel so
32 * use the space between the ISA and S3C main interrupts. Note, these
33 * are not in the same order as the S3C24XX series! */
34
35#define IRQ_S3CUART_BASE0 (16)
36#define IRQ_S3CUART_BASE1 (20)
37#define IRQ_S3CUART_BASE2 (24)
38#define IRQ_S3CUART_BASE3 (28)
39
40#define UART_IRQ_RXD (0)
41#define UART_IRQ_ERR (1)
42#define UART_IRQ_TXD (2)
43#define UART_IRQ_MODEM (3)
44
45#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
46#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
47#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
48
49#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
50#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
51#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
52
53#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
54#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
55#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
56
57#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
58#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
59#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
60
61/* VIC based IRQs */
62
63#define S5PC1XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x))
64#define S5PC1XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x))
65#define S5PC1XX_IRQ_VIC2(x) (S3C_VIC2_BASE + (x))
66
67/*
68 * VIC0: system, DMA, timer
69 */
70#define IRQ_EINT0 S5PC1XX_IRQ_VIC0(0)
71#define IRQ_EINT1 S5PC1XX_IRQ_VIC0(1)
72#define IRQ_EINT2 S5PC1XX_IRQ_VIC0(2)
73#define IRQ_EINT3 S5PC1XX_IRQ_VIC0(3)
74#define IRQ_EINT4 S5PC1XX_IRQ_VIC0(4)
75#define IRQ_EINT5 S5PC1XX_IRQ_VIC0(5)
76#define IRQ_EINT6 S5PC1XX_IRQ_VIC0(6)
77#define IRQ_EINT7 S5PC1XX_IRQ_VIC0(7)
78#define IRQ_EINT8 S5PC1XX_IRQ_VIC0(8)
79#define IRQ_EINT9 S5PC1XX_IRQ_VIC0(9)
80#define IRQ_EINT10 S5PC1XX_IRQ_VIC0(10)
81#define IRQ_EINT11 S5PC1XX_IRQ_VIC0(11)
82#define IRQ_EINT12 S5PC1XX_IRQ_VIC0(12)
83#define IRQ_EINT13 S5PC1XX_IRQ_VIC0(13)
84#define IRQ_EINT14 S5PC1XX_IRQ_VIC0(14)
85#define IRQ_EINT15 S5PC1XX_IRQ_VIC0(15)
86#define IRQ_EINT16_31 S5PC1XX_IRQ_VIC0(16)
87#define IRQ_BATF S5PC1XX_IRQ_VIC0(17)
88#define IRQ_MDMA S5PC1XX_IRQ_VIC0(18)
89#define IRQ_PDMA0 S5PC1XX_IRQ_VIC0(19)
90#define IRQ_PDMA1 S5PC1XX_IRQ_VIC0(20)
91#define IRQ_TIMER0_VIC S5PC1XX_IRQ_VIC0(21)
92#define IRQ_TIMER1_VIC S5PC1XX_IRQ_VIC0(22)
93#define IRQ_TIMER2_VIC S5PC1XX_IRQ_VIC0(23)
94#define IRQ_TIMER3_VIC S5PC1XX_IRQ_VIC0(24)
95#define IRQ_TIMER4_VIC S5PC1XX_IRQ_VIC0(25)
96#define IRQ_SYSTIMER S5PC1XX_IRQ_VIC0(26)
97#define IRQ_WDT S5PC1XX_IRQ_VIC0(27)
98#define IRQ_RTC_ALARM S5PC1XX_IRQ_VIC0(28)
99#define IRQ_RTC_TIC S5PC1XX_IRQ_VIC0(29)
100#define IRQ_GPIOINT S5PC1XX_IRQ_VIC0(30)
101
102/*
103 * VIC1: ARM, power, memory, connectivity
104 */
105#define IRQ_CORTEX0 S5PC1XX_IRQ_VIC1(0)
106#define IRQ_CORTEX1 S5PC1XX_IRQ_VIC1(1)
107#define IRQ_CORTEX2 S5PC1XX_IRQ_VIC1(2)
108#define IRQ_CORTEX3 S5PC1XX_IRQ_VIC1(3)
109#define IRQ_CORTEX4 S5PC1XX_IRQ_VIC1(4)
110#define IRQ_IEMAPC S5PC1XX_IRQ_VIC1(5)
111#define IRQ_IEMIEC S5PC1XX_IRQ_VIC1(6)
112#define IRQ_ONENAND S5PC1XX_IRQ_VIC1(7)
113#define IRQ_NFC S5PC1XX_IRQ_VIC1(8)
114#define IRQ_CFC S5PC1XX_IRQ_VIC1(9)
115#define IRQ_UART0 S5PC1XX_IRQ_VIC1(10)
116#define IRQ_UART1 S5PC1XX_IRQ_VIC1(11)
117#define IRQ_UART2 S5PC1XX_IRQ_VIC1(12)
118#define IRQ_UART3 S5PC1XX_IRQ_VIC1(13)
119#define IRQ_IIC S5PC1XX_IRQ_VIC1(14)
120#define IRQ_SPI0 S5PC1XX_IRQ_VIC1(15)
121#define IRQ_SPI1 S5PC1XX_IRQ_VIC1(16)
122#define IRQ_SPI2 S5PC1XX_IRQ_VIC1(17)
123#define IRQ_IRDA S5PC1XX_IRQ_VIC1(18)
124#define IRQ_CAN0 S5PC1XX_IRQ_VIC1(19)
125#define IRQ_CAN1 S5PC1XX_IRQ_VIC1(20)
126#define IRQ_HSIRX S5PC1XX_IRQ_VIC1(21)
127#define IRQ_HSITX S5PC1XX_IRQ_VIC1(22)
128#define IRQ_UHOST S5PC1XX_IRQ_VIC1(23)
129#define IRQ_OTG S5PC1XX_IRQ_VIC1(24)
130#define IRQ_MSM S5PC1XX_IRQ_VIC1(25)
131#define IRQ_HSMMC0 S5PC1XX_IRQ_VIC1(26)
132#define IRQ_HSMMC1 S5PC1XX_IRQ_VIC1(27)
133#define IRQ_HSMMC2 S5PC1XX_IRQ_VIC1(28)
134#define IRQ_MIPICSI S5PC1XX_IRQ_VIC1(29)
135#define IRQ_MIPIDSI S5PC1XX_IRQ_VIC1(30)
136
137/*
138 * VIC2: multimedia, audio, security
139 */
140#define IRQ_LCD0 S5PC1XX_IRQ_VIC2(0)
141#define IRQ_LCD1 S5PC1XX_IRQ_VIC2(1)
142#define IRQ_LCD2 S5PC1XX_IRQ_VIC2(2)
143#define IRQ_LCD3 S5PC1XX_IRQ_VIC2(3)
144#define IRQ_ROTATOR S5PC1XX_IRQ_VIC2(4)
145#define IRQ_FIMC0 S5PC1XX_IRQ_VIC2(5)
146#define IRQ_FIMC1 S5PC1XX_IRQ_VIC2(6)
147#define IRQ_FIMC2 S5PC1XX_IRQ_VIC2(7)
148#define IRQ_JPEG S5PC1XX_IRQ_VIC2(8)
149#define IRQ_2D S5PC1XX_IRQ_VIC2(9)
150#define IRQ_3D S5PC1XX_IRQ_VIC2(10)
151#define IRQ_MIXER S5PC1XX_IRQ_VIC2(11)
152#define IRQ_HDMI S5PC1XX_IRQ_VIC2(12)
153#define IRQ_IIC1 S5PC1XX_IRQ_VIC2(13)
154#define IRQ_MFC S5PC1XX_IRQ_VIC2(14)
155#define IRQ_TVENC S5PC1XX_IRQ_VIC2(15)
156#define IRQ_I2S0 S5PC1XX_IRQ_VIC2(16)
157#define IRQ_I2S1 S5PC1XX_IRQ_VIC2(17)
158#define IRQ_I2S2 S5PC1XX_IRQ_VIC2(18)
159#define IRQ_AC97 S5PC1XX_IRQ_VIC2(19)
160#define IRQ_PCM0 S5PC1XX_IRQ_VIC2(20)
161#define IRQ_PCM1 S5PC1XX_IRQ_VIC2(21)
162#define IRQ_SPDIF S5PC1XX_IRQ_VIC2(22)
163#define IRQ_ADC S5PC1XX_IRQ_VIC2(23)
164#define IRQ_PENDN S5PC1XX_IRQ_VIC2(24)
165#define IRQ_TC IRQ_PENDN
166#define IRQ_KEYPAD S5PC1XX_IRQ_VIC2(25)
167#define IRQ_CG S5PC1XX_IRQ_VIC2(26)
168#define IRQ_SEC S5PC1XX_IRQ_VIC2(27)
169#define IRQ_SECRX S5PC1XX_IRQ_VIC2(28)
170#define IRQ_SECTX S5PC1XX_IRQ_VIC2(29)
171#define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30)
172#define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31)
173
174#define IRQ_TIMER(x) (IRQ_SDMFIQ + 1 + (x))
175#define IRQ_TIMER0 IRQ_TIMER(0)
176#define IRQ_TIMER1 IRQ_TIMER(1)
177#define IRQ_TIMER2 IRQ_TIMER(2)
178#define IRQ_TIMER3 IRQ_TIMER(3)
179#define IRQ_TIMER4 IRQ_TIMER(4)
180
181/* External interrupt */
182#define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 6)
183
184#define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16))
185#define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x))
186#define IRQ_EINT_BIT(x) (x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0))
187
188/* GPIO interrupt */
189#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1)
190#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x))
191
192/*
193 * Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs
194 */
195#define NR_IRQS (S3C_IRQ_GPIO(320) + 1)
196
197#endif /* __ASM_PLAT_S5PC1XX_IRQS_H */
198
diff --git a/arch/arm/plat-s5pc1xx/include/plat/pll.h b/arch/arm/plat-s5pc1xx/include/plat/pll.h
deleted file mode 100644
index 21afef1573e7..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/pll.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/* arch/arm/plat-s5pc1xx/include/plat/pll.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC1XX PLL code
7 *
8 * Based on plat-s3c64xx/include/plat/pll.h
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S5P_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
16#define S5P_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
17#define S5P_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
18#define S5P_PLL_MDIV_SHIFT (16)
19#define S5P_PLL_PDIV_SHIFT (8)
20#define S5P_PLL_SDIV_SHIFT (0)
21
22#include <asm/div64.h>
23
24static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk,
25 u32 pllcon)
26{
27 u32 mdiv, pdiv, sdiv;
28 u64 fvco = baseclk;
29
30 mdiv = (pllcon >> S5P_PLL_MDIV_SHIFT) & S5P_PLL_MDIV_MASK;
31 pdiv = (pllcon >> S5P_PLL_PDIV_SHIFT) & S5P_PLL_PDIV_MASK;
32 sdiv = (pllcon >> S5P_PLL_SDIV_SHIFT) & S5P_PLL_SDIV_MASK;
33
34 fvco *= mdiv;
35 do_div(fvco, (pdiv << sdiv));
36
37 return (unsigned long)fvco;
38}
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
deleted file mode 100644
index 24dec4e52538..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+++ /dev/null
@@ -1,252 +0,0 @@
1/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC1XX clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_REGS_CLOCK_H
14#define __PLAT_REGS_CLOCK_H __FILE__
15
16#define S5PC100_CLKREG(x) (S5PC1XX_VA_CLK + (x))
17#define S5PC100_CLKREG_OTHER(x) (S5PC1XX_VA_CLK_OTHER + (x))
18
19/* s5pc100 register for clock */
20#define S5PC100_APLL_LOCK S5PC100_CLKREG(0x00)
21#define S5PC100_MPLL_LOCK S5PC100_CLKREG(0x04)
22#define S5PC100_EPLL_LOCK S5PC100_CLKREG(0x08)
23#define S5PC100_HPLL_LOCK S5PC100_CLKREG(0x0C)
24
25#define S5PC100_APLL_CON S5PC100_CLKREG(0x100)
26#define S5PC100_MPLL_CON S5PC100_CLKREG(0x104)
27#define S5PC100_EPLL_CON S5PC100_CLKREG(0x108)
28#define S5PC100_HPLL_CON S5PC100_CLKREG(0x10C)
29
30#define S5PC100_CLKSRC0 S5PC100_CLKREG(0x200)
31#define S5PC100_CLKSRC1 S5PC100_CLKREG(0x204)
32#define S5PC100_CLKSRC2 S5PC100_CLKREG(0x208)
33#define S5PC100_CLKSRC3 S5PC100_CLKREG(0x20C)
34
35#define S5PC100_CLKDIV0 S5PC100_CLKREG(0x300)
36#define S5PC100_CLKDIV1 S5PC100_CLKREG(0x304)
37#define S5PC100_CLKDIV2 S5PC100_CLKREG(0x308)
38#define S5PC100_CLKDIV3 S5PC100_CLKREG(0x30C)
39#define S5PC100_CLKDIV4 S5PC100_CLKREG(0x310)
40
41#define S5PC100_CLK_OUT S5PC100_CLKREG(0x400)
42
43#define S5PC100_CLKGATE_D00 S5PC100_CLKREG(0x500)
44#define S5PC100_CLKGATE_D01 S5PC100_CLKREG(0x504)
45#define S5PC100_CLKGATE_D02 S5PC100_CLKREG(0x508)
46
47#define S5PC100_CLKGATE_D10 S5PC100_CLKREG(0x520)
48#define S5PC100_CLKGATE_D11 S5PC100_CLKREG(0x524)
49#define S5PC100_CLKGATE_D12 S5PC100_CLKREG(0x528)
50#define S5PC100_CLKGATE_D13 S5PC100_CLKREG(0x52C)
51#define S5PC100_CLKGATE_D14 S5PC100_CLKREG(0x530)
52#define S5PC100_CLKGATE_D15 S5PC100_CLKREG(0x534)
53
54#define S5PC100_CLKGATE_D20 S5PC100_CLKREG(0x540)
55
56#define S5PC100_SCLKGATE0 S5PC100_CLKREG(0x560)
57#define S5PC100_SCLKGATE1 S5PC100_CLKREG(0x564)
58
59/* EPLL_CON */
60#define S5PC100_EPLL_EN (1<<31)
61#define S5PC100_EPLL_MASK 0xffffffff
62#define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
63
64/* CLKSRC0..CLKSRC3 -> mostly removed due to clksrc updates */
65#define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24)
66#define S5PC100_CLKSRC1_CLK48M_SHIFT (24)
67
68/* CLKDIV0 */
69#define S5PC100_CLKDIV0_APLL_MASK (0x1<<0)
70#define S5PC100_CLKDIV0_APLL_SHIFT (0)
71#define S5PC100_CLKDIV0_ARM_MASK (0x7<<4)
72#define S5PC100_CLKDIV0_ARM_SHIFT (4)
73#define S5PC100_CLKDIV0_D0_MASK (0x7<<8)
74#define S5PC100_CLKDIV0_D0_SHIFT (8)
75#define S5PC100_CLKDIV0_PCLKD0_MASK (0x7<<12)
76#define S5PC100_CLKDIV0_PCLKD0_SHIFT (12)
77#define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16)
78#define S5PC100_CLKDIV0_SECSS_SHIFT (16)
79
80/* CLKDIV1 (OneNAND clock only used in one place, removed) */
81#define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0)
82#define S5PC100_CLKDIV1_APLL2_SHIFT (0)
83#define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4)
84#define S5PC100_CLKDIV1_MPLL_SHIFT (4)
85#define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8)
86#define S5PC100_CLKDIV1_MPLL2_SHIFT (8)
87#define S5PC100_CLKDIV1_D1_MASK (0x7<<12)
88#define S5PC100_CLKDIV1_D1_SHIFT (12)
89#define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16)
90#define S5PC100_CLKDIV1_PCLKD1_SHIFT (16)
91#define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24)
92#define S5PC100_CLKDIV1_CAM_SHIFT (24)
93
94/* CLKDIV2 => removed in clksrc update */
95/* CLKDIV3 => removed in clksrc update, or not needed */
96/* CLKDIV4 => removed in clksrc update, or not needed */
97
98/* HCLKD0/PCLKD0 Clock Gate 0 Registers */
99#define S5PC100_CLKGATE_D00_INTC (1<<0)
100#define S5PC100_CLKGATE_D00_TZIC (1<<1)
101#define S5PC100_CLKGATE_D00_CFCON (1<<2)
102#define S5PC100_CLKGATE_D00_MDMA (1<<3)
103#define S5PC100_CLKGATE_D00_G2D (1<<4)
104#define S5PC100_CLKGATE_D00_SECSS (1<<5)
105#define S5PC100_CLKGATE_D00_CSSYS (1<<6)
106
107/* HCLKD0/PCLKD0 Clock Gate 1 Registers */
108#define S5PC100_CLKGATE_D01_DMC (1<<0)
109#define S5PC100_CLKGATE_D01_SROMC (1<<1)
110#define S5PC100_CLKGATE_D01_ONENAND (1<<2)
111#define S5PC100_CLKGATE_D01_NFCON (1<<3)
112#define S5PC100_CLKGATE_D01_INTMEM (1<<4)
113#define S5PC100_CLKGATE_D01_EBI (1<<5)
114
115/* PCLKD0 Clock Gate 2 Registers */
116#define S5PC100_CLKGATE_D02_SECKEY (1<<1)
117#define S5PC100_CLKGATE_D02_SDM (1<<2)
118
119/* HCLKD1/PCLKD1 Clock Gate 0 Registers */
120#define S5PC100_CLKGATE_D10_PDMA0 (1<<0)
121#define S5PC100_CLKGATE_D10_PDMA1 (1<<1)
122#define S5PC100_CLKGATE_D10_USBHOST (1<<2)
123#define S5PC100_CLKGATE_D10_USBOTG (1<<3)
124#define S5PC100_CLKGATE_D10_MODEMIF (1<<4)
125#define S5PC100_CLKGATE_D10_HSMMC0 (1<<5)
126#define S5PC100_CLKGATE_D10_HSMMC1 (1<<6)
127#define S5PC100_CLKGATE_D10_HSMMC2 (1<<7)
128
129/* HCLKD1/PCLKD1 Clock Gate 1 Registers */
130#define S5PC100_CLKGATE_D11_LCD (1<<0)
131#define S5PC100_CLKGATE_D11_ROTATOR (1<<1)
132#define S5PC100_CLKGATE_D11_FIMC0 (1<<2)
133#define S5PC100_CLKGATE_D11_FIMC1 (1<<3)
134#define S5PC100_CLKGATE_D11_FIMC2 (1<<4)
135#define S5PC100_CLKGATE_D11_JPEG (1<<5)
136#define S5PC100_CLKGATE_D11_DSI (1<<6)
137#define S5PC100_CLKGATE_D11_CSI (1<<7)
138#define S5PC100_CLKGATE_D11_G3D (1<<8)
139
140/* HCLKD1/PCLKD1 Clock Gate 2 Registers */
141#define S5PC100_CLKGATE_D12_TV (1<<0)
142#define S5PC100_CLKGATE_D12_VP (1<<1)
143#define S5PC100_CLKGATE_D12_MIXER (1<<2)
144#define S5PC100_CLKGATE_D12_HDMI (1<<3)
145#define S5PC100_CLKGATE_D12_MFC (1<<4)
146
147/* HCLKD1/PCLKD1 Clock Gate 3 Registers */
148#define S5PC100_CLKGATE_D13_CHIPID (1<<0)
149#define S5PC100_CLKGATE_D13_GPIO (1<<1)
150#define S5PC100_CLKGATE_D13_APC (1<<2)
151#define S5PC100_CLKGATE_D13_IEC (1<<3)
152#define S5PC100_CLKGATE_D13_PWM (1<<6)
153#define S5PC100_CLKGATE_D13_SYSTIMER (1<<7)
154#define S5PC100_CLKGATE_D13_WDT (1<<8)
155#define S5PC100_CLKGATE_D13_RTC (1<<9)
156
157/* HCLKD1/PCLKD1 Clock Gate 4 Registers */
158#define S5PC100_CLKGATE_D14_UART0 (1<<0)
159#define S5PC100_CLKGATE_D14_UART1 (1<<1)
160#define S5PC100_CLKGATE_D14_UART2 (1<<2)
161#define S5PC100_CLKGATE_D14_UART3 (1<<3)
162#define S5PC100_CLKGATE_D14_IIC (1<<4)
163#define S5PC100_CLKGATE_D14_HDMI_IIC (1<<5)
164#define S5PC100_CLKGATE_D14_SPI0 (1<<6)
165#define S5PC100_CLKGATE_D14_SPI1 (1<<7)
166#define S5PC100_CLKGATE_D14_SPI2 (1<<8)
167#define S5PC100_CLKGATE_D14_IRDA (1<<9)
168#define S5PC100_CLKGATE_D14_CCAN0 (1<<10)
169#define S5PC100_CLKGATE_D14_CCAN1 (1<<11)
170#define S5PC100_CLKGATE_D14_HSITX (1<<12)
171#define S5PC100_CLKGATE_D14_HSIRX (1<<13)
172
173/* HCLKD1/PCLKD1 Clock Gate 5 Registers */
174#define S5PC100_CLKGATE_D15_IIS0 (1<<0)
175#define S5PC100_CLKGATE_D15_IIS1 (1<<1)
176#define S5PC100_CLKGATE_D15_IIS2 (1<<2)
177#define S5PC100_CLKGATE_D15_AC97 (1<<3)
178#define S5PC100_CLKGATE_D15_PCM0 (1<<4)
179#define S5PC100_CLKGATE_D15_PCM1 (1<<5)
180#define S5PC100_CLKGATE_D15_SPDIF (1<<6)
181#define S5PC100_CLKGATE_D15_TSADC (1<<7)
182#define S5PC100_CLKGATE_D15_KEYIF (1<<8)
183#define S5PC100_CLKGATE_D15_CG (1<<9)
184
185/* HCLKD2 Clock Gate 0 Registers */
186#define S5PC100_CLKGATE_D20_HCLKD2 (1<<0)
187#define S5PC100_CLKGATE_D20_I2SD2 (1<<1)
188
189/* Special Clock Gate 0 Registers */
190#define S5PC100_CLKGATE_SCLK0_HPM (1<<0)
191#define S5PC100_CLKGATE_SCLK0_PWI (1<<1)
192#define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2)
193#define S5PC100_CLKGATE_SCLK0_UART (1<<3)
194#define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4)
195#define S5PC100_CLKGATE_SCLK0_SPI1 (1<<5)
196#define S5PC100_CLKGATE_SCLK0_SPI2 (1<<6)
197#define S5PC100_CLKGATE_SCLK0_SPI0_48 (1<<7)
198#define S5PC100_CLKGATE_SCLK0_SPI1_48 (1<<8)
199#define S5PC100_CLKGATE_SCLK0_SPI2_48 (1<<9)
200#define S5PC100_CLKGATE_SCLK0_IRDA (1<<10)
201#define S5PC100_CLKGATE_SCLK0_USBHOST (1<<11)
202#define S5PC100_CLKGATE_SCLK0_MMC0 (1<<12)
203#define S5PC100_CLKGATE_SCLK0_MMC1 (1<<13)
204#define S5PC100_CLKGATE_SCLK0_MMC2 (1<<14)
205#define S5PC100_CLKGATE_SCLK0_MMC0_48 (1<<15)
206#define S5PC100_CLKGATE_SCLK0_MMC1_48 (1<<16)
207#define S5PC100_CLKGATE_SCLK0_MMC2_48 (1<<17)
208
209/* Special Clock Gate 1 Registers */
210#define S5PC100_CLKGATE_SCLK1_LCD (1<<0)
211#define S5PC100_CLKGATE_SCLK1_FIMC0 (1<<1)
212#define S5PC100_CLKGATE_SCLK1_FIMC1 (1<<2)
213#define S5PC100_CLKGATE_SCLK1_FIMC2 (1<<3)
214#define S5PC100_CLKGATE_SCLK1_TV54 (1<<4)
215#define S5PC100_CLKGATE_SCLK1_VDAC54 (1<<5)
216#define S5PC100_CLKGATE_SCLK1_MIXER (1<<6)
217#define S5PC100_CLKGATE_SCLK1_HDMI (1<<7)
218#define S5PC100_CLKGATE_SCLK1_AUDIO0 (1<<8)
219#define S5PC100_CLKGATE_SCLK1_AUDIO1 (1<<9)
220#define S5PC100_CLKGATE_SCLK1_AUDIO2 (1<<10)
221#define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11)
222#define S5PC100_CLKGATE_SCLK1_CAM (1<<12)
223
224#define S5PC100_SWRESET S5PC100_CLKREG_OTHER(0x000)
225#define S5PC100_OND_SWRESET S5PC100_CLKREG_OTHER(0x008)
226#define S5PC100_GEN_CTRL S5PC100_CLKREG_OTHER(0x100)
227#define S5PC100_GEN_STATUS S5PC100_CLKREG_OTHER(0x104)
228#define S5PC100_MEM_SYS_CFG S5PC100_CLKREG_OTHER(0x200)
229#define S5PC100_CAM_MUX_SEL S5PC100_CLKREG_OTHER(0x300)
230#define S5PC100_MIXER_OUT_SEL S5PC100_CLKREG_OTHER(0x304)
231#define S5PC100_LPMP_MODE_SEL S5PC100_CLKREG_OTHER(0x308)
232#define S5PC100_MIPI_PHY_CON0 S5PC100_CLKREG_OTHER(0x400)
233#define S5PC100_MIPI_PHY_CON1 S5PC100_CLKREG_OTHER(0x414)
234#define S5PC100_HDMI_PHY_CON0 S5PC100_CLKREG_OTHER(0x420)
235
236#define S5PC100_SWRESET_RESETVAL 0xc100
237#define S5PC100_OTHER_SYS_INT 24
238#define S5PC100_OTHER_STA_TYPE 23
239#define STA_TYPE_EXPON 0
240#define STA_TYPE_SFR 1
241
242#define S5PC100_SLEEP_CFG_OSC_EN 0
243
244/* OTHERS Resgister */
245#define S5PC100_OTHERS_USB_SIG_MASK (1 << 16)
246#define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28)
247
248/* MIPI D-PHY Control Register 0 */
249#define S5PC100_MIPI_PHY_CON0_M_RESETN (1 << 1)
250#define S5PC100_MIPI_PHY_CON0_S_RESETN (1 << 0)
251
252#endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h
deleted file mode 100644
index 02ffa491b53a..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h
+++ /dev/null
@@ -1,84 +0,0 @@
1/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Jongse Won <jongse.won@samsung.com>
5 *
6 * S5PC1XX clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARM_REGS_PWR
14#define __ASM_ARM_REGS_PWR __FILE__
15
16#define S5PC1XX_PWRREG(x) (S5PC1XX_VA_PWR + (x))
17
18/* s5pc100 (0xE0108000) register for power management */
19#define S5PC100_PWR_CFG S5PC1XX_PWRREG(0x0)
20#define S5PC100_EINT_WAKEUP_MASK S5PC1XX_PWRREG(0x4)
21#define S5PC100_NORMAL_CFG S5PC1XX_PWRREG(0x10)
22#define S5PC100_STOP_CFG S5PC1XX_PWRREG(0x14)
23#define S5PC100_SLEEP_CFG S5PC1XX_PWRREG(0x18)
24#define S5PC100_STOP_MEM_CFG S5PC1XX_PWRREG(0x1C)
25#define S5PC100_OSC_FREQ S5PC1XX_PWRREG(0x100)
26#define S5PC100_OSC_STABLE S5PC1XX_PWRREG(0x104)
27#define S5PC100_PWR_STABLE S5PC1XX_PWRREG(0x108)
28#define S5PC100_MTC_STABLE S5PC1XX_PWRREG(0x110)
29#define S5PC100_CLAMP_STABLE S5PC1XX_PWRREG(0x114)
30#define S5PC100_OTHERS S5PC1XX_PWRREG(0x200)
31#define S5PC100_RST_STAT S5PC1XX_PWRREG(0x300)
32#define S5PC100_WAKEUP_STAT S5PC1XX_PWRREG(0x304)
33#define S5PC100_BLK_PWR_STAT S5PC1XX_PWRREG(0x308)
34#define S5PC100_INFORM0 S5PC1XX_PWRREG(0x400)
35#define S5PC100_INFORM1 S5PC1XX_PWRREG(0x404)
36#define S5PC100_INFORM2 S5PC1XX_PWRREG(0x408)
37#define S5PC100_INFORM3 S5PC1XX_PWRREG(0x40C)
38#define S5PC100_INFORM4 S5PC1XX_PWRREG(0x410)
39#define S5PC100_INFORM5 S5PC1XX_PWRREG(0x414)
40#define S5PC100_INFORM6 S5PC1XX_PWRREG(0x418)
41#define S5PC100_INFORM7 S5PC1XX_PWRREG(0x41C)
42#define S5PC100_DCGIDX_MAP0 S5PC1XX_PWRREG(0x500)
43#define S5PC100_DCGIDX_MAP1 S5PC1XX_PWRREG(0x504)
44#define S5PC100_DCGIDX_MAP2 S5PC1XX_PWRREG(0x508)
45#define S5PC100_DCGPERF_MAP0 S5PC1XX_PWRREG(0x50C)
46#define S5PC100_DCGPERF_MAP1 S5PC1XX_PWRREG(0x510)
47#define S5PC100_DVCIDX_MAP S5PC1XX_PWRREG(0x514)
48#define S5PC100_FREQ_CPU S5PC1XX_PWRREG(0x518)
49#define S5PC100_FREQ_DPM S5PC1XX_PWRREG(0x51C)
50#define S5PC100_DVSEMCLK_EN S5PC1XX_PWRREG(0x520)
51#define S5PC100_APLL_CON_L8 S5PC1XX_PWRREG(0x600)
52#define S5PC100_APLL_CON_L7 S5PC1XX_PWRREG(0x604)
53#define S5PC100_APLL_CON_L6 S5PC1XX_PWRREG(0x608)
54#define S5PC100_APLL_CON_L5 S5PC1XX_PWRREG(0x60C)
55#define S5PC100_APLL_CON_L4 S5PC1XX_PWRREG(0x610)
56#define S5PC100_APLL_CON_L3 S5PC1XX_PWRREG(0x614)
57#define S5PC100_APLL_CON_L2 S5PC1XX_PWRREG(0x618)
58#define S5PC100_APLL_CON_L1 S5PC1XX_PWRREG(0x61C)
59#define S5PC100_IEM_CONTROL S5PC1XX_PWRREG(0x620)
60#define S5PC100_CLKDIV_IEM_L8 S5PC1XX_PWRREG(0x700)
61#define S5PC100_CLKDIV_IEM_L7 S5PC1XX_PWRREG(0x704)
62#define S5PC100_CLKDIV_IEM_L6 S5PC1XX_PWRREG(0x708)
63#define S5PC100_CLKDIV_IEM_L5 S5PC1XX_PWRREG(0x70C)
64#define S5PC100_CLKDIV_IEM_L4 S5PC1XX_PWRREG(0x710)
65#define S5PC100_CLKDIV_IEM_L3 S5PC1XX_PWRREG(0x714)
66#define S5PC100_CLKDIV_IEM_L2 S5PC1XX_PWRREG(0x718)
67#define S5PC100_CLKDIV_IEM_L1 S5PC1XX_PWRREG(0x71C)
68#define S5PC100_IEM_HPMCLK_DIV S5PC1XX_PWRREG(0x724)
69
70/* PWR_CFG */
71#define S5PC100_PWRCFG_CFG_DEEP_IDLE (1 << 31)
72#define S5PC100_PWRCFG_CFG_WFI_MASK (3 << 5)
73#define S5PC100_PWRCFG_CFG_WFI_IDLE (0 << 5)
74#define S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE (1 << 5)
75#define S5PC100_PWRCFG_CFG_WFI_STOP (2 << 5)
76#define S5PC100_PWRCFG_CFG_WFI_SLEEP (3 << 5)
77
78/* SLEEP_CFG */
79#define S5PC100_SLEEP_OSC_EN_SLEEP (1 << 0)
80
81/* OTHERS */
82#define S5PC100_PMU_INT_DISABLE (1 << 24)
83
84#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
deleted file mode 100644
index 2531f34a56f3..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/* arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * Header file for s5pc100 cpu support
7 *
8 * Based on plat-s3c64xx/include/plat/s3c6400.h
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Common init code for S5PC100 related SoCs */
16extern int s5pc100_init(void);
17extern void s5pc100_map_io(void);
18extern void s5pc100_init_clocks(int xtal);
19extern int s5pc100_register_baseclocks(unsigned long xtal);
20extern void s5pc100_init_irq(void);
21extern void s5pc100_init_io(struct map_desc *mach_desc, int size);
22extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
23extern void s5pc100_register_clocks(void);
24extern void s5pc100_setup_clocks(void);
25extern struct sysdev_class s5pc100_sysclass;
26
27#define s5pc100_init_uarts s5pc100_common_init_uarts
28
29/* Some day, belows will be moved to plat-s5pc/include/plat/cpu.h */
30extern void s5pc1xx_init_irq(u32 *vic_valid, int num);
31extern void s5pc1xx_init_io(struct map_desc *mach_desc, int size);
32
33/* Some day, belows will be moved to plat-s5pc/include/plat/clock.h */
34extern struct clk clk_hpll;
35extern struct clk clk_hd0;
36extern struct clk clk_pd0;
37extern struct clk clk_54m;
38extern void s5pc1xx_register_clocks(void);
39extern int s5pc100_sclk0_ctrl(struct clk *clk, int enable);
40extern int s5pc100_sclk1_ctrl(struct clk *clk, int enable);
41
42/* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */
43extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
44extern struct platform_device s3c_device_g2d;
45extern struct platform_device s3c_device_g3d;
46extern struct platform_device s3c_device_vpp;
47extern struct platform_device s3c_device_tvenc;
48extern struct platform_device s3c_device_tvscaler;
49extern struct platform_device s3c_device_rotator;
50extern struct platform_device s3c_device_jpeg;
51extern struct platform_device s3c_device_onenand;
52extern struct platform_device s3c_device_usb_otghcd;
53extern struct platform_device s3c_device_keypad;
54extern struct platform_device s3c_device_ts;
55extern struct platform_device s3c_device_g3d;
56extern struct platform_device s3c_device_smc911x;
57extern struct platform_device s3c_device_fimc0;
58extern struct platform_device s3c_device_fimc1;
59extern struct platform_device s3c_device_mfc;
60extern struct platform_device s3c_device_ac97;
61extern struct platform_device s3c_device_fimc0;
62extern struct platform_device s3c_device_fimc1;
63extern struct platform_device s3c_device_fimc2;
64
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 03:15:18 -0500