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authorKukjin Kim <kgene.kim@samsung.com>2010-10-04 21:49:38 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-10-25 03:03:05 -0400
commitdd56d2df56485553f4777f68e0ead87fbb02f706 (patch)
tree96a1f740d97f12ceaaabed1e56aedbd7f737465b /arch/arm/plat-s5p
parent3b7998f529a18696baafb8cca63a7720565ad77f (diff)
ARM: S5P: Cleanup the S5P SoCs' VA address mapping
Basically S5P SoCs use the Samsung common VA address mapping where plat-samsung and use plat-s5p's mapping also. The later is a little mess. So this patch cleans it up. Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-s5p')
-rw-r--r--arch/arm/plat-s5p/include/plat/map-s5p.h40
1 files changed, 21 insertions, 19 deletions
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index c833f3f21816..ec96a193f5e1 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -13,27 +13,35 @@
13#ifndef __ASM_PLAT_MAP_S5P_H 13#ifndef __ASM_PLAT_MAP_S5P_H
14#define __ASM_PLAT_MAP_S5P_H __FILE__ 14#define __ASM_PLAT_MAP_S5P_H __FILE__
15 15
16#define S5P_VA_CHIPID S3C_ADDR(0x00700000) 16#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
17#define S5P_VA_GPIO S3C_ADDR(0x00500000) 17#define S5P_VA_CMU S3C_ADDR(0x02100000)
18#define S5P_VA_SYSTIMER S3C_ADDR(0x01200000) 18#define S5P_VA_GPIO S3C_ADDR(0x02200000)
19#define S5P_VA_SROMC S3C_ADDR(0x01100000) 19
20#define S5P_VA_SYSRAM S3C_ADDR(0x01180000) 20#define S5P_VA_SYSRAM S3C_ADDR(0x02400000)
21#define S3C_VA_USB_HSPHY S3C_ADDR(0x02000000) 21#define S5P_VA_DMC0 S3C_ADDR(0x02440000)
22#define S5P_VA_DMC0 S3C_ADDR(0x00A00000) 22#define S5P_VA_DMC1 S3C_ADDR(0x02480000)
23#define S5P_VA_DMC1 S3C_ADDR(0x00A80000) 23#define S5P_VA_SROMC S3C_ADDR(0x024C0000)
24 24
25#define S5P_VA_COMBINER_BASE S3C_ADDR(0x00600000) 25#define S5P_VA_SYSTIMER S3C_ADDR(0x02500000)
26#define S5P_VA_L2CC S3C_ADDR(0x02600000)
27
28#define S5P_VA_COMBINER_BASE S3C_ADDR(0x02700000)
26#define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10) 29#define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)
27 30
28#define S5P_VA_COREPERI_BASE S3C_ADDR(0x00800000) 31#define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000)
29#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x)) 32#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x))
30#define S5P_VA_SCU S5P_VA_COREPERI(0x0) 33#define S5P_VA_SCU S5P_VA_COREPERI(0x0)
31#define S5P_VA_GIC_CPU S5P_VA_COREPERI(0x100) 34#define S5P_VA_GIC_CPU S5P_VA_COREPERI(0x100)
32#define S5P_VA_TWD S5P_VA_COREPERI(0x600) 35#define S5P_VA_TWD S5P_VA_COREPERI(0x600)
33#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000) 36#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000)
34 37
35#define S5P_VA_L2CC S3C_ADDR(0x00900000) 38#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000)
36#define S5P_VA_CMU S3C_ADDR(0x00920000) 39
40#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
41#define VA_VIC0 VA_VIC(0)
42#define VA_VIC1 VA_VIC(1)
43#define VA_VIC2 VA_VIC(2)
44#define VA_VIC3 VA_VIC(3)
37 45
38#define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 46#define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
39#define S5P_VA_UART0 S5P_VA_UART(0) 47#define S5P_VA_UART0 S5P_VA_UART(0)
@@ -45,10 +53,4 @@
45#define S3C_UART_OFFSET (0x400) 53#define S3C_UART_OFFSET (0x400)
46#endif 54#endif
47 55
48#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
49#define VA_VIC0 VA_VIC(0)
50#define VA_VIC1 VA_VIC(1)
51#define VA_VIC2 VA_VIC(2)
52#define VA_VIC3 VA_VIC(3)
53
54#endif /* __ASM_PLAT_MAP_S5P_H */ 56#endif /* __ASM_PLAT_MAP_S5P_H */