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authorKukjin Kim <kgene.kim@samsung.com>2010-09-01 02:35:30 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-10-18 05:33:02 -0400
commit3109e55099cb013f9e1b63d39606dc5d7ecf25bd (patch)
tree46fc9d0af9f08df90b079f953b4c0015e7f6134a /arch/arm/plat-s5p
parenta2e0d6249fa866ce7f5a8fe08a4d75511e4701c6 (diff)
ARM: S5P64X0: Update Clock for S5P6440 and S5P6450
This patch updates regarding clock files for supporting S5P6440 and S5P6450 with one kernel image. The mach-s5p64x0/clock.c is for common of them and there are specific clock files for each SoCs. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-s5p')
-rw-r--r--arch/arm/plat-s5p/clock.c19
-rw-r--r--arch/arm/plat-s5p/include/plat/pll.h7
-rw-r--r--arch/arm/plat-s5p/include/plat/s5p-clock.h8
3 files changed, 31 insertions, 3 deletions
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index b5e255265f20..8aaf4e6b60c3 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -74,6 +74,13 @@ struct clk clk_fout_epll = {
74 .ctrlbit = (1 << 31), 74 .ctrlbit = (1 << 31),
75}; 75};
76 76
77/* DPLL clock output */
78struct clk clk_fout_dpll = {
79 .name = "fout_dpll",
80 .id = -1,
81 .ctrlbit = (1 << 31),
82};
83
77/* VPLL clock output */ 84/* VPLL clock output */
78struct clk clk_fout_vpll = { 85struct clk clk_fout_vpll = {
79 .name = "fout_vpll", 86 .name = "fout_vpll",
@@ -122,6 +129,17 @@ struct clksrc_sources clk_src_epll = {
122 .nr_sources = ARRAY_SIZE(clk_src_epll_list), 129 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
123}; 130};
124 131
132/* Possible clock sources for DPLL Mux */
133static struct clk *clk_src_dpll_list[] = {
134 [0] = &clk_fin_dpll,
135 [1] = &clk_fout_dpll,
136};
137
138struct clksrc_sources clk_src_dpll = {
139 .sources = clk_src_dpll_list,
140 .nr_sources = ARRAY_SIZE(clk_src_dpll_list),
141};
142
125struct clk clk_vpll = { 143struct clk clk_vpll = {
126 .name = "vpll", 144 .name = "vpll",
127 .id = -1, 145 .id = -1,
@@ -145,6 +163,7 @@ static struct clk *s5p_clks[] __initdata = {
145 &clk_fout_apll, 163 &clk_fout_apll,
146 &clk_fout_mpll, 164 &clk_fout_mpll,
147 &clk_fout_epll, 165 &clk_fout_epll,
166 &clk_fout_dpll,
148 &clk_fout_vpll, 167 &clk_fout_vpll,
149 &clk_arm, 168 &clk_arm,
150 &clk_vpll, 169 &clk_vpll,
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
index 4e8fe08cb70d..bf28fadee7ae 100644
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -47,6 +47,7 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
47} 47}
48 48
49#define PLL46XX_KDIV_MASK (0xFFFF) 49#define PLL46XX_KDIV_MASK (0xFFFF)
50#define PLL4650C_KDIV_MASK (0xFFF)
50#define PLL46XX_MDIV_MASK (0x1FF) 51#define PLL46XX_MDIV_MASK (0x1FF)
51#define PLL46XX_PDIV_MASK (0x3F) 52#define PLL46XX_PDIV_MASK (0x3F)
52#define PLL46XX_SDIV_MASK (0x7) 53#define PLL46XX_SDIV_MASK (0x7)
@@ -57,6 +58,7 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
57enum pll46xx_type_t { 58enum pll46xx_type_t {
58 pll_4600, 59 pll_4600,
59 pll_4650, 60 pll_4650,
61 pll_4650c,
60}; 62};
61 63
62static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, 64static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
@@ -72,6 +74,11 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
72 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; 74 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
73 kdiv = pll_con1 & PLL46XX_KDIV_MASK; 75 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
74 76
77 if (pll_type == pll_4650c)
78 kdiv = pll_con1 & PLL4650C_KDIV_MASK;
79 else
80 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
81
75 tmp = baseclk; 82 tmp = baseclk;
76 83
77 if (pll_type == pll_4600) { 84 if (pll_type == pll_4600) {
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h
index 09418b1101fe..17036c898409 100644
--- a/arch/arm/plat-s5p/include/plat/s5p-clock.h
+++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h
@@ -1,7 +1,7 @@
1/* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h 1/* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h
2 * 2 *
3 * Copyright 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Header file for s5p clock support 6 * Header file for s5p clock support
7 * 7 *
@@ -20,6 +20,7 @@
20#define clk_fin_apll clk_ext_xtal_mux 20#define clk_fin_apll clk_ext_xtal_mux
21#define clk_fin_mpll clk_ext_xtal_mux 21#define clk_fin_mpll clk_ext_xtal_mux
22#define clk_fin_epll clk_ext_xtal_mux 22#define clk_fin_epll clk_ext_xtal_mux
23#define clk_fin_dpll clk_ext_xtal_mux
23#define clk_fin_vpll clk_ext_xtal_mux 24#define clk_fin_vpll clk_ext_xtal_mux
24#define clk_fin_hpll clk_ext_xtal_mux 25#define clk_fin_hpll clk_ext_xtal_mux
25 26
@@ -30,6 +31,7 @@ extern struct clk s5p_clk_27m;
30extern struct clk clk_fout_apll; 31extern struct clk clk_fout_apll;
31extern struct clk clk_fout_mpll; 32extern struct clk clk_fout_mpll;
32extern struct clk clk_fout_epll; 33extern struct clk clk_fout_epll;
34extern struct clk clk_fout_dpll;
33extern struct clk clk_fout_vpll; 35extern struct clk clk_fout_vpll;
34extern struct clk clk_arm; 36extern struct clk clk_arm;
35extern struct clk clk_vpll; 37extern struct clk clk_vpll;
@@ -37,8 +39,8 @@ extern struct clk clk_vpll;
37extern struct clksrc_sources clk_src_apll; 39extern struct clksrc_sources clk_src_apll;
38extern struct clksrc_sources clk_src_mpll; 40extern struct clksrc_sources clk_src_mpll;
39extern struct clksrc_sources clk_src_epll; 41extern struct clksrc_sources clk_src_epll;
42extern struct clksrc_sources clk_src_dpll;
40 43
41extern int s5p6440_clk48m_ctrl(struct clk *clk, int enable);
42extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable); 44extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
43 45
44#endif /* __ASM_PLAT_S5P_CLOCK_H */ 46#endif /* __ASM_PLAT_S5P_CLOCK_H */