diff options
author | Changhwan Youn <chaos.youn@samsung.com> | 2010-07-27 04:52:39 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-08-05 05:32:41 -0400 |
commit | c8bef14051b261f86278fad84ccc23c891242d25 (patch) | |
tree | 196e3abd37764ef4521c0a54853a107a317b15b0 /arch/arm/plat-s5p | |
parent | 2b12b5c4ff9e0f1c5f4e5d5bde57b919fe522df2 (diff) |
ARM: S5PV310: Add Clock and PLL support
This patch adds clock and pll support for S5PV310.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-s5p')
-rw-r--r-- | arch/arm/plat-s5p/include/plat/pll.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h index 7db322726bc2..4e8fe08cb70d 100644 --- a/arch/arm/plat-s5p/include/plat/pll.h +++ b/arch/arm/plat-s5p/include/plat/pll.h | |||
@@ -46,6 +46,47 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con, | |||
46 | return (unsigned long)fvco; | 46 | return (unsigned long)fvco; |
47 | } | 47 | } |
48 | 48 | ||
49 | #define PLL46XX_KDIV_MASK (0xFFFF) | ||
50 | #define PLL46XX_MDIV_MASK (0x1FF) | ||
51 | #define PLL46XX_PDIV_MASK (0x3F) | ||
52 | #define PLL46XX_SDIV_MASK (0x7) | ||
53 | #define PLL46XX_MDIV_SHIFT (16) | ||
54 | #define PLL46XX_PDIV_SHIFT (8) | ||
55 | #define PLL46XX_SDIV_SHIFT (0) | ||
56 | |||
57 | enum pll46xx_type_t { | ||
58 | pll_4600, | ||
59 | pll_4650, | ||
60 | }; | ||
61 | |||
62 | static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, | ||
63 | u32 pll_con0, u32 pll_con1, | ||
64 | enum pll46xx_type_t pll_type) | ||
65 | { | ||
66 | unsigned long result; | ||
67 | u32 mdiv, pdiv, sdiv, kdiv; | ||
68 | u64 tmp; | ||
69 | |||
70 | mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; | ||
71 | pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; | ||
72 | sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; | ||
73 | kdiv = pll_con1 & PLL46XX_KDIV_MASK; | ||
74 | |||
75 | tmp = baseclk; | ||
76 | |||
77 | if (pll_type == pll_4600) { | ||
78 | tmp *= (mdiv << 16) + kdiv; | ||
79 | do_div(tmp, (pdiv << sdiv)); | ||
80 | result = tmp >> 16; | ||
81 | } else { | ||
82 | tmp *= (mdiv << 10) + kdiv; | ||
83 | do_div(tmp, (pdiv << sdiv)); | ||
84 | result = tmp >> 10; | ||
85 | } | ||
86 | |||
87 | return result; | ||
88 | } | ||
89 | |||
49 | #define PLL90XX_MDIV_MASK (0xFF) | 90 | #define PLL90XX_MDIV_MASK (0xFF) |
50 | #define PLL90XX_PDIV_MASK (0x3F) | 91 | #define PLL90XX_PDIV_MASK (0x3F) |
51 | #define PLL90XX_SDIV_MASK (0x7) | 92 | #define PLL90XX_SDIV_MASK (0x7) |