Merge branch 'next/board' of git://git.linaro.org/people/arnd/arm-soc

* 'next/board' of git://git.linaro.org/people/arnd/arm-soc: (34 commits)
  ep93xx: add support Vision EP9307 SoM
  ARM: mxs: Add initial support for DENX MX28
  ARM: EXYNOS4: Add support SMDK4412 Board
  ARM: EXYNOS4: Add MCT support for EXYNOS4412
  ARM: EXYNOS4: Add functions for gic interrupt handling
  ARM: EXYNOS4: Add support clock for EXYNOS4412
  ARM: EXYNOS4: Add support new EXYNOS4412 SoC
  ARM: EXYNOS4: Add support MCT PPI for EXYNOS4212
  ARM: EXYNOS4: Add support PPI in external GIC
  ARM: EXYNOS4: convert boot_params to atag_offset
  ixp4xx: support omicron ixp425 based boards
  ARM: EXYNOS4: Add support SMDK4212 Board
  ARM: EXYNOS4: Add support PM for EXYNOS4212
  ARM: EXYNOS4: Add support clock for EXYNOS4212
  ARM: EXYNOS4: Add support new EXYNOS4212 SoC
  at91: USB-A9G20 C01 & C11 board support
  at91: merge board USB-A9260 and USB-A9263 together
  at91: add support for RSIs EWS board
  ARM: SAMSUNG: Fix mask value for S5P64X0 CPU IDs
  ARM: SAMSUNG: Fix mask for S3C64xx CPU IDs
  ...

3 files changed, 88 insertions, 18 deletions

diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index bbc2aa7449ca..7b0a28f73a68 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -33,48 +33,66 @@ static const char name_s5p6450[] = "S5P6450";
 static const char name_s5pc100[] = "S5PC100";
 static const char name_s5pv210[] = "S5PV210/S5PC110";
 static const char name_exynos4210[] = "EXYNOS4210";
+static const char name_exynos4212[] = "EXYNOS4212";
+static const char name_exynos4412[] = "EXYNOS4412";
 
 static struct cpu_table cpu_ids[] __initdata = {
         {
-                .idcode         = 0x56440100,
-                .idmask         = 0xfffff000,
+                .idcode         = S5P6440_CPU_ID,
+                .idmask         = S5P64XX_CPU_MASK,
                 .map_io         = s5p6440_map_io,
                 .init_clocks    = s5p6440_init_clocks,
                 .init_uarts     = s5p6440_init_uarts,
                 .init           = s5p64x0_init,
                 .name           = name_s5p6440,
         }, {
-                .idcode         = 0x36450000,
-                .idmask         = 0xfffff000,
+                .idcode         = S5P6450_CPU_ID,
+                .idmask         = S5P64XX_CPU_MASK,
                 .map_io         = s5p6450_map_io,
                 .init_clocks    = s5p6450_init_clocks,
                 .init_uarts     = s5p6450_init_uarts,
                 .init           = s5p64x0_init,
                 .name           = name_s5p6450,
         }, {
-                .idcode         = 0x43100000,
-                .idmask         = 0xfffff000,
+                .idcode         = S5PC100_CPU_ID,
+                .idmask         = S5PC100_CPU_MASK,
                 .map_io         = s5pc100_map_io,
                 .init_clocks    = s5pc100_init_clocks,
                 .init_uarts     = s5pc100_init_uarts,
                 .init           = s5pc100_init,
                 .name           = name_s5pc100,
         }, {
-                .idcode         = 0x43110000,
-                .idmask         = 0xfffff000,
+                .idcode         = S5PV210_CPU_ID,
+                .idmask         = S5PV210_CPU_MASK,
                 .map_io         = s5pv210_map_io,
                 .init_clocks    = s5pv210_init_clocks,
                 .init_uarts     = s5pv210_init_uarts,
                 .init           = s5pv210_init,
                 .name           = name_s5pv210,
         }, {
-                .idcode         = 0x43210000,
-                .idmask         = 0xfffe0000,
+                .idcode         = EXYNOS4210_CPU_ID,
+                .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
                 .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos4_init,
                 .name           = name_exynos4210,
+        }, {
+                .idcode         = EXYNOS4212_CPU_ID,
+                .idmask         = EXYNOS4_CPU_MASK,
+                .map_io         = exynos4_map_io,
+                .init_clocks    = exynos4_init_clocks,
+                .init_uarts     = exynos4_init_uarts,
+                .init           = exynos4_init,
+                .name           = name_exynos4212,
+        }, {
+                .idcode         = EXYNOS4412_CPU_ID,
+                .idmask         = EXYNOS4_CPU_MASK,
+                .map_io         = exynos4_map_io,
+                .init_clocks    = exynos4_init_clocks,
+                .init_uarts     = exynos4_init_uarts,
+                .init           = exynos4_init,
+                .name           = name_exynos4412,
         },
 };
 
@@ -114,13 +132,13 @@ static struct map_desc s5p_iodesc[] __initdata = {
 void __init s5p_init_io(struct map_desc *mach_desc,
                         int size, void __iomem *cpuid_addr)
 {
-        unsigned long idcode;
-
         /* initialize the io descriptors we need for initialization */
         iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc));
         if (mach_desc)
                 iotable_init(mach_desc, size);
 
-        idcode = __raw_readl(cpuid_addr);
-        s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
+        /* detect cpu id and rev. */
+        s5p_init_cpu(cpuid_addr);
+
+        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h
index 907caab53dcf..f680a143e38c 100644
--- a/arch/arm/plat-s5p/include/plat/exynos4.h
+++ b/arch/arm/plat-s5p/include/plat/exynos4.h
@@ -14,10 +14,11 @@
 
 extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void exynos4_register_clocks(void);
+extern void exynos4210_register_clocks(void);
+extern void exynos4212_register_clocks(void);
 extern void exynos4_setup_clocks(void);
 
-#ifdef CONFIG_CPU_EXYNOS4210
-
+#ifdef CONFIG_ARCH_EXYNOS4
 extern  int exynos4_init(void);
 extern void exynos4_init_irq(void);
 extern void exynos4_map_io(void);
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
index ebc142c5c84c..3e21b9444cc5 100644
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -12,6 +12,59 @@
  * published by the Free Software Foundation.
 */
 
+#include <asm/div64.h>
+
+#define PLL35XX_MDIV_MASK       (0x3FF)
+#define PLL35XX_PDIV_MASK       (0x3F)
+#define PLL35XX_SDIV_MASK       (0x7)
+#define PLL35XX_MDIV_SHIFT      (16)
+#define PLL35XX_PDIV_SHIFT      (8)
+#define PLL35XX_SDIV_SHIFT      (0)
+
+static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con)
+{
+        u32 mdiv, pdiv, sdiv;
+        u64 fvco = baseclk;
+
+        mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+        pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
+        sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
+
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+
+        return (unsigned long)fvco;
+}
+
+#define PLL36XX_KDIV_MASK       (0xFFFF)
+#define PLL36XX_MDIV_MASK       (0x1FF)
+#define PLL36XX_PDIV_MASK       (0x3F)
+#define PLL36XX_SDIV_MASK       (0x7)
+#define PLL36XX_MDIV_SHIFT      (16)
+#define PLL36XX_PDIV_SHIFT      (8)
+#define PLL36XX_SDIV_SHIFT      (0)
+
+static inline unsigned long s5p_get_pll36xx(unsigned long baseclk,
+                                            u32 pll_con0, u32 pll_con1)
+{
+        unsigned long result;
+        u32 mdiv, pdiv, sdiv, kdiv;
+        u64 tmp;
+
+        mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
+        pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
+        sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
+        kdiv = pll_con1 & PLL36XX_KDIV_MASK;
+
+        tmp = baseclk;
+
+        tmp *= (mdiv << 16) + kdiv;
+        do_div(tmp, (pdiv << sdiv));
+        result = tmp >> 16;
+
+        return result;
+}
+
 #define PLL45XX_MDIV_MASK       (0x3FF)
 #define PLL45XX_PDIV_MASK       (0x3F)
 #define PLL45XX_SDIV_MASK       (0x7)
@@ -19,8 +72,6 @@
 #define PLL45XX_PDIV_SHIFT      (8)
 #define PLL45XX_SDIV_SHIFT      (0)
 
-#include <asm/div64.h>
-
 enum pll45xx_type_t {
         pll_4500,
         pll_4502,