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authorThomas Gleixner <tglx@linutronix.de>2011-03-24 08:25:22 -0400
committerThomas Gleixner <tglx@linutronix.de>2011-03-29 08:47:57 -0400
commit6845664a6a7d443f03883db59d10749d38d98b8e (patch)
tree4b4499f4d41f24152190220d93ea186fbf991fca /arch/arm/plat-s5p
parent25a5662a13e604d86b0a9fd71703582a7393d8ec (diff)
arm: Cleanup the irq namespace
Convert to the new function names. Automated with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/plat-s5p')
-rw-r--r--arch/arm/plat-s5p/irq-eint.c8
-rw-r--r--arch/arm/plat-s5p/irq-gpioint.c22
2 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
index 225aa25405db..f3d15e8c02c1 100644
--- a/arch/arm/plat-s5p/irq-eint.c
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -205,15 +205,15 @@ int __init s5p_init_irq_eint(void)
205 int irq; 205 int irq;
206 206
207 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) 207 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
208 set_irq_chip(irq, &s5p_irq_vic_eint); 208 irq_set_chip(irq, &s5p_irq_vic_eint);
209 209
210 for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { 210 for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
211 set_irq_chip(irq, &s5p_irq_eint); 211 irq_set_chip(irq, &s5p_irq_eint);
212 set_irq_handler(irq, handle_level_irq); 212 irq_set_handler(irq, handle_level_irq);
213 set_irq_flags(irq, IRQF_VALID); 213 set_irq_flags(irq, IRQF_VALID);
214 } 214 }
215 215
216 set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); 216 irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
217 return 0; 217 return 0;
218} 218}
219 219
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index cd87d3256e03..46dd078147d8 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -43,13 +43,13 @@ LIST_HEAD(banks);
43 43
44static int s5p_gpioint_get_offset(struct irq_data *data) 44static int s5p_gpioint_get_offset(struct irq_data *data)
45{ 45{
46 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); 46 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
47 return data->irq - chip->irq_base; 47 return data->irq - chip->irq_base;
48} 48}
49 49
50static void s5p_gpioint_ack(struct irq_data *data) 50static void s5p_gpioint_ack(struct irq_data *data)
51{ 51{
52 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); 52 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
53 int group, offset, pend_offset; 53 int group, offset, pend_offset;
54 unsigned int value; 54 unsigned int value;
55 55
@@ -64,7 +64,7 @@ static void s5p_gpioint_ack(struct irq_data *data)
64 64
65static void s5p_gpioint_mask(struct irq_data *data) 65static void s5p_gpioint_mask(struct irq_data *data)
66{ 66{
67 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); 67 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
68 int group, offset, mask_offset; 68 int group, offset, mask_offset;
69 unsigned int value; 69 unsigned int value;
70 70
@@ -79,7 +79,7 @@ static void s5p_gpioint_mask(struct irq_data *data)
79 79
80static void s5p_gpioint_unmask(struct irq_data *data) 80static void s5p_gpioint_unmask(struct irq_data *data)
81{ 81{
82 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); 82 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
83 int group, offset, mask_offset; 83 int group, offset, mask_offset;
84 unsigned int value; 84 unsigned int value;
85 85
@@ -100,7 +100,7 @@ static void s5p_gpioint_mask_ack(struct irq_data *data)
100 100
101static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type) 101static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
102{ 102{
103 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); 103 struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
104 int group, offset, con_offset; 104 int group, offset, con_offset;
105 unsigned int value; 105 unsigned int value;
106 106
@@ -149,7 +149,7 @@ static struct irq_chip s5p_gpioint = {
149 149
150static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) 150static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
151{ 151{
152 struct s5p_gpioint_bank *bank = get_irq_data(irq); 152 struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
153 int group, pend_offset, mask_offset; 153 int group, pend_offset, mask_offset;
154 unsigned int pend, mask; 154 unsigned int pend, mask;
155 155
@@ -200,8 +200,8 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
200 if (!bank->chips) 200 if (!bank->chips)
201 return -ENOMEM; 201 return -ENOMEM;
202 202
203 set_irq_chained_handler(bank->irq, s5p_gpioint_handler); 203 irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
204 set_irq_data(bank->irq, bank); 204 irq_set_handler_data(bank->irq, bank);
205 bank->handler = s5p_gpioint_handler; 205 bank->handler = s5p_gpioint_handler;
206 printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n", 206 printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
207 bank->irq); 207 bank->irq);
@@ -219,9 +219,9 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
219 bank->chips[group - bank->start] = chip; 219 bank->chips[group - bank->start] = chip;
220 for (i = 0; i < chip->chip.ngpio; i++) { 220 for (i = 0; i < chip->chip.ngpio; i++) {
221 irq = chip->irq_base + i; 221 irq = chip->irq_base + i;
222 set_irq_chip(irq, &s5p_gpioint); 222 irq_set_chip(irq, &s5p_gpioint);
223 set_irq_data(irq, chip); 223 irq_set_handler_data(irq, chip);
224 set_irq_handler(irq, handle_level_irq); 224 irq_set_handler(irq, handle_level_irq);
225 set_irq_flags(irq, IRQF_VALID); 225 set_irq_flags(irq, IRQF_VALID);
226 } 226 }
227 return 0; 227 return 0;